Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release

16 files changed, 1306 insertions, 0 deletions

diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
new file mode 100644
index 000000000..55d9aed7c
--- /dev/null
+++ b/arch/mips/generic/Kconfig
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0
+if MIPS_GENERIC_KERNEL
+
+config LEGACY_BOARDS
+        bool
+        help
+          Select this from your board if the board must use a legacy, non-UHI,
+          boot protocol. This will cause the kernel to scan through the list of
+          supported machines calling their detect functions in turn if the
+          kernel is booted without being provided with an FDT via the UHI
+          boot protocol.
+
+config YAMON_DT_SHIM
+        bool
+        help
+          Select this from your board if the board uses the YAMON bootloader
+          and you wish to include code which helps translate various
+          YAMON-provided environment variables into a device tree properties.
+
+comment "Legacy (non-UHI/non-FIT) Boards"
+
+config LEGACY_BOARD_SEAD3
+        bool "Support MIPS SEAD-3 boards"
+        select LEGACY_BOARDS
+        select YAMON_DT_SHIM
+        help
+          Enable this to include support for booting on MIPS SEAD-3 FPGA-based
+          development boards, which boot using a legacy boot protocol.
+
+comment "MSCC Ocelot doesn't work with SEAD3 enabled"
+        depends on LEGACY_BOARD_SEAD3
+
+config LEGACY_BOARD_OCELOT
+        bool "Support MSCC Ocelot boards"
+        depends on LEGACY_BOARD_SEAD3=n
+        select LEGACY_BOARDS
+        select MSCC_OCELOT
+        select SYS_HAS_EARLY_PRINTK
+        select USE_GENERIC_EARLY_PRINTK_8250
+
+config MSCC_OCELOT
+        bool
+        select GPIOLIB
+        select MSCC_OCELOT_IRQ
+
+comment "FIT/UHI Boards"
+
+config FIT_IMAGE_FDT_BOSTON
+        bool "Include FDT for MIPS Boston boards"
+        help
+          Enable this to include the FDT for the MIPS Boston development board
+          from Imagination Technologies in the FIT kernel image. You should
+          enable this if you wish to boot on a MIPS Boston board, as it is
+          expected by the bootloader.
+
+config FIT_IMAGE_FDT_NI169445
+        bool "Include FDT for NI 169445"
+        help
+          Enable this to include the FDT for the 169445 platform from
+          National Instruments in the FIT kernel image.
+
+config FIT_IMAGE_FDT_XILFPGA
+        bool "Include FDT for Xilfpga"
+        help
+          Enable this to include the FDT for the MIPSfpga platform
+          from Imagination Technologies in the FIT kernel image.
+
+config FIT_IMAGE_FDT_OCELOT
+        bool "Include FDT for Microsemi Ocelot development platforms"
+        select MSCC_OCELOT
+        help
+          Enable this to include the FDT for the Ocelot development platforms
+          from Microsemi in the FIT kernel image.
+          This requires u-boot on the platform.
+
+config BOARD_INGENIC
+        bool "Support boards based on Ingenic SoCs"
+        select MACH_INGENIC_GENERIC
+        help
+          Enable support for boards based on Ingenic SoCs.
+
+config VIRT_BOARD_RANCHU
+        bool "Support Ranchu platform for Android emulator"
+        help
+          This enables support for the platform used by Android emulator.
+
+          Ranchu platform consists of a set of virtual devices. This platform
+          enables emulation of variety of virtual configurations while using
+          Android emulator. Android emulator is based on Qemu, and contains
+          the support for the same set of virtual devices.
+
+endif
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
new file mode 100644
index 000000000..e37a59bae
--- /dev/null
+++ b/arch/mips/generic/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2016 Imagination Technologies
+# Author: Paul Burton <paul.burton@mips.com>
+#
+
+obj-y += init.o
+obj-y += irq.o
+obj-y += proc.o
+
+obj-$(CONFIG_YAMON_DT_SHIM)             += yamon-dt.o
+obj-$(CONFIG_LEGACY_BOARD_SEAD3)        += board-sead3.o
+obj-$(CONFIG_LEGACY_BOARD_OCELOT)       += board-ocelot.o
+obj-$(CONFIG_MACH_INGENIC)                      += board-ingenic.o
+obj-$(CONFIG_VIRT_BOARD_RANCHU)         += board-ranchu.o
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
new file mode 100644
index 000000000..f8ef2f9d1
--- /dev/null
+++ b/arch/mips/generic/Platform
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2016 Imagination Technologies
+# Author: Paul Burton <paul.burton@mips.com>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation;  either version 2 of the  License, or (at your
+# option) any later version.
+#
+
+# Note: order matters, keep the asm/mach-generic include last.
+cflags-$(CONFIG_MACH_INGENIC_SOC)       += -I$(srctree)/arch/mips/include/asm/mach-ingenic
+cflags-$(CONFIG_MIPS_GENERIC)   += -I$(srctree)/arch/mips/include/asm/mach-generic
+
+load-$(CONFIG_MIPS_GENERIC)     += 0xffffffff80100000
+zload-$(CONFIG_MIPS_GENERIC)    += 0xffffffff81000000
+all-$(CONFIG_MIPS_GENERIC)      := vmlinux.gz.itb
+
+its-y                                   := vmlinux.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_BOSTON)      += board-boston.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_NI169445)    += board-ni169445.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_OCELOT)      += board-ocelot.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)     += board-xilfpga.its.S
diff --git a/arch/mips/generic/board-boston.its.S b/arch/mips/generic/board-boston.its.S
new file mode 100644
index 000000000..c45ad2759
--- /dev/null
+++ b/arch/mips/generic/board-boston.its.S
@@ -0,0 +1,22 @@
+/ {
+        images {
+                fdt-boston {
+                        description = "img,boston Device Tree";
+                        data = /incbin/("boot/dts/img/boston.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf-boston {
+                        description = "Boston Linux kernel";
+                        kernel = "kernel";
+                        fdt = "fdt-boston";
+                };
+        };
+};
diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c
new file mode 100644
index 000000000..0cec0bea1
--- /dev/null
+++ b/arch/mips/generic/board-ingenic.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Support for Ingenic SoCs
+ *
+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
+ * Copyright (C) 2020 Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/pm.h>
+#include <linux/sizes.h>
+#include <linux/suspend.h>
+#include <linux/types.h>
+
+#include <asm/bootinfo.h>
+#include <asm/machine.h>
+#include <asm/reboot.h>
+
+static __init char *ingenic_get_system_type(unsigned long machtype)
+{
+        switch (machtype) {
+        case MACH_INGENIC_X2000E:
+                return "X2000E";
+        case MACH_INGENIC_X2000:
+                return "X2000";
+        case MACH_INGENIC_X1830:
+                return "X1830";
+        case MACH_INGENIC_X1000E:
+                return "X1000E";
+        case MACH_INGENIC_X1000:
+                return "X1000";
+        case MACH_INGENIC_JZ4780:
+                return "JZ4780";
+        case MACH_INGENIC_JZ4775:
+                return "JZ4775";
+        case MACH_INGENIC_JZ4770:
+                return "JZ4770";
+        case MACH_INGENIC_JZ4725B:
+                return "JZ4725B";
+        default:
+                return "JZ4740";
+        }
+}
+
+static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data)
+{
+        /*
+         * Old devicetree files for the qi,lb60 board did not have a /memory
+         * node. Hardcode the memory info here.
+         */
+        if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") &&
+            fdt_path_offset(fdt, "/memory") < 0)
+                early_init_dt_add_memory_arch(0, SZ_32M);
+
+        mips_machtype = (unsigned long)match_data;
+        system_type = ingenic_get_system_type(mips_machtype);
+
+        return fdt;
+}
+
+static const struct of_device_id ingenic_of_match[] __initconst = {
+        { .compatible = "ingenic,jz4740", .data = (void *)MACH_INGENIC_JZ4740 },
+        { .compatible = "ingenic,jz4725b", .data = (void *)MACH_INGENIC_JZ4725B },
+        { .compatible = "ingenic,jz4770", .data = (void *)MACH_INGENIC_JZ4770 },
+        { .compatible = "ingenic,jz4775", .data = (void *)MACH_INGENIC_JZ4775 },
+        { .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
+        { .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
+        { .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
+        { .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
+        { .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
+        { .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
+        {}
+};
+
+MIPS_MACHINE(ingenic) = {
+        .matches = ingenic_of_match,
+        .fixup_fdt = ingenic_fixup_fdt,
+};
+
+static void ingenic_wait_instr(void)
+{
+        __asm__(".set push;\n"
+                ".set mips3;\n"
+                "wait;\n"
+                ".set pop;\n"
+        );
+}
+
+static void ingenic_halt(void)
+{
+        for (;;)
+                ingenic_wait_instr();
+}
+
+static int __maybe_unused ingenic_pm_enter(suspend_state_t state)
+{
+        ingenic_wait_instr();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = {
+        .valid = suspend_valid_only_mem,
+        .enter = ingenic_pm_enter,
+};
+
+static int __init ingenic_pm_init(void)
+{
+        if (boot_cpu_type() == CPU_XBURST) {
+                if (IS_ENABLED(CONFIG_PM_SLEEP))
+                        suspend_set_ops(&ingenic_pm_ops);
+                _machine_halt = ingenic_halt;
+        }
+
+        return 0;
+
+}
+late_initcall(ingenic_pm_init);
diff --git a/arch/mips/generic/board-ni169445.its.S b/arch/mips/generic/board-ni169445.its.S
new file mode 100644
index 000000000..0a2e8f7a8
--- /dev/null
+++ b/arch/mips/generic/board-ni169445.its.S
@@ -0,0 +1,22 @@
+/ {
+        images {
+                fdt-ni169445 {
+                        description = "NI 169445 device tree";
+                        data = /incbin/("boot/dts/ni/169445.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf-ni169445 {
+                        description = "NI 169445 Linux Kernel";
+                        kernel = "kernel";
+                        fdt = "fdt-ni169445";
+                };
+        };
+};
diff --git a/arch/mips/generic/board-ocelot.c b/arch/mips/generic/board-ocelot.c
new file mode 100644
index 000000000..c238e9519
--- /dev/null
+++ b/arch/mips/generic/board-ocelot.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi MIPS SoC support
+ *
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+#include <asm/machine.h>
+#include <asm/prom.h>
+
+#define DEVCPU_GCB_CHIP_REGS_CHIP_ID    0x71070000
+#define CHIP_ID_PART_ID                 GENMASK(27, 12)
+
+#define OCELOT_PART_ID                  (0x7514 << 12)
+
+#define UART_UART                       0x70100000
+
+static __init bool ocelot_detect(void)
+{
+        u32 rev;
+        int idx;
+
+        /* Look for the TLB entry set up by redboot before trying to use it */
+        write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
+        mtc0_tlbw_hazard();
+        tlb_probe();
+        tlb_probe_hazard();
+        idx = read_c0_index();
+        if (idx < 0)
+                return 0;
+
+        /* A TLB entry exists, lets assume its usable and check the CHIP ID */
+        rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
+
+        if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
+                return 0;
+
+        /* Copy command line from bootloader early for Initrd detection */
+        if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
+                unsigned int prom_argc = fw_arg0;
+                const char **prom_argv = (const char **)fw_arg1;
+
+                if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
+                        /* ignore all built-in args if any f/w args given */
+                        strcpy(arcs_cmdline, prom_argv[1]);
+        }
+
+        return 1;
+}
+
+static void __init ocelot_earlyprintk_init(void)
+{
+        void __iomem *uart_base;
+
+        uart_base = ioremap(UART_UART, 0x20);
+        setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
+}
+
+static void __init ocelot_late_init(void)
+{
+        ocelot_earlyprintk_init();
+}
+
+static __init const void *ocelot_fixup_fdt(const void *fdt,
+                                           const void *match_data)
+{
+        /* This has to be done so late because ioremap needs to work */
+        late_time_init = ocelot_late_init;
+
+        return fdt;
+}
+
+extern char __dtb_ocelot_pcb123_begin[];
+
+MIPS_MACHINE(ocelot) = {
+        .fdt = __dtb_ocelot_pcb123_begin,
+        .fixup_fdt = ocelot_fixup_fdt,
+        .detect = ocelot_detect,
+};
diff --git a/arch/mips/generic/board-ocelot.its.S b/arch/mips/generic/board-ocelot.its.S
new file mode 100644
index 000000000..8c7e3a1b6
--- /dev/null
+++ b/arch/mips/generic/board-ocelot.its.S
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/ {
+        images {
+                fdt-ocelot_pcb123 {
+                        description = "MSCC Ocelot PCB123 Device Tree";
+                        data = /incbin/("boot/dts/mscc/ocelot_pcb123.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+
+                fdt-ocelot_pcb120 {
+                        description = "MSCC Ocelot PCB120 Device Tree";
+                        data = /incbin/("boot/dts/mscc/ocelot_pcb120.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf-ocelot_pcb123 {
+                        description = "Ocelot Linux kernel";
+                        kernel = "kernel";
+                        fdt = "fdt-ocelot_pcb123";
+                };
+
+                conf-ocelot_pcb120 {
+                        description = "Ocelot Linux kernel";
+                        kernel = "kernel";
+                        fdt = "fdt-ocelot_pcb120";
+                };
+        };
+};
diff --git a/arch/mips/generic/board-ranchu.c b/arch/mips/generic/board-ranchu.c
new file mode 100644
index 000000000..a89aaad59
--- /dev/null
+++ b/arch/mips/generic/board-ranchu.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Support code for virtual Ranchu board for MIPS.
+ *
+ * Author: Miodrag Dinic <miodrag.dinic@mips.com>
+ */
+
+#include <linux/of_address.h>
+#include <linux/types.h>
+
+#include <asm/machine.h>
+#include <asm/mipsregs.h>
+#include <asm/time.h>
+
+#define GOLDFISH_TIMER_LOW              0x00
+#define GOLDFISH_TIMER_HIGH             0x04
+
+static __init u64 read_rtc_time(void __iomem *base)
+{
+        u32 time_low;
+        u32 time_high;
+
+        /*
+         * Reading the low address latches the high value
+         * as well so there is no fear that we may read
+         * inaccurate high value.
+         */
+        time_low = readl(base + GOLDFISH_TIMER_LOW);
+        time_high = readl(base + GOLDFISH_TIMER_HIGH);
+
+        return ((u64)time_high << 32) | time_low;
+}
+
+static __init unsigned int ranchu_measure_hpt_freq(void)
+{
+        u64 rtc_start, rtc_current, rtc_delta;
+        unsigned int start, count;
+        struct device_node *np;
+        void __iomem *rtc_base;
+
+        np = of_find_compatible_node(NULL, NULL, "google,goldfish-rtc");
+        if (!np)
+                panic("%s(): Failed to find 'google,goldfish-rtc' dt node!",
+                      __func__);
+
+        rtc_base = of_iomap(np, 0);
+        if (!rtc_base)
+                panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
+
+        /*
+         * Poll the nanosecond resolution RTC for one
+         * second to calibrate the CPU frequency.
+         */
+        rtc_start = read_rtc_time(rtc_base);
+        start = read_c0_count();
+
+        do {
+                rtc_current = read_rtc_time(rtc_base);
+                rtc_delta = rtc_current - rtc_start;
+        } while (rtc_delta < NSEC_PER_SEC);
+
+        count = read_c0_count() - start;
+
+        /*
+         * Make sure the frequency will be a round number.
+         * Without this correction, the returned value may vary
+         * between subsequent emulation executions.
+         *
+         * TODO: Set this value using device tree.
+         */
+        count += 5000;
+        count -= count % 10000;
+
+        iounmap(rtc_base);
+
+        return count;
+}
+
+static const struct of_device_id ranchu_of_match[] __initconst = {
+        {
+                .compatible = "mti,ranchu",
+        },
+        {}
+};
+
+MIPS_MACHINE(ranchu) = {
+        .matches = ranchu_of_match,
+        .measure_hpt_freq = ranchu_measure_hpt_freq,
+};
diff --git a/arch/mips/generic/board-sead3.c b/arch/mips/generic/board-sead3.c
new file mode 100644
index 000000000..748ef4228
--- /dev/null
+++ b/arch/mips/generic/board-sead3.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#define pr_fmt(fmt) "sead3: " fmt
+
+#include <linux/errno.h>
+#include <linux/libfdt.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+#include <asm/fw/fw.h>
+#include <asm/io.h>
+#include <asm/machine.h>
+#include <asm/yamon-dt.h>
+
+#define SEAD_CONFIG                     CKSEG1ADDR(0x1b100110)
+#define SEAD_CONFIG_GIC_PRESENT         BIT(1)
+
+#define MIPS_REVISION                   CKSEG1ADDR(0x1fc00010)
+#define MIPS_REVISION_MACHINE           (0xf << 4)
+#define MIPS_REVISION_MACHINE_SEAD3     (0x4 << 4)
+
+/*
+ * Maximum 384MB RAM at physical address 0, preceding any I/O.
+ */
+static struct yamon_mem_region mem_regions[] __initdata = {
+        /* start        size */
+        { 0,            SZ_256M + SZ_128M },
+        {}
+};
+
+static __init bool sead3_detect(void)
+{
+        uint32_t rev;
+
+        rev = __raw_readl((void *)MIPS_REVISION);
+        return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
+}
+
+static __init int append_memory(void *fdt)
+{
+        return yamon_dt_append_memory(fdt, mem_regions);
+}
+
+static __init int remove_gic(void *fdt)
+{
+        const unsigned int cpu_ehci_int = 2;
+        const unsigned int cpu_uart_int = 4;
+        const unsigned int cpu_eth_int = 6;
+        int gic_off, cpu_off, uart_off, eth_off, ehci_off, err;
+        uint32_t cfg, cpu_phandle;
+
+        /* leave the GIC node intact if a GIC is present */
+        cfg = __raw_readl((uint32_t *)SEAD_CONFIG);
+        if (cfg & SEAD_CONFIG_GIC_PRESENT)
+                return 0;
+
+        gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
+        if (gic_off < 0) {
+                pr_err("unable to find DT GIC node: %d\n", gic_off);
+                return gic_off;
+        }
+
+        err = fdt_nop_node(fdt, gic_off);
+        if (err) {
+                pr_err("unable to nop GIC node\n");
+                return err;
+        }
+
+        cpu_off = fdt_node_offset_by_compatible(fdt, -1,
+                        "mti,cpu-interrupt-controller");
+        if (cpu_off < 0) {
+                pr_err("unable to find CPU intc node: %d\n", cpu_off);
+                return cpu_off;
+        }
+
+        cpu_phandle = fdt_get_phandle(fdt, cpu_off);
+        if (!cpu_phandle) {
+                pr_err("unable to get CPU intc phandle\n");
+                return -EINVAL;
+        }
+
+        uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
+        while (uart_off >= 0) {
+                err = fdt_setprop_u32(fdt, uart_off, "interrupt-parent",
+                                      cpu_phandle);
+                if (err) {
+                        pr_warn("unable to set UART interrupt-parent: %d\n",
+                                err);
+                        return err;
+                }
+
+                err = fdt_setprop_u32(fdt, uart_off, "interrupts",
+                                      cpu_uart_int);
+                if (err) {
+                        pr_err("unable to set UART interrupts property: %d\n",
+                               err);
+                        return err;
+                }
+
+                uart_off = fdt_node_offset_by_compatible(fdt, uart_off,
+                                                         "ns16550a");
+        }
+        if (uart_off != -FDT_ERR_NOTFOUND) {
+                pr_err("error searching for UART DT node: %d\n", uart_off);
+                return uart_off;
+        }
+
+        eth_off = fdt_node_offset_by_compatible(fdt, -1, "smsc,lan9115");
+        if (eth_off < 0) {
+                pr_err("unable to find ethernet DT node: %d\n", eth_off);
+                return eth_off;
+        }
+
+        err = fdt_setprop_u32(fdt, eth_off, "interrupt-parent", cpu_phandle);
+        if (err) {
+                pr_err("unable to set ethernet interrupt-parent: %d\n", err);
+                return err;
+        }
+
+        err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
+        if (err) {
+                pr_err("unable to set ethernet interrupts property: %d\n", err);
+                return err;
+        }
+
+        ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
+        if (ehci_off < 0) {
+                pr_err("unable to find EHCI DT node: %d\n", ehci_off);
+                return ehci_off;
+        }
+
+        err = fdt_setprop_u32(fdt, ehci_off, "interrupt-parent", cpu_phandle);
+        if (err) {
+                pr_err("unable to set EHCI interrupt-parent: %d\n", err);
+                return err;
+        }
+
+        err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
+        if (err) {
+                pr_err("unable to set EHCI interrupts property: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}
+
+static const struct mips_fdt_fixup sead3_fdt_fixups[] __initconst = {
+        { yamon_dt_append_cmdline, "append command line" },
+        { append_memory, "append memory" },
+        { remove_gic, "remove GIC when not present" },
+        { yamon_dt_serial_config, "append serial configuration" },
+        { },
+};
+
+static __init const void *sead3_fixup_fdt(const void *fdt,
+                                          const void *match_data)
+{
+        static unsigned char fdt_buf[16 << 10] __initdata;
+        int err;
+
+        if (fdt_check_header(fdt))
+                panic("Corrupt DT");
+
+        /* if this isn't SEAD3, something went wrong */
+        BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
+
+        fw_init_cmdline();
+
+        err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf),
+                                    fdt, sead3_fdt_fixups);
+        if (err)
+                panic("Unable to fixup FDT: %d", err);
+
+        return fdt_buf;
+}
+
+static __init unsigned int sead3_measure_hpt_freq(void)
+{
+        void __iomem *status_reg = (void __iomem *)0xbf000410;
+        unsigned int freq, orig, tick = 0;
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        orig = readl(status_reg) & 0x2;               /* get original sample */
+        /* wait for transition */
+        while ((readl(status_reg) & 0x2) == orig)
+                ;
+        orig = orig ^ 0x2;                            /* flip the bit */
+
+        write_c0_count(0);
+
+        /* wait 1 second (the sampling clock transitions every 10ms) */
+        while (tick < 100) {
+                /* wait for transition */
+                while ((readl(status_reg) & 0x2) == orig)
+                        ;
+                orig = orig ^ 0x2;                            /* flip the bit */
+                tick++;
+        }
+
+        freq = read_c0_count();
+
+        local_irq_restore(flags);
+
+        return freq;
+}
+
+extern char __dtb_sead3_begin[];
+
+MIPS_MACHINE(sead3) = {
+        .fdt = __dtb_sead3_begin,
+        .detect = sead3_detect,
+        .fixup_fdt = sead3_fixup_fdt,
+        .measure_hpt_freq = sead3_measure_hpt_freq,
+};
diff --git a/arch/mips/generic/board-xilfpga.its.S b/arch/mips/generic/board-xilfpga.its.S
new file mode 100644
index 000000000..08c1e900e
--- /dev/null
+++ b/arch/mips/generic/board-xilfpga.its.S
@@ -0,0 +1,22 @@
+/ {
+        images {
+                fdt-xilfpga {
+                        description = "MIPSfpga (xilfpga) Device Tree";
+                        data = /incbin/("boot/dts/xilfpga/nexys4ddr.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf-xilfpga {
+                        description = "MIPSfpga Linux kernel";
+                        kernel = "kernel";
+                        fdt = "fdt-xilfpga";
+                };
+        };
+};
diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c
new file mode 100644
index 000000000..66a19337d
--- /dev/null
+++ b/arch/mips/generic/init.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/of_clk.h>
+#include <linux/of_fdt.h>
+
+#include <asm/bootinfo.h>
+#include <asm/fw/fw.h>
+#include <asm/irq_cpu.h>
+#include <asm/machine.h>
+#include <asm/mips-cps.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+#include <asm/time.h>
+
+static __initconst const void *fdt;
+static __initconst const struct mips_machine *mach;
+static __initconst const void *mach_match_data;
+
+void __init prom_init(void)
+{
+        plat_get_fdt();
+        BUG_ON(!fdt);
+}
+
+void __init *plat_get_fdt(void)
+{
+        const struct mips_machine *check_mach;
+        const struct of_device_id *match;
+
+        if (fdt)
+                /* Already set up */
+                return (void *)fdt;
+
+        if (fw_passed_dtb && !fdt_check_header((void *)fw_passed_dtb)) {
+                /*
+                 * We have been provided with the appropriate device tree for
+                 * the board. Make use of it & search for any machine struct
+                 * based upon the root compatible string.
+                 */
+                fdt = (void *)fw_passed_dtb;
+
+                for_each_mips_machine(check_mach) {
+                        match = mips_machine_is_compatible(check_mach, fdt);
+                        if (match) {
+                                mach = check_mach;
+                                mach_match_data = match->data;
+                                break;
+                        }
+                }
+        } else if (IS_ENABLED(CONFIG_LEGACY_BOARDS)) {
+                /*
+                 * We weren't booted using the UHI boot protocol, but do
+                 * support some number of boards with legacy boot protocols.
+                 * Attempt to find the right one.
+                 */
+                for_each_mips_machine(check_mach) {
+                        if (!check_mach->detect)
+                                continue;
+
+                        if (!check_mach->detect())
+                                continue;
+
+                        mach = check_mach;
+                }
+
+                /*
+                 * If we don't recognise the machine then we can't continue, so
+                 * die here.
+                 */
+                BUG_ON(!mach);
+
+                /* Retrieve the machine's FDT */
+                fdt = mach->fdt;
+        }
+        return (void *)fdt;
+}
+
+#ifdef CONFIG_RELOCATABLE
+
+void __init plat_fdt_relocated(void *new_location)
+{
+        /*
+         * reset fdt as the cached value would point to the location
+         * before relocations happened and update the location argument
+         * if it was passed using UHI
+         */
+        fdt = NULL;
+
+        if (fw_arg0 == -2)
+                fw_arg1 = (unsigned long)new_location;
+}
+
+#endif /* CONFIG_RELOCATABLE */
+
+void __init plat_mem_setup(void)
+{
+        if (mach && mach->fixup_fdt)
+                fdt = mach->fixup_fdt(fdt, mach_match_data);
+
+        fw_init_cmdline();
+        __dt_setup_arch((void *)fdt);
+}
+
+void __init device_tree_init(void)
+{
+        int err;
+
+        unflatten_and_copy_device_tree();
+        mips_cpc_probe();
+
+        err = register_cps_smp_ops();
+        if (err)
+                err = register_up_smp_ops();
+}
+
+int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
+                                 const void *fdt_in,
+                                 const struct mips_fdt_fixup *fixups)
+{
+        int err;
+
+        err = fdt_open_into(fdt_in, fdt_out, fdt_out_size);
+        if (err) {
+                pr_err("Failed to open FDT\n");
+                return err;
+        }
+
+        for (; fixups->apply; fixups++) {
+                err = fixups->apply(fdt_out);
+                if (err) {
+                        pr_err("Failed to apply FDT fixup \"%s\"\n",
+                               fixups->description);
+                        return err;
+                }
+        }
+
+        err = fdt_pack(fdt_out);
+        if (err)
+                pr_err("Failed to pack FDT\n");
+        return err;
+}
+
+void __init plat_time_init(void)
+{
+        struct device_node *np;
+        struct clk *clk;
+
+        of_clk_init(NULL);
+
+        if (!cpu_has_counter) {
+                mips_hpt_frequency = 0;
+        } else if (mach && mach->measure_hpt_freq) {
+                mips_hpt_frequency = mach->measure_hpt_freq();
+        } else {
+                np = of_get_cpu_node(0, NULL);
+                if (!np) {
+                        pr_err("Failed to get CPU node\n");
+                        return;
+                }
+
+                clk = of_clk_get(np, 0);
+                if (IS_ERR(clk)) {
+                        pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
+                        return;
+                }
+
+                mips_hpt_frequency = clk_get_rate(clk);
+                clk_put(clk);
+
+                switch (boot_cpu_type()) {
+                case CPU_20KC:
+                case CPU_25KF:
+                        /* The counter runs at the CPU clock rate */
+                        break;
+                default:
+                        /* The counter runs at half the CPU clock rate */
+                        mips_hpt_frequency /= 2;
+                        break;
+                }
+        }
+
+        timer_probe();
+}
+
+void __init arch_init_irq(void)
+{
+        struct device_node *intc_node;
+
+        intc_node = of_find_compatible_node(NULL, NULL,
+                                            "mti,cpu-interrupt-controller");
+        if (!cpu_has_veic && !intc_node)
+                mips_cpu_irq_init();
+        of_node_put(intc_node);
+
+        irqchip_init();
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c
new file mode 100644
index 000000000..933119262
--- /dev/null
+++ b/arch/mips/generic/irq.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include <asm/irq.h>
+#include <asm/mips-cps.h>
+#include <asm/time.h>
+
+int get_c0_fdc_int(void)
+{
+        int mips_cpu_fdc_irq;
+
+        if (mips_gic_present())
+                mips_cpu_fdc_irq = gic_get_c0_fdc_int();
+        else if (cpu_has_veic)
+                panic("Unimplemented!");
+        else if (cp0_fdc_irq >= 0)
+                mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
+        else
+                mips_cpu_fdc_irq = -1;
+
+        return mips_cpu_fdc_irq;
+}
+
+int get_c0_perfcount_int(void)
+{
+        int mips_cpu_perf_irq;
+
+        if (mips_gic_present())
+                mips_cpu_perf_irq = gic_get_c0_perfcount_int();
+        else if (cpu_has_veic)
+                panic("Unimplemented!");
+        else if (cp0_perfcount_irq >= 0)
+                mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+        else
+                mips_cpu_perf_irq = -1;
+
+        return mips_cpu_perf_irq;
+}
+
+unsigned int get_c0_compare_int(void)
+{
+        int mips_cpu_timer_irq;
+
+        if (mips_gic_present())
+                mips_cpu_timer_irq = gic_get_c0_compare_int();
+        else if (cpu_has_veic)
+                panic("Unimplemented!");
+        else
+                mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+
+        return mips_cpu_timer_irq;
+}
diff --git a/arch/mips/generic/proc.c b/arch/mips/generic/proc.c
new file mode 100644
index 000000000..cce2fde21
--- /dev/null
+++ b/arch/mips/generic/proc.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#include <linux/of.h>
+
+#include <asm/bootinfo.h>
+
+char *system_type;
+
+const char *get_system_type(void)
+{
+        const char *str;
+        int err;
+
+        if (system_type)
+                return system_type;
+
+        err = of_property_read_string(of_root, "model", &str);
+        if (!err)
+                return str;
+
+        err = of_property_read_string_index(of_root, "compatible", 0, &str);
+        if (!err)
+                return str;
+
+        return "Unknown";
+}
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
new file mode 100644
index 000000000..3e2546765
--- /dev/null
+++ b/arch/mips/generic/vmlinux.its.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/dts-v1/;
+
+/ {
+        description = KERNEL_NAME;
+        #address-cells = <ADDR_CELLS>;
+
+        images {
+                kernel {
+                        description = KERNEL_NAME;
+                        data = /incbin/(VMLINUX_BINARY);
+                        type = "kernel";
+                        arch = "mips";
+                        os = "linux";
+                        compression = VMLINUX_COMPRESSION;
+                        load = /bits/ ADDR_BITS <VMLINUX_LOAD_ADDRESS>;
+                        entry = /bits/ ADDR_BITS <VMLINUX_ENTRY_ADDRESS>;
+                        hash {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                default = "conf-default";
+
+                conf-default {
+                        description = "Generic Linux kernel";
+                        kernel = "kernel";
+                };
+        };
+};
diff --git a/arch/mips/generic/yamon-dt.c b/arch/mips/generic/yamon-dt.c
new file mode 100644
index 000000000..a07a5edbc
--- /dev/null
+++ b/arch/mips/generic/yamon-dt.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#define pr_fmt(fmt) "yamon-dt: " fmt
+
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/libfdt.h>
+#include <linux/printk.h>
+
+#include <asm/fw/fw.h>
+#include <asm/yamon-dt.h>
+
+#define MAX_MEM_ARRAY_ENTRIES   2
+
+__init int yamon_dt_append_cmdline(void *fdt)
+{
+        int err, chosen_off;
+
+        /* find or add chosen node */
+        chosen_off = fdt_path_offset(fdt, "/chosen");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
+        if (chosen_off < 0) {
+                pr_err("Unable to find or add DT chosen node: %d\n",
+                       chosen_off);
+                return chosen_off;
+        }
+
+        err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
+        if (err) {
+                pr_err("Unable to set bootargs property: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}
+
+static unsigned int __init gen_fdt_mem_array(
+                                        const struct yamon_mem_region *regions,
+                                        __be32 *mem_array,
+                                        unsigned int max_entries,
+                                        unsigned long memsize)
+{
+        const struct yamon_mem_region *mr;
+        unsigned long size;
+        unsigned int entries = 0;
+
+        for (mr = regions; mr->size && memsize; ++mr) {
+                if (entries >= max_entries) {
+                        pr_warn("Number of regions exceeds max %u\n",
+                                max_entries);
+                        break;
+                }
+
+                /* How much of the remaining RAM fits in the next region? */
+                size = min_t(unsigned long, memsize, mr->size);
+                memsize -= size;
+
+                /* Emit a memory region */
+                *(mem_array++) = cpu_to_be32(mr->start);
+                *(mem_array++) = cpu_to_be32(size);
+                ++entries;
+
+                /* Discard the next mr->discard bytes */
+                memsize -= min_t(unsigned long, memsize, mr->discard);
+        }
+        return entries;
+}
+
+__init int yamon_dt_append_memory(void *fdt,
+                                  const struct yamon_mem_region *regions)
+{
+        unsigned long phys_memsize = 0, memsize;
+        __be32 mem_array[2 * MAX_MEM_ARRAY_ENTRIES];
+        unsigned int mem_entries;
+        int i, err, mem_off;
+        char *var, param_name[10], *var_names[] = {
+                "ememsize", "memsize",
+        };
+
+        /* find memory size from the bootloader environment */
+        for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+                var = fw_getenv(var_names[i]);
+                if (!var)
+                        continue;
+
+                err = kstrtoul(var, 0, &phys_memsize);
+                if (!err)
+                        break;
+
+                pr_warn("Failed to read the '%s' env variable '%s'\n",
+                        var_names[i], var);
+        }
+
+        if (!phys_memsize) {
+                pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
+                phys_memsize = 32 << 20;
+        }
+
+        /* default to using all available RAM */
+        memsize = phys_memsize;
+
+        /* allow the user to override the usable memory */
+        for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+                snprintf(param_name, sizeof(param_name), "%s=", var_names[i]);
+                var = strstr(arcs_cmdline, param_name);
+                if (!var)
+                        continue;
+
+                memsize = memparse(var + strlen(param_name), NULL);
+        }
+
+        /* if the user says there's more RAM than we thought, believe them */
+        phys_memsize = max_t(unsigned long, phys_memsize, memsize);
+
+        /* find or add a memory node */
+        mem_off = fdt_path_offset(fdt, "/memory");
+        if (mem_off == -FDT_ERR_NOTFOUND)
+                mem_off = fdt_add_subnode(fdt, 0, "memory");
+        if (mem_off < 0) {
+                pr_err("Unable to find or add memory DT node: %d\n", mem_off);
+                return mem_off;
+        }
+
+        err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
+        if (err) {
+                pr_err("Unable to set memory node device_type: %d\n", err);
+                return err;
+        }
+
+        mem_entries = gen_fdt_mem_array(regions, mem_array,
+                                        MAX_MEM_ARRAY_ENTRIES, phys_memsize);
+        err = fdt_setprop(fdt, mem_off, "reg",
+                          mem_array, mem_entries * 2 * sizeof(mem_array[0]));
+        if (err) {
+                pr_err("Unable to set memory regs property: %d\n", err);
+                return err;
+        }
+
+        mem_entries = gen_fdt_mem_array(regions, mem_array,
+                                        MAX_MEM_ARRAY_ENTRIES, memsize);
+        err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
+                          mem_array, mem_entries * 2 * sizeof(mem_array[0]));
+        if (err) {
+                pr_err("Unable to set linux,usable-memory property: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}
+
+__init int yamon_dt_serial_config(void *fdt)
+{
+        const char *yamontty, *mode_var;
+        char mode_var_name[9], path[20], parity;
+        unsigned int uart, baud, stop_bits;
+        bool hw_flow;
+        int chosen_off, err;
+
+        yamontty = fw_getenv("yamontty");
+        if (!yamontty || !strcmp(yamontty, "tty0")) {
+                uart = 0;
+        } else if (!strcmp(yamontty, "tty1")) {
+                uart = 1;
+        } else {
+                pr_warn("yamontty environment variable '%s' invalid\n",
+                        yamontty);
+                uart = 0;
+        }
+
+        baud = stop_bits = 0;
+        parity = 0;
+        hw_flow = false;
+
+        snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
+        mode_var = fw_getenv(mode_var_name);
+        if (mode_var) {
+                while (mode_var[0] >= '0' && mode_var[0] <= '9') {
+                        baud *= 10;
+                        baud += mode_var[0] - '0';
+                        mode_var++;
+                }
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (mode_var[0])
+                        parity = mode_var[0];
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (mode_var[0])
+                        stop_bits = mode_var[0] - '0';
+                if (mode_var[0] == ',')
+                        mode_var++;
+                if (!strcmp(mode_var, "hw"))
+                        hw_flow = true;
+        }
+
+        if (!baud)
+                baud = 38400;
+
+        if (parity != 'e' && parity != 'n' && parity != 'o')
+                parity = 'n';
+
+        if (stop_bits != 7 && stop_bits != 8)
+                stop_bits = 8;
+
+        WARN_ON(snprintf(path, sizeof(path), "serial%u:%u%c%u%s",
+                         uart, baud, parity, stop_bits,
+                         hw_flow ? "r" : "") >= sizeof(path));
+
+        /* find or add chosen node */
+        chosen_off = fdt_path_offset(fdt, "/chosen");
+        if (chosen_off == -FDT_ERR_NOTFOUND)
+                chosen_off = fdt_add_subnode(fdt, 0, "chosen");
+        if (chosen_off < 0) {
+                pr_err("Unable to find or add DT chosen node: %d\n",
+                       chosen_off);
+                return chosen_off;
+        }
+
+        err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
+        if (err) {
+                pr_err("Unable to set stdout-path property: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}