Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release

653 files changed, 128852 insertions, 0 deletions

diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
new file mode 100644
index 000000000..95b4fa7bd
--- /dev/null
+++ b/arch/mips/include/asm/Kbuild
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+# MIPS headers
+generated-y += syscall_table_32_o32.h
+generated-y += syscall_table_64_n32.h
+generated-y += syscall_table_64_n64.h
+generated-y += syscall_table_64_o32.h
+generic-y += export.h
+generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += parport.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
+generic-y += user.h
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
new file mode 100644
index 000000000..dba7f4b6b
--- /dev/null
+++ b/arch/mips/include/asm/abi.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2005 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_ABI_H
+#define _ASM_ABI_H
+
+#include <linux/signal_types.h>
+
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+#include <asm/vdso.h>
+
+struct mips_abi {
+        int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
+                                  struct pt_regs *regs, sigset_t *set);
+        int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
+                                     struct pt_regs *regs, sigset_t *set);
+        const unsigned long     restart;
+
+        unsigned        off_sc_fpregs;
+        unsigned        off_sc_fpc_csr;
+        unsigned        off_sc_used_math;
+
+        struct mips_vdso_image *vdso;
+};
+
+#endif /* _ASM_ABI_H */
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
new file mode 100644
index 000000000..59a48c60a
--- /dev/null
+++ b/arch/mips/include/asm/addrspace.h
@@ -0,0 +1,144 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ADDRSPACE_H
+#define _ASM_ADDRSPACE_H
+
+#include <spaces.h>
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)    x
+#else
+#define _ATYPE_         __PTRDIFF_TYPE__
+#define _ATYPE32_       int
+#define _ATYPE64_       __s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)    x ## L
+#else
+#define _CONST64_(x)    x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_               (_ATYPE_)(_ATYPE32_)    /* widen if necessary */
+#define _ACAST64_               (_ATYPE64_)             /* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)                ((_ACAST32_(a)) & _ACAST32_(0xe0000000))
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)            ((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)            ((_ACAST64_(a)) &                       \
+                                 _CONST64_(0x0000ffffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG                  _CONST64_(0x0000000000000000)
+#define XKSSEG                  _CONST64_(0x4000000000000000)
+#define XKPHYS                  _CONST64_(0x8000000000000000)
+#define XKSEG                   _CONST64_(0xc000000000000000)
+#define CKSEG0                  _CONST64_(0xffffffff80000000)
+#define CKSEG1                  _CONST64_(0xffffffffa0000000)
+#define CKSSEG                  _CONST64_(0xffffffffc0000000)
+#define CKSEG3                  _CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)            (CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)            (CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)            (CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)            (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG                   0x00000000
+#define KSEG0                   0x80000000
+#define KSEG1                   0xa0000000
+#define KSEG2                   0xc0000000
+#define KSEG3                   0xe0000000
+
+#define CKUSEG                  0x00000000
+#define CKSEG0                  0x80000000
+#define CKSEG1                  0xa0000000
+#define CKSEG2                  0xc0000000
+#define CKSEG3                  0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2   0
+#define K_CALG_COH_SHRL1_NOL2   1
+#define K_CALG_UNCACHED         2
+#define K_CALG_NONCOHERENT      3
+#define K_CALG_COH_EXCL         4
+#define K_CALG_COH_SHAREABLE    5
+#define K_CALG_NOTUSED          6
+#define K_CALG_UNCACHED_ACCEL   7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)           (XKPHYS | (_ACAST64_(cm) << 59) | (a))
+
+/*
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
+ */
+#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
+
+#define COMPAT_K1BASE32         _CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#define KDM_TO_PHYS(x)          (_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)           (_ACAST64_ (x) | CAC_BASE)
+
+#endif /* _ASM_ADDRSPACE_H */
diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h
new file mode 100644
index 000000000..3cc03c64a
--- /dev/null
+++ b/arch/mips/include/asm/amon.h
@@ -0,0 +1,12 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * Arbitrary Monitor Support (AMON)
+ */
+int amon_cpu_avail(int cpu);
+int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
+                   unsigned long gp, unsigned long a0);
diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644
index 000000000..712a7445e
--- /dev/null
+++ b/arch/mips/include/asm/arch_hweight.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef _ASM_ARCH_HWEIGHT_H
+#define _ASM_ARCH_HWEIGHT_H
+
+#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
+
+#include <asm/types.h>
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+        return __builtin_popcount(w);
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+        return __builtin_popcount(w & 0xffff);
+}
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+        return __builtin_popcount(w & 0xff);
+}
+
+static inline unsigned long __arch_hweight64(__u64 w)
+{
+        return __builtin_popcountll(w);
+}
+
+#else
+#include <asm-generic/bitops/arch_hweight.h>
+#endif
+
+#endif /* _ASM_ARCH_HWEIGHT_H */
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
new file mode 100644
index 000000000..e327ebc76
--- /dev/null
+++ b/arch/mips/include/asm/asm-eva.h
@@ -0,0 +1,190 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ *
+ */
+
+#ifndef __ASM_ASM_EVA_H
+#define __ASM_ASM_EVA_H
+
+#ifndef __ASSEMBLY__
+
+/* Kernel variants */
+
+#define kernel_cache(op, base)          "cache " op ", " base "\n"
+#define kernel_pref(hint, base)         "pref " hint ", " base "\n"
+#define kernel_ll(reg, addr)            "ll " reg ", " addr "\n"
+#define kernel_sc(reg, addr)            "sc " reg ", " addr "\n"
+#define kernel_lw(reg, addr)            "lw " reg ", " addr "\n"
+#define kernel_lwl(reg, addr)           "lwl " reg ", " addr "\n"
+#define kernel_lwr(reg, addr)           "lwr " reg ", " addr "\n"
+#define kernel_lh(reg, addr)            "lh " reg ", " addr "\n"
+#define kernel_lb(reg, addr)            "lb " reg ", " addr "\n"
+#define kernel_lbu(reg, addr)           "lbu " reg ", " addr "\n"
+#define kernel_sw(reg, addr)            "sw " reg ", " addr "\n"
+#define kernel_swl(reg, addr)           "swl " reg ", " addr "\n"
+#define kernel_swr(reg, addr)           "swr " reg ", " addr "\n"
+#define kernel_sh(reg, addr)            "sh " reg ", " addr "\n"
+#define kernel_sb(reg, addr)            "sb " reg ", " addr "\n"
+
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define kernel_sd(reg, addr)            user_sw(reg, addr)
+#define kernel_ld(reg, addr)            user_lw(reg, addr)
+#else
+#define kernel_sd(reg, addr)            "sd " reg", " addr "\n"
+#define kernel_ld(reg, addr)            "ld " reg", " addr "\n"
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_EVA
+
+#define __BUILD_EVA_INSN(insn, reg, addr)                               \
+                                "       .set    push\n"                 \
+                                "       .set    mips0\n"                \
+                                "       .set    eva\n"                  \
+                                "       "insn" "reg", "addr "\n"        \
+                                "       .set    pop\n"
+
+#define user_cache(op, base)            __BUILD_EVA_INSN("cachee", op, base)
+#define user_pref(hint, base)           __BUILD_EVA_INSN("prefe", hint, base)
+#define user_ll(reg, addr)              __BUILD_EVA_INSN("lle", reg, addr)
+#define user_sc(reg, addr)              __BUILD_EVA_INSN("sce", reg, addr)
+#define user_lw(reg, addr)              __BUILD_EVA_INSN("lwe", reg, addr)
+#define user_lwl(reg, addr)             __BUILD_EVA_INSN("lwle", reg, addr)
+#define user_lwr(reg, addr)             __BUILD_EVA_INSN("lwre", reg, addr)
+#define user_lh(reg, addr)              __BUILD_EVA_INSN("lhe", reg, addr)
+#define user_lb(reg, addr)              __BUILD_EVA_INSN("lbe", reg, addr)
+#define user_lbu(reg, addr)             __BUILD_EVA_INSN("lbue", reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#define user_sw(reg, addr)              __BUILD_EVA_INSN("swe", reg, addr)
+#define user_swl(reg, addr)             __BUILD_EVA_INSN("swle", reg, addr)
+#define user_swr(reg, addr)             __BUILD_EVA_INSN("swre", reg, addr)
+#define user_sh(reg, addr)              __BUILD_EVA_INSN("she", reg, addr)
+#define user_sb(reg, addr)              __BUILD_EVA_INSN("sbe", reg, addr)
+/* No 64-bit EVA instruction for storing double words */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+
+#else
+
+#define user_cache(op, base)            kernel_cache(op, base)
+#define user_pref(hint, base)           kernel_pref(hint, base)
+#define user_ll(reg, addr)              kernel_ll(reg, addr)
+#define user_sc(reg, addr)              kernel_sc(reg, addr)
+#define user_lw(reg, addr)              kernel_lw(reg, addr)
+#define user_lwl(reg, addr)             kernel_lwl(reg, addr)
+#define user_lwr(reg, addr)             kernel_lwr(reg, addr)
+#define user_lh(reg, addr)              kernel_lh(reg, addr)
+#define user_lb(reg, addr)              kernel_lb(reg, addr)
+#define user_lbu(reg, addr)             kernel_lbu(reg, addr)
+#define user_sw(reg, addr)              kernel_sw(reg, addr)
+#define user_swl(reg, addr)             kernel_swl(reg, addr)
+#define user_swr(reg, addr)             kernel_swr(reg, addr)
+#define user_sh(reg, addr)              kernel_sh(reg, addr)
+#define user_sb(reg, addr)              kernel_sb(reg, addr)
+
+#ifdef CONFIG_32BIT
+#define user_sd(reg, addr)              kernel_sw(reg, addr)
+#define user_ld(reg, addr)              kernel_lw(reg, addr)
+#else
+#define user_sd(reg, addr)              kernel_sd(reg, addr)
+#define user_ld(reg, addr)              kernel_ld(reg, addr)
+#endif /* CONFIG_32BIT */
+
+#endif /* CONFIG_EVA */
+
+#else /* __ASSEMBLY__ */
+
+#define kernel_cache(op, base)          cache op, base
+#define kernel_pref(hint, base)         pref hint, base
+#define kernel_ll(reg, addr)            ll reg, addr
+#define kernel_sc(reg, addr)            sc reg, addr
+#define kernel_lw(reg, addr)            lw reg, addr
+#define kernel_lwl(reg, addr)           lwl reg, addr
+#define kernel_lwr(reg, addr)           lwr reg, addr
+#define kernel_lh(reg, addr)            lh reg, addr
+#define kernel_lb(reg, addr)            lb reg, addr
+#define kernel_lbu(reg, addr)           lbu reg, addr
+#define kernel_sw(reg, addr)            sw reg, addr
+#define kernel_swl(reg, addr)           swl reg, addr
+#define kernel_swr(reg, addr)           swr reg, addr
+#define kernel_sh(reg, addr)            sh reg, addr
+#define kernel_sb(reg, addr)            sb reg, addr
+
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define kernel_sd(reg, addr)            user_sw(reg, addr)
+#define kernel_ld(reg, addr)            user_lw(reg, addr)
+#else
+#define kernel_sd(reg, addr)            sd reg, addr
+#define kernel_ld(reg, addr)            ld reg, addr
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_EVA
+
+#define __BUILD_EVA_INSN(insn, reg, addr)                       \
+                                .set    push;                   \
+                                .set    mips0;                  \
+                                .set    eva;                    \
+                                insn reg, addr;                 \
+                                .set    pop;
+
+#define user_cache(op, base)            __BUILD_EVA_INSN(cachee, op, base)
+#define user_pref(hint, base)           __BUILD_EVA_INSN(prefe, hint, base)
+#define user_ll(reg, addr)              __BUILD_EVA_INSN(lle, reg, addr)
+#define user_sc(reg, addr)              __BUILD_EVA_INSN(sce, reg, addr)
+#define user_lw(reg, addr)              __BUILD_EVA_INSN(lwe, reg, addr)
+#define user_lwl(reg, addr)             __BUILD_EVA_INSN(lwle, reg, addr)
+#define user_lwr(reg, addr)             __BUILD_EVA_INSN(lwre, reg, addr)
+#define user_lh(reg, addr)              __BUILD_EVA_INSN(lhe, reg, addr)
+#define user_lb(reg, addr)              __BUILD_EVA_INSN(lbe, reg, addr)
+#define user_lbu(reg, addr)             __BUILD_EVA_INSN(lbue, reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#define user_sw(reg, addr)              __BUILD_EVA_INSN(swe, reg, addr)
+#define user_swl(reg, addr)             __BUILD_EVA_INSN(swle, reg, addr)
+#define user_swr(reg, addr)             __BUILD_EVA_INSN(swre, reg, addr)
+#define user_sh(reg, addr)              __BUILD_EVA_INSN(she, reg, addr)
+#define user_sb(reg, addr)              __BUILD_EVA_INSN(sbe, reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+#else
+
+#define user_cache(op, base)            kernel_cache(op, base)
+#define user_pref(hint, base)           kernel_pref(hint, base)
+#define user_ll(reg, addr)              kernel_ll(reg, addr)
+#define user_sc(reg, addr)              kernel_sc(reg, addr)
+#define user_lw(reg, addr)              kernel_lw(reg, addr)
+#define user_lwl(reg, addr)             kernel_lwl(reg, addr)
+#define user_lwr(reg, addr)             kernel_lwr(reg, addr)
+#define user_lh(reg, addr)              kernel_lh(reg, addr)
+#define user_lb(reg, addr)              kernel_lb(reg, addr)
+#define user_lbu(reg, addr)             kernel_lbu(reg, addr)
+#define user_sw(reg, addr)              kernel_sw(reg, addr)
+#define user_swl(reg, addr)             kernel_swl(reg, addr)
+#define user_swr(reg, addr)             kernel_swr(reg, addr)
+#define user_sh(reg, addr)              kernel_sh(reg, addr)
+#define user_sb(reg, addr)              kernel_sb(reg, addr)
+
+#ifdef CONFIG_32BIT
+#define user_sd(reg, addr)              kernel_sw(reg, addr)
+#define user_ld(reg, addr)              kernel_lw(reg, addr)
+#else
+#define user_sd(reg, addr)              kernel_sd(reg, addr)
+#define user_ld(reg, addr)              kernel_ld(reg, addr)
+#endif /* CONFIG_32BIT */
+
+#endif /* CONFIG_EVA */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ASM_EVA_H */
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000..d370ee36a
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/asm-prototypes.h b/arch/mips/include/asm/asm-prototypes.h
new file mode 100644
index 000000000..f901ed043
--- /dev/null
+++ b/arch/mips/include/asm/asm-prototypes.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm/checksum.h>
+#include <asm/page.h>
+#include <asm/fpu.h>
+#include <asm-generic/asm-prototypes.h>
+#include <linux/uaccess.h>
+#include <asm/ftrace.h>
+#include <asm/mmu_context.h>
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
new file mode 100644
index 000000000..ea4b62ece
--- /dev/null
+++ b/arch/mips/include/asm/asm.h
@@ -0,0 +1,331 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_ASM_H
+#define __ASM_ASM_H
+
+#include <asm/sgidefs.h>
+#include <asm/asm-eva.h>
+
+#ifndef __VDSO__
+/*
+ * Emit CFI data in .debug_frame sections, not .eh_frame sections.
+ * We don't do DWARF unwinding at runtime, so only the offline DWARF
+ * information is useful to anyone. Note we should change this if we
+ * ever decide to enable DWARF unwinding at runtime.
+ */
+#define CFI_SECTIONS    .cfi_sections .debug_frame
+#else
+ /*
+  * For the vDSO, emit both runtime unwind information and debug
+  * symbols for the .dbg file.
+  */
+#define CFI_SECTIONS
+#endif
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define LEAF(symbol)                                    \
+                CFI_SECTIONS;                           \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol, @function;              \
+                .ent    symbol, 0;                      \
+symbol:         .frame  sp, 0, ra;                      \
+                .cfi_startproc;                         \
+                .insn
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define NESTED(symbol, framesize, rpc)                  \
+                CFI_SECTIONS;                           \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol, @function;              \
+                .ent    symbol, 0;                      \
+symbol:         .frame  sp, framesize, rpc;             \
+                .cfi_startproc;                         \
+                .insn
+
+/*
+ * END - mark end of function
+ */
+#define END(function)                                   \
+                .cfi_endproc;                           \
+                .end    function;                       \
+                .size   function, .-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)                                  \
+                .globl  symbol;                         \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)                                 \
+                .globl  symbol;                         \
+                .type   symbol, @function;              \
+symbol:         .insn
+
+/*
+ * ABS - export absolute symbol
+ */
+#define ABS(symbol,value)                               \
+                .globl  symbol;                         \
+symbol          =       value
+
+#define TEXT(msg)                                       \
+                .pushsection .data;                     \
+8:              .asciiz msg;                            \
+                .popsection;
+
+#define ASM_PANIC(msg)                                  \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0, 8f;                         \
+                jal     panic;                          \
+9:              b       9b;                             \
+                .set    pop;                            \
+                TEXT(msg)
+
+/*
+ * Print formatted string
+ */
+#ifdef CONFIG_PRINTK
+#define ASM_PRINT(string)                               \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0, 8f;                         \
+                jal     printk;                         \
+                .set    pop;                            \
+                TEXT(string)
+#else
+#define ASM_PRINT(string)
+#endif
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define ALSZ    7
+#define ALMASK  ~7
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define ALSZ    15
+#define ALMASK  ~15
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#ifdef __mips64
+#define SZREG   8
+#else
+#define SZREG   4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define REG_S           sw
+#define REG_L           lw
+#define REG_SUBU        subu
+#define REG_ADDU        addu
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define REG_S           sd
+#define REG_L           ld
+#define REG_SUBU        dsubu
+#define REG_ADDU        daddu
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+#define INT_ADD         add
+#define INT_ADDU        addu
+#define INT_ADDI        addi
+#define INT_ADDIU       addiu
+#define INT_SUB         sub
+#define INT_SUBU        subu
+#define INT_L           lw
+#define INT_S           sw
+#define INT_SLL         sll
+#define INT_SLLV        sllv
+#define INT_SRL         srl
+#define INT_SRLV        srlv
+#define INT_SRA         sra
+#define INT_SRAV        srav
+#endif
+
+#if (_MIPS_SZINT == 64)
+#define INT_ADD         dadd
+#define INT_ADDU        daddu
+#define INT_ADDI        daddi
+#define INT_ADDIU       daddiu
+#define INT_SUB         dsub
+#define INT_SUBU        dsubu
+#define INT_L           ld
+#define INT_S           sd
+#define INT_SLL         dsll
+#define INT_SLLV        dsllv
+#define INT_SRL         dsrl
+#define INT_SRLV        dsrlv
+#define INT_SRA         dsra
+#define INT_SRAV        dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+#define LONG_ADD        add
+#define LONG_ADDU       addu
+#define LONG_ADDI       addi
+#define LONG_ADDIU      addiu
+#define LONG_SUB        sub
+#define LONG_SUBU       subu
+#define LONG_L          lw
+#define LONG_S          sw
+#define LONG_SP         swp
+#define LONG_SLL        sll
+#define LONG_SLLV       sllv
+#define LONG_SRL        srl
+#define LONG_SRLV       srlv
+#define LONG_SRA        sra
+#define LONG_SRAV       srav
+
+#ifdef __ASSEMBLY__
+#define LONG            .word
+#endif
+#define LONGSIZE        4
+#define LONGMASK        3
+#define LONGLOG         2
+#endif
+
+#if (_MIPS_SZLONG == 64)
+#define LONG_ADD        dadd
+#define LONG_ADDU       daddu
+#define LONG_ADDI       daddi
+#define LONG_ADDIU      daddiu
+#define LONG_SUB        dsub
+#define LONG_SUBU       dsubu
+#define LONG_L          ld
+#define LONG_S          sd
+#define LONG_SP         sdp
+#define LONG_SLL        dsll
+#define LONG_SLLV       dsllv
+#define LONG_SRL        dsrl
+#define LONG_SRLV       dsrlv
+#define LONG_SRA        dsra
+#define LONG_SRAV       dsrav
+
+#ifdef __ASSEMBLY__
+#define LONG            .dword
+#endif
+#define LONGSIZE        8
+#define LONGMASK        7
+#define LONGLOG         3
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD         add
+#define PTR_ADDU        addu
+#define PTR_ADDI        addi
+#define PTR_ADDIU       addiu
+#define PTR_SUB         sub
+#define PTR_SUBU        subu
+#define PTR_L           lw
+#define PTR_S           sw
+#define PTR_LA          la
+#define PTR_LI          li
+#define PTR_SLL         sll
+#define PTR_SLLV        sllv
+#define PTR_SRL         srl
+#define PTR_SRLV        srlv
+#define PTR_SRA         sra
+#define PTR_SRAV        srav
+
+#define PTR_SCALESHIFT  2
+
+#define PTR             .word
+#define PTRSIZE         4
+#define PTRLOG          2
+#endif
+
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD         dadd
+#define PTR_ADDU        daddu
+#define PTR_ADDI        daddi
+#define PTR_ADDIU       daddiu
+#define PTR_SUB         dsub
+#define PTR_SUBU        dsubu
+#define PTR_L           ld
+#define PTR_S           sd
+#define PTR_LA          dla
+#define PTR_LI          dli
+#define PTR_SLL         dsll
+#define PTR_SLLV        dsllv
+#define PTR_SRL         dsrl
+#define PTR_SRLV        dsrlv
+#define PTR_SRA         dsra
+#define PTR_SRAV        dsrav
+
+#define PTR_SCALESHIFT  3
+
+#define PTR             .dword
+#define PTRSIZE         8
+#define PTRLOG          3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define MFC0            mfc0
+#define MTC0            mtc0
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define MFC0            dmfc0
+#define MTC0            dmtc0
+#endif
+
+#define SSNOP           sll zero, zero, 1
+
+#ifdef CONFIG_SGI_IP28
+/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
+#include <asm/cacheops.h>
+#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#else
+#define R10KCBARRIER(addr)
+#endif
+
+#endif /* __ASM_ASM_H */
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
new file mode 100644
index 000000000..1c08c1f79
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998, 1999, 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_32_H
+#define _ASM_ASMMACRO_32_H
+
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  fpu_save_single thread tmp=t0
+        .set push
+        SET_HARDFLOAT
+        cfc1    \tmp,  fcr31
+        s.d     $f0,  THREAD_FPR0(\thread)
+        s.d     $f2,  THREAD_FPR2(\thread)
+        s.d     $f4,  THREAD_FPR4(\thread)
+        s.d     $f6,  THREAD_FPR6(\thread)
+        s.d     $f8,  THREAD_FPR8(\thread)
+        s.d     $f10, THREAD_FPR10(\thread)
+        s.d     $f12, THREAD_FPR12(\thread)
+        s.d     $f14, THREAD_FPR14(\thread)
+        s.d     $f16, THREAD_FPR16(\thread)
+        s.d     $f18, THREAD_FPR18(\thread)
+        s.d     $f20, THREAD_FPR20(\thread)
+        s.d     $f22, THREAD_FPR22(\thread)
+        s.d     $f24, THREAD_FPR24(\thread)
+        s.d     $f26, THREAD_FPR26(\thread)
+        s.d     $f28, THREAD_FPR28(\thread)
+        s.d     $f30, THREAD_FPR30(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .set pop
+        .endm
+
+        .macro  fpu_restore_single thread tmp=t0
+        .set push
+        SET_HARDFLOAT
+        lw      \tmp, THREAD_FCR31(\thread)
+        l.d     $f0,  THREAD_FPR0(\thread)
+        l.d     $f2,  THREAD_FPR2(\thread)
+        l.d     $f4,  THREAD_FPR4(\thread)
+        l.d     $f6,  THREAD_FPR6(\thread)
+        l.d     $f8,  THREAD_FPR8(\thread)
+        l.d     $f10, THREAD_FPR10(\thread)
+        l.d     $f12, THREAD_FPR12(\thread)
+        l.d     $f14, THREAD_FPR14(\thread)
+        l.d     $f16, THREAD_FPR16(\thread)
+        l.d     $f18, THREAD_FPR18(\thread)
+        l.d     $f20, THREAD_FPR20(\thread)
+        l.d     $f22, THREAD_FPR22(\thread)
+        l.d     $f24, THREAD_FPR24(\thread)
+        l.d     $f26, THREAD_FPR26(\thread)
+        l.d     $f28, THREAD_FPR28(\thread)
+        l.d     $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .set pop
+        .endm
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_32_H */
diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
new file mode 100644
index 000000000..68039dee5
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro-64.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998, 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ASMMACRO_64_H
+#define _ASM_ASMMACRO_64_H
+
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_64_H */
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
new file mode 100644
index 000000000..ca83ada70
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro.h
@@ -0,0 +1,658 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_H
+#define _ASM_ASMMACRO_H
+
+#include <asm/hazards.h>
+#include <asm/asm-offsets.h>
+#include <asm/msa.h>
+
+#ifdef CONFIG_32BIT
+#include <asm/asmmacro-32.h>
+#endif
+#ifdef CONFIG_64BIT
+#include <asm/asmmacro-64.h>
+#endif
+
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
+/*
+ * Helper macros for generating raw instruction encodings.
+ */
+#ifdef CONFIG_CPU_MICROMIPS
+        .macro  insn32_if_mm enc
+        .insn
+        .hword ((\enc) >> 16)
+        .hword ((\enc) & 0xffff)
+        .endm
+
+        .macro  insn_if_mips enc
+        .endm
+#else
+        .macro  insn32_if_mm enc
+        .endm
+
+        .macro  insn_if_mips enc
+        .insn
+        .word (\enc)
+        .endm
+#endif
+
+#ifdef CONFIG_CPU_HAS_DIEI
+        .macro  local_irq_enable reg=t0
+        ei
+        irq_enable_hazard
+        .endm
+
+        .macro  local_irq_disable reg=t0
+        di
+        irq_disable_hazard
+        .endm
+#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
+        .macro  local_irq_enable reg=t0
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_enable_hazard
+        .endm
+
+        .macro  local_irq_disable reg=t0
+#ifdef CONFIG_PREEMPTION
+        lw      \reg, TI_PRE_COUNT($28)
+        addi    \reg, \reg, 1
+        sw      \reg, TI_PRE_COUNT($28)
+#endif
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        xori    \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_disable_hazard
+#ifdef CONFIG_PREEMPTION
+        lw      \reg, TI_PRE_COUNT($28)
+        addi    \reg, \reg, -1
+        sw      \reg, TI_PRE_COUNT($28)
+#endif
+        .endm
+#endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
+
+        .macro  fpu_save_16even thread tmp=t0
+        .set    push
+        SET_HARDFLOAT
+        cfc1    \tmp, fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .set    pop
+        .endm
+
+        .macro  fpu_save_16odd thread
+        .set    push
+        .set    mips64r2
+        .set    fp=64
+        SET_HARDFLOAT
+        sdc1    $f1,  THREAD_FPR1(\thread)
+        sdc1    $f3,  THREAD_FPR3(\thread)
+        sdc1    $f5,  THREAD_FPR5(\thread)
+        sdc1    $f7,  THREAD_FPR7(\thread)
+        sdc1    $f9,  THREAD_FPR9(\thread)
+        sdc1    $f11, THREAD_FPR11(\thread)
+        sdc1    $f13, THREAD_FPR13(\thread)
+        sdc1    $f15, THREAD_FPR15(\thread)
+        sdc1    $f17, THREAD_FPR17(\thread)
+        sdc1    $f19, THREAD_FPR19(\thread)
+        sdc1    $f21, THREAD_FPR21(\thread)
+        sdc1    $f23, THREAD_FPR23(\thread)
+        sdc1    $f25, THREAD_FPR25(\thread)
+        sdc1    $f27, THREAD_FPR27(\thread)
+        sdc1    $f29, THREAD_FPR29(\thread)
+        sdc1    $f31, THREAD_FPR31(\thread)
+        .set    pop
+        .endm
+
+        .macro  fpu_save_double thread status tmp
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
+        sll     \tmp, \status, 5
+        bgez    \tmp, 10f
+        fpu_save_16odd \thread
+10:
+#endif
+        fpu_save_16even \thread \tmp
+        .endm
+
+        .macro  fpu_restore_16even thread tmp=t0
+        .set    push
+        SET_HARDFLOAT
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .set    pop
+        .endm
+
+        .macro  fpu_restore_16odd thread
+        .set    push
+        .set    mips64r2
+        .set    fp=64
+        SET_HARDFLOAT
+        ldc1    $f1,  THREAD_FPR1(\thread)
+        ldc1    $f3,  THREAD_FPR3(\thread)
+        ldc1    $f5,  THREAD_FPR5(\thread)
+        ldc1    $f7,  THREAD_FPR7(\thread)
+        ldc1    $f9,  THREAD_FPR9(\thread)
+        ldc1    $f11, THREAD_FPR11(\thread)
+        ldc1    $f13, THREAD_FPR13(\thread)
+        ldc1    $f15, THREAD_FPR15(\thread)
+        ldc1    $f17, THREAD_FPR17(\thread)
+        ldc1    $f19, THREAD_FPR19(\thread)
+        ldc1    $f21, THREAD_FPR21(\thread)
+        ldc1    $f23, THREAD_FPR23(\thread)
+        ldc1    $f25, THREAD_FPR25(\thread)
+        ldc1    $f27, THREAD_FPR27(\thread)
+        ldc1    $f29, THREAD_FPR29(\thread)
+        ldc1    $f31, THREAD_FPR31(\thread)
+        .set    pop
+        .endm
+
+        .macro  fpu_restore_double thread status tmp
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
+        sll     \tmp, \status, 5
+        bgez    \tmp, 10f                               # 16 register mode?
+
+        fpu_restore_16odd \thread
+10:
+#endif
+        fpu_restore_16even \thread \tmp
+        .endm
+
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
+    defined(CONFIG_CPU_MIPSR6)
+        .macro  _EXT    rd, rs, p, s
+        ext     \rd, \rs, \p, \s
+        .endm
+#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
+        .macro  _EXT    rd, rs, p, s
+        srl     \rd, \rs, \p
+        andi    \rd, \rd, (1 << \s) - 1
+        .endm
+#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
+
+/*
+ * Temporary until all gas have MT ASE support
+ */
+        .macro  DMT     reg=0
+        .word   0x41600bc1 | (\reg << 16)
+        .endm
+
+        .macro  EMT     reg=0
+        .word   0x41600be1 | (\reg << 16)
+        .endm
+
+        .macro  DVPE    reg=0
+        .word   0x41600001 | (\reg << 16)
+        .endm
+
+        .macro  EVPE    reg=0
+        .word   0x41600021 | (\reg << 16)
+        .endm
+
+        .macro  MFTR    rt=0, rd=0, u=0, sel=0
+         .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+        .endm
+
+        .macro  MTTR    rt=0, rd=0, u=0, sel=0
+         .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+        .endm
+
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+        .macro  _cfcmsa rd, cs
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        cfcmsa  \rd, $\cs
+        .set    pop
+        .endm
+
+        .macro  _ctcmsa cd, rs
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        ctcmsa  $\cd, \rs
+        .set    pop
+        .endm
+
+        .macro  ld_b    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        ld.b    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  ld_h    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        ld.h    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  ld_w    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        ld.w    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  ld_d    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        ld.d    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  st_b    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        st.b    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  st_h    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        st.h    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  st_w    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        st.w    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  st_d    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        st.d    $w\wd, \off(\base)
+        .set    pop
+        .endm
+
+        .macro  copy_s_w        ws, n
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        copy_s.w $1, $w\ws[\n]
+        .set    pop
+        .endm
+
+        .macro  copy_s_d        ws, n
+        .set    push
+        .set    mips64r2
+        .set    fp=64
+        .set    msa
+        copy_s.d $1, $w\ws[\n]
+        .set    pop
+        .endm
+
+        .macro  insert_w        wd, n
+        .set    push
+        .set    mips32r2
+        .set    fp=64
+        .set    msa
+        insert.w $w\wd[\n], $1
+        .set    pop
+        .endm
+
+        .macro  insert_d        wd, n
+        .set    push
+        .set    mips64r2
+        .set    fp=64
+        .set    msa
+        insert.d $w\wd[\n], $1
+        .set    pop
+        .endm
+#else
+
+        /*
+         * Temporary until all toolchains in use include MSA support.
+         */
+        .macro  _cfcmsa rd, cs
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        insn_if_mips 0x787e0059 | (\cs << 11)
+        insn32_if_mm 0x587e0056 | (\cs << 11)
+        move    \rd, $1
+        .set    pop
+        .endm
+
+        .macro  _ctcmsa cd, rs
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        move    $1, \rs
+        insn_if_mips 0x783e0819 | (\cd << 6)
+        insn32_if_mm 0x583e0816 | (\cd << 6)
+        .set    pop
+        .endm
+
+        .macro  ld_b    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000820 | (\wd << 6)
+        insn32_if_mm 0x58000807 | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  ld_h    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000821 | (\wd << 6)
+        insn32_if_mm 0x58000817 | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  ld_w    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000822 | (\wd << 6)
+        insn32_if_mm 0x58000827 | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  ld_d    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000823 | (\wd << 6)
+        insn32_if_mm 0x58000837 | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  st_b    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000824 | (\wd << 6)
+        insn32_if_mm 0x5800080f | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  st_h    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000825 | (\wd << 6)
+        insn32_if_mm 0x5800081f | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  st_w    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000826 | (\wd << 6)
+        insn32_if_mm 0x5800082f | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  st_d    wd, off, base
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        PTR_ADDU $1, \base, \off
+        insn_if_mips 0x78000827 | (\wd << 6)
+        insn32_if_mm 0x5800083f | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  copy_s_w        ws, n
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
+        insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
+        .set    pop
+        .endm
+
+        .macro  copy_s_d        ws, n
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
+        insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
+        .set    pop
+        .endm
+
+        .macro  insert_w        wd, n
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
+        insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
+        .set    pop
+        .endm
+
+        .macro  insert_d        wd, n
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
+        insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
+        .set    pop
+        .endm
+#endif
+
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+#define FPR_BASE_OFFS   THREAD_FPR0
+#define FPR_BASE        $1
+#else
+#define FPR_BASE_OFFS   0
+#define FPR_BASE        \thread
+#endif
+
+        .macro  msa_save_all    thread
+        .set    push
+        .set    noat
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+        PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
+#endif
+        st_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
+        st_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
+        st_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
+        st_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
+        st_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
+        st_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
+        st_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
+        st_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
+        st_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
+        st_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
+        st_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
+        st_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
+        st_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
+        st_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
+        st_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
+        st_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
+        st_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
+        st_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
+        st_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
+        st_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
+        st_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
+        st_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
+        st_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
+        st_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
+        st_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
+        st_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
+        st_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
+        st_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
+        st_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
+        st_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
+        st_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
+        st_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
+        SET_HARDFLOAT
+        _cfcmsa $1, MSA_CSR
+        sw      $1, THREAD_MSA_CSR(\thread)
+        .set    pop
+        .endm
+
+        .macro  msa_restore_all thread
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        lw      $1, THREAD_MSA_CSR(\thread)
+        _ctcmsa MSA_CSR, $1
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+        PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
+#endif
+        ld_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
+        ld_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
+        ld_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
+        ld_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
+        .set pop
+        .endm
+
+#undef FPR_BASE_OFFS
+#undef FPR_BASE
+
+        .macro  msa_init_upper wd
+#ifdef CONFIG_64BIT
+        insert_d \wd, 1
+#else
+        insert_w \wd, 2
+        insert_w \wd, 3
+#endif
+        .endm
+
+        .macro  msa_init_all_upper
+        .set    push
+        .set    noat
+        SET_HARDFLOAT
+        not     $1, zero
+        msa_init_upper  0
+        msa_init_upper  1
+        msa_init_upper  2
+        msa_init_upper  3
+        msa_init_upper  4
+        msa_init_upper  5
+        msa_init_upper  6
+        msa_init_upper  7
+        msa_init_upper  8
+        msa_init_upper  9
+        msa_init_upper  10
+        msa_init_upper  11
+        msa_init_upper  12
+        msa_init_upper  13
+        msa_init_upper  14
+        msa_init_upper  15
+        msa_init_upper  16
+        msa_init_upper  17
+        msa_init_upper  18
+        msa_init_upper  19
+        msa_init_upper  20
+        msa_init_upper  21
+        msa_init_upper  22
+        msa_init_upper  23
+        msa_init_upper  24
+        msa_init_upper  25
+        msa_init_upper  26
+        msa_init_upper  27
+        msa_init_upper  28
+        msa_init_upper  29
+        msa_init_upper  30
+        msa_init_upper  31
+        .set    pop
+        .endm
+
+#endif /* _ASM_ASMMACRO_H */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
new file mode 100644
index 000000000..27ad76791
--- /dev/null
+++ b/arch/mips/include/asm/atomic.h
@@ -0,0 +1,267 @@
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ * But use these as seldom as possible since they are much more slower
+ * than regular operations.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
+ */
+#ifndef _ASM_ATOMIC_H
+#define _ASM_ATOMIC_H
+
+#include <linux/irqflags.h>
+#include <linux/types.h>
+#include <asm/barrier.h>
+#include <asm/compiler.h>
+#include <asm/cpu-features.h>
+#include <asm/cmpxchg.h>
+#include <asm/llsc.h>
+#include <asm/sync.h>
+#include <asm/war.h>
+
+#define ATOMIC_OPS(pfx, type)                                           \
+static __always_inline type pfx##_read(const pfx##_t *v)                \
+{                                                                       \
+        return READ_ONCE(v->counter);                                   \
+}                                                                       \
+                                                                        \
+static __always_inline void pfx##_set(pfx##_t *v, type i)               \
+{                                                                       \
+        WRITE_ONCE(v->counter, i);                                      \
+}                                                                       \
+                                                                        \
+static __always_inline type pfx##_cmpxchg(pfx##_t *v, type o, type n)   \
+{                                                                       \
+        return cmpxchg(&v->counter, o, n);                              \
+}                                                                       \
+                                                                        \
+static __always_inline type pfx##_xchg(pfx##_t *v, type n)              \
+{                                                                       \
+        return xchg(&v->counter, n);                                    \
+}
+
+ATOMIC_OPS(atomic, int)
+
+#ifdef CONFIG_64BIT
+# define ATOMIC64_INIT(i)       { (i) }
+ATOMIC_OPS(atomic64, s64)
+#endif
+
+#define ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc)                  \
+static __inline__ void pfx##_##op(type i, pfx##_t * v)                  \
+{                                                                       \
+        type temp;                                                      \
+                                                                        \
+        if (!kernel_uses_llsc) {                                        \
+                unsigned long flags;                                    \
+                                                                        \
+                raw_local_irq_save(flags);                              \
+                v->counter c_op i;                                      \
+                raw_local_irq_restore(flags);                           \
+                return;                                                 \
+        }                                                               \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    " MIPS_ISA_LEVEL "                      \n"     \
+        "       " __SYNC(full, loongson3_war) "                 \n"     \
+        "1:     " #ll " %0, %1          # " #pfx "_" #op "      \n"     \
+        "       " #asm_op " %0, %2                              \n"     \
+        "       " #sc " %0, %1                                  \n"     \
+        "\t" __SC_BEQZ "%0, 1b                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter)            \
+        : "Ir" (i) : __LLSC_CLOBBER);                                   \
+}
+
+#define ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc)           \
+static __inline__ type pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
+{                                                                       \
+        type temp, result;                                              \
+                                                                        \
+        if (!kernel_uses_llsc) {                                        \
+                unsigned long flags;                                    \
+                                                                        \
+                raw_local_irq_save(flags);                              \
+                result = v->counter;                                    \
+                result c_op i;                                          \
+                v->counter = result;                                    \
+                raw_local_irq_restore(flags);                           \
+                return result;                                          \
+        }                                                               \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    " MIPS_ISA_LEVEL "                      \n"     \
+        "       " __SYNC(full, loongson3_war) "                 \n"     \
+        "1:     " #ll " %1, %2          # " #pfx "_" #op "_return\n"    \
+        "       " #asm_op " %0, %1, %3                          \n"     \
+        "       " #sc " %0, %2                                  \n"     \
+        "\t" __SC_BEQZ "%0, 1b                                  \n"     \
+        "       " #asm_op " %0, %1, %3                          \n"     \
+        "       .set    pop                                     \n"     \
+        : "=&r" (result), "=&r" (temp),                                 \
+          "+" GCC_OFF_SMALL_ASM() (v->counter)                          \
+        : "Ir" (i) : __LLSC_CLOBBER);                                   \
+                                                                        \
+        return result;                                                  \
+}
+
+#define ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)            \
+static __inline__ type pfx##_fetch_##op##_relaxed(type i, pfx##_t * v)  \
+{                                                                       \
+        int temp, result;                                               \
+                                                                        \
+        if (!kernel_uses_llsc) {                                        \
+                unsigned long flags;                                    \
+                                                                        \
+                raw_local_irq_save(flags);                              \
+                result = v->counter;                                    \
+                v->counter c_op i;                                      \
+                raw_local_irq_restore(flags);                           \
+                return result;                                          \
+        }                                                               \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    " MIPS_ISA_LEVEL "                      \n"     \
+        "       " __SYNC(full, loongson3_war) "                 \n"     \
+        "1:     " #ll " %1, %2          # " #pfx "_fetch_" #op "\n"     \
+        "       " #asm_op " %0, %1, %3                          \n"     \
+        "       " #sc " %0, %2                                  \n"     \
+        "\t" __SC_BEQZ "%0, 1b                                  \n"     \
+        "       .set    pop                                     \n"     \
+        "       move    %0, %1                                  \n"     \
+        : "=&r" (result), "=&r" (temp),                                 \
+          "+" GCC_OFF_SMALL_ASM() (v->counter)                          \
+        : "Ir" (i) : __LLSC_CLOBBER);                                   \
+                                                                        \
+        return result;                                                  \
+}
+
+#undef ATOMIC_OPS
+#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc)                 \
+        ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc)                  \
+        ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc)           \
+        ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
+
+ATOMIC_OPS(atomic, add, int, +=, addu, ll, sc)
+ATOMIC_OPS(atomic, sub, int, -=, subu, ll, sc)
+
+#define atomic_add_return_relaxed       atomic_add_return_relaxed
+#define atomic_sub_return_relaxed       atomic_sub_return_relaxed
+#define atomic_fetch_add_relaxed        atomic_fetch_add_relaxed
+#define atomic_fetch_sub_relaxed        atomic_fetch_sub_relaxed
+
+#ifdef CONFIG_64BIT
+ATOMIC_OPS(atomic64, add, s64, +=, daddu, lld, scd)
+ATOMIC_OPS(atomic64, sub, s64, -=, dsubu, lld, scd)
+# define atomic64_add_return_relaxed    atomic64_add_return_relaxed
+# define atomic64_sub_return_relaxed    atomic64_sub_return_relaxed
+# define atomic64_fetch_add_relaxed     atomic64_fetch_add_relaxed
+# define atomic64_fetch_sub_relaxed     atomic64_fetch_sub_relaxed
+#endif /* CONFIG_64BIT */
+
+#undef ATOMIC_OPS
+#define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc)                 \
+        ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc)                  \
+        ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
+
+ATOMIC_OPS(atomic, and, int, &=, and, ll, sc)
+ATOMIC_OPS(atomic, or, int, |=, or, ll, sc)
+ATOMIC_OPS(atomic, xor, int, ^=, xor, ll, sc)
+
+#define atomic_fetch_and_relaxed        atomic_fetch_and_relaxed
+#define atomic_fetch_or_relaxed         atomic_fetch_or_relaxed
+#define atomic_fetch_xor_relaxed        atomic_fetch_xor_relaxed
+
+#ifdef CONFIG_64BIT
+ATOMIC_OPS(atomic64, and, s64, &=, and, lld, scd)
+ATOMIC_OPS(atomic64, or, s64, |=, or, lld, scd)
+ATOMIC_OPS(atomic64, xor, s64, ^=, xor, lld, scd)
+# define atomic64_fetch_and_relaxed     atomic64_fetch_and_relaxed
+# define atomic64_fetch_or_relaxed      atomic64_fetch_or_relaxed
+# define atomic64_fetch_xor_relaxed     atomic64_fetch_xor_relaxed
+#endif
+
+#undef ATOMIC_OPS
+#undef ATOMIC_FETCH_OP
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
+
+/*
+ * atomic_sub_if_positive - conditionally subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically test @v and subtract @i if @v is greater or equal than @i.
+ * The function returns the old value of @v minus @i.
+ */
+#define ATOMIC_SIP_OP(pfx, type, op, ll, sc)                            \
+static __inline__ int pfx##_sub_if_positive(type i, pfx##_t * v)        \
+{                                                                       \
+        type temp, result;                                              \
+                                                                        \
+        smp_mb__before_atomic();                                        \
+                                                                        \
+        if (!kernel_uses_llsc) {                                        \
+                unsigned long flags;                                    \
+                                                                        \
+                raw_local_irq_save(flags);                              \
+                result = v->counter;                                    \
+                result -= i;                                            \
+                if (result >= 0)                                        \
+                        v->counter = result;                            \
+                raw_local_irq_restore(flags);                           \
+                smp_mb__after_atomic();                                 \
+                return result;                                          \
+        }                                                               \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    " MIPS_ISA_LEVEL "                      \n"     \
+        "       " __SYNC(full, loongson3_war) "                 \n"     \
+        "1:     " #ll " %1, %2          # atomic_sub_if_positive\n"     \
+        "       .set    pop                                     \n"     \
+        "       " #op " %0, %1, %3                              \n"     \
+        "       move    %1, %0                                  \n"     \
+        "       bltz    %0, 2f                                  \n"     \
+        "       .set    push                                    \n"     \
+        "       .set    " MIPS_ISA_LEVEL "                      \n"     \
+        "       " #sc " %1, %2                                  \n"     \
+        "       " __SC_BEQZ "%1, 1b                             \n"     \
+        "2:     " __SYNC(full, loongson3_war) "                 \n"     \
+        "       .set    pop                                     \n"     \
+        : "=&r" (result), "=&r" (temp),                                 \
+          "+" GCC_OFF_SMALL_ASM() (v->counter)                          \
+        : "Ir" (i)                                                      \
+        : __LLSC_CLOBBER);                                              \
+                                                                        \
+        /*                                                              \
+         * In the Loongson3 workaround case we already have a           \
+         * completion barrier at 2: above, which is needed due to the   \
+         * bltz that can branch to code outside of the LL/SC loop. As   \
+         * such, we don't need to emit another barrier here.            \
+         */                                                             \
+        if (__SYNC_loongson3_war == 0)                                  \
+                smp_mb__after_atomic();                                 \
+                                                                        \
+        return result;                                                  \
+}
+
+ATOMIC_SIP_OP(atomic, int, subu, ll, sc)
+#define atomic_dec_if_positive(v)       atomic_sub_if_positive(1, v)
+
+#ifdef CONFIG_64BIT
+ATOMIC_SIP_OP(atomic64, s64, dsubu, lld, scd)
+#define atomic64_dec_if_positive(v)     atomic64_sub_if_positive(1, v)
+#endif
+
+#undef ATOMIC_SIP_OP
+
+#endif /* _ASM_ATOMIC_H */
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
new file mode 100644
index 000000000..49ff172a7
--- /dev/null
+++ b/arch/mips/include/asm/barrier.h
@@ -0,0 +1,142 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+#include <asm/addrspace.h>
+#include <asm/sync.h>
+
+static inline void __sync(void)
+{
+        asm volatile(__SYNC(full, always) ::: "memory");
+}
+
+static inline void rmb(void)
+{
+        asm volatile(__SYNC(rmb, always) ::: "memory");
+}
+#define rmb rmb
+
+static inline void wmb(void)
+{
+        asm volatile(__SYNC(wmb, always) ::: "memory");
+}
+#define wmb wmb
+
+#define fast_mb()       __sync()
+
+#define __fast_iob()                            \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "nop\n\t"                       \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1)          \
+                : "memory")
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+# define fast_iob()     do { } while (0)
+#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
+# ifdef CONFIG_SGI_IP28
+#  define fast_iob()                            \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "sync\n\t"                      \
+                "lw     $0,%0\n\t"              \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
+                : "memory")
+# else
+#  define fast_iob()                            \
+        do {                                    \
+                __sync();                       \
+                __fast_iob();                   \
+        } while (0)
+# endif
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
+
+#ifdef CONFIG_CPU_HAS_WB
+
+#include <asm/wbflush.h>
+
+#define mb()            wbflush()
+#define iob()           wbflush()
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define mb()            fast_mb()
+#define iob()           fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#if defined(CONFIG_WEAK_ORDERING)
+# define __smp_mb()     __sync()
+# define __smp_rmb()    rmb()
+# define __smp_wmb()    wmb()
+#else
+# define __smp_mb()     barrier()
+# define __smp_rmb()    barrier()
+# define __smp_wmb()    barrier()
+#endif
+
+/*
+ * When LL/SC does imply order, it must also be a compiler barrier to avoid the
+ * compiler from reordering where the CPU will not. When it does not imply
+ * order, the compiler is also free to reorder across the LL/SC loop and
+ * ordering will be done by smp_llsc_mb() and friends.
+ */
+#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
+# define __WEAK_LLSC_MB         sync
+# define smp_llsc_mb() \
+        __asm__ __volatile__(__stringify(__WEAK_LLSC_MB) : : :"memory")
+# define __LLSC_CLOBBER
+#else
+# define __WEAK_LLSC_MB
+# define smp_llsc_mb()          do { } while (0)
+# define __LLSC_CLOBBER         "memory"
+#endif
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define smp_mb__before_llsc() smp_wmb()
+#define __smp_mb__before_llsc() __smp_wmb()
+/* Cause previous writes to become visible on all CPUs as soon as possible */
+#define nudge_writes() __asm__ __volatile__(".set push\n\t"             \
+                                            ".set arch=octeon\n\t"      \
+                                            "syncw\n\t"                 \
+                                            ".set pop" : : : "memory")
+#else
+#define smp_mb__before_llsc() smp_llsc_mb()
+#define __smp_mb__before_llsc() smp_llsc_mb()
+#define nudge_writes() mb()
+#endif
+
+/*
+ * In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have
+ * a completion barrier immediately preceding the LL instruction. Therefore we
+ * can skip emitting a barrier from __smp_mb__before_atomic().
+ */
+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
+# define __smp_mb__before_atomic()
+#else
+# define __smp_mb__before_atomic()      __smp_mb__before_llsc()
+#endif
+
+#define __smp_mb__after_atomic()        smp_llsc_mb()
+
+static inline void sync_ginv(void)
+{
+        asm volatile(__SYNC(ginv, always));
+}
+
+#include <asm-generic/barrier.h>
+
+#endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h
new file mode 100644
index 000000000..a00857b13
--- /dev/null
+++ b/arch/mips/include/asm/bcache.h
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BCACHE_H
+#define _ASM_BCACHE_H
+
+#include <linux/types.h>
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
+   chipset implemented caches.  On machines with other CPUs the CPU does the
+   cache thing itself. */
+struct bcache_ops {
+        void (*bc_enable)(void);
+        void (*bc_disable)(void);
+        void (*bc_wback_inv)(unsigned long page, unsigned long size);
+        void (*bc_inv)(unsigned long page, unsigned long size);
+        void (*bc_prefetch_enable)(void);
+        void (*bc_prefetch_disable)(void);
+        bool (*bc_prefetch_is_enabled)(void);
+};
+
+extern void indy_sc_init(void);
+
+#ifdef CONFIG_BOARD_SCACHE
+
+extern struct bcache_ops *bcops;
+
+static inline void bc_enable(void)
+{
+        bcops->bc_enable();
+}
+
+static inline void bc_disable(void)
+{
+        bcops->bc_disable();
+}
+
+static inline void bc_wback_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_wback_inv(page, size);
+}
+
+static inline void bc_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_inv(page, size);
+}
+
+static inline void bc_prefetch_enable(void)
+{
+        if (bcops->bc_prefetch_enable)
+                bcops->bc_prefetch_enable();
+}
+
+static inline void bc_prefetch_disable(void)
+{
+        if (bcops->bc_prefetch_disable)
+                bcops->bc_prefetch_disable();
+}
+
+static inline bool bc_prefetch_is_enabled(void)
+{
+        if (bcops->bc_prefetch_is_enabled)
+                return bcops->bc_prefetch_is_enabled();
+
+        return false;
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000.  */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+#define bc_prefetch_enable() do { } while (0)
+#define bc_prefetch_disable() do { } while (0)
+#define bc_prefetch_is_enabled() 0
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
+
+#endif /* _ASM_BCACHE_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
new file mode 100644
index 000000000..a74769940
--- /dev/null
+++ b/arch/mips/include/asm/bitops.h
@@ -0,0 +1,463 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/bits.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/barrier.h>
+#include <asm/byteorder.h>              /* sigh ... */
+#include <asm/compiler.h>
+#include <asm/cpu-features.h>
+#include <asm/isa-rev.h>
+#include <asm/llsc.h>
+#include <asm/sgidefs.h>
+#include <asm/war.h>
+
+#define __bit_op(mem, insn, inputs...) do {                     \
+        unsigned long temp;                                     \
+                                                                \
+        asm volatile(                                           \
+        "       .set            push                    \n"     \
+        "       .set            " MIPS_ISA_LEVEL "      \n"     \
+        "       " __SYNC(full, loongson3_war) "         \n"     \
+        "1:     " __LL          "%0, %1                 \n"     \
+        "       " insn          "                       \n"     \
+        "       " __SC          "%0, %1                 \n"     \
+        "       " __SC_BEQZ     "%0, 1b                 \n"     \
+        "       .set            pop                     \n"     \
+        : "=&r"(temp), "+" GCC_OFF_SMALL_ASM()(mem)             \
+        : inputs                                                \
+        : __LLSC_CLOBBER);                                      \
+} while (0)
+
+#define __test_bit_op(mem, ll_dst, insn, inputs...) ({          \
+        unsigned long orig, temp;                               \
+                                                                \
+        asm volatile(                                           \
+        "       .set            push                    \n"     \
+        "       .set            " MIPS_ISA_LEVEL "      \n"     \
+        "       " __SYNC(full, loongson3_war) "         \n"     \
+        "1:     " __LL          ll_dst ", %2            \n"     \
+        "       " insn          "                       \n"     \
+        "       " __SC          "%1, %2                 \n"     \
+        "       " __SC_BEQZ     "%1, 1b                 \n"     \
+        "       .set            pop                     \n"     \
+        : "=&r"(orig), "=&r"(temp),                             \
+          "+" GCC_OFF_SMALL_ASM()(mem)                          \
+        : inputs                                                \
+        : __LLSC_CLOBBER);                                      \
+                                                                \
+        orig;                                                   \
+})
+
+/*
+ * These are the "slower" versions of the functions and are in bitops.c.
+ * These functions call raw_local_irq_{save,restore}().
+ */
+void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
+void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
+int __mips_test_and_set_bit_lock(unsigned long nr,
+                                 volatile unsigned long *addr);
+int __mips_test_and_clear_bit(unsigned long nr,
+                              volatile unsigned long *addr);
+int __mips_test_and_change_bit(unsigned long nr,
+                               volatile unsigned long *addr);
+
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+
+        if (!kernel_uses_llsc) {
+                __mips_set_bit(nr, addr);
+                return;
+        }
+
+        if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) {
+                __bit_op(*m, __INS "%0, %3, %2, 1", "i"(bit), "r"(~0));
+                return;
+        }
+
+        __bit_op(*m, "or\t%0, %2", "ir"(BIT(bit)));
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+
+        if (!kernel_uses_llsc) {
+                __mips_clear_bit(nr, addr);
+                return;
+        }
+
+        if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) {
+                __bit_op(*m, __INS "%0, $0, %2, 1", "i"(bit));
+                return;
+        }
+
+        __bit_op(*m, "and\t%0, %2", "ir"(~BIT(bit)));
+}
+
+/*
+ * clear_bit_unlock - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and implies release semantics before the memory
+ * operation. It can be used for an unlock.
+ */
+static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
+{
+        smp_mb__before_atomic();
+        clear_bit(nr, addr);
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+
+        if (!kernel_uses_llsc) {
+                __mips_change_bit(nr, addr);
+                return;
+        }
+
+        __bit_op(*m, "xor\t%0, %2", "ir"(BIT(bit)));
+}
+
+/*
+ * test_and_set_bit_lock - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and implies acquire ordering semantics
+ * after the memory operation.
+ */
+static inline int test_and_set_bit_lock(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+        unsigned long res, orig;
+
+        if (!kernel_uses_llsc) {
+                res = __mips_test_and_set_bit_lock(nr, addr);
+        } else {
+                orig = __test_bit_op(*m, "%0",
+                                     "or\t%1, %0, %3",
+                                     "ir"(BIT(bit)));
+                res = (orig & BIT(bit)) != 0;
+        }
+
+        smp_llsc_mb();
+
+        return res;
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        smp_mb__before_atomic();
+        return test_and_set_bit_lock(nr, addr);
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+        unsigned long res, orig;
+
+        smp_mb__before_atomic();
+
+        if (!kernel_uses_llsc) {
+                res = __mips_test_and_clear_bit(nr, addr);
+        } else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
+                res = __test_bit_op(*m, "%1",
+                                    __EXT "%0, %1, %3, 1;"
+                                    __INS "%1, $0, %3, 1",
+                                    "i"(bit));
+        } else {
+                orig = __test_bit_op(*m, "%0",
+                                     "or\t%1, %0, %3;"
+                                     "xor\t%1, %1, %3",
+                                     "ir"(BIT(bit)));
+                res = (orig & BIT(bit)) != 0;
+        }
+
+        smp_llsc_mb();
+
+        return res;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        volatile unsigned long *m = &addr[BIT_WORD(nr)];
+        int bit = nr % BITS_PER_LONG;
+        unsigned long res, orig;
+
+        smp_mb__before_atomic();
+
+        if (!kernel_uses_llsc) {
+                res = __mips_test_and_change_bit(nr, addr);
+        } else {
+                orig = __test_bit_op(*m, "%0",
+                                     "xor\t%1, %0, %3",
+                                     "ir"(BIT(bit)));
+                res = (orig & BIT(bit)) != 0;
+        }
+
+        smp_llsc_mb();
+
+        return res;
+}
+
+#undef __bit_op
+#undef __test_bit_op
+
+#include <asm-generic/bitops/non-atomic.h>
+
+/*
+ * __clear_bit_unlock - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * __clear_bit() is non-atomic and implies release semantics before the memory
+ * operation. It can be used for an unlock if no other CPUs can concurrently
+ * modify other bits in the word.
+ */
+static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
+{
+        smp_mb__before_llsc();
+        __clear_bit(nr, addr);
+        nudge_writes();
+}
+
+/*
+ * Return the bit position (0..63) of the most significant 1 bit in a word
+ * Returns -1 if no 1 bit exists
+ */
+static __always_inline unsigned long __fls(unsigned long word)
+{
+        int num;
+
+        if (BITS_PER_LONG == 32 && !__builtin_constant_p(word) &&
+            __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
+                __asm__(
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_LEVEL"                        \n"
+                "       clz     %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (num)
+                : "r" (word));
+
+                return 31 - num;
+        }
+
+        if (BITS_PER_LONG == 64 && !__builtin_constant_p(word) &&
+            __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
+                __asm__(
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_LEVEL"                        \n"
+                "       dclz    %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (num)
+                : "r" (word));
+
+                return 63 - num;
+        }
+
+        num = BITS_PER_LONG - 1;
+
+#if BITS_PER_LONG == 64
+        if (!(word & (~0ul << 32))) {
+                num -= 32;
+                word <<= 32;
+        }
+#endif
+        if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
+                num -= 16;
+                word <<= 16;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
+                num -= 8;
+                word <<= 8;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
+                num -= 4;
+                word <<= 4;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
+                num -= 2;
+                word <<= 2;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-1))))
+                num -= 1;
+        return num;
+}
+
+/*
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Returns 0..SZLONG-1
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __ffs(unsigned long word)
+{
+        return __fls(word & -word);
+}
+
+/*
+ * fls - find last bit set.
+ * @word: The word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int fls(unsigned int x)
+{
+        int r;
+
+        if (!__builtin_constant_p(x) &&
+            __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
+                __asm__(
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_LEVEL"                        \n"
+                "       clz     %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (x)
+                : "r" (x));
+
+                return 32 - x;
+        }
+
+        r = 32;
+        if (!x)
+                return 0;
+        if (!(x & 0xffff0000u)) {
+                x <<= 16;
+                r -= 16;
+        }
+        if (!(x & 0xff000000u)) {
+                x <<= 8;
+                r -= 8;
+        }
+        if (!(x & 0xf0000000u)) {
+                x <<= 4;
+                r -= 4;
+        }
+        if (!(x & 0xc0000000u)) {
+                x <<= 2;
+                r -= 2;
+        }
+        if (!(x & 0x80000000u)) {
+                x <<= 1;
+                r -= 1;
+        }
+        return r;
+}
+
+#include <asm-generic/bitops/fls64.h>
+
+/*
+ * ffs - find first bit set.
+ * @word: The word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int word)
+{
+        if (!word)
+                return 0;
+
+        return fls(word & -word);
+}
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/sched.h>
+
+#include <asm/arch_hweight.h>
+#include <asm-generic/bitops/const_hweight.h>
+
+#include <asm-generic/bitops/le.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_BITOPS_H */
diff --git a/arch/mips/include/asm/bitrev.h b/arch/mips/include/asm/bitrev.h
new file mode 100644
index 000000000..8a2538e08
--- /dev/null
+++ b/arch/mips/include/asm/bitrev.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MIPS_ASM_BITREV_H__
+#define __MIPS_ASM_BITREV_H__
+
+#include <linux/swab.h>
+
+static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x)
+{
+        u32 ret;
+
+        asm("bitswap    %0, %1" : "=r"(ret) : "r"(__swab32(x)));
+        return ret;
+}
+
+static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x)
+{
+        u16 ret;
+
+        asm("bitswap    %0, %1" : "=r"(ret) : "r"(__swab16(x)));
+        return ret;
+}
+
+static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x)
+{
+        u8 ret;
+
+        asm("bitswap    %0, %1" : "=r"(ret) : "r"(x));
+        return ret;
+}
+
+#endif /* __MIPS_ASM_BITREV_H__ */
diff --git a/arch/mips/include/asm/bmips-spaces.h b/arch/mips/include/asm/bmips-spaces.h
new file mode 100644
index 000000000..febc4c30a
--- /dev/null
+++ b/arch/mips/include/asm/bmips-spaces.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_BMIPS_SPACES_H
+#define __ASM_BMIPS_SPACES_H
+
+/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0xff000000)
+
+#endif /* __ASM_BMIPS_SPACES_H */
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 000000000..581a6a3c6
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,128 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * Definitions for BMIPS processors
+ */
+#ifndef _ASM_BMIPS_H
+#define _ASM_BMIPS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+
+/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
+#define BMIPS_GET_CBR()                 ((void __iomem *)(CKSEG1 | \
+                                         (unsigned long) \
+                                         ((read_c0_brcm_cbr() >> 18) << 18)))
+
+#define BMIPS_RAC_CONFIG                0x00000000
+#define BMIPS_RAC_ADDRESS_RANGE         0x00000004
+#define BMIPS_RAC_CONFIG_1              0x00000008
+#define BMIPS_L2_CONFIG                 0x0000000c
+#define BMIPS_LMB_CONTROL               0x0000001c
+#define BMIPS_SYSTEM_BASE               0x00000020
+#define BMIPS_PERF_GLOBAL_CONTROL       0x00020000
+#define BMIPS_PERF_CONTROL_0            0x00020004
+#define BMIPS_PERF_CONTROL_1            0x00020008
+#define BMIPS_PERF_COUNTER_0            0x00020010
+#define BMIPS_PERF_COUNTER_1            0x00020014
+#define BMIPS_PERF_COUNTER_2            0x00020018
+#define BMIPS_PERF_COUNTER_3            0x0002001c
+#define BMIPS_RELO_VECTOR_CONTROL_0     0x00030000
+#define BMIPS_RELO_VECTOR_CONTROL_1     0x00038000
+
+#define BMIPS_NMI_RESET_VEC             0x80000000
+#define BMIPS_WARM_RESTART_VEC          0x80000380
+
+#define ZSCM_REG_BASE                   0x97000000
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/cpumask.h>
+#include <asm/r4kcache.h>
+#include <asm/smp-ops.h>
+
+extern const struct plat_smp_ops bmips43xx_smp_ops;
+extern const struct plat_smp_ops bmips5000_smp_ops;
+
+static inline int register_bmips_smp_ops(void)
+{
+#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
+        switch (current_cpu_type()) {
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+                return register_up_smp_ops();
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                register_smp_ops(&bmips43xx_smp_ops);
+                break;
+        case CPU_BMIPS5000:
+                register_smp_ops(&bmips5000_smp_ops);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+#else
+        return -ENODEV;
+#endif
+}
+
+extern char bmips_reset_nmi_vec[];
+extern char bmips_reset_nmi_vec_end[];
+extern char bmips_smp_movevec[];
+extern char bmips_smp_int_vec[];
+extern char bmips_smp_int_vec_end[];
+
+extern int bmips_smp_enabled;
+extern int bmips_cpu_offset;
+extern cpumask_t bmips_booted_mask;
+extern unsigned long bmips_tp1_irqs;
+
+extern void bmips_ebase_setup(void);
+extern asmlinkage void plat_wired_tlb_setup(void);
+extern void bmips_cpu_setup(void);
+
+static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
+{
+        unsigned long ret;
+
+        barrier();
+        cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
+        __sync();
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        ret = read_c0_ddatalo();
+        _ssnop();
+
+        return ret;
+}
+
+static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
+{
+        write_c0_ddatalo(data);
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
+        _ssnop();
+        _ssnop();
+        _ssnop();
+        barrier();
+}
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
new file mode 100644
index 000000000..aa03b1237
--- /dev/null
+++ b/arch/mips/include/asm/bootinfo.h
@@ -0,0 +1,166 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2003 by Ralf Baechle
+ * Copyright (C) 1995, 1996 Andreas Busse
+ * Copyright (C) 1995, 1996 Stoned Elipot
+ * Copyright (C) 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 2009       Zhang Le
+ */
+#ifndef _ASM_BOOTINFO_H
+#define _ASM_BOOTINFO_H
+
+#include <linux/types.h>
+#include <asm/setup.h>
+
+/*
+ * The MACH_ IDs are sort of equivalent to PCI product IDs.  As such the
+ * numbers do not necessarily reflect technical relations or similarities
+ * between systems.
+ */
+
+/*
+ * Valid machtype values for group unknown
+ */
+#define  MACH_UNKNOWN           0       /* whatever...                  */
+
+/*
+ * Valid machtype for group DEC
+ */
+#define  MACH_DSUNKNOWN         0
+#define  MACH_DS23100           1       /* DECstation 2100 or 3100      */
+#define  MACH_DS5100            2       /* DECsystem 5100               */
+#define  MACH_DS5000_200        3       /* DECstation 5000/200          */
+#define  MACH_DS5000_1XX        4       /* DECstation 5000/120, 125, 133, 150 */
+#define  MACH_DS5000_XX         5       /* DECstation 5000/20, 25, 33, 50 */
+#define  MACH_DS5000_2X0        6       /* DECstation 5000/240, 260     */
+#define  MACH_DS5400            7       /* DECsystem 5400               */
+#define  MACH_DS5500            8       /* DECsystem 5500               */
+#define  MACH_DS5800            9       /* DECsystem 5800               */
+#define  MACH_DS5900            10      /* DECsystem 5900               */
+
+/*
+ * Valid machtype for group Mikrotik
+ */
+#define MACH_MIKROTIK_RB532     0       /* Mikrotik RouterBoard 532     */
+#define MACH_MIKROTIK_RB532A    1       /* Mikrotik RouterBoard 532A    */
+
+/*
+ * Valid machtype for Loongson family
+ */
+enum loongson2ef_machine_type {
+        MACH_LOONGSON_UNKNOWN,
+        MACH_LEMOTE_FL2E,
+        MACH_LEMOTE_FL2F,
+        MACH_LEMOTE_ML2F7,
+        MACH_LEMOTE_YL2F89,
+        MACH_DEXXON_GDIUM2F10,
+        MACH_LEMOTE_NAS,
+        MACH_LEMOTE_LL2F,
+        MACH_LOONGSON_END
+};
+
+/*
+ * Valid machtype for group INGENIC
+ */
+enum ingenic_machine_type {
+        MACH_INGENIC_UNKNOWN,
+        MACH_INGENIC_JZ4720,
+        MACH_INGENIC_JZ4725,
+        MACH_INGENIC_JZ4725B,
+        MACH_INGENIC_JZ4730,
+        MACH_INGENIC_JZ4740,
+        MACH_INGENIC_JZ4750,
+        MACH_INGENIC_JZ4755,
+        MACH_INGENIC_JZ4760,
+        MACH_INGENIC_JZ4770,
+        MACH_INGENIC_JZ4775,
+        MACH_INGENIC_JZ4780,
+        MACH_INGENIC_X1000,
+        MACH_INGENIC_X1000E,
+        MACH_INGENIC_X1830,
+        MACH_INGENIC_X2000,
+        MACH_INGENIC_X2000E,
+};
+
+extern char *system_type;
+const char *get_system_type(void);
+
+extern unsigned long mips_machtype;
+
+extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min,  phys_addr_t sz_max);
+
+extern void prom_init(void);
+extern void prom_free_prom_memory(void);
+extern void prom_cleanup(void);
+
+extern void free_init_pages(const char *what,
+                            unsigned long begin, unsigned long end);
+
+extern void (*free_init_pages_eva)(void *begin, void *end);
+
+/*
+ * Initial kernel command line, usually setup by prom_init()
+ */
+extern char arcs_cmdline[COMMAND_LINE_SIZE];
+
+/*
+ * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
+ */
+extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
+
+#ifdef CONFIG_USE_OF
+extern unsigned long fw_passed_dtb;
+#endif
+
+/*
+ * Platform memory detection hook called by arch_mem_init()
+ */
+extern void plat_mem_setup(void);
+
+#ifdef CONFIG_SWIOTLB
+/*
+ * Optional platform hook to call swiotlb_setup().
+ */
+extern void plat_swiotlb_setup(void);
+
+#else
+
+static inline void plat_swiotlb_setup(void) {}
+
+#endif /* CONFIG_SWIOTLB */
+
+#ifdef CONFIG_USE_OF
+/**
+ * plat_get_fdt() - Return a pointer to the platform's device tree blob
+ *
+ * This function provides a platform independent API to get a pointer to the
+ * flattened device tree blob. The interface between bootloader and kernel
+ * is not consistent across platforms so it is necessary to provide this
+ * API such that common startup code can locate the FDT.
+ *
+ * This is used by the KASLR code to get command line arguments and random
+ * seed from the device tree. Any platform wishing to use KASLR should
+ * provide this API and select SYS_SUPPORTS_RELOCATABLE.
+ *
+ * Return: Pointer to the flattened device tree blob.
+ */
+extern void *plat_get_fdt(void);
+
+#ifdef CONFIG_RELOCATABLE
+
+/**
+ * plat_fdt_relocated() - Update platform's information about relocated dtb
+ *
+ * This function provides a platform-independent API to set platform's
+ * information about relocated DTB if it needs to be moved due to kernel
+ * relocation occurring at boot.
+ */
+void plat_fdt_relocated(void *new_location);
+
+#endif /* CONFIG_RELOCATABLE */
+#endif /* CONFIG_USE_OF */
+
+#endif /* _ASM_BOOTINFO_H */
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
new file mode 100644
index 000000000..fa3dcbf56
--- /dev/null
+++ b/arch/mips/include/asm/branch.h
@@ -0,0 +1,103 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
+ */
+#ifndef _ASM_BRANCH_H
+#define _ASM_BRANCH_H
+
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/inst.h>
+
+extern int __isa_exception_epc(struct pt_regs *regs);
+extern int __compute_return_epc(struct pt_regs *regs);
+extern int __compute_return_epc_for_insn(struct pt_regs *regs,
+                                         union mips_instruction insn);
+extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
+extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
+
+/*
+ * microMIPS bitfields
+ */
+#define MM_POOL32A_MINOR_MASK   0x3f
+#define MM_POOL32A_MINOR_SHIFT  0x6
+#define MM_MIPS32_COND_FC       0x30
+
+int isBranchInstr(struct pt_regs *regs,
+        struct mm_decoded_insn dec_insn, unsigned long *contpc);
+
+extern int __mm_isBranchInstr(struct pt_regs *regs,
+        struct mm_decoded_insn dec_insn, unsigned long *contpc);
+
+static inline int mm_isBranchInstr(struct pt_regs *regs,
+        struct mm_decoded_insn dec_insn, unsigned long *contpc)
+{
+        if (!cpu_has_mmips)
+                return 0;
+
+        return __mm_isBranchInstr(regs, dec_insn, contpc);
+}
+
+static inline int delay_slot(struct pt_regs *regs)
+{
+        return regs->cp0_cause & CAUSEF_BD;
+}
+
+static inline void clear_delay_slot(struct pt_regs *regs)
+{
+        regs->cp0_cause &= ~CAUSEF_BD;
+}
+
+static inline void set_delay_slot(struct pt_regs *regs)
+{
+        regs->cp0_cause |= CAUSEF_BD;
+}
+
+static inline unsigned long exception_epc(struct pt_regs *regs)
+{
+        if (likely(!delay_slot(regs)))
+                return regs->cp0_epc;
+
+        if (get_isa16_mode(regs->cp0_epc))
+                return __isa_exception_epc(regs);
+
+        return regs->cp0_epc + 4;
+}
+
+#define BRANCH_LIKELY_TAKEN 0x0001
+
+static inline int compute_return_epc(struct pt_regs *regs)
+{
+        if (get_isa16_mode(regs->cp0_epc)) {
+                if (cpu_has_mmips)
+                        return __microMIPS_compute_return_epc(regs);
+                if (cpu_has_mips16)
+                        return __MIPS16e_compute_return_epc(regs);
+        } else if (!delay_slot(regs)) {
+                regs->cp0_epc += 4;
+                return 0;
+        }
+
+        return __compute_return_epc(regs);
+}
+
+static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
+                                             union mips16e_instruction *inst)
+{
+        if (likely(!delay_slot(regs))) {
+                if (inst->ri.opcode == MIPS16e_extend_op) {
+                        regs->cp0_epc += 4;
+                        return 0;
+                }
+                regs->cp0_epc += 2;
+                return 0;
+        }
+
+        return __MIPS16e_compute_return_epc(regs);
+}
+
+#endif /* _ASM_BRANCH_H */
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
new file mode 100644
index 000000000..0ef11429a
--- /dev/null
+++ b/arch/mips/include/asm/break.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_BREAK_H
+#define __ASM_BREAK_H
+
+#ifdef __UAPI_ASM_BREAK_H
+#error "Error: Do not directly include <uapi/asm/break.h>"
+#endif
+#include <uapi/asm/break.h>
+
+/*
+ * Break codes used internally to the kernel.
+ */
+#define BRK_KDB         513     /* Used in KDB_ENTER() */
+#define BRK_MEMU        514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP   515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516  /* Kprobe single step software implementation */
+#define BRK_MULOVF      1023    /* Multiply overflow */
+
+#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h
new file mode 100644
index 000000000..745dc160a
--- /dev/null
+++ b/arch/mips/include/asm/bug.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_BUG_H
+#define __ASM_BUG_H
+
+#include <linux/compiler.h>
+#include <asm/sgidefs.h>
+
+#ifdef CONFIG_BUG
+
+#include <asm/break.h>
+
+static inline void __noreturn BUG(void)
+{
+        __asm__ __volatile__("break %0" : : "i" (BRK_BUG));
+        unreachable();
+}
+
+#define HAVE_ARCH_BUG
+
+#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
+
+static inline void  __BUG_ON(unsigned long condition)
+{
+        if (__builtin_constant_p(condition)) {
+                if (condition)
+                        BUG();
+                else
+                        return;
+        }
+        __asm__ __volatile__("tne $0, %0, %1"
+                             : : "r" (condition), "i" (BRK_BUG));
+}
+
+#define BUG_ON(C) __BUG_ON((unsigned long)(C))
+
+#define HAVE_ARCH_BUG_ON
+
+#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
+
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif /* __ASM_BUG_H */
diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h
new file mode 100644
index 000000000..d72dc6e1c
--- /dev/null
+++ b/arch/mips/include/asm/bugs.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Copyright (C) 2007  Maciej W. Rozycki
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+#ifndef _ASM_BUGS_H
+#define _ASM_BUGS_H
+
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+
+extern int daddiu_bug;
+
+extern void check_bugs64_early(void);
+
+extern void check_bugs32(void);
+extern void check_bugs64(void);
+
+static inline void check_bugs_early(void)
+{
+        if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
+                check_bugs64_early();
+}
+
+static inline void check_bugs(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        cpu_data[cpu].udelay_val = loops_per_jiffy;
+        check_bugs32();
+
+        if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
+                check_bugs64();
+}
+
+static inline int r4k_daddiu_bug(void)
+{
+        if (!IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
+                return 0;
+
+        WARN_ON(daddiu_bug < 0);
+        return daddiu_bug != 0;
+}
+
+#endif /* _ASM_BUGS_H */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 000000000..29187e12b
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,19 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <kmalloc.h>
+
+#define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define __read_mostly __section(".data..read_mostly")
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
new file mode 100644
index 000000000..d687b40b9
--- /dev/null
+++ b/arch/mips/include/asm/cacheflush.h
@@ -0,0 +1,153 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHEFLUSH_H
+#define _ASM_CACHEFLUSH_H
+
+/* Keep includes the same across arches.  */
+#include <linux/mm.h>
+#include <asm/cpu-features.h>
+
+/* Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *  - flush_icache_range(start, end) flush a range of instructions
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *
+ * MIPS specific flush operations:
+ *
+ *  - flush_icache_all() flush the entire instruction cache
+ *  - flush_data_cache_page() flushes a page from the data cache
+ *  - __flush_icache_user_range(start, end) flushes range of user instructions
+ */
+
+ /*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty                 PG_arch_1
+
+#define Page_dcache_dirty(page)         \
+        test_bit(PG_dcache_dirty, &(page)->flags)
+#define SetPageDcacheDirty(page)        \
+        set_bit(PG_dcache_dirty, &(page)->flags)
+#define ClearPageDcacheDirty(page)      \
+        clear_bit(PG_dcache_dirty, &(page)->flags)
+
+extern void (*flush_cache_all)(void);
+extern void (*__flush_cache_all)(void);
+extern void (*flush_cache_mm)(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm)  do { (void) (mm); } while (0)
+extern void (*flush_cache_range)(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+extern void __flush_dcache_page(struct page *page);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+static inline void flush_dcache_page(struct page *page)
+{
+        if (cpu_has_dc_aliases)
+                __flush_dcache_page(page);
+        else if (!cpu_has_ic_fills_f_dc)
+                SetPageDcacheDirty(page);
+}
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+extern void __flush_anon_page(struct page *, unsigned long);
+static inline void flush_anon_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vmaddr)
+{
+        if (cpu_has_dc_aliases && PageAnon(page))
+                __flush_anon_page(page, vmaddr);
+}
+
+static inline void flush_icache_page(struct vm_area_struct *vma,
+        struct page *page)
+{
+}
+
+extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*__flush_icache_user_range)(unsigned long start,
+                                         unsigned long end);
+extern void (*__local_flush_icache_user_range)(unsigned long start,
+                                               unsigned long end);
+
+extern void (*__flush_cache_vmap)(void);
+
+static inline void flush_cache_vmap(unsigned long start, unsigned long end)
+{
+        if (cpu_has_dc_aliases)
+                __flush_cache_vmap();
+}
+
+extern void (*__flush_cache_vunmap)(void);
+
+static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
+{
+        if (cpu_has_dc_aliases)
+                __flush_cache_vunmap();
+}
+
+extern void copy_to_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void (*flush_icache_all)(void);
+extern void (*local_flush_data_cache_page)(void * addr);
+extern void (*flush_data_cache_page)(unsigned long addr);
+
+/* Run kernel code uncached, useful for cache probing functions. */
+unsigned long run_uncached(void *func);
+
+extern void *kmap_coherent(struct page *page, unsigned long addr);
+extern void kunmap_coherent(void);
+extern void *kmap_noncoherent(struct page *page, unsigned long addr);
+
+static inline void kunmap_noncoherent(void)
+{
+        kunmap_coherent();
+}
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+        BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
+        flush_dcache_page(page);
+}
+
+/*
+ * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
+ * cache writeback and invalidate operation.
+ */
+extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+
+static inline void flush_kernel_vmap_range(void *vaddr, int size)
+{
+        if (cpu_has_dc_aliases)
+                __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
+{
+        if (cpu_has_dc_aliases)
+                __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
+#endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
new file mode 100644
index 000000000..50253efec
--- /dev/null
+++ b/arch/mips/include/asm/cacheops.h
@@ -0,0 +1,116 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H
+
+/*
+ * Most cache ops are split into a 2 bit field identifying the cache, and a 3
+ * bit field identifying the cache operation.
+ */
+#define CacheOp_Cache                   0x03
+#define CacheOp_Op                      0x1c
+
+#define Cache_I                         0x00
+#define Cache_D                         0x01
+#define Cache_T                         0x02
+#define Cache_V                         0x02 /* Loongson-3 */
+#define Cache_S                         0x03
+
+#define Index_Writeback_Inv             0x00
+#define Index_Load_Tag                  0x04
+#define Index_Store_Tag                 0x08
+#define Hit_Invalidate                  0x10
+#define Hit_Writeback_Inv               0x14    /* not with Cache_I though */
+#define Hit_Writeback                   0x18
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Invalidate_I              (Cache_I | Index_Writeback_Inv)
+#define Index_Writeback_Inv_D           (Cache_D | Index_Writeback_Inv)
+#define Index_Load_Tag_I                (Cache_I | Index_Load_Tag)
+#define Index_Load_Tag_D                (Cache_D | Index_Load_Tag)
+#define Index_Store_Tag_I               (Cache_I | Index_Store_Tag)
+#define Index_Store_Tag_D               (Cache_D | Index_Store_Tag)
+#define Hit_Invalidate_I                (Cache_I | Hit_Invalidate)
+#define Hit_Invalidate_D                (Cache_D | Hit_Invalidate)
+#define Hit_Writeback_Inv_D             (Cache_D | Hit_Writeback_Inv)
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D             (Cache_D | 0x0c)
+#define Fill_I                          (Cache_I | 0x14)
+#define Hit_Writeback_I                 (Cache_I | Hit_Writeback)
+#define Hit_Writeback_D                 (Cache_D | Hit_Writeback)
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Cache_SI                        0x02
+#define Cache_SD                        0x03
+
+#define Index_Invalidate_SI             (Cache_SI | Index_Writeback_Inv)
+#define Index_Writeback_Inv_SD          (Cache_SD | Index_Writeback_Inv)
+#define Index_Load_Tag_SI               (Cache_SI | Index_Load_Tag)
+#define Index_Load_Tag_SD               (Cache_SD | Index_Load_Tag)
+#define Index_Store_Tag_SI              (Cache_SI | Index_Store_Tag)
+#define Index_Store_Tag_SD              (Cache_SD | Index_Store_Tag)
+#define Create_Dirty_Excl_SD            (Cache_SD | 0x0c)
+#define Hit_Invalidate_SI               (Cache_SI | Hit_Invalidate)
+#define Hit_Invalidate_SD               (Cache_SD | Hit_Invalidate)
+#define Hit_Writeback_Inv_SD            (Cache_SD | Hit_Writeback_Inv)
+#define Hit_Writeback_SD                (Cache_SD | Hit_Writeback)
+#define Hit_Set_Virtual_SI              (Cache_SI | 0x1c)
+#define Hit_Set_Virtual_SD              (Cache_SD | 0x1c)
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S           (Cache_S | 0x14)
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T               (Cache_T | 0x14)
+#define Index_Store_Tag_T               (Cache_T | Index_Store_Tag)
+#define Index_Load_Tag_T                (Cache_T | Index_Load_Tag)
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S           (Cache_S | Index_Writeback_Inv)
+#define Index_Load_Tag_S                (Cache_S | Index_Load_Tag)
+#define Index_Store_Tag_S               (Cache_S | Index_Store_Tag)
+#define Hit_Invalidate_S                (Cache_S | Hit_Invalidate)
+#define Cache_Barrier                   0x14
+#define Hit_Writeback_Inv_S             (Cache_S | Hit_Writeback_Inv)
+#define Index_Load_Data_I               (Cache_I | 0x18)
+#define Index_Load_Data_D               (Cache_D | 0x18)
+#define Index_Load_Data_S               (Cache_S | 0x18)
+#define Index_Store_Data_I              (Cache_I | 0x1c)
+#define Index_Store_Data_D              (Cache_D | 0x1c)
+#define Index_Store_Data_S              (Cache_S | 0x1c)
+
+/*
+ * Loongson2-specific cacheops
+ */
+#define Hit_Invalidate_I_Loongson2      (Cache_I | 0x00)
+
+/*
+ * Loongson3-specific cacheops
+ */
+#define Index_Writeback_Inv_V           (Cache_V | Index_Writeback_Inv)
+
+#endif  /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/cdmm.h b/arch/mips/include/asm/cdmm.h
new file mode 100644
index 000000000..c06dbf8ba
--- /dev/null
+++ b/arch/mips/include/asm/cdmm.h
@@ -0,0 +1,109 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef __ASM_CDMM_H
+#define __ASM_CDMM_H
+
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+/**
+ * struct mips_cdmm_device - Represents a single device on a CDMM bus.
+ * @dev:        Driver model device object.
+ * @cpu:        CPU which can access this device.
+ * @res:        MMIO resource.
+ * @type:       Device type identifier.
+ * @rev:        Device revision number.
+ */
+struct mips_cdmm_device {
+        struct device           dev;
+        unsigned int            cpu;
+        struct resource         res;
+        unsigned int            type;
+        unsigned int            rev;
+};
+
+/**
+ * struct mips_cdmm_driver - Represents a driver for a CDMM device.
+ * @drv:        Driver model driver object.
+ * @probe       Callback for probing newly discovered devices.
+ * @remove:     Callback to remove the device.
+ * @shutdown:   Callback on system shutdown.
+ * @cpu_down:   Callback when the parent CPU is going down.
+ *              Any CPU pinned threads/timers should be disabled.
+ * @cpu_up:     Callback when the parent CPU is coming back up again.
+ *              CPU pinned threads/timers can be restarted.
+ * @id_table:   Table for CDMM IDs to match against.
+ */
+struct mips_cdmm_driver {
+        struct device_driver    drv;
+        int                     (*probe)(struct mips_cdmm_device *);
+        int                     (*remove)(struct mips_cdmm_device *);
+        void                    (*shutdown)(struct mips_cdmm_device *);
+        int                     (*cpu_down)(struct mips_cdmm_device *);
+        int                     (*cpu_up)(struct mips_cdmm_device *);
+        const struct mips_cdmm_device_id *id_table;
+};
+
+/**
+ * mips_cdmm_phys_base() - Choose a physical base address for CDMM region.
+ *
+ * Picking a suitable physical address at which to map the CDMM region is
+ * platform specific, so this function can be defined by platform code to
+ * pick a suitable value if none is configured by the bootloader.
+ *
+ * This address must be 32kB aligned, and the region occupies a maximum of 32kB
+ * of physical address space which must not be used for anything else.
+ *
+ * Returns:     Physical base address for CDMM region, or 0 on failure.
+ */
+phys_addr_t mips_cdmm_phys_base(void);
+
+extern struct bus_type mips_cdmm_bustype;
+void __iomem *mips_cdmm_early_probe(unsigned int dev_type);
+
+#define to_mips_cdmm_device(d)  container_of(d, struct mips_cdmm_device, dev)
+
+#define mips_cdmm_get_drvdata(d)        dev_get_drvdata(&d->dev)
+#define mips_cdmm_set_drvdata(d, p)     dev_set_drvdata(&d->dev, p)
+
+int mips_cdmm_driver_register(struct mips_cdmm_driver *);
+void mips_cdmm_driver_unregister(struct mips_cdmm_driver *);
+
+/*
+ * module_mips_cdmm_driver() - Helper macro for drivers that don't do
+ * anything special in module init/exit.  This eliminates a lot of
+ * boilerplate.  Each module may only use this macro once, and
+ * calling it replaces module_init() and module_exit()
+ */
+#define module_mips_cdmm_driver(__mips_cdmm_driver) \
+        module_driver(__mips_cdmm_driver, mips_cdmm_driver_register, \
+                        mips_cdmm_driver_unregister)
+
+/*
+ * builtin_mips_cdmm_driver() - Helper macro for drivers that don't do anything
+ * special in init and have no exit. This eliminates some boilerplate. Each
+ * driver may only use this macro once, and calling it replaces device_initcall
+ * (or in some cases, the legacy __initcall). This is meant to be a direct
+ * parallel of module_mips_cdmm_driver() above but without the __exit stuff that
+ * is not used for builtin cases.
+ */
+#define builtin_mips_cdmm_driver(__mips_cdmm_driver) \
+        builtin_driver(__mips_cdmm_driver, mips_cdmm_driver_register)
+
+/* drivers/tty/mips_ejtag_fdc.c */
+
+#ifdef CONFIG_MIPS_EJTAG_FDC_EARLYCON
+int setup_early_fdc_console(void);
+#else
+static inline int setup_early_fdc_console(void)
+{
+        return -ENODEV;
+}
+#endif
+
+#endif /* __ASM_CDMM_H */
diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h
new file mode 100644
index 000000000..2e13a038d
--- /dev/null
+++ b/arch/mips/include/asm/cevt-r4k.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Kevin D. Kissell
+ */
+
+/*
+ * Definitions used for common event timer implementation
+ * for MIPS 4K-type processors and their MIPS MT variants.
+ * Avoids unsightly extern declarations in C files.
+ */
+#ifndef __ASM_CEVT_R4K_H
+#define __ASM_CEVT_R4K_H
+
+#include <linux/clockchips.h>
+#include <asm/time.h>
+
+DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+
+void mips_event_handler(struct clock_event_device *dev);
+int c0_compare_int_usable(void);
+irqreturn_t c0_compare_interrupt(int, void *);
+
+extern struct irqaction c0_compare_irqaction;
+extern int cp0_timer_irq_installed;
+
+#endif /* __ASM_CEVT_R4K_H */
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
new file mode 100644
index 000000000..5f80c28f5
--- /dev/null
+++ b/arch/mips/include/asm/checksum.h
@@ -0,0 +1,253 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Thiemo Seufer.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef _ASM_CHECKSUM_H
+#define _ASM_CHECKSUM_H
+
+#ifdef CONFIG_GENERIC_CSUM
+#include <asm-generic/checksum.h>
+#else
+
+#include <linux/in6.h>
+
+#include <linux/uaccess.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+__wsum csum_partial(const void *buff, int len, __wsum sum);
+
+__wsum __csum_partial_copy_from_user(const void __user *src, void *dst, int len);
+__wsum __csum_partial_copy_to_user(const void *src, void __user *dst, int len);
+
+#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
+static inline
+__wsum csum_and_copy_from_user(const void __user *src, void *dst, int len)
+{
+        might_fault();
+        if (!access_ok(src, len))
+                return 0;
+        return __csum_partial_copy_from_user(src, dst, len);
+}
+
+/*
+ * Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static inline
+__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len)
+{
+        might_fault();
+        if (!access_ok(dst, len))
+                return 0;
+        return __csum_partial_copy_to_user(src, dst, len);
+}
+
+/*
+ * the same as csum_partial, but copies from user space (but on MIPS
+ * we have just one address space, so this is identical to the above)
+ */
+#define _HAVE_ARCH_CSUM_AND_COPY
+__wsum __csum_partial_copy_nocheck(const void *src, void *dst, int len);
+static inline __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len)
+{
+        return __csum_partial_copy_nocheck(src, dst, len);
+}
+
+/*
+ *      Fold a partial checksum without adding pseudo headers
+ */
+static inline __sum16 csum_fold(__wsum csum)
+{
+        u32 sum = (__force u32)csum;
+
+        sum += (sum << 16);
+        csum = (__force __wsum)(sum < (__force u32)csum);
+        sum >>= 16;
+        sum += (__force u32)csum;
+
+        return (__force __sum16)~sum;
+}
+#define csum_fold csum_fold
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ *      By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
+ *      Arnt Gulbrandsen.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        const unsigned int *word = iph;
+        const unsigned int *stop = word + ihl;
+        unsigned int csum;
+        int carry;
+
+        csum = word[0];
+        csum += word[1];
+        carry = (csum < word[1]);
+        csum += carry;
+
+        csum += word[2];
+        carry = (csum < word[2]);
+        csum += carry;
+
+        csum += word[3];
+        carry = (csum < word[3]);
+        csum += carry;
+
+        word += 4;
+        do {
+                csum += *word;
+                carry = (csum < *word);
+                csum += carry;
+                word++;
+        } while (word != stop);
+
+        return csum_fold(csum);
+}
+#define ip_fast_csum ip_fast_csum
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                        __u32 len, __u8 proto,
+                                        __wsum sum)
+{
+        __asm__(
+        "       .set    push            # csum_tcpudp_nofold\n"
+        "       .set    noat            \n"
+#ifdef CONFIG_32BIT
+        "       addu    %0, %2          \n"
+        "       sltu    $1, %0, %2      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %3          \n"
+        "       sltu    $1, %0, %3      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %4          \n"
+        "       sltu    $1, %0, %4      \n"
+        "       addu    %0, $1          \n"
+#endif
+#ifdef CONFIG_64BIT
+        "       daddu   %0, %2          \n"
+        "       daddu   %0, %3          \n"
+        "       daddu   %0, %4          \n"
+        "       dsll32  $1, %0, 0       \n"
+        "       daddu   %0, $1          \n"
+        "       sltu    $1, %0, $1      \n"
+        "       dsra32  %0, %0, 0       \n"
+        "       addu    %0, $1          \n"
+#endif
+        "       .set    pop"
+        : "=r" (sum)
+        : "0" ((__force unsigned long)daddr),
+          "r" ((__force unsigned long)saddr),
+#ifdef __MIPSEL__
+          "r" ((proto + len) << 8),
+#else
+          "r" (proto + len),
+#endif
+          "r" ((__force unsigned long)sum));
+
+        return sum;
+}
+#define csum_tcpudp_nofold csum_tcpudp_nofold
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                          const struct in6_addr *daddr,
+                                          __u32 len, __u8 proto,
+                                          __wsum sum)
+{
+        __wsum tmp;
+
+        __asm__(
+        "       .set    push            # csum_ipv6_magic\n"
+        "       .set    noreorder       \n"
+        "       .set    noat            \n"
+        "       addu    %0, %5          # proto (long in network byte order)\n"
+        "       sltu    $1, %0, %5      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %6          # csum\n"
+        "       sltu    $1, %0, %6      \n"
+        "       lw      %1, 0(%2)       # four words source address\n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%2)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 0(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%3)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       addu    %0, $1          # Add final carry\n"
+        "       .set    pop"
+        : "=&r" (sum), "=&r" (tmp)
+        : "r" (saddr), "r" (daddr),
+          "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
+
+        return csum_fold(sum);
+}
+
+#include <asm-generic/checksum.h>
+#endif /* CONFIG_GENERIC_CSUM */
+
+#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/mips/include/asm/clocksource.h b/arch/mips/include/asm/clocksource.h
new file mode 100644
index 000000000..2f1ebbea3
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ */
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include <asm/vdso/clocksource.h>
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/cmp.h b/arch/mips/include/asm/cmp.h
new file mode 100644
index 000000000..e9e87504b
--- /dev/null
+++ b/arch/mips/include/asm/cmp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_CMP_H
+#define _ASM_CMP_H
+
+/*
+ * Definitions for CMP multitasking on MIPS cores
+ */
+struct task_struct;
+
+extern void cmp_smp_setup(void);
+extern void cmp_smp_finish(void);
+extern void cmp_boot_secondary(int cpu, struct task_struct *t);
+extern void cmp_init_secondary(void);
+extern void cmp_prepare_cpus(unsigned int max_cpus);
+
+/* This is platform specific */
+extern void cmp_send_ipi(int cpu, unsigned int action);
+#endif /*  _ASM_CMP_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
new file mode 100644
index 000000000..3e9c41f69
--- /dev/null
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -0,0 +1,327 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <linux/bug.h>
+#include <linux/irqflags.h>
+#include <asm/compiler.h>
+#include <asm/llsc.h>
+#include <asm/sync.h>
+#include <asm/war.h>
+
+/*
+ * These functions doesn't exist, so if they are called you'll either:
+ *
+ * - Get an error at compile-time due to __compiletime_error, if supported by
+ *   your compiler.
+ *
+ * or:
+ *
+ * - Get an error at link-time due to the call to the missing function.
+ */
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
+        __compiletime_error("Bad argument size for cmpxchg");
+extern unsigned long __cmpxchg64_unsupported(void)
+        __compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false");
+extern unsigned long __xchg_called_with_bad_pointer(void)
+        __compiletime_error("Bad argument size for xchg");
+
+#define __xchg_asm(ld, st, m, val)                                      \
+({                                                                      \
+        __typeof(*(m)) __ret;                                           \
+                                                                        \
+        if (kernel_uses_llsc) {                                         \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    push                            \n"     \
+                "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"     \
+                "       " __SYNC(full, loongson3_war) "         \n"     \
+                "1:     " ld "  %0, %2          # __xchg_asm    \n"     \
+                "       .set    pop                             \n"     \
+                "       move    $1, %z3                         \n"     \
+                "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"     \
+                "       " st "  $1, %1                          \n"     \
+                "\t" __SC_BEQZ  "$1, 1b                         \n"     \
+                "       .set    pop                             \n"     \
+                : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)           \
+                : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)                  \
+                : __LLSC_CLOBBER);                                      \
+        } else {                                                        \
+                unsigned long __flags;                                  \
+                                                                        \
+                raw_local_irq_save(__flags);                            \
+                __ret = *m;                                             \
+                *m = val;                                               \
+                raw_local_irq_restore(__flags);                         \
+        }                                                               \
+                                                                        \
+        __ret;                                                          \
+})
+
+extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
+                                  unsigned int size);
+
+static __always_inline
+unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
+{
+        switch (size) {
+        case 1:
+        case 2:
+                return __xchg_small(ptr, x, size);
+
+        case 4:
+                return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
+
+        case 8:
+                if (!IS_ENABLED(CONFIG_64BIT))
+                        return __xchg_called_with_bad_pointer();
+
+                return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x);
+
+        default:
+                return __xchg_called_with_bad_pointer();
+        }
+}
+
+#define xchg(ptr, x)                                                    \
+({                                                                      \
+        __typeof__(*(ptr)) __res;                                       \
+                                                                        \
+        /*                                                              \
+         * In the Loongson3 workaround case __xchg_asm() already        \
+         * contains a completion barrier prior to the LL, so we don't   \
+         * need to emit an extra one here.                              \
+         */                                                             \
+        if (__SYNC_loongson3_war == 0)                                  \
+                smp_mb__before_llsc();                                  \
+                                                                        \
+        __res = (__typeof__(*(ptr)))                                    \
+                __xchg((ptr), (unsigned long)(x), sizeof(*(ptr)));      \
+                                                                        \
+        smp_llsc_mb();                                                  \
+                                                                        \
+        __res;                                                          \
+})
+
+#define __cmpxchg_asm(ld, st, m, old, new)                              \
+({                                                                      \
+        __typeof(*(m)) __ret;                                           \
+                                                                        \
+        if (kernel_uses_llsc) {                                         \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    push                            \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
+                "       " __SYNC(full, loongson3_war) "         \n"     \
+                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
+                "       bne     %0, %z3, 2f                     \n"     \
+                "       .set    pop                             \n"     \
+                "       move    $1, %z4                         \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
+                "       " st "  $1, %1                          \n"     \
+                "\t" __SC_BEQZ  "$1, 1b                         \n"     \
+                "       .set    pop                             \n"     \
+                "2:     " __SYNC(full, loongson3_war) "         \n"     \
+                : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)           \
+                : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new)      \
+                : __LLSC_CLOBBER);                                      \
+        } else {                                                        \
+                unsigned long __flags;                                  \
+                                                                        \
+                raw_local_irq_save(__flags);                            \
+                __ret = *m;                                             \
+                if (__ret == old)                                       \
+                        *m = new;                                       \
+                raw_local_irq_restore(__flags);                         \
+        }                                                               \
+                                                                        \
+        __ret;                                                          \
+})
+
+extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
+                                     unsigned long new, unsigned int size);
+
+static __always_inline
+unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                        unsigned long new, unsigned int size)
+{
+        switch (size) {
+        case 1:
+        case 2:
+                return __cmpxchg_small(ptr, old, new, size);
+
+        case 4:
+                return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr,
+                                     (u32)old, new);
+
+        case 8:
+                /* lld/scd are only available for MIPS64 */
+                if (!IS_ENABLED(CONFIG_64BIT))
+                        return __cmpxchg_called_with_bad_pointer();
+
+                return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr,
+                                     (u64)old, new);
+
+        default:
+                return __cmpxchg_called_with_bad_pointer();
+        }
+}
+
+#define cmpxchg_local(ptr, old, new)                                    \
+        ((__typeof__(*(ptr)))                                           \
+                __cmpxchg((ptr),                                        \
+                          (unsigned long)(__typeof__(*(ptr)))(old),     \
+                          (unsigned long)(__typeof__(*(ptr)))(new),     \
+                          sizeof(*(ptr))))
+
+#define cmpxchg(ptr, old, new)                                          \
+({                                                                      \
+        __typeof__(*(ptr)) __res;                                       \
+                                                                        \
+        /*                                                              \
+         * In the Loongson3 workaround case __cmpxchg_asm() already     \
+         * contains a completion barrier prior to the LL, so we don't   \
+         * need to emit an extra one here.                              \
+         */                                                             \
+        if (__SYNC_loongson3_war == 0)                                  \
+                smp_mb__before_llsc();                                  \
+                                                                        \
+        __res = cmpxchg_local((ptr), (old), (new));                     \
+                                                                        \
+        /*                                                              \
+         * In the Loongson3 workaround case __cmpxchg_asm() already     \
+         * contains a completion barrier after the SC, so we don't      \
+         * need to emit an extra one here.                              \
+         */                                                             \
+        if (__SYNC_loongson3_war == 0)                                  \
+                smp_llsc_mb();                                          \
+                                                                        \
+        __res;                                                          \
+})
+
+#ifdef CONFIG_64BIT
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+
+#define cmpxchg64(ptr, o, n)                                            \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg((ptr), (o), (n));                                       \
+  })
+#else
+
+# include <asm-generic/cmpxchg-local.h>
+# define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+# ifdef CONFIG_SMP
+
+static inline unsigned long __cmpxchg64(volatile void *ptr,
+                                        unsigned long long old,
+                                        unsigned long long new)
+{
+        unsigned long long tmp, ret;
+        unsigned long flags;
+
+        /*
+         * The assembly below has to combine 32 bit values into a 64 bit
+         * register, and split 64 bit values from one register into two. If we
+         * were to take an interrupt in the middle of this we'd only save the
+         * least significant 32 bits of each register & probably clobber the
+         * most significant 32 bits of the 64 bit values we're using. In order
+         * to avoid this we must disable interrupts.
+         */
+        local_irq_save(flags);
+
+        asm volatile(
+        "       .set    push                            \n"
+        "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"
+        /* Load 64 bits from ptr */
+        "       " __SYNC(full, loongson3_war) "         \n"
+        "1:     lld     %L0, %3         # __cmpxchg64   \n"
+        "       .set    pop                             \n"
+        /*
+         * Split the 64 bit value we loaded into the 2 registers that hold the
+         * ret variable.
+         */
+        "       dsra    %M0, %L0, 32                    \n"
+        "       sll     %L0, %L0, 0                     \n"
+        /*
+         * Compare ret against old, breaking out of the loop if they don't
+         * match.
+         */
+        "       bne     %M0, %M4, 2f                    \n"
+        "       bne     %L0, %L4, 2f                    \n"
+        /*
+         * Combine the 32 bit halves from the 2 registers that hold the new
+         * variable into a single 64 bit register.
+         */
+#  if MIPS_ISA_REV >= 2
+        "       move    %L1, %L5                        \n"
+        "       dins    %L1, %M5, 32, 32                \n"
+#  else
+        "       dsll    %L1, %L5, 32                    \n"
+        "       dsrl    %L1, %L1, 32                    \n"
+        "       .set    noat                            \n"
+        "       dsll    $at, %M5, 32                    \n"
+        "       or      %L1, %L1, $at                   \n"
+        "       .set    at                              \n"
+#  endif
+        "       .set    push                            \n"
+        "       .set    " MIPS_ISA_ARCH_LEVEL "         \n"
+        /* Attempt to store new at ptr */
+        "       scd     %L1, %2                         \n"
+        /* If we failed, loop! */
+        "\t" __SC_BEQZ "%L1, 1b                         \n"
+        "2:     " __SYNC(full, loongson3_war) "         \n"
+        "       .set    pop                             \n"
+        : "=&r"(ret),
+          "=&r"(tmp),
+          "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)
+        : GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr),
+          "r" (old),
+          "r" (new)
+        : "memory");
+
+        local_irq_restore(flags);
+        return ret;
+}
+
+#  define cmpxchg64(ptr, o, n) ({                                       \
+        unsigned long long __old = (__typeof__(*(ptr)))(o);             \
+        unsigned long long __new = (__typeof__(*(ptr)))(n);             \
+        __typeof__(*(ptr)) __res;                                       \
+                                                                        \
+        /*                                                              \
+         * We can only use cmpxchg64 if we know that the CPU supports   \
+         * 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported  \
+         * will cause a build error unless cpu_has_64bits is a          \
+         * compile-time constant 1.                                     \
+         */                                                             \
+        if (cpu_has_64bits && kernel_uses_llsc) {                       \
+                smp_mb__before_llsc();                                  \
+                __res = __cmpxchg64((ptr), __old, __new);               \
+                smp_llsc_mb();                                          \
+        } else {                                                        \
+                __res = __cmpxchg64_unsupported();                      \
+        }                                                               \
+                                                                        \
+        __res;                                                          \
+})
+
+# else /* !CONFIG_SMP */
+#  define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
+# endif /* !CONFIG_SMP */
+#endif /* !CONFIG_64BIT */
+
+#endif /* __ASM_CMPXCHG_H */
diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h
new file mode 100644
index 000000000..c3b7a2550
--- /dev/null
+++ b/arch/mips/include/asm/compat-signal.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_COMPAT_SIGNAL_H
+#define __ASM_COMPAT_SIGNAL_H
+
+#include <linux/bug.h>
+#include <linux/compat.h>
+#include <linux/compiler.h>
+
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+
+#include <linux/uaccess.h>
+
+static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
+        const sigset_t *s)
+{
+        BUILD_BUG_ON(sizeof(*d) != sizeof(*s));
+        BUILD_BUG_ON(_NSIG_WORDS != 2);
+
+        return put_compat_sigset(d, s, sizeof(*d));
+}
+
+static inline int __copy_conv_sigset_from_user(sigset_t *d,
+        const compat_sigset_t __user *s)
+{
+        return get_compat_sigset(d, s);
+}
+
+#endif /* __ASM_COMPAT_SIGNAL_H */
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
new file mode 100644
index 000000000..65975712a
--- /dev/null
+++ b/arch/mips/include/asm/compat.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_COMPAT_H
+#define _ASM_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/thread_info.h>
+#include <linux/types.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+
+#include <asm-generic/compat.h>
+
+#define COMPAT_USER_HZ          100
+#define COMPAT_UTS_MACHINE      "mips\0\0\0"
+
+typedef s32             __compat_uid_t;
+typedef s32             __compat_gid_t;
+typedef __compat_uid_t  __compat_uid32_t;
+typedef __compat_gid_t  __compat_gid32_t;
+typedef u32             compat_mode_t;
+typedef u32             compat_dev_t;
+typedef u32             compat_nlink_t;
+typedef s32             compat_ipc_pid_t;
+typedef s32             compat_caddr_t;
+typedef struct {
+        s32     val[2];
+} compat_fsid_t;
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        s32             st_pad1[3];
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
+        compat_dev_t    st_rdev;
+        s32             st_pad2[2];
+        compat_off_t    st_size;
+        s32             st_pad3;
+        old_time32_t    st_atime;
+        s32             st_atime_nsec;
+        old_time32_t    st_mtime;
+        s32             st_mtime_nsec;
+        old_time32_t    st_ctime;
+        s32             st_ctime_nsec;
+        s32             st_blksize;
+        s32             st_blocks;
+        s32             st_pad4[14];
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        s32             l_sysid;
+        compat_pid_t    l_pid;
+        s32             pad[4];
+};
+
+#define F_GETLK64       33
+#define F_SETLK64       34
+#define F_SETLKW64      35
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+};
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_frsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_files;
+        int             f_ffree;
+        int             f_bavail;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;
+        int             f_flags;
+        int             f_spare[5];
+};
+
+#define COMPAT_RLIM_INFINITY    0x7fffffffUL
+
+typedef u32             compat_old_sigset_t;    /* at least 32 bits */
+
+#define _COMPAT_NSIG            128             /* Don't ask !$@#% ...  */
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+
+static inline void __user *arch_compat_alloc_user_space(long len)
+{
+        struct pt_regs *regs = (struct pt_regs *)
+                ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
+
+        return (void __user *) (regs->regs[29] - len);
+}
+
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        compat_mode_t mode;
+        unsigned short seq;
+        unsigned short __pad2;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        compat_ulong_t  sem_otime;
+        compat_ulong_t  sem_ctime;
+        compat_ulong_t  sem_nsems;
+        compat_ulong_t  sem_otime_high;
+        compat_ulong_t  sem_ctime_high;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_stime_high;
+#endif
+        compat_ulong_t  msg_stime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_stime_high;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_rtime_high;
+#endif
+        compat_ulong_t  msg_rtime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_rtime_high;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_ctime_high;
+#endif
+        compat_ulong_t  msg_ctime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  msg_ctime_high;
+#endif
+        compat_ulong_t  msg_cbytes;
+        compat_ulong_t  msg_qnum;
+        compat_ulong_t  msg_qbytes;
+        compat_pid_t    msg_lspid;
+        compat_pid_t    msg_lrpid;
+        compat_ulong_t  __unused4;
+        compat_ulong_t  __unused5;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        compat_size_t   shm_segsz;
+        compat_ulong_t  shm_atime;
+        compat_ulong_t  shm_dtime;
+        compat_ulong_t  shm_ctime;
+        compat_pid_t    shm_cpid;
+        compat_pid_t    shm_lpid;
+        compat_ulong_t  shm_nattch;
+        compat_ushort_t shm_atime_high;
+        compat_ushort_t shm_dtime_high;
+        compat_ushort_t shm_ctime_high;
+        compat_ushort_t __unused2;
+};
+
+/* MIPS has unusual order of fields in stack_t */
+typedef struct compat_sigaltstack {
+        compat_uptr_t                   ss_sp;
+        compat_size_t                   ss_size;
+        int                             ss_flags;
+} compat_stack_t;
+#define compat_sigaltstack compat_sigaltstack
+
+static inline int is_compat_task(void)
+{
+        return test_thread_flag(TIF_32BIT_ADDR);
+}
+
+#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
new file mode 100644
index 000000000..a2cb2d2b1
--- /dev/null
+++ b/arch/mips/include/asm/compiler.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004, 2007  Maciej W. Rozycki
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_COMPILER_H
+#define _ASM_COMPILER_H
+
+/*
+ * With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
+ * compiler that a particular code path will never be hit. This allows it to be
+ * optimised out of the generated binary.
+ *
+ * Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
+ * that can lead to instructions from beyond an unreachable statement being
+ * incorrectly reordered into earlier delay slots if the unreachable statement
+ * is the only content of a case in a switch statement. This can lead to
+ * seemingly random behaviour, such as invalid memory accesses from incorrectly
+ * reordered loads or stores. See this potential GCC fix for details:
+ *
+ *   https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
+ *
+ * It is unclear whether GCC 8 onwards suffer from the same issue - nothing
+ * relevant is mentioned in GCC 8 release notes and nothing obviously relevant
+ * stands out in GCC commit logs, but these newer GCC versions generate very
+ * different code for the testcase which doesn't exhibit the bug.
+ *
+ * GCC also handles stack allocation suboptimally when calling noreturn
+ * functions or calling __builtin_unreachable():
+ *
+ *   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
+ *
+ * We work around both of these issues by placing a volatile asm statement,
+ * which GCC is prevented from reordering past, prior to __builtin_unreachable
+ * calls.
+ *
+ * The .insn statement is required to ensure that any branches to the
+ * statement, which sadly must be kept due to the asm statement, are known to
+ * be branches to code and satisfy linker requirements for microMIPS kernels.
+ */
+#undef barrier_before_unreachable
+#define barrier_before_unreachable() asm volatile(".insn")
+
+#if !defined(CONFIG_CC_IS_GCC) || \
+    (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
+# define GCC_OFF_SMALL_ASM() "ZC"
+#elif defined(CONFIG_CPU_MICROMIPS)
+# error "microMIPS compilation unsupported with GCC older than 4.9"
+#else
+# define GCC_OFF_SMALL_ASM() "R"
+#endif
+
+#ifdef CONFIG_CPU_MIPSR6
+#define MIPS_ISA_LEVEL "mips64r6"
+#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
+#define MIPS_ISA_LEVEL_RAW mips64r6
+#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
+#elif defined(CONFIG_CPU_MIPSR5)
+#define MIPS_ISA_LEVEL "mips64r5"
+#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
+#define MIPS_ISA_LEVEL_RAW mips64r5
+#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
+#else
+/* MIPS64 is a superset of MIPS32 */
+#define MIPS_ISA_LEVEL "mips64r2"
+#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
+#define MIPS_ISA_LEVEL_RAW mips64r2
+#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
+#endif /* CONFIG_CPU_MIPSR6 */
+
+#endif /* _ASM_COMPILER_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000..6b7396a6a
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_COP2_H
+#define __ASM_COP2_H
+
+#include <linux/notifier.h>
+
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
+
+extern void octeon_cop2_save(struct octeon_cop2_state *);
+extern void octeon_cop2_restore(struct octeon_cop2_state *);
+
+#define cop2_save(r)            octeon_cop2_save(&(r)->thread.cp2)
+#define cop2_restore(r)         octeon_cop2_restore(&(r)->thread.cp2)
+
+#define cop2_present            1
+#define cop2_lazy_restore       1
+
+#elif defined(CONFIG_CPU_XLP)
+
+extern void nlm_cop2_save(struct nlm_cop2_state *);
+extern void nlm_cop2_restore(struct nlm_cop2_state *);
+
+#define cop2_save(r)            nlm_cop2_save(&(r)->thread.cp2)
+#define cop2_restore(r)         nlm_cop2_restore(&(r)->thread.cp2)
+
+#define cop2_present            1
+#define cop2_lazy_restore       0
+
+#elif defined(CONFIG_CPU_LOONGSON64)
+
+#define cop2_present            1
+#define cop2_lazy_restore       1
+#define cop2_save(r)            do { (void)(r); } while (0)
+#define cop2_restore(r)         do { (void)(r); } while (0)
+
+#else
+
+#define cop2_present            0
+#define cop2_lazy_restore       0
+#define cop2_save(r)            do { (void)(r); } while (0)
+#define cop2_restore(r)         do { (void)(r); } while (0)
+#endif
+
+enum cu2_ops {
+        CU2_EXCEPTION,
+        CU2_LWC2_OP,
+        CU2_LDC2_OP,
+        CU2_SWC2_OP,
+        CU2_SDC2_OP,
+};
+
+extern int register_cu2_notifier(struct notifier_block *nb);
+extern int cu2_notifier_call_chain(unsigned long val, void *v);
+
+#define cu2_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_cu2_notifier(&fn##_nb);                                \
+})
+
+#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 000000000..8294eaa6f
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,739 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <asm/isa-rev.h>
+#include <cpu-feature-overrides.h>
+
+#define __ase(ase)                      (cpu_data[0].ases & (ase))
+#define __isa(isa)                      (cpu_data[0].isa_level & (isa))
+#define __opt(opt)                      (cpu_data[0].options & (opt))
+
+/*
+ * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
+ * boot (typically by cpu_probe()).
+ *
+ * Note that these should only be used in cases where a kernel built for an
+ * older ISA *cannot* run on a CPU which supports the feature in question. For
+ * example this may be used for features introduced with MIPSr6, since a kernel
+ * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
+ * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
+ * MIPSr2 CPU.
+ */
+#define __isa_ge_and_ase(isa, ase)      ((MIPS_ISA_REV >= (isa)) && __ase(ase))
+#define __isa_ge_and_opt(isa, opt)      ((MIPS_ISA_REV >= (isa)) && __opt(opt))
+
+/*
+ * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
+ * boot (typically by cpu_probe()).
+ *
+ * These are for use with features that are optional up until a particular ISA
+ * revision & then become required.
+ */
+#define __isa_ge_or_ase(isa, ase)       ((MIPS_ISA_REV >= (isa)) || __ase(ase))
+#define __isa_ge_or_opt(isa, opt)       ((MIPS_ISA_REV >= (isa)) || __opt(opt))
+
+/*
+ * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
+ * boot (typically by cpu_probe()).
+ *
+ * These are for use with features that are optional up until a particular ISA
+ * revision & are then removed - ie. no longer present in any CPU implementing
+ * the given ISA revision.
+ */
+#define __isa_lt_and_ase(isa, ase)      ((MIPS_ISA_REV < (isa)) && __ase(ase))
+#define __isa_lt_and_opt(isa, opt)      ((MIPS_ISA_REV < (isa)) && __opt(opt))
+
+/*
+ * Similarly allow for ISA level checks that take into account knowledge of the
+ * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
+ */
+#define __isa_ge_and_flag(isa, flag)    ((MIPS_ISA_REV >= (isa)) && __isa(flag))
+#define __isa_ge_or_flag(isa, flag)     ((MIPS_ISA_REV >= (isa)) || __isa(flag))
+#define __isa_lt_and_flag(isa, flag)    ((MIPS_ISA_REV < (isa)) && __isa(flag))
+#define __isa_range(ge, lt) \
+        ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
+#define __isa_range_or_flag(ge, lt, flag) \
+        (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
+#define __isa_range_and_ase(ge, lt, ase) \
+        (__isa_range(ge, lt) && __ase(ase))
+
+/*
+ * SMP assumption: Options of CPU 0 are a superset of all processors.
+ * This is true for all known MIPS systems.
+ */
+#ifndef cpu_has_tlb
+#define cpu_has_tlb             __opt(MIPS_CPU_TLB)
+#endif
+#ifndef cpu_has_ftlb
+#define cpu_has_ftlb            __opt(MIPS_CPU_FTLB)
+#endif
+#ifndef cpu_has_tlbinv
+#define cpu_has_tlbinv          __opt(MIPS_CPU_TLBINV)
+#endif
+#ifndef cpu_has_segments
+#define cpu_has_segments        __opt(MIPS_CPU_SEGMENTS)
+#endif
+#ifndef cpu_has_eva
+#define cpu_has_eva             __opt(MIPS_CPU_EVA)
+#endif
+#ifndef cpu_has_htw
+#define cpu_has_htw             __opt(MIPS_CPU_HTW)
+#endif
+#ifndef cpu_has_ldpte
+#define cpu_has_ldpte           __opt(MIPS_CPU_LDPTE)
+#endif
+#ifndef cpu_has_rixiex
+#define cpu_has_rixiex          __isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
+#endif
+#ifndef cpu_has_maar
+#define cpu_has_maar            __opt(MIPS_CPU_MAAR)
+#endif
+#ifndef cpu_has_rw_llb
+#define cpu_has_rw_llb          __isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
+#endif
+
+/*
+ * For the moment we don't consider R6000 and R8000 so we can assume that
+ * anything that doesn't support R4000-style exceptions and interrupts is
+ * R3000-like.  Users should still treat these two macro definitions as
+ * opaque.
+ */
+#ifndef cpu_has_3kex
+#define cpu_has_3kex            (!cpu_has_4kex)
+#endif
+#ifndef cpu_has_4kex
+#define cpu_has_4kex            __isa_ge_or_opt(1, MIPS_CPU_4KEX)
+#endif
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache        __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache        0
+#define cpu_has_8k_cache        0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache        __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache      __opt(MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_octeon_cache
+#define cpu_has_octeon_cache    0
+#endif
+/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
+#ifndef cpu_has_fpu
+# ifdef CONFIG_MIPS_FP_SUPPORT
+#  define cpu_has_fpu           (current_cpu_data.options & MIPS_CPU_FPU)
+#  define raw_cpu_has_fpu       (raw_current_cpu_data.options & MIPS_CPU_FPU)
+# else
+#  define cpu_has_fpu           0
+#  define raw_cpu_has_fpu       0
+# endif
+#else
+# define raw_cpu_has_fpu        cpu_has_fpu
+#endif
+#ifndef cpu_has_32fpr
+#define cpu_has_32fpr           __isa_ge_or_opt(1, MIPS_CPU_32FPR)
+#endif
+#ifndef cpu_has_counter
+#define cpu_has_counter         __opt(MIPS_CPU_COUNTER)
+#endif
+#ifndef cpu_has_watch
+#define cpu_has_watch           __opt(MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_has_divec
+#define cpu_has_divec           __isa_ge_or_opt(1, MIPS_CPU_DIVEC)
+#endif
+#ifndef cpu_has_vce
+#define cpu_has_vce             __opt(MIPS_CPU_VCE)
+#endif
+#ifndef cpu_has_cache_cdex_p
+#define cpu_has_cache_cdex_p    __opt(MIPS_CPU_CACHE_CDEX_P)
+#endif
+#ifndef cpu_has_cache_cdex_s
+#define cpu_has_cache_cdex_s    __opt(MIPS_CPU_CACHE_CDEX_S)
+#endif
+#ifndef cpu_has_prefetch
+#define cpu_has_prefetch        __isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
+#endif
+#ifndef cpu_has_mcheck
+#define cpu_has_mcheck          __isa_ge_or_opt(1, MIPS_CPU_MCHECK)
+#endif
+#ifndef cpu_has_ejtag
+#define cpu_has_ejtag           __opt(MIPS_CPU_EJTAG)
+#endif
+#ifndef cpu_has_llsc
+#define cpu_has_llsc            __isa_ge_or_opt(1, MIPS_CPU_LLSC)
+#endif
+#ifndef kernel_uses_llsc
+#define kernel_uses_llsc        cpu_has_llsc
+#endif
+#ifndef cpu_has_guestctl0ext
+#define cpu_has_guestctl0ext    __opt(MIPS_CPU_GUESTCTL0EXT)
+#endif
+#ifndef cpu_has_guestctl1
+#define cpu_has_guestctl1       __opt(MIPS_CPU_GUESTCTL1)
+#endif
+#ifndef cpu_has_guestctl2
+#define cpu_has_guestctl2       __opt(MIPS_CPU_GUESTCTL2)
+#endif
+#ifndef cpu_has_guestid
+#define cpu_has_guestid         __opt(MIPS_CPU_GUESTID)
+#endif
+#ifndef cpu_has_drg
+#define cpu_has_drg             __opt(MIPS_CPU_DRG)
+#endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16          __isa_lt_and_ase(6, MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mips16e2
+#define cpu_has_mips16e2        __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx            __isa_lt_and_ase(6, MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d          __isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips       __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
+#endif
+
+#ifndef cpu_has_rixi
+#define cpu_has_rixi            __isa_ge_or_opt(6, MIPS_CPU_RIXI)
+#endif
+
+#ifndef cpu_has_mmips
+# if defined(__mips_micromips)
+#  define cpu_has_mmips         1
+# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#  define cpu_has_mmips         __opt(MIPS_CPU_MICROMIPS)
+# else
+#  define cpu_has_mmips         0
+# endif
+#endif
+
+#ifndef cpu_has_lpa
+#define cpu_has_lpa             __opt(MIPS_CPU_LPA)
+#endif
+#ifndef cpu_has_mvh
+#define cpu_has_mvh             __opt(MIPS_CPU_MVH)
+#endif
+#ifndef cpu_has_xpa
+#define cpu_has_xpa             (cpu_has_lpa && cpu_has_mvh)
+#endif
+#ifndef cpu_has_vtag_icache
+#define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
+#endif
+#ifndef cpu_has_dc_aliases
+#define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
+#endif
+#ifndef cpu_has_ic_fills_f_dc
+#define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+#ifndef cpu_has_pindexed_dcache
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#endif
+
+/*
+ * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
+ * such as the R10000 have I-Caches that snoop local stores; the embedded ones
+ * don't.  For maintaining I-cache coherency this means we need to flush the
+ * D-cache all the way back to whever the I-cache does refills from, so the
+ * I-cache has a chance to see the new data at all.  Then we have to flush the
+ * I-cache also.
+ * Note we may have been rescheduled and may no longer be running on the CPU
+ * that did the store so we can't optimize this into only doing the flush on
+ * the local CPU.
+ */
+#ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
+#define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
+#else
+#define cpu_icache_snoops_remote_store  1
+#endif
+#endif
+
+#ifndef cpu_has_mips_1
+# define cpu_has_mips_1         (MIPS_ISA_REV < 6)
+#endif
+#ifndef cpu_has_mips_2
+# define cpu_has_mips_2         __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
+#endif
+#ifndef cpu_has_mips_3
+# define cpu_has_mips_3         __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
+#endif
+#ifndef cpu_has_mips_4
+# define cpu_has_mips_4         __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
+#endif
+#ifndef cpu_has_mips_5
+# define cpu_has_mips_5         __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
+#endif
+#ifndef cpu_has_mips32r1
+# define cpu_has_mips32r1       __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
+#endif
+#ifndef cpu_has_mips32r2
+# define cpu_has_mips32r2       __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
+#endif
+#ifndef cpu_has_mips32r5
+# define cpu_has_mips32r5       __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
+#endif
+#ifndef cpu_has_mips32r6
+# define cpu_has_mips32r6       __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
+#endif
+#ifndef cpu_has_mips64r1
+# define cpu_has_mips64r1       (cpu_has_64bits && \
+                                 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
+#endif
+#ifndef cpu_has_mips64r2
+# define cpu_has_mips64r2       (cpu_has_64bits && \
+                                 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
+#endif
+#ifndef cpu_has_mips64r5
+# define cpu_has_mips64r5       (cpu_has_64bits && \
+                                 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
+#endif
+#ifndef cpu_has_mips64r6
+# define cpu_has_mips64r6       __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
+#endif
+
+/*
+ * Shortcuts ...
+ */
+#define cpu_has_mips_2_3_4_5    (cpu_has_mips_2 | cpu_has_mips_3_4_5)
+#define cpu_has_mips_3_4_5      (cpu_has_mips_3 | cpu_has_mips_4_5)
+#define cpu_has_mips_4_5        (cpu_has_mips_4 | cpu_has_mips_5)
+
+#define cpu_has_mips_2_3_4_5_r  (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
+#define cpu_has_mips_3_4_5_r    (cpu_has_mips_3 | cpu_has_mips_4_5_r)
+#define cpu_has_mips_4_5_r      (cpu_has_mips_4 | cpu_has_mips_5_r)
+#define cpu_has_mips_5_r        (cpu_has_mips_5 | cpu_has_mips_r)
+
+#define cpu_has_mips_3_4_5_64_r2_r6                                     \
+                                (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
+#define cpu_has_mips_4_5_64_r2_r6                                       \
+                                (cpu_has_mips_4_5 | cpu_has_mips64r1 |  \
+                                 cpu_has_mips_r2 | cpu_has_mips_r5 | \
+                                 cpu_has_mips_r6)
+
+#define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
+                         cpu_has_mips32r5 | cpu_has_mips32r6)
+#define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | \
+                         cpu_has_mips64r5 | cpu_has_mips64r6)
+#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
+#define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5)
+#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
+#define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
+                         cpu_has_mips32r5 | cpu_has_mips32r6 | \
+                         cpu_has_mips64r1 | cpu_has_mips64r2 | \
+                         cpu_has_mips64r5 | cpu_has_mips64r6)
+
+/* MIPSR2 - MIPSR6 have a lot of similarities */
+#define cpu_has_mips_r2_r6      (cpu_has_mips_r2 | cpu_has_mips_r5 | \
+                                 cpu_has_mips_r6)
+
+/*
+ * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
+ *
+ * Returns non-zero value if the current processor implementation requires
+ * an IHB instruction to deal with an instruction hazard as per MIPS R2
+ * architecture specification, zero otherwise.
+ */
+#ifndef cpu_has_mips_r2_exec_hazard
+#define cpu_has_mips_r2_exec_hazard                                     \
+({                                                                      \
+        int __res;                                                      \
+                                                                        \
+        switch (current_cpu_type()) {                                   \
+        case CPU_M14KC:                                                 \
+        case CPU_74K:                                                   \
+        case CPU_1074K:                                                 \
+        case CPU_PROAPTIV:                                              \
+        case CPU_P5600:                                                 \
+        case CPU_M5150:                                                 \
+        case CPU_QEMU_GENERIC:                                          \
+        case CPU_CAVIUM_OCTEON:                                         \
+        case CPU_CAVIUM_OCTEON_PLUS:                                    \
+        case CPU_CAVIUM_OCTEON2:                                        \
+        case CPU_CAVIUM_OCTEON3:                                        \
+                __res = 0;                                              \
+                break;                                                  \
+                                                                        \
+        default:                                                        \
+                __res = 1;                                              \
+        }                                                               \
+                                                                        \
+        __res;                                                          \
+})
+#endif
+
+/*
+ * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
+ * pre-MIPS32/MIPS64 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
+ * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
+ */
+#ifndef cpu_has_clo_clz
+#define cpu_has_clo_clz cpu_has_mips_r
+#endif
+
+/*
+ * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
+ * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
+ * This indicates the availability of WSBH and in case of 64 bit CPUs also
+ * DSBH and DSHD.
+ */
+#ifndef cpu_has_wsbh
+#define cpu_has_wsbh            cpu_has_mips_r2
+#endif
+
+#ifndef cpu_has_dsp
+#define cpu_has_dsp             __ase(MIPS_ASE_DSP)
+#endif
+
+#ifndef cpu_has_dsp2
+#define cpu_has_dsp2            __ase(MIPS_ASE_DSP2P)
+#endif
+
+#ifndef cpu_has_dsp3
+#define cpu_has_dsp3            __ase(MIPS_ASE_DSP3)
+#endif
+
+#ifndef cpu_has_loongson_mmi
+#define cpu_has_loongson_mmi            __ase(MIPS_ASE_LOONGSON_MMI)
+#endif
+
+#ifndef cpu_has_loongson_cam
+#define cpu_has_loongson_cam            __ase(MIPS_ASE_LOONGSON_CAM)
+#endif
+
+#ifndef cpu_has_loongson_ext
+#define cpu_has_loongson_ext            __ase(MIPS_ASE_LOONGSON_EXT)
+#endif
+
+#ifndef cpu_has_loongson_ext2
+#define cpu_has_loongson_ext2           __ase(MIPS_ASE_LOONGSON_EXT2)
+#endif
+
+#ifndef cpu_has_mipsmt
+#define cpu_has_mipsmt          __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
+#endif
+
+#ifndef cpu_has_vp
+#define cpu_has_vp              __isa_ge_and_opt(6, MIPS_CPU_VP)
+#endif
+
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal       __isa_ge_or_opt(6, MIPS_CPU_ULRI)
+#endif
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex        __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          0
+# endif
+# ifndef cpu_vmbits
+# define cpu_vmbits 31
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex                0
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits                 1
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg         1
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          1
+# endif
+# ifndef cpu_vmbits
+# define cpu_vmbits cpu_data[0].vmbits
+# define __NEED_VMBITS_PROBE
+# endif
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+# define cpu_has_vint           __opt(MIPS_CPU_VINT)
+#elif !defined(cpu_has_vint)
+# define cpu_has_vint                   0
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+# define cpu_has_veic           __opt(MIPS_CPU_VEIC)
+#elif !defined(cpu_has_veic)
+# define cpu_has_veic                   0
+#endif
+
+#ifndef cpu_has_inclusive_pcaches
+#define cpu_has_inclusive_pcaches       __opt(MIPS_CPU_INCLUSIVE_CACHES)
+#endif
+
+#ifndef cpu_dcache_line_size
+#define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
+#endif
+#ifndef cpu_icache_line_size
+#define cpu_icache_line_size()  cpu_data[0].icache.linesz
+#endif
+#ifndef cpu_scache_line_size
+#define cpu_scache_line_size()  cpu_data[0].scache.linesz
+#endif
+#ifndef cpu_tcache_line_size
+#define cpu_tcache_line_size()  cpu_data[0].tcache.linesz
+#endif
+
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits            0
+#endif
+
+#ifndef cpu_has_perf_cntr_intr_bit
+#define cpu_has_perf_cntr_intr_bit      __opt(MIPS_CPU_PCI)
+#endif
+
+#ifndef cpu_has_vz
+#define cpu_has_vz              __ase(MIPS_ASE_VZ)
+#endif
+
+#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
+# define cpu_has_msa            __ase(MIPS_ASE_MSA)
+#elif !defined(cpu_has_msa)
+# define cpu_has_msa            0
+#endif
+
+#ifndef cpu_has_ufr
+# define cpu_has_ufr            __opt(MIPS_CPU_UFR)
+#endif
+
+#ifndef cpu_has_fre
+# define cpu_has_fre            __opt(MIPS_CPU_FRE)
+#endif
+
+#ifndef cpu_has_cdmm
+# define cpu_has_cdmm           __opt(MIPS_CPU_CDMM)
+#endif
+
+#ifndef cpu_has_small_pages
+# define cpu_has_small_pages    __opt(MIPS_CPU_SP)
+#endif
+
+#ifndef cpu_has_nan_legacy
+#define cpu_has_nan_legacy      __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
+#endif
+#ifndef cpu_has_nan_2008
+#define cpu_has_nan_2008        __isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
+#endif
+
+#ifndef cpu_has_ebase_wg
+# define cpu_has_ebase_wg       __opt(MIPS_CPU_EBASE_WG)
+#endif
+
+#ifndef cpu_has_badinstr
+# define cpu_has_badinstr       __isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
+#endif
+
+#ifndef cpu_has_badinstrp
+# define cpu_has_badinstrp      __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
+#endif
+
+#ifndef cpu_has_contextconfig
+# define cpu_has_contextconfig  __opt(MIPS_CPU_CTXTC)
+#endif
+
+#ifndef cpu_has_perf
+# define cpu_has_perf           __opt(MIPS_CPU_PERF)
+#endif
+
+#ifndef cpu_has_mac2008_only
+# define cpu_has_mac2008_only   __opt(MIPS_CPU_MAC_2008_ONLY)
+#endif
+
+#ifndef cpu_has_ftlbparex
+# define cpu_has_ftlbparex      __opt(MIPS_CPU_FTLBPAREX)
+#endif
+
+#ifndef cpu_has_gsexcex
+# define cpu_has_gsexcex        __opt(MIPS_CPU_GSEXCEX)
+#endif
+
+#ifdef CONFIG_SMP
+/*
+ * Some systems share FTLB RAMs between threads within a core (siblings in
+ * kernel parlance). This means that FTLB entries may become invalid at almost
+ * any point when an entry is evicted due to a sibling thread writing an entry
+ * to the shared FTLB RAM.
+ *
+ * This is only relevant to SMP systems, and the only systems that exhibit this
+ * property implement MIPSr6 or higher so we constrain support for this to
+ * kernels that will run on such systems.
+ */
+# ifndef cpu_has_shared_ftlb_ram
+#  define cpu_has_shared_ftlb_ram \
+        __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
+# endif
+
+/*
+ * Some systems take this a step further & share FTLB entries between siblings.
+ * This is implemented as TLB writes happening as usual, but if an entry
+ * written by a sibling exists in the shared FTLB for a translation which would
+ * otherwise cause a TLB refill exception then the CPU will use the entry
+ * written by its sibling rather than triggering a refill & writing a matching
+ * TLB entry for itself.
+ *
+ * This is naturally only valid if a TLB entry is known to be suitable for use
+ * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
+ * rather than ASIDs or when a TLB entry is marked global.
+ */
+# ifndef cpu_has_shared_ftlb_entries
+#  define cpu_has_shared_ftlb_entries \
+        __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
+# endif
+#endif /* SMP */
+
+#ifndef cpu_has_shared_ftlb_ram
+# define cpu_has_shared_ftlb_ram 0
+#endif
+#ifndef cpu_has_shared_ftlb_entries
+# define cpu_has_shared_ftlb_entries 0
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMP
+# define cpu_has_mipsmt_pertccounters \
+        __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
+#else
+# define cpu_has_mipsmt_pertccounters 0
+#endif /* CONFIG_MIPS_MT_SMP */
+
+/*
+ * We only enable MMID support for configurations which natively support 64 bit
+ * atomics because getting good performance from the allocator relies upon
+ * efficient atomic64_*() functions.
+ */
+#ifndef cpu_has_mmid
+# ifdef CONFIG_GENERIC_ATOMIC64
+#  define cpu_has_mmid          0
+# else
+#  define cpu_has_mmid          __isa_ge_and_opt(6, MIPS_CPU_MMID)
+# endif
+#endif
+
+#ifndef cpu_has_mm_sysad
+# define cpu_has_mm_sysad       __opt(MIPS_CPU_MM_SYSAD)
+#endif
+
+#ifndef cpu_has_mm_full
+# define cpu_has_mm_full        __opt(MIPS_CPU_MM_FULL)
+#endif
+
+/*
+ * Guest capabilities
+ */
+#ifndef cpu_guest_has_conf1
+#define cpu_guest_has_conf1     (cpu_data[0].guest.conf & (1 << 1))
+#endif
+#ifndef cpu_guest_has_conf2
+#define cpu_guest_has_conf2     (cpu_data[0].guest.conf & (1 << 2))
+#endif
+#ifndef cpu_guest_has_conf3
+#define cpu_guest_has_conf3     (cpu_data[0].guest.conf & (1 << 3))
+#endif
+#ifndef cpu_guest_has_conf4
+#define cpu_guest_has_conf4     (cpu_data[0].guest.conf & (1 << 4))
+#endif
+#ifndef cpu_guest_has_conf5
+#define cpu_guest_has_conf5     (cpu_data[0].guest.conf & (1 << 5))
+#endif
+#ifndef cpu_guest_has_conf6
+#define cpu_guest_has_conf6     (cpu_data[0].guest.conf & (1 << 6))
+#endif
+#ifndef cpu_guest_has_conf7
+#define cpu_guest_has_conf7     (cpu_data[0].guest.conf & (1 << 7))
+#endif
+#ifndef cpu_guest_has_fpu
+#define cpu_guest_has_fpu       (cpu_data[0].guest.options & MIPS_CPU_FPU)
+#endif
+#ifndef cpu_guest_has_watch
+#define cpu_guest_has_watch     (cpu_data[0].guest.options & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_guest_has_contextconfig
+#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
+#endif
+#ifndef cpu_guest_has_segments
+#define cpu_guest_has_segments  (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
+#endif
+#ifndef cpu_guest_has_badinstr
+#define cpu_guest_has_badinstr  (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
+#endif
+#ifndef cpu_guest_has_badinstrp
+#define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
+#endif
+#ifndef cpu_guest_has_htw
+#define cpu_guest_has_htw       (cpu_data[0].guest.options & MIPS_CPU_HTW)
+#endif
+#ifndef cpu_guest_has_ldpte
+#define cpu_guest_has_ldpte     (cpu_data[0].guest.options & MIPS_CPU_LDPTE)
+#endif
+#ifndef cpu_guest_has_mvh
+#define cpu_guest_has_mvh       (cpu_data[0].guest.options & MIPS_CPU_MVH)
+#endif
+#ifndef cpu_guest_has_msa
+#define cpu_guest_has_msa       (cpu_data[0].guest.ases & MIPS_ASE_MSA)
+#endif
+#ifndef cpu_guest_has_kscr
+#define cpu_guest_has_kscr(n)   (cpu_data[0].guest.kscratch_mask & (1u << (n)))
+#endif
+#ifndef cpu_guest_has_rw_llb
+#define cpu_guest_has_rw_llb    (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
+#endif
+#ifndef cpu_guest_has_perf
+#define cpu_guest_has_perf      (cpu_data[0].guest.options & MIPS_CPU_PERF)
+#endif
+#ifndef cpu_guest_has_maar
+#define cpu_guest_has_maar      (cpu_data[0].guest.options & MIPS_CPU_MAAR)
+#endif
+#ifndef cpu_guest_has_userlocal
+#define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI)
+#endif
+
+/*
+ * Guest dynamic capabilities
+ */
+#ifndef cpu_guest_has_dyn_fpu
+#define cpu_guest_has_dyn_fpu   (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
+#endif
+#ifndef cpu_guest_has_dyn_watch
+#define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_guest_has_dyn_contextconfig
+#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
+#endif
+#ifndef cpu_guest_has_dyn_perf
+#define cpu_guest_has_dyn_perf  (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
+#endif
+#ifndef cpu_guest_has_dyn_msa
+#define cpu_guest_has_dyn_msa   (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
+#endif
+#ifndef cpu_guest_has_dyn_maar
+#define cpu_guest_has_dyn_maar  (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
new file mode 100644
index 000000000..a600670d0
--- /dev/null
+++ b/arch/mips/include/asm/cpu-info.h
@@ -0,0 +1,219 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+#include <linux/cache.h>
+#include <linux/types.h>
+
+#include <asm/mipsregs.h>
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+        unsigned int waysize;   /* Bytes per way */
+        unsigned short sets;    /* Number of lines per set */
+        unsigned char ways;     /* Number of ways */
+        unsigned char linesz;   /* Size of line in bytes */
+        unsigned char waybit;   /* Bits to select in a cache set */
+        unsigned char flags;    /* Flags describing cache properties */
+};
+
+struct guest_info {
+        unsigned long           ases;
+        unsigned long           ases_dyn;
+        unsigned long long      options;
+        unsigned long long      options_dyn;
+        int                     tlbsize;
+        u8                      conf;
+        u8                      kscratch_mask;
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT  0x00000001
+#define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
+#define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
+#define MIPS_IC_SNOOPS_REMOTE   0x00000010      /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX       0x00000020      /* Physically indexed cache */
+
+struct cpuinfo_mips {
+        u64                     asid_cache;
+#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
+        unsigned long           asid_mask;
+#endif
+
+        /*
+         * Capability and feature descriptor structure for MIPS CPU
+         */
+        unsigned long           ases;
+        unsigned long long      options;
+        unsigned int            udelay_val;
+        unsigned int            processor_id;
+        unsigned int            fpu_id;
+        unsigned int            fpu_csr31;
+        unsigned int            fpu_msk31;
+        unsigned int            msa_id;
+        unsigned int            cputype;
+        int                     isa_level;
+        int                     tlbsize;
+        int                     tlbsizevtlb;
+        int                     tlbsizeftlbsets;
+        int                     tlbsizeftlbways;
+        struct cache_desc       icache; /* Primary I-cache */
+        struct cache_desc       dcache; /* Primary D or combined I/D cache */
+        struct cache_desc       vcache; /* Victim cache, between pcache and scache */
+        struct cache_desc       scache; /* Secondary cache */
+        struct cache_desc       tcache; /* Tertiary/split secondary cache */
+        int                     srsets; /* Shadow register sets */
+        int                     package;/* physical package number */
+        unsigned int            globalnumber;
+#ifdef CONFIG_64BIT
+        int                     vmbits; /* Virtual memory size in bits */
+#endif
+        void                    *data;  /* Additional data */
+        unsigned int            watch_reg_count;   /* Number that exist */
+        unsigned int            watch_reg_use_cnt; /* Usable by ptrace */
+#define NUM_WATCH_REGS 4
+        u16                     watch_reg_masks[NUM_WATCH_REGS];
+        unsigned int            kscratch_mask; /* Usable KScratch mask. */
+        /*
+         * Cache Coherency attribute for write-combine memory writes.
+         * (shifted by _CACHE_SHIFT)
+         */
+        unsigned int            writecombine;
+        /*
+         * Simple counter to prevent enabling HTW in nested
+         * htw_start/htw_stop calls
+         */
+        unsigned int            htw_seq;
+
+        /* VZ & Guest features */
+        struct guest_info       guest;
+        unsigned int            gtoffset_mask;
+        unsigned int            guestid_mask;
+        unsigned int            guestid_cache;
+
+#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
+        /* CPUCFG data for this CPU, synthesized at probe time.
+         *
+         * CPUCFG select 0 is PRId, 4 and above are unimplemented for now.
+         * So the only stored values are for CPUCFG selects 1-3 inclusive.
+         */
+        u32 loongson3_cpucfg_data[3];
+#endif
+} __attribute__((aligned(SMP_CACHE_BYTES)));
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+#define boot_cpu_data cpu_data[0]
+
+extern void cpu_probe(void);
+extern void cpu_report(void);
+
+extern const char *__cpu_name[];
+#define cpu_name_string()       __cpu_name[raw_smp_processor_id()]
+
+struct seq_file;
+struct notifier_block;
+
+extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
+extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
+
+#define proc_cpuinfo_notifier(fn, pri)                                  \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_proc_cpuinfo_notifier(&fn##_nb);                       \
+})
+
+struct proc_cpuinfo_notifier_args {
+        struct seq_file *m;
+        unsigned long n;
+};
+
+static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
+{
+        /* Optimisation for systems where multiple clusters aren't used */
+        if (!IS_ENABLED(CONFIG_CPU_MIPSR5) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
+                return 0;
+
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
+                MIPS_GLOBALNUMBER_CLUSTER_SHF;
+}
+
+static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
+{
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
+                MIPS_GLOBALNUMBER_CORE_SHF;
+}
+
+static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
+{
+        /* Optimisation for systems where VP(E)s aren't used */
+        if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
+                return 0;
+
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
+                MIPS_GLOBALNUMBER_VP_SHF;
+}
+
+extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
+extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
+extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
+
+static inline bool cpus_are_siblings(int cpua, int cpub)
+{
+        struct cpuinfo_mips *infoa = &cpu_data[cpua];
+        struct cpuinfo_mips *infob = &cpu_data[cpub];
+        unsigned int gnuma, gnumb;
+
+        if (infoa->package != infob->package)
+                return false;
+
+        gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
+        gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
+        if (gnuma != gnumb)
+                return false;
+
+        return true;
+}
+
+static inline unsigned long cpu_asid_inc(void)
+{
+        return 1 << CONFIG_MIPS_ASID_SHIFT;
+}
+
+static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
+{
+#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
+        return cpuinfo->asid_mask;
+#endif
+        return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
+}
+
+static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
+                                     unsigned long asid_mask)
+{
+#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
+        cpuinfo->asid_mask = asid_mask;
+#endif
+}
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
new file mode 100644
index 000000000..3288cef4b
--- /dev/null
+++ b/arch/mips/include/asm/cpu-type.h
@@ -0,0 +1,223 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_TYPE_H
+#define __ASM_CPU_TYPE_H
+
+#include <linux/smp.h>
+#include <linux/compiler.h>
+
+static inline int __pure __get_cpu_type(const int cpu_type)
+{
+        switch (cpu_type) {
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
+    defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
+        case CPU_LOONGSON2EF:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64
+        case CPU_LOONGSON64:
+#endif
+
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
+    defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
+        case CPU_LOONGSON32:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
+        case CPU_4KC:
+        case CPU_ALCHEMY:
+        case CPU_PR4450:
+#endif
+
+#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
+        case CPU_4KEC:
+        case CPU_XBURST:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
+        case CPU_4KSC:
+        case CPU_24K:
+        case CPU_34K:
+        case CPU_1004K:
+        case CPU_74K:
+        case CPU_1074K:
+        case CPU_M14KC:
+        case CPU_M14KEC:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
+        case CPU_M5150:
+        case CPU_P5600:
+#endif
+
+#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS32_R5) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS64_R5) || \
+    defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
+        case CPU_QEMU_GENERIC:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
+        case CPU_5KC:
+        case CPU_5KE:
+        case CPU_20KC:
+        case CPU_25KF:
+        case CPU_SB1:
+        case CPU_SB1A:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
+        /*
+         * All MIPS64 R2 processors have their own special symbols.  That is,
+         * there currently is no pure R2 core
+         */
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6
+        case CPU_M6250:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
+        case CPU_I6400:
+        case CPU_I6500:
+        case CPU_P6600:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_R3000
+        case CPU_R2000:
+        case CPU_R3000:
+        case CPU_R3000A:
+        case CPU_R3041:
+        case CPU_R3051:
+        case CPU_R3052:
+        case CPU_R3081:
+        case CPU_R3081E:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_TX39XX
+        case CPU_TX3912:
+        case CPU_TX3922:
+        case CPU_TX3927:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_VR41XX
+        case CPU_VR41XX:
+        case CPU_VR4111:
+        case CPU_VR4121:
+        case CPU_VR4122:
+        case CPU_VR4131:
+        case CPU_VR4133:
+        case CPU_VR4181:
+        case CPU_VR4181A:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_R4X00
+        case CPU_R4000PC:
+        case CPU_R4000SC:
+        case CPU_R4000MC:
+        case CPU_R4200:
+        case CPU_R4400PC:
+        case CPU_R4400SC:
+        case CPU_R4400MC:
+        case CPU_R4600:
+        case CPU_R4700:
+        case CPU_R4640:
+        case CPU_R4650:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_TX49XX
+        case CPU_TX49XX:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_R5000
+        case CPU_R5000:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_R5500
+        case CPU_R5500:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_NEVADA
+        case CPU_NEVADA:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_R10000
+        case CPU_R10000:
+        case CPU_R12000:
+        case CPU_R14000:
+        case CPU_R16000:
+#endif
+#ifdef CONFIG_SYS_HAS_CPU_RM7000
+        case CPU_RM7000:
+        case CPU_SR71000:
+#endif
+#ifdef CONFIG_SYS_HAS_CPU_SB1
+        case CPU_SB1:
+        case CPU_SB1A:
+#endif
+#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
+        case CPU_CAVIUM_OCTEON:
+        case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_CAVIUM_OCTEON2:
+        case CPU_CAVIUM_OCTEON3:
+#endif
+
+#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
+        defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
+        case CPU_BMIPS4350:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
+        case CPU_BMIPS4380:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
+        case CPU_BMIPS5000:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_XLP
+        case CPU_XLP:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_XLR
+        case CPU_XLR:
+#endif
+                break;
+        default:
+                unreachable();
+        }
+
+        return cpu_type;
+}
+
+static inline int __pure current_cpu_type(void)
+{
+        const int cpu_type = current_cpu_data.cputype;
+
+        return __get_cpu_type(cpu_type);
+}
+
+static inline int __pure boot_cpu_type(void)
+{
+        const int cpu_type = cpu_data[0].cputype;
+
+        return __get_cpu_type(cpu_type);
+}
+
+#endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
new file mode 100644
index 000000000..c9222cc22
--- /dev/null
+++ b/arch/mips/include/asm/cpu.h
@@ -0,0 +1,451 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * cpu.h: Values of the PRId register used to match up
+ *        various MIPS cpu types.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 2004, 2013  Maciej W. Rozycki
+ */
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+#include <linux/bits.h>
+
+/*
+   As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
+   register 15, select 0) is defined in this (backwards compatible) way:
+
+  +----------------+----------------+----------------+----------------+
+  | Company Options| Company ID     | Processor ID   | Revision       |
+  +----------------+----------------+----------------+----------------+
+   31            24 23            16 15             8 7
+
+   I don't have docs for all the previous processors, but my impression is
+   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+   spec.
+*/
+
+#define PRID_OPT_MASK           0xff000000
+
+/*
+ * Assigned Company values for bits 23:16 of the PRId register.
+ */
+
+#define PRID_COMP_MASK          0xff0000
+
+#define PRID_COMP_LEGACY        0x000000
+#define PRID_COMP_MIPS          0x010000
+#define PRID_COMP_BROADCOM      0x020000
+#define PRID_COMP_ALCHEMY       0x030000
+#define PRID_COMP_SIBYTE        0x040000
+#define PRID_COMP_SANDCRAFT     0x050000
+#define PRID_COMP_NXP           0x060000
+#define PRID_COMP_TOSHIBA       0x070000
+#define PRID_COMP_LSI           0x080000
+#define PRID_COMP_LEXRA         0x0b0000
+#define PRID_COMP_NETLOGIC      0x0c0000
+#define PRID_COMP_CAVIUM        0x0d0000
+#define PRID_COMP_LOONGSON      0x140000
+#define PRID_COMP_INGENIC_13    0x130000        /* X2000 */
+#define PRID_COMP_INGENIC_D0    0xd00000        /* JZ4740, JZ4750, X1830 */
+#define PRID_COMP_INGENIC_D1    0xd10000        /* JZ4770, JZ4775, X1000 */
+#define PRID_COMP_INGENIC_E1    0xe10000        /* JZ4780 */
+
+/*
+ * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
+ * register.  In order to detect a certain CPU type exactly eventually
+ * additional registers may need to be examined.
+ */
+
+#define PRID_IMP_MASK           0xff00
+
+/*
+ * These are valid when 23:16 == PRID_COMP_LEGACY
+ */
+
+#define PRID_IMP_R2000          0x0100
+#define PRID_IMP_AU1_REV1       0x0100
+#define PRID_IMP_AU1_REV2       0x0200
+#define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
+#define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
+#define PRID_IMP_R4000          0x0400
+#define PRID_IMP_R6000A         0x0600
+#define PRID_IMP_R10000         0x0900
+#define PRID_IMP_R4300          0x0b00
+#define PRID_IMP_VR41XX         0x0c00
+#define PRID_IMP_R12000         0x0e00
+#define PRID_IMP_R14000         0x0f00          /* R14K && R16K */
+#define PRID_IMP_R8000          0x1000
+#define PRID_IMP_PR4450         0x1200
+#define PRID_IMP_R4600          0x2000
+#define PRID_IMP_R4700          0x2100
+#define PRID_IMP_TX39           0x2200
+#define PRID_IMP_R4640          0x2200
+#define PRID_IMP_R4650          0x2200          /* Same as R4640 */
+#define PRID_IMP_R5000          0x2300
+#define PRID_IMP_TX49           0x2d00
+#define PRID_IMP_SONIC          0x2400
+#define PRID_IMP_MAGIC          0x2500
+#define PRID_IMP_RM7000         0x2700
+#define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
+#define PRID_IMP_RM9000         0x3400
+#define PRID_IMP_LOONGSON_32    0x4200  /* Loongson-1 */
+#define PRID_IMP_R5432          0x5400
+#define PRID_IMP_R5500          0x5500
+#define PRID_IMP_LOONGSON_64R   0x6100  /* Reduced Loongson-2 */
+#define PRID_IMP_LOONGSON_64C   0x6300  /* Classic Loongson-2 and Loongson-3 */
+#define PRID_IMP_LOONGSON_64G   0xc000  /* Generic Loongson-2 and Loongson-3 */
+
+#define PRID_IMP_UNKNOWN        0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+
+#define PRID_IMP_QEMU_GENERIC   0x0000
+#define PRID_IMP_4KC            0x8000
+#define PRID_IMP_5KC            0x8100
+#define PRID_IMP_20KC           0x8200
+#define PRID_IMP_4KEC           0x8400
+#define PRID_IMP_4KSC           0x8600
+#define PRID_IMP_25KF           0x8800
+#define PRID_IMP_5KE            0x8900
+#define PRID_IMP_4KECR2         0x9000
+#define PRID_IMP_4KEMPR2        0x9100
+#define PRID_IMP_4KSD           0x9200
+#define PRID_IMP_24K            0x9300
+#define PRID_IMP_34K            0x9500
+#define PRID_IMP_24KE           0x9600
+#define PRID_IMP_74K            0x9700
+#define PRID_IMP_1004K          0x9900
+#define PRID_IMP_1074K          0x9a00
+#define PRID_IMP_M14KC          0x9c00
+#define PRID_IMP_M14KEC         0x9e00
+#define PRID_IMP_INTERAPTIV_UP  0xa000
+#define PRID_IMP_INTERAPTIV_MP  0xa100
+#define PRID_IMP_PROAPTIV_UP    0xa200
+#define PRID_IMP_PROAPTIV_MP    0xa300
+#define PRID_IMP_P6600          0xa400
+#define PRID_IMP_M5150          0xa700
+#define PRID_IMP_P5600          0xa800
+#define PRID_IMP_I6400          0xa900
+#define PRID_IMP_M6250          0xab00
+#define PRID_IMP_I6500          0xb000
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+
+#define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
+ */
+
+#define PRID_IMP_SR71000        0x0400
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BMIPS32_REV4   0x4000
+#define PRID_IMP_BMIPS32_REV8   0x8000
+#define PRID_IMP_BMIPS3300      0x9000
+#define PRID_IMP_BMIPS3300_ALT  0x9100
+#define PRID_IMP_BMIPS3300_BUG  0x0000
+#define PRID_IMP_BMIPS43XX      0xa000
+#define PRID_IMP_BMIPS5000      0x5a00
+#define PRID_IMP_BMIPS5200      0x5b00
+
+#define PRID_REV_BMIPS4380_LO   0x0040
+#define PRID_REV_BMIPS4380_HI   0x006f
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
+ */
+
+#define PRID_IMP_CAVIUM_CN38XX 0x0000
+#define PRID_IMP_CAVIUM_CN31XX 0x0100
+#define PRID_IMP_CAVIUM_CN30XX 0x0200
+#define PRID_IMP_CAVIUM_CN58XX 0x0300
+#define PRID_IMP_CAVIUM_CN56XX 0x0400
+#define PRID_IMP_CAVIUM_CN50XX 0x0600
+#define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
+#define PRID_IMP_CAVIUM_CN68XX 0x9100
+#define PRID_IMP_CAVIUM_CN66XX 0x9200
+#define PRID_IMP_CAVIUM_CN61XX 0x9300
+#define PRID_IMP_CAVIUM_CNF71XX 0x9400
+#define PRID_IMP_CAVIUM_CN78XX 0x9500
+#define PRID_IMP_CAVIUM_CN70XX 0x9600
+#define PRID_IMP_CAVIUM_CN73XX 0x9700
+#define PRID_IMP_CAVIUM_CNF75XX 0x9800
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
+ */
+
+#define PRID_IMP_XBURST_REV1    0x0200  /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA        */
+#define PRID_IMP_XBURST_REV2    0x0100  /* XBurst®1 with MXU2.0 SIMD ISA               */
+#define PRID_IMP_XBURST2                0x2000  /* XBurst®2 with MXU2.1 SIMD ISA               */
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
+ */
+#define PRID_IMP_NETLOGIC_XLR732        0x0000
+#define PRID_IMP_NETLOGIC_XLR716        0x0200
+#define PRID_IMP_NETLOGIC_XLR532        0x0900
+#define PRID_IMP_NETLOGIC_XLR308        0x0600
+#define PRID_IMP_NETLOGIC_XLR532C       0x0800
+#define PRID_IMP_NETLOGIC_XLR516C       0x0a00
+#define PRID_IMP_NETLOGIC_XLR508C       0x0b00
+#define PRID_IMP_NETLOGIC_XLR308C       0x0f00
+#define PRID_IMP_NETLOGIC_XLS608        0x8000
+#define PRID_IMP_NETLOGIC_XLS408        0x8800
+#define PRID_IMP_NETLOGIC_XLS404        0x8c00
+#define PRID_IMP_NETLOGIC_XLS208        0x8e00
+#define PRID_IMP_NETLOGIC_XLS204        0x8f00
+#define PRID_IMP_NETLOGIC_XLS108        0xce00
+#define PRID_IMP_NETLOGIC_XLS104        0xcf00
+#define PRID_IMP_NETLOGIC_XLS616B       0x4000
+#define PRID_IMP_NETLOGIC_XLS608B       0x4a00
+#define PRID_IMP_NETLOGIC_XLS416B       0x4400
+#define PRID_IMP_NETLOGIC_XLS412B       0x4c00
+#define PRID_IMP_NETLOGIC_XLS408B       0x4e00
+#define PRID_IMP_NETLOGIC_XLS404B       0x4f00
+#define PRID_IMP_NETLOGIC_AU13XX        0x8000
+
+#define PRID_IMP_NETLOGIC_XLP8XX        0x1000
+#define PRID_IMP_NETLOGIC_XLP3XX        0x1100
+#define PRID_IMP_NETLOGIC_XLP2XX        0x1200
+#define PRID_IMP_NETLOGIC_XLP9XX        0x1500
+#define PRID_IMP_NETLOGIC_XLP5XX        0x1300
+
+/*
+ * Particular Revision values for bits 7:0 of the PRId register.
+ */
+
+#define PRID_REV_MASK           0x00ff
+
+/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+#define PRID_REV_TX4927                 0x0022
+#define PRID_REV_TX4937                 0x0030
+#define PRID_REV_R4400                  0x0040
+#define PRID_REV_R3000A                 0x0030
+#define PRID_REV_R3000                  0x0020
+#define PRID_REV_R2000A                 0x0010
+#define PRID_REV_TX3912                 0x0010
+#define PRID_REV_TX3922                 0x0030
+#define PRID_REV_TX3927                 0x0040
+#define PRID_REV_VR4111                 0x0050
+#define PRID_REV_VR4181                 0x0050  /* Same as VR4111 */
+#define PRID_REV_VR4121                 0x0060
+#define PRID_REV_VR4122                 0x0070
+#define PRID_REV_VR4181A                0x0070  /* Same as VR4122 */
+#define PRID_REV_VR4130                 0x0080
+#define PRID_REV_34K_V1_0_2             0x0022
+#define PRID_REV_LOONGSON1B             0x0020
+#define PRID_REV_LOONGSON1C             0x0020  /* Same as Loongson-1B */
+#define PRID_REV_LOONGSON2E             0x0002
+#define PRID_REV_LOONGSON2F             0x0003
+#define PRID_REV_LOONGSON2K_R1_0        0x0000
+#define PRID_REV_LOONGSON2K_R1_1        0x0001
+#define PRID_REV_LOONGSON2K_R1_2        0x0002
+#define PRID_REV_LOONGSON2K_R1_3        0x0003
+#define PRID_REV_LOONGSON3A_R1          0x0005
+#define PRID_REV_LOONGSON3B_R1          0x0006
+#define PRID_REV_LOONGSON3B_R2          0x0007
+#define PRID_REV_LOONGSON3A_R2_0        0x0008
+#define PRID_REV_LOONGSON3A_R3_0        0x0009
+#define PRID_REV_LOONGSON3A_R2_1        0x000c
+#define PRID_REV_LOONGSON3A_R3_1        0x000d
+
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)                                    \
+        ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)                            \
+        ((ver) << 5 | (rev) << 2 | (patch))
+
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0                               | Implementation | Revision       |
+ * +---------------------------------+----------------+----------------+
+ *  31                             16 15             8 7              0
+ */
+
+#define FPIR_IMP_MASK           0xff00
+
+#define FPIR_IMP_NONE           0x0000
+
+#if !defined(__ASSEMBLY__)
+
+enum cpu_type_enum {
+        CPU_UNKNOWN,
+
+        /*
+         * R2000 class processors
+         */
+        CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
+        CPU_R3081, CPU_R3081E,
+
+        /*
+         * R4000 class processors
+         */
+        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200,
+        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
+        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
+        CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+        CPU_SR71000, CPU_TX49XX,
+
+        /*
+         * TX3900 class processors
+         */
+        CPU_TX3912, CPU_TX3922, CPU_TX3927,
+
+        /*
+         * MIPS32 class processors
+         */
+        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
+        CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
+        CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
+
+        /*
+         * MIPS64 class processors
+         */
+        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
+        CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
+
+        CPU_QEMU_GENERIC,
+
+        CPU_LAST
+};
+
+#endif /* !__ASSEMBLY */
+
+/*
+ * ISA Level encodings
+ *
+ */
+#define MIPS_CPU_ISA_II         0x00000001
+#define MIPS_CPU_ISA_III        0x00000002
+#define MIPS_CPU_ISA_IV         0x00000004
+#define MIPS_CPU_ISA_V          0x00000008
+#define MIPS_CPU_ISA_M32R1      0x00000010
+#define MIPS_CPU_ISA_M32R2      0x00000020
+#define MIPS_CPU_ISA_M64R1      0x00000040
+#define MIPS_CPU_ISA_M64R2      0x00000080
+#define MIPS_CPU_ISA_M32R5      0x00000100
+#define MIPS_CPU_ISA_M64R5      0x00000200
+#define MIPS_CPU_ISA_M32R6      0x00000400
+#define MIPS_CPU_ISA_M64R6      0x00000800
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
+        MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+        MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
+        MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
+
+/*
+ * CPU Option encodings
+ */
+#define MIPS_CPU_TLB            BIT_ULL( 0)     /* CPU has TLB */
+#define MIPS_CPU_4KEX           BIT_ULL( 1)     /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE       BIT_ULL( 2)     /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE       BIT_ULL( 3)     /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE     BIT_ULL( 4)     /* TX3900-style caches */
+#define MIPS_CPU_FPU            BIT_ULL( 5)     /* CPU has FPU */
+#define MIPS_CPU_32FPR          BIT_ULL( 6)     /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER        BIT_ULL( 7)     /* Cycle count/compare */
+#define MIPS_CPU_WATCH          BIT_ULL( 8)     /* watchpoint registers */
+#define MIPS_CPU_DIVEC          BIT_ULL( 9)     /* dedicated interrupt vector */
+#define MIPS_CPU_VCE            BIT_ULL(10)     /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P   BIT_ULL(11)     /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S   BIT_ULL(12)     /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK         BIT_ULL(13)     /* Machine check exception */
+#define MIPS_CPU_EJTAG          BIT_ULL(14)     /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX        BIT_ULL(15)     /* no FPU exception */
+#define MIPS_CPU_LLSC           BIT_ULL(16)     /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17)   /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       BIT_ULL(18)     /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           BIT_ULL(19)     /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           BIT_ULL(20)     /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI           BIT_ULL(21)     /* CPU has ULRI feature */
+#define MIPS_CPU_PCI            BIT_ULL(22)     /* CPU has Perf Ctr Int indicator */
+#define MIPS_CPU_RIXI           BIT_ULL(23)     /* CPU has TLB Read/eXec Inhibit */
+#define MIPS_CPU_MICROMIPS      BIT_ULL(24)     /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV         BIT_ULL(25)     /* CPU supports TLBINV/F */
+#define MIPS_CPU_SEGMENTS       BIT_ULL(26)     /* CPU supports Segmentation Control registers */
+#define MIPS_CPU_EVA            BIT_ULL(27)     /* CPU supports Enhanced Virtual Addressing */
+#define MIPS_CPU_HTW            BIT_ULL(28)     /* CPU support Hardware Page Table Walker */
+#define MIPS_CPU_RIXIEX         BIT_ULL(29)     /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
+#define MIPS_CPU_MAAR           BIT_ULL(30)     /* MAAR(I) registers are present */
+#define MIPS_CPU_FRE            BIT_ULL(31)     /* FRE & UFE bits implemented */
+#define MIPS_CPU_RW_LLB         BIT_ULL(32)     /* LLADDR/LLB writes are allowed */
+#define MIPS_CPU_LPA            BIT_ULL(33)     /* CPU supports Large Physical Addressing */
+#define MIPS_CPU_CDMM           BIT_ULL(34)     /* CPU has Common Device Memory Map */
+#define MIPS_CPU_SP             BIT_ULL(36)     /* Small (1KB) page support */
+#define MIPS_CPU_FTLB           BIT_ULL(37)     /* CPU has Fixed-page-size TLB */
+#define MIPS_CPU_NAN_LEGACY     BIT_ULL(38)     /* Legacy NaN implemented */
+#define MIPS_CPU_NAN_2008       BIT_ULL(39)     /* 2008 NaN implemented */
+#define MIPS_CPU_VP             BIT_ULL(40)     /* MIPSr6 Virtual Processors (multi-threading) */
+#define MIPS_CPU_LDPTE          BIT_ULL(41)     /* CPU has ldpte/lddir instructions */
+#define MIPS_CPU_MVH            BIT_ULL(42)     /* CPU supports MFHC0/MTHC0 */
+#define MIPS_CPU_EBASE_WG       BIT_ULL(43)     /* CPU has EBase.WG */
+#define MIPS_CPU_BADINSTR       BIT_ULL(44)     /* CPU has BadInstr register */
+#define MIPS_CPU_BADINSTRP      BIT_ULL(45)     /* CPU has BadInstrP register */
+#define MIPS_CPU_CTXTC          BIT_ULL(46)     /* CPU has [X]ConfigContext registers */
+#define MIPS_CPU_PERF           BIT_ULL(47)     /* CPU has MIPS performance counters */
+#define MIPS_CPU_GUESTCTL0EXT   BIT_ULL(48)     /* CPU has VZ GuestCtl0Ext register */
+#define MIPS_CPU_GUESTCTL1      BIT_ULL(49)     /* CPU has VZ GuestCtl1 register */
+#define MIPS_CPU_GUESTCTL2      BIT_ULL(50)     /* CPU has VZ GuestCtl2 register */
+#define MIPS_CPU_GUESTID        BIT_ULL(51)     /* CPU uses VZ ASE GuestID feature */
+#define MIPS_CPU_DRG            BIT_ULL(52)     /* CPU has VZ Direct Root to Guest (DRG) */
+#define MIPS_CPU_UFR            BIT_ULL(53)     /* CPU supports User mode FR switching */
+#define MIPS_CPU_SHARED_FTLB_RAM \
+                                BIT_ULL(54)     /* CPU shares FTLB RAM with another */
+#define MIPS_CPU_SHARED_FTLB_ENTRIES \
+                                BIT_ULL(55)     /* CPU shares FTLB entries with another */
+#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
+                                BIT_ULL(56)     /* CPU has perf counters implemented per TC (MIPSMT ASE) */
+#define MIPS_CPU_MMID           BIT_ULL(57)     /* CPU supports MemoryMapIDs */
+#define MIPS_CPU_MM_SYSAD       BIT_ULL(58)     /* CPU supports write-through SysAD Valid merge */
+#define MIPS_CPU_MM_FULL        BIT_ULL(59)     /* CPU supports write-through full merge */
+#define MIPS_CPU_MAC_2008_ONLY  BIT_ULL(60)     /* CPU Only support MAC2008 Fused multiply-add instruction */
+#define MIPS_CPU_FTLBPAREX      BIT_ULL(61)     /* CPU has FTLB parity exception */
+#define MIPS_CPU_GSEXCEX        BIT_ULL(62)     /* CPU has GSExc exception */
+
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16         0x00000001 /* code compression */
+#define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
+#define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
+#define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
+#define MIPS_ASE_MSA            0x00000100 /* MIPS SIMD Architecture */
+#define MIPS_ASE_DSP3           0x00000200 /* Signal Processing ASE Rev 3*/
+#define MIPS_ASE_MIPS16E2       0x00000400 /* MIPS16e2 */
+#define MIPS_ASE_LOONGSON_MMI   0x00000800 /* Loongson MultiMedia extensions Instructions */
+#define MIPS_ASE_LOONGSON_CAM   0x00001000 /* Loongson CAM */
+#define MIPS_ASE_LOONGSON_EXT   0x00002000 /* Loongson EXTensions */
+#define MIPS_ASE_LOONGSON_EXT2  0x00004000 /* Loongson EXTensions R2 */
+
+#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/cpufeature.h b/arch/mips/include/asm/cpufeature.h
new file mode 100644
index 000000000..ba9e62faf
--- /dev/null
+++ b/arch/mips/include/asm/cpufeature.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * CPU feature definitions for module loading, used by
+ * module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features.
+ */
+
+#ifndef __ASM_CPUFEATURE_H
+#define __ASM_CPUFEATURE_H
+
+#include <uapi/asm/hwcap.h>
+#include <asm/elf.h>
+
+#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
+
+#define cpu_feature(x)          ilog2(HWCAP_ ## x)
+
+static inline bool cpu_have_feature(unsigned int num)
+{
+        return elf_hwcap & (1UL << num);
+}
+
+#endif /* __ASM_CPUFEATURE_H */
diff --git a/arch/mips/include/asm/debug.h b/arch/mips/include/asm/debug.h
new file mode 100644
index 000000000..c7013e1cb
--- /dev/null
+++ b/arch/mips/include/asm/debug.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ */
+
+#ifndef __MIPS_ASM_DEBUG_H__
+#define __MIPS_ASM_DEBUG_H__
+
+#include <linux/dcache.h>
+
+/*
+ * mips_debugfs_dir corresponds to the "mips" directory at the top level
+ * of the DebugFS hierarchy. MIPS-specific DebugFS entires should be
+ * placed beneath this directory.
+ */
+extern struct dentry *mips_debugfs_dir;
+
+#endif /* __MIPS_ASM_DEBUG_H__ */
diff --git a/arch/mips/include/asm/dec/ecc.h b/arch/mips/include/asm/dec/ecc.h
new file mode 100644
index 000000000..c3a3f71f1
--- /dev/null
+++ b/arch/mips/include/asm/dec/ecc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/ecc.h
+ *
+ *      ECC handling logic definitions common to DECstation/DECsystem
+ *      5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
+ *      DECsystem 5900 (KN03), 5900/260 (KN05) systems.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_ECC_H
+#define __ASM_MIPS_DEC_ECC_H
+
+/*
+ * Error Address Register bits.
+ * The register is r/wc -- any write clears it.
+ */
+#define KN0X_EAR_VALID          (1<<31)         /* error data valid, bus IRQ */
+#define KN0X_EAR_CPU            (1<<30)         /* CPU/DMA transaction */
+#define KN0X_EAR_WRITE          (1<<29)         /* write/read transaction */
+#define KN0X_EAR_ECCERR         (1<<28)         /* ECC/timeout or overrun */
+#define KN0X_EAR_RES_27         (1<<27)         /* unused */
+#define KN0X_EAR_ADDRESS        (0x7ffffff<<0)  /* address involved */
+
+/*
+ * Error Syndrome Register bits.
+ * The register is frozen when EAR.VALID is set, otherwise it records bits
+ * from the last memory read.  The register is r/wc -- any write clears it.
+ */
+#define KN0X_ESR_VLDHI          (1<<31)         /* error data valid hi word */
+#define KN0X_ESR_CHKHI          (0x7f<<24)      /* check bits read from mem */
+#define KN0X_ESR_SNGHI          (1<<23)         /* single/double bit error */
+#define KN0X_ESR_SYNHI          (0x7f<<16)      /* syndrome from ECC logic */
+#define KN0X_ESR_VLDLO          (1<<15)         /* error data valid lo word */
+#define KN0X_ESR_CHKLO          (0x7f<<8)       /* check bits read from mem */
+#define KN0X_ESR_SNGLO          (1<<7)          /* single/double bit error */
+#define KN0X_ESR_SYNLO          (0x7f<<0)       /* syndrome from ECC logic */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_ecc_be_init(void);
+extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/arch/mips/include/asm/dec/interrupts.h b/arch/mips/include/asm/dec/interrupts.h
new file mode 100644
index 000000000..e10d34106
--- /dev/null
+++ b/arch/mips/include/asm/dec/interrupts.h
@@ -0,0 +1,126 @@
+/*
+ * Miscellaneous definitions used to initialise the interrupt vector table
+ * with the machine-specific interrupt routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 by Paul M. Antoine.
+ * reworked 1998 by Harald Koerfgen.
+ * Copyright (C) 2001, 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_INTERRUPTS_H
+#define __ASM_DEC_INTERRUPTS_H
+
+#include <irq.h>
+#include <asm/mipsregs.h>
+
+
+/*
+ * The list of possible system devices which provide an
+ * interrupt.  Not all devices exist on a given system.
+ */
+#define DEC_IRQ_CASCADE         0       /* cascade from CSR or I/O ASIC */
+
+/* Ordinary interrupts */
+#define DEC_IRQ_AB_RECV         1       /* ACCESS.bus receive */
+#define DEC_IRQ_AB_XMIT         2       /* ACCESS.bus transmit */
+#define DEC_IRQ_DZ11            3       /* DZ11 (DC7085) serial */
+#define DEC_IRQ_ASC             4       /* ASC (NCR53C94) SCSI */
+#define DEC_IRQ_FLOPPY          5       /* 82077 FDC */
+#define DEC_IRQ_FPU             6       /* R3k FPU */
+#define DEC_IRQ_HALT            7       /* HALT button or from ACCESS.Bus */
+#define DEC_IRQ_ISDN            8       /* Am79C30A ISDN */
+#define DEC_IRQ_LANCE           9       /* LANCE (Am7990) Ethernet */
+#define DEC_IRQ_BUS             10      /* memory, I/O bus read/write errors */
+#define DEC_IRQ_PSU             11      /* power supply unit warning */
+#define DEC_IRQ_RTC             12      /* DS1287 RTC */
+#define DEC_IRQ_SCC0            13      /* SCC (Z85C30) serial #0 */
+#define DEC_IRQ_SCC1            14      /* SCC (Z85C30) serial #1 */
+#define DEC_IRQ_SII             15      /* SII (DC7061) SCSI */
+#define DEC_IRQ_TC0             16      /* TURBOchannel slot #0 */
+#define DEC_IRQ_TC1             17      /* TURBOchannel slot #1 */
+#define DEC_IRQ_TC2             18      /* TURBOchannel slot #2 */
+#define DEC_IRQ_TIMER           19      /* ARC periodic timer */
+#define DEC_IRQ_VIDEO           20      /* framebuffer */
+
+/* I/O ASIC DMA interrupts */
+#define DEC_IRQ_ASC_MERR        21      /* ASC memory read error */
+#define DEC_IRQ_ASC_ERR         22      /* ASC page overrun */
+#define DEC_IRQ_ASC_DMA         23      /* ASC buffer pointer loaded */
+#define DEC_IRQ_FLOPPY_ERR      24      /* FDC error */
+#define DEC_IRQ_ISDN_ERR        25      /* ISDN memory read/overrun error */
+#define DEC_IRQ_ISDN_RXDMA      26      /* ISDN recv buffer pointer loaded */
+#define DEC_IRQ_ISDN_TXDMA      27      /* ISDN xmit buffer pointer loaded */
+#define DEC_IRQ_LANCE_MERR      28      /* LANCE memory read error */
+#define DEC_IRQ_SCC0A_RXERR     29      /* SCC0A (printer) receive overrun */
+#define DEC_IRQ_SCC0A_RXDMA     30      /* SCC0A receive half page */
+#define DEC_IRQ_SCC0A_TXERR     31      /* SCC0A xmit memory read/overrun */
+#define DEC_IRQ_SCC0A_TXDMA     32      /* SCC0A transmit page end */
+#define DEC_IRQ_AB_RXERR        33      /* ACCESS.bus receive overrun */
+#define DEC_IRQ_AB_RXDMA        34      /* ACCESS.bus receive half page */
+#define DEC_IRQ_AB_TXERR        35      /* ACCESS.bus xmit memory read/ovrn */
+#define DEC_IRQ_AB_TXDMA        36      /* ACCESS.bus transmit page end */
+#define DEC_IRQ_SCC1A_RXERR     37      /* SCC1A (modem) receive overrun */
+#define DEC_IRQ_SCC1A_RXDMA     38      /* SCC1A receive half page */
+#define DEC_IRQ_SCC1A_TXERR     39      /* SCC1A xmit memory read/overrun */
+#define DEC_IRQ_SCC1A_TXDMA     40      /* SCC1A transmit page end */
+
+/* TC5 & TC6 are virtual slots for KN02's onboard devices */
+#define DEC_IRQ_TC5             DEC_IRQ_ASC     /* virtual PMAZ-AA */
+#define DEC_IRQ_TC6             DEC_IRQ_LANCE   /* virtual PMAD-AA */
+
+#define DEC_NR_INTS             41
+
+
+/* Largest of cpu mask_nr tables. */
+#define DEC_MAX_CPU_INTS        6
+/* Largest of asic mask_nr tables. */
+#define DEC_MAX_ASIC_INTS       9
+
+
+/*
+ * CPU interrupt bits common to all systems.
+ */
+#define DEC_CPU_INR_FPU         7       /* R3k FPU */
+#define DEC_CPU_INR_SW1         1       /* software #1 */
+#define DEC_CPU_INR_SW0         0       /* software #0 */
+
+#define DEC_CPU_IRQ_BASE        MIPS_CPU_IRQ_BASE       /* first IRQ assigned to CPU */
+
+#define DEC_CPU_IRQ_NR(n)       ((n) + DEC_CPU_IRQ_BASE)
+#define DEC_CPU_IRQ_MASK(n)     (1 << ((n) + CAUSEB_IP))
+#define DEC_CPU_IRQ_ALL         (0xff << CAUSEB_IP)
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Interrupt table structures to hide differences between systems.
+ */
+typedef union { int i; void *p; } int_ptr;
+extern int dec_interrupt[DEC_NR_INTS];
+extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
+extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
+extern int cpu_fpu_mask;
+
+
+/*
+ * Common interrupt routine prototypes for all DECStations
+ */
+extern void kn02_io_int(void);
+extern void kn02xa_io_int(void);
+extern void kn03_io_int(void);
+extern void asic_dma_int(void);
+extern void asic_all_int(void);
+extern void kn02_all_int(void);
+extern void cpu_all_int(void);
+
+extern void dec_intr_unimplemented(void);
+extern void asic_intr_unimplemented(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
new file mode 100644
index 000000000..6d912f095
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/ioasic.h
+ *
+ *      DEC I/O ASIC access operations.
+ *
+ *      Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_IOASIC_H
+#define __ASM_DEC_IOASIC_H
+
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+extern spinlock_t ioasic_ssr_lock;
+
+extern volatile u32 *ioasic_base;
+
+static inline void ioasic_write(unsigned int reg, u32 v)
+{
+        ioasic_base[reg / 4] = v;
+}
+
+static inline u32 ioasic_read(unsigned int reg)
+{
+        return ioasic_base[reg / 4];
+}
+
+extern void init_ioasic_irqs(int base);
+
+extern int dec_ioasic_clocksource_init(void);
+
+#endif /* __ASM_DEC_IOASIC_H */
diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
new file mode 100644
index 000000000..8bd95971f
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -0,0 +1,152 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the address map in the JUNKIO Asic
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
+#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
+
+#define IOASIC_SLOT_SIZE 0x00040000
+
+/*
+ * Address ranges decoded by the I/O ASIC for onboard devices.
+ */
+#define IOASIC_SYS_ROM  (0*IOASIC_SLOT_SIZE)    /* system board ROM */
+#define IOASIC_IOCTL    (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define IOASIC_ESAR     (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define IOASIC_LANCE    (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define IOASIC_SCC0     (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
+#define IOASIC_VDAC_HI  (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_SCC1     (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
+#define IOASIC_VDAC_LO  (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_TOY      (8*IOASIC_SLOT_SIZE)    /* RTC */
+#define IOASIC_ISDN     (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
+#define IOASIC_ERRADDR  (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
+#define IOASIC_CHKSYN   (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
+#define IOASIC_ACC_BUS  (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
+#define IOASIC_MCR      (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
+#define IOASIC_FLOPPY   (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
+#define IOASIC_SCSI     (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define IOASIC_FDC_DMA  (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
+#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)   /* ??? */
+#define IOASIC_RES_15   (15*IOASIC_SLOT_SIZE)   /* unused? */
+
+
+/*
+ * Offsets for I/O ASIC registers
+ * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
+ */
+                                        /* all systems */
+#define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
+#define IO_REG_SCSI_DMA_BP      0x10    /* SCSI DMA Buffer Pointer */
+#define IO_REG_LANCE_DMA_P      0x20    /* LANCE DMA Pointer */
+#define IO_REG_SCC0A_T_DMA_P    0x30    /* SCC0A Transmit DMA Pointer */
+#define IO_REG_SCC0A_R_DMA_P    0x40    /* SCC0A Receive DMA Pointer */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_T_DMA_P    0x50    /* SCC1A Transmit DMA Pointer */
+#define IO_REG_SCC1A_R_DMA_P    0x60    /* SCC1A Receive DMA Pointer */
+
+                                        /* Maxine */
+#define IO_REG_AB_T_DMA_P       0x50    /* ACCESS.bus Transmit DMA Pointer */
+#define IO_REG_AB_R_DMA_P       0x60    /* ACCESS.bus Receive DMA Pointer */
+#define IO_REG_FLOPPY_DMA_P     0x70    /* Floppy DMA Pointer */
+#define IO_REG_ISDN_T_DMA_P     0x80    /* ISDN Transmit DMA Pointer */
+#define IO_REG_ISDN_T_DMA_BP    0x90    /* ISDN Transmit DMA Buffer Pointer */
+#define IO_REG_ISDN_R_DMA_P     0xa0    /* ISDN Receive DMA Pointer */
+#define IO_REG_ISDN_R_DMA_BP    0xb0    /* ISDN Receive DMA Buffer Pointer */
+
+                                        /* all systems */
+#define IO_REG_DATA_0           0xc0    /* System Data Buffer 0 */
+#define IO_REG_DATA_1           0xd0    /* System Data Buffer 1 */
+#define IO_REG_DATA_2           0xe0    /* System Data Buffer 2 */
+#define IO_REG_DATA_3           0xf0    /* System Data Buffer 3 */
+
+                                        /* all systems */
+#define IO_REG_SSR              0x100   /* System Support Register */
+#define IO_REG_SIR              0x110   /* System Interrupt Register */
+#define IO_REG_SIMR             0x120   /* System Interrupt Mask Reg. */
+#define IO_REG_SAR              0x130   /* System Address Register */
+
+                                        /* Maxine */
+#define IO_REG_ISDN_T_DATA      0x140   /* ISDN Xmit Data Register */
+#define IO_REG_ISDN_R_DATA      0x150   /* ISDN Receive Data Register */
+
+                                        /* all systems */
+#define IO_REG_LANCE_SLOT       0x160   /* LANCE I/O Slot Register */
+#define IO_REG_SCSI_SLOT        0x170   /* SCSI Slot Register */
+#define IO_REG_SCC0A_SLOT       0x180   /* SCC0A DMA Slot Register */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_SLOT       0x190   /* SCC1A DMA Slot Register */
+
+                                        /* Maxine */
+#define IO_REG_AB_SLOT          0x190   /* ACCESS.bus DMA Slot Register */
+#define IO_REG_FLOPPY_SLOT      0x1a0   /* Floppy Slot Register */
+
+                                        /* all systems */
+#define IO_REG_SCSI_SCR         0x1b0   /* SCSI Partial-Word DMA Control */
+#define IO_REG_SCSI_SDR0        0x1c0   /* SCSI DMA Partial Word 0 */
+#define IO_REG_SCSI_SDR1        0x1d0   /* SCSI DMA Partial Word 1 */
+#define IO_REG_FCTR             0x1e0   /* Free-Running Counter */
+#define IO_REG_RES_31           0x1f0   /* unused */
+
+
+/*
+ * The upper 16 bits of the System Support Register are a part of the
+ * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
+ * machines.  The exception is the Maxine, which makes use of the
+ * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
+ * wiring.
+ */
+                                                /* all systems */
+#define IO_SSR_SCC0A_TX_DMA_EN  (1<<31)         /* SCC0A transmit DMA enable */
+#define IO_SSR_SCC0A_RX_DMA_EN  (1<<30)         /* SCC0A receive DMA enable */
+#define IO_SSR_RES_27           (1<<27)         /* unused */
+#define IO_SSR_RES_26           (1<<26)         /* unused */
+#define IO_SSR_RES_25           (1<<25)         /* unused */
+#define IO_SSR_RES_24           (1<<24)         /* unused */
+#define IO_SSR_RES_23           (1<<23)         /* unused */
+#define IO_SSR_SCSI_DMA_DIR     (1<<18)         /* SCSI DMA direction */
+#define IO_SSR_SCSI_DMA_EN      (1<<17)         /* SCSI DMA enable */
+#define IO_SSR_LANCE_DMA_EN     (1<<16)         /* LANCE DMA enable */
+
+                                                /* except Maxine */
+#define IO_SSR_SCC1A_TX_DMA_EN  (1<<29)         /* SCC1A transmit DMA enable */
+#define IO_SSR_SCC1A_RX_DMA_EN  (1<<28)         /* SCC1A receive DMA enable */
+#define IO_SSR_RES_22           (1<<22)         /* unused */
+#define IO_SSR_RES_21           (1<<21)         /* unused */
+#define IO_SSR_RES_20           (1<<20)         /* unused */
+#define IO_SSR_RES_19           (1<<19)         /* unused */
+
+                                                /* Maxine */
+#define IO_SSR_AB_TX_DMA_EN     (1<<29)         /* ACCESS.bus xmit DMA enable */
+#define IO_SSR_AB_RX_DMA_EN     (1<<28)         /* ACCESS.bus recv DMA enable */
+#define IO_SSR_FLOPPY_DMA_DIR   (1<<22)         /* Floppy DMA direction */
+#define IO_SSR_FLOPPY_DMA_EN    (1<<21)         /* Floppy DMA enable */
+#define IO_SSR_ISDN_TX_DMA_EN   (1<<20)         /* ISDN transmit DMA enable */
+#define IO_SSR_ISDN_RX_DMA_EN   (1<<19)         /* ISDN receive DMA enable */
+
+/*
+ * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
+ * defined here.  The rest is defined in system-specific headers.
+ */
+#define KN0X_IO_SSR_DIAGDN      (1<<15)         /* diagnostic jumper */
+#define KN0X_IO_SSR_SCC_RST     (1<<11)         /* ~SCC0,1 (Z85C30) reset */
+#define KN0X_IO_SSR_RTC_RST     (1<<10)         /* ~RTC (DS1287) reset */
+#define KN0X_IO_SSR_ASC_RST     (1<<9)          /* ~ASC (NCR53C94) reset */
+#define KN0X_IO_SSR_LANCE_RST   (1<<8)          /* ~LANCE (Am7990) reset */
+
+#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/arch/mips/include/asm/dec/ioasic_ints.h b/arch/mips/include/asm/dec/ioasic_ints.h
new file mode 100644
index 000000000..9aaa98696
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_ints.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the interrupt related bits in the I/O ASIC
+ * interrupt status register (and the interrupt mask register, of course)
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_IOASIC_INTS_H
+#define __ASM_DEC_IOASIC_INTS_H
+
+/*
+ * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
+ * and thus are common to all I/O ASIC machines.  The exception is
+ * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
+ * unused) and has a different SCC wiring.
+ */
+                                        /* all systems */
+#define IO_INR_SCC0A_TXDMA      31      /* SCC0A transmit page end */
+#define IO_INR_SCC0A_TXERR      30      /* SCC0A transmit memory read error */
+#define IO_INR_SCC0A_RXDMA      29      /* SCC0A receive half page */
+#define IO_INR_SCC0A_RXERR      28      /* SCC0A receive overrun */
+#define IO_INR_ASC_DMA          19      /* ASC buffer pointer loaded */
+#define IO_INR_ASC_ERR          18      /* ASC page overrun */
+#define IO_INR_ASC_MERR         17      /* ASC memory read error */
+#define IO_INR_LANCE_MERR       16      /* LANCE memory read error */
+
+                                        /* except Maxine */
+#define IO_INR_SCC1A_TXDMA      27      /* SCC1A transmit page end */
+#define IO_INR_SCC1A_TXERR      26      /* SCC1A transmit memory read error */
+#define IO_INR_SCC1A_RXDMA      25      /* SCC1A receive half page */
+#define IO_INR_SCC1A_RXERR      24      /* SCC1A receive overrun */
+#define IO_INR_RES_23           23      /* unused */
+#define IO_INR_RES_22           22      /* unused */
+#define IO_INR_RES_21           21      /* unused */
+#define IO_INR_RES_20           20      /* unused */
+
+                                        /* Maxine */
+#define IO_INR_AB_TXDMA         27      /* ACCESS.bus transmit page end */
+#define IO_INR_AB_TXERR         26      /* ACCESS.bus xmit memory read error */
+#define IO_INR_AB_RXDMA         25      /* ACCESS.bus receive half page */
+#define IO_INR_AB_RXERR         24      /* ACCESS.bus receive overrun */
+#define IO_INR_FLOPPY_ERR       23      /* FDC error */
+#define IO_INR_ISDN_TXDMA       22      /* ISDN xmit buffer pointer loaded */
+#define IO_INR_ISDN_RXDMA       21      /* ISDN recv buffer pointer loaded */
+#define IO_INR_ISDN_ERR         20      /* ISDN memory read/overrun error */
+
+#define IO_INR_DMA              16      /* first DMA IRQ */
+
+/*
+ * The lower 16 bits are system-specific and thus defined in
+ * system-specific headers.
+ */
+
+
+#define IO_IRQ_BASE             8       /* first IRQ assigned to I/O ASIC */
+#define IO_IRQ_LINES            32      /* number of I/O ASIC interrupts */
+
+#define IO_IRQ_NR(n)            ((n) + IO_IRQ_BASE)
+#define IO_IRQ_MASK(n)          (1 << (n))
+#define IO_IRQ_ALL              0x0000ffff
+#define IO_IRQ_DMA              0xffff0000
+
+#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
new file mode 100644
index 000000000..88d9ffd74
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -0,0 +1,89 @@
+/*
+ * Hardware info about DECstation DS2100/3100 systems (otherwise known as
+ * pmin/pmax or KN01).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN01_H
+#define __ASM_MIPS_DEC_KN01_H
+
+#define KN01_SLOT_BASE  0x10000000
+#define KN01_SLOT_SIZE  0x01000000
+
+/*
+ * Address ranges for devices.
+ */
+#define KN01_PMASK      (0*KN01_SLOT_SIZE)      /* color plane mask */
+#define KN01_PCC        (1*KN01_SLOT_SIZE)      /* PCC (DC503) cursor */
+#define KN01_VDAC       (2*KN01_SLOT_SIZE)      /* color map */
+#define KN01_RES_3      (3*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_4      (4*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_5      (5*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_6      (6*KN01_SLOT_SIZE)      /* unused */
+#define KN01_ERRADDR    (7*KN01_SLOT_SIZE)      /* write error address */
+#define KN01_LANCE      (8*KN01_SLOT_SIZE)      /* LANCE (Am7990) Ethernet */
+#define KN01_LANCE_MEM  (9*KN01_SLOT_SIZE)      /* LANCE buffer memory */
+#define KN01_SII        (10*KN01_SLOT_SIZE)     /* SII (DC7061) SCSI */
+#define KN01_SII_MEM    (11*KN01_SLOT_SIZE)     /* SII buffer memory */
+#define KN01_DZ11       (12*KN01_SLOT_SIZE)     /* DZ11 (DC7085) serial */
+#define KN01_RTC        (13*KN01_SLOT_SIZE)     /* DS1287 RTC (bytes #0) */
+#define KN01_ESAR       (13*KN01_SLOT_SIZE)     /* MAC address (bytes #1) */
+#define KN01_CSR        (14*KN01_SLOT_SIZE)     /* system ctrl & status reg */
+#define KN01_SYS_ROM    (15*KN01_SLOT_SIZE)     /* system board ROM */
+
+
+/*
+ * Frame buffer memory address.
+ */
+#define KN01_VFB_MEM    0x0fc00000
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN01_CPU_INR_BUS        6       /* memory, I/O bus read/write errors */
+#define KN01_CPU_INR_VIDEO      6       /* PCC area detect #2 */
+#define KN01_CPU_INR_RTC        5       /* DS1287 RTC */
+#define KN01_CPU_INR_DZ11       4       /* DZ11 (DC7085) serial */
+#define KN01_CPU_INR_LANCE      3       /* LANCE (Am7990) Ethernet */
+#define KN01_CPU_INR_SII        2       /* SII (DC7061) SCSI */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN01_CSR_MNFMOD         (1<<15) /* MNFMOD manufacturing jumper */
+#define KN01_CSR_STATUS         (1<<14) /* self-test result status output */
+#define KN01_CSR_PARDIS         (1<<13) /* parity error disable */
+#define KN01_CSR_CRSRTST        (1<<12) /* PCC test output */
+#define KN01_CSR_MONO           (1<<11) /* mono/color fb SIMM installed */
+#define KN01_CSR_MEMERR         (1<<10) /* write timeout error status & ack*/
+#define KN01_CSR_VINT           (1<<9)  /* PCC area detect #2 status & ack */
+#define KN01_CSR_TXDIS          (1<<8)  /* DZ11 transmit disable */
+#define KN01_CSR_VBGTRG         (1<<2)  /* blue DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRG         (1<<1)  /* red DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
+#define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+extern u16 cached_kn01_csr;
+
+extern void dec_kn01_be_init(void);
+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/arch/mips/include/asm/dec/kn02.h b/arch/mips/include/asm/dec/kn02.h
new file mode 100644
index 000000000..93430b5f4
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02.h
@@ -0,0 +1,91 @@
+/*
+ * Hardware info about DECstation 5000/200 systems (otherwise known as
+ * 3max or KN02).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN02_H
+#define __ASM_MIPS_DEC_KN02_H
+
+#define KN02_SLOT_BASE  0x1fc00000
+#define KN02_SLOT_SIZE  0x00080000
+
+/*
+ * Address ranges decoded by the "system slot" logic for onboard devices.
+ */
+#define KN02_SYS_ROM    (0*KN02_SLOT_SIZE)      /* system board ROM */
+#define KN02_RES_1      (1*KN02_SLOT_SIZE)      /* unused */
+#define KN02_CHKSYN     (2*KN02_SLOT_SIZE)      /* ECC syndrome */
+#define KN02_ERRADDR    (3*KN02_SLOT_SIZE)      /* bus error address */
+#define KN02_DZ11       (4*KN02_SLOT_SIZE)      /* DZ11 (DC7085) serial */
+#define KN02_RTC        (5*KN02_SLOT_SIZE)      /* DS1287 RTC */
+#define KN02_CSR        (6*KN02_SLOT_SIZE)      /* system ctrl & status reg */
+#define KN02_SYS_ROM_7  (7*KN02_SLOT_SIZE)      /* system board ROM (alias) */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN02_CSR_RES_28         (0xf<<28)       /* unused */
+#define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
+#define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
+#define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
+#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN02_CSR_LEDIAG         (1<<12)         /* ECC diagn. latch strobe */
+#define KN02_CSR_TXDIS          (1<<11)         /* DZ11 transmit disable */
+#define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
+#define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
+#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02_CPU_INR_RES_6      6       /* unused */
+#define KN02_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN02_CPU_INR_RES_4      4       /* unused */
+#define KN02_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN02_CPU_INR_CASCADE    2       /* CSR cascade */
+
+/*
+ * CSR interrupt bits.
+ */
+#define KN02_CSR_INR_DZ11       7       /* DZ11 (DC7085) serial */
+#define KN02_CSR_INR_LANCE      6       /* LANCE (Am7990) Ethernet */
+#define KN02_CSR_INR_ASC        5       /* ASC (NCR53C94) SCSI */
+#define KN02_CSR_INR_RES_4      4       /* unused */
+#define KN02_CSR_INR_RES_3      3       /* unused */
+#define KN02_CSR_INR_TC2        2       /* TURBOchannel slot #2 */
+#define KN02_CSR_INR_TC1        1       /* TURBOchannel slot #1 */
+#define KN02_CSR_INR_TC0        0       /* TURBOchannel slot #0 */
+
+
+#define KN02_IRQ_BASE           8       /* first IRQ assigned to CSR */
+#define KN02_IRQ_LINES          8       /* number of CSR interrupts */
+
+#define KN02_IRQ_NR(n)          ((n) + KN02_IRQ_BASE)
+#define KN02_IRQ_MASK(n)        (1 << (n))
+#define KN02_IRQ_ALL            0xff
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+extern u32 cached_kn02_csr;
+extern void init_kn02_irqs(int base);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/arch/mips/include/asm/dec/kn02ba.h b/arch/mips/include/asm/dec/kn02ba.h
new file mode 100644
index 000000000..81a6cc1c5
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ba.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/kn02ba.h
+ *
+ *      DECstation 5000/1xx (3min or KN02-BA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN02BA_H
+#define __ASM_MIPS_DEC_KN02BA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02BA_CPU_INR_HALT     6       /* HALT button */
+#define KN02BA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02BA_CPU_INR_TC2      4       /* TURBOchannel slot #2 */
+#define KN02BA_CPU_INR_TC1      3       /* TURBOchannel slot #1 */
+#define KN02BA_CPU_INR_TC0      2       /* TURBOchannel slot #0 */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02BA_IO_INR_RES_15    15      /* unused */
+#define KN02BA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02BA_IO_INR_RES_13    13      /* unused */
+#define KN02BA_IO_INR_BUS       12      /* memory, I/O bus read/write errors */
+#define KN02BA_IO_INR_RES_11    11      /* unused */
+#define KN02BA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02BA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02BA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02BA_IO_INR_SCC1      7       /* SCC (Z85C30) serial #1 */
+#define KN02BA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02BA_IO_INR_RTC       5       /* DS1287 RTC */
+#define KN02BA_IO_INR_PSU       4       /* power supply unit warning */
+#define KN02BA_IO_INR_RES_3     3       /* unused */
+#define KN02BA_IO_INR_ASC_DATA  2       /* SCSI data ready (for PIO) */
+#define KN02BA_IO_INR_PBNC      1       /* ~HALT button debouncer */
+#define KN02BA_IO_INR_PBNO      0       /* HALT button debouncer */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02BA_MER_RES_27       (1<<27)         /* unused */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02BA_MSR_RES_17       (0x3ff<<17)     /* unused */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN02BA_IO_SSR_TXDIS1    (1<<14)         /* SCC1 transmit disable */
+#define KN02BA_IO_SSR_TXDIS0    (1<<13)         /* SCC0 transmit disable */
+#define KN02BA_IO_SSR_RES_12    (1<<12)         /* unused */
+
+#define KN02BA_IO_SSR_LEDS      (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
new file mode 100644
index 000000000..a466101eb
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/kn02ca.h
+ *
+ *      Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN02CA_H
+#define __ASM_MIPS_DEC_KN02CA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02CA_CPU_INR_HALT     6       /* HALT from ACCESS.Bus */
+#define KN02CA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02CA_CPU_INR_BUS      4       /* memory, I/O bus read/write errors */
+#define KN02CA_CPU_INR_RTC      3       /* DS1287 RTC */
+#define KN02CA_CPU_INR_TIMER    2       /* ARC periodic timer */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02CA_IO_INR_FLOPPY    15      /* 82077 FDC */
+#define KN02CA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02CA_IO_INR_POWERON   13      /* (*) ACCESS.Bus/power-on reset */
+#define KN02CA_IO_INR_TC0       12      /* TURBOchannel slot #0 */
+#define KN02CA_IO_INR_TIMER     12      /* ARC periodic timer (?) */
+#define KN02CA_IO_INR_ISDN      11      /* Am79C30A ISDN */
+#define KN02CA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02CA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02CA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02CA_IO_INR_HDFLOPPY  7       /* (*) HD (1.44MB) floppy status */
+#define KN02CA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02CA_IO_INR_TC1       5       /* TURBOchannel slot #1 */
+#define KN02CA_IO_INR_XDFLOPPY  4       /* (*) XD (2.88MB) floppy status */
+#define KN02CA_IO_INR_VIDEO     3       /* framebuffer */
+#define KN02CA_IO_INR_XVIDEO    2       /* ~framebuffer */
+#define KN02CA_IO_INR_AB_XMIT   1       /* ACCESS.bus transmit */
+#define KN02CA_IO_INR_AB_RECV   0       /* ACCESS.bus receive */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02CA_MER_INTR         (1<<27)         /* ARC IRQ status & ack */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02CA_MSR_INTREN       (1<<26)         /* ARC periodic IRQ enable */
+#define KN02CA_MSR_MS10EN       (1<<25)         /* 10/1ms IRQ period select */
+#define KN02CA_MSR_PFORCE       (0xf<<21)       /* byte lane error force */
+#define KN02CA_MSR_MABEN        (1<<20)         /* A side VFB address enable */
+#define KN02CA_MSR_LASTBANK     (0x7<<17)       /* onboard RAM bank # */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03CA_IO_SSR_RES_14    (1<<14)         /* unused */
+#define KN03CA_IO_SSR_RES_13    (1<<13)         /* unused */
+#define KN03CA_IO_SSR_ISDN_RST  (1<<12)         /* ~ISDN (Am79C30A) reset */
+
+#define KN03CA_IO_SSR_FLOPPY_RST (1<<7)         /* ~FDC (82077) reset */
+#define KN03CA_IO_SSR_VIDEO_RST (1<<6)          /* ~framebuffer reset */
+#define KN03CA_IO_SSR_AB_RST    (1<<5)          /* ACCESS.bus reset */
+#define KN03CA_IO_SSR_RES_4     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_3     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_2     (1<<2)          /* unused */
+#define KN03CA_IO_SSR_RES_1     (1<<1)          /* unused */
+#define KN03CA_IO_SSR_LED       (1<<0)          /* power LED */
+
+#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/arch/mips/include/asm/dec/kn02xa.h b/arch/mips/include/asm/dec/kn02xa.h
new file mode 100644
index 000000000..b56b4577f
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02xa.h
@@ -0,0 +1,84 @@
+/*
+ * Hardware info common to DECstation 5000/1xx systems (otherwise
+ * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
+ * (otherwise known as maxine or kn02ca).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
+ *
+ * These are addresses which have to be known early in the boot process.
+ * For other addresses refer to tc.h, ioasic_addrs.h and friends.
+ */
+#ifndef __ASM_MIPS_DEC_KN02XA_H
+#define __ASM_MIPS_DEC_KN02XA_H
+
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN02XA_SLOT_BASE        0x1c000000
+
+/*
+ * Memory control ASIC registers.
+ */
+#define KN02XA_MER              0x0c400000      /* memory error register */
+#define KN02XA_MSR              0x0c800000      /* memory size register */
+
+/*
+ * CPU control ASIC registers.
+ */
+#define KN02XA_MEM_CONF         0x0e000000      /* write timeout config */
+#define KN02XA_EAR              0x0e000004      /* error address register */
+#define KN02XA_BOOT0            0x0e000008      /* boot 0 register */
+#define KN02XA_MEM_INTR         0x0e00000c      /* write err IRQ stat & ack */
+
+/*
+ * Memory Error Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MER_RES_28       (0xf<<28)       /* unused */
+#define KN02XA_MER_RES_17       (0x3ff<<17)     /* unused */
+#define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
+#define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
+#define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
+#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
+#define KN02XA_MER_RES_12       (1<<12)         /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
+#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
+#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
+#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
+#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
+#define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
+
+/*
+ * Memory Size Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MSR_RES_27       (0x1f<<27)      /* unused */
+#define KN02XA_MSR_RES_14       (0x7<<14)       /* unused */
+#define KN02XA_MSR_SIZE         (1<<13)         /* 16M/4M stride */
+#define KN02XA_MSR_RES_0        (0x1fff<<0)     /* unused */
+
+/*
+ * Error Address Register bits.
+ */
+#define KN02XA_EAR_RES_29       (0x7<<29)       /* unused */
+#define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
+#define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_kn02xa_be_init(void);
+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/arch/mips/include/asm/dec/kn03.h b/arch/mips/include/asm/dec/kn03.h
new file mode 100644
index 000000000..edede923f
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn03.h
@@ -0,0 +1,74 @@
+/*
+ * Hardware info about DECstation 5000/2x0 systems (otherwise known as
+ * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
+ * differ mechanically but are otherwise identical (both are known as
+ * KN03).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN03_H
+#define __ASM_MIPS_DEC_KN03_H
+
+#include <asm/dec/ecc.h>
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN03_SLOT_BASE          0x1f800000
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN03_CPU_INR_HALT       6       /* HALT button */
+#define KN03_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN03_CPU_INR_RES_4      4       /* unused */
+#define KN03_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN03_CPU_INR_CASCADE    2       /* I/O ASIC cascade */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN03_IO_INR_3MAXP       15      /* (*) 3max+/bigmax ID */
+#define KN03_IO_INR_NVRAM       14      /* (*) NVRAM clear jumper */
+#define KN03_IO_INR_TC2         13      /* TURBOchannel slot #2 */
+#define KN03_IO_INR_TC1         12      /* TURBOchannel slot #1 */
+#define KN03_IO_INR_TC0         11      /* TURBOchannel slot #0 */
+#define KN03_IO_INR_NRMOD       10      /* (*) NRMOD manufacturing jumper */
+#define KN03_IO_INR_ASC         9       /* ASC (NCR53C94) SCSI */
+#define KN03_IO_INR_LANCE       8       /* LANCE (Am7990) Ethernet */
+#define KN03_IO_INR_SCC1        7       /* SCC (Z85C30) serial #1 */
+#define KN03_IO_INR_SCC0        6       /* SCC (Z85C30) serial #0 */
+#define KN03_IO_INR_RTC         5       /* DS1287 RTC */
+#define KN03_IO_INR_PSU         4       /* power supply unit warning */
+#define KN03_IO_INR_RES_3       3       /* unused */
+#define KN03_IO_INR_ASC_DATA    2       /* SCSI data ready (for PIO) */
+#define KN03_IO_INR_PBNC        1       /* ~HALT button debouncer */
+#define KN03_IO_INR_PBNO        0       /* HALT button debouncer */
+
+
+/*
+ * Memory Control Register bits.
+ */
+#define KN03_MCR_RES_16         (0xffff<<16)    /* unused */
+#define KN03_MCR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN03_MCR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN03_MCR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN03_MCR_RES_11         (0x3<<12)       /* unused */
+#define KN03_MCR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN03_MCR_RES_7          (0x7<<7)        /* unused */
+#define KN03_MCR_CHECK          (0x7f<<0)       /* diagnostic check bits */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03_IO_SSR_TXDIS1      (1<<14)         /* SCC1 transmit disable */
+#define KN03_IO_SSR_TXDIS0      (1<<13)         /* SCC0 transmit disable */
+#define KN03_IO_SSR_RES_12      (1<<12)         /* unused */
+
+#define KN03_IO_SSR_LEDS        (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h
new file mode 100644
index 000000000..3b1524e9f
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn05.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/kn05.h
+ *
+ *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
+ *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
+ *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
+ *      definitions.
+ *
+ *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
+ *
+ *      WARNING!  All this information is pure guesswork based on the
+ *      ROM.  It is provided here in hope it will give someone some
+ *      food for thought.  No documentation for the KN05 nor the KN04
+ *      module has been located so far.
+ */
+#ifndef __ASM_MIPS_DEC_KN05_H
+#define __ASM_MIPS_DEC_KN05_H
+
+#include <asm/dec/ioasic_addrs.h>
+
+/*
+ * The oncard MB (Memory Buffer) ASIC provides an additional address
+ * decoder.  Certain address ranges within the "high" 16 slots are
+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
+ * Others are handled locally.  "Low" slots are always passed.
+ */
+#define KN4K_SLOT_BASE  0x1fc00000
+
+#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
+#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
+#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
+#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
+#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
+#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
+
+/*
+ * MB ASIC interrupt bits.
+ */
+#define KN4K_MB_INR_MB          4       /* ??? */
+#define KN4K_MB_INR_MT          3       /* memory, I/O bus read/write errors */
+#define KN4K_MB_INR_RES_2       2       /* unused */
+#define KN4K_MB_INR_RTC         1       /* RTC */
+#define KN4K_MB_INR_TC          0       /* I/O ASIC cascade */
+
+/*
+ * Bits for the MB interrupt register.
+ * The register appears read-only.
+ */
+#define KN4K_MB_INT_IRQ         (0x1f<<0)       /* CPU Int[4:0] status. */
+#define KN4K_MB_INT_IRQ_N(n)    (1<<(n))        /* Individual status bits. */
+
+/*
+ * Bits for the MB control & status register.
+ * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
+ */
+#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
+#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
+#define KN4K_MB_CSR_MSK_N(n)    (1<<((n)+16))   /* Individual mask bits. */
+#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_W           (1<<31)         /* ??? */
+
+#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/arch/mips/include/asm/dec/kn230.h b/arch/mips/include/asm/dec/kn230.h
new file mode 100644
index 000000000..cb13a7799
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn230.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/kn230.h
+ *
+ *      DECsystem 5100 (MIPSmate or KN230) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN230_H
+#define __ASM_MIPS_DEC_KN230_H
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN230_CPU_INR_HALT      6       /* HALT button */
+#define KN230_CPU_INR_BUS       5       /* memory, I/O bus read/write errors */
+#define KN230_CPU_INR_RTC       4       /* DS1287 RTC */
+#define KN230_CPU_INR_SII       3       /* SII (DC7061) SCSI */
+#define KN230_CPU_INR_LANCE     3       /* LANCE (Am7990) Ethernet */
+#define KN230_CPU_INR_DZ11      2       /* DZ11 (DC7085) serial */
+
+#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/arch/mips/include/asm/dec/machtype.h b/arch/mips/include/asm/dec/machtype.h
new file mode 100644
index 000000000..a6ecdebc4
--- /dev/null
+++ b/arch/mips/include/asm/dec/machtype.h
@@ -0,0 +1,27 @@
+/*
+ * Various machine type macros
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998, 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_DEC_MACHTYPE_H
+#define __ASM_DEC_MACHTYPE_H
+
+#include <asm/bootinfo.h>
+
+#define TURBOCHANNEL    (mips_machtype == MACH_DS5000_200 || \
+                         mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#define IOASIC          (mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#endif
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
new file mode 100644
index 000000000..1e1247add
--- /dev/null
+++ b/arch/mips/include/asm/dec/prom.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/prom.h
+ *
+ *      DECstation PROM interface.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ *
+ *      Based on arch/mips/dec/prom/prom.h by the Anonymous.
+ */
+#ifndef _ASM_DEC_PROM_H
+#define _ASM_DEC_PROM_H
+
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+/*
+ * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
+ * Many of these will work for MIPSen as well!
+ */
+#define VEC_RESET               (u64 *)CKSEG1ADDR(0x1fc00000)
+                                                        /* Prom base address */
+
+#define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
+
+#define PMAX_PROM_HALT          PMAX_PROM_ENTRY(2)      /* valid on MIPSen */
+#define PMAX_PROM_AUTOBOOT      PMAX_PROM_ENTRY(5)      /* valid on MIPSen */
+#define PMAX_PROM_OPEN          PMAX_PROM_ENTRY(6)
+#define PMAX_PROM_READ          PMAX_PROM_ENTRY(7)
+#define PMAX_PROM_CLOSE         PMAX_PROM_ENTRY(10)
+#define PMAX_PROM_LSEEK         PMAX_PROM_ENTRY(11)
+#define PMAX_PROM_GETCHAR       PMAX_PROM_ENTRY(12)
+#define PMAX_PROM_PUTCHAR       PMAX_PROM_ENTRY(13)     /* 12 on MIPSen */
+#define PMAX_PROM_GETS          PMAX_PROM_ENTRY(15)
+#define PMAX_PROM_PRINTF        PMAX_PROM_ENTRY(17)
+#define PMAX_PROM_GETENV        PMAX_PROM_ENTRY(33)     /* valid on MIPSen */
+
+
+/*
+ * Magic number indicating REX PROM available on DECstation.  Found in
+ * register a2 on transfer of control to program from PROM.
+ */
+#define REX_PROM_MAGIC          0x30464354
+
+/* KN04 and KN05 are REX PROMs, so only do the check for R3k systems.  */
+static inline bool prom_is_rex(u32 magic)
+{
+        return !IS_ENABLED(CONFIG_CPU_R3000) || magic == REX_PROM_MAGIC;
+}
+
+/*
+ * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
+ * DS5000/2x0.
+ */
+#define REX_PROM_GETBITMAP      0x84/4  /* get mem bitmap */
+#define REX_PROM_GETCHAR        0x24/4  /* getch() */
+#define REX_PROM_GETENV         0x64/4  /* get env. variable */
+#define REX_PROM_GETSYSID       0x80/4  /* get system id */
+#define REX_PROM_GETTCINFO      0xa4/4
+#define REX_PROM_PRINTF         0x30/4  /* printf() */
+#define REX_PROM_SLOTADDR       0x6c/4  /* slotaddr */
+#define REX_PROM_BOOTINIT       0x54/4  /* open() */
+#define REX_PROM_BOOTREAD       0x58/4  /* read() */
+#define REX_PROM_CLEARCACHE     0x7c/4
+
+
+/*
+ * Used by rex_getbitmap().
+ */
+typedef struct {
+        int pagesize;
+        unsigned char bitmap[0];
+} memmap;
+
+
+/*
+ * Function pointers as read from a PROM's callback vector.
+ */
+extern int (*__rex_bootinit)(void);
+extern int (*__rex_bootread)(void);
+extern int (*__rex_getbitmap)(memmap *);
+extern unsigned long *(*__rex_slot_address)(int);
+extern void *(*__rex_gettcinfo)(void);
+extern int (*__rex_getsysid)(void);
+extern void (*__rex_clear_cache)(void);
+
+extern int (*__prom_getchar)(void);
+extern char *(*__prom_getenv)(char *);
+extern int (*__prom_printf)(char *, ...);
+
+extern int (*__pmax_open)(char*, int);
+extern int (*__pmax_lseek)(int, long, int);
+extern int (*__pmax_read)(int, void *, int);
+extern int (*__pmax_close)(int);
+
+
+#ifdef CONFIG_64BIT
+
+/*
+ * On MIPS64 we have to call PROM functions via a helper
+ * dispatcher to accommodate ABI incompatibilities.
+ */
+#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
+                                 __asm__(#fun " = call_o32")
+
+int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *));
+int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *));
+int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *));
+unsigned long *__DEC_PROM_O32(_rex_slot_address,
+                             (unsigned long *(*)(int), void *, int));
+void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *));
+int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *));
+void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *));
+
+int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *));
+char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *));
+int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...));
+
+
+#define rex_bootinit()          _rex_bootinit(__rex_bootinit, NULL)
+#define rex_bootread()          _rex_bootread(__rex_bootread, NULL)
+#define rex_getbitmap(x)        _rex_getbitmap(__rex_getbitmap, NULL, x)
+#define rex_slot_address(x)     _rex_slot_address(__rex_slot_address, NULL, x)
+#define rex_gettcinfo()         _rex_gettcinfo(__rex_gettcinfo, NULL)
+#define rex_getsysid()          _rex_getsysid(__rex_getsysid, NULL)
+#define rex_clear_cache()       _rex_clear_cache(__rex_clear_cache, NULL)
+
+#define prom_getchar()          _prom_getchar(__prom_getchar, NULL)
+#define prom_getenv(x)          _prom_getenv(__prom_getenv, NULL, x)
+#define prom_printf(x...)       _prom_printf(__prom_printf, NULL, x)
+
+#else /* !CONFIG_64BIT */
+
+/*
+ * On plain MIPS we just call PROM functions directly.
+ */
+#define rex_bootinit            __rex_bootinit
+#define rex_bootread            __rex_bootread
+#define rex_getbitmap           __rex_getbitmap
+#define rex_slot_address        __rex_slot_address
+#define rex_gettcinfo           __rex_gettcinfo
+#define rex_getsysid            __rex_getsysid
+#define rex_clear_cache         __rex_clear_cache
+
+#define prom_getchar            __prom_getchar
+#define prom_getenv             __prom_getenv
+#define prom_printf             __prom_printf
+
+#define pmax_open               __pmax_open
+#define pmax_lseek              __pmax_lseek
+#define pmax_read               __pmax_read
+#define pmax_close              __pmax_close
+
+#endif /* !CONFIG_64BIT */
+
+
+extern void prom_meminit(u32);
+extern void prom_identify_arch(u32);
+extern void prom_init_cmdline(s32, s32 *, u32);
+
+extern void register_prom_console(void);
+extern void unregister_prom_console(void);
+
+#endif /* _ASM_DEC_PROM_H */
diff --git a/arch/mips/include/asm/dec/system.h b/arch/mips/include/asm/dec/system.h
new file mode 100644
index 000000000..d0873fd4e
--- /dev/null
+++ b/arch/mips/include/asm/dec/system.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/dec/system.h
+ *
+ *      Generic DECstation/DECsystem bits.
+ *
+ *      Copyright (C) 2005, 2006  Maciej W. Rozycki
+ */
+#ifndef __ASM_DEC_SYSTEM_H
+#define __ASM_DEC_SYSTEM_H
+
+extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
+extern int dec_tc_bus;
+
+#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
new file mode 100644
index 000000000..dc0a5f77a
--- /dev/null
+++ b/arch/mips/include/asm/delay.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf Electronics
+ * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_DELAY_H
+#define _ASM_DELAY_H
+
+#include <linux/param.h>
+
+extern void __delay(unsigned long loops);
+extern void __ndelay(unsigned long ns);
+extern void __udelay(unsigned long us);
+
+#define ndelay(ns) __ndelay(ns)
+#define udelay(us) __udelay(us)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS   1
+#elif HZ <= 200
+#define MAX_UDELAY_MS   5
+#else
+#define MAX_UDELAY_MS   (1000 / HZ)
+#endif
+
+#endif /* _ASM_DELAY_H */
diff --git a/arch/mips/include/asm/div64.h b/arch/mips/include/asm/div64.h
new file mode 100644
index 000000000..ceece76fc
--- /dev/null
+++ b/arch/mips/include/asm/div64.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2000, 2004, 2021  Maciej W. Rozycki
+ * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_DIV64_H
+#define __ASM_DIV64_H
+
+#include <asm/bitsperlong.h>
+
+#if BITS_PER_LONG == 32
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define do_div64_32(res, high, low, base) ({                            \
+        unsigned long __cf, __tmp, __tmp2, __i;                         \
+        unsigned long __quot32, __mod32;                                \
+                                                                        \
+        __asm__(                                                        \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    noreorder                               \n"     \
+        "       move    %2, $0                                  \n"     \
+        "       move    %3, $0                                  \n"     \
+        "       b       1f                                      \n"     \
+        "        li     %4, 0x21                                \n"     \
+        "0:                                                     \n"     \
+        "       sll     $1, %0, 0x1                             \n"     \
+        "       srl     %3, %0, 0x1f                            \n"     \
+        "       or      %0, $1, %5                              \n"     \
+        "       sll     %1, %1, 0x1                             \n"     \
+        "       sll     %2, %2, 0x1                             \n"     \
+        "1:                                                     \n"     \
+        "       bnez    %3, 2f                                  \n"     \
+        "        sltu   %5, %0, %z6                             \n"     \
+        "       bnez    %5, 3f                                  \n"     \
+        "2:                                                     \n"     \
+        "        addiu  %4, %4, -1                              \n"     \
+        "       subu    %0, %0, %z6                             \n"     \
+        "       addiu   %2, %2, 1                               \n"     \
+        "3:                                                     \n"     \
+        "       bnez    %4, 0b                                  \n"     \
+        "        srl    %5, %1, 0x1f                            \n"     \
+        "       .set    pop"                                            \
+        : "=&r" (__mod32), "=&r" (__tmp),                               \
+          "=&r" (__quot32), "=&r" (__cf),                               \
+          "=&r" (__i), "=&r" (__tmp2)                                   \
+        : "Jr" (base), "0" (high), "1" (low));                          \
+                                                                        \
+        (res) = __quot32;                                               \
+        __mod32;                                                        \
+})
+
+#define __div64_32(n, base) ({                                          \
+        unsigned long __upper, __low, __high, __radix;                  \
+        unsigned long long __quot;                                      \
+        unsigned long long __div;                                       \
+        unsigned long __mod;                                            \
+                                                                        \
+        __div = (*n);                                                   \
+        __radix = (base);                                               \
+                                                                        \
+        __high = __div >> 32;                                           \
+        __low = __div;                                                  \
+                                                                        \
+        if (__high < __radix) {                                         \
+                __upper = __high;                                       \
+                __high = 0;                                             \
+        } else {                                                        \
+                __upper = __high % __radix;                             \
+                __high /= __radix;                                      \
+        }                                                               \
+                                                                        \
+        __mod = do_div64_32(__low, __upper, __low, __radix);            \
+                                                                        \
+        __quot = __high;                                                \
+        __quot = __quot << 32 | __low;                                  \
+        (*n) = __quot;                                                  \
+        __mod;                                                          \
+})
+
+#endif /* BITS_PER_LONG == 32 */
+
+#include <asm-generic/div64.h>
+
+#endif /* __ASM_DIV64_H */
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
new file mode 100644
index 000000000..5eaa1fcc8
--- /dev/null
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+#ifndef __ASM_DMA_COHERENCE_H
+#define __ASM_DMA_COHERENCE_H
+
+enum coherent_io_user_state {
+        IO_COHERENCE_DEFAULT,
+        IO_COHERENCE_ENABLED,
+        IO_COHERENCE_DISABLED,
+};
+
+#if defined(CONFIG_DMA_PERDEV_COHERENT)
+/* Don't provide (hw_)coherentio to avoid misuse */
+#elif defined(CONFIG_DMA_MAYBE_COHERENT)
+extern enum coherent_io_user_state coherentio;
+extern int hw_coherentio;
+
+static inline bool dev_is_dma_coherent(struct device *dev)
+{
+        return coherentio == IO_COHERENCE_ENABLED ||
+                (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
+}
+#else
+#ifdef CONFIG_DMA_NONCOHERENT
+#define coherentio      IO_COHERENCE_DISABLED
+#else
+#define coherentio      IO_COHERENCE_ENABLED
+#endif
+#define hw_coherentio   0
+#endif /* CONFIG_DMA_MAYBE_COHERENT */
+
+#endif
diff --git a/arch/mips/include/asm/dma-direct.h b/arch/mips/include/asm/dma-direct.h
new file mode 100644
index 000000000..9a6401183
--- /dev/null
+++ b/arch/mips/include/asm/dma-direct.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MIPS_DMA_DIRECT_H
+#define _MIPS_DMA_DIRECT_H 1
+
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+#endif /* _MIPS_DMA_DIRECT_H */
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
new file mode 100644
index 000000000..34de7b17b
--- /dev/null
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+
+#include <linux/swiotlb.h>
+
+extern const struct dma_map_ops jazz_dma_ops;
+
+static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+#if defined(CONFIG_MACH_JAZZ)
+        return &jazz_dma_ops;
+#else
+        return NULL;
+#endif
+}
+
+#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
new file mode 100644
index 000000000..be726b943
--- /dev/null
+++ b/arch/mips/include/asm/dma.h
@@ -0,0 +1,318 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ *
+ * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
+ * and can only be used for expansion cards. Onboard DMA controllers, such
+ * as the R4030 on Jazz boards behave totally different!
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <asm/io.h>                     /* need byte IO */
+#include <linux/spinlock.h>             /* And spinlocks */
+#include <linux/delay.h>
+
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb        outb_p
+#else
+#define dma_outb        outb
+#endif
+
+#define dma_inb         inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
+#define MAX_DMA_CHANNELS        8
+#endif
+
+/*
+ * The maximum address in KSEG0 that we can perform a DMA transfer to on this
+ * platform.  This describes only the PC style part of the DMA logic like on
+ * Deskstations or Acer PICA but not the much more versatile DMA logic used
+ * for the local devices on Acer PICA or Magnums.
+ */
+#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
+/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
+#define MAX_DMA_ADDRESS         PAGE_OFFSET
+#else
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
+#endif
+#define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+
+#ifndef MAX_DMA32_PFN
+#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
+#endif
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            0x08    /* command register (w) */
+#define DMA1_STAT_REG           0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG           0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            0xD0    /* command register (w) */
+#define DMA2_STAT_REG           0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG           0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_PAGE_0              0x87    /* DMA page registers */
+#define DMA_PAGE_1              0x83
+#define DMA_PAGE_2              0x81
+#define DMA_PAGE_3              0x82
+#define DMA_PAGE_5              0x8B
+#define DMA_PAGE_6              0x89
+#define DMA_PAGE_7              0x8A
+
+#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT    0x10
+
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr,  DMA1_MASK_REG);
+        else
+                dma_outb(dmanr & 3,  DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr | 4,  DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(0,  DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0,  DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr<=3)
+                dma_outb(mode | dmanr,  DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+        switch(dmanr) {
+                case 0:
+                        dma_outb(pagenr, DMA_PAGE_0);
+                        break;
+                case 1:
+                        dma_outb(pagenr, DMA_PAGE_1);
+                        break;
+                case 2:
+                        dma_outb(pagenr, DMA_PAGE_2);
+                        break;
+                case 3:
+                        dma_outb(pagenr, DMA_PAGE_3);
+                        break;
+                case 5:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
+                        break;
+                case 6:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
+                        break;
+                case 7:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
+                        break;
+        }
+}
+
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+        set_dma_page(dmanr, a>>16);
+        if (dmanr <= 3)  {
+            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+        }  else  {
+            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+        }
+}
+
+
+/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3)  {
+            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+        } else {
+            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr);       /* release it again */
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* _ASM_DMA_H */
diff --git a/arch/mips/include/asm/dmi.h b/arch/mips/include/asm/dmi.h
new file mode 100644
index 000000000..27415a288
--- /dev/null
+++ b/arch/mips/include/asm/dmi.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_DMI_H
+#define _ASM_DMI_H
+
+#include <linux/io.h>
+#include <linux/memblock.h>
+
+#define dmi_early_remap(x, l)           ioremap_cache(x, l)
+#define dmi_early_unmap(x, l)           iounmap(x)
+#define dmi_remap(x, l)                 ioremap_cache(x, l)
+#define dmi_unmap(x)                    iounmap(x)
+
+/* MIPS initialize DMI scan before SLAB is ready, so we use memblock here */
+#define dmi_alloc(l)                    memblock_alloc_low(l, PAGE_SIZE)
+
+#if defined(CONFIG_MACH_LOONGSON64)
+#define SMBIOS_ENTRY_POINT_SCAN_START   0xFFFE000
+#endif
+
+#endif /* _ASM_DMI_H */
diff --git a/arch/mips/include/asm/ds1287.h b/arch/mips/include/asm/ds1287.h
new file mode 100644
index 000000000..46cfb01f9
--- /dev/null
+++ b/arch/mips/include/asm/ds1287.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  DS1287 timer functions.
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __ASM_DS1287_H
+#define __ASM_DS1287_H
+
+extern int ds1287_timer_state(void);
+extern void ds1287_set_base_clock(unsigned int clock);
+extern int ds1287_clockevent_init(int irq);
+
+#endif
diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h
new file mode 100644
index 000000000..08bfe8fa3
--- /dev/null
+++ b/arch/mips/include/asm/dsemul.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_DSEMUL_H__
+#define __MIPS_ASM_DSEMUL_H__
+
+#include <asm/break.h>
+#include <asm/inst.h>
+
+/* Break instruction with special math emu break code set */
+#define BREAK_MATH(micromips)   (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16))
+
+/* When used as a frame index, indicates the lack of a frame */
+#define BD_EMUFRAME_NONE        ((int)BIT(31))
+
+struct mm_struct;
+struct pt_regs;
+struct task_struct;
+
+/**
+ * mips_dsemul() - 'Emulate' an instruction from a branch delay slot
+ * @regs:       User thread register context.
+ * @ir:         The instruction to be 'emulated'.
+ * @branch_pc:  The PC of the branch instruction.
+ * @cont_pc:    The PC to continue at following 'emulation'.
+ *
+ * Emulate or execute an arbitrary MIPS instruction within the context of
+ * the current user thread. This is used primarily to handle instructions
+ * in the delay slots of emulated branch instructions, for example FP
+ * branch instructions on systems without an FPU.
+ *
+ * Return: Zero on success, negative if ir is a NOP, signal number on failure.
+ */
+extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
+                       unsigned long branch_pc, unsigned long cont_pc);
+
+/**
+ * do_dsemulret() - Return from a delay slot 'emulation' frame
+ * @xcp:        User thread register context.
+ *
+ * Call in response to the BRK_MEMU break instruction used to return to
+ * the kernel from branch delay slot 'emulation' frames following a call
+ * to mips_dsemul(). Restores the user thread PC to the value that was
+ * passed as the cpc parameter to mips_dsemul().
+ *
+ * Return: True if an emulation frame was returned from, else false.
+ */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+extern bool do_dsemulret(struct pt_regs *xcp);
+#else
+static inline bool do_dsemulret(struct pt_regs *xcp)
+{
+        return false;
+}
+#endif
+
+/**
+ * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
+ * @tsk: The task structure associated with the thread
+ *
+ * If the thread @tsk has a branch delay slot 'emulation' frame
+ * allocated to it then free that frame.
+ *
+ * Return: True if a frame was freed, else false.
+ */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+extern bool dsemul_thread_cleanup(struct task_struct *tsk);
+#else
+static inline bool dsemul_thread_cleanup(struct task_struct *tsk)
+{
+        return false;
+}
+#endif
+/**
+ * dsemul_thread_rollback() - Rollback from an 'emulation' frame
+ * @regs:       User thread register context.
+ *
+ * If the current thread, whose register context is represented by @regs,
+ * is executing within a delay slot 'emulation' frame then exit that
+ * frame. The PC will be rolled back to the branch if the instruction
+ * that was being 'emulated' has not yet executed, or advanced to the
+ * continuation PC if it has.
+ *
+ * Return: True if a frame was exited, else false.
+ */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+extern bool dsemul_thread_rollback(struct pt_regs *regs);
+#else
+static inline bool dsemul_thread_rollback(struct pt_regs *regs)
+{
+        return false;
+}
+#endif
+
+/**
+ * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
+ * @mm:         The struct mm_struct to cleanup state for.
+ *
+ * Cleanup state for the given @mm, ensuring that any memory allocated
+ * for delay slot 'emulation' book-keeping is freed. This is to be called
+ * before @mm is freed in order to avoid memory leaks.
+ */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+extern void dsemul_mm_cleanup(struct mm_struct *mm);
+#else
+static inline void dsemul_mm_cleanup(struct mm_struct *mm)
+{
+        /* no-op */
+}
+#endif
+
+#endif /* __MIPS_ASM_DSEMUL_H__ */
diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h
new file mode 100644
index 000000000..77fe0d675
--- /dev/null
+++ b/arch/mips/include/asm/dsp.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2005 Mips Technologies
+ * Author: Chris Dearman, chris@mips.com derived from fpu.h
+ */
+#ifndef _ASM_DSP_H
+#define _ASM_DSP_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+
+#define DSP_DEFAULT     0x00000000
+#define DSP_MASK        0x3f
+
+#define __enable_dsp_hazard()                                           \
+do {                                                                    \
+        asm("_ehb");                                                    \
+} while (0)
+
+static inline void __init_dsp(void)
+{
+        mthi1(0);
+        mtlo1(0);
+        mthi2(0);
+        mtlo2(0);
+        mthi3(0);
+        mtlo3(0);
+        wrdsp(DSP_DEFAULT, DSP_MASK);
+}
+
+static inline void init_dsp(void)
+{
+        if (cpu_has_dsp)
+                __init_dsp();
+}
+
+#define __save_dsp(tsk)                                                 \
+do {                                                                    \
+        tsk->thread.dsp.dspr[0] = mfhi1();                              \
+        tsk->thread.dsp.dspr[1] = mflo1();                              \
+        tsk->thread.dsp.dspr[2] = mfhi2();                              \
+        tsk->thread.dsp.dspr[3] = mflo2();                              \
+        tsk->thread.dsp.dspr[4] = mfhi3();                              \
+        tsk->thread.dsp.dspr[5] = mflo3();                              \
+        tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK);                   \
+} while (0)
+
+#define save_dsp(tsk)                                                   \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(tsk);                                        \
+} while (0)
+
+#define __restore_dsp(tsk)                                              \
+do {                                                                    \
+        mthi1(tsk->thread.dsp.dspr[0]);                                 \
+        mtlo1(tsk->thread.dsp.dspr[1]);                                 \
+        mthi2(tsk->thread.dsp.dspr[2]);                                 \
+        mtlo2(tsk->thread.dsp.dspr[3]);                                 \
+        mthi3(tsk->thread.dsp.dspr[4]);                                 \
+        mtlo3(tsk->thread.dsp.dspr[5]);                                 \
+        wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK);                    \
+} while (0)
+
+#define restore_dsp(tsk)                                                \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(tsk);                                     \
+} while (0)
+
+#define __get_dsp_regs(tsk)                                             \
+({                                                                      \
+        if (tsk == current)                                             \
+                __save_dsp(current);                                    \
+                                                                        \
+        tsk->thread.dsp.dspr;                                           \
+})
+
+#endif /* _ASM_DSP_H */
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
new file mode 100644
index 000000000..c5d147744
--- /dev/null
+++ b/arch/mips/include/asm/edac.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef ASM_EDAC_H
+#define ASM_EDAC_H
+
+#include <asm/compiler.h>
+
+/* ECC atomic, DMA, SMP and interrupt safe scrub function */
+
+static inline void edac_atomic_scrub(void *va, u32 size)
+{
+        unsigned long *virt_addr = va;
+        unsigned long temp;
+        u32 i;
+
+        for (i = 0; i < size / sizeof(unsigned long); i++) {
+                /*
+                 * Very carefully read and write to memory atomically
+                 * so we are interrupt, DMA and SMP safe.
+                 *
+                 * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
+                 */
+
+                __asm__ __volatile__ (
+                "       .set    push                                    \n"
+                "       .set    mips2                                   \n"
+                "1:     ll      %0, %1          # edac_atomic_scrub     \n"
+                "       addu    %0, $0                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       .set    pop                                     \n"
+                : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
+                : GCC_OFF_SMALL_ASM() (*virt_addr));
+
+                virt_addr++;
+        }
+}
+
+#endif
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
new file mode 100644
index 000000000..71c762202
--- /dev/null
+++ b/arch/mips/include/asm/elf.h
@@ -0,0 +1,538 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Much of this is taken from binutils and GNU libc ...
+ */
+#ifndef _ASM_ELF_H
+#define _ASM_ELF_H
+
+#include <linux/auxvec.h>
+#include <linux/fs.h>
+#include <linux/mm_types.h>
+
+#include <uapi/linux/elf.h>
+
+#include <asm/current.h>
+
+/* ELF header e_flags defines. */
+/* MIPS architecture level. */
+#define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
+#define EF_MIPS_ARCH_2          0x10000000      /* -mips2 code.  */
+#define EF_MIPS_ARCH_3          0x20000000      /* -mips3 code.  */
+#define EF_MIPS_ARCH_4          0x30000000      /* -mips4 code.  */
+#define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
+#define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
+#define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
+#define EF_MIPS_ARCH_32R2       0x70000000      /* MIPS32 R2 code.  */
+#define EF_MIPS_ARCH_64R2       0x80000000      /* MIPS64 R2 code.  */
+
+/* The ABI of a file. */
+#define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
+#define EF_MIPS_ABI_O64         0x00002000      /* O32 extended for 64 bit.  */
+
+#define PT_MIPS_REGINFO         0x70000000
+#define PT_MIPS_RTPROC          0x70000001
+#define PT_MIPS_OPTIONS         0x70000002
+#define PT_MIPS_ABIFLAGS        0x70000003
+
+/* Flags in the e_flags field of the header */
+#define EF_MIPS_NOREORDER       0x00000001
+#define EF_MIPS_PIC             0x00000002
+#define EF_MIPS_CPIC            0x00000004
+#define EF_MIPS_ABI2            0x00000020
+#define EF_MIPS_OPTIONS_FIRST   0x00000080
+#define EF_MIPS_32BITMODE       0x00000100
+#define EF_MIPS_FP64            0x00000200
+#define EF_MIPS_NAN2008         0x00000400
+#define EF_MIPS_ABI             0x0000f000
+#define EF_MIPS_ARCH            0xf0000000
+
+#define DT_MIPS_RLD_VERSION     0x70000001
+#define DT_MIPS_TIME_STAMP      0x70000002
+#define DT_MIPS_ICHECKSUM       0x70000003
+#define DT_MIPS_IVERSION        0x70000004
+#define DT_MIPS_FLAGS           0x70000005
+        #define RHF_NONE        0x00000000
+        #define RHF_HARDWAY     0x00000001
+        #define RHF_NOTPOT      0x00000002
+        #define RHF_SGI_ONLY    0x00000010
+#define DT_MIPS_BASE_ADDRESS    0x70000006
+#define DT_MIPS_CONFLICT        0x70000008
+#define DT_MIPS_LIBLIST         0x70000009
+#define DT_MIPS_LOCAL_GOTNO     0x7000000a
+#define DT_MIPS_CONFLICTNO      0x7000000b
+#define DT_MIPS_LIBLISTNO       0x70000010
+#define DT_MIPS_SYMTABNO        0x70000011
+#define DT_MIPS_UNREFEXTNO      0x70000012
+#define DT_MIPS_GOTSYM          0x70000013
+#define DT_MIPS_HIPAGENO        0x70000014
+#define DT_MIPS_RLD_MAP         0x70000016
+
+#define R_MIPS_NONE             0
+#define R_MIPS_16               1
+#define R_MIPS_32               2
+#define R_MIPS_REL32            3
+#define R_MIPS_26               4
+#define R_MIPS_HI16             5
+#define R_MIPS_LO16             6
+#define R_MIPS_GPREL16          7
+#define R_MIPS_LITERAL          8
+#define R_MIPS_GOT16            9
+#define R_MIPS_PC16             10
+#define R_MIPS_CALL16           11
+#define R_MIPS_GPREL32          12
+/* The remaining relocs are defined on Irix, although they are not
+   in the MIPS ELF ABI.  */
+#define R_MIPS_UNUSED1          13
+#define R_MIPS_UNUSED2          14
+#define R_MIPS_UNUSED3          15
+#define R_MIPS_SHIFT5           16
+#define R_MIPS_SHIFT6           17
+#define R_MIPS_64               18
+#define R_MIPS_GOT_DISP         19
+#define R_MIPS_GOT_PAGE         20
+#define R_MIPS_GOT_OFST         21
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_GOTHI16          22
+#define R_MIPS_GOTLO16          23
+#define R_MIPS_SUB              24
+#define R_MIPS_INSERT_A         25
+#define R_MIPS_INSERT_B         26
+#define R_MIPS_DELETE           27
+#define R_MIPS_HIGHER           28
+#define R_MIPS_HIGHEST          29
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_CALLHI16         30
+#define R_MIPS_CALLLO16         31
+/*
+ * Introduced for MIPSr6.
+ */
+#define R_MIPS_PC21_S2          60
+#define R_MIPS_PC26_S2          61
+/*
+ * This range is reserved for vendor specific relocations.
+ */
+#define R_MIPS_LOVENDOR         100
+#define R_MIPS_HIVENDOR         127
+
+#define SHN_MIPS_ACCOMON        0xff00          /* Allocated common symbols */
+#define SHN_MIPS_TEXT           0xff01          /* Allocated test symbols.  */
+#define SHN_MIPS_DATA           0xff02          /* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON        0xff03          /* Small common symbols */
+#define SHN_MIPS_SUNDEFINED     0xff04          /* Small undefined symbols */
+
+#define SHT_MIPS_LIST           0x70000000
+#define SHT_MIPS_CONFLICT       0x70000002
+#define SHT_MIPS_GPTAB          0x70000003
+#define SHT_MIPS_UCODE          0x70000004
+#define SHT_MIPS_DEBUG          0x70000005
+#define SHT_MIPS_REGINFO        0x70000006
+#define SHT_MIPS_PACKAGE        0x70000007
+#define SHT_MIPS_PACKSYM        0x70000008
+#define SHT_MIPS_RELD           0x70000009
+#define SHT_MIPS_IFACE          0x7000000b
+#define SHT_MIPS_CONTENT        0x7000000c
+#define SHT_MIPS_OPTIONS        0x7000000d
+#define SHT_MIPS_SHDR           0x70000010
+#define SHT_MIPS_FDESC          0x70000011
+#define SHT_MIPS_EXTSYM         0x70000012
+#define SHT_MIPS_DENSE          0x70000013
+#define SHT_MIPS_PDESC          0x70000014
+#define SHT_MIPS_LOCSYM         0x70000015
+#define SHT_MIPS_AUXSYM         0x70000016
+#define SHT_MIPS_OPTSYM         0x70000017
+#define SHT_MIPS_LOCSTR         0x70000018
+#define SHT_MIPS_LINE           0x70000019
+#define SHT_MIPS_RFDESC         0x7000001a
+#define SHT_MIPS_DELTASYM       0x7000001b
+#define SHT_MIPS_DELTAINST      0x7000001c
+#define SHT_MIPS_DELTACLASS     0x7000001d
+#define SHT_MIPS_DWARF          0x7000001e
+#define SHT_MIPS_DELTADECL      0x7000001f
+#define SHT_MIPS_SYMBOL_LIB     0x70000020
+#define SHT_MIPS_EVENTS         0x70000021
+#define SHT_MIPS_TRANSLATE      0x70000022
+#define SHT_MIPS_PIXIE          0x70000023
+#define SHT_MIPS_XLATE          0x70000024
+#define SHT_MIPS_XLATE_DEBUG    0x70000025
+#define SHT_MIPS_WHIRL          0x70000026
+#define SHT_MIPS_EH_REGION      0x70000027
+#define SHT_MIPS_XLATE_OLD      0x70000028
+#define SHT_MIPS_PDR_EXCEPTION  0x70000029
+
+#define SHF_MIPS_GPREL          0x10000000
+#define SHF_MIPS_MERGE          0x20000000
+#define SHF_MIPS_ADDR           0x40000000
+#define SHF_MIPS_STRING         0x80000000
+#define SHF_MIPS_NOSTRIP        0x08000000
+#define SHF_MIPS_LOCAL          0x04000000
+#define SHF_MIPS_NAMES          0x02000000
+#define SHF_MIPS_NODUPES        0x01000000
+
+#define MIPS_ABI_FP_ANY         0       /* FP ABI doesn't matter */
+#define MIPS_ABI_FP_DOUBLE      1       /* -mdouble-float */
+#define MIPS_ABI_FP_SINGLE      2       /* -msingle-float */
+#define MIPS_ABI_FP_SOFT        3       /* -msoft-float */
+#define MIPS_ABI_FP_OLD_64      4       /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_XX          5       /* -mfpxx */
+#define MIPS_ABI_FP_64          6       /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_64A         7       /* -mips32r2 -mfp64 -mno-odd-spreg */
+
+struct mips_elf_abiflags_v0 {
+        uint16_t version;       /* Version of flags structure */
+        uint8_t isa_level;      /* The level of the ISA: 1-5, 32, 64 */
+        uint8_t isa_rev;        /* The revision of ISA: 0 for MIPS V and below,
+                                   1-n otherwise */
+        uint8_t gpr_size;       /* The size of general purpose registers */
+        uint8_t cpr1_size;      /* The size of co-processor 1 registers */
+        uint8_t cpr2_size;      /* The size of co-processor 2 registers */
+        uint8_t fp_abi;         /* The floating-point ABI */
+        uint32_t isa_ext;       /* Mask of processor-specific extensions */
+        uint32_t ases;          /* Mask of ASEs used */
+        uint32_t flags1;        /* Mask of general flags */
+        uint32_t flags2;
+};
+
+#ifndef ELF_ARCH
+/* ELF register definitions */
+#define ELF_NGREG       45
+#define ELF_NFPREG      33
+
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs);
+void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs);
+
+#ifdef CONFIG_32BIT
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch elfo32_check_arch
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+
+#define ELF_CORE_COPY_REGS(dest, regs) \
+        mips_dump_regs32((u32 *)&(dest), (regs));
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch elfn64_check_arch
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS64
+
+#define ELF_CORE_COPY_REGS(dest, regs) \
+        mips_dump_regs64((u64 *)&(dest), (regs));
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#ifdef __MIPSEB__
+#define ELF_DATA        ELFDATA2MSB
+#elif defined(__MIPSEL__)
+#define ELF_DATA        ELFDATA2LSB
+#endif
+#define ELF_ARCH        EM_MIPS
+
+#endif /* !defined(ELF_ARCH) */
+
+/*
+ * In order to be sure that we don't attempt to execute an O32 binary which
+ * requires 64 bit FP (FR=1) on a system which does not support it we refuse
+ * to execute any binary which has bits specified by the following macro set
+ * in its ELF header flags.
+ */
+#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
+# define __MIPS_O32_FP64_MUST_BE_ZERO   0
+#else
+# define __MIPS_O32_FP64_MUST_BE_ZERO   EF_MIPS_FP64
+#endif
+
+#define mips_elf_check_machine(x) ((x)->e_machine == EM_MIPS)
+
+#define vmcore_elf32_check_arch mips_elf_check_machine
+#define vmcore_elf64_check_arch mips_elf_check_machine
+
+/*
+ * Return non-zero if HDR identifies an o32 ELF binary.
+ */
+#define elfo32_check_arch(hdr)                                          \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (!mips_elf_check_machine(__h))                               \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS32)                       \
+                __res = 0;                                              \
+        if ((__h->e_flags & EF_MIPS_ABI2) != 0)                         \
+                __res = 0;                                              \
+        if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
+            ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
+                __res = 0;                                              \
+        if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO)                \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * Return non-zero if HDR identifies an n64 ELF binary.
+ */
+#define elfn64_check_arch(hdr)                                          \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (!mips_elf_check_machine(__h))                               \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * Return non-zero if HDR identifies an n32 ELF binary.
+ */
+#define elfn32_check_arch(hdr)                                          \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (!mips_elf_check_machine(__h))                               \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS32)                       \
+                __res = 0;                                              \
+        if (((__h->e_flags & EF_MIPS_ABI2) == 0) ||                     \
+            ((__h->e_flags & EF_MIPS_ABI) != 0))                        \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+struct mips_abi;
+
+extern struct mips_abi mips_abi;
+extern struct mips_abi mips_abi_32;
+extern struct mips_abi mips_abi_n32;
+
+#ifdef CONFIG_32BIT
+
+#define SET_PERSONALITY2(ex, state)                                     \
+do {                                                                    \
+        clear_thread_flag(TIF_HYBRID_FPREGS);                           \
+        set_thread_flag(TIF_32BIT_FPREGS);                              \
+                                                                        \
+        current->thread.abi = &mips_abi;                                \
+                                                                        \
+        mips_set_personality_fp(state);                                 \
+        mips_set_personality_nan(state);                                \
+                                                                        \
+        if (personality(current->personality) != PER_LINUX)             \
+                set_personality(PER_LINUX);                             \
+} while (0)
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifdef CONFIG_MIPS32_N32
+#define __SET_PERSONALITY32_N32()                                       \
+        do {                                                            \
+                set_thread_flag(TIF_32BIT_ADDR);                        \
+                                                                        \
+                current->thread.abi = &mips_abi_n32;                    \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_N32()                                       \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_O32
+#define __SET_PERSONALITY32_O32(ex, state)                              \
+        do {                                                            \
+                set_thread_flag(TIF_32BIT_REGS);                        \
+                set_thread_flag(TIF_32BIT_ADDR);                        \
+                clear_thread_flag(TIF_HYBRID_FPREGS);                   \
+                set_thread_flag(TIF_32BIT_FPREGS);                      \
+                                                                        \
+                current->thread.abi = &mips_abi_32;                     \
+                                                                        \
+                mips_set_personality_fp(state);                         \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_O32(ex, state)                              \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_COMPAT
+#define __SET_PERSONALITY32(ex, state)                                  \
+do {                                                                    \
+        if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&                     \
+             ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
+                __SET_PERSONALITY32_N32();                              \
+        else                                                            \
+                __SET_PERSONALITY32_O32(ex, state);                     \
+} while (0)
+#else
+#define __SET_PERSONALITY32(ex, state) do { } while (0)
+#endif
+
+#define SET_PERSONALITY2(ex, state)                                     \
+do {                                                                    \
+        unsigned int p;                                                 \
+                                                                        \
+        clear_thread_flag(TIF_32BIT_REGS);                              \
+        clear_thread_flag(TIF_32BIT_FPREGS);                            \
+        clear_thread_flag(TIF_HYBRID_FPREGS);                           \
+        clear_thread_flag(TIF_32BIT_ADDR);                              \
+        current->personality &= ~READ_IMPLIES_EXEC;                     \
+                                                                        \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
+                __SET_PERSONALITY32(ex, state);                         \
+        else                                                            \
+                current->thread.abi = &mips_abi;                        \
+                                                                        \
+        mips_set_personality_nan(state);                                \
+                                                                        \
+        p = personality(current->personality);                          \
+        if (p != PER_LINUX32 && p != PER_LINUX)                         \
+                set_personality(PER_LINUX);                             \
+} while (0)
+
+#endif /* CONFIG_64BIT */
+
+#define CORE_DUMP_USE_REGSET
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This could be done in userspace,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (elf_hwcap)
+extern unsigned int elf_hwcap;
+#include <asm/hwcap.h>
+
+/*
+ * This yields a string that ld.so will use to load implementation
+ * specific libraries for optimization.  This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
+ */
+
+#define ELF_PLATFORM  __elf_platform
+extern const char *__elf_platform;
+
+#define ELF_BASE_PLATFORM  __elf_base_platform
+extern const char *__elf_base_platform;
+
+/*
+ * See comments in asm-alpha/elf.h, this is the same thing
+ * on the MIPS.
+ */
+#define ELF_PLAT_INIT(_r, load_addr)    do { \
+        _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0;      \
+        _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0;      \
+        _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0;   \
+        _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0;  \
+        _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0;  \
+        _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0;  \
+        _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0;  \
+        _r->regs[30] = _r->regs[31] = 0;                                \
+} while (0)
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#ifndef ELF_ET_DYN_BASE
+#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
+#endif
+
+/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
+#define ARCH_DLINFO                                                     \
+do {                                                                    \
+        NEW_AUX_ENT(AT_SYSINFO_EHDR,                                    \
+                    (unsigned long)current->mm->context.vdso);          \
+} while (0)
+
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+                                       int uses_interp);
+
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
+struct arch_elf_state {
+        int nan_2008;
+        int fp_abi;
+        int interp_fp_abi;
+        int overall_fp_mode;
+};
+
+#define MIPS_ABI_FP_UNKNOWN     (-1)    /* Unknown FP ABI (kernel internal) */
+
+#define INIT_ARCH_ELF_STATE {                   \
+        .nan_2008 = -1,                         \
+        .fp_abi = MIPS_ABI_FP_UNKNOWN,          \
+        .interp_fp_abi = MIPS_ABI_FP_UNKNOWN,   \
+        .overall_fp_mode = -1,                  \
+}
+
+extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf,
+                            bool is_interp, struct arch_elf_state *state);
+
+extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr,
+                          struct arch_elf_state *state);
+
+/* Whether to accept legacy-NaN and 2008-NaN user binaries.  */
+extern bool mips_use_nan_legacy;
+extern bool mips_use_nan_2008;
+
+extern void mips_set_personality_nan(struct arch_elf_state *state);
+extern void mips_set_personality_fp(struct arch_elf_state *state);
+
+#else /* !CONFIG_MIPS_FP_SUPPORT */
+
+struct arch_elf_state;
+
+static inline void mips_set_personality_nan(struct arch_elf_state *state)
+{
+        /* no-op */
+}
+
+static inline void mips_set_personality_fp(struct arch_elf_state *state)
+{
+        /* no-op */
+}
+
+#endif /* !CONFIG_MIPS_FP_SUPPORT */
+
+#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk)
+extern int mips_elf_read_implies_exec(void *elf_ex, int exstack);
+
+#endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h
new file mode 100644
index 000000000..21d91cdfe
--- /dev/null
+++ b/arch/mips/include/asm/errno.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_ERRNO_H
+#define _ASM_ERRNO_H
+
+#include <uapi/asm/errno.h>
+
+
+/* The biggest error number defined here or in <linux/errno.h>. */
+#define EMAXERRNO       1133
+
+#endif /* _ASM_ERRNO_H */
diff --git a/arch/mips/include/asm/eva.h b/arch/mips/include/asm/eva.h
new file mode 100644
index 000000000..a3d1807f2
--- /dev/null
+++ b/arch/mips/include/asm/eva.h
@@ -0,0 +1,43 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014, Imagination Technologies Ltd.
+ *
+ * EVA functions for generic code
+ */
+
+#ifndef _ASM_EVA_H
+#define _ASM_EVA_H
+
+#include <kernel-entry-init.h>
+
+#ifdef __ASSEMBLY__
+
+#ifdef CONFIG_EVA
+
+/*
+ * EVA early init code
+ *
+ * Platforms must define their own 'platform_eva_init' macro in
+ * their kernel-entry-init.h header. This macro usually does the
+ * platform specific configuration of the segmentation registers,
+ * and it is normally called from assembly code.
+ *
+ */
+
+.macro eva_init
+platform_eva_init
+.endm
+
+#else
+
+.macro eva_init
+.endm
+
+#endif /* CONFIG_EVA */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/exec.h b/arch/mips/include/asm/exec.h
new file mode 100644
index 000000000..c1f6afa4b
--- /dev/null
+++ b/arch/mips/include/asm/exec.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_EXEC_H
+#define _ASM_EXEC_H
+
+extern unsigned long arch_align_stack(unsigned long sp);
+
+#endif /* _ASM_EXEC_H */
diff --git a/arch/mips/include/asm/extable.h b/arch/mips/include/asm/extable.h
new file mode 100644
index 000000000..78d0ae156
--- /dev/null
+++ b/arch/mips/include/asm/extable.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_EXTABLE_H
+#define _ASM_EXTABLE_H
+
+struct exception_table_entry
+{
+        unsigned long insn;
+        unsigned long nextinsn;
+};
+
+struct pt_regs;
+extern int fixup_exception(struct pt_regs *regs);
+
+#endif
diff --git a/arch/mips/include/asm/fb.h b/arch/mips/include/asm/fb.h
new file mode 100644
index 000000000..bd3f68c9d
--- /dev/null
+++ b/arch/mips/include/asm/fb.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
new file mode 100644
index 000000000..743535be7
--- /dev/null
+++ b/arch/mips/include/asm/fixmap.h
@@ -0,0 +1,79 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <asm/page.h>
+#include <spaces.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the end of virtual memory (0xfffff000) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanizm,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+#define FIX_N_COLOURS 8
+        FIX_CMAP_BEGIN,
+        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
+#ifdef CONFIG_HIGHMEM
+        /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_BEGIN = FIX_CMAP_END + 1,
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between vmalloc'ed areas and
+ * the start of the fixmap, and leave one page empty
+ * at the top of mem..
+ */
+#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#include <asm-generic/fixmap.h>
+
+/*
+ * Called from pgtable_init()
+ */
+extern void fixrange_init(unsigned long start, unsigned long end,
+        pgd_t *pgd_base);
+
+
+#endif
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
new file mode 100644
index 000000000..021d09ae5
--- /dev/null
+++ b/arch/mips/include/asm/floppy.h
@@ -0,0 +1,56 @@
+/*
+ * Architecture specific parts of the Floppy driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 2000 Ralf Baechle
+ */
+#ifndef _ASM_FLOPPY_H
+#define _ASM_FLOPPY_H
+
+#include <asm/io.h>
+
+static inline void fd_cacheflush(char * addr, long size)
+{
+        dma_cache_wback_inv((unsigned long)addr, size);
+}
+
+#define MAX_BUFFER_SECTORS 24
+
+
+/*
+ * And on Mips's the CMOS info fails also ...
+ *
+ * FIXME: This information should come from the ARC configuration tree
+ *        or wherever a particular machine has stored this ...
+ */
+#define FLOPPY0_TYPE            fd_drive_type(0)
+#define FLOPPY1_TYPE            fd_drive_type(1)
+
+#define FDC1                    fd_getfdaddr1()
+
+#define N_FDC 1                 /* do you *really* want a second controller? */
+#define N_DRIVE 8
+
+/*
+ * The DMA channel used by the floppy controller cannot access data at
+ * addresses >= 16MB
+ *
+ * Went back to the 1MB limit, as some people had problems with the floppy
+ * driver otherwise. It doesn't matter much for performance anyway, as most
+ * floppy accesses go through the track buffer.
+ *
+ * On MIPSes using vdma, this actually means that *all* transfers go thru
+ * the * track buffer since 0x1000000 is always smaller than KSEG0/1.
+ * Actually this needs to be a bit more complicated since the so much different
+ * hardware available with MIPS CPUs ...
+ */
+#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
+
+#define EXTRA_FLOPPY_PARAMS
+
+#include <floppy.h>
+
+#endif /* _ASM_FLOPPY_H */
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
new file mode 100644
index 000000000..f184ba088
--- /dev/null
+++ b/arch/mips/include/asm/fpregdef.h
@@ -0,0 +1,113 @@
+/*
+ * Definitions for the FPU register names
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_FPREGDEF_H
+#define _ASM_FPREGDEF_H
+
+#include <asm/sgidefs.h>
+
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * These definitions only cover the R3000-ish 16/32 register model.
+ * But we're trying to be R3000 friendly anyway ...
+ */
+#define fv0     $f0      /* return value */
+#define fv0f    $f1
+#define fv1     $f2
+#define fv1f    $f3
+#define fa0     $f12     /* argument registers */
+#define fa0f    $f13
+#define fa1     $f14
+#define fa1f    $f15
+#define ft0     $f4      /* caller saved */
+#define ft0f    $f5
+#define ft1     $f6
+#define ft1f    $f7
+#define ft2     $f8
+#define ft2f    $f9
+#define ft3     $f10
+#define ft3f    $f11
+#define ft4     $f16
+#define ft4f    $f17
+#define ft5     $f18
+#define ft5f    $f19
+#define fs0     $f20     /* callee saved */
+#define fs0f    $f21
+#define fs1     $f22
+#define fs1f    $f23
+#define fs2     $f24
+#define fs2f    $f25
+#define fs3     $f26
+#define fs3f    $f27
+#define fs4     $f28
+#define fs4f    $f29
+#define fs5     $f30
+#define fs5f    $f31
+
+#define fcr31   $31      /* FPU status register */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define fv0     $f0     /* return value */
+#define fv1     $f2
+#define fa0     $f12    /* argument registers */
+#define fa1     $f13
+#define fa2     $f14
+#define fa3     $f15
+#define fa4     $f16
+#define fa5     $f17
+#define fa6     $f18
+#define fa7     $f19
+#define ft0     $f4     /* caller saved */
+#define ft1     $f5
+#define ft2     $f6
+#define ft3     $f7
+#define ft4     $f8
+#define ft5     $f9
+#define ft6     $f10
+#define ft7     $f11
+#define ft8     $f20
+#define ft9     $f21
+#define ft10    $f22
+#define ft11    $f23
+#define ft12    $f1
+#define ft13    $f3
+#define fs0     $f24    /* callee saved */
+#define fs1     $f25
+#define fs2     $f26
+#define fs3     $f27
+#define fs4     $f28
+#define fs5     $f29
+#define fs6     $f30
+#define fs7     $f31
+
+#define fcr31   $31
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_FPREGDEF_H */
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
new file mode 100644
index 000000000..08f9dd690
--- /dev/null
+++ b/arch/mips/include/asm/fpu.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ */
+#ifndef _ASM_FPU_H
+#define _ASM_FPU_H
+
+#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
+#include <linux/ptrace.h>
+#include <linux/thread_info.h>
+#include <linux/bitops.h>
+
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/fpu_emulator.h>
+#include <asm/hazards.h>
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/current.h>
+#include <asm/msa.h>
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+#include <asm/mips_mt.h>
+#endif
+
+/*
+ * This enum specifies a mode in which we want the FPU to operate, for cores
+ * which implement the Status.FR bit. Note that the bottom bit of the value
+ * purposefully matches the desired value of the Status.FR bit.
+ */
+enum fpu_mode {
+        FPU_32BIT = 0,          /* FR = 0 */
+        FPU_64BIT,              /* FR = 1, FRE = 0 */
+        FPU_AS_IS,
+        FPU_HYBRID,             /* FR = 1, FRE = 1 */
+
+#define FPU_FR_MASK             0x1
+};
+
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
+extern void _save_fp(struct task_struct *);
+extern void _restore_fp(struct task_struct *);
+
+#define __disable_fpu()                                                 \
+do {                                                                    \
+        clear_c0_status(ST0_CU1);                                       \
+        disable_fpu_hazard();                                           \
+} while (0)
+
+static inline int __enable_fpu(enum fpu_mode mode)
+{
+        int fr;
+
+        switch (mode) {
+        case FPU_AS_IS:
+                /* just enable the FPU in its current mode */
+                set_c0_status(ST0_CU1);
+                enable_fpu_hazard();
+                return 0;
+
+        case FPU_HYBRID:
+                if (!cpu_has_fre)
+                        return SIGFPE;
+
+                /* set FRE */
+                set_c0_config5(MIPS_CONF5_FRE);
+                goto fr_common;
+
+        case FPU_64BIT:
+#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
+      defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT))
+                /* we only have a 32-bit FPU */
+                return SIGFPE;
+#endif
+                fallthrough;
+        case FPU_32BIT:
+                if (cpu_has_fre) {
+                        /* clear FRE */
+                        clear_c0_config5(MIPS_CONF5_FRE);
+                }
+fr_common:
+                /* set CU1 & change FR appropriately */
+                fr = (int)mode & FPU_FR_MASK;
+                change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
+                enable_fpu_hazard();
+
+                /* check FR has the desired value */
+                if (!!(read_c0_status() & ST0_FR) == !!fr)
+                        return 0;
+
+                /* unsupported FR value */
+                __disable_fpu();
+                return SIGFPE;
+
+        default:
+                BUG();
+        }
+
+        return SIGFPE;
+}
+
+#define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
+
+static inline int __is_fpu_owner(void)
+{
+        return test_thread_flag(TIF_USEDFPU);
+}
+
+static inline int is_fpu_owner(void)
+{
+        return cpu_has_fpu && __is_fpu_owner();
+}
+
+static inline int __own_fpu(void)
+{
+        enum fpu_mode mode;
+        int ret;
+
+        if (test_thread_flag(TIF_HYBRID_FPREGS))
+                mode = FPU_HYBRID;
+        else
+                mode = !test_thread_flag(TIF_32BIT_FPREGS);
+
+        ret = __enable_fpu(mode);
+        if (ret)
+                return ret;
+
+        KSTK_STATUS(current) |= ST0_CU1;
+        if (mode == FPU_64BIT || mode == FPU_HYBRID)
+                KSTK_STATUS(current) |= ST0_FR;
+        else /* mode == FPU_32BIT */
+                KSTK_STATUS(current) &= ~ST0_FR;
+
+        set_thread_flag(TIF_USEDFPU);
+        return 0;
+}
+
+static inline int own_fpu_inatomic(int restore)
+{
+        int ret = 0;
+
+        if (cpu_has_fpu && !__is_fpu_owner()) {
+                ret = __own_fpu();
+                if (restore && !ret)
+                        _restore_fp(current);
+        }
+        return ret;
+}
+
+static inline int own_fpu(int restore)
+{
+        int ret;
+
+        preempt_disable();
+        ret = own_fpu_inatomic(restore);
+        preempt_enable();
+        return ret;
+}
+
+static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
+{
+        if (is_msa_enabled()) {
+                if (save) {
+                        save_msa(tsk);
+                        tsk->thread.fpu.fcr31 =
+                                        read_32bit_cp1_register(CP1_STATUS);
+                }
+                disable_msa();
+                clear_tsk_thread_flag(tsk, TIF_USEDMSA);
+                __disable_fpu();
+        } else if (is_fpu_owner()) {
+                if (save)
+                        _save_fp(tsk);
+                __disable_fpu();
+        } else {
+                /* FPU should not have been left enabled with no owner */
+                WARN(read_c0_status() & ST0_CU1,
+                     "Orphaned FPU left enabled");
+        }
+        KSTK_STATUS(tsk) &= ~ST0_CU1;
+        clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+}
+
+static inline void lose_fpu(int save)
+{
+        preempt_disable();
+        lose_fpu_inatomic(save, current);
+        preempt_enable();
+}
+
+/**
+ * init_fp_ctx() - Initialize task FP context
+ * @target: The task whose FP context should be initialized.
+ *
+ * Initializes the FP context of the target task to sane default values if that
+ * target task does not already have valid FP context. Once the context has
+ * been initialized, the task will be marked as having used FP & thus having
+ * valid FP context.
+ *
+ * Returns: true if context is initialized, else false.
+ */
+static inline bool init_fp_ctx(struct task_struct *target)
+{
+        /* If FP has been used then the target already has context */
+        if (tsk_used_math(target))
+                return false;
+
+        /* Begin with data registers set to all 1s... */
+        memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
+
+        /* FCSR has been preset by `mips_set_personality_nan'.  */
+
+        /*
+         * Record that the target has "used" math, such that the context
+         * just initialised, and any modifications made by the caller,
+         * aren't discarded.
+         */
+        set_stopped_child_used_math(target);
+
+        return true;
+}
+
+static inline void save_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _save_fp(tsk);
+}
+
+static inline void restore_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _restore_fp(tsk);
+}
+
+static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
+{
+        if (tsk == current) {
+                preempt_disable();
+                if (is_fpu_owner())
+                        _save_fp(current);
+                preempt_enable();
+        }
+
+        return tsk->thread.fpu.fpr;
+}
+
+#else /* !CONFIG_MIPS_FP_SUPPORT */
+
+/*
+ * When FP support is disabled we provide only a minimal set of stub functions
+ * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
+ */
+
+static inline int __enable_fpu(enum fpu_mode mode)
+{
+        return SIGILL;
+}
+
+static inline void __disable_fpu(void)
+{
+        /* no-op */
+}
+
+
+static inline int is_fpu_owner(void)
+{
+        return 0;
+}
+
+static inline void clear_fpu_owner(void)
+{
+        /* no-op */
+}
+
+static inline int own_fpu_inatomic(int restore)
+{
+        return SIGILL;
+}
+
+static inline int own_fpu(int restore)
+{
+        return SIGILL;
+}
+
+static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
+{
+        /* no-op */
+}
+
+static inline void lose_fpu(int save)
+{
+        /* no-op */
+}
+
+static inline bool init_fp_ctx(struct task_struct *target)
+{
+        return false;
+}
+
+/*
+ * The following functions should only be called in paths where we know that FP
+ * support is enabled, typically a path where own_fpu() or __enable_fpu() have
+ * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
+ * time that this should never happen, so calls to these functions should be
+ * optimized away & never actually be emitted.
+ */
+
+extern void save_fp(struct task_struct *tsk)
+        __compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _save_fp(struct task_struct *)
+        __compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void restore_fp(struct task_struct *tsk)
+        __compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _restore_fp(struct task_struct *)
+        __compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern union fpureg *get_fpu_regs(struct task_struct *tsk)
+        __compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+#endif /* !CONFIG_MIPS_FP_SUPPORT */
+#endif /* _ASM_FPU_H */
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
new file mode 100644
index 000000000..f67759e81
--- /dev/null
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Further private data for which no space exists in mips_fpu_struct.
+ * This should be subsumed into the mips_fpu_struct structure as
+ * defined in processor.h as soon as the absurd wired absolute assembler
+ * offsets become dynamic at compile time.
+ *
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ */
+#ifndef _ASM_FPU_EMULATOR_H
+#define _ASM_FPU_EMULATOR_H
+
+#include <linux/sched.h>
+#include <asm/dsemul.h>
+#include <asm/thread_info.h>
+#include <asm/inst.h>
+#include <asm/local.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_DEBUG_FS
+
+struct mips_fpu_emulator_stats {
+        unsigned long emulated;
+        unsigned long loads;
+        unsigned long stores;
+        unsigned long branches;
+        unsigned long cp1ops;
+        unsigned long cp1xops;
+        unsigned long errors;
+        unsigned long ieee754_inexact;
+        unsigned long ieee754_underflow;
+        unsigned long ieee754_overflow;
+        unsigned long ieee754_zerodiv;
+        unsigned long ieee754_invalidop;
+        unsigned long ds_emul;
+
+        unsigned long abs_s;
+        unsigned long abs_d;
+        unsigned long add_s;
+        unsigned long add_d;
+        unsigned long bc1eqz;
+        unsigned long bc1nez;
+        unsigned long ceil_w_s;
+        unsigned long ceil_w_d;
+        unsigned long ceil_l_s;
+        unsigned long ceil_l_d;
+        unsigned long class_s;
+        unsigned long class_d;
+        unsigned long cmp_af_s;
+        unsigned long cmp_af_d;
+        unsigned long cmp_eq_s;
+        unsigned long cmp_eq_d;
+        unsigned long cmp_le_s;
+        unsigned long cmp_le_d;
+        unsigned long cmp_lt_s;
+        unsigned long cmp_lt_d;
+        unsigned long cmp_ne_s;
+        unsigned long cmp_ne_d;
+        unsigned long cmp_or_s;
+        unsigned long cmp_or_d;
+        unsigned long cmp_ueq_s;
+        unsigned long cmp_ueq_d;
+        unsigned long cmp_ule_s;
+        unsigned long cmp_ule_d;
+        unsigned long cmp_ult_s;
+        unsigned long cmp_ult_d;
+        unsigned long cmp_un_s;
+        unsigned long cmp_un_d;
+        unsigned long cmp_une_s;
+        unsigned long cmp_une_d;
+        unsigned long cmp_saf_s;
+        unsigned long cmp_saf_d;
+        unsigned long cmp_seq_s;
+        unsigned long cmp_seq_d;
+        unsigned long cmp_sle_s;
+        unsigned long cmp_sle_d;
+        unsigned long cmp_slt_s;
+        unsigned long cmp_slt_d;
+        unsigned long cmp_sne_s;
+        unsigned long cmp_sne_d;
+        unsigned long cmp_sor_s;
+        unsigned long cmp_sor_d;
+        unsigned long cmp_sueq_s;
+        unsigned long cmp_sueq_d;
+        unsigned long cmp_sule_s;
+        unsigned long cmp_sule_d;
+        unsigned long cmp_sult_s;
+        unsigned long cmp_sult_d;
+        unsigned long cmp_sun_s;
+        unsigned long cmp_sun_d;
+        unsigned long cmp_sune_s;
+        unsigned long cmp_sune_d;
+        unsigned long cvt_d_l;
+        unsigned long cvt_d_s;
+        unsigned long cvt_d_w;
+        unsigned long cvt_l_s;
+        unsigned long cvt_l_d;
+        unsigned long cvt_s_d;
+        unsigned long cvt_s_l;
+        unsigned long cvt_s_w;
+        unsigned long cvt_w_s;
+        unsigned long cvt_w_d;
+        unsigned long div_s;
+        unsigned long div_d;
+        unsigned long floor_w_s;
+        unsigned long floor_w_d;
+        unsigned long floor_l_s;
+        unsigned long floor_l_d;
+        unsigned long maddf_s;
+        unsigned long maddf_d;
+        unsigned long max_s;
+        unsigned long max_d;
+        unsigned long maxa_s;
+        unsigned long maxa_d;
+        unsigned long min_s;
+        unsigned long min_d;
+        unsigned long mina_s;
+        unsigned long mina_d;
+        unsigned long mov_s;
+        unsigned long mov_d;
+        unsigned long msubf_s;
+        unsigned long msubf_d;
+        unsigned long mul_s;
+        unsigned long mul_d;
+        unsigned long neg_s;
+        unsigned long neg_d;
+        unsigned long recip_s;
+        unsigned long recip_d;
+        unsigned long rint_s;
+        unsigned long rint_d;
+        unsigned long round_w_s;
+        unsigned long round_w_d;
+        unsigned long round_l_s;
+        unsigned long round_l_d;
+        unsigned long rsqrt_s;
+        unsigned long rsqrt_d;
+        unsigned long sel_s;
+        unsigned long sel_d;
+        unsigned long seleqz_s;
+        unsigned long seleqz_d;
+        unsigned long selnez_s;
+        unsigned long selnez_d;
+        unsigned long sqrt_s;
+        unsigned long sqrt_d;
+        unsigned long sub_s;
+        unsigned long sub_d;
+        unsigned long trunc_w_s;
+        unsigned long trunc_w_d;
+        unsigned long trunc_l_s;
+        unsigned long trunc_l_d;
+};
+
+DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
+
+#define MIPS_FPU_EMU_INC_STATS(M)                                       \
+do {                                                                    \
+        preempt_disable();                                              \
+        __this_cpu_inc(fpuemustats.M);                                  \
+        preempt_enable();                                               \
+} while (0)
+
+#else
+#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
+#endif /* CONFIG_DEBUG_FS */
+
+extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
+                                    struct mips_fpu_struct *ctx, int has_fpu,
+                                    void __user **fault_addr);
+void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
+                     struct task_struct *tsk);
+int process_fpemu_return(int sig, void __user *fault_addr,
+                         unsigned long fcr31);
+
+/*
+ * Mask the FCSR Cause bits according to the Enable bits, observing
+ * that Unimplemented is always enabled.
+ */
+static inline unsigned long mask_fcr31_x(unsigned long fcr31)
+{
+        return fcr31 & (FPU_CSR_UNI_X |
+                        ((fcr31 & FPU_CSR_ALL_E) <<
+                         (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));
+}
+
+#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
new file mode 100644
index 000000000..b463f2aa5
--- /dev/null
+++ b/arch/mips/include/asm/ftrace.h
@@ -0,0 +1,90 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ *
+ * Copyright (C) 2009 DSLab, Lanzhou University, China
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef _ASM_MIPS_FTRACE_H
+#define _ASM_MIPS_FTRACE_H
+
+#ifdef CONFIG_FUNCTION_TRACER
+
+#define MCOUNT_ADDR ((unsigned long)(_mcount))
+#define MCOUNT_INSN_SIZE 4              /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#define mcount _mcount
+
+#define safe_load(load, src, dst, error)                \
+do {                                                    \
+        asm volatile (                                  \
+                "1: " load " %[tmp_dst], 0(%[tmp_src])\n"       \
+                "   li %[tmp_err], 0\n"                 \
+                "2: .insn\n"                            \
+                                                        \
+                ".section .fixup, \"ax\"\n"             \
+                "3: li %[tmp_err], 1\n"                 \
+                "   j 2b\n"                             \
+                ".previous\n"                           \
+                                                        \
+                ".section\t__ex_table,\"a\"\n\t"        \
+                STR(PTR) "\t1b, 3b\n\t"                 \
+                ".previous\n"                           \
+                                                        \
+                : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
+                : [tmp_src] "r" (src)                   \
+                : "memory"                              \
+        );                                              \
+} while (0)
+
+#define safe_store(store, src, dst, error)      \
+do {                                            \
+        asm volatile (                          \
+                "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
+                "   li %[tmp_err], 0\n"         \
+                "2: .insn\n"                    \
+                                                \
+                ".section .fixup, \"ax\"\n"     \
+                "3: li %[tmp_err], 1\n"         \
+                "   j 2b\n"                     \
+                ".previous\n"                   \
+                                                \
+                ".section\t__ex_table,\"a\"\n\t"\
+                STR(PTR) "\t1b, 3b\n\t"         \
+                ".previous\n"                   \
+                                                \
+                : [tmp_err] "=r" (error)        \
+                : [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
+                : "memory"                      \
+        );                                      \
+} while (0)
+
+#define safe_load_code(dst, src, error) \
+        safe_load(STR(lw), src, dst, error)
+#define safe_store_code(src, dst, error) \
+        safe_store(STR(sw), src, dst, error)
+
+#define safe_load_stack(dst, src, error) \
+        safe_load(STR(PTR_L), src, dst, error)
+
+#define safe_store_stack(src, dst, error) \
+        safe_store(STR(PTR_S), src, dst, error)
+
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        return addr;
+}
+
+struct dyn_arch_ftrace {
+};
+
+#endif /*  CONFIG_DYNAMIC_FTRACE */
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_FUNCTION_TRACER */
+#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
new file mode 100644
index 000000000..d85248404
--- /dev/null
+++ b/arch/mips/include/asm/futex.h
@@ -0,0 +1,204 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/asm-eva.h>
+#include <asm/barrier.h>
+#include <asm/compiler.h>
+#include <asm/errno.h>
+#include <asm/sync.h>
+#include <asm/war.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
+{                                                                       \
+        if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {       \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    push                            \n"     \
+                "       .set    arch=r4000                      \n"     \
+                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
+                "       .set    pop                             \n"     \
+                "       " insn  "                               \n"     \
+                "       .set    arch=r4000                      \n"     \
+                "2:     sc      $1, %2                          \n"     \
+                "       beqzl   $1, 1b                          \n"     \
+                __stringify(__WEAK_LLSC_MB) "                   \n"     \
+                "3:                                             \n"     \
+                "       .insn                                   \n"     \
+                "       .set    pop                             \n"     \
+                "       .section .fixup,\"ax\"                  \n"     \
+                "4:     li      %0, %6                          \n"     \
+                "       j       3b                              \n"     \
+                "       .previous                               \n"     \
+                "       .section __ex_table,\"a\"               \n"     \
+                "       "__UA_ADDR "\t1b, 4b                    \n"     \
+                "       "__UA_ADDR "\t2b, 4b                    \n"     \
+                "       .previous                               \n"     \
+                : "=r" (ret), "=&r" (oldval),                           \
+                  "=" GCC_OFF_SMALL_ASM() (*uaddr)                              \
+                : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),  \
+                  "i" (-EFAULT)                                         \
+                : "memory");                                            \
+        } else if (cpu_has_llsc) {                                      \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    push                            \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
+                "       " __SYNC(full, loongson3_war) "         \n"     \
+                "1:     "user_ll("%1", "%4")" # __futex_atomic_op\n"    \
+                "       .set    pop                             \n"     \
+                "       " insn  "                               \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
+                "2:     "user_sc("$1", "%2")"                   \n"     \
+                "       beqz    $1, 1b                          \n"     \
+                __stringify(__WEAK_LLSC_MB) "                   \n"     \
+                "3:                                             \n"     \
+                "       .insn                                   \n"     \
+                "       .set    pop                             \n"     \
+                "       .section .fixup,\"ax\"                  \n"     \
+                "4:     li      %0, %6                          \n"     \
+                "       j       3b                              \n"     \
+                "       .previous                               \n"     \
+                "       .section __ex_table,\"a\"               \n"     \
+                "       "__UA_ADDR "\t1b, 4b                    \n"     \
+                "       "__UA_ADDR "\t2b, 4b                    \n"     \
+                "       .previous                               \n"     \
+                : "=r" (ret), "=&r" (oldval),                           \
+                  "=" GCC_OFF_SMALL_ASM() (*uaddr)                              \
+                : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),  \
+                  "i" (-EFAULT)                                         \
+                : "memory");                                            \
+        } else                                                          \
+                ret = -ENOSYS;                                          \
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+        int oldval = 0, ret;
+
+        if (!access_ok(uaddr, sizeof(u32)))
+                return -EFAULT;
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
+                break;
+
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("addu $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or   $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and  $1, %1, %z5",
+                                  ret, oldval, uaddr, ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor  $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        if (!ret)
+                *oval = oldval;
+
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
+{
+        int ret = 0;
+        u32 val;
+
+        if (!access_ok(uaddr, sizeof(u32)))
+                return -EFAULT;
+
+        if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
+                __asm__ __volatile__(
+                "# futex_atomic_cmpxchg_inatomic                        \n"
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    push                                    \n"
+                "       .set    arch=r4000                              \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bne     %1, %z4, 3f                             \n"
+                "       .set    pop                                     \n"
+                "       move    $1, %z5                                 \n"
+                "       .set    arch=r4000                              \n"
+                "2:     sc      $1, %2                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                __stringify(__WEAK_LLSC_MB) "                           \n"
+                "3:                                                     \n"
+                "       .insn                                           \n"
+                "       .set    pop                                     \n"
+                "       .section .fixup,\"ax\"                          \n"
+                "4:     li      %0, %6                                  \n"
+                "       j       3b                                      \n"
+                "       .previous                                       \n"
+                "       .section __ex_table,\"a\"                       \n"
+                "       "__UA_ADDR "\t1b, 4b                            \n"
+                "       "__UA_ADDR "\t2b, 4b                            \n"
+                "       .previous                                       \n"
+                : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
+                : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+                  "i" (-EFAULT)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "# futex_atomic_cmpxchg_inatomic                        \n"
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
+                "       " __SYNC(full, loongson3_war) "                 \n"
+                "1:     "user_ll("%1", "%3")"                           \n"
+                "       bne     %1, %z4, 3f                             \n"
+                "       .set    pop                                     \n"
+                "       move    $1, %z5                                 \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
+                "2:     "user_sc("$1", "%2")"                           \n"
+                "       beqz    $1, 1b                                  \n"
+                "3:     " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
+                "       .insn                                           \n"
+                "       .set    pop                                     \n"
+                "       .section .fixup,\"ax\"                          \n"
+                "4:     li      %0, %6                                  \n"
+                "       j       3b                                      \n"
+                "       .previous                                       \n"
+                "       .section __ex_table,\"a\"                       \n"
+                "       "__UA_ADDR "\t1b, 4b                            \n"
+                "       "__UA_ADDR "\t2b, 4b                            \n"
+                "       .previous                                       \n"
+                : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
+                : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+                  "i" (-EFAULT)
+                : "memory");
+        } else
+                return -ENOSYS;
+
+        *uval = val;
+        return ret;
+}
+
+#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
new file mode 100644
index 000000000..d67b6a90f
--- /dev/null
+++ b/arch/mips/include/asm/fw/arc/hinv.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ARCS hardware/memory inventory/configuration and system ID definitions.
+ */
+#ifndef _ASM_ARC_HINV_H
+#define _ASM_ARC_HINV_H
+
+#include <asm/sgidefs.h>
+#include <asm/fw/arc/types.h>
+
+/* configuration query defines */
+typedef enum configclass {
+        SystemClass,
+        ProcessorClass,
+        CacheClass,
+#ifndef _NT_PROM
+        MemoryClass,
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass
+#else   /* _NT_PROM */
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass,
+        MemoryClass
+#endif  /* _NT_PROM */
+} CONFIGCLASS;
+
+typedef enum configtype {
+        ARC,
+        CPU,
+        FPU,
+        PrimaryICache,
+        PrimaryDCache,
+        SecondaryICache,
+        SecondaryDCache,
+        SecondaryCache,
+#ifndef _NT_PROM
+        Memory,
+#endif
+        EISAAdapter,
+        TCAdapter,
+        SCSIAdapter,
+        DTIAdapter,
+        MultiFunctionAdapter,
+        DiskController,
+        TapeController,
+        CDROMController,
+        WORMController,
+        SerialController,
+        NetworkController,
+        DisplayController,
+        ParallelController,
+        PointerController,
+        KeyboardController,
+        AudioController,
+        OtherController,
+        DiskPeripheral,
+        FloppyDiskPeripheral,
+        TapePeripheral,
+        ModemPeripheral,
+        MonitorPeripheral,
+        PrinterPeripheral,
+        PointerPeripheral,
+        KeyboardPeripheral,
+        TerminalPeripheral,
+        LinePeripheral,
+        NetworkPeripheral,
+#ifdef  _NT_PROM
+        Memory,
+#endif
+        OtherPeripheral,
+
+        /* new stuff for IP30 */
+        /* added without moving anything */
+        /* except ANONYMOUS. */
+
+        XTalkAdapter,
+        PCIAdapter,
+        GIOAdapter,
+        TPUAdapter,
+
+        Anonymous
+} CONFIGTYPE;
+
+typedef enum {
+        Failed = 1,
+        ReadOnly = 2,
+        Removable = 4,
+        ConsoleIn = 8,
+        ConsoleOut = 16,
+        Input = 32,
+        Output = 64
+} IDENTIFIERFLAG;
+
+#ifndef NULL                    /* for GetChild(NULL); */
+#define NULL    0
+#endif
+
+union key_u {
+        struct {
+#ifdef  _MIPSEB
+                unsigned char  c_bsize;         /* block size in lines */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned short c_size;          /* cache size in 4K pages */
+#else   /* _MIPSEL */
+                unsigned short c_size;          /* cache size in 4K pages */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned char  c_bsize;         /* block size in lines */
+#endif  /* _MIPSEL */
+        } cache;
+        ULONG FullKey;
+};
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+#define SGI_ARCS_VERS   64                      /* sgi 64-bit version */
+#define SGI_ARCS_REV    0                       /* rev .00 */
+#else
+#define SGI_ARCS_VERS   1                       /* first version */
+#define SGI_ARCS_REV    10                      /* rev .10, 3/04/92 */
+#endif
+
+typedef struct {
+        CONFIGCLASS     Class;
+        CONFIGTYPE      Type;
+        IDENTIFIERFLAG  Flags;
+        USHORT          Version;
+        USHORT          Revision;
+        ULONG           Key;
+        ULONG           AffinityMask;
+        ULONG           ConfigurationDataSize;
+        ULONG           IdentifierLength;
+        char            *Identifier;
+} COMPONENT;
+
+/* internal structure that holds pathname parsing data */
+struct cfgdata {
+        char *name;                     /* full name */
+        int minlen;                     /* minimum length to match */
+        CONFIGTYPE type;                /* type of token */
+};
+
+/* System ID */
+typedef struct {
+        CHAR VendorId[8];
+        CHAR ProductId[8];
+} SYSTEMID;
+
+/* memory query functions */
+typedef enum memorytype {
+        ExceptionBlock,
+        SPBPage,                        /* ARCS == SystemParameterBlock */
+#ifndef _NT_PROM
+        FreeContiguous,
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent
+#else   /* _NT_PROM */
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent,
+        FreeContiguous
+#endif  /* _NT_PROM */
+} MEMORYTYPE;
+
+typedef struct {
+        MEMORYTYPE      Type;
+        LONG            BasePage;
+        LONG            PageCount;
+} MEMORYDESCRIPTOR;
+
+#endif /* _ASM_ARC_HINV_H */
diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
new file mode 100644
index 000000000..ad1638061
--- /dev/null
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ARC_TYPES_H
+#define _ASM_ARC_TYPES_H
+
+
+#ifdef CONFIG_FW_ARC32
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__SI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__SI__)));
+typedef void            VOID;
+
+/* The pointer types.  Note that we're using a 64-bit compiler but all
+   pointer in the ARC structures are only 32-bit, so we need some disgusting
+   workarounds.  Keep your vomit bag handy.  */
+typedef LONG            _PCHAR;
+typedef LONG            _PSHORT;
+typedef LONG            _PLARGE_INTEGER;
+typedef LONG            _PLONG;
+typedef LONG            _PUCHAR;
+typedef LONG            _PUSHORT;
+typedef LONG            _PULONG;
+typedef LONG            _PVOID;
+
+#endif /* CONFIG_FW_ARC32 */
+
+#ifdef CONFIG_FW_ARC64
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__DI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__DI__)));
+typedef void            VOID;
+
+/* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
+   live is sane ...  */
+typedef CHAR            *_PCHAR;
+typedef SHORT           *_PSHORT;
+typedef LARGE_INTEGER   *_PLARGE_INTEGER;
+typedef LONG            *_PLONG;
+typedef UCHAR           *_PUCHAR;
+typedef USHORT          *_PUSHORT;
+typedef ULONG           *_PULONG;
+typedef VOID            *_PVOID;
+
+#endif /* CONFIG_FW_ARC64  */
+
+typedef CHAR            *PCHAR;
+typedef SHORT           *PSHORT;
+typedef LARGE_INTEGER   *PLARGE_INTEGER;
+typedef LONG            *PLONG;
+typedef UCHAR           *PUCHAR;
+typedef USHORT          *PUSHORT;
+typedef ULONG           *PULONG;
+typedef VOID            *PVOID;
+
+/*
+ * Return type of ArcGetDisplayStatus()
+ */
+typedef struct {
+        USHORT  CursorXPosition;
+        USHORT  CursorYPosition;
+        USHORT  CursorMaxXPosition;
+        USHORT  CursorMaxYPosition;
+        USHORT  ForegroundColor;
+        USHORT  BackgroundColor;
+        UCHAR   HighIntensity;
+        UCHAR   Underscored;
+        UCHAR   ReverseVideo;
+} DISPLAY_STATUS;
+
+#endif /* _ASM_ARC_TYPES_H */
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
new file mode 100644
index 000000000..6457f3689
--- /dev/null
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ */
+/*
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * This file contains declarations for doing callbacks to
+ * cfe from an application.  It should be the only header
+ * needed by the application to use this library
+ *
+ * Authors:  Mitch Lichtenberg, Chris Demetriou
+ */
+#ifndef CFE_API_H
+#define CFE_API_H
+
+#include <linux/types.h>
+#include <linux/string.h>
+
+typedef long intptr_t;
+
+
+/*
+ * Constants
+ */
+
+/* Seal indicating CFE's presence, passed to user program. */
+#define CFE_EPTSEAL 0x43464531
+
+#define CFE_MI_RESERVED 0       /* memory is reserved, do not use */
+#define CFE_MI_AVAILABLE 1      /* memory is available */
+
+#define CFE_FLG_WARMSTART     0x00000001
+#define CFE_FLG_FULL_ARENA    0x00000001
+#define CFE_FLG_ENV_PERMANENT 0x00000001
+
+#define CFE_CPU_CMD_START 1
+#define CFE_CPU_CMD_STOP 0
+
+#define CFE_STDHANDLE_CONSOLE   0
+
+#define CFE_DEV_NETWORK         1
+#define CFE_DEV_DISK            2
+#define CFE_DEV_FLASH           3
+#define CFE_DEV_SERIAL          4
+#define CFE_DEV_CPU             5
+#define CFE_DEV_NVRAM           6
+#define CFE_DEV_CLOCK           7
+#define CFE_DEV_OTHER           8
+#define CFE_DEV_MASK            0x0F
+
+#define CFE_CACHE_FLUSH_D       1
+#define CFE_CACHE_INVAL_I       2
+#define CFE_CACHE_INVAL_D       4
+#define CFE_CACHE_INVAL_L2      8
+
+#define CFE_FWI_64BIT           0x00000001
+#define CFE_FWI_32BIT           0x00000002
+#define CFE_FWI_RELOC           0x00000004
+#define CFE_FWI_UNCACHED        0x00000008
+#define CFE_FWI_MULTICPU        0x00000010
+#define CFE_FWI_FUNCSIM         0x00000020
+#define CFE_FWI_RTLSIM          0x00000040
+
+typedef struct {
+        int64_t fwi_version;            /* major, minor, eco version */
+        int64_t fwi_totalmem;           /* total installed mem */
+        int64_t fwi_flags;              /* various flags */
+        int64_t fwi_boardid;            /* board ID */
+        int64_t fwi_bootarea_va;        /* VA of boot area */
+        int64_t fwi_bootarea_pa;        /* PA of boot area */
+        int64_t fwi_bootarea_size;      /* size of boot area */
+} cfe_fwinfo_t;
+
+
+/*
+ * Defines and prototypes for functions which take no arguments.
+ */
+int64_t cfe_getticks(void);
+
+/*
+ * Defines and prototypes for the rest of the functions.
+ */
+int cfe_close(int handle);
+int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
+int cfe_cpu_stop(int cpu);
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
+int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
+                uint64_t * type);
+int cfe_exit(int warm, int status);
+int cfe_flushcache(int flg);
+int cfe_getdevinfo(char *name);
+int cfe_getenv(char *name, char *dest, int destlen);
+int cfe_getfwinfo(cfe_fwinfo_t * info);
+int cfe_getstdhandle(int flg);
+int cfe_init(uint64_t handle, uint64_t ept);
+int cfe_inpstat(int handle);
+int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+              int length, int *retlen, uint64_t offset);
+int cfe_open(char *name);
+int cfe_read(int handle, unsigned char *buffer, int length);
+int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
+                int length);
+int cfe_setenv(char *name, char *val);
+int cfe_write(int handle, const char *buffer, int length);
+int cfe_writeblk(int handle, int64_t offset, const char *buffer,
+                 int length);
+
+#endif                          /* CFE_API_H */
diff --git a/arch/mips/include/asm/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h
new file mode 100644
index 000000000..2f04a39fd
--- /dev/null
+++ b/arch/mips/include/asm/fw/cfe/cfe_error.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ */
+
+/*
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * CFE's global error code list is here.
+ *
+ * Author:  Mitch Lichtenberg
+ */
+
+#define CFE_OK                   0
+#define CFE_ERR                 -1      /* generic error */
+#define CFE_ERR_INV_COMMAND     -2
+#define CFE_ERR_EOF             -3
+#define CFE_ERR_IOERR           -4
+#define CFE_ERR_NOMEM           -5
+#define CFE_ERR_DEVNOTFOUND     -6
+#define CFE_ERR_DEVOPEN         -7
+#define CFE_ERR_INV_PARAM       -8
+#define CFE_ERR_ENVNOTFOUND     -9
+#define CFE_ERR_ENVREADONLY     -10
+
+#define CFE_ERR_NOTELF          -11
+#define CFE_ERR_NOT32BIT        -12
+#define CFE_ERR_WRONGENDIAN     -13
+#define CFE_ERR_BADELFVERS      -14
+#define CFE_ERR_NOTMIPS         -15
+#define CFE_ERR_BADELFFMT       -16
+#define CFE_ERR_BADADDR         -17
+
+#define CFE_ERR_FILENOTFOUND    -18
+#define CFE_ERR_UNSUPPORTED     -19
+
+#define CFE_ERR_HOSTUNKNOWN     -20
+
+#define CFE_ERR_TIMEOUT         -21
+
+#define CFE_ERR_PROTOCOLERR     -22
+
+#define CFE_ERR_NETDOWN         -23
+#define CFE_ERR_NONAMESERVER    -24
+
+#define CFE_ERR_NOHANDLES       -25
+#define CFE_ERR_ALREADYBOUND    -26
+
+#define CFE_ERR_CANNOTSET       -27
+#define CFE_ERR_NOMORE          -28
+#define CFE_ERR_BADFILESYS      -29
+#define CFE_ERR_FSNOTAVAIL      -30
+
+#define CFE_ERR_INVBOOTBLOCK    -31
+#define CFE_ERR_WRONGDEVTYPE    -32
+#define CFE_ERR_BBCHECKSUM      -33
+#define CFE_ERR_BOOTPROGCHKSUM  -34
+
+#define CFE_ERR_LDRNOTAVAIL     -35
+
+#define CFE_ERR_NOTREADY        -36
+
+#define CFE_ERR_GETMEM          -37
+#define CFE_ERR_SETMEM          -38
+
+#define CFE_ERR_NOTCONN         -39
+#define CFE_ERR_ADDRINUSE       -40
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h
new file mode 100644
index 000000000..d0494ce4b
--- /dev/null
+++ b/arch/mips/include/asm/fw/fw.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_FW_H_
+#define __ASM_FW_H_
+
+#include <asm/bootinfo.h>       /* For cleaner code... */
+
+extern int fw_argc;
+extern int *_fw_argv;
+extern int *_fw_envp;
+
+/*
+ * Most firmware like YAMON, PMON, etc. pass arguments and environment
+ * variables as 32-bit pointers. These take care of sign extension.
+ */
+#define fw_argv(index)          ((char *)(long)_fw_argv[(index)])
+#define fw_envp(index)          ((char *)(long)_fw_envp[(index)])
+
+extern void fw_init_cmdline(void);
+extern char *fw_getcmdline(void);
+extern void fw_meminit(void);
+extern char *fw_getenv(char *name);
+extern unsigned long fw_getenvl(char *name);
+extern void fw_init_early_console(void);
+
+#endif /* __ASM_FW_H_ */
diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h
new file mode 100644
index 000000000..6eb7c2b94
--- /dev/null
+++ b/arch/mips/include/asm/ginvt.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MIPS_ASM_GINVT_H__
+#define __MIPS_ASM_GINVT_H__
+
+#include <asm/mipsregs.h>
+
+enum ginvt_type {
+        GINVT_FULL,
+        GINVT_VA,
+        GINVT_MMID,
+};
+
+#ifdef TOOLCHAIN_SUPPORTS_GINV
+# define _ASM_SET_GINV  ".set   ginv\n"
+#else
+_ASM_MACRO_1R1I(ginvt, rs, type,
+                _ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8))
+                _ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9)));
+# define _ASM_SET_GINV
+#endif
+
+static __always_inline void ginvt(unsigned long addr, enum ginvt_type type)
+{
+        asm volatile(
+                ".set   push\n"
+                _ASM_SET_GINV
+                "       ginvt   %0, %1\n"
+                ".set   pop"
+                : /* no outputs */
+                : "r"(addr), "i"(type)
+                : "memory");
+}
+
+static inline void ginvt_full(void)
+{
+        ginvt(0, GINVT_FULL);
+}
+
+static inline void ginvt_va(unsigned long addr)
+{
+        addr &= PAGE_MASK << 1;
+        ginvt(addr, GINVT_VA);
+}
+
+static inline void ginvt_mmid(void)
+{
+        ginvt(0, GINVT_MMID);
+}
+
+static inline void ginvt_va_mmid(unsigned long addr)
+{
+        addr &= PAGE_MASK << 1;
+        ginvt(addr, GINVT_VA | GINVT_MMID);
+}
+
+#endif /* __MIPS_ASM_GINVT_H__ */
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
new file mode 100644
index 000000000..159087f53
--- /dev/null
+++ b/arch/mips/include/asm/gio_device.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+struct gio_device_id {
+        __u8 id;
+};
+
+struct gio_device {
+        struct device   dev;
+        struct resource resource;
+        unsigned int    irq;
+        unsigned int    slotno;
+
+        const char      *name;
+        struct gio_device_id id;
+        unsigned        id32:1;
+        unsigned        gio64:1;
+};
+#define to_gio_device(d) container_of(d, struct gio_device, dev)
+
+struct gio_driver {
+        const char    *name;
+        struct module *owner;
+        const struct gio_device_id *id_table;
+
+        int  (*probe)(struct gio_device *, const struct gio_device_id *);
+        void (*remove)(struct gio_device *);
+        void (*shutdown)(struct gio_device *);
+
+        struct device_driver driver;
+};
+#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
+
+extern struct gio_device *gio_dev_get(struct gio_device *);
+extern void gio_dev_put(struct gio_device *);
+
+extern int gio_device_register(struct gio_device *);
+extern void gio_device_unregister(struct gio_device *);
+extern void gio_release_dev(struct device *);
+
+static inline void gio_device_free(struct gio_device *dev)
+{
+        gio_release_dev(&dev->dev);
+}
+
+extern int gio_register_driver(struct gio_driver *);
+extern void gio_unregister_driver(struct gio_driver *);
+
+#define gio_get_drvdata(_dev)        dev_get_drvdata(&(_dev)->dev)
+#define gio_set_drvdata(_dev, data)  dev_set_drvdata(&(_dev)->dev, (data))
+
+extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
new file mode 100644
index 000000000..5d68d7265
--- /dev/null
+++ b/arch/mips/include/asm/gt64120.h
@@ -0,0 +1,566 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#define MSK(n)                  ((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS              0x000
+
+#define GT_MULTI_OFS            0x120
+
+/* CPU Address Decode.  */
+#define GT_SCS10LD_OFS          0x008
+#define GT_SCS10HD_OFS          0x010
+#define GT_SCS32LD_OFS          0x018
+#define GT_SCS32HD_OFS          0x020
+#define GT_CS20LD_OFS           0x028
+#define GT_CS20HD_OFS           0x030
+#define GT_CS3BOOTLD_OFS        0x038
+#define GT_CS3BOOTHD_OFS        0x040
+#define GT_PCI0IOLD_OFS         0x048
+#define GT_PCI0IOHD_OFS         0x050
+#define GT_PCI0M0LD_OFS         0x058
+#define GT_PCI0M0HD_OFS         0x060
+#define GT_ISD_OFS              0x068
+
+#define GT_PCI0M1LD_OFS         0x080
+#define GT_PCI0M1HD_OFS         0x088
+#define GT_PCI1IOLD_OFS         0x090
+#define GT_PCI1IOHD_OFS         0x098
+#define GT_PCI1M0LD_OFS         0x0a0
+#define GT_PCI1M0HD_OFS         0x0a8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+
+#define GT_SCS10AR_OFS          0x0d0
+#define GT_SCS32AR_OFS          0x0d8
+#define GT_CS20R_OFS            0x0e0
+#define GT_CS3BOOTR_OFS         0x0e8
+
+#define GT_PCI0IOREMAP_OFS      0x0f0
+#define GT_PCI0M0REMAP_OFS      0x0f8
+#define GT_PCI0M1REMAP_OFS      0x100
+#define GT_PCI1IOREMAP_OFS      0x108
+#define GT_PCI1M0REMAP_OFS      0x110
+#define GT_PCI1M1REMAP_OFS      0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS    0x070
+#define GT_CPUERR_ADDRHI_OFS    0x078
+
+#define GT_CPUERR_DATALO_OFS    0x128                   /* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS    0x130                   /* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS    0x138                   /* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS         0x0c0
+#define GT_PCI1SYNC_OFS         0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS           0x400
+#define GT_SCS0HD_OFS           0x404
+#define GT_SCS1LD_OFS           0x408
+#define GT_SCS1HD_OFS           0x40c
+#define GT_SCS2LD_OFS           0x410
+#define GT_SCS2HD_OFS           0x414
+#define GT_SCS3LD_OFS           0x418
+#define GT_SCS3HD_OFS           0x41c
+#define GT_CS0LD_OFS            0x420
+#define GT_CS0HD_OFS            0x424
+#define GT_CS1LD_OFS            0x428
+#define GT_CS1HD_OFS            0x42c
+#define GT_CS2LD_OFS            0x430
+#define GT_CS2HD_OFS            0x434
+#define GT_CS3LD_OFS            0x438
+#define GT_CS3HD_OFS            0x43c
+#define GT_BOOTLD_OFS           0x440
+#define GT_BOOTHD_OFS           0x444
+
+#define GT_ADERR_OFS            0x470
+
+/* SDRAM Configuration.  */
+#define GT_SDRAM_CFG_OFS        0x448
+
+#define GT_SDRAM_OPMODE_OFS     0x474
+#define GT_SDRAM_BM_OFS         0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS         0x44c
+#define GT_SDRAM_B1_OFS         0x450
+#define GT_SDRAM_B2_OFS         0x454
+#define GT_SDRAM_B3_OFS         0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS           0x45c
+#define GT_DEV_B1_OFS           0x460
+#define GT_DEV_B2_OFS           0x464
+#define GT_DEV_B3_OFS           0x468
+#define GT_DEV_BOOT_OFS         0x46c
+
+/* ECC.  */
+#define GT_ECC_ERRDATALO        0x480                   /* GT-64120A only  */
+#define GT_ECC_ERRDATAHI        0x484                   /* GT-64120A only  */
+#define GT_ECC_MEM              0x488                   /* GT-64120A only  */
+#define GT_ECC_CALC             0x48c                   /* GT-64120A only  */
+#define GT_ECC_ERRADDR          0x490                   /* GT-64120A only  */
+
+/* DMA Record.  */
+#define GT_DMA0_CNT_OFS         0x800
+#define GT_DMA1_CNT_OFS         0x804
+#define GT_DMA2_CNT_OFS         0x808
+#define GT_DMA3_CNT_OFS         0x80c
+#define GT_DMA0_SA_OFS          0x810
+#define GT_DMA1_SA_OFS          0x814
+#define GT_DMA2_SA_OFS          0x818
+#define GT_DMA3_SA_OFS          0x81c
+#define GT_DMA0_DA_OFS          0x820
+#define GT_DMA1_DA_OFS          0x824
+#define GT_DMA2_DA_OFS          0x828
+#define GT_DMA3_DA_OFS          0x82c
+#define GT_DMA0_NEXT_OFS        0x830
+#define GT_DMA1_NEXT_OFS        0x834
+#define GT_DMA2_NEXT_OFS        0x838
+#define GT_DMA3_NEXT_OFS        0x83c
+
+#define GT_DMA0_CUR_OFS         0x870
+#define GT_DMA1_CUR_OFS         0x874
+#define GT_DMA2_CUR_OFS         0x878
+#define GT_DMA3_CUR_OFS         0x87c
+
+/* DMA Channel Control.  */
+#define GT_DMA0_CTRL_OFS        0x840
+#define GT_DMA1_CTRL_OFS        0x844
+#define GT_DMA2_CTRL_OFS        0x848
+#define GT_DMA3_CTRL_OFS        0x84c
+
+/* DMA Arbiter.  */
+#define GT_DMA_ARB_OFS          0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS              0x850
+#define GT_TC1_OFS              0x854
+#define GT_TC2_OFS              0x858
+#define GT_TC3_OFS              0x85c
+
+#define GT_TC_CONTROL_OFS       0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS         0xc00
+#define GT_PCI0_TOR_OFS         0xc04
+#define GT_PCI0_BS_SCS10_OFS    0xc08
+#define GT_PCI0_BS_SCS32_OFS    0xc0c
+#define GT_PCI0_BS_CS20_OFS     0xc10
+#define GT_PCI0_BS_CS3BT_OFS    0xc14
+
+#define GT_PCI1_IACK_OFS        0xc30
+#define GT_PCI0_IACK_OFS        0xc34
+
+#define GT_PCI0_BARE_OFS        0xc3c
+#define GT_PCI0_PREFMBR_OFS     0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS   0xc48
+#define GT_PCI0_SCS32_BAR_OFS   0xc4c
+#define GT_PCI0_CS20_BAR_OFS    0xc50
+#define GT_PCI0_CS3BT_BAR_OFS   0xc54
+#define GT_PCI0_SSCS10_BAR_OFS  0xc58
+#define GT_PCI0_SSCS32_BAR_OFS  0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS  0xc64
+
+#define GT_PCI1_CMD_OFS         0xc80
+#define GT_PCI1_TOR_OFS         0xc84
+#define GT_PCI1_BS_SCS10_OFS    0xc88
+#define GT_PCI1_BS_SCS32_OFS    0xc8c
+#define GT_PCI1_BS_CS20_OFS     0xc90
+#define GT_PCI1_BS_CS3BT_OFS    0xc94
+
+#define GT_PCI1_BARE_OFS        0xcbc
+#define GT_PCI1_PREFMBR_OFS     0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS   0xcc8
+#define GT_PCI1_SCS32_BAR_OFS   0xccc
+#define GT_PCI1_CS20_BAR_OFS    0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS   0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS  0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS  0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS  0xce4
+
+#define GT_PCI1_CFGADDR_OFS     0xcf0
+#define GT_PCI1_CFGDATA_OFS     0xcf4
+#define GT_PCI0_CFGADDR_OFS     0xcf8
+#define GT_PCI0_CFGDATA_OFS     0xcfc
+
+/* Interrupts.  */
+#define GT_INTRCAUSE_OFS        0xc18
+#define GT_INTRMASK_OFS         0xc1c
+
+#define GT_PCI0_ICMASK_OFS      0xc24
+#define GT_PCI0_SERR0MASK_OFS   0xc28
+
+#define GT_CPU_INTSEL_OFS       0xc70
+#define GT_PCI0_INTSEL_OFS      0xc74
+
+#define GT_HINTRCAUSE_OFS       0xc98
+#define GT_HINTRMASK_OFS        0xc9c
+
+#define GT_PCI0_HICMASK_OFS     0xca4
+#define GT_PCI1_SERR1MASK_OFS   0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE              0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE              0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE             0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE             0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE              0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE       0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE        0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE             0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE      0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE       0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE    0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE                 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE            0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE     0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE     0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE     0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE     0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE    0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE    0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE    0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE    0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE              0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE              0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE             0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE             0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE              0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE       0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE        0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE             0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE      0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE       0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE    0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE                 0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE            0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF       12
+#define GT_CPU_ENDIAN_MSK       (MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT       GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF           16
+#define GT_CPU_WR_MSK           (MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT           GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX      0
+#define GT_CPU_WR_DDDD          1
+
+
+#define GT_PCI_DCRM_SHF         21
+#define GT_PCI_LD_SHF           0
+#define GT_PCI_LD_MSK           (MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF           0
+#define GT_PCI_HD_MSK           (MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF        0
+#define GT_PCI_REMAP_MSK        (MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF    31
+#define GT_CFGADDR_CFGEN_MSK    (MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT    GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF   16
+#define GT_CFGADDR_BUSNUM_MSK   (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF   11
+#define GT_CFGADDR_DEVNUM_MSK   (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF  8
+#define GT_CFGADDR_FUNCNUM_MSK  (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF   2
+#define GT_CFGADDR_REGNUM_MSK   (MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF   2
+#define GT_SDRAM_BM_ORDER_MSK   (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT   GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB   1
+#define GT_SDRAM_BM_ORDER_LIN   0
+
+#define GT_SDRAM_BM_RSVD_ALL1   0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF    0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK    (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0      0
+#define GT_SDRAM_ADDRDECODE_ADDR_1      1
+#define GT_SDRAM_ADDRDECODE_ADDR_2      2
+#define GT_SDRAM_ADDRDECODE_ADDR_3      3
+#define GT_SDRAM_ADDRDECODE_ADDR_4      4
+#define GT_SDRAM_ADDRDECODE_ADDR_5      5
+#define GT_SDRAM_ADDRDECODE_ADDR_6      6
+#define GT_SDRAM_ADDRDECODE_ADDR_7      7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF          0
+#define GT_SDRAM_B0_CASLAT_MSK          (MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2            1
+#define GT_SDRAM_B0_CASLAT_3            2
+
+#define GT_SDRAM_B0_FTDIS_SHF           2
+#define GT_SDRAM_B0_FTDIS_MSK           (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT           GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF       3
+#define GT_SDRAM_B0_SRASPRCHG_MSK       (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT       GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2         0
+#define GT_SDRAM_B0_SRASPRCHG_3         1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF        4
+#define GT_SDRAM_B0_B0COMPAB_MSK        (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT        GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF        5
+#define GT_SDRAM_B0_64BITINT_MSK        (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT        GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2          0
+#define GT_SDRAM_B0_64BITINT_4          1
+
+#define GT_SDRAM_B0_BW_SHF              6
+#define GT_SDRAM_B0_BW_MSK              (MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT              GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32               0
+#define GT_SDRAM_B0_BW_64               1
+
+#define GT_SDRAM_B0_BLODD_SHF           7
+#define GT_SDRAM_B0_BLODD_MSK           (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT           GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF             8
+#define GT_SDRAM_B0_PAR_MSK             (MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT             GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF          9
+#define GT_SDRAM_B0_BYPASS_MSK          (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT          GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF       10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK       (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT       GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2         0
+#define GT_SDRAM_B0_SRAS2SCAS_3         1
+
+#define GT_SDRAM_B0_SIZE_SHF            11
+#define GT_SDRAM_B0_SIZE_MSK            (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT            GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M            0
+#define GT_SDRAM_B0_SIZE_64M            1
+
+#define GT_SDRAM_B0_EXTPAR_SHF          12
+#define GT_SDRAM_B0_EXTPAR_MSK          (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT          GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF            13
+#define GT_SDRAM_B0_BLEN_MSK            (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT            GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8              0
+#define GT_SDRAM_B0_BLEN_4              1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF         0
+#define GT_SDRAM_CFG_REFINT_MSK         (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF    14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK    (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT    GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF            15
+#define GT_SDRAM_CFG_RMW_MSK            (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT            GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF     16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK     (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT     GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF        19
+#define GT_SDRAM_CFG_DUPCNTL_MSK        (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT        GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF          20
+#define GT_SDRAM_CFG_DUPBA_MSK          (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT          GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF        21
+#define GT_SDRAM_CFG_DUPEOT0_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT        GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF        22
+#define GT_SDRAM_CFG_DUPEOT1_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT        GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF          0
+#define GT_SDRAM_OPMODE_OP_MSK          (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL       0
+#define GT_SDRAM_OPMODE_OP_NOP          1
+#define GT_SDRAM_OPMODE_OP_PRCHG        2
+#define GT_SDRAM_OPMODE_OP_MODE         3
+#define GT_SDRAM_OPMODE_OP_CBR          4
+
+#define GT_TC_CONTROL_ENTC0_SHF         0
+#define GT_TC_CONTROL_ENTC0_MSK         (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
+#define GT_TC_CONTROL_ENTC0_BIT         GT_TC_CONTROL_ENTC0_MSK
+#define GT_TC_CONTROL_SELTC0_SHF        1
+#define GT_TC_CONTROL_SELTC0_MSK        (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
+#define GT_TC_CONTROL_SELTC0_BIT        GT_TC_CONTROL_SELTC0_MSK
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF  0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK  (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT  GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF     1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT     GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF     2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT     GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF       3
+#define GT_PCI0_BARE_INTIODIS_MSK       (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT       GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF      4
+#define GT_PCI0_BARE_INTMEMDIS_MSK      (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT      GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF     5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK     (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT     GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF        6
+#define GT_PCI0_BARE_CS20DIS_MSK        (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT        GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF       7
+#define GT_PCI0_BARE_SCS32DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT       GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF       8
+#define GT_PCI0_BARE_SCS10DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT       GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF      18
+#define GT_INTRCAUSE_MASABORT0_MSK      (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT      GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF      19
+#define GT_INTRCAUSE_TARABORT0_MSK      (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT      GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF      2
+#define GT_PCI0_CFGADDR_REGNUM_MSK      (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF    8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF      11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK      (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF      16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK      (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF    31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK    (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT    GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF       0
+#define GT_PCI0_CMD_MBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT       GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF       10
+#define GT_PCI0_CMD_MWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT       GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF       16
+#define GT_PCI0_CMD_SBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT       GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF       11
+#define GT_PCI0_CMD_SWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT       GT_PCI0_CMD_SWORDSWAP_MSK
+
+#define GT_INTR_T0EXP_SHF               8
+#define GT_INTR_T0EXP_MSK               (MSK(1) << GT_INTR_T0EXP_SHF)
+#define GT_INTR_T0EXP_BIT               GT_INTR_T0EXP_MSK
+#define GT_INTR_RETRYCTR0_SHF           20
+#define GT_INTR_RETRYCTR0_MSK           (MSK(1) << GT_INTR_RETRYCTR0_SHF)
+#define GT_INTR_RETRYCTR0_BIT           GT_INTR_RETRYCTR0_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE     0x10000000UL
+#define GT_DEF_PCI0_IO_SIZE     0x02000000UL
+#define GT_DEF_PCI0_MEM0_BASE   0x12000000UL
+#define GT_DEF_PCI0_MEM0_SIZE   0x02000000UL
+#define GT_DEF_BASE             0x14000000UL
+
+#define GT_MAX_BANKSIZE         (256 * 1024 * 1024)     /* Max 256MB bank  */
+#define GT_LATTIM_MIN           6                       /* Minimum lat  */
+
+/*
+ * The gt64120_dep.h file must define the following macros
+ *
+ *   GT_READ(ofs, data_pointer)
+ *   GT_WRITE(ofs, data)           - read/write GT64120 registers in 32bit
+ *
+ *   TIMER      - gt64120 timer irq, temporary solution until
+ *                full gt64120 cascade interrupt support is in place
+ */
+
+#include <mach-gt64120.h>
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.  We also provide non-swapping versions.
+ */
+#define __GT_READ(ofs)                                                  \
+        (*(volatile u32 *)(GT64120_BASE+(ofs)))
+#define __GT_WRITE(ofs, data)                                           \
+        do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+#define GT_READ(ofs)            le32_to_cpu(__GT_READ(ofs))
+#define GT_WRITE(ofs, data)     __GT_WRITE(ofs, cpu_to_le32(data))
+
+extern void gt641xx_set_base_clock(unsigned int clock);
+extern int gt641xx_timer0_state(void);
+
+#endif /* _ASM_GT64120_H */
diff --git a/arch/mips/include/asm/hardirq.h b/arch/mips/include/asm/hardirq.h
new file mode 100644
index 000000000..c977a86c2
--- /dev/null
+++ b/arch/mips/include/asm/hardirq.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_HARDIRQ_H
+#define _ASM_HARDIRQ_H
+
+extern void ack_bad_irq(unsigned int irq);
+#define ack_bad_irq ack_bad_irq
+
+#include <asm-generic/hardirq.h>
+
+#endif /* _ASM_HARDIRQ_H */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
new file mode 100644
index 000000000..f855478d1
--- /dev/null
+++ b/arch/mips/include/asm/hazards.h
@@ -0,0 +1,422 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) MIPS Technologies, Inc.
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef _ASM_HAZARDS_H
+#define _ASM_HAZARDS_H
+
+#include <linux/stringify.h>
+#include <asm/compiler.h>
+
+#define ___ssnop                                                        \
+        sll     $0, $0, 1
+
+#define ___ehb                                                          \
+        sll     $0, $0, 3
+
+/*
+ * TLB hazards
+ */
+#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
+     defined(CONFIG_CPU_MIPSR6)) && \
+    !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
+
+/*
+ * MIPSR2 defines ehb for hazard avoidance
+ */
+
+#define __mtc0_tlbw_hazard                                              \
+        ___ehb
+
+#define __mtc0_tlbr_hazard                                              \
+        ___ehb
+
+#define __tlbw_use_hazard                                               \
+        ___ehb
+
+#define __tlb_read_hazard                                               \
+        ___ehb
+
+#define __tlb_probe_hazard                                              \
+        ___ehb
+
+#define __irq_enable_hazard                                             \
+        ___ehb
+
+#define __irq_disable_hazard                                            \
+        ___ehb
+
+#define __back_to_back_c0_hazard                                        \
+        ___ehb
+
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler.  Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alternative is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code...
+ */
+#define instruction_hazard()                                            \
+do {                                                                    \
+        unsigned long tmp;                                              \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set "MIPS_ISA_LEVEL"                           \n"     \
+        "       dla     %0, 1f                                  \n"     \
+        "       jr.hb   %0                                      \n"     \
+        "       .set    pop                                     \n"     \
+        "1:                                                     \n"     \
+        : "=r" (tmp));                                                  \
+} while (0)
+
+#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
+        defined(CONFIG_CPU_BMIPS)
+
+/*
+ * These are slightly complicated by the fact that we guarantee R1 kernels to
+ * run fine on R2 processors.
+ */
+
+#define __mtc0_tlbw_hazard                                              \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __mtc0_tlbr_hazard                                              \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __tlbw_use_hazard                                               \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __tlb_read_hazard                                               \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __tlb_probe_hazard                                              \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __irq_enable_hazard                                             \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __irq_disable_hazard                                            \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+#define __back_to_back_c0_hazard                                        \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ehb
+
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler.  Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alternative is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code...
+ */
+#define __instruction_hazard()                                          \
+do {                                                                    \
+        unsigned long tmp;                                              \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips64r2                                \n"     \
+        "       dla     %0, 1f                                  \n"     \
+        "       jr.hb   %0                                      \n"     \
+        "       .set    pop                                     \n"     \
+        "1:                                                     \n"     \
+        : "=r" (tmp));                                                  \
+} while (0)
+
+#define instruction_hazard()                                            \
+do {                                                                    \
+        if (cpu_has_mips_r2_r6)                                         \
+                __instruction_hazard();                                 \
+} while (0)
+
+#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+        defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
+        defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+#define __mtc0_tlbw_hazard
+
+#define __mtc0_tlbr_hazard
+
+#define __tlbw_use_hazard
+
+#define __tlb_read_hazard
+
+#define __tlb_probe_hazard
+
+#define __irq_enable_hazard
+
+#define __irq_disable_hazard
+
+#define __back_to_back_c0_hazard
+
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_SB1)
+
+/*
+ * Mostly like R4000 for historic reasons
+ */
+#define __mtc0_tlbw_hazard
+
+#define __mtc0_tlbr_hazard
+
+#define __tlbw_use_hazard
+
+#define __tlb_read_hazard
+
+#define __tlb_probe_hazard
+
+#define __irq_enable_hazard
+
+#define __irq_disable_hazard                                            \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop
+
+#define __back_to_back_c0_hazard
+
+#define instruction_hazard() do { } while (0)
+
+#else
+
+/*
+ * Finally the catchall case for all other processors including R4000, R4400,
+ * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
+ *
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400.  Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.
+ */
+#define __mtc0_tlbw_hazard                                              \
+        nop;                                                            \
+        nop
+
+#define __mtc0_tlbr_hazard                                              \
+        nop;                                                            \
+        nop
+
+#define __tlbw_use_hazard                                               \
+        nop;                                                            \
+        nop;                                                            \
+        nop
+
+#define __tlb_read_hazard                                               \
+        nop;                                                            \
+        nop;                                                            \
+        nop
+
+#define __tlb_probe_hazard                                              \
+        nop;                                                            \
+        nop;                                                            \
+        nop
+
+#define __irq_enable_hazard                                             \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop
+
+#define __irq_disable_hazard                                            \
+        nop;                                                            \
+        nop;                                                            \
+        nop
+
+#define __back_to_back_c0_hazard                                        \
+        ___ssnop;                                                       \
+        ___ssnop;                                                       \
+        ___ssnop
+
+#define instruction_hazard() do { } while (0)
+
+#endif
+
+
+/* FPU hazards */
+
+#if defined(CONFIG_CPU_SB1)
+
+#define __enable_fpu_hazard                                             \
+        .set    push;                                                   \
+        .set    mips64;                                                 \
+        .set    noreorder;                                              \
+        ___ssnop;                                                       \
+        bnezl   $0, .+4;                                                \
+        ___ssnop;                                                       \
+        .set    pop
+
+#define __disable_fpu_hazard
+
+#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
+      defined(CONFIG_CPU_MIPSR6)
+
+#define __enable_fpu_hazard                                             \
+        ___ehb
+
+#define __disable_fpu_hazard                                            \
+        ___ehb
+
+#else
+
+#define __enable_fpu_hazard                                             \
+        nop;                                                            \
+        nop;                                                            \
+        nop;                                                            \
+        nop
+
+#define __disable_fpu_hazard                                            \
+        ___ehb
+
+#endif
+
+#ifdef __ASSEMBLY__
+
+#define _ssnop ___ssnop
+#define _ehb ___ehb
+#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
+#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
+#define tlbw_use_hazard __tlbw_use_hazard
+#define tlb_read_hazard __tlb_read_hazard
+#define tlb_probe_hazard __tlb_probe_hazard
+#define irq_enable_hazard __irq_enable_hazard
+#define irq_disable_hazard __irq_disable_hazard
+#define back_to_back_c0_hazard __back_to_back_c0_hazard
+#define enable_fpu_hazard __enable_fpu_hazard
+#define disable_fpu_hazard __disable_fpu_hazard
+
+#else
+
+#define _ssnop()                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(___ssnop)                                           \
+        );                                                              \
+} while (0)
+
+#define _ehb()                                                          \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(___ehb)                                             \
+        );                                                              \
+} while (0)
+
+
+#define mtc0_tlbw_hazard()                                              \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__mtc0_tlbw_hazard)                                 \
+        );                                                              \
+} while (0)
+
+
+#define mtc0_tlbr_hazard()                                              \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__mtc0_tlbr_hazard)                                 \
+        );                                                              \
+} while (0)
+
+
+#define tlbw_use_hazard()                                               \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__tlbw_use_hazard)                                  \
+        );                                                              \
+} while (0)
+
+
+#define tlb_read_hazard()                                               \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__tlb_read_hazard)                                  \
+        );                                                              \
+} while (0)
+
+
+#define tlb_probe_hazard()                                              \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__tlb_probe_hazard)                                 \
+        );                                                              \
+} while (0)
+
+
+#define irq_enable_hazard()                                             \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__irq_enable_hazard)                                \
+        );                                                              \
+} while (0)
+
+
+#define irq_disable_hazard()                                            \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__irq_disable_hazard)                               \
+        );                                                              \
+} while (0)
+
+
+#define back_to_back_c0_hazard()                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__back_to_back_c0_hazard)                           \
+        );                                                              \
+} while (0)
+
+
+#define enable_fpu_hazard()                                             \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__enable_fpu_hazard)                                \
+        );                                                              \
+} while (0)
+
+
+#define disable_fpu_hazard()                                            \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        __stringify(__disable_fpu_hazard)                               \
+        );                                                              \
+} while (0)
+
+/*
+ * MIPS R2 instruction hazard barrier.   Needs to be called as a subroutine.
+ */
+extern void mips_ihb(void);
+
+#endif /* __ASSEMBLY__  */
+
+#endif /* _ASM_HAZARDS_H */
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
new file mode 100644
index 000000000..9f021cf51
--- /dev/null
+++ b/arch/mips/include/asm/highmem.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/cpu-features.h>
+#include <asm/kmap_types.h>
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) || defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#define LAST_PKMAP 512
+#else
+#define LAST_PKMAP 1024
+#endif
+
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define ARCH_HAS_KMAP_FLUSH_TLB
+extern void kmap_flush_tlb(unsigned long addr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+
+#define flush_cache_kmaps()     BUG_ON(cpu_has_dc_aliases)
+
+extern void kmap_init(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/mips/include/asm/hpet.h b/arch/mips/include/asm/hpet.h
new file mode 100644
index 000000000..d47268ece
--- /dev/null
+++ b/arch/mips/include/asm/hpet.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_HPET_H
+#define _ASM_HPET_H
+
+#ifdef CONFIG_RS780_HPET
+
+#define HPET_MMAP_SIZE          1024
+
+#define HPET_ID                 0x000
+#define HPET_PERIOD             0x004
+#define HPET_CFG                0x010
+#define HPET_STATUS             0x020
+#define HPET_COUNTER    0x0f0
+
+#define HPET_Tn_CFG(n)          (0x100 + 0x20 * n)
+#define HPET_Tn_CMP(n)          (0x108 + 0x20 * n)
+#define HPET_Tn_ROUTE(n)        (0x110 + 0x20 * n)
+
+#define HPET_T0_IRS             0x001
+#define HPET_T1_IRS             0x002
+#define HPET_T3_IRS             0x004
+
+#define HPET_T0_CFG             0x100
+#define HPET_T0_CMP             0x108
+#define HPET_T0_ROUTE   0x110
+#define HPET_T1_CFG             0x120
+#define HPET_T1_CMP             0x128
+#define HPET_T1_ROUTE   0x130
+#define HPET_T2_CFG             0x140
+#define HPET_T2_CMP             0x148
+#define HPET_T2_ROUTE   0x150
+
+#define HPET_ID_REV                     0x000000ff
+#define HPET_ID_NUMBER          0x00001f00
+#define HPET_ID_64BIT           0x00002000
+#define HPET_ID_LEGSUP          0x00008000
+#define HPET_ID_VENDOR          0xffff0000
+#define HPET_ID_NUMBER_SHIFT    8
+#define HPET_ID_VENDOR_SHIFT    16
+
+#define HPET_CFG_ENABLE         0x001
+#define HPET_CFG_LEGACY         0x002
+#define HPET_LEGACY_8254                2
+#define HPET_LEGACY_RTC         8
+
+#define HPET_TN_LEVEL           0x0002
+#define HPET_TN_ENABLE          0x0004
+#define HPET_TN_PERIODIC        0x0008
+#define HPET_TN_PERIODIC_CAP    0x0010
+#define HPET_TN_64BIT_CAP       0x0020
+#define HPET_TN_SETVAL          0x0040
+#define HPET_TN_32BIT           0x0100
+#define HPET_TN_ROUTE           0x3e00
+#define HPET_TN_FSB                     0x4000
+#define HPET_TN_FSB_CAP         0x8000
+#define HPET_TN_ROUTE_SHIFT     9
+
+/* Max HPET Period is 10^8 femto sec as in HPET spec */
+#define HPET_MAX_PERIOD         100000000UL
+/*
+ * Min HPET period is 10^5 femto sec just for safety. If it is less than this,
+ * then 32 bit HPET counter wrapsaround in less than 0.5 sec.
+ */
+#define HPET_MIN_PERIOD         100000UL
+
+#define HPET_ADDR               0x20000
+#define HPET_MMIO_ADDR  0x90000e0000020000
+#define HPET_FREQ               14318780
+#define HPET_COMPARE_VAL        ((HPET_FREQ + HZ / 2) / HZ)
+#define HPET_T0_IRQ             0
+
+extern void __init setup_hpet_timer(void);
+#endif /* CONFIG_RS780_HPET */
+#endif /* _ASM_HPET_H */
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
new file mode 100644
index 000000000..c2144409c
--- /dev/null
+++ b/arch/mips/include/asm/hugetlb.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008, 2009 Cavium Networks, Inc.
+ */
+
+#ifndef __ASM_HUGETLB_H
+#define __ASM_HUGETLB_H
+
+#include <asm/page.h>
+
+#define __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr,
+                                         unsigned long len)
+{
+        unsigned long task_size = STACK_TOP;
+        struct hstate *h = hstate_file(file);
+
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        if (len > task_size)
+                return -ENOMEM;
+        if (task_size - len < addr)
+                return -EINVAL;
+        return 0;
+}
+
+#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        pte_t clear;
+        pte_t pte = *ptep;
+
+        pte_val(clear) = (unsigned long)invalid_pte_table;
+        set_pte_at(mm, addr, ptep, clear);
+        return pte;
+}
+
+#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+        /*
+         * clear the huge pte entry firstly, so that the other smp threads will
+         * not get old pte entry after finishing flush_tlb_page and before
+         * setting new huge pte entry
+         */
+        huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
+        flush_tlb_page(vma, addr);
+}
+
+#define __HAVE_ARCH_HUGE_PTE_NONE
+static inline int huge_pte_none(pte_t pte)
+{
+        unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
+        return !val || (val == (unsigned long)invalid_pte_table);
+}
+
+#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr,
+                                             pte_t *ptep, pte_t pte,
+                                             int dirty)
+{
+        int changed = !pte_same(*ptep, pte);
+
+        if (changed) {
+                set_pte_at(vma->vm_mm, addr, ptep, pte);
+                /*
+                 * There could be some standard sized pages in there,
+                 * get them all.
+                 */
+                flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
+        }
+        return changed;
+}
+
+#include <asm-generic/hugetlb.h>
+
+#endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h
new file mode 100644
index 000000000..9e8ef5994
--- /dev/null
+++ b/arch/mips/include/asm/hw_irq.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2001, 2002 by Ralf Baechle
+ */
+#ifndef __ASM_HW_IRQ_H
+#define __ASM_HW_IRQ_H
+
+#include <linux/atomic.h>
+
+extern atomic_t irq_err_count;
+
+/*
+ * interrupt-retrigger: NOP for now. This may not be appropriate for all
+ * machines, we'll see ...
+ */
+
+#endif /* __ASM_HW_IRQ_H */
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
new file mode 100644
index 000000000..a54b9649d
--- /dev/null
+++ b/arch/mips/include/asm/i8259.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/i8259.h
+ *
+ *      i8259A interrupt definitions.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ *      Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef _ASM_I8259_H
+#define _ASM_I8259_H
+
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+#include <irq.h>
+
+/* i8259A PIC registers */
+#define PIC_MASTER_CMD          0x20
+#define PIC_MASTER_IMR          0x21
+#define PIC_MASTER_ISR          PIC_MASTER_CMD
+#define PIC_MASTER_POLL         PIC_MASTER_ISR
+#define PIC_MASTER_OCW3         PIC_MASTER_ISR
+#define PIC_SLAVE_CMD           0xa0
+#define PIC_SLAVE_IMR           0xa1
+
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR          2
+#define MASTER_ICW4_DEFAULT     0x01
+#define SLAVE_ICW4_DEFAULT      0x01
+#define PIC_ICW4_AEOI           2
+
+extern raw_spinlock_t i8259A_lock;
+
+extern void make_8259A_irq(unsigned int irq);
+
+extern void init_i8259_irqs(void);
+extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
+
+/**
+ * i8159_set_poll() - Override the i8259 polling function
+ * @poll: pointer to platform-specific polling function
+ *
+ * Call this to override the generic i8259 polling function, which directly
+ * accesses i8259 registers, with a platform specific one which may be faster
+ * in cases where hardware provides a more optimal means of polling for an
+ * interrupt.
+ */
+extern void i8259_set_poll(int (*poll)(void));
+
+/*
+ * Do the traditional i8259 interrupt polling thing.  This is for the few
+ * cases where no better interrupt acknowledge method is available and we
+ * absolutely must touch the i8259.
+ */
+static inline int i8259_irq(void)
+{
+        int irq;
+
+        raw_spin_lock(&i8259A_lock);
+
+        /* Perform an interrupt acknowledge cycle on controller 1. */
+        outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
+        irq = inb(PIC_MASTER_CMD) & 7;
+        if (irq == PIC_CASCADE_IR) {
+                /*
+                 * Interrupt is cascaded so perform interrupt
+                 * acknowledge on controller 2.
+                 */
+                outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
+                irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
+        }
+
+        if (unlikely(irq == 7)) {
+                /*
+                 * This may be a spurious interrupt.
+                 *
+                 * Read the interrupt status register (ISR). If the most
+                 * significant bit is not set then there is no valid
+                 * interrupt.
+                 */
+                outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
+                if(~inb(PIC_MASTER_ISR) & 0x80)
+                        irq = -1;
+        }
+
+        raw_spin_unlock(&i8259A_lock);
+
+        return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
+}
+
+#endif /* _ASM_I8259_H */
diff --git a/arch/mips/include/asm/ide.h b/arch/mips/include/asm/ide.h
new file mode 100644
index 000000000..bb674c3b0
--- /dev/null
+++ b/arch/mips/include/asm/ide.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file contains the MIPS architecture specific IDE code.
+ */
+#ifndef __ASM_IDE_H
+#define __ASM_IDE_H
+
+#include <ide.h>
+
+#endif /* __ASM_IDE_H */
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
new file mode 100644
index 000000000..0992cad9c
--- /dev/null
+++ b/arch/mips/include/asm/idle.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_IDLE_H
+#define __ASM_IDLE_H
+
+#include <linux/cpuidle.h>
+#include <linux/linkage.h>
+
+extern void (*cpu_wait)(void);
+extern void r4k_wait(void);
+extern asmlinkage void __r4k_wait(void);
+extern void r4k_wait_irqoff(void);
+
+static inline int using_rollback_handler(void)
+{
+        return cpu_wait == r4k_wait;
+}
+
+extern void __init check_wait(void);
+
+extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
+                                   struct cpuidle_driver *drv, int index);
+
+#define MIPS_CPUIDLE_WAIT_STATE {\
+        .enter                  = mips_cpuidle_wait_enter,\
+        .exit_latency           = 1,\
+        .target_residency       = 1,\
+        .power_usage            = UINT_MAX,\
+        .name                   = "wait",\
+        .desc                   = "MIPS wait",\
+}
+
+#endif /* __ASM_IDLE_H  */
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
new file mode 100644
index 000000000..22912f784
--- /dev/null
+++ b/arch/mips/include/asm/inst.h
@@ -0,0 +1,88 @@
+/*
+ * Format of an instruction in memory.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2000 by Ralf Baechle
+ * Copyright (C) 2006 by Thiemo Seufer
+ */
+#ifndef _ASM_INST_H
+#define _ASM_INST_H
+
+#include <uapi/asm/inst.h>
+
+/* HACHACHAHCAHC ...  */
+
+/* In case some other massaging is needed, keep MIPSInst as wrapper */
+
+#define MIPSInst(x) x
+
+#define I_OPCODE_SFT    26
+#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
+
+#define I_JTARGET_SFT   0
+#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
+
+#define I_RS_SFT        21
+#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
+
+#define I_RT_SFT        16
+#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
+
+#define I_IMM_SFT       0
+#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
+#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
+
+#define I_CACHEOP_SFT   18
+#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
+
+#define I_CACHESEL_SFT  16
+#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
+
+#define I_RD_SFT        11
+#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
+
+#define I_RE_SFT        6
+#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
+
+#define I_FUNC_SFT      0
+#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
+
+#define I_FFMT_SFT      21
+#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
+
+#define I_FT_SFT        16
+#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
+
+#define I_FS_SFT        11
+#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
+
+#define I_FD_SFT        6
+#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
+
+#define I_FR_SFT        21
+#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
+
+#define I_FMA_FUNC_SFT  2
+#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
+
+#define I_FMA_FFMT_SFT  0
+#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
+
+typedef unsigned int mips_instruction;
+
+/* microMIPS instruction decode structure. Do NOT export!!! */
+struct mm_decoded_insn {
+        mips_instruction insn;
+        mips_instruction next_insn;
+        int pc_inc;
+        int next_pc_inc;
+        int micro_mips_mode;
+};
+
+/* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
+extern const int reg16to32[];
+
+#endif /* _ASM_INST_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
new file mode 100644
index 000000000..78537aa23
--- /dev/null
+++ b/arch/mips/include/asm/io.h
@@ -0,0 +1,562 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf GmbH
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Author: Maciej W. Rozycki <macro@mips.com>
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#define ARCH_HAS_IOREMAP_WC
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/irqflags.h>
+
+#include <asm/addrspace.h>
+#include <asm/barrier.h>
+#include <asm/bug.h>
+#include <asm/byteorder.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm-generic/iomap.h>
+#include <asm/page.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+#include <mangle-port.h>
+
+/*
+ * Raw operations are never swapped in software.  OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware.  An example use would be for flash memory that's used for
+ * execute in place.
+ */
+# define __raw_ioswabb(a, x)    (x)
+# define __raw_ioswabw(a, x)    (x)
+# define __raw_ioswabl(a, x)    (x)
+# define __raw_ioswabq(a, x)    (x)
+# define ____raw_ioswabq(a, x)  (x)
+
+# define __relaxed_ioswabb ioswabb
+# define __relaxed_ioswabw ioswabw
+# define __relaxed_ioswabl ioswabl
+# define __relaxed_ioswabq ioswabq
+
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. mips_io_port_base is the virtual address to
+ * which all ports are being mapped.  For sake of efficiency some code
+ * assumes that this is an address that can be loaded with a single lui
+ * instruction, so the lower 16 bits must be zero.  Should be true on
+ * any sane architecture; generic code does not use this assumption.
+ */
+extern unsigned long mips_io_port_base;
+
+static inline void set_io_port_base(unsigned long base)
+{
+        mips_io_port_base = base;
+}
+
+/*
+ * Provide the necessary definitions for generic iomap. We make use of
+ * mips_io_port_base for iomap(), but we don't reserve any low addresses for
+ * use with I/O ports.
+ */
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET      mips_io_port_base
+#define PIO_MASK        IO_SPACE_LIMIT
+#define PIO_RESERVED    0x0UL
+
+/*
+ * Enforce in-order execution of data I/O.  In the MIPS architecture
+ * these are equivalent to corresponding platform-specific memory
+ * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
+ * with sync additionally defined.
+ */
+#define iobarrier_rw() mb()
+#define iobarrier_r() rmb()
+#define iobarrier_w() wmb()
+#define iobarrier_sync() iob()
+
+/*
+ *     virt_to_phys    -       map virtual addresses to physical
+ *     @address: address to remap
+ *
+ *     The returned physical address is the physical (CPU) mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses directly mapped or allocated via kmalloc.
+ *
+ *     This function does not give bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline unsigned long virt_to_phys(volatile const void *address)
+{
+        return __pa(address);
+}
+
+/*
+ *     phys_to_virt    -       map physical address to virtual
+ *     @address: address to remap
+ *
+ *     The returned virtual address is a current CPU mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses that have a kernel mapping
+ *
+ *     This function does not handle bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
+}
+
+/*
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
+ */
+static inline unsigned long isa_virt_to_bus(volatile void *address)
+{
+        return virt_to_phys(address);
+}
+
+static inline void *isa_bus_to_virt(unsigned long address)
+{
+        return phys_to_virt(address);
+}
+
+/*
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
+ */
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
+
+void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
+                unsigned long prot_val);
+void iounmap(const volatile void __iomem *addr);
+
+/*
+ * ioremap     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ */
+#define ioremap(offset, size)                                           \
+        ioremap_prot((offset), (size), _CACHE_UNCACHED)
+#define ioremap_uc              ioremap
+
+/*
+ * ioremap_cache -      map bus memory into CPU space
+ * @offset:         bus address of the memory
+ * @size:           size of the resource to map
+ *
+ * ioremap_cache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU.  Also enables full write-combining.  Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cache(offset, size)                                     \
+        ioremap_prot((offset), (size), _page_cachable_default)
+
+/*
+ * ioremap_wc     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap_wc performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * but accelerated by means of write-combining feature. It is specifically
+ * useful for PCIe prefetchable windows, which may vastly improve a
+ * communications performance. If it was determined on boot stage, what
+ * CPU CCA doesn't support UCA, the method shall fall-back to the
+ * _CACHE_UNCACHED option (see cpu_probe() method).
+ */
+#define ioremap_wc(offset, size)                                        \
+        ioremap_prot((offset), (size), boot_cpu_data.writecombine)
+
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
+#define war_io_reorder_wmb()            wmb()
+#else
+#define war_io_reorder_wmb()            barrier()
+#endif
+
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)     \
+                                                                        \
+static inline void pfx##write##bwlq(type val,                           \
+                                    volatile void __iomem *mem)         \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        if (barrier)                                                    \
+                iobarrier_rw();                                         \
+        else                                                            \
+                war_io_reorder_wmb();                                   \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        __val = pfx##ioswab##bwlq(__mem, val);                          \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                *__mem = __val;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                type __tmp;                                             \
+                                                                        \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
+                __asm__ __volatile__(                                   \
+                        ".set   push"           "\t\t# __writeq""\n\t"  \
+                        ".set   arch=r4000"                     "\n\t"  \
+                        "dsll32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsrl32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsll32 %M0, %M0, 0"                    "\n\t"  \
+                        "or     %L0, %L0, %M0"                  "\n\t"  \
+                        "sd     %L0, %2"                        "\n\t"  \
+                        ".set   pop"                            "\n"    \
+                        : "=r" (__tmp)                                  \
+                        : "0" (__val), "m" (*__mem));                   \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
+        } else                                                          \
+                BUG();                                                  \
+}                                                                       \
+                                                                        \
+static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        if (barrier)                                                    \
+                iobarrier_rw();                                         \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                __val = *__mem;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                                                                        \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
+                __asm__ __volatile__(                                   \
+                        ".set   push"           "\t\t# __readq" "\n\t"  \
+                        ".set   arch=r4000"                     "\n\t"  \
+                        "ld     %L0, %1"                        "\n\t"  \
+                        "dsra32 %M0, %L0, 0"                    "\n\t"  \
+                        "sll    %L0, %L0, 0"                    "\n\t"  \
+                        ".set   pop"                            "\n"    \
+                        : "=r" (__val)                                  \
+                        : "m" (*__mem));                                \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
+        } else {                                                        \
+                __val = 0;                                              \
+                BUG();                                                  \
+        }                                                               \
+                                                                        \
+        /* prevent prefetching of coherent DMA data prematurely */      \
+        if (!relax)                                                     \
+                rmb();                                                  \
+        return pfx##ioswab##bwlq(__mem, __val);                         \
+}
+
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p)       \
+                                                                        \
+static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        if (barrier)                                                    \
+                iobarrier_rw();                                         \
+        else                                                            \
+                war_io_reorder_wmb();                                   \
+                                                                        \
+        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+                                                                        \
+        __val = pfx##ioswab##bwlq(__addr, val);                         \
+                                                                        \
+        /* Really, we want this to be atomic */                         \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        *__addr = __val;                                                \
+}                                                                       \
+                                                                        \
+static inline type pfx##in##bwlq##p(unsigned long port)                 \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+                                                                        \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        if (barrier)                                                    \
+                iobarrier_rw();                                         \
+                                                                        \
+        __val = *__addr;                                                \
+                                                                        \
+        /* prevent prefetching of coherent DMA data prematurely */      \
+        if (!relax)                                                     \
+                rmb();                                                  \
+        return pfx##ioswab##bwlq(__addr, __val);                        \
+}
+
+#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)                      \
+                                                                        \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
+
+#define BUILDIO_MEM(bwlq, type)                                         \
+                                                                        \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)                               \
+__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)                           \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)                               \
+__BUILD_MEMORY_PFX(, bwlq, type, 0)
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_MEM(q, u64)
+#else
+__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
+__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
+#endif
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,)                   \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
+
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)                                \
+        __BUILD_IOPORT_PFX(__mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
+
+#define __BUILDIO(bwlq, type)                                           \
+                                                                        \
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed                   __relaxed_readb
+#define readw_relaxed                   __relaxed_readw
+#define readl_relaxed                   __relaxed_readl
+#ifdef CONFIG_64BIT
+#define readq_relaxed                   __relaxed_readq
+#endif
+
+#define writeb_relaxed                  __relaxed_writeb
+#define writew_relaxed                  __relaxed_writew
+#define writel_relaxed                  __relaxed_writel
+#ifdef CONFIG_64BIT
+#define writeq_relaxed                  __relaxed_writeq
+#endif
+
+#define readb_be(addr)                                                  \
+        __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr)                                                  \
+        be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr)                                                  \
+        be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr)                                                  \
+        be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr)                                            \
+        __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr)                                            \
+        __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr)                                            \
+        __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr)                                            \
+        __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+
+/*
+ * Some code tests for these symbols
+ */
+#ifdef CONFIG_64BIT
+#define readq                           readq
+#define writeq                          writeq
+#endif
+
+#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+                                                                        \
+static inline void writes##bwlq(volatile void __iomem *mem,             \
+                                const void *addr, unsigned int count)   \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __mem_write##bwlq(*__addr, mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
+                               unsigned int count)                      \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __mem_read##bwlq(mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define __BUILD_IOPORT_STRING(bwlq, type)                               \
+                                                                        \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
+                              unsigned int count)                       \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __mem_out##bwlq(*__addr, port);                         \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void ins##bwlq(unsigned long port, void *addr,            \
+                             unsigned int count)                        \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __mem_in##bwlq(port);                         \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define BUILDSTRING(bwlq, type)                                         \
+                                                                        \
+__BUILD_MEMORY_STRING(bwlq, type)                                       \
+__BUILD_IOPORT_STRING(bwlq, type)
+
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
+
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+        memset((void __force *) addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+        memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+        memcpy((void __force *) dst, src, count);
+}
+
+/*
+ * The caches on some architectures aren't dma-coherent and have need to
+ * handle this in software.  There are three types of operations that
+ * can be applied to dma buffers.
+ *
+ *  - dma_cache_wback_inv(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_wback(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_inv(start, size) invalidates the affected parts of the
+ *    caches.  Dirty lines of the caches may be written back or simply
+ *    be discarded.  This operation is necessary before dma operations
+ *    to the memory.
+ *
+ * This API used to be exported; it now is for arch code internal use only.
+ */
+#ifdef CONFIG_DMA_NONCOHERENT
+
+extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+#define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
+#define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
+#define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
+
+#else /* Sane hardware */
+
+#define dma_cache_wback_inv(start,size) \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size)     \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size)       \
+        do { (void) (start); (void) (size); } while (0)
+
+#endif /* CONFIG_DMA_NONCOHERENT */
+
+/*
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
+ */
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+void __ioread64_copy(void *to, const void __iomem *from, size_t count);
+
+#endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h
new file mode 100644
index 000000000..16c94a27b
--- /dev/null
+++ b/arch/mips/include/asm/ip32/crime.h
@@ -0,0 +1,158 @@
+/*
+ * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
+ * Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_CRIME_H__
+#define __ASM_CRIME_H__
+
+/*
+ * Address map
+ */
+#define CRIME_BASE      0x14000000      /* physical */
+
+struct sgi_crime {
+        volatile unsigned long id;
+#define CRIME_ID_MASK                   0xff
+#define CRIME_ID_IDBITS                 0xf0
+#define CRIME_ID_IDVALUE                0xa0
+#define CRIME_ID_REV                    0x0f
+#define CRIME_REV_PETTY                 0x00
+#define CRIME_REV_11                    0x11
+#define CRIME_REV_13                    0x13
+#define CRIME_REV_14                    0x14
+
+        volatile unsigned long control;
+#define CRIME_CONTROL_MASK              0x3fff
+#define CRIME_CONTROL_TRITON_SYSADC     0x2000
+#define CRIME_CONTROL_CRIME_SYSADC      0x1000
+#define CRIME_CONTROL_HARD_RESET        0x0800
+#define CRIME_CONTROL_SOFT_RESET        0x0400
+#define CRIME_CONTROL_DOG_ENA           0x0200
+#define CRIME_CONTROL_ENDIANESS         0x0100
+#define CRIME_CONTROL_ENDIAN_BIG        0x0100
+#define CRIME_CONTROL_ENDIAN_LITTLE     0x0000
+#define CRIME_CONTROL_CQUEUE_HWM        0x000f
+#define CRIME_CONTROL_CQUEUE_SHFT       0
+#define CRIME_CONTROL_WBUF_HWM          0x00f0
+#define CRIME_CONTROL_WBUF_SHFT         8
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+        volatile unsigned long soft_int;
+        volatile unsigned long hard_int;
+#define MACE_VID_IN1_INT                BIT(0)
+#define MACE_VID_IN2_INT                BIT(1)
+#define MACE_VID_OUT_INT                BIT(2)
+#define MACE_ETHERNET_INT               BIT(3)
+#define MACE_SUPERIO_INT                BIT(4)
+#define MACE_MISC_INT                   BIT(5)
+#define MACE_AUDIO_INT                  BIT(6)
+#define MACE_PCI_BRIDGE_INT             BIT(7)
+#define MACEPCI_SCSI0_INT               BIT(8)
+#define MACEPCI_SCSI1_INT               BIT(9)
+#define MACEPCI_SLOT0_INT               BIT(10)
+#define MACEPCI_SLOT1_INT               BIT(11)
+#define MACEPCI_SLOT2_INT               BIT(12)
+#define MACEPCI_SHARED0_INT             BIT(13)
+#define MACEPCI_SHARED1_INT             BIT(14)
+#define MACEPCI_SHARED2_INT             BIT(15)
+#define CRIME_GBE0_INT                  BIT(16)
+#define CRIME_GBE1_INT                  BIT(17)
+#define CRIME_GBE2_INT                  BIT(18)
+#define CRIME_GBE3_INT                  BIT(19)
+#define CRIME_CPUERR_INT                BIT(20)
+#define CRIME_MEMERR_INT                BIT(21)
+#define CRIME_RE_EMPTY_E_INT            BIT(22)
+#define CRIME_RE_FULL_E_INT             BIT(23)
+#define CRIME_RE_IDLE_E_INT             BIT(24)
+#define CRIME_RE_EMPTY_L_INT            BIT(25)
+#define CRIME_RE_FULL_L_INT             BIT(26)
+#define CRIME_RE_IDLE_L_INT             BIT(27)
+#define CRIME_SOFT0_INT                 BIT(28)
+#define CRIME_SOFT1_INT                 BIT(29)
+#define CRIME_SOFT2_INT                 BIT(30)
+#define CRIME_SYSCORERR_INT             CRIME_SOFT2_INT
+#define CRIME_VICE_INT                  BIT(31)
+/* Masks for deciding who handles the interrupt */
+#define CRIME_MACE_INT_MASK             0x8f
+#define CRIME_MACEISA_INT_MASK          0x70
+#define CRIME_MACEPCI_INT_MASK          0xff00
+#define CRIME_CRIME_INT_MASK            0xffff0000
+
+        volatile unsigned long watchdog;
+#define CRIME_DOG_POWER_ON_RESET        0x00010000
+#define CRIME_DOG_WARM_RESET            0x00080000
+#define CRIME_DOG_TIMEOUT               (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
+#define CRIME_DOG_VALUE                 0x00007fff
+
+        volatile unsigned long timer;
+#define CRIME_MASTER_FREQ               66666500        /* Crime upcounter frequency */
+#define CRIME_NS_PER_TICK               15              /* for delay_calibrate */
+
+        volatile unsigned long cpu_error_addr;
+#define CRIME_CPU_ERROR_ADDR_MASK       0x3ffffffff
+
+        volatile unsigned long cpu_error_stat;
+#define CRIME_CPU_ERROR_MASK            0x7             /* cpu error stat is 3 bits */
+#define CRIME_CPU_ERROR_CPU_ILL_ADDR    0x4
+#define CRIME_CPU_ERROR_VICE_WRT_PRTY   0x2
+#define CRIME_CPU_ERROR_CPU_WRT_PRTY    0x1
+
+        unsigned long _pad0[54];
+
+        volatile unsigned long mc_ctrl;
+        volatile unsigned long bank_ctrl[8];
+#define CRIME_MEM_BANK_CONTROL_MASK             0x11f   /* 9 bits 7:5 reserved */
+#define CRIME_MEM_BANK_CONTROL_ADDR             0x01f
+#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE       0x100
+#define CRIME_MAXBANKS                          8
+
+        volatile unsigned long mem_ref_counter;
+#define CRIME_MEM_REF_COUNTER_MASK      0x3ff           /* 10bit */
+
+        volatile unsigned long mem_error_stat;
+#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff      /* 28-bit register */
+#define CRIME_MEM_ERROR_MACE_ID         0x0000007f
+#define CRIME_MEM_ERROR_MACE_ACCESS     0x00000080
+#define CRIME_MEM_ERROR_RE_ID           0x00007f00
+#define CRIME_MEM_ERROR_RE_ACCESS       0x00008000
+#define CRIME_MEM_ERROR_GBE_ACCESS      0x00010000
+#define CRIME_MEM_ERROR_VICE_ACCESS     0x00020000
+#define CRIME_MEM_ERROR_CPU_ACCESS      0x00040000
+#define CRIME_MEM_ERROR_RESERVED        0x00080000
+#define CRIME_MEM_ERROR_SOFT_ERR        0x00100000
+#define CRIME_MEM_ERROR_HARD_ERR        0x00200000
+#define CRIME_MEM_ERROR_MULTIPLE        0x00400000
+#define CRIME_MEM_ERROR_ECC             0x01800000
+#define CRIME_MEM_ERROR_MEM_ECC_RD      0x00800000
+#define CRIME_MEM_ERROR_MEM_ECC_RMW     0x01000000
+#define CRIME_MEM_ERROR_INV             0x0e000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
+
+        volatile unsigned long mem_error_addr;
+#define CRIME_MEM_ERROR_ADDR_MASK       0x3fffffff
+
+        volatile unsigned long mem_ecc_syn;
+#define CRIME_MEM_ERROR_ECC_SYN_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_chk;
+#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_repl;
+#define CRIME_MEM_ERROR_ECC_REPL_MASK   0xffffffff
+};
+
+extern struct sgi_crime __iomem *crime;
+
+#define CRIME_HI_MEM_BASE       0x40000000      /* this is where whole 1G of RAM is mapped */
+
+#endif /* __ASM_CRIME_H__ */
diff --git a/arch/mips/include/asm/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h
new file mode 100644
index 000000000..72e3368de
--- /dev/null
+++ b/arch/mips/include/asm/ip32/ip32_ints.h
@@ -0,0 +1,114 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_IP32_INTS_H
+#define __ASM_IP32_INTS_H
+
+#include <asm/irq.h>
+
+/*
+ * This list reflects the assignment of interrupt numbers to
+ * interrupting events.  Order is fairly irrelevant to handling
+ * priority.  This differs from irix.
+ */
+
+enum ip32_irq_no {
+        /*
+         * CPU interrupts are 0 ... 7
+         */
+
+        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE + 8,
+
+        /*
+         * MACE
+         */
+        MACE_VID_IN1_IRQ                = CRIME_IRQ_BASE,
+        MACE_VID_IN2_IRQ,
+        MACE_VID_OUT_IRQ,
+        MACE_ETHERNET_IRQ,
+        /* SUPERIO, MISC, and AUDIO are MACEISA */
+        __MACE_SUPERIO,
+        __MACE_MISC,
+        __MACE_AUDIO,
+        MACE_PCI_BRIDGE_IRQ,
+
+        /*
+         * MACEPCI
+         */
+        MACEPCI_SCSI0_IRQ,
+        MACEPCI_SCSI1_IRQ,
+        MACEPCI_SLOT0_IRQ,
+        MACEPCI_SLOT1_IRQ,
+        MACEPCI_SLOT2_IRQ,
+        MACEPCI_SHARED0_IRQ,
+        MACEPCI_SHARED1_IRQ,
+        MACEPCI_SHARED2_IRQ,
+
+        /*
+         * CRIME
+         */
+        CRIME_GBE0_IRQ,
+        CRIME_GBE1_IRQ,
+        CRIME_GBE2_IRQ,
+        CRIME_GBE3_IRQ,
+        CRIME_CPUERR_IRQ,
+        CRIME_MEMERR_IRQ,
+        CRIME_RE_EMPTY_E_IRQ,
+        CRIME_RE_FULL_E_IRQ,
+        CRIME_RE_IDLE_E_IRQ,
+        CRIME_RE_EMPTY_L_IRQ,
+        CRIME_RE_FULL_L_IRQ,
+        CRIME_RE_IDLE_L_IRQ,
+        CRIME_SOFT0_IRQ,
+        CRIME_SOFT1_IRQ,
+        CRIME_SOFT2_IRQ,
+        CRIME_SYSCORERR_IRQ             = CRIME_SOFT2_IRQ,
+        CRIME_VICE_IRQ,
+
+        /*
+         * MACEISA
+         */
+        MACEISA_AUDIO_SW_IRQ,
+        MACEISA_AUDIO_SC_IRQ,
+        MACEISA_AUDIO1_DMAT_IRQ,
+        MACEISA_AUDIO1_OF_IRQ,
+        MACEISA_AUDIO2_DMAT_IRQ,
+        MACEISA_AUDIO2_MERR_IRQ,
+        MACEISA_AUDIO3_DMAT_IRQ,
+        MACEISA_AUDIO3_MERR_IRQ,
+        MACEISA_RTC_IRQ,
+        MACEISA_KEYB_IRQ,
+        /* MACEISA_KEYB_POLL is not an IRQ */
+        __MACEISA_KEYB_POLL,
+        MACEISA_MOUSE_IRQ,
+        /* MACEISA_MOUSE_POLL is not an IRQ */
+        __MACEISA_MOUSE_POLL,
+        MACEISA_TIMER0_IRQ,
+        MACEISA_TIMER1_IRQ,
+        MACEISA_TIMER2_IRQ,
+        MACEISA_PARALLEL_IRQ,
+        MACEISA_PAR_CTXA_IRQ,
+        MACEISA_PAR_CTXB_IRQ,
+        MACEISA_PAR_MERR_IRQ,
+        MACEISA_SERIAL1_IRQ,
+        MACEISA_SERIAL1_TDMAT_IRQ,
+        MACEISA_SERIAL1_TDMAPR_IRQ,
+        MACEISA_SERIAL1_TDMAME_IRQ,
+        MACEISA_SERIAL1_RDMAT_IRQ,
+        MACEISA_SERIAL1_RDMAOR_IRQ,
+        MACEISA_SERIAL2_IRQ,
+        MACEISA_SERIAL2_TDMAT_IRQ,
+        MACEISA_SERIAL2_TDMAPR_IRQ,
+        MACEISA_SERIAL2_TDMAME_IRQ,
+        MACEISA_SERIAL2_RDMAT_IRQ,
+        MACEISA_SERIAL2_RDMAOR_IRQ,
+
+        IP32_IRQ_MAX                    = MACEISA_SERIAL2_RDMAOR_IRQ
+};
+
+#endif /* __ASM_IP32_INTS_H */
diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h
new file mode 100644
index 000000000..253ed7ea8
--- /dev/null
+++ b/arch/mips/include/asm/ip32/mace.h
@@ -0,0 +1,365 @@
+/*
+ * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ * Copyright (C) 2004 Ladislav Michl
+ */
+
+#ifndef __ASM_MACE_H__
+#define __ASM_MACE_H__
+
+/*
+ * Address map
+ */
+#define MACE_BASE       0x1f000000      /* physical */
+
+/*
+ * PCI interface
+ */
+struct mace_pci {
+        volatile unsigned int error_addr;
+        volatile unsigned int error;
+#define MACEPCI_ERROR_MASTER_ABORT              BIT(31)
+#define MACEPCI_ERROR_TARGET_ABORT              BIT(30)
+#define MACEPCI_ERROR_DATA_PARITY_ERR           BIT(29)
+#define MACEPCI_ERROR_RETRY_ERR                 BIT(28)
+#define MACEPCI_ERROR_ILLEGAL_CMD               BIT(27)
+#define MACEPCI_ERROR_SYSTEM_ERR                BIT(26)
+#define MACEPCI_ERROR_INTERRUPT_TEST            BIT(25)
+#define MACEPCI_ERROR_PARITY_ERR                BIT(24)
+#define MACEPCI_ERROR_OVERRUN                   BIT(23)
+#define MACEPCI_ERROR_RSVD                      BIT(22)
+#define MACEPCI_ERROR_MEMORY_ADDR               BIT(21)
+#define MACEPCI_ERROR_CONFIG_ADDR               BIT(20)
+#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
+#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
+#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
+#define MACEPCI_ERROR_RETRY_ADDR_VALID          BIT(16)
+#define MACEPCI_ERROR_SIG_TABORT                BIT(4)
+#define MACEPCI_ERROR_DEVSEL_MASK               0xc0
+#define MACEPCI_ERROR_DEVSEL_FAST               0
+#define MACEPCI_ERROR_DEVSEL_MED                0x40
+#define MACEPCI_ERROR_DEVSEL_SLOW               0x80
+#define MACEPCI_ERROR_FBB                       BIT(1)
+#define MACEPCI_ERROR_66MHZ                     BIT(0)
+        volatile unsigned int control;
+#define MACEPCI_CONTROL_INT(x)                  BIT(x)
+#define MACEPCI_CONTROL_INT_MASK                0xff
+#define MACEPCI_CONTROL_SERR_ENA                BIT(8)
+#define MACEPCI_CONTROL_ARB_N6                  BIT(9)
+#define MACEPCI_CONTROL_PARITY_ERR              BIT(10)
+#define MACEPCI_CONTROL_MRMRA_ENA               BIT(11)
+#define MACEPCI_CONTROL_ARB_N3                  BIT(12)
+#define MACEPCI_CONTROL_ARB_N4                  BIT(13)
+#define MACEPCI_CONTROL_ARB_N5                  BIT(14)
+#define MACEPCI_CONTROL_PARK_LIU                BIT(15)
+#define MACEPCI_CONTROL_INV_INT(x)              BIT(16+x)
+#define MACEPCI_CONTROL_INV_INT_MASK            0x00ff0000
+#define MACEPCI_CONTROL_OVERRUN_INT             BIT(24)
+#define MACEPCI_CONTROL_PARITY_INT              BIT(25)
+#define MACEPCI_CONTROL_SERR_INT                BIT(26)
+#define MACEPCI_CONTROL_IT_INT                  BIT(27)
+#define MACEPCI_CONTROL_RE_INT                  BIT(28)
+#define MACEPCI_CONTROL_DPED_INT                BIT(29)
+#define MACEPCI_CONTROL_TAR_INT                 BIT(30)
+#define MACEPCI_CONTROL_MAR_INT                 BIT(31)
+        volatile unsigned int rev;
+        unsigned int _pad[0xcf8/4 - 4];
+        volatile unsigned int config_addr;
+        union {
+                volatile unsigned char b[4];
+                volatile unsigned short w[2];
+                volatile unsigned int l;
+        } config_data;
+};
+#define MACEPCI_LOW_MEMORY              0x1a000000
+#define MACEPCI_LOW_IO                  0x18000000
+#define MACEPCI_SWAPPED_VIEW            0
+#define MACEPCI_NATIVE_VIEW             0x40000000
+#define MACEPCI_IO                      0x80000000
+#define MACEPCI_HI_MEMORY               0x280000000
+#define MACEPCI_HI_IO                   0x100000000
+
+/*
+ * Video interface
+ */
+struct mace_video {
+        unsigned long xxx;      /* later... */
+};
+
+/*
+ * Ethernet interface
+ */
+struct mace_ethernet {
+        volatile u64 mac_ctrl;
+        volatile unsigned long int_stat;
+        volatile unsigned long dma_ctrl;
+        volatile unsigned long timer;
+        volatile unsigned long tx_int_al;
+        volatile unsigned long rx_int_al;
+        volatile unsigned long tx_info;
+        volatile unsigned long tx_info_al;
+        volatile unsigned long rx_buff;
+        volatile unsigned long rx_buff_al1;
+        volatile unsigned long rx_buff_al2;
+        volatile unsigned long diag;
+        volatile unsigned long phy_data;
+        volatile unsigned long phy_regs;
+        volatile unsigned long phy_trans_go;
+        volatile unsigned long backoff_seed;
+        /*===================================*/
+        volatile unsigned long imq_reserved[4];
+        volatile unsigned long mac_addr;
+        volatile unsigned long mac_addr2;
+        volatile unsigned long mcast_filter;
+        volatile unsigned long tx_ring_base;
+        /* Following are read-only registers for debugging */
+        volatile unsigned long tx_pkt1_hdr;
+        volatile unsigned long tx_pkt1_ptr[3];
+        volatile unsigned long tx_pkt2_hdr;
+        volatile unsigned long tx_pkt2_ptr[3];
+        /*===================================*/
+        volatile unsigned long rx_fifo;
+};
+
+/*
+ * Peripherals
+ */
+
+/* Audio registers */
+struct mace_audio {
+        volatile unsigned long control;
+        volatile unsigned long codec_control;           /* codec status control */
+        volatile unsigned long codec_mask;              /* codec status input mask */
+        volatile unsigned long codec_read;              /* codec status read data */
+        struct {
+                volatile unsigned long control;         /* channel control */
+                volatile unsigned long read_ptr;        /* channel read pointer */
+                volatile unsigned long write_ptr;       /* channel write pointer */
+                volatile unsigned long depth;           /* channel depth */
+        } chan[3];
+};
+
+
+/* register definitions for parallel port DMA */
+struct mace_parport {
+        /* 0 - do nothing,
+         * 1 - pulse terminal count to the device after buffer is drained */
+#define MACEPAR_CONTEXT_LASTFLAG        BIT(63)
+        /* Should not cross 4K page boundary */
+#define MACEPAR_CONTEXT_DATA_BOUND      0x0000000000001000UL
+#define MACEPAR_CONTEXT_DATALEN_MASK    0x00000fff00000000UL
+#define MACEPAR_CONTEXT_DATALEN_SHIFT   32
+        /* Can be arbitrarily aligned on any byte boundary on output,
+         * 64 byte aligned on input */
+#define MACEPAR_CONTEXT_BASEADDR_MASK   0x00000000ffffffffUL
+        volatile u64 context_a;
+        volatile u64 context_b;
+        /* 0 - mem->device, 1 - device->mem */
+#define MACEPAR_CTLSTAT_DIRECTION       BIT(0)
+        /* 0 - channel frozen, 1 - channel enabled */
+#define MACEPAR_CTLSTAT_ENABLE          BIT(1)
+        /* 0 - channel active, 1 - complete channel reset */
+#define MACEPAR_CTLSTAT_RESET           BIT(2)
+#define MACEPAR_CTLSTAT_CTXB_VALID      BIT(3)
+#define MACEPAR_CTLSTAT_CTXA_VALID      BIT(4)
+        volatile u64 cntlstat;          /* Control/Status register */
+#define MACEPAR_DIAG_CTXINUSE           BIT(0)
+        /* 1 - Dma engine is enabled and processing something */
+#define MACEPAR_DIAG_DMACTIVE           BIT(1)
+        /* Counter of bytes left */
+#define MACEPAR_DIAG_CTRMASK            0x0000000000003ffcUL
+#define MACEPAR_DIAG_CTRSHIFT           2
+        volatile u64 diagnostic;        /* RO: diagnostic register */
+};
+
+/* ISA Control and DMA registers */
+struct mace_isactrl {
+        volatile unsigned long ringbase;
+#define MACEISA_RINGBUFFERS_SIZE        (8 * 4096)
+
+        volatile unsigned long misc;
+#define MACEISA_FLASH_WE                BIT(0)  /* 1=> Enable FLASH writes */
+#define MACEISA_PWD_CLEAR               BIT(1)  /* 1=> PWD CLEAR jumper detected */
+#define MACEISA_NIC_DEASSERT            BIT(2)
+#define MACEISA_NIC_DATA                BIT(3)
+#define MACEISA_LED_RED                 BIT(4)  /* 0=> Illuminate red LED */
+#define MACEISA_LED_GREEN               BIT(5)  /* 0=> Illuminate green LED */
+#define MACEISA_DP_RAM_ENABLE           BIT(6)
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+#define MACEISA_AUDIO_SW_INT            BIT(0)
+#define MACEISA_AUDIO_SC_INT            BIT(1)
+#define MACEISA_AUDIO1_DMAT_INT         BIT(2)
+#define MACEISA_AUDIO1_OF_INT           BIT(3)
+#define MACEISA_AUDIO2_DMAT_INT         BIT(4)
+#define MACEISA_AUDIO2_MERR_INT         BIT(5)
+#define MACEISA_AUDIO3_DMAT_INT         BIT(6)
+#define MACEISA_AUDIO3_MERR_INT         BIT(7)
+#define MACEISA_RTC_INT                 BIT(8)
+#define MACEISA_KEYB_INT                BIT(9)
+#define MACEISA_KEYB_POLL_INT           BIT(10)
+#define MACEISA_MOUSE_INT               BIT(11)
+#define MACEISA_MOUSE_POLL_INT          BIT(12)
+#define MACEISA_TIMER0_INT              BIT(13)
+#define MACEISA_TIMER1_INT              BIT(14)
+#define MACEISA_TIMER2_INT              BIT(15)
+#define MACEISA_PARALLEL_INT            BIT(16)
+#define MACEISA_PAR_CTXA_INT            BIT(17)
+#define MACEISA_PAR_CTXB_INT            BIT(18)
+#define MACEISA_PAR_MERR_INT            BIT(19)
+#define MACEISA_SERIAL1_INT             BIT(20)
+#define MACEISA_SERIAL1_TDMAT_INT       BIT(21)
+#define MACEISA_SERIAL1_TDMAPR_INT      BIT(22)
+#define MACEISA_SERIAL1_TDMAME_INT      BIT(23)
+#define MACEISA_SERIAL1_RDMAT_INT       BIT(24)
+#define MACEISA_SERIAL1_RDMAOR_INT      BIT(25)
+#define MACEISA_SERIAL2_INT             BIT(26)
+#define MACEISA_SERIAL2_TDMAT_INT       BIT(27)
+#define MACEISA_SERIAL2_TDMAPR_INT      BIT(28)
+#define MACEISA_SERIAL2_TDMAME_INT      BIT(29)
+#define MACEISA_SERIAL2_RDMAT_INT       BIT(30)
+#define MACEISA_SERIAL2_RDMAOR_INT      BIT(31)
+
+        volatile unsigned long _pad[0x2000/8 - 4];
+
+        volatile unsigned long dp_ram[0x400];
+        struct mace_parport parport;
+};
+
+/* Keyboard & Mouse registers
+ * -> drivers/input/serio/maceps2.c */
+struct mace_ps2port {
+        volatile unsigned long tx;
+        volatile unsigned long rx;
+        volatile unsigned long control;
+        volatile unsigned long status;
+};
+
+struct mace_ps2 {
+        struct mace_ps2port keyb;
+        struct mace_ps2port mouse;
+};
+
+/* I2C registers
+ * -> drivers/i2c/algos/i2c-algo-sgi.c */
+struct mace_i2c {
+        volatile unsigned long config;
+#define MACEI2C_RESET           BIT(0)
+#define MACEI2C_FAST            BIT(1)
+#define MACEI2C_DATA_OVERRIDE   BIT(2)
+#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
+#define MACEI2C_DATA_STATUS     BIT(4)
+#define MACEI2C_CLOCK_STATUS    BIT(5)
+        volatile unsigned long control;
+        volatile unsigned long data;
+};
+
+/* Timer registers */
+typedef union {
+        volatile unsigned long ust_msc;
+        struct reg {
+                volatile unsigned int ust;
+                volatile unsigned int msc;
+        } reg;
+} timer_reg;
+
+struct mace_timers {
+        volatile unsigned long ust;
+#define MACE_UST_PERIOD_NS      960
+
+        volatile unsigned long compare1;
+        volatile unsigned long compare2;
+        volatile unsigned long compare3;
+
+        timer_reg audio_in;
+        timer_reg audio_out1;
+        timer_reg audio_out2;
+        timer_reg video_in1;
+        timer_reg video_in2;
+        timer_reg video_out;
+};
+
+struct mace_perif {
+        struct mace_audio audio;
+        char _pad0[0x10000 - sizeof(struct mace_audio)];
+
+        struct mace_isactrl ctrl;
+        char _pad1[0x10000 - sizeof(struct mace_isactrl)];
+
+        struct mace_ps2 ps2;
+        char _pad2[0x10000 - sizeof(struct mace_ps2)];
+
+        struct mace_i2c i2c;
+        char _pad3[0x10000 - sizeof(struct mace_i2c)];
+
+        struct mace_timers timers;
+        char _pad4[0x10000 - sizeof(struct mace_timers)];
+};
+
+
+/*
+ * ISA peripherals
+ */
+
+/* Parallel port */
+struct mace_parallel {
+};
+
+struct mace_ecp1284 {   /* later... */
+};
+
+/* Serial port */
+struct mace_serial {
+        volatile unsigned long xxx;     /* later... */
+};
+
+struct mace_isa {
+        struct mace_parallel parallel;
+        char _pad1[0x8000 - sizeof(struct mace_parallel)];
+
+        struct mace_ecp1284 ecp1284;
+        char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
+
+        struct mace_serial serial1;
+        char _pad3[0x8000 - sizeof(struct mace_serial)];
+
+        struct mace_serial serial2;
+        char _pad4[0x8000 - sizeof(struct mace_serial)];
+
+        volatile unsigned char rtc[0x10000];
+};
+
+struct sgi_mace {
+        char _reserved[0x80000];
+
+        struct mace_pci pci;
+        char _pad0[0x80000 - sizeof(struct mace_pci)];
+
+        struct mace_video video_in1;
+        char _pad1[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_in2;
+        char _pad2[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_out;
+        char _pad3[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_ethernet eth;
+        char _pad4[0x80000 - sizeof(struct mace_ethernet)];
+
+        struct mace_perif perif;
+        char _pad5[0x80000 - sizeof(struct mace_perif)];
+
+        struct mace_isa isa;
+        char _pad6[0x80000 - sizeof(struct mace_isa)];
+};
+
+extern struct sgi_mace __iomem *mace;
+
+#endif /* __ASM_MACE_H__ */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
new file mode 100644
index 000000000..c5d351786
--- /dev/null
+++ b/arch/mips/include/asm/irq.h
@@ -0,0 +1,85 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ */
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#include <linux/linkage.h>
+#include <linux/smp.h>
+#include <linux/irqdomain.h>
+
+#include <asm/mipsmtregs.h>
+
+#include <irq.h>
+
+#define IRQ_STACK_SIZE                  THREAD_SIZE
+#define IRQ_STACK_START                 (IRQ_STACK_SIZE - 16)
+
+extern void *irq_stack[NR_CPUS];
+
+/*
+ * The highest address on the IRQ stack contains a dummy frame put down in
+ * genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
+ *
+ *   top ------------
+ *       | task sp  | <- irq_stack[cpu] + IRQ_STACK_START
+ *       ------------
+ *       |          | <- First frame of IRQ context
+ *       ------------
+ *
+ * task sp holds a copy of the task stack pointer where the struct pt_regs
+ * from exception entry can be found.
+ */
+
+static inline bool on_irq_stack(int cpu, unsigned long sp)
+{
+        unsigned long low = (unsigned long)irq_stack[cpu];
+        unsigned long high = low + IRQ_STACK_SIZE;
+
+        return (low <= sp && sp <= high);
+}
+
+#ifdef CONFIG_I8259
+static inline int irq_canonicalize(int irq)
+{
+        return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
+}
+#else
+#define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
+#endif
+
+asmlinkage void plat_irq_dispatch(void);
+
+extern void do_IRQ(unsigned int irq);
+
+extern void arch_init_irq(void);
+extern void spurious_interrupt(void);
+
+extern int allocate_irqno(void);
+extern void alloc_legacy_irqno(void);
+extern void free_irqno(unsigned int irq);
+
+/*
+ * Before R2 the timer and performance counter interrupts were both fixed to
+ * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ */
+#define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
+
+extern int cp0_compare_irq;
+extern int cp0_compare_irq_shift;
+extern int cp0_perfcount_irq;
+extern int cp0_fdc_irq;
+
+extern int get_c0_fdc_int(void);
+
+void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
+                                    bool exclude_self);
+#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
+
+#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
new file mode 100644
index 000000000..8d321180b
--- /dev/null
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/irq_cpu.h
+ *
+ *      MIPS CPU interrupt definitions.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_IRQ_CPU_H
+#define _ASM_IRQ_CPU_H
+
+extern void mips_cpu_irq_init(void);
+extern void rm7k_cpu_irq_init(void);
+extern void rm9k_cpu_irq_init(void);
+
+#ifdef CONFIG_IRQ_DOMAIN
+struct device_node;
+extern int mips_cpu_irq_of_init(struct device_node *of_node,
+                                struct device_node *parent);
+#endif
+
+#endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/include/asm/irq_gt641xx.h b/arch/mips/include/asm/irq_gt641xx.h
new file mode 100644
index 000000000..d689c1c6c
--- /dev/null
+++ b/arch/mips/include/asm/irq_gt641xx.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Galileo/Marvell GT641xx IRQ definitions.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef _ASM_IRQ_GT641XX_H
+#define _ASM_IRQ_GT641XX_H
+
+#ifndef GT641XX_IRQ_BASE
+#define GT641XX_IRQ_BASE                8
+#endif
+
+#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ         (GT641XX_IRQ_BASE + 1)
+#define GT641XX_DMA_OUT_OF_RANGE_IRQ            (GT641XX_IRQ_BASE + 2)
+#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ     (GT641XX_IRQ_BASE + 3)
+#define GT641XX_DMA0_IRQ                        (GT641XX_IRQ_BASE + 4)
+#define GT641XX_DMA1_IRQ                        (GT641XX_IRQ_BASE + 5)
+#define GT641XX_DMA2_IRQ                        (GT641XX_IRQ_BASE + 6)
+#define GT641XX_DMA3_IRQ                        (GT641XX_IRQ_BASE + 7)
+#define GT641XX_TIMER0_IRQ                      (GT641XX_IRQ_BASE + 8)
+#define GT641XX_TIMER1_IRQ                      (GT641XX_IRQ_BASE + 9)
+#define GT641XX_TIMER2_IRQ                      (GT641XX_IRQ_BASE + 10)
+#define GT641XX_TIMER3_IRQ                      (GT641XX_IRQ_BASE + 11)
+#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ     (GT641XX_IRQ_BASE + 12)
+#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ     (GT641XX_IRQ_BASE + 13)
+#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ    (GT641XX_IRQ_BASE + 14)
+#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ      (GT641XX_IRQ_BASE + 15)
+#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ         (GT641XX_IRQ_BASE + 16)
+#define GT641XX_MEMORY_ERROR_IRQ                (GT641XX_IRQ_BASE + 17)
+#define GT641XX_PCI_0_MASTER_ABORT_IRQ          (GT641XX_IRQ_BASE + 18)
+#define GT641XX_PCI_0_TARGET_ABORT_IRQ          (GT641XX_IRQ_BASE + 19)
+#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ         (GT641XX_IRQ_BASE + 20)
+#define GT641XX_CPU_INT0_IRQ                    (GT641XX_IRQ_BASE + 21)
+#define GT641XX_CPU_INT1_IRQ                    (GT641XX_IRQ_BASE + 22)
+#define GT641XX_CPU_INT2_IRQ                    (GT641XX_IRQ_BASE + 23)
+#define GT641XX_CPU_INT3_IRQ                    (GT641XX_IRQ_BASE + 24)
+#define GT641XX_CPU_INT4_IRQ                    (GT641XX_IRQ_BASE + 25)
+#define GT641XX_PCI_INT0_IRQ                    (GT641XX_IRQ_BASE + 26)
+#define GT641XX_PCI_INT1_IRQ                    (GT641XX_IRQ_BASE + 27)
+#define GT641XX_PCI_INT2_IRQ                    (GT641XX_IRQ_BASE + 28)
+#define GT641XX_PCI_INT3_IRQ                    (GT641XX_IRQ_BASE + 29)
+
+extern void gt641xx_irq_dispatch(void);
+extern void gt641xx_irq_init(void);
+
+#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/arch/mips/include/asm/irq_regs.h b/arch/mips/include/asm/irq_regs.h
new file mode 100644
index 000000000..7795dc02c
--- /dev/null
+++ b/arch/mips/include/asm/irq_regs.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *
+ * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_IRQ_REGS_H
+#define __ASM_IRQ_REGS_H
+
+#define ARCH_HAS_OWN_IRQ_REGS
+
+#include <linux/thread_info.h>
+
+static inline struct pt_regs *get_irq_regs(void)
+{
+        return current_thread_info()->regs;
+}
+
+static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
+{
+        struct pt_regs *old_regs;
+
+        old_regs = get_irq_regs();
+        current_thread_info()->regs = new_regs;
+
+        return old_regs;
+}
+
+#endif /* __ASM_IRQ_REGS_H */
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
new file mode 100644
index 000000000..f5b8300f4
--- /dev/null
+++ b/arch/mips/include/asm/irqflags.h
@@ -0,0 +1,185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/stringify.h>
+#include <asm/compiler.h>
+#include <asm/hazards.h>
+
+#if defined(CONFIG_CPU_HAS_DIEI)
+
+static inline void arch_local_irq_disable(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noat                                            \n"
+        "       di                                                      \n"
+        "       " __stringify(__irq_disable_hazard) "                   \n"
+        "       .set    pop                                             \n"
+        : /* no outputs */
+        : /* no inputs */
+        : "memory");
+}
+
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+
+        asm __volatile__(
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#if defined(CONFIG_CPU_LOONGSON64) || defined(CONFIG_CPU_LOONGSON32)
+        "       mfc0    %[flags], $12                                   \n"
+        "       di                                                      \n"
+#else
+        "       di      %[flags]                                        \n"
+#endif
+        "       andi    %[flags], 1                                     \n"
+        "       " __stringify(__irq_disable_hazard) "                   \n"
+        "       .set    pop                                             \n"
+        : [flags] "=r" (flags)
+        : /* no inputs */
+        : "memory");
+
+        return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+        unsigned long __tmp1;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+#if defined(CONFIG_IRQ_MIPS_CPU)
+        /*
+         * Slow, but doesn't suffer from a relatively unlikely race
+         * condition we're having since days 1.
+         */
+        "       beqz    %[flags], 1f                                    \n"
+        "       di                                                      \n"
+        "       ei                                                      \n"
+        "1:                                                             \n"
+#else
+        /*
+         * Fast, dangerous.  Life is fun, life is good.
+         */
+        "       mfc0    $1, $12                                         \n"
+        "       ins     $1, %[flags], 0, 1                              \n"
+        "       mtc0    $1, $12                                         \n"
+#endif
+        "       " __stringify(__irq_disable_hazard) "                   \n"
+        "       .set    pop                                             \n"
+        : [flags] "=r" (__tmp1)
+        : "0" (flags)
+        : "memory");
+}
+
+#else
+/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
+void arch_local_irq_disable(void);
+unsigned long arch_local_irq_save(void);
+void arch_local_irq_restore(unsigned long flags);
+#endif /* CONFIG_CPU_HAS_DIEI */
+
+static inline void arch_local_irq_enable(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#if defined(CONFIG_CPU_HAS_DIEI)
+        "       ei                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1e                                         \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       " __stringify(__irq_enable_hazard) "                    \n"
+        "       .set    pop                                             \n"
+        : /* no outputs */
+        : /* no inputs */
+        : "memory");
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+        unsigned long flags;
+
+        asm __volatile__(
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       mfc0    %[flags], $12                                   \n"
+        "       .set    pop                                             \n"
+        : [flags] "=r" (flags));
+
+        return flags;
+}
+
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+        return !(flags & 1);
+}
+
+static inline int arch_irqs_disabled(void)
+{
+        return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+
+#endif /* #ifndef __ASSEMBLY__ */
+
+/*
+ * Do the CPU's IRQ-state tracing from assembly code.
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+/* Reload some registers clobbered by trace_hardirqs_on */
+#ifdef CONFIG_64BIT
+# define TRACE_IRQS_RELOAD_REGS                                         \
+        LONG_L  $11, PT_R11(sp);                                        \
+        LONG_L  $10, PT_R10(sp);                                        \
+        LONG_L  $9, PT_R9(sp);                                          \
+        LONG_L  $8, PT_R8(sp);                                          \
+        LONG_L  $7, PT_R7(sp);                                          \
+        LONG_L  $6, PT_R6(sp);                                          \
+        LONG_L  $5, PT_R5(sp);                                          \
+        LONG_L  $4, PT_R4(sp);                                          \
+        LONG_L  $2, PT_R2(sp)
+#else
+# define TRACE_IRQS_RELOAD_REGS                                         \
+        LONG_L  $7, PT_R7(sp);                                          \
+        LONG_L  $6, PT_R6(sp);                                          \
+        LONG_L  $5, PT_R5(sp);                                          \
+        LONG_L  $4, PT_R4(sp);                                          \
+        LONG_L  $2, PT_R2(sp)
+#endif
+# define TRACE_IRQS_ON                                                  \
+        CLI;    /* make sure trace_hardirqs_on() is called in kernel level */ \
+        jal     trace_hardirqs_on
+# define TRACE_IRQS_ON_RELOAD                                           \
+        TRACE_IRQS_ON;                                                  \
+        TRACE_IRQS_RELOAD_REGS
+# define TRACE_IRQS_OFF                                                 \
+        jal     trace_hardirqs_off
+#else
+# define TRACE_IRQS_ON
+# define TRACE_IRQS_ON_RELOAD
+# define TRACE_IRQS_OFF
+#endif
+
+#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/mips/include/asm/isa-rev.h b/arch/mips/include/asm/isa-rev.h
new file mode 100644
index 000000000..683ea3454
--- /dev/null
+++ b/arch/mips/include/asm/isa-rev.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MIPS Tech, LLC
+ * Author: Matt Redfearn <matt.redfearn@mips.com>
+ */
+
+#ifndef __MIPS_ASM_ISA_REV_H__
+#define __MIPS_ASM_ISA_REV_H__
+
+/*
+ * The ISA revision level. This is 0 for MIPS I to V and N for
+ * MIPS{32,64}rN.
+ */
+
+/* If the compiler has defined __mips_isa_rev, believe it. */
+#ifdef __mips_isa_rev
+#define MIPS_ISA_REV __mips_isa_rev
+#else
+/* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */
+#define MIPS_ISA_REV 0
+#endif
+
+
+#endif /* __MIPS_ASM_ISA_REV_H__ */
diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
new file mode 100644
index 000000000..d16832023
--- /dev/null
+++ b/arch/mips/include/asm/isadep.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Various ISA level dependent constants.
+ * Most of the following constants reflect the different layout
+ * of Coprocessor 0 registers.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+
+#ifndef __ASM_ISADEP_H
+#define __ASM_ISADEP_H
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+/*
+ * R2000 or R3000
+ */
+
+/*
+ * kernel or user mode? (CP0_STATUS)
+ */
+#define KU_MASK 0x08
+#define KU_USER 0x08
+#define KU_KERN 0x00
+
+#else
+/*
+ * kernel or user mode?
+ */
+#define KU_MASK 0x18
+#define KU_USER 0x10
+#define KU_KERN 0x00
+
+#endif
+
+#endif /* __ASM_ISADEP_H */
diff --git a/arch/mips/include/asm/jazz.h b/arch/mips/include/asm/jazz.h
new file mode 100644
index 000000000..a61970d01
--- /dev/null
+++ b/arch/mips/include/asm/jazz.h
@@ -0,0 +1,310 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
+ */
+#ifndef __ASM_JAZZ_H
+#define __ASM_JAZZ_H
+
+/*
+ * The addresses below are virtual address. The mappings are
+ * created on startup via wired entries in the tlb. The Mips
+ * Magnum R3000 and R4000 machines are similar in many aspects,
+ * but many hardware register are accessible at 0xb9000000 in
+ * instead of 0xe0000000.
+ */
+
+#define JAZZ_LOCAL_IO_SPACE     0xe0000000
+
+/*
+ * Revision numbers in PICA_ASIC_REVISION
+ *
+ * 0xf0000000 - Rev1
+ * 0xf0000001 - Rev2
+ * 0xf0000002 - Rev3
+ */
+#define PICA_ASIC_REVISION      0xe0000008
+
+/*
+ * The segments of the seven segment LED are mapped
+ * to the control bits as follows:
+ *
+ *         (7)
+ *      ---------
+ *      |       |
+ *  (2) |       | (6)
+ *      |  (1)  |
+ *      ---------
+ *      |       |
+ *  (3) |       | (5)
+ *      |  (4)  |
+ *      --------- . (0)
+ */
+#define PICA_LED                0xe000f000
+
+/*
+ * Some characters for the LED control registers
+ * The original Mips machines seem to have a LED display
+ * with integrated decoder while the Acer machines can
+ * control each of the seven segments and the dot independently.
+ * It's only a toy, anyway...
+ */
+#define LED_DOT                 0x01
+#define LED_SPACE               0x00
+#define LED_0                   0xfc
+#define LED_1                   0x60
+#define LED_2                   0xda
+#define LED_3                   0xf2
+#define LED_4                   0x66
+#define LED_5                   0xb6
+#define LED_6                   0xbe
+#define LED_7                   0xe0
+#define LED_8                   0xfe
+#define LED_9                   0xf6
+#define LED_A                   0xee
+#define LED_b                   0x3e
+#define LED_C                   0x9c
+#define LED_d                   0x7a
+#define LED_E                   0x9e
+#define LED_F                   0x8e
+
+#ifndef __ASSEMBLY__
+
+static __inline__ void pica_set_led(unsigned int bits)
+{
+        volatile unsigned int *led_register = (unsigned int *) PICA_LED;
+
+        *led_register = bits;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Base address of the Sonic Ethernet adapter in Jazz machines.
+ */
+#define JAZZ_ETHERNET_BASE  0xe0001000
+
+/*
+ * Base address of the 53C94 SCSI hostadapter in Jazz machines.
+ */
+#define JAZZ_SCSI_BASE          0xe0002000
+
+/*
+ * i8042 keyboard controller for JAZZ and PICA chipsets.
+ * This address is just a guess and seems to differ from
+ * other mips machines such as RC3xxx...
+ */
+#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
+#define JAZZ_KEYBOARD_DATA      0xe0005000
+#define JAZZ_KEYBOARD_COMMAND   0xe0005001
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned char data;
+        unsigned char command;
+} jazz_keyboard_hardware;
+
+#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
+
+typedef struct {
+        unsigned char pad0[3];
+        unsigned char data;
+        unsigned char pad1[3];
+        unsigned char command;
+} mips_keyboard_hardware;
+
+/*
+ * For now. Needs to be changed for RC3xxx support. See below.
+ */
+#define keyboard_hardware       jazz_keyboard_hardware
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * i8042 keyboard controller for most other Mips machines.
+ */
+#define MIPS_KEYBOARD_ADDRESS   0xb9005000
+#define MIPS_KEYBOARD_DATA      0xb9005003
+#define MIPS_KEYBOARD_COMMAND   0xb9005007
+
+/*
+ * Serial and parallel ports (WD 16C552) on the Mips JAZZ
+ */
+#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
+#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
+#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
+
+/*
+ * Dummy Device Address. Used in jazzdma.c
+ */
+#define JAZZ_DUMMY_DEVICE       0xe000d000
+
+/*
+ * JAZZ timer registers and interrupt no.
+ * Note that the hardware timer interrupt is actually on
+ * cpu level 6, but to keep compatibility with PC stuff
+ * it is remapped to vector 0. See arch/mips/kernel/entry.S.
+ */
+#define JAZZ_TIMER_INTERVAL     0xe0000228
+#define JAZZ_TIMER_REGISTER     0xe0000230
+
+/*
+ * DRAM configuration register
+ */
+#ifndef __ASSEMBLY__
+#ifdef __MIPSEL__
+typedef struct {
+        unsigned int bank2 : 3;
+        unsigned int bank1 : 3;
+        unsigned int mem_bus_width : 1;
+        unsigned int reserved2 : 1;
+        unsigned int page_mode : 1;
+        unsigned int reserved1 : 23;
+} dram_configuration;
+#else /* defined (__MIPSEB__) */
+typedef struct {
+        unsigned int reserved1 : 23;
+        unsigned int page_mode : 1;
+        unsigned int reserved2 : 1;
+        unsigned int mem_bus_width : 1;
+        unsigned int bank1 : 3;
+        unsigned int bank2 : 3;
+} dram_configuration;
+#endif
+#endif /* !__ASSEMBLY__ */
+
+#define PICA_DRAM_CONFIG        0xe00fffe0
+
+/*
+ * JAZZ interrupt control registers
+ */
+#define JAZZ_IO_IRQ_SOURCE      0xe0010000
+#define JAZZ_IO_IRQ_ENABLE      0xe0010002
+
+/*
+ * JAZZ Interrupt Level definitions
+ *
+ * This is somewhat broken.  For reasons which nobody can remember anymore
+ * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
+ */
+#define JAZZ_IRQ_START          24
+#define JAZZ_IRQ_END            (24 + 9)
+#define JAZZ_PARALLEL_IRQ       (JAZZ_IRQ_START + 0)
+#define JAZZ_FLOPPY_IRQ         (JAZZ_IRQ_START + 1)
+#define JAZZ_SOUND_IRQ          (JAZZ_IRQ_START + 2)
+#define JAZZ_VIDEO_IRQ          (JAZZ_IRQ_START + 3)
+#define JAZZ_ETHERNET_IRQ       (JAZZ_IRQ_START + 4)
+#define JAZZ_SCSI_IRQ           (JAZZ_IRQ_START + 5)
+#define JAZZ_KEYBOARD_IRQ       (JAZZ_IRQ_START + 6)
+#define JAZZ_MOUSE_IRQ          (JAZZ_IRQ_START + 7)
+#define JAZZ_SERIAL1_IRQ        (JAZZ_IRQ_START + 8)
+#define JAZZ_SERIAL2_IRQ        (JAZZ_IRQ_START + 9)
+
+#define JAZZ_TIMER_IRQ          (MIPS_CPU_IRQ_BASE+6)
+
+
+/*
+ * JAZZ DMA Channels
+ * Note: Channels 4...7 are not used with respect to the Acer PICA-61
+ * chipset which does not provide these DMA channels.
+ */
+#define JAZZ_SCSI_DMA           0              /* SCSI */
+#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
+#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
+#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
+
+/*
+ * JAZZ R4030 MCT_ADR chip (DMA controller)
+ * Note: Virtual Addresses !
+ */
+#define JAZZ_R4030_CONFIG       0xE0000000      /* R4030 config register */
+#define JAZZ_R4030_REVISION     0xE0000008      /* same as PICA_ASIC_REVISION */
+#define JAZZ_R4030_INV_ADDR     0xE0000010      /* Invalid Address register */
+
+#define JAZZ_R4030_TRSTBL_BASE  0xE0000018      /* Translation Table Base */
+#define JAZZ_R4030_TRSTBL_LIM   0xE0000020      /* Translation Table Limit */
+#define JAZZ_R4030_TRSTBL_INV   0xE0000028      /* Translation Table Invalidate */
+
+#define JAZZ_R4030_CACHE_MTNC   0xE0000030      /* Cache Maintenance */
+#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038      /* Remote Failed Address */
+#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040      /* Memory Failed Address */
+
+#define JAZZ_R4030_CACHE_PTAG   0xE0000048      /* I/O Cache Physical Tag */
+#define JAZZ_R4030_CACHE_LTAG   0xE0000050      /* I/O Cache Logical Tag */
+#define JAZZ_R4030_CACHE_BMASK  0xE0000058      /* I/O Cache Byte Mask */
+#define JAZZ_R4030_CACHE_BWIN   0xE0000060      /* I/O Cache Buffer Window */
+
+/*
+ * Remote Speed Registers.
+ *
+ *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
+ *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
+ *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
+ * 12: reserved, 13: free,     14: 7seg LED, 15: ???
+ */
+#define JAZZ_R4030_REM_SPEED    0xE0000070      /* 16 Remote Speed Registers */
+                                                /* 0xE0000070,78,80... 0xE00000E8 */
+#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8      /* Internal Interrupt Enable */
+#define JAZZ_R4030_INVAL_ADDR   0xE0000010      /* Invalid address Register */
+#define JAZZ_R4030_IRQ_SOURCE   0xE0000200      /* Interrupt Source Register */
+#define JAZZ_R4030_I386_ERROR   0xE0000208      /* i386/EISA Bus Error */
+
+/*
+ * Virtual (E)ISA controller address
+ */
+#define JAZZ_EISA_IRQ_ACK       0xE0000238      /* EISA interrupt acknowledge */
+
+/*
+ * Access the R4030 DMA and I/O Controller
+ */
+#ifndef __ASSEMBLY__
+
+static inline void r4030_delay(void)
+{
+__asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".set\treorder");
+}
+
+static inline unsigned short r4030_read_reg16(unsigned long addr)
+{
+        unsigned short ret = *((volatile unsigned short *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline unsigned int r4030_read_reg32(unsigned long addr)
+{
+        unsigned int ret = *((volatile unsigned int *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline void r4030_write_reg16(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned short *)addr) = val;
+        r4030_delay();
+}
+
+static inline void r4030_write_reg32(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned int *)addr) = val;
+        r4030_delay();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#define JAZZ_FDC_BASE   0xe0003000
+#define JAZZ_RTC_BASE   0xe0004000
+#define JAZZ_PORT_BASE  0xe2000000
+
+#define JAZZ_EISA_BASE  0xe3000000
+
+#endif /* __ASM_JAZZ_H */
diff --git a/arch/mips/include/asm/jazzdma.h b/arch/mips/include/asm/jazzdma.h
new file mode 100644
index 000000000..c831da7fa
--- /dev/null
+++ b/arch/mips/include/asm/jazzdma.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
+ */
+#ifndef _ASM_JAZZDMA_H
+#define _ASM_JAZZDMA_H
+
+/*
+ * Prototypes and macros
+ */
+extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
+extern int vdma_free(unsigned long laddr);
+extern unsigned long vdma_phys2log(unsigned long paddr);
+extern unsigned long vdma_log2phys(unsigned long laddr);
+extern void vdma_stats(void);           /* for debugging only */
+
+extern void vdma_enable(int channel);
+extern void vdma_disable(int channel);
+extern void vdma_set_mode(int channel, int mode);
+extern void vdma_set_addr(int channel, long addr);
+extern void vdma_set_count(int channel, int count);
+extern int vdma_get_residue(int channel);
+extern int vdma_get_enable(int channel);
+
+/*
+ * some definitions used by the driver functions
+ */
+#define VDMA_PAGESIZE           4096
+#define VDMA_PGTBL_ENTRIES      4096
+#define VDMA_PGTBL_SIZE         (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
+#define VDMA_PAGE_EMPTY         0xff000000
+
+/*
+ * Macros to get page no. and offset of a given address
+ * Note that VDMA_PAGE() works for physical addresses only
+ */
+#define VDMA_PAGE(a)            ((unsigned int)(a) >> 12)
+#define VDMA_OFFSET(a)          ((unsigned int)(a) & (VDMA_PAGESIZE-1))
+
+/*
+ * VDMA pagetable entry description
+ */
+typedef volatile struct VDMA_PGTBL_ENTRY {
+        unsigned int frame;             /* physical frame no. */
+        unsigned int owner;             /* owner of this entry (0=free) */
+} VDMA_PGTBL_ENTRY;
+
+
+/*
+ * DMA channel control registers
+ * in the R4030 MCT_ADR chip
+ */
+#define JAZZ_R4030_CHNL_MODE    0xE0000100      /* 8 DMA Channel Mode Registers, */
+                                                /* 0xE0000100,120,140... */
+#define JAZZ_R4030_CHNL_ENABLE  0xE0000108      /* 8 DMA Channel Enable Regs, */
+                                                /* 0xE0000108,128,148... */
+#define JAZZ_R4030_CHNL_COUNT   0xE0000110      /* 8 DMA Channel Byte Cnt Regs, */
+                                                /* 0xE0000110,130,150... */
+#define JAZZ_R4030_CHNL_ADDR    0xE0000118      /* 8 DMA Channel Address Regs, */
+                                                /* 0xE0000118,138,158... */
+
+/* channel enable register bits */
+
+#define R4030_CHNL_ENABLE        (1<<0)
+#define R4030_CHNL_WRITE         (1<<1)
+#define R4030_TC_INTR            (1<<8)
+#define R4030_MEM_INTR           (1<<9)
+#define R4030_ADDR_INTR          (1<<10)
+
+/*
+ * Channel mode register bits
+ */
+#define R4030_MODE_ATIME_40      (0) /* device access time on remote bus */
+#define R4030_MODE_ATIME_80      (1)
+#define R4030_MODE_ATIME_120     (2)
+#define R4030_MODE_ATIME_160     (3)
+#define R4030_MODE_ATIME_200     (4)
+#define R4030_MODE_ATIME_240     (5)
+#define R4030_MODE_ATIME_280     (6)
+#define R4030_MODE_ATIME_320     (7)
+#define R4030_MODE_WIDTH_8       (1<<3) /* device data bus width */
+#define R4030_MODE_WIDTH_16      (2<<3)
+#define R4030_MODE_WIDTH_32      (3<<3)
+#define R4030_MODE_INTR_EN       (1<<5)
+#define R4030_MODE_BURST         (1<<6) /* Rev. 2 only */
+#define R4030_MODE_FAST_ACK      (1<<7) /* Rev. 2 only */
+
+#endif /* _ASM_JAZZDMA_H */
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
new file mode 100644
index 000000000..3185fd322
--- /dev/null
+++ b/arch/mips/include/asm/jump_label.h
@@ -0,0 +1,75 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2010 Cavium Networks, Inc.
+ */
+#ifndef _ASM_MIPS_JUMP_LABEL_H
+#define _ASM_MIPS_JUMP_LABEL_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/isa-rev.h>
+
+#define JUMP_LABEL_NOP_SIZE 4
+
+#ifdef CONFIG_64BIT
+#define WORD_INSN ".dword"
+#else
+#define WORD_INSN ".word"
+#endif
+
+#ifdef CONFIG_CPU_MICROMIPS
+# define B_INSN "b32"
+# define J_INSN "j32"
+#elif MIPS_ISA_REV >= 6
+# define B_INSN "bc"
+# define J_INSN "bc"
+#else
+# define B_INSN "b"
+# define J_INSN "j"
+#endif
+
+static __always_inline bool arch_static_branch(struct static_key *key, bool branch)
+{
+        asm_volatile_goto("1:\t" B_INSN " 2f\n\t"
+                "2:\t.insn\n\t"
+                ".pushsection __jump_table,  \"aw\"\n\t"
+                WORD_INSN " 1b, %l[l_yes], %0\n\t"
+                ".popsection\n\t"
+                : :  "i" (&((char *)key)[branch]) : : l_yes);
+
+        return false;
+l_yes:
+        return true;
+}
+
+static __always_inline bool arch_static_branch_jump(struct static_key *key, bool branch)
+{
+        asm_volatile_goto("1:\t" J_INSN " %l[l_yes]\n\t"
+                ".pushsection __jump_table,  \"aw\"\n\t"
+                WORD_INSN " 1b, %l[l_yes], %0\n\t"
+                ".popsection\n\t"
+                : :  "i" (&((char *)key)[branch]) : : l_yes);
+
+        return false;
+l_yes:
+        return true;
+}
+
+#ifdef CONFIG_64BIT
+typedef u64 jump_label_t;
+#else
+typedef u32 jump_label_t;
+#endif
+
+struct jump_entry {
+        jump_label_t code;
+        jump_label_t target;
+        jump_label_t key;
+};
+
+#endif  /* __ASSEMBLY__ */
+#endif /* _ASM_MIPS_JUMP_LABEL_H */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
new file mode 100644
index 000000000..a55a207cf
--- /dev/null
+++ b/arch/mips/include/asm/kdebug.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MIPS_KDEBUG_H
+#define _ASM_MIPS_KDEBUG_H
+
+#include <linux/notifier.h>
+
+enum die_val {
+        DIE_OOPS = 1,
+        DIE_FP,
+        DIE_TRAP,
+        DIE_RI,
+        DIE_PAGE_FAULT,
+        DIE_BREAK,
+        DIE_SSTEPBP,
+        DIE_MSAFP,
+        DIE_UPROBE,
+        DIE_UPROBE_XOL,
+};
+
+#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
new file mode 100644
index 000000000..d6d5fa5cc
--- /dev/null
+++ b/arch/mips/include/asm/kexec.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * kexec.h for kexec
+ * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
+ */
+
+#ifndef _MIPS_KEXEC
+# define _MIPS_KEXEC
+
+#include <asm/stacktrace.h>
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+ /* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
+/* Reserve 3*4096 bytes for board-specific info */
+#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_MIPS
+#define MAX_NOTE_BYTES 1024
+
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else
+                prepare_frametrace(newregs);
+}
+
+#ifdef CONFIG_KEXEC
+struct kimage;
+extern unsigned long kexec_args[4];
+extern int (*_machine_kexec_prepare)(struct kimage *);
+extern void (*_machine_kexec_shutdown)(void);
+extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
+void default_machine_crash_shutdown(struct pt_regs *regs);
+void kexec_nonboot_cpu_jump(void);
+void kexec_reboot(void);
+#ifdef CONFIG_SMP
+extern const unsigned char kexec_smp_wait[];
+extern unsigned long secondary_kexec_args[4];
+extern atomic_t kexec_ready_to_reboot;
+extern void (*_crash_smp_send_stop)(void);
+#endif
+#endif
+
+#endif /* !_MIPS_KEXEC */
diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h
new file mode 100644
index 000000000..4f2302267
--- /dev/null
+++ b/arch/mips/include/asm/kgdb.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_KGDB_H_
+#define __ASM_KGDB_H_
+
+#ifdef __KERNEL__
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
+        (_MIPS_ISA == _MIPS_ISA_MIPS32)
+
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
+
+#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
+        (_MIPS_ISA == _MIPS_ISA_MIPS64)
+
+#ifdef CONFIG_32BIT
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
+#else /* CONFIG_CPU_32BIT */
+#define KGDB_GDB_REG_SIZE       64
+#define GDB_SIZEOF_REG          sizeof(u64)
+#endif
+#else
+#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
+#endif /* _MIPS_ISA */
+
+#define BUFMAX                  2048
+#define DBG_MAX_REG_NUM         72
+#define NUMREGBYTES             (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
+#define NUMCRITREGBYTES         (12 * sizeof(GDB_SIZEOF_REG))
+#define BREAK_INSTR_SIZE        4
+#define CACHE_FLUSH_IS_SAFE     0
+
+extern void arch_kgdb_breakpoint(void);
+extern void *saved_vectors[32];
+extern void handle_exception(struct pt_regs *regs);
+extern void breakinst(void);
+extern int kgdb_ll_trap(int cmd, const char *str,
+                        struct pt_regs *regs, long err, int trap, int sig);
+
+#endif                          /* __KERNEL__ */
+
+#endif /* __ASM_KGDB_H_ */
diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
new file mode 100644
index 000000000..16665dc24
--- /dev/null
+++ b/arch/mips/include/asm/kmap_types.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+#define  __WITH_KM_FENCE
+#endif
+
+#include <asm-generic/kmap_types.h>
+
+#undef __WITH_KM_FENCE
+
+#endif
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 000000000..68b1e5d45
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-mips/kprobes.h
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ */
+
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <asm-generic/kprobes.h>
+
+#ifdef CONFIG_KPROBES
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/inst.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct kprobe;
+struct pt_regs;
+
+typedef union mips_instruction kprobe_opcode_t;
+
+#define MAX_INSN_SIZE 2
+
+#define flush_insn_slot(p)                                              \
+do {                                                                    \
+        if (p->addr)                                                    \
+                flush_icache_range((unsigned long)p->addr,              \
+                           (unsigned long)p->addr +                     \
+                           (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)));  \
+} while (0)
+
+
+#define kretprobe_blacklist_size 0
+
+void arch_remove_kprobe(struct kprobe *p);
+int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t *insn;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long old_SR;
+        unsigned long saved_SR;
+        unsigned long saved_epc;
+};
+
+#define SKIP_DELAYSLOT 0x0001
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_old_SR;
+        unsigned long kprobe_saved_SR;
+        unsigned long kprobe_saved_epc;
+        /* Per-thread fields, used while emulating branches */
+        unsigned long flags;
+        unsigned long target_epc;
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+#endif /* CONFIG_KPROBES */
+#endif /* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
new file mode 100644
index 000000000..24f3d0f99
--- /dev/null
+++ b/arch/mips/include/asm/kvm_host.h
@@ -0,0 +1,1158 @@
+/*
+* This file is subject to the terms and conditions of the GNU General Public
+* License.  See the file "COPYING" in the main directory of this archive
+* for more details.
+*
+* Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
+* Authors: Sanjay Lal <sanjayl@kymasys.com>
+*/
+
+#ifndef __MIPS_KVM_HOST_H__
+#define __MIPS_KVM_HOST_H__
+
+#include <linux/cpumask.h>
+#include <linux/mutex.h>
+#include <linux/hrtimer.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/kvm.h>
+#include <linux/kvm_types.h>
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+
+#include <asm/inst.h>
+#include <asm/mipsregs.h>
+
+#include <kvm/iodev.h>
+
+/* MIPS KVM register ids */
+#define MIPS_CP0_32(_R, _S)                                     \
+        (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
+
+#define MIPS_CP0_64(_R, _S)                                     \
+        (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
+
+#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
+#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
+#define KVM_REG_MIPS_CP0_CONTEXTCONFIG  MIPS_CP0_32(4, 1)
+#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
+#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
+#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
+#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_SEGCTL0        MIPS_CP0_64(5, 2)
+#define KVM_REG_MIPS_CP0_SEGCTL1        MIPS_CP0_64(5, 3)
+#define KVM_REG_MIPS_CP0_SEGCTL2        MIPS_CP0_64(5, 4)
+#define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)
+#define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)
+#define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)
+#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)
+#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
+#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_BADINSTR       MIPS_CP0_32(8, 1)
+#define KVM_REG_MIPS_CP0_BADINSTRP      MIPS_CP0_32(8, 2)
+#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
+#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
+#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
+#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
+#define KVM_REG_MIPS_CP0_INTCTL         MIPS_CP0_32(12, 1)
+#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
+#define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
+#define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
+#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
+#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
+#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
+#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
+#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
+#define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
+#define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
+#define KVM_REG_MIPS_CP0_CONFIG6        MIPS_CP0_32(16, 6)
+#define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_MAARI          MIPS_CP0_64(17, 2)
+#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
+#define KVM_REG_MIPS_CP0_DIAG           MIPS_CP0_32(22, 0)
+#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
+#define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
+#define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
+#define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
+#define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
+#define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
+#define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
+
+
+#define KVM_MAX_VCPUS           16
+#define KVM_USER_MEM_SLOTS      16
+/* memory slots that does not exposed to userspace */
+#define KVM_PRIVATE_MEM_SLOTS   0
+
+#define KVM_HALT_POLL_NS_DEFAULT 500000
+
+#ifdef CONFIG_KVM_MIPS_VZ
+extern unsigned long GUESTID_MASK;
+extern unsigned long GUESTID_FIRST_VERSION;
+extern unsigned long GUESTID_VERSION_MASK;
+#endif
+
+
+/*
+ * Special address that contains the comm page, used for reducing # of traps
+ * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
+ * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
+ * caught.
+ */
+#define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
+                                         (0x8000 - PAGE_SIZE))
+
+#define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
+                                        ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
+
+#define KVM_GUEST_KUSEG                 0x00000000UL
+#define KVM_GUEST_KSEG0                 0x40000000UL
+#define KVM_GUEST_KSEG1                 0x40000000UL
+#define KVM_GUEST_KSEG23                0x60000000UL
+#define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
+#define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
+
+#define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
+#define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
+#define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
+#define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
+#define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
+
+#define KVM_INVALID_PAGE                0xdeadbeef
+#define KVM_INVALID_ADDR                0xdeadbeef
+
+/*
+ * EVA has overlapping user & kernel address spaces, so user VAs may be >
+ * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
+ * PAGE_OFFSET.
+ */
+
+#define KVM_HVA_ERR_BAD                 (-1UL)
+#define KVM_HVA_ERR_RO_BAD              (-2UL)
+
+static inline bool kvm_is_error_hva(unsigned long addr)
+{
+        return IS_ERR_VALUE(addr);
+}
+
+struct kvm_vm_stat {
+        ulong remote_tlb_flush;
+};
+
+struct kvm_vcpu_stat {
+        u64 wait_exits;
+        u64 cache_exits;
+        u64 signal_exits;
+        u64 int_exits;
+        u64 cop_unusable_exits;
+        u64 tlbmod_exits;
+        u64 tlbmiss_ld_exits;
+        u64 tlbmiss_st_exits;
+        u64 addrerr_st_exits;
+        u64 addrerr_ld_exits;
+        u64 syscall_exits;
+        u64 resvd_inst_exits;
+        u64 break_inst_exits;
+        u64 trap_inst_exits;
+        u64 msa_fpe_exits;
+        u64 fpe_exits;
+        u64 msa_disabled_exits;
+        u64 flush_dcache_exits;
+#ifdef CONFIG_KVM_MIPS_VZ
+        u64 vz_gpsi_exits;
+        u64 vz_gsfc_exits;
+        u64 vz_hc_exits;
+        u64 vz_grr_exits;
+        u64 vz_gva_exits;
+        u64 vz_ghfc_exits;
+        u64 vz_gpa_exits;
+        u64 vz_resvd_exits;
+#ifdef CONFIG_CPU_LOONGSON64
+        u64 vz_cpucfg_exits;
+#endif
+#endif
+        u64 halt_successful_poll;
+        u64 halt_attempted_poll;
+        u64 halt_poll_success_ns;
+        u64 halt_poll_fail_ns;
+        u64 halt_poll_invalid;
+        u64 halt_wakeup;
+};
+
+struct kvm_arch_memory_slot {
+};
+
+#ifdef CONFIG_CPU_LOONGSON64
+struct ipi_state {
+        uint32_t status;
+        uint32_t en;
+        uint32_t set;
+        uint32_t clear;
+        uint64_t buf[4];
+};
+
+struct loongson_kvm_ipi;
+
+struct ipi_io_device {
+        int node_id;
+        struct loongson_kvm_ipi *ipi;
+        struct kvm_io_device device;
+};
+
+struct loongson_kvm_ipi {
+        spinlock_t lock;
+        struct kvm *kvm;
+        struct ipi_state ipistate[16];
+        struct ipi_io_device dev_ipi[4];
+};
+#endif
+
+struct kvm_arch {
+        /* Guest physical mm */
+        struct mm_struct gpa_mm;
+        /* Mask of CPUs needing GPA ASID flush */
+        cpumask_t asid_flush_mask;
+#ifdef CONFIG_CPU_LOONGSON64
+        struct loongson_kvm_ipi ipi;
+#endif
+};
+
+#define N_MIPS_COPROC_REGS      32
+#define N_MIPS_COPROC_SEL       8
+
+struct mips_coproc {
+        unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
+#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
+        unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
+#endif
+};
+
+/*
+ * Coprocessor 0 register names
+ */
+#define MIPS_CP0_TLB_INDEX      0
+#define MIPS_CP0_TLB_RANDOM     1
+#define MIPS_CP0_TLB_LOW        2
+#define MIPS_CP0_TLB_LO0        2
+#define MIPS_CP0_TLB_LO1        3
+#define MIPS_CP0_TLB_CONTEXT    4
+#define MIPS_CP0_TLB_PG_MASK    5
+#define MIPS_CP0_TLB_WIRED      6
+#define MIPS_CP0_HWRENA         7
+#define MIPS_CP0_BAD_VADDR      8
+#define MIPS_CP0_COUNT          9
+#define MIPS_CP0_TLB_HI         10
+#define MIPS_CP0_COMPARE        11
+#define MIPS_CP0_STATUS         12
+#define MIPS_CP0_CAUSE          13
+#define MIPS_CP0_EXC_PC         14
+#define MIPS_CP0_PRID           15
+#define MIPS_CP0_CONFIG         16
+#define MIPS_CP0_LLADDR         17
+#define MIPS_CP0_WATCH_LO       18
+#define MIPS_CP0_WATCH_HI       19
+#define MIPS_CP0_TLB_XCONTEXT   20
+#define MIPS_CP0_DIAG           22
+#define MIPS_CP0_ECC            26
+#define MIPS_CP0_CACHE_ERR      27
+#define MIPS_CP0_TAG_LO         28
+#define MIPS_CP0_TAG_HI         29
+#define MIPS_CP0_ERROR_PC       30
+#define MIPS_CP0_DEBUG          23
+#define MIPS_CP0_DEPC           24
+#define MIPS_CP0_PERFCNT        25
+#define MIPS_CP0_ERRCTL         26
+#define MIPS_CP0_DATA_LO        28
+#define MIPS_CP0_DATA_HI        29
+#define MIPS_CP0_DESAVE         31
+
+#define MIPS_CP0_CONFIG_SEL     0
+#define MIPS_CP0_CONFIG1_SEL    1
+#define MIPS_CP0_CONFIG2_SEL    2
+#define MIPS_CP0_CONFIG3_SEL    3
+#define MIPS_CP0_CONFIG4_SEL    4
+#define MIPS_CP0_CONFIG5_SEL    5
+
+#define MIPS_CP0_GUESTCTL2      10
+#define MIPS_CP0_GUESTCTL2_SEL  5
+#define MIPS_CP0_GTOFFSET       12
+#define MIPS_CP0_GTOFFSET_SEL   7
+
+/* Resume Flags */
+#define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
+#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
+
+#define RESUME_GUEST            0
+#define RESUME_GUEST_DR         RESUME_FLAG_DR
+#define RESUME_HOST             RESUME_FLAG_HOST
+
+enum emulation_result {
+        EMULATE_DONE,           /* no further processing */
+        EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
+        EMULATE_FAIL,           /* can't emulate this instruction */
+        EMULATE_WAIT,           /* WAIT instruction */
+        EMULATE_PRIV_FAIL,
+        EMULATE_EXCEPT,         /* A guest exception has been generated */
+        EMULATE_HYPERCALL,      /* HYPCALL instruction */
+};
+
+#define mips3_paddr_to_tlbpfn(x) \
+        (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
+#define mips3_tlbpfn_to_paddr(x) \
+        ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
+
+#define MIPS3_PG_SHIFT          6
+#define MIPS3_PG_FRAME          0x3fffffc0
+
+#if defined(CONFIG_64BIT)
+#define VPN2_MASK               GENMASK(cpu_vmbits - 1, 13)
+#else
+#define VPN2_MASK               0xffffe000
+#endif
+#define KVM_ENTRYHI_ASID        cpu_asid_mask(&boot_cpu_data)
+#define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
+#define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
+#define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
+#define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
+#define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
+#define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
+#define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
+                                 ((y) & VPN2_MASK & ~(x).tlb_mask))
+#define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
+                                 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
+
+struct kvm_mips_tlb {
+        long tlb_mask;
+        long tlb_hi;
+        long tlb_lo[2];
+};
+
+#define KVM_MIPS_AUX_FPU        0x1
+#define KVM_MIPS_AUX_MSA        0x2
+
+#define KVM_MIPS_GUEST_TLB_SIZE 64
+struct kvm_vcpu_arch {
+        void *guest_ebase;
+        int (*vcpu_run)(struct kvm_vcpu *vcpu);
+
+        /* Host registers preserved across guest mode execution */
+        unsigned long host_stack;
+        unsigned long host_gp;
+        unsigned long host_pgd;
+        unsigned long host_entryhi;
+
+        /* Host CP0 registers used when handling exits from guest */
+        unsigned long host_cp0_badvaddr;
+        unsigned long host_cp0_epc;
+        u32 host_cp0_cause;
+        u32 host_cp0_guestctl0;
+        u32 host_cp0_badinstr;
+        u32 host_cp0_badinstrp;
+
+        /* GPRS */
+        unsigned long gprs[32];
+        unsigned long hi;
+        unsigned long lo;
+        unsigned long pc;
+
+        /* FPU State */
+        struct mips_fpu_struct fpu;
+        /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
+        unsigned int aux_inuse;
+
+        /* COP0 State */
+        struct mips_coproc *cop0;
+
+        /* Host KSEG0 address of the EI/DI offset */
+        void *kseg0_commpage;
+
+        /* Resume PC after MMIO completion */
+        unsigned long io_pc;
+        /* GPR used as IO source/target */
+        u32 io_gpr;
+
+        struct hrtimer comparecount_timer;
+        /* Count timer control KVM register */
+        u32 count_ctl;
+        /* Count bias from the raw time */
+        u32 count_bias;
+        /* Frequency of timer in Hz */
+        u32 count_hz;
+        /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
+        s64 count_dyn_bias;
+        /* Resume time */
+        ktime_t count_resume;
+        /* Period of timer tick in ns */
+        u64 count_period;
+
+        /* Bitmask of exceptions that are pending */
+        unsigned long pending_exceptions;
+
+        /* Bitmask of pending exceptions to be cleared */
+        unsigned long pending_exceptions_clr;
+
+        /* S/W Based TLB for guest */
+        struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
+
+        /* Guest kernel/user [partial] mm */
+        struct mm_struct guest_kernel_mm, guest_user_mm;
+
+        /* Guest ASID of last user mode execution */
+        unsigned int last_user_gasid;
+
+        /* Cache some mmu pages needed inside spinlock regions */
+        struct kvm_mmu_memory_cache mmu_page_cache;
+
+#ifdef CONFIG_KVM_MIPS_VZ
+        /* vcpu's vzguestid is different on each host cpu in an smp system */
+        u32 vzguestid[NR_CPUS];
+
+        /* wired guest TLB entries */
+        struct kvm_mips_tlb *wired_tlb;
+        unsigned int wired_tlb_limit;
+        unsigned int wired_tlb_used;
+
+        /* emulated guest MAAR registers */
+        unsigned long maar[6];
+#endif
+
+        /* Last CPU the VCPU state was loaded on */
+        int last_sched_cpu;
+        /* Last CPU the VCPU actually executed guest code on */
+        int last_exec_cpu;
+
+        /* WAIT executed */
+        int wait;
+
+        u8 fpu_enabled;
+        u8 msa_enabled;
+};
+
+static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
+                                                unsigned long val)
+{
+        unsigned long temp;
+        do {
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
+                "       " __LL "%0, %1                          \n"
+                "       or      %0, %2                          \n"
+                "       " __SC  "%0, %1                         \n"
+                "       .set    pop                             \n"
+                : "=&r" (temp), "+m" (*reg)
+                : "r" (val));
+        } while (unlikely(!temp));
+}
+
+static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
+                                                  unsigned long val)
+{
+        unsigned long temp;
+        do {
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
+                "       " __LL "%0, %1                          \n"
+                "       and     %0, %2                          \n"
+                "       " __SC  "%0, %1                         \n"
+                "       .set    pop                             \n"
+                : "=&r" (temp), "+m" (*reg)
+                : "r" (~val));
+        } while (unlikely(!temp));
+}
+
+static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
+                                                   unsigned long change,
+                                                   unsigned long val)
+{
+        unsigned long temp;
+        do {
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
+                "       " __LL "%0, %1                          \n"
+                "       and     %0, %2                          \n"
+                "       or      %0, %3                          \n"
+                "       " __SC  "%0, %1                         \n"
+                "       .set    pop                             \n"
+                : "=&r" (temp), "+m" (*reg)
+                : "r" (~change), "r" (val & change));
+        } while (unlikely(!temp));
+}
+
+/* Guest register types, used in accessor build below */
+#define __KVMT32        u32
+#define __KVMTl unsigned long
+
+/*
+ * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
+ * These operate on the saved guest C0 state in RAM.
+ */
+
+/* Generate saved context simple accessors */
+#define __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
+static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
+{                                                                       \
+        return cop0->reg[(_reg)][(sel)];                                \
+}                                                                       \
+static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0,    \
+                                           __KVMT##type val)            \
+{                                                                       \
+        cop0->reg[(_reg)][(sel)] = val;                                 \
+}
+
+/* Generate saved context bitwise modifiers */
+#define __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
+static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
+                                         __KVMT##type val)              \
+{                                                                       \
+        cop0->reg[(_reg)][(sel)] |= val;                                \
+}                                                                       \
+static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
+                                           __KVMT##type val)            \
+{                                                                       \
+        cop0->reg[(_reg)][(sel)] &= ~val;                               \
+}                                                                       \
+static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
+                                            __KVMT##type mask,          \
+                                            __KVMT##type val)           \
+{                                                                       \
+        unsigned long _mask = mask;                                     \
+        cop0->reg[(_reg)][(sel)] &= ~_mask;                             \
+        cop0->reg[(_reg)][(sel)] |= val & _mask;                        \
+}
+
+/* Generate saved context atomic bitwise modifiers */
+#define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
+static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
+                                         __KVMT##type val)              \
+{                                                                       \
+        _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val);   \
+}                                                                       \
+static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
+                                           __KVMT##type val)            \
+{                                                                       \
+        _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
+}                                                                       \
+static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
+                                            __KVMT##type mask,          \
+                                            __KVMT##type val)           \
+{                                                                       \
+        _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
+                                        val);                           \
+}
+
+/*
+ * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
+ * These operate on the VZ guest C0 context in hardware.
+ */
+
+/* Generate VZ guest context simple accessors */
+#define __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
+static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
+{                                                                       \
+        return read_gc0_##name();                                       \
+}                                                                       \
+static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0,    \
+                                           __KVMT##type val)            \
+{                                                                       \
+        write_gc0_##name(val);                                          \
+}
+
+/* Generate VZ guest context bitwise modifiers */
+#define __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
+static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0,      \
+                                         __KVMT##type val)              \
+{                                                                       \
+        set_gc0_##name(val);                                            \
+}                                                                       \
+static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0,    \
+                                           __KVMT##type val)            \
+{                                                                       \
+        clear_gc0_##name(val);                                          \
+}                                                                       \
+static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0,   \
+                                            __KVMT##type mask,          \
+                                            __KVMT##type val)           \
+{                                                                       \
+        change_gc0_##name(mask, val);                                   \
+}
+
+/* Generate VZ guest context save/restore to/from saved context */
+#define __BUILD_KVM_SAVE_VZ(name, _reg, sel)                    \
+static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0)     \
+{                                                                       \
+        write_gc0_##name(cop0->reg[(_reg)][(sel)]);                     \
+}                                                                       \
+static inline void kvm_save_gc0_##name(struct mips_coproc *cop0)        \
+{                                                                       \
+        cop0->reg[(_reg)][(sel)] = read_gc0_##name();                   \
+}
+
+/*
+ * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
+ * These wrap a set of operations to provide them with a different name.
+ */
+
+/* Generate simple accessor wrapper */
+#define __BUILD_KVM_RW_WRAP(name1, name2, type)                         \
+static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0)   \
+{                                                                       \
+        return kvm_read_##name2(cop0);                                  \
+}                                                                       \
+static inline void kvm_write_##name1(struct mips_coproc *cop0,          \
+                                     __KVMT##type val)                  \
+{                                                                       \
+        kvm_write_##name2(cop0, val);                                   \
+}
+
+/* Generate bitwise modifier wrapper */
+#define __BUILD_KVM_SET_WRAP(name1, name2, type)                        \
+static inline void kvm_set_##name1(struct mips_coproc *cop0,            \
+                                   __KVMT##type val)                    \
+{                                                                       \
+        kvm_set_##name2(cop0, val);                                     \
+}                                                                       \
+static inline void kvm_clear_##name1(struct mips_coproc *cop0,          \
+                                     __KVMT##type val)                  \
+{                                                                       \
+        kvm_clear_##name2(cop0, val);                                   \
+}                                                                       \
+static inline void kvm_change_##name1(struct mips_coproc *cop0,         \
+                                      __KVMT##type mask,                \
+                                      __KVMT##type val)                 \
+{                                                                       \
+        kvm_change_##name2(cop0, mask, val);                            \
+}
+
+/*
+ * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
+ * These generate accessors operating on the saved context in RAM, and wrap them
+ * with the common guest C0 accessors (for use by common emulation code).
+ */
+
+#define __BUILD_KVM_RW_SW(name, type, _reg, sel)                        \
+        __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
+        __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
+
+#define __BUILD_KVM_SET_SW(name, type, _reg, sel)                       \
+        __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
+        __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
+
+#define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel)                    \
+        __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
+        __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
+
+#ifndef CONFIG_KVM_MIPS_VZ
+
+/*
+ * T&E (trap & emulate software based virtualisation)
+ * We generate the common accessors operating exclusively on the saved context
+ * in RAM.
+ */
+
+#define __BUILD_KVM_RW_HW       __BUILD_KVM_RW_SW
+#define __BUILD_KVM_SET_HW      __BUILD_KVM_SET_SW
+#define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_ATOMIC_SW
+
+#else
+
+/*
+ * VZ (hardware assisted virtualisation)
+ * These macros use the active guest state in VZ mode (hardware registers),
+ */
+
+/*
+ * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
+ * These generate accessors operating on the VZ guest context in hardware, and
+ * wrap them with the common guest C0 accessors (for use by common emulation
+ * code).
+ *
+ * Accessors operating on the saved context in RAM are also generated to allow
+ * convenient explicit saving and restoring of the state.
+ */
+
+#define __BUILD_KVM_RW_HW(name, type, _reg, sel)                        \
+        __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
+        __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
+        __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type)       \
+        __BUILD_KVM_SAVE_VZ(name, _reg, sel)
+
+#define __BUILD_KVM_SET_HW(name, type, _reg, sel)                       \
+        __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
+        __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
+        __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
+
+/*
+ * We can't do atomic modifications of COP0 state if hardware can modify it.
+ * Races must be handled explicitly.
+ */
+#define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_SET_HW
+
+#endif
+
+/*
+ * Define accessors for CP0 registers that are accessible to the guest. These
+ * are primarily used by common emulation code, which may need to access the
+ * registers differently depending on the implementation.
+ *
+ *    fns_hw/sw    name     type    reg num         select
+ */
+__BUILD_KVM_RW_HW(index,          32, MIPS_CP0_TLB_INDEX,    0)
+__BUILD_KVM_RW_HW(entrylo0,       l,  MIPS_CP0_TLB_LO0,      0)
+__BUILD_KVM_RW_HW(entrylo1,       l,  MIPS_CP0_TLB_LO1,      0)
+__BUILD_KVM_RW_HW(context,        l,  MIPS_CP0_TLB_CONTEXT,  0)
+__BUILD_KVM_RW_HW(contextconfig,  32, MIPS_CP0_TLB_CONTEXT,  1)
+__BUILD_KVM_RW_HW(userlocal,      l,  MIPS_CP0_TLB_CONTEXT,  2)
+__BUILD_KVM_RW_HW(xcontextconfig, l,  MIPS_CP0_TLB_CONTEXT,  3)
+__BUILD_KVM_RW_HW(pagemask,       l,  MIPS_CP0_TLB_PG_MASK,  0)
+__BUILD_KVM_RW_HW(pagegrain,      32, MIPS_CP0_TLB_PG_MASK,  1)
+__BUILD_KVM_RW_HW(segctl0,        l,  MIPS_CP0_TLB_PG_MASK,  2)
+__BUILD_KVM_RW_HW(segctl1,        l,  MIPS_CP0_TLB_PG_MASK,  3)
+__BUILD_KVM_RW_HW(segctl2,        l,  MIPS_CP0_TLB_PG_MASK,  4)
+__BUILD_KVM_RW_HW(pwbase,         l,  MIPS_CP0_TLB_PG_MASK,  5)
+__BUILD_KVM_RW_HW(pwfield,        l,  MIPS_CP0_TLB_PG_MASK,  6)
+__BUILD_KVM_RW_HW(pwsize,         l,  MIPS_CP0_TLB_PG_MASK,  7)
+__BUILD_KVM_RW_HW(wired,          32, MIPS_CP0_TLB_WIRED,    0)
+__BUILD_KVM_RW_HW(pwctl,          32, MIPS_CP0_TLB_WIRED,    6)
+__BUILD_KVM_RW_HW(hwrena,         32, MIPS_CP0_HWRENA,       0)
+__BUILD_KVM_RW_HW(badvaddr,       l,  MIPS_CP0_BAD_VADDR,    0)
+__BUILD_KVM_RW_HW(badinstr,       32, MIPS_CP0_BAD_VADDR,    1)
+__BUILD_KVM_RW_HW(badinstrp,      32, MIPS_CP0_BAD_VADDR,    2)
+__BUILD_KVM_RW_SW(count,          32, MIPS_CP0_COUNT,        0)
+__BUILD_KVM_RW_HW(entryhi,        l,  MIPS_CP0_TLB_HI,       0)
+__BUILD_KVM_RW_HW(compare,        32, MIPS_CP0_COMPARE,      0)
+__BUILD_KVM_RW_HW(status,         32, MIPS_CP0_STATUS,       0)
+__BUILD_KVM_RW_HW(intctl,         32, MIPS_CP0_STATUS,       1)
+__BUILD_KVM_RW_HW(cause,          32, MIPS_CP0_CAUSE,        0)
+__BUILD_KVM_RW_HW(epc,            l,  MIPS_CP0_EXC_PC,       0)
+__BUILD_KVM_RW_SW(prid,           32, MIPS_CP0_PRID,         0)
+__BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
+__BUILD_KVM_RW_HW(config,         32, MIPS_CP0_CONFIG,       0)
+__BUILD_KVM_RW_HW(config1,        32, MIPS_CP0_CONFIG,       1)
+__BUILD_KVM_RW_HW(config2,        32, MIPS_CP0_CONFIG,       2)
+__BUILD_KVM_RW_HW(config3,        32, MIPS_CP0_CONFIG,       3)
+__BUILD_KVM_RW_HW(config4,        32, MIPS_CP0_CONFIG,       4)
+__BUILD_KVM_RW_HW(config5,        32, MIPS_CP0_CONFIG,       5)
+__BUILD_KVM_RW_HW(config6,        32, MIPS_CP0_CONFIG,       6)
+__BUILD_KVM_RW_HW(config7,        32, MIPS_CP0_CONFIG,       7)
+__BUILD_KVM_RW_SW(maari,          l,  MIPS_CP0_LLADDR,       2)
+__BUILD_KVM_RW_HW(xcontext,       l,  MIPS_CP0_TLB_XCONTEXT, 0)
+__BUILD_KVM_RW_HW(errorepc,       l,  MIPS_CP0_ERROR_PC,     0)
+__BUILD_KVM_RW_HW(kscratch1,      l,  MIPS_CP0_DESAVE,       2)
+__BUILD_KVM_RW_HW(kscratch2,      l,  MIPS_CP0_DESAVE,       3)
+__BUILD_KVM_RW_HW(kscratch3,      l,  MIPS_CP0_DESAVE,       4)
+__BUILD_KVM_RW_HW(kscratch4,      l,  MIPS_CP0_DESAVE,       5)
+__BUILD_KVM_RW_HW(kscratch5,      l,  MIPS_CP0_DESAVE,       6)
+__BUILD_KVM_RW_HW(kscratch6,      l,  MIPS_CP0_DESAVE,       7)
+
+/* Bitwise operations (on HW state) */
+__BUILD_KVM_SET_HW(status,        32, MIPS_CP0_STATUS,       0)
+/* Cause can be modified asynchronously from hardirq hrtimer callback */
+__BUILD_KVM_ATOMIC_HW(cause,      32, MIPS_CP0_CAUSE,        0)
+__BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
+
+/* Bitwise operations (on saved state) */
+__BUILD_KVM_SET_SAVED(config,     32, MIPS_CP0_CONFIG,       0)
+__BUILD_KVM_SET_SAVED(config1,    32, MIPS_CP0_CONFIG,       1)
+__BUILD_KVM_SET_SAVED(config2,    32, MIPS_CP0_CONFIG,       2)
+__BUILD_KVM_SET_SAVED(config3,    32, MIPS_CP0_CONFIG,       3)
+__BUILD_KVM_SET_SAVED(config4,    32, MIPS_CP0_CONFIG,       4)
+__BUILD_KVM_SET_SAVED(config5,    32, MIPS_CP0_CONFIG,       5)
+
+/* Helpers */
+
+static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
+{
+        return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
+                vcpu->fpu_enabled;
+}
+
+static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
+{
+        return kvm_mips_guest_can_have_fpu(vcpu) &&
+                kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
+}
+
+static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
+{
+        return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
+                vcpu->msa_enabled;
+}
+
+static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
+{
+        return kvm_mips_guest_can_have_msa(vcpu) &&
+                kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
+}
+
+struct kvm_mips_callbacks {
+        int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
+        int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
+        int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
+        int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
+        int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
+        int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
+        int (*handle_syscall)(struct kvm_vcpu *vcpu);
+        int (*handle_res_inst)(struct kvm_vcpu *vcpu);
+        int (*handle_break)(struct kvm_vcpu *vcpu);
+        int (*handle_trap)(struct kvm_vcpu *vcpu);
+        int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
+        int (*handle_fpe)(struct kvm_vcpu *vcpu);
+        int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
+        int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
+        int (*hardware_enable)(void);
+        void (*hardware_disable)(void);
+        int (*check_extension)(struct kvm *kvm, long ext);
+        int (*vcpu_init)(struct kvm_vcpu *vcpu);
+        void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
+        int (*vcpu_setup)(struct kvm_vcpu *vcpu);
+        void (*flush_shadow_all)(struct kvm *kvm);
+        /*
+         * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
+         * VZ root TLB, or T&E GVA page tables and corresponding root TLB
+         * mappings).
+         */
+        void (*flush_shadow_memslot)(struct kvm *kvm,
+                                     const struct kvm_memory_slot *slot);
+        gpa_t (*gva_to_gpa)(gva_t gva);
+        void (*queue_timer_int)(struct kvm_vcpu *vcpu);
+        void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
+        void (*queue_io_int)(struct kvm_vcpu *vcpu,
+                             struct kvm_mips_interrupt *irq);
+        void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
+                               struct kvm_mips_interrupt *irq);
+        int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
+                           u32 cause);
+        int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
+                         u32 cause);
+        unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
+        int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
+        int (*get_one_reg)(struct kvm_vcpu *vcpu,
+                           const struct kvm_one_reg *reg, s64 *v);
+        int (*set_one_reg)(struct kvm_vcpu *vcpu,
+                           const struct kvm_one_reg *reg, s64 v);
+        int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
+        int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
+        int (*vcpu_run)(struct kvm_vcpu *vcpu);
+        void (*vcpu_reenter)(struct kvm_vcpu *vcpu);
+};
+extern struct kvm_mips_callbacks *kvm_mips_callbacks;
+int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
+
+/* Debug: dump vcpu state */
+int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
+
+extern int kvm_mips_handle_exit(struct kvm_vcpu *vcpu);
+
+/* Building of entry/exception code */
+int kvm_mips_entry_setup(void);
+void *kvm_mips_build_vcpu_run(void *addr);
+void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
+void *kvm_mips_build_exception(void *addr, void *handler);
+void *kvm_mips_build_exit(void *addr);
+
+/* FPU/MSA context management */
+void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
+void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
+void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
+void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
+void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
+void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
+void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
+void kvm_own_fpu(struct kvm_vcpu *vcpu);
+void kvm_own_msa(struct kvm_vcpu *vcpu);
+void kvm_drop_fpu(struct kvm_vcpu *vcpu);
+void kvm_lose_fpu(struct kvm_vcpu *vcpu);
+
+/* TLB handling */
+u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
+
+u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
+
+u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
+
+#ifdef CONFIG_KVM_MIPS_VZ
+int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
+                                      struct kvm_vcpu *vcpu, bool write_fault);
+#endif
+extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
+                                           struct kvm_vcpu *vcpu,
+                                           bool write_fault);
+
+extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
+                                              struct kvm_vcpu *vcpu);
+
+extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
+                                                struct kvm_mips_tlb *tlb,
+                                                unsigned long gva,
+                                                bool write_fault);
+
+extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
+                                                     u32 *opc,
+                                                     struct kvm_vcpu *vcpu,
+                                                     bool write_fault);
+
+extern void kvm_mips_dump_host_tlbs(void);
+extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
+extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
+                                 bool user, bool kernel);
+
+extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
+                                     unsigned long entryhi);
+
+#ifdef CONFIG_KVM_MIPS_VZ
+int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
+int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
+                            unsigned long *gpa);
+void kvm_vz_local_flush_roottlb_all_guests(void);
+void kvm_vz_local_flush_guesttlb_all(void);
+void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
+                          unsigned int count);
+void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
+                          unsigned int count);
+#ifdef CONFIG_CPU_LOONGSON64
+void kvm_loongson_clear_guest_vtlb(void);
+void kvm_loongson_clear_guest_ftlb(void);
+#endif
+#endif
+
+void kvm_mips_suspend_mm(int cpu);
+void kvm_mips_resume_mm(int cpu);
+
+/* MMU handling */
+
+/**
+ * enum kvm_mips_flush - Types of MMU flushes.
+ * @KMF_USER:   Flush guest user virtual memory mappings.
+ *              Guest USeg only.
+ * @KMF_KERN:   Flush guest kernel virtual memory mappings.
+ *              Guest USeg and KSeg2/3.
+ * @KMF_GPA:    Flush guest physical memory mappings.
+ *              Also includes KSeg0 if KMF_KERN is set.
+ */
+enum kvm_mips_flush {
+        KMF_USER        = 0x0,
+        KMF_KERN        = 0x1,
+        KMF_GPA         = 0x2,
+};
+void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
+bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
+int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
+pgd_t *kvm_pgd_alloc(void);
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
+                                  bool user);
+void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
+void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
+
+enum kvm_mips_fault_result {
+        KVM_MIPS_MAPPED = 0,
+        KVM_MIPS_GVA,
+        KVM_MIPS_GPA,
+        KVM_MIPS_TLB,
+        KVM_MIPS_TLBINV,
+        KVM_MIPS_TLBMOD,
+};
+enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
+                                                   unsigned long gva,
+                                                   bool write);
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end, unsigned flags);
+int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
+int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
+
+/* Emulation */
+int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
+enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
+int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
+int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
+
+/**
+ * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
+ * @vcpu:       Virtual CPU.
+ *
+ * Returns:     Whether the TLBL exception was likely due to an instruction
+ *              fetch fault rather than a data load fault.
+ */
+static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
+{
+        unsigned long badvaddr = vcpu->host_cp0_badvaddr;
+        unsigned long epc = msk_isa16_mode(vcpu->pc);
+        u32 cause = vcpu->host_cp0_cause;
+
+        if (epc == badvaddr)
+                return true;
+
+        /*
+         * Branches may be 32-bit or 16-bit instructions.
+         * This isn't exact, but we don't really support MIPS16 or microMIPS yet
+         * in KVM anyway.
+         */
+        if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
+                return true;
+
+        return false;
+}
+
+extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
+                                                   u32 *opc,
+                                                   struct kvm_vcpu *vcpu);
+
+long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
+                                                      u32 *opc,
+                                                      struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
+                                                         u32 *opc,
+                                                         struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
+                                                        u32 *opc,
+                                                        struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
+                                                         u32 *opc,
+                                                         struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
+                                                        u32 *opc,
+                                                        struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
+                                                     u32 *opc,
+                                                     struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
+                                                      u32 *opc,
+                                                      struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_handle_ri(u32 cause,
+                                                u32 *opc,
+                                                struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
+                                                     u32 *opc,
+                                                     struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
+                                                     u32 *opc,
+                                                     struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
+                                                       u32 *opc,
+                                                       struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
+                                                         u32 *opc,
+                                                         struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
+                                                      u32 *opc,
+                                                      struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
+                                                         u32 *opc,
+                                                         struct kvm_vcpu *vcpu);
+
+extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu);
+
+u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
+void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
+void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
+void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
+int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
+int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
+int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
+void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
+void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
+enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
+
+/* fairly internal functions requiring some care to use */
+int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
+ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
+int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
+                             u32 count, int min_drift);
+
+#ifdef CONFIG_KVM_MIPS_VZ
+void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
+void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
+#else
+static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {}
+static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {}
+#endif
+
+enum emulation_result kvm_mips_check_privilege(u32 cause,
+                                               u32 *opc,
+                                               struct kvm_vcpu *vcpu);
+
+enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
+                                             u32 *opc,
+                                             u32 cause,
+                                             struct kvm_vcpu *vcpu);
+enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
+                                           u32 *opc,
+                                           u32 cause,
+                                           struct kvm_vcpu *vcpu);
+enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
+                                             u32 cause,
+                                             struct kvm_vcpu *vcpu);
+enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
+                                            u32 cause,
+                                            struct kvm_vcpu *vcpu);
+
+/* COP0 */
+enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
+
+unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
+unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
+unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
+unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
+
+/* Hypercalls (hypcall.c) */
+
+enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
+                                            union mips_instruction inst);
+int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
+
+/* Dynamic binary translation */
+extern int kvm_mips_trans_cache_index(union mips_instruction inst,
+                                      u32 *opc, struct kvm_vcpu *vcpu);
+extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
+                                   struct kvm_vcpu *vcpu);
+extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
+                               struct kvm_vcpu *vcpu);
+extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
+                               struct kvm_vcpu *vcpu);
+
+/* Misc */
+extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
+extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
+extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
+                             struct kvm_mips_interrupt *irq);
+
+static inline void kvm_arch_hardware_unsetup(void) {}
+static inline void kvm_arch_sync_events(struct kvm *kvm) {}
+static inline void kvm_arch_free_memslot(struct kvm *kvm,
+                                         struct kvm_memory_slot *slot) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
+static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
+static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
+static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
+
+#endif /* __MIPS_KVM_HOST_H__ */
diff --git a/arch/mips/include/asm/kvm_types.h b/arch/mips/include/asm/kvm_types.h
new file mode 100644
index 000000000..213754d9e
--- /dev/null
+++ b/arch/mips/include/asm/kvm_types.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MIPS_KVM_TYPES_H
+#define _ASM_MIPS_KVM_TYPES_H
+
+#define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE     4
+
+#endif /* _ASM_MIPS_KVM_TYPES_H */
diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h
new file mode 100644
index 000000000..1829c2b6d
--- /dev/null
+++ b/arch/mips/include/asm/linkage.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#ifdef __ASSEMBLY__
+#include <asm/asm.h>
+#endif
+
+#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
+#define SYSCALL_ALIAS(alias, name)                                      \
+        asm ( #alias " = " #name "\n\t.globl " #alias)
+
+#endif
diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h
new file mode 100644
index 000000000..ec09fe5d6
--- /dev/null
+++ b/arch/mips/include/asm/llsc.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Macros for 32/64-bit neutral inline assembler
+ */
+
+#ifndef __ASM_LLSC_H
+#define __ASM_LLSC_H
+
+#include <asm/isa-rev.h>
+
+#if _MIPS_SZLONG == 32
+#define __LL            "ll     "
+#define __SC            "sc     "
+#define __INS           "ins    "
+#define __EXT           "ext    "
+#elif _MIPS_SZLONG == 64
+#define __LL            "lld    "
+#define __SC            "scd    "
+#define __INS           "dins   "
+#define __EXT           "dext   "
+#endif
+
+/*
+ * Using a branch-likely instruction to check the result of an sc instruction
+ * works around a bug present in R10000 CPUs prior to revision 3.0 that could
+ * cause ll-sc sequences to execute non-atomically.
+ */
+#ifdef CONFIG_WAR_R10000_LLSC
+# define __SC_BEQZ "beqzl       "
+#elif MIPS_ISA_REV >= 6
+# define __SC_BEQZ "beqzc       "
+#else
+# define __SC_BEQZ "beqz        "
+#endif
+
+#endif /* __ASM_LLSC_H  */
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
new file mode 100644
index 000000000..ecda7295d
--- /dev/null
+++ b/arch/mips/include/asm/local.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ARCH_MIPS_LOCAL_H
+#define _ARCH_MIPS_LOCAL_H
+
+#include <linux/percpu.h>
+#include <linux/bitops.h>
+#include <linux/atomic.h>
+#include <asm/cmpxchg.h>
+#include <asm/compiler.h>
+#include <asm/war.h>
+
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
+
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
+
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l, i) atomic_long_set(&(l)->a, (i))
+
+#define local_add(i, l) atomic_long_add((i), (&(l)->a))
+#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ long local_add_return(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    arch=r4000                              \n"
+                        __SYNC(full, loongson3_war) "                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    pop                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (kernel_uses_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
+                        __SYNC(full, loongson3_war) "                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    pop                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result += i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
+
+static __inline__ long local_sub_return(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    arch=r4000                              \n"
+                        __SYNC(full, loongson3_war) "                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    pop                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (kernel_uses_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
+                        __SYNC(full, loongson3_war) "                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    pop                                     \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result -= i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
+
+#define local_cmpxchg(l, o, n) \
+        ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (atomic_long_xchg((&(l)->a), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) \
+                c = old;                                        \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_dec_return(l) local_sub_return(1, (l))
+#define local_inc_return(l) local_add_return(1, (l))
+
+/*
+ * local_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @l: pointer of type local_t
+ *
+ * Atomically subtracts @i from @l and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
+
+/*
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_inc_and_test(l) (local_inc_return(l) == 0)
+
+/*
+ * local_dec_and_test - decrement by 1 and test
+ * @l: pointer of type local_t
+ *
+ * Atomically decrements @l by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
+
+/*
+ * local_add_negative - add and test if negative
+ * @l: pointer of type local_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @l and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
+
+/* Use these for per-cpu local_t variables: on some archs they are
+ * much more efficient than these naive implementations.  Note they take
+ * a variable, not an address.
+ */
+
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i, l)       ((l)->a.counter+=(i))
+#define __local_sub(i, l)       ((l)->a.counter-=(i))
+
+#endif /* _ARCH_MIPS_LOCAL_H */
diff --git a/arch/mips/include/asm/maar.h b/arch/mips/include/asm/maar.h
new file mode 100644
index 000000000..99f1c3e4b
--- /dev/null
+++ b/arch/mips/include/asm/maar.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2014 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MIPS_MAAR_H__
+#define __MIPS_ASM_MIPS_MAAR_H__
+
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+
+/**
+ * platform_maar_init() - perform platform-level MAAR configuration
+ * @num_pairs:  The number of MAAR pairs present in the system.
+ *
+ * Platforms should implement this function such that it configures as many
+ * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
+ * the number that were used. Any further MAARs will be configured to be
+ * invalid. The default implementation of this function will simply indicate
+ * that it has configured 0 MAAR pairs.
+ *
+ * Return:      The number of MAAR pairs configured.
+ */
+unsigned platform_maar_init(unsigned num_pairs);
+
+/**
+ * write_maar_pair() - write to a pair of MAARs
+ * @idx:        The index of the pair (ie. use MAARs idx*2 & (idx*2)+1).
+ * @lower:      The lowest address that the MAAR pair will affect. Must be
+ *              aligned to a 2^16 byte boundary.
+ * @upper:      The highest address that the MAAR pair will affect. Must be
+ *              aligned to one byte before a 2^16 byte boundary.
+ * @attrs:      The accessibility attributes to program, eg. MIPS_MAAR_S. The
+ *              MIPS_MAAR_VL/MIPS_MAAR_VH attributes will automatically be set.
+ *
+ * Program the pair of MAAR registers specified by idx to apply the attributes
+ * specified by attrs to the range of addresses from lower to higher.
+ */
+static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
+                                   phys_addr_t upper, unsigned attrs)
+{
+        /* Addresses begin at bit 16, but are shifted right 4 bits */
+        BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4)));
+        BUG_ON(((upper & 0xffff) != 0xffff)
+                || ((upper & ~0xffffull) & ~(MIPS_MAAR_ADDR << 4)));
+
+        /* Automatically set MIPS_MAAR_VL */
+        attrs |= MIPS_MAAR_VL;
+
+        /*
+         * Write the upper address & attributes (both MIPS_MAAR_VL and
+         * MIPS_MAAR_VH matter)
+         */
+        write_c0_maari(idx << 1);
+        back_to_back_c0_hazard();
+        write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
+        back_to_back_c0_hazard();
+#ifdef CONFIG_XPA
+        upper >>= MIPS_MAARX_ADDR_SHIFT;
+        writex_c0_maar(((upper >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
+        back_to_back_c0_hazard();
+#endif
+
+        /* Write the lower address & attributes */
+        write_c0_maari((idx << 1) | 0x1);
+        back_to_back_c0_hazard();
+        write_c0_maar((lower >> 4) | attrs);
+        back_to_back_c0_hazard();
+#ifdef CONFIG_XPA
+        lower >>= MIPS_MAARX_ADDR_SHIFT;
+        writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
+        back_to_back_c0_hazard();
+#endif
+}
+
+/**
+ * maar_init() - initialise MAARs
+ *
+ * Performs initialisation of MAARs for the current CPU, making use of the
+ * platforms implementation of platform_maar_init where necessary and
+ * duplicating the setup it provides on secondary CPUs.
+ */
+extern void maar_init(void);
+
+/**
+ * struct maar_config - MAAR configuration data
+ * @lower:      The lowest address that the MAAR pair will affect. Must be
+ *              aligned to a 2^16 byte boundary.
+ * @upper:      The highest address that the MAAR pair will affect. Must be
+ *              aligned to one byte before a 2^16 byte boundary.
+ * @attrs:      The accessibility attributes to program, eg. MIPS_MAAR_S. The
+ *              MIPS_MAAR_VL attribute will automatically be set.
+ *
+ * Describes the configuration of a pair of Memory Accessibility Attribute
+ * Registers - applying attributes from attrs to the range of physical
+ * addresses from lower to upper inclusive.
+ */
+struct maar_config {
+        phys_addr_t lower;
+        phys_addr_t upper;
+        unsigned attrs;
+};
+
+/**
+ * maar_config() - configure MAARs according to provided data
+ * @cfg:        Pointer to an array of struct maar_config.
+ * @num_cfg:    The number of structs in the cfg array.
+ * @num_pairs:  The number of MAAR pairs present in the system.
+ *
+ * Configures as many MAARs as are present and specified in the cfg
+ * array with the values taken from the cfg array.
+ *
+ * Return:      The number of MAAR pairs configured.
+ */
+static inline unsigned maar_config(const struct maar_config *cfg,
+                                   unsigned num_cfg, unsigned num_pairs)
+{
+        unsigned i;
+
+        for (i = 0; i < min(num_cfg, num_pairs); i++)
+                write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs);
+
+        return i;
+}
+
+#endif /* __MIPS_ASM_MIPS_MAAR_H__ */
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
new file mode 100644
index 000000000..dd09c3bf0
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
+ */
+
+#ifndef __AR7_H__
+#define __AR7_H__
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+
+#include <asm/addrspace.h>
+
+#define AR7_SDRAM_BASE  0x14000000
+
+#define AR7_REGS_BASE   0x08610000
+
+#define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
+#define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
+/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
+#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
+#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
+#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
+#define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
+#define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
+#define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
+#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
+#define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
+#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
+#define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
+#define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
+#define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
+
+#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
+#define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
+#define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
+
+/* Titan registers */
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)
+#define TITAN_REGS_MAC0         (TITAN_REGS_ESWITCH_BASE)
+#define TITAN_REGS_MAC1         (TITAN_REGS_ESWITCH_BASE + 0x0800)
+#define TITAN_REGS_MDIO         (TITAN_REGS_ESWITCH_BASE + 0x02000)
+#define TITAN_REGS_VLYNQ0       (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1       (AR7_REGS_BASE + 0x1300)
+
+#define AR7_RESET_PERIPHERAL    0x0
+#define AR7_RESET_SOFTWARE      0x4
+#define AR7_RESET_STATUS        0x8
+
+#define AR7_RESET_BIT_CPMAC_LO  17
+#define AR7_RESET_BIT_CPMAC_HI  21
+#define AR7_RESET_BIT_MDIO      22
+#define AR7_RESET_BIT_EPHY      26
+
+#define TITAN_RESET_BIT_EPHY1   28
+
+/* GPIO control registers */
+#define AR7_GPIO_INPUT  0x0
+#define AR7_GPIO_OUTPUT 0x4
+#define AR7_GPIO_DIR    0x8
+#define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0      0x0
+#define TITAN_GPIO_INPUT_1      0x4
+#define TITAN_GPIO_OUTPUT_0     0x8
+#define TITAN_GPIO_OUTPUT_1     0xc
+#define TITAN_GPIO_DIR_0        0x10
+#define TITAN_GPIO_DIR_1        0x14
+#define TITAN_GPIO_ENBL_0       0x18
+#define TITAN_GPIO_ENBL_1       0x1c
+
+#define AR7_CHIP_7100   0x18
+#define AR7_CHIP_7200   0x2b
+#define AR7_CHIP_7300   0x05
+#define AR7_CHIP_TITAN  0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
+
+/* Interrupts */
+#define AR7_IRQ_UART0   15
+#define AR7_IRQ_UART1   16
+
+/* Clocks */
+#define AR7_AFE_CLOCK   35328000
+#define AR7_REF_CLOCK   25000000
+#define AR7_XTAL_CLOCK  24000000
+
+/* DCL */
+#define AR7_WDT_HW_ENA  0x10
+
+struct plat_cpmac_data {
+        int reset_bit;
+        int power_bit;
+        u32 phy_mask;
+        char dev_addr[6];
+};
+
+struct plat_dsl_data {
+        int reset_bit_dsl;
+        int reset_bit_sar;
+};
+
+extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+
+static inline int ar7_is_titan(void)
+{
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+                AR7_CHIP_TITAN;
+}
+
+static inline u16 ar7_chip_id(void)
+{
+        return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+                KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
+}
+
+static inline u16 titan_chip_id(void)
+{
+        unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
+                                                TITAN_GPIO_INPUT_1));
+        return ((val >> 12) & 0x0f);
+}
+
+static inline u8 ar7_chip_rev(void)
+{
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+                0x14))) >> 16) & 0xff;
+}
+
+struct clk {
+        unsigned int    rate;
+};
+
+static inline int ar7_has_high_cpmac(void)
+{
+        u16 chip_id = ar7_chip_id();
+        switch (chip_id) {
+        case AR7_CHIP_7100:
+        case AR7_CHIP_7200:
+                return 0;
+        case AR7_CHIP_7300:
+                return 1;
+        default:
+                return -ENXIO;
+        }
+}
+#define ar7_has_high_vlynq ar7_has_high_cpmac
+#define ar7_has_second_uart ar7_has_high_cpmac
+
+static inline void ar7_device_enable(u32 bit)
+{
+        void *reset_reg =
+                (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
+        writel(readl(reset_reg) | (1 << bit), reset_reg);
+        msleep(20);
+}
+
+static inline void ar7_device_disable(u32 bit)
+{
+        void *reset_reg =
+                (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
+        writel(readl(reset_reg) & ~(1 << bit), reset_reg);
+        msleep(20);
+}
+
+static inline void ar7_device_reset(u32 bit)
+{
+        ar7_device_disable(bit);
+        ar7_device_enable(bit);
+}
+
+static inline void ar7_device_on(u32 bit)
+{
+        void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
+        writel(readl(power_reg) | (1 << bit), power_reg);
+        msleep(20);
+}
+
+static inline void ar7_device_off(u32 bit)
+{
+        void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
+        writel(readl(power_reg) & ~(1 << bit), power_reg);
+        msleep(20);
+}
+
+int __init ar7_gpio_init(void);
+void __init ar7_init_clocks(void);
+
+/* Board specific GPIO functions */
+int ar7_gpio_enable(unsigned gpio);
+int ar7_gpio_disable(unsigned gpio);
+
+#endif /* __AR7_H__ */
diff --git a/arch/mips/include/asm/mach-ar7/irq.h b/arch/mips/include/asm/mach-ar7/irq.h
new file mode 100644
index 000000000..46bb730ea
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar7/irq.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Shamelessly copied from asm-mips/mach-emma2rh/
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_AR7_IRQ_H
+#define __ASM_AR7_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_AR7_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ar7/prom.h b/arch/mips/include/asm/mach-ar7/prom.h
new file mode 100644
index 000000000..9e1d20b06
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar7/prom.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
+ */
+
+#ifndef __PROM_H__
+#define __PROM_H__
+
+extern char *prom_getenv(const char *name);
+extern void prom_meminit(void);
+
+#endif /* __PROM_H__ */
diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h
new file mode 100644
index 000000000..a004d94df
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar7/spaces.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_AR7_SPACES_H
+#define _ASM_AR7_SPACES_H
+
+/*
+ * This handles the memory map.
+ * We handle pages at KSEG0 for kernels with 32 bit address space.
+ */
+#define PAGE_OFFSET     _AC(0x94000000, UL)
+#define PHYS_OFFSET     _AC(0x14000000, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_AR7_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ath25/ath25_platform.h b/arch/mips/include/asm/mach-ath25/ath25_platform.h
new file mode 100644
index 000000000..0aacc55aa
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_ATH25_PLATFORM_H
+#define __ASM_MACH_ATH25_PLATFORM_H
+
+#include <linux/etherdevice.h>
+
+/*
+ * This is board-specific data that is stored in a "fixed" location in flash.
+ * It is shared across operating systems, so it should not be changed lightly.
+ * The main reason we need it is in order to extract the ethernet MAC
+ * address(es).
+ */
+struct ath25_boarddata {
+        u32 magic;                   /* board data is valid */
+#define ATH25_BD_MAGIC 0x35333131    /* "5311", for all 531x/231x platforms */
+        u16 cksum;                   /* checksum (starting with BD_REV 2) */
+        u16 rev;                     /* revision of this struct */
+#define BD_REV 4
+        char board_name[64];         /* Name of board */
+        u16 major;                   /* Board major number */
+        u16 minor;                   /* Board minor number */
+        u32 flags;                   /* Board configuration */
+#define BD_ENET0        0x00000001   /* ENET0 is stuffed */
+#define BD_ENET1        0x00000002   /* ENET1 is stuffed */
+#define BD_UART1        0x00000004   /* UART1 is stuffed */
+#define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
+#define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
+#define BD_SYSLED       0x00000020   /* System LED stuffed */
+#define BD_EXTUARTCLK   0x00000040   /* External UART clock */
+#define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
+#define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
+#define BD_WLAN0        0x00000200   /* Enable WLAN0 */
+#define BD_MEMCAP       0x00000400   /* CAP SDRAM @ mem_cap for testing */
+#define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
+#define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
+#define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
+#define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
+#define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
+#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
+#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
+        u16 reset_config_gpio;       /* Reset factory GPIO pin */
+        u16 sys_led_gpio;            /* System LED GPIO pin */
+
+        u32 cpu_freq;                /* CPU core frequency in Hz */
+        u32 sys_freq;                /* System frequency in Hz */
+        u32 cnt_freq;                /* Calculated C0_COUNT frequency */
+
+        u8  wlan0_mac[ETH_ALEN];
+        u8  enet0_mac[ETH_ALEN];
+        u8  enet1_mac[ETH_ALEN];
+
+        u16 pci_id;                  /* Pseudo PCIID for common code */
+        u16 mem_cap;                 /* cap bank1 in MB */
+
+        /* version 3 */
+        u8  wlan1_mac[ETH_ALEN];     /* (ar5212) */
+};
+
+#define BOARD_CONFIG_BUFSZ              0x1000
+
+/*
+ * Platform device information for the Wireless MAC
+ */
+struct ar231x_board_config {
+        u16 devid;
+
+        /* board config data */
+        struct ath25_boarddata *config;
+
+        /* radio calibration data */
+        const char *radio;
+};
+
+#endif /* __ASM_MACH_ATH25_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
new file mode 100644
index 000000000..a54f20d95
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR231x/AR531x SoC specific CPU feature overrides
+ *
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_sb1_cache               0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_ejtag                   1
+
+#if !defined(CONFIG_SOC_AR5312)
+#  define cpu_has_llsc                  1
+#else
+/*
+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
+ * ll/sc instructions.
+ */
+#  define cpu_has_llsc                  0
+#endif
+
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+
+#define cpu_has_mips32r1                1
+
+#if !defined(CONFIG_SOC_AR5312)
+#  define cpu_has_mips32r2              1
+#endif
+
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_mipsmt                  0
+
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#define cpu_has_64bit_gp_regs           0
+
+#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
new file mode 100644
index 000000000..1f9e571af
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -0,0 +1,1321 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#define AR71XX_APB_BASE         0x18000000
+#define AR71XX_GE0_BASE         0x19000000
+#define AR71XX_GE0_SIZE         0x10000
+#define AR71XX_GE1_BASE         0x1a000000
+#define AR71XX_GE1_SIZE         0x10000
+#define AR71XX_EHCI_BASE        0x1b000000
+#define AR71XX_EHCI_SIZE        0x1000
+#define AR71XX_OHCI_BASE        0x1c000000
+#define AR71XX_OHCI_SIZE        0x1000
+#define AR71XX_SPI_BASE         0x1f000000
+#define AR71XX_SPI_SIZE         0x01000000
+
+#define AR71XX_DDR_CTRL_BASE    (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE    0x100
+#define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE        0x100
+#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE    0x100
+#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE        0x100
+#define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE         0x100
+#define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE       0x100
+#define AR71XX_MII_BASE         (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE         0x100
+
+#define AR71XX_PCI_MEM_BASE     0x10000000
+#define AR71XX_PCI_MEM_SIZE     0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS    0x10000000
+#define AR71XX_PCI_WIN1_OFFS    0x11000000
+#define AR71XX_PCI_WIN2_OFFS    0x12000000
+#define AR71XX_PCI_WIN3_OFFS    0x13000000
+#define AR71XX_PCI_WIN4_OFFS    0x14000000
+#define AR71XX_PCI_WIN5_OFFS    0x15000000
+#define AR71XX_PCI_WIN6_OFFS    0x16000000
+#define AR71XX_PCI_WIN7_OFFS    0x07000000
+
+#define AR71XX_PCI_CFG_BASE     \
+        (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE     0x100
+
+#define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE    0x100
+#define AR7240_OHCI_BASE        0x1b000000
+#define AR7240_OHCI_SIZE        0x1000
+
+#define AR724X_PCI_MEM_BASE     0x10000000
+#define AR724X_PCI_MEM_SIZE     0x04000000
+
+#define AR724X_PCI_CFG_BASE     0x14000000
+#define AR724X_PCI_CFG_SIZE     0x1000
+#define AR724X_PCI_CRP_BASE     (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE     0x1000
+#define AR724X_PCI_CTRL_BASE    (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE    0x100
+
+#define AR724X_EHCI_BASE        0x1b000000
+#define AR724X_EHCI_SIZE        0x1000
+
+#define AR913X_EHCI_BASE        0x1b000000
+#define AR913X_EHCI_SIZE        0x1000
+#define AR913X_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE        0x30000
+
+#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE        0x14
+#define AR933X_GMAC_BASE        (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE        0x04
+#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE        0x20000
+#define AR933X_EHCI_BASE        0x1b000000
+#define AR933X_EHCI_SIZE        0x1000
+
+#define AR934X_GMAC_BASE        (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE        0x14
+#define AR934X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE        0x20000
+#define AR934X_EHCI_BASE        0x1b000000
+#define AR934X_EHCI_SIZE        0x200
+#define AR934X_NFC_BASE         0x1b000200
+#define AR934X_NFC_SIZE         0xb8
+#define AR934X_SRIF_BASE        (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE        0x1000
+
+#define QCA953X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE       0x14
+#define QCA953X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE       0x20000
+#define QCA953X_EHCI_BASE       0x1b000000
+#define QCA953X_EHCI_SIZE       0x200
+#define QCA953X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE       0x1000
+
+#define QCA953X_PCI_CFG_BASE0   0x14000000
+#define QCA953X_PCI_CTRL_BASE0  (AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0   (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0   0x10000000
+#define QCA953X_PCI_MEM_SIZE    0x02000000
+
+#define QCA955X_PCI_MEM_BASE0   0x10000000
+#define QCA955X_PCI_MEM_BASE1   0x12000000
+#define QCA955X_PCI_MEM_SIZE    0x02000000
+#define QCA955X_PCI_CFG_BASE0   0x14000000
+#define QCA955X_PCI_CFG_BASE1   0x16000000
+#define QCA955X_PCI_CFG_SIZE    0x1000
+#define QCA955X_PCI_CRP_BASE0   (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1   (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE    0x1000
+#define QCA955X_PCI_CTRL_BASE0  (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1  (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE   0x100
+
+#define QCA955X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE       0x40
+#define QCA955X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE       0x20000
+#define QCA955X_EHCI0_BASE      0x1b000000
+#define QCA955X_EHCI1_BASE      0x1b400000
+#define QCA955X_EHCI_SIZE       0x1000
+#define QCA955X_NFC_BASE        0x1b800200
+#define QCA955X_NFC_SIZE        0xb8
+
+#define QCA956X_PCI_MEM_BASE1   0x12000000
+#define QCA956X_PCI_MEM_SIZE    0x02000000
+#define QCA956X_PCI_CFG_BASE1   0x16000000
+#define QCA956X_PCI_CFG_SIZE    0x1000
+#define QCA956X_PCI_CRP_BASE1   (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE    0x1000
+#define QCA956X_PCI_CTRL_BASE1  (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE   0x100
+
+#define QCA956X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE       0x20000
+#define QCA956X_EHCI0_BASE      0x1b000000
+#define QCA956X_EHCI1_BASE      0x1b400000
+#define QCA956X_EHCI_SIZE       0x200
+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SGMII_SIZE 0x64
+#define QCA956X_PLL_BASE        (AR71XX_APB_BASE + 0x00050000)
+#define QCA956X_PLL_SIZE        0x50
+#define QCA956X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE       0x64
+
+/*
+ * Hidden Registers
+ */
+#define QCA956X_MAC_CFG_BASE            0xb9000000
+#define QCA956X_MAC_CFG_SIZE            0x64
+
+#define QCA956X_MAC_CFG1_REG            0x00
+#define QCA956X_MAC_CFG1_SOFT_RST       BIT(31)
+#define QCA956X_MAC_CFG1_RX_RST         BIT(19)
+#define QCA956X_MAC_CFG1_TX_RST         BIT(18)
+#define QCA956X_MAC_CFG1_LOOPBACK       BIT(8)
+#define QCA956X_MAC_CFG1_RX_EN          BIT(2)
+#define QCA956X_MAC_CFG1_TX_EN          BIT(0)
+
+#define QCA956X_MAC_CFG2_REG            0x04
+#define QCA956X_MAC_CFG2_IF_1000        BIT(9)
+#define QCA956X_MAC_CFG2_IF_10_100      BIT(8)
+#define QCA956X_MAC_CFG2_HUGE_FRAME_EN  BIT(5)
+#define QCA956X_MAC_CFG2_LEN_CHECK      BIT(4)
+#define QCA956X_MAC_CFG2_PAD_CRC_EN     BIT(2)
+#define QCA956X_MAC_CFG2_FDX            BIT(0)
+
+#define QCA956X_MAC_MII_MGMT_CFG_REG    0x20
+#define QCA956X_MGMT_CFG_CLK_DIV_20     0x07
+
+#define QCA956X_MAC_FIFO_CFG0_REG       0x48
+#define QCA956X_MAC_FIFO_CFG1_REG       0x4c
+#define QCA956X_MAC_FIFO_CFG2_REG       0x50
+#define QCA956X_MAC_FIFO_CFG3_REG       0x54
+#define QCA956X_MAC_FIFO_CFG4_REG       0x58
+#define QCA956X_MAC_FIFO_CFG5_REG       0x5c
+
+#define QCA956X_DAM_RESET_OFFSET        0xb90001bc
+#define QCA956X_DAM_RESET_SIZE          0x4
+#define QCA956X_INLINE_CHKSUM_ENG       BIT(27)
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0         0x7c
+#define AR71XX_DDR_REG_PCI_WIN1         0x80
+#define AR71XX_DDR_REG_PCI_WIN2         0x84
+#define AR71XX_DDR_REG_PCI_WIN3         0x88
+#define AR71XX_DDR_REG_PCI_WIN4         0x8c
+#define AR71XX_DDR_REG_PCI_WIN5         0x90
+#define AR71XX_DDR_REG_PCI_WIN6         0x94
+#define AR71XX_DDR_REG_PCI_WIN7         0x98
+#define AR71XX_DDR_REG_FLUSH_GE0        0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1        0xa0
+#define AR71XX_DDR_REG_FLUSH_USB        0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI        0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0        0x7c
+#define AR724X_DDR_REG_FLUSH_GE1        0x80
+#define AR724X_DDR_REG_FLUSH_USB        0x84
+#define AR724X_DDR_REG_FLUSH_PCIE       0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0        0x7c
+#define AR913X_DDR_REG_FLUSH_GE1        0x80
+#define AR913X_DDR_REG_FLUSH_USB        0x84
+#define AR913X_DDR_REG_FLUSH_WMAC       0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0        0x7c
+#define AR933X_DDR_REG_FLUSH_GE1        0x80
+#define AR933X_DDR_REG_FLUSH_USB        0x84
+#define AR933X_DDR_REG_FLUSH_WMAC       0x88
+
+#define AR934X_DDR_REG_FLUSH_GE0        0x9c
+#define AR934X_DDR_REG_FLUSH_GE1        0xa0
+#define AR934X_DDR_REG_FLUSH_USB        0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE       0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC       0xac
+
+#define QCA953X_DDR_REG_FLUSH_GE0       0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1       0xa0
+#define QCA953X_DDR_REG_FLUSH_USB       0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE      0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC      0xac
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG       0x00
+#define AR71XX_PLL_REG_SEC_CONFIG       0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK   0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK   0x14
+
+#define AR71XX_PLL_FB_SHIFT             3
+#define AR71XX_PLL_FB_MASK              0x1f
+#define AR71XX_CPU_DIV_SHIFT            16
+#define AR71XX_CPU_DIV_MASK             0x3
+#define AR71XX_DDR_DIV_SHIFT            18
+#define AR71XX_DDR_DIV_MASK             0x3
+#define AR71XX_AHB_DIV_SHIFT            20
+#define AR71XX_AHB_DIV_MASK             0x7
+
+#define AR71XX_ETH0_PLL_SHIFT           17
+#define AR71XX_ETH1_PLL_SHIFT           19
+
+#define AR724X_PLL_REG_CPU_CONFIG       0x00
+#define AR724X_PLL_REG_PCIE_CONFIG      0x10
+
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS   BIT(16)
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET    BIT(25)
+
+#define AR724X_PLL_FB_SHIFT             0
+#define AR724X_PLL_FB_MASK              0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT        10
+#define AR724X_PLL_REF_DIV_MASK         0xf
+#define AR724X_AHB_DIV_SHIFT            19
+#define AR724X_AHB_DIV_MASK             0x1
+#define AR724X_DDR_DIV_SHIFT            22
+#define AR724X_DDR_DIV_MASK             0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK   0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG       0x00
+#define AR913X_PLL_REG_ETH_CONFIG       0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK   0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK   0x18
+
+#define AR913X_PLL_FB_SHIFT             0
+#define AR913X_PLL_FB_MASK              0x3ff
+#define AR913X_DDR_DIV_SHIFT            22
+#define AR913X_DDR_DIV_MASK             0x3
+#define AR913X_AHB_DIV_SHIFT            19
+#define AR913X_AHB_DIV_MASK             0x1
+
+#define AR913X_ETH0_PLL_SHIFT           20
+#define AR913X_ETH1_PLL_SHIFT           22
+
+#define AR933X_PLL_CPU_CONFIG_REG       0x00
+#define AR933X_PLL_CLOCK_CTRL_REG       0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG               0x00
+#define AR934X_PLL_DDR_CONFIG_REG               0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG         0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG     0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG         0x2c
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT       0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK        0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT        6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK         0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT      12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT      19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK       0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT       0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK        0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT        10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK         0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT      16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK       0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT      23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK       0x7
+
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS      BIT(2)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS      BIT(3)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS      BIT(4)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT  5
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK   0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT  10
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK   0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT  15
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK   0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL  BIT(20)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL  BIT(21)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL  BIT(24)
+
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL    BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG              0x00
+#define QCA953X_PLL_DDR_CONFIG_REG              0x04
+#define QCA953X_PLL_CLK_CTRL_REG                0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG    0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG        0x2c
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG       0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT       6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK        0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT     12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT     19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK      0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT      0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK       0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT       10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK        0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT     16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK      0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT     23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK      0x7
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+#define QCA955X_PLL_CPU_CONFIG_REG              0x00
+#define QCA955X_PLL_DDR_CONFIG_REG              0x04
+#define QCA955X_PLL_CLK_CTRL_REG                0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG        0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG       0x48
+#define QCA955X_PLL_ETH_SGMII_SERDES_REG        0x4c
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT       6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT     12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT     19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK      0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK       0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT       10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT     16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT     23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK      0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT        BIT(2)
+#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK         BIT(1)
+#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL             BIT(0)
+
+#define QCA956X_PLL_CPU_CONFIG_REG                      0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG                     0x04
+#define QCA956X_PLL_DDR_CONFIG_REG                      0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG                     0x0c
+#define QCA956X_PLL_CLK_CTRL_REG                        0x10
+#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG            0x28
+#define QCA956X_PLL_ETH_XMII_CONTROL_REG                0x30
+#define QCA956X_PLL_ETH_SGMII_SERDES_REG                0x4c
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT           0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK            0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT           5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK            0x1fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT              18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK               0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT           0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK            0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT           5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK            0x1fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT              18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK               0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL     BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL     BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB             BIT(5)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1          BIT(6)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL            BIT(7)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK  0xf
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP               BIT(12)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2          BIT(13)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1          BIT(14)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2          BIT(15)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE     BIT(16)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE               BIT(17)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL          BIT(18)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL            BIT(19)
+
+#define QCA956X_PLL_ETH_XMII_TX_INVERT                  BIT(1)
+#define QCA956X_PLL_ETH_XMII_GIGE                       BIT(25)
+#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT             28
+#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK              0x3
+#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT             26
+#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK              3
+
+#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT                BIT(2)
+#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                 BIT(1)
+#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL                     BIT(0)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ       0x00
+#define AR71XX_USB_CTRL_REG_CONFIG      0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER                  0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD           0x04
+#define AR71XX_RESET_REG_WDOG_CTRL              0x08
+#define AR71XX_RESET_REG_WDOG                   0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS        0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE        0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS         0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE         0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS      0x20
+#define AR71XX_RESET_REG_RESET_MODULE           0x24
+#define AR71XX_RESET_REG_PERFC_CTRL             0x2c
+#define AR71XX_RESET_REG_PERFC0                 0x30
+#define AR71XX_RESET_REG_PERFC1                 0x34
+#define AR71XX_RESET_REG_REV_ID                 0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS      0x18
+#define AR913X_RESET_REG_RESET_MODULE           0x1c
+#define AR913X_RESET_REG_PERF_CTRL              0x20
+#define AR913X_RESET_REG_PERFC0                 0x24
+#define AR913X_RESET_REG_PERFC1                 0x28
+
+#define AR724X_RESET_REG_RESET_MODULE           0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE           0x1c
+#define AR933X_RESET_REG_BOOTSTRAP              0xac
+
+#define AR934X_RESET_REG_RESET_MODULE           0x1c
+#define AR934X_RESET_REG_BOOTSTRAP              0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE          0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP             0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE          0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP             0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS        0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE          0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP             0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS        0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK  BIT(28)
+#define MISC_INT_ETHSW                  BIT(12)
+#define MISC_INT_TIMER4                 BIT(10)
+#define MISC_INT_TIMER3                 BIT(9)
+#define MISC_INT_TIMER2                 BIT(8)
+#define MISC_INT_DMA                    BIT(7)
+#define MISC_INT_OHCI                   BIT(6)
+#define MISC_INT_PERFC                  BIT(5)
+#define MISC_INT_WDOG                   BIT(4)
+#define MISC_INT_UART                   BIT(3)
+#define MISC_INT_GPIO                   BIT(2)
+#define MISC_INT_ERROR                  BIT(1)
+#define MISC_INT_TIMER                  BIT(0)
+
+#define AR71XX_RESET_EXTERNAL           BIT(28)
+#define AR71XX_RESET_FULL_CHIP          BIT(24)
+#define AR71XX_RESET_CPU_NMI            BIT(21)
+#define AR71XX_RESET_CPU_COLD           BIT(20)
+#define AR71XX_RESET_DMA                BIT(19)
+#define AR71XX_RESET_SLIC               BIT(18)
+#define AR71XX_RESET_STEREO             BIT(17)
+#define AR71XX_RESET_DDR                BIT(16)
+#define AR71XX_RESET_GE1_MAC            BIT(13)
+#define AR71XX_RESET_GE1_PHY            BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR71XX_RESET_GE0_MAC            BIT(9)
+#define AR71XX_RESET_GE0_PHY            BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL       BIT(6)
+#define AR71XX_RESET_USB_HOST           BIT(5)
+#define AR71XX_RESET_USB_PHY            BIT(4)
+#define AR71XX_RESET_PCI_BUS            BIT(1)
+#define AR71XX_RESET_PCI_CORE           BIT(0)
+
+#define AR7240_RESET_USB_HOST           BIT(5)
+#define AR7240_RESET_OHCI_DLL           BIT(3)
+
+#define AR724X_RESET_GE1_MDIO           BIT(23)
+#define AR724X_RESET_GE0_MDIO           BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
+#define AR724X_RESET_PCIE_PHY           BIT(7)
+#define AR724X_RESET_PCIE               BIT(6)
+#define AR724X_RESET_USB_HOST           BIT(5)
+#define AR724X_RESET_USB_PHY            BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC          BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR913X_RESET_USB_HOST           BIT(5)
+#define AR913X_RESET_USB_PHY            BIT(4)
+
+#define AR933X_RESET_GE1_MDIO           BIT(23)
+#define AR933X_RESET_GE0_MDIO           BIT(22)
+#define AR933X_RESET_GE1_MAC            BIT(13)
+#define AR933X_RESET_WMAC               BIT(11)
+#define AR933X_RESET_GE0_MAC            BIT(9)
+#define AR933X_RESET_USB_HOST           BIT(5)
+#define AR933X_RESET_USB_PHY            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
+
+#define AR934X_RESET_HOST               BIT(31)
+#define AR934X_RESET_SLIC               BIT(30)
+#define AR934X_RESET_HDMA               BIT(29)
+#define AR934X_RESET_EXTERNAL           BIT(28)
+#define AR934X_RESET_RTC                BIT(27)
+#define AR934X_RESET_PCIE_EP_INT        BIT(26)
+#define AR934X_RESET_CHKSUM_ACC         BIT(25)
+#define AR934X_RESET_FULL_CHIP          BIT(24)
+#define AR934X_RESET_GE1_MDIO           BIT(23)
+#define AR934X_RESET_GE0_MDIO           BIT(22)
+#define AR934X_RESET_CPU_NMI            BIT(21)
+#define AR934X_RESET_CPU_COLD           BIT(20)
+#define AR934X_RESET_HOST_RESET_INT     BIT(19)
+#define AR934X_RESET_PCIE_EP            BIT(18)
+#define AR934X_RESET_UART1              BIT(17)
+#define AR934X_RESET_DDR                BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF              BIT(14)
+#define AR934X_RESET_GE1_MAC            BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG  BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG     BIT(11)
+#define AR934X_RESET_HOST_DMA_INT       BIT(10)
+#define AR934X_RESET_GE0_MAC            BIT(9)
+#define AR934X_RESET_ETH_SWITCH         BIT(8)
+#define AR934X_RESET_PCIE_PHY           BIT(7)
+#define AR934X_RESET_PCIE               BIT(6)
+#define AR934X_RESET_USB_HOST           BIT(5)
+#define AR934X_RESET_USB_PHY            BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE    BIT(3)
+#define AR934X_RESET_LUT                BIT(2)
+#define AR934X_RESET_MBOX               BIT(1)
+#define AR934X_RESET_I2S                BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR       BIT(29)
+#define QCA953X_RESET_EXTERNAL          BIT(28)
+#define QCA953X_RESET_RTC               BIT(27)
+#define QCA953X_RESET_FULL_CHIP         BIT(24)
+#define QCA953X_RESET_GE1_MDIO          BIT(23)
+#define QCA953X_RESET_GE0_MDIO          BIT(22)
+#define QCA953X_RESET_CPU_NMI           BIT(21)
+#define QCA953X_RESET_CPU_COLD          BIT(20)
+#define QCA953X_RESET_DDR               BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA953X_RESET_GE1_MAC           BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG    BIT(11)
+#define QCA953X_RESET_GE0_MAC           BIT(9)
+#define QCA953X_RESET_ETH_SWITCH        BIT(8)
+#define QCA953X_RESET_PCIE_PHY          BIT(7)
+#define QCA953X_RESET_PCIE              BIT(6)
+#define QCA953X_RESET_USB_HOST          BIT(5)
+#define QCA953X_RESET_USB_PHY           BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE   BIT(3)
+
+#define QCA955X_RESET_HOST              BIT(31)
+#define QCA955X_RESET_SLIC              BIT(30)
+#define QCA955X_RESET_HDMA              BIT(29)
+#define QCA955X_RESET_EXTERNAL          BIT(28)
+#define QCA955X_RESET_RTC               BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT       BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC        BIT(25)
+#define QCA955X_RESET_FULL_CHIP         BIT(24)
+#define QCA955X_RESET_GE1_MDIO          BIT(23)
+#define QCA955X_RESET_GE0_MDIO          BIT(22)
+#define QCA955X_RESET_CPU_NMI           BIT(21)
+#define QCA955X_RESET_CPU_COLD          BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT    BIT(19)
+#define QCA955X_RESET_PCIE_EP           BIT(18)
+#define QCA955X_RESET_UART1             BIT(17)
+#define QCA955X_RESET_DDR               BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF             BIT(14)
+#define QCA955X_RESET_GE1_MAC           BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG      BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG    BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT      BIT(10)
+#define QCA955X_RESET_GE0_MAC           BIT(9)
+#define QCA955X_RESET_SGMII             BIT(8)
+#define QCA955X_RESET_PCIE_PHY          BIT(7)
+#define QCA955X_RESET_PCIE              BIT(6)
+#define QCA955X_RESET_USB_HOST          BIT(5)
+#define QCA955X_RESET_USB_PHY           BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE   BIT(3)
+#define QCA955X_RESET_LUT               BIT(2)
+#define QCA955X_RESET_MBOX              BIT(1)
+#define QCA955X_RESET_I2S               BIT(0)
+
+#define QCA956X_RESET_EXTERNAL          BIT(28)
+#define QCA956X_RESET_FULL_CHIP         BIT(24)
+#define QCA956X_RESET_GE1_MDIO          BIT(23)
+#define QCA956X_RESET_GE0_MDIO          BIT(22)
+#define QCA956X_RESET_CPU_NMI           BIT(21)
+#define QCA956X_RESET_CPU_COLD          BIT(20)
+#define QCA956X_RESET_DMA               BIT(19)
+#define QCA956X_RESET_DDR               BIT(16)
+#define QCA956X_RESET_GE1_MAC           BIT(13)
+#define QCA956X_RESET_SGMII_ANALOG      BIT(12)
+#define QCA956X_RESET_USB_PHY_ANALOG    BIT(11)
+#define QCA956X_RESET_GE0_MAC           BIT(9)
+#define QCA956X_RESET_SGMII             BIT(8)
+#define QCA956X_RESET_USB_HOST          BIT(5)
+#define QCA956X_RESET_USB_PHY           BIT(4)
+#define QCA956X_RESET_USBSUS_OVERRIDE   BIT(3)
+#define QCA956X_RESET_SWITCH_ANALOG     BIT(2)
+#define QCA956X_RESET_SWITCH            BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN   BIT(18)
+#define AR933X_BOOTSTRAP_EEPBUSY        BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40     BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8     BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7     BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6     BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5     BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4     BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3     BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2     BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1     BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC        BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE     BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40     BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI  BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1           BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2    BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1    BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE    BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40    BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1          BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40    BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40    BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC          BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX            BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP          BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP          BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC            BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0           BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1           BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2           BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3           BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+         AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP         BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC           BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0          BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1          BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2          BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3          BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+        (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+         QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+        (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+         QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+         QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC               BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX                 BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP               BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP               BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1                BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0           BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1           BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2           BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3           BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2                BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0           BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1           BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2           BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3           BIT(16)
+#define QCA955X_EXT_INT_USB1                    BIT(24)
+#define QCA955X_EXT_INT_USB2                    BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+        (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+         QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+        (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+        (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC               BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX                 BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP               BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP               BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1                BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0           BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1           BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2           BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3           BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2                BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0           BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1           BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2           BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3           BIT(16)
+#define QCA956X_EXT_INT_USB1                    BIT(24)
+#define QCA956X_EXT_INT_USB2                    BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+        (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+         QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+        (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+         QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+         QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+        (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+         QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+         QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK               0xfff0
+#define REV_ID_MAJOR_AR71XX             0x00a0
+#define REV_ID_MAJOR_AR913X             0x00b0
+#define REV_ID_MAJOR_AR7240             0x00c0
+#define REV_ID_MAJOR_AR7241             0x0100
+#define REV_ID_MAJOR_AR7242             0x1100
+#define REV_ID_MAJOR_AR9330             0x0110
+#define REV_ID_MAJOR_AR9331             0x1110
+#define REV_ID_MAJOR_AR9341             0x0120
+#define REV_ID_MAJOR_AR9342             0x1120
+#define REV_ID_MAJOR_AR9344             0x2120
+#define REV_ID_MAJOR_QCA9533            0x0140
+#define REV_ID_MAJOR_QCA9533_V2         0x0160
+#define REV_ID_MAJOR_QCA9556            0x0130
+#define REV_ID_MAJOR_QCA9558            0x1130
+#define REV_ID_MAJOR_TP9343             0x0150
+#define REV_ID_MAJOR_QCA956X            0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK        0x3
+#define AR71XX_REV_ID_MINOR_AR7130      0x0
+#define AR71XX_REV_ID_MINOR_AR7141      0x1
+#define AR71XX_REV_ID_MINOR_AR7161      0x2
+#define AR71XX_REV_ID_REVISION_MASK     0x3
+#define AR71XX_REV_ID_REVISION_SHIFT    2
+
+#define AR913X_REV_ID_MINOR_MASK        0x3
+#define AR913X_REV_ID_MINOR_AR9130      0x0
+#define AR913X_REV_ID_MINOR_AR9132      0x1
+#define AR913X_REV_ID_REVISION_MASK     0x3
+#define AR913X_REV_ID_REVISION_SHIFT    2
+
+#define AR933X_REV_ID_REVISION_MASK     0x3
+
+#define AR724X_REV_ID_REVISION_MASK     0x3
+
+#define AR934X_REV_ID_REVISION_MASK     0xf
+
+#define QCA953X_REV_ID_REVISION_MASK    0xf
+
+#define QCA955X_REV_ID_REVISION_MASK    0xf
+
+#define QCA956X_REV_ID_REVISION_MASK    0xf
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS       0x00    /* Function Select */
+#define AR71XX_SPI_REG_CTRL     0x04    /* SPI Control */
+#define AR71XX_SPI_REG_IOC      0x08    /* SPI I/O Control */
+#define AR71XX_SPI_REG_RDS      0x0c    /* Read Data Shift */
+
+#define AR71XX_SPI_FS_GPIO      BIT(0)  /* Enable GPIO mode */
+
+#define AR71XX_SPI_CTRL_RD      BIT(6)  /* Remap Disable */
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO       BIT(0)  /* Data Out pin */
+#define AR71XX_SPI_IOC_CLK      BIT(8)  /* CLK pin */
+#define AR71XX_SPI_IOC_CS(n)    BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0      AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1      AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2      AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL   (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
+                                 AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE              0x00
+#define AR71XX_GPIO_REG_IN              0x04
+#define AR71XX_GPIO_REG_OUT             0x08
+#define AR71XX_GPIO_REG_SET             0x0c
+#define AR71XX_GPIO_REG_CLEAR           0x10
+#define AR71XX_GPIO_REG_INT_MODE        0x14
+#define AR71XX_GPIO_REG_INT_TYPE        0x18
+#define AR71XX_GPIO_REG_INT_POLARITY    0x1c
+#define AR71XX_GPIO_REG_INT_PENDING     0x20
+#define AR71XX_GPIO_REG_INT_ENABLE      0x24
+#define AR71XX_GPIO_REG_FUNC            0x28
+
+#define AR934X_GPIO_REG_OUT_FUNC0       0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1       0x30
+#define AR934X_GPIO_REG_OUT_FUNC2       0x34
+#define AR934X_GPIO_REG_OUT_FUNC3       0x38
+#define AR934X_GPIO_REG_OUT_FUNC4       0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5       0x40
+#define AR934X_GPIO_REG_FUNC            0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0      0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1      0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2      0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3      0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4      0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0     0x44
+#define QCA953X_GPIO_REG_FUNC           0x6c
+
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1            10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2            11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0            9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK            8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI           12
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1          41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2          42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3          43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4          44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5          45
+
+#define QCA955X_GPIO_REG_OUT_FUNC0      0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1      0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2      0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3      0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4      0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5      0x40
+#define QCA955X_GPIO_REG_FUNC           0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0      0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1      0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2      0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3      0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4      0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5      0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0     0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3     0x50
+#define QCA956X_GPIO_REG_FUNC           0x6c
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO    32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC    33
+
+#define AR71XX_GPIO_COUNT               16
+#define AR7240_GPIO_COUNT               18
+#define AR7241_GPIO_COUNT               20
+#define AR913X_GPIO_COUNT               22
+#define AR933X_GPIO_COUNT               30
+#define AR934X_GPIO_COUNT               23
+#define QCA953X_GPIO_COUNT              18
+#define QCA955X_GPIO_COUNT              24
+#define QCA956X_GPIO_COUNT              23
+
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG       0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG       0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG       0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG       0x240
+#define AR934X_SRIF_DDR_DPLL2_REG       0x244
+#define AR934X_SRIF_DDR_DPLL3_REG       0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT  27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK   0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT    18
+#define AR934X_SRIF_DPLL1_NINT_MASK     0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK    0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL     BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT  13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK   0x7
+
+#define QCA953X_SRIF_CPU_DPLL1_REG      0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG      0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG      0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG      0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG      0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG      0x248
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK  0x1f
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT   18
+#define QCA953X_SRIF_DPLL1_NINT_MASK    0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK   0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL    BIT(30)
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK  0x7
+
+#define AR71XX_GPIO_FUNC_STEREO_EN              BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN                BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN             BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN             BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN                BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN              BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN             BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN         BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN                 BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2             BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1             BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN            BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN            BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN            BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN            BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN            BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN     BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN     BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN     BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN     BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN     BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN        BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN                BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE           BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN            BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN         BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN           BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN              BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN                BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN                BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN                BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN         BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN                BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN             BIT(4)
+
+#define AR933X_GPIO_FUNC_SPDIF2TCK              BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN               BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN          BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN             BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN                BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL    BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL    BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT     BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN                 BIT(18)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2             BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1             BIT(13)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN     BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN     BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN     BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN     BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN     BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN        BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN                BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE           BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN            BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN            BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN            BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN            BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN            BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN            BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN            BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN            BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE           BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO            0
+#define AR934X_GPIO_OUT_SPI_CS1 7
+#define AR934X_GPIO_OUT_LED_LINK0       41
+#define AR934X_GPIO_OUT_LED_LINK1       42
+#define AR934X_GPIO_OUT_LED_LINK2       43
+#define AR934X_GPIO_OUT_LED_LINK3       44
+#define AR934X_GPIO_OUT_LED_LINK4       45
+#define AR934X_GPIO_OUT_EXT_LNA0        46
+#define AR934X_GPIO_OUT_EXT_LNA1        47
+
+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN           BIT(9)
+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN           BIT(8)
+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN           BIT(7)
+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN           BIT(6)
+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN           BIT(5)
+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN           BIT(4)
+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN           BIT(3)
+#define QCA955X_GPIO_FUNC_JTAG_DISABLE          BIT(1)
+
+#define QCA955X_GPIO_OUT_GPIO           0
+#define QCA955X_MII_EXT_MDI             1
+#define QCA955X_SLIC_DATA_OUT           3
+#define QCA955X_SLIC_PCM_FS             4
+#define QCA955X_SLIC_PCM_CLK            5
+#define QCA955X_SPI_CLK                 8
+#define QCA955X_SPI_CS_0                9
+#define QCA955X_SPI_CS_1                10
+#define QCA955X_SPI_CS_2                11
+#define QCA955X_SPI_MISO                12
+#define QCA955X_I2S_CLK                 13
+#define QCA955X_I2S_WS                  14
+#define QCA955X_I2S_SD                  15
+#define QCA955X_I2S_MCK                 16
+#define QCA955X_SPDIF_OUT               17
+#define QCA955X_UART1_TD                18
+#define QCA955X_UART1_RTS               19
+#define QCA955X_UART1_RD                20
+#define QCA955X_UART1_CTS               21
+#define QCA955X_UART0_SOUT              22
+#define QCA955X_SPDIF2_OUT              23
+#define QCA955X_LED_SGMII_SPEED0        24
+#define QCA955X_LED_SGMII_SPEED1        25
+#define QCA955X_LED_SGMII_DUPLEX        26
+#define QCA955X_LED_SGMII_LINK_UP       27
+#define QCA955X_SGMII_SPEED0_INVERT     28
+#define QCA955X_SGMII_SPEED1_INVERT     29
+#define QCA955X_SGMII_DUPLEX_INVERT     30
+#define QCA955X_SGMII_LINK_UP_INVERT    31
+#define QCA955X_GE1_MII_MDO             32
+#define QCA955X_GE1_MII_MDC             33
+#define QCA955X_SWCOM2                  38
+#define QCA955X_SWCOM3                  39
+#define QCA955X_MAC2_GPIO               40
+#define QCA955X_MAC3_GPIO               41
+#define QCA955X_ATT_LED                 42
+#define QCA955X_PWR_LED                 43
+#define QCA955X_TX_FRAME                44
+#define QCA955X_RX_CLEAR_EXTERNAL       45
+#define QCA955X_LED_NETWORK_EN          46
+#define QCA955X_LED_POWER_EN            47
+#define QCA955X_WMAC_GLUE_WOW           68
+#define QCA955X_RX_CLEAR_EXTENSION      70
+#define QCA955X_CP_NAND_CS1             73
+#define QCA955X_USB_SUSPEND             74
+#define QCA955X_ETH_TX_ERR              75
+#define QCA955X_DDR_DQ_OE               76
+#define QCA955X_CLKREQ_N_EP             77
+#define QCA955X_CLKREQ_N_RC             78
+#define QCA955X_CLK_OBS0                79
+#define QCA955X_CLK_OBS1                80
+#define QCA955X_CLK_OBS2                81
+#define QCA955X_CLK_OBS3                82
+#define QCA955X_CLK_OBS4                83
+#define QCA955X_CLK_OBS5                84
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL        0x00
+#define AR71XX_MII_REG_MII1_CTRL        0x04
+
+#define AR71XX_MII_CTRL_IF_MASK         3
+#define AR71XX_MII_CTRL_SPEED_SHIFT     4
+#define AR71XX_MII_CTRL_SPEED_MASK      3
+#define AR71XX_MII_CTRL_SPEED_10        0
+#define AR71XX_MII_CTRL_SPEED_100       1
+#define AR71XX_MII_CTRL_SPEED_1000      2
+
+#define AR71XX_MII0_CTRL_IF_GMII        0
+#define AR71XX_MII0_CTRL_IF_MII         1
+#define AR71XX_MII0_CTRL_IF_RGMII       2
+#define AR71XX_MII0_CTRL_IF_RMII        3
+
+#define AR71XX_MII1_CTRL_IF_RGMII       0
+#define AR71XX_MII1_CTRL_IF_RMII        1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG         0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0        BIT(0)
+#define AR933X_ETH_CFG_MII_GE0          BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0         BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER   BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE    BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN   BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP      BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0         BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10  0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG         0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0      BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0        BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0       BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE  BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE     BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP      BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS    BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0       BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED   BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14
+#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG                0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE            BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP             BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS           BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG        0x00
+#define QCA955X_GMAC_REG_SGMII_SERDES   0x18
+
+#define QCA955X_ETH_CFG_RGMII_EN        BIT(0)
+#define QCA955X_ETH_CFG_MII_GE0         BIT(1)
+#define QCA955X_ETH_CFG_GMII_GE0        BIT(2)
+#define QCA955X_ETH_CFG_MII_GE0_MASTER  BIT(3)
+#define QCA955X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
+#define QCA955X_ETH_CFG_GE0_ERR_EN      BIT(5)
+#define QCA955X_ETH_CFG_GE0_SGMII       BIT(6)
+#define QCA955X_ETH_CFG_RMII_GE0        BIT(10)
+#define QCA955X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
+#define QCA955X_ETH_CFG_RXD_DELAY_MASK  0x3
+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define QCA955X_ETH_CFG_RDV_DELAY       BIT(16)
+#define QCA955X_ETH_CFG_RDV_DELAY_MASK  0x3
+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
+#define QCA955X_ETH_CFG_TXD_DELAY_MASK  0x3
+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
+#define QCA955X_ETH_CFG_TXE_DELAY_MASK  0x3
+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+/*
+ * QCA956X GMAC Interface
+ */
+
+#define QCA956X_GMAC_REG_ETH_CFG        0x00
+#define QCA956X_GMAC_REG_SGMII_RESET    0x14
+#define QCA956X_GMAC_REG_SGMII_SERDES   0x18
+#define QCA956X_GMAC_REG_MR_AN_CONTROL  0x1c
+#define QCA956X_GMAC_REG_SGMII_CONFIG   0x34
+#define QCA956X_GMAC_REG_SGMII_DEBUG    0x58
+
+#define QCA956X_ETH_CFG_RGMII_EN                BIT(0)
+#define QCA956X_ETH_CFG_GE0_SGMII               BIT(6)
+#define QCA956X_ETH_CFG_SW_ONLY_MODE            BIT(7)
+#define QCA956X_ETH_CFG_SW_PHY_SWAP             BIT(8)
+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(9)
+#define QCA956X_ETH_CFG_SW_APB_ACCESS           BIT(10)
+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
+#define QCA956X_ETH_CFG_RXD_DELAY_MASK          0x3
+#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT         14
+#define QCA956X_ETH_CFG_RDV_DELAY_MASK          0x3
+#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT         16
+
+#define QCA956X_SGMII_RESET_RX_CLK_N_RESET      0x0
+#define QCA956X_SGMII_RESET_RX_CLK_N            BIT(0)
+#define QCA956X_SGMII_RESET_TX_CLK_N            BIT(1)
+#define QCA956X_SGMII_RESET_RX_125M_N           BIT(2)
+#define QCA956X_SGMII_RESET_TX_125M_N           BIT(3)
+#define QCA956X_SGMII_RESET_HW_RX_125M_N        BIT(4)
+
+#define QCA956X_SGMII_SERDES_CDR_BW_MASK        0x3
+#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT       1
+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK    0x7
+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT   4
+#define QCA956X_SGMII_SERDES_PLL_BW             BIT(8)
+#define QCA956X_SGMII_SERDES_VCO_FAST           BIT(9)
+#define QCA956X_SGMII_SERDES_VCO_SLOW           BIT(10)
+#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT   BIT(16)
+#define QCA956X_SGMII_SERDES_FIBER_SDO          BIT(17)
+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT      27
+#define QCA956X_SGMII_SERDES_VCO_REG_MASK       0xf
+
+#define QCA956X_MR_AN_CONTROL_AN_ENABLE         BIT(12)
+#define QCA956X_MR_AN_CONTROL_PHY_RESET         BIT(15)
+
+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT    0
+#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK     0x7
+
+#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 000000000..cacf3545e
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR933X UART defines
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef __AR933X_UART_H
+#define __AR933X_UART_H
+
+#define AR933X_UART_REGS_SIZE           20
+#define AR933X_UART_FIFO_SIZE           16
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLOCK_REG           0x08
+#define AR933X_UART_INT_REG             0x0c
+#define AR933X_UART_INT_EN_REG          0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+
+#define AR933X_UART_CS_PARITY_S         0
+#define AR933X_UART_CS_PARITY_M         0x3
+#define   AR933X_UART_CS_PARITY_NONE    0
+#define   AR933X_UART_CS_PARITY_ODD     2
+#define   AR933X_UART_CS_PARITY_EVEN    3
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define   AR933X_UART_CS_IF_MODE_NONE   0
+#define   AR933X_UART_CS_IF_MODE_DTE    1
+#define   AR933X_UART_CS_IF_MODE_DCE    2
+#define AR933X_UART_CS_FLOW_CTRL_S      4
+#define AR933X_UART_CS_FLOW_CTRL_M      0x3
+#define AR933X_UART_CS_DMA_EN           BIT(6)
+#define AR933X_UART_CS_TX_READY_ORIDE   BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE   BIT(8)
+#define AR933X_UART_CS_TX_READY         BIT(9)
+#define AR933X_UART_CS_RX_BREAK         BIT(10)
+#define AR933X_UART_CS_TX_BREAK         BIT(11)
+#define AR933X_UART_CS_HOST_INT         BIT(12)
+#define AR933X_UART_CS_HOST_INT_EN      BIT(13)
+#define AR933X_UART_CS_TX_BUSY          BIT(14)
+#define AR933X_UART_CS_RX_BUSY          BIT(15)
+
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+#define AR933X_UART_CLOCK_SCALE_M       0xfff
+#define AR933X_UART_CLOCK_SCALE_S       16
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+
+#define AR933X_UART_INT_RX_VALID        BIT(0)
+#define AR933X_UART_INT_TX_READY        BIT(1)
+#define AR933X_UART_INT_RX_FRAMING_ERR  BIT(2)
+#define AR933X_UART_INT_RX_OFLOW_ERR    BIT(3)
+#define AR933X_UART_INT_TX_OFLOW_ERR    BIT(4)
+#define AR933X_UART_INT_RX_PARITY_ERR   BIT(5)
+#define AR933X_UART_INT_RX_BREAK_ON     BIT(6)
+#define AR933X_UART_INT_RX_BREAK_OFF    BIT(7)
+#define AR933X_UART_INT_RX_FULL         BIT(8)
+#define AR933X_UART_INT_TX_EMPTY        BIT(9)
+#define AR933X_UART_INT_ALLINTS         0x3ff
+
+#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
new file mode 100644
index 000000000..70cda7449
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+enum ath79_soc_type {
+        ATH79_SOC_UNKNOWN,
+        ATH79_SOC_AR7130,
+        ATH79_SOC_AR7141,
+        ATH79_SOC_AR7161,
+        ATH79_SOC_AR7240,
+        ATH79_SOC_AR7241,
+        ATH79_SOC_AR7242,
+        ATH79_SOC_AR9130,
+        ATH79_SOC_AR9132,
+        ATH79_SOC_AR9330,
+        ATH79_SOC_AR9331,
+        ATH79_SOC_AR9341,
+        ATH79_SOC_AR9342,
+        ATH79_SOC_AR9344,
+        ATH79_SOC_QCA9533,
+        ATH79_SOC_QCA9556,
+        ATH79_SOC_QCA9558,
+        ATH79_SOC_TP9343,
+        ATH79_SOC_QCA956X,
+};
+
+extern enum ath79_soc_type ath79_soc;
+extern unsigned int ath79_soc_rev;
+
+static inline int soc_is_ar71xx(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7130 ||
+                ath79_soc == ATH79_SOC_AR7141 ||
+                ath79_soc == ATH79_SOC_AR7161);
+}
+
+static inline int soc_is_ar724x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7240 ||
+                ath79_soc == ATH79_SOC_AR7241 ||
+                ath79_soc == ATH79_SOC_AR7242);
+}
+
+static inline int soc_is_ar7240(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7240);
+}
+
+static inline int soc_is_ar7241(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7241);
+}
+
+static inline int soc_is_ar7242(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7242);
+}
+
+static inline int soc_is_ar913x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9130 ||
+                ath79_soc == ATH79_SOC_AR9132);
+}
+
+static inline int soc_is_ar933x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9330 ||
+                ath79_soc == ATH79_SOC_AR9331);
+}
+
+static inline int soc_is_ar9341(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9341);
+}
+
+static inline int soc_is_ar9342(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9342);
+}
+
+static inline int soc_is_ar9344(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9344);
+}
+
+static inline int soc_is_ar934x(void)
+{
+        return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+        return ath79_soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+        return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+        return ath79_soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+        return ath79_soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+        return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+        return ath79_soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+        return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca9563(void)
+{
+        return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca956x(void)
+{
+        return soc_is_qca9561() || soc_is_qca9563();
+}
+
+void ath79_ddr_wb_flush(unsigned int reg);
+void ath79_ddr_set_pci_windows(void);
+
+extern void __iomem *ath79_pll_base;
+extern void __iomem *ath79_reset_base;
+
+static inline void ath79_pll_wr(unsigned reg, u32 val)
+{
+        __raw_writel(val, ath79_pll_base + reg);
+}
+
+static inline u32 ath79_pll_rr(unsigned reg)
+{
+        return __raw_readl(ath79_pll_base + reg);
+}
+
+static inline void ath79_reset_wr(unsigned reg, u32 val)
+{
+        __raw_writel(val, ath79_reset_base + reg);
+        (void) __raw_readl(ath79_reset_base + reg); /* flush */
+}
+
+static inline u32 ath79_reset_rr(unsigned reg)
+{
+        return __raw_readl(ath79_reset_base + reg);
+}
+
+void ath79_device_reset_set(u32 mask);
+void ath79_device_reset_clear(u32 mask);
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
new file mode 100644
index 000000000..79ab3ad9f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR71XX/AR724X/AR913X specific CPU feature overrides
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+#define cpu_has_rixi            0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      1
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+
+#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
new file mode 100644
index 000000000..882534be0
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ */
+#ifndef __ASM_MACH_ATH79_IRQ_H
+#define __ASM_MACH_ATH79_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE       0
+#define NR_IRQS                 51
+
+#define ATH79_CPU_IRQ(_x)       (MIPS_CPU_IRQ_BASE + (_x))
+
+#define ATH79_MISC_IRQ_BASE     8
+#define ATH79_MISC_IRQ_COUNT    32
+#define ATH79_MISC_IRQ(_x)      (ATH79_MISC_IRQ_BASE + (_x))
+
+#define ATH79_PCI_IRQ_BASE      (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
+#define ATH79_PCI_IRQ_COUNT     6
+#define ATH79_PCI_IRQ(_x)       (ATH79_PCI_IRQ_BASE + (_x))
+
+#define ATH79_IP2_IRQ_BASE      (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
+#define ATH79_IP2_IRQ_COUNT     2
+#define ATH79_IP2_IRQ(_x)       (ATH79_IP2_IRQ_BASE + (_x))
+
+#define ATH79_IP3_IRQ_BASE      (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
+#define ATH79_IP3_IRQ_COUNT     3
+#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
new file mode 100644
index 000000000..88db67bf4
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Atheros AR71XX/AR724X/AR913X specific kernel entry setup
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ */
+#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H
+#define __ASM_MACH_ATH79_KERNEL_ENTRY_H
+
+        /*
+         * Some bootloaders set the 'Kseg0 coherency algorithm' to
+         * 'Cacheable, noncoherent, write-through, no write allocate'
+         * and this cause performance issues. Let's go and change it to
+         * 'Cacheable, noncoherent, write-back, write allocate'
+         */
+        .macro  kernel_entry_setup
+        mfc0    t0, CP0_CONFIG
+        li      t1, ~CONF_CM_CMASK
+        and     t0, t1
+        ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+        mtc0    t0, CP0_CONFIG
+        nop
+        .endm
+
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
new file mode 100644
index 000000000..a7eec3364
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -0,0 +1,1211 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+ /*
+  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
+  */
+
+#ifndef _AU1000_H_
+#define _AU1000_H_
+
+/* SOC Interrupt numbers */
+/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
+#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
+#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
+#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
+
+/* Au1300-style (GPIC): 1 controller with up to 128 sources */
+#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define ALCHEMY_GPIC_INT_NUM    128
+#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
+
+/* common clock names, shared among all variants. AUXPLL2 is Au1300 */
+#define ALCHEMY_ROOT_CLK                "root_clk"
+#define ALCHEMY_CPU_CLK                 "cpu_clk"
+#define ALCHEMY_AUXPLL_CLK              "auxpll_clk"
+#define ALCHEMY_AUXPLL2_CLK             "auxpll2_clk"
+#define ALCHEMY_SYSBUS_CLK              "sysbus_clk"
+#define ALCHEMY_PERIPH_CLK              "periph_clk"
+#define ALCHEMY_MEM_CLK                 "mem_clk"
+#define ALCHEMY_LR_CLK                  "lr_clk"
+#define ALCHEMY_FG0_CLK                 "fg0_clk"
+#define ALCHEMY_FG1_CLK                 "fg1_clk"
+#define ALCHEMY_FG2_CLK                 "fg2_clk"
+#define ALCHEMY_FG3_CLK                 "fg3_clk"
+#define ALCHEMY_FG4_CLK                 "fg4_clk"
+#define ALCHEMY_FG5_CLK                 "fg5_clk"
+
+/* Au1300 peripheral interrupt numbers */
+#define AU1300_FIRST_INT        (ALCHEMY_GPIC_INT_BASE)
+#define AU1300_UART1_INT        (AU1300_FIRST_INT + 17)
+#define AU1300_UART2_INT        (AU1300_FIRST_INT + 25)
+#define AU1300_UART3_INT        (AU1300_FIRST_INT + 27)
+#define AU1300_SD1_INT          (AU1300_FIRST_INT + 32)
+#define AU1300_SD2_INT          (AU1300_FIRST_INT + 38)
+#define AU1300_PSC0_INT         (AU1300_FIRST_INT + 48)
+#define AU1300_PSC1_INT         (AU1300_FIRST_INT + 52)
+#define AU1300_PSC2_INT         (AU1300_FIRST_INT + 56)
+#define AU1300_PSC3_INT         (AU1300_FIRST_INT + 60)
+#define AU1300_NAND_INT         (AU1300_FIRST_INT + 62)
+#define AU1300_DDMA_INT         (AU1300_FIRST_INT + 75)
+#define AU1300_MMU_INT          (AU1300_FIRST_INT + 76)
+#define AU1300_MPU_INT          (AU1300_FIRST_INT + 77)
+#define AU1300_GPU_INT          (AU1300_FIRST_INT + 78)
+#define AU1300_UDMA_INT         (AU1300_FIRST_INT + 79)
+#define AU1300_TOY_INT          (AU1300_FIRST_INT + 80)
+#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)
+#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)
+#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)
+#define AU1300_RTC_INT          (AU1300_FIRST_INT + 84)
+#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)
+#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)
+#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)
+#define AU1300_UART0_INT        (AU1300_FIRST_INT + 88)
+#define AU1300_SD0_INT          (AU1300_FIRST_INT + 89)
+#define AU1300_USB_INT          (AU1300_FIRST_INT + 90)
+#define AU1300_LCD_INT          (AU1300_FIRST_INT + 91)
+#define AU1300_BSA_INT          (AU1300_FIRST_INT + 92)
+#define AU1300_MPE_INT          (AU1300_FIRST_INT + 93)
+#define AU1300_ITE_INT          (AU1300_FIRST_INT + 94)
+#define AU1300_AES_INT          (AU1300_FIRST_INT + 95)
+#define AU1300_CIM_INT          (AU1300_FIRST_INT + 96)
+
+/**********************************************************************/
+
+/*
+ * Physical base addresses for integrated peripherals
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
+ */
+
+#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1300_ROM_PHYS_ADDR            0x10000000 /* 5 */
+#define AU1300_OTP_PHYS_ADDR            0x10002000 /* 5 */
+#define AU1300_VSS_PHYS_ADDR            0x10003000 /* 5 */
+#define AU1300_UART0_PHYS_ADDR          0x10100000 /* 5 */
+#define AU1300_UART1_PHYS_ADDR          0x10101000 /* 5 */
+#define AU1300_UART2_PHYS_ADDR          0x10102000 /* 5 */
+#define AU1300_UART3_PHYS_ADDR          0x10103000 /* 5 */
+#define AU1000_USB_OHCI_PHYS_ADDR       0x10100000 /* 012 */
+#define AU1000_USB_UDC_PHYS_ADDR        0x10200000 /* 0123 */
+#define AU1300_GPIC_PHYS_ADDR           0x10200000 /* 5 */
+#define AU1000_IRDA_PHYS_ADDR           0x10300000 /* 02 */
+#define AU1200_AES_PHYS_ADDR            0x10300000 /* 45 */
+#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1300_GPU_PHYS_ADDR            0x10500000 /* 5 */
+#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
+#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
+#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 245 */
+#define AU1300_SD1_PHYS_ADDR            0x10601000 /* 5 */
+#define AU1300_SD2_PHYS_ADDR            0x10602000 /* 5 */
+#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1300_SYS_PHYS_ADDR            0x10900000 /* 5 */
+#define AU1550_PSC2_PHYS_ADDR           0x10A00000 /* 3 */
+#define AU1550_PSC3_PHYS_ADDR           0x10B00000 /* 3 */
+#define AU1300_PSC0_PHYS_ADDR           0x10A00000 /* 5 */
+#define AU1300_PSC1_PHYS_ADDR           0x10A01000 /* 5 */
+#define AU1300_PSC2_PHYS_ADDR           0x10A02000 /* 5 */
+#define AU1300_PSC3_PHYS_ADDR           0x10A03000 /* 5 */
+#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
+#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
+#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
+#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
+#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
+#define AU1200_SWCNT_PHYS_ADDR          0x1110010C /* 4 */
+#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
+#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
+#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
+#define AU1000_SSI0_PHYS_ADDR           0x11600000 /* 02 */
+#define AU1000_SSI1_PHYS_ADDR           0x11680000 /* 02 */
+#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
+#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 012345 */
+#define AU1550_PSC0_PHYS_ADDR           0x11A00000 /* 34 */
+#define AU1550_PSC1_PHYS_ADDR           0x11B00000 /* 34 */
+#define AU1000_MEM_PHYS_ADDR            0x14000000 /* 01234 */
+#define AU1000_STATIC_MEM_PHYS_ADDR     0x14001000 /* 01234 */
+#define AU1300_UDMA_PHYS_ADDR           0x14001800 /* 5 */
+#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 345 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 345 */
+#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
+#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
+#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 45 */
+#define AU1500_PCI_PHYS_ADDR            0x14005000 /* 13 */
+#define AU1550_PE_PHYS_ADDR             0x14008000 /* 3 */
+#define AU1200_MAEBE_PHYS_ADDR          0x14010000 /* 4 */
+#define AU1200_MAEFE_PHYS_ADDR          0x14012000 /* 4 */
+#define AU1300_MAEITE_PHYS_ADDR         0x14010000 /* 5 */
+#define AU1300_MAEMPE_PHYS_ADDR         0x14014000 /* 5 */
+#define AU1550_USB_OHCI_PHYS_ADDR       0x14020000 /* 3 */
+#define AU1200_USB_CTL_PHYS_ADDR        0x14020000 /* 4 */
+#define AU1200_USB_OTG_PHYS_ADDR        0x14020020 /* 4 */
+#define AU1200_USB_OHCI_PHYS_ADDR       0x14020100 /* 4 */
+#define AU1200_USB_EHCI_PHYS_ADDR       0x14020200 /* 4 */
+#define AU1200_USB_UDC_PHYS_ADDR        0x14022000 /* 4 */
+#define AU1300_USB_EHCI_PHYS_ADDR       0x14020000 /* 5 */
+#define AU1300_USB_OHCI0_PHYS_ADDR      0x14020400 /* 5 */
+#define AU1300_USB_OHCI1_PHYS_ADDR      0x14020800 /* 5 */
+#define AU1300_USB_CTL_PHYS_ADDR        0x14021000 /* 5 */
+#define AU1300_USB_OTG_PHYS_ADDR        0x14022000 /* 5 */
+#define AU1300_MAEBSA_PHYS_ADDR         0x14030000 /* 5 */
+#define AU1100_LCD_PHYS_ADDR            0x15000000 /* 2 */
+#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 45 */
+#define AU1500_PCI_MEM_PHYS_ADDR        0x400000000ULL /* 13 */
+#define AU1500_PCI_IO_PHYS_ADDR         0x500000000ULL /* 13 */
+#define AU1500_PCI_CONFIG0_PHYS_ADDR    0x600000000ULL /* 13 */
+#define AU1500_PCI_CONFIG1_PHYS_ADDR    0x680000000ULL /* 13 */
+#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 012345 */
+#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 012345 */
+#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 012345 */
+
+/**********************************************************************/
+
+
+/*
+ * Au1300 GPIO+INT controller (GPIC) register offsets and bits
+ * Registers are 128bits (0x10 bytes), divided into 4 "banks".
+ */
+#define AU1300_GPIC_PINVAL      0x0000
+#define AU1300_GPIC_PINVALCLR   0x0010
+#define AU1300_GPIC_IPEND       0x0020
+#define AU1300_GPIC_PRIENC      0x0030
+#define AU1300_GPIC_IEN         0x0040  /* int_mask in manual */
+#define AU1300_GPIC_IDIS        0x0050  /* int_maskclr in manual */
+#define AU1300_GPIC_DMASEL      0x0060
+#define AU1300_GPIC_DEVSEL      0x0080
+#define AU1300_GPIC_DEVCLR      0x0090
+#define AU1300_GPIC_RSTVAL      0x00a0
+/* pin configuration space. one 32bit register for up to 128 IRQs */
+#define AU1300_GPIC_PINCFG      0x1000
+
+#define GPIC_GPIO_TO_BIT(gpio)  \
+        (1 << ((gpio) & 0x1f))
+
+#define GPIC_GPIO_BANKOFF(gpio) \
+        (((gpio) >> 5) * 4)
+
+/* Pin Control bits: who owns the pin, what does it do */
+#define GPIC_CFG_PC_GPIN                0
+#define GPIC_CFG_PC_DEV                 1
+#define GPIC_CFG_PC_GPOLOW              2
+#define GPIC_CFG_PC_GPOHIGH             3
+#define GPIC_CFG_PC_MASK                3
+
+/* assign pin to MIPS IRQ line */
+#define GPIC_CFG_IL_SET(x)      (((x) & 3) << 2)
+#define GPIC_CFG_IL_MASK        (3 << 2)
+
+/* pin interrupt type setup */
+#define GPIC_CFG_IC_OFF         (0 << 4)
+#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)
+#define GPIC_CFG_IC_LEVEL_HIGH  (2 << 4)
+#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)
+#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)
+#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)
+#define GPIC_CFG_IC_MASK        (7 << 4)
+
+/* allow interrupt to wake cpu from 'wait' */
+#define GPIC_CFG_IDLEWAKE       (1 << 7)
+
+/***********************************************************************/
+
+/* Au1000 SDRAM memory controller register offsets */
+#define AU1000_MEM_SDMODE0              0x0000
+#define AU1000_MEM_SDMODE1              0x0004
+#define AU1000_MEM_SDMODE2              0x0008
+#define AU1000_MEM_SDADDR0              0x000C
+#define AU1000_MEM_SDADDR1              0x0010
+#define AU1000_MEM_SDADDR2              0x0014
+#define AU1000_MEM_SDREFCFG             0x0018
+#define AU1000_MEM_SDPRECMD             0x001C
+#define AU1000_MEM_SDAUTOREF            0x0020
+#define AU1000_MEM_SDWRMD0              0x0024
+#define AU1000_MEM_SDWRMD1              0x0028
+#define AU1000_MEM_SDWRMD2              0x002C
+#define AU1000_MEM_SDSLEEP              0x0030
+#define AU1000_MEM_SDSMCKE              0x0034
+
+/* MEM_SDMODE register content definitions */
+#define MEM_SDMODE_F            (1 << 22)
+#define MEM_SDMODE_SR           (1 << 21)
+#define MEM_SDMODE_BS           (1 << 20)
+#define MEM_SDMODE_RS           (3 << 18)
+#define MEM_SDMODE_CS           (7 << 15)
+#define MEM_SDMODE_TRAS         (15 << 11)
+#define MEM_SDMODE_TMRD         (3 << 9)
+#define MEM_SDMODE_TWR          (3 << 7)
+#define MEM_SDMODE_TRP          (3 << 5)
+#define MEM_SDMODE_TRCD         (3 << 3)
+#define MEM_SDMODE_TCL          (7 << 0)
+
+#define MEM_SDMODE_BS_2Bank     (0 << 20)
+#define MEM_SDMODE_BS_4Bank     (1 << 20)
+#define MEM_SDMODE_RS_11Row     (0 << 18)
+#define MEM_SDMODE_RS_12Row     (1 << 18)
+#define MEM_SDMODE_RS_13Row     (2 << 18)
+#define MEM_SDMODE_RS_N(N)      ((N) << 18)
+#define MEM_SDMODE_CS_7Col      (0 << 15)
+#define MEM_SDMODE_CS_8Col      (1 << 15)
+#define MEM_SDMODE_CS_9Col      (2 << 15)
+#define MEM_SDMODE_CS_10Col     (3 << 15)
+#define MEM_SDMODE_CS_11Col     (4 << 15)
+#define MEM_SDMODE_CS_N(N)      ((N) << 15)
+#define MEM_SDMODE_TRAS_N(N)    ((N) << 11)
+#define MEM_SDMODE_TMRD_N(N)    ((N) << 9)
+#define MEM_SDMODE_TWR_N(N)     ((N) << 7)
+#define MEM_SDMODE_TRP_N(N)     ((N) << 5)
+#define MEM_SDMODE_TRCD_N(N)    ((N) << 3)
+#define MEM_SDMODE_TCL_N(N)     ((N) << 0)
+
+/* MEM_SDADDR register contents definitions */
+#define MEM_SDADDR_E            (1 << 20)
+#define MEM_SDADDR_CSBA         (0x03FF << 10)
+#define MEM_SDADDR_CSMASK       (0x03FF << 0)
+#define MEM_SDADDR_CSBA_N(N)    ((N) & (0x03FF << 22) >> 12)
+#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF << 22) >> 22)
+
+/* MEM_SDREFCFG register content definitions */
+#define MEM_SDREFCFG_TRC        (15 << 28)
+#define MEM_SDREFCFG_TRPM       (3 << 26)
+#define MEM_SDREFCFG_E          (1 << 25)
+#define MEM_SDREFCFG_RE         (0x1ffffff << 0)
+#define MEM_SDREFCFG_TRC_N(N)   ((N) << MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N)  ((N) << MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)   (N)
+
+/* Au1550 SDRAM Register Offsets */
+#define AU1550_MEM_SDMODE0              0x0800
+#define AU1550_MEM_SDMODE1              0x0808
+#define AU1550_MEM_SDMODE2              0x0810
+#define AU1550_MEM_SDADDR0              0x0820
+#define AU1550_MEM_SDADDR1              0x0828
+#define AU1550_MEM_SDADDR2              0x0830
+#define AU1550_MEM_SDCONFIGA            0x0840
+#define AU1550_MEM_SDCONFIGB            0x0848
+#define AU1550_MEM_SDSTAT               0x0850
+#define AU1550_MEM_SDERRADDR            0x0858
+#define AU1550_MEM_SDSTRIDE0            0x0860
+#define AU1550_MEM_SDSTRIDE1            0x0868
+#define AU1550_MEM_SDSTRIDE2            0x0870
+#define AU1550_MEM_SDWRMD0              0x0880
+#define AU1550_MEM_SDWRMD1              0x0888
+#define AU1550_MEM_SDWRMD2              0x0890
+#define AU1550_MEM_SDPRECMD             0x08C0
+#define AU1550_MEM_SDAUTOREF            0x08C8
+#define AU1550_MEM_SDSREF               0x08D0
+#define AU1550_MEM_SDSLEEP              MEM_SDSREF
+
+/* Static Bus Controller register offsets */
+#define AU1000_MEM_STCFG0       0x000
+#define AU1000_MEM_STTIME0      0x004
+#define AU1000_MEM_STADDR0      0x008
+#define AU1000_MEM_STCFG1       0x010
+#define AU1000_MEM_STTIME1      0x014
+#define AU1000_MEM_STADDR1      0x018
+#define AU1000_MEM_STCFG2       0x020
+#define AU1000_MEM_STTIME2      0x024
+#define AU1000_MEM_STADDR2      0x028
+#define AU1000_MEM_STCFG3       0x030
+#define AU1000_MEM_STTIME3      0x034
+#define AU1000_MEM_STADDR3      0x038
+#define AU1000_MEM_STNDCTL      0x100
+#define AU1000_MEM_STSTAT       0x104
+
+#define MEM_STNAND_CMD          0x0
+#define MEM_STNAND_ADDR         0x4
+#define MEM_STNAND_DATA         0x20
+
+
+/* Programmable Counters 0 and 1 */
+#define AU1000_SYS_CNTRCTRL     0x14
+#  define SYS_CNTRL_E1S         (1 << 23)
+#  define SYS_CNTRL_T1S         (1 << 20)
+#  define SYS_CNTRL_M21         (1 << 19)
+#  define SYS_CNTRL_M11         (1 << 18)
+#  define SYS_CNTRL_M01         (1 << 17)
+#  define SYS_CNTRL_C1S         (1 << 16)
+#  define SYS_CNTRL_BP          (1 << 14)
+#  define SYS_CNTRL_EN1         (1 << 13)
+#  define SYS_CNTRL_BT1         (1 << 12)
+#  define SYS_CNTRL_EN0         (1 << 11)
+#  define SYS_CNTRL_BT0         (1 << 10)
+#  define SYS_CNTRL_E0          (1 << 8)
+#  define SYS_CNTRL_E0S         (1 << 7)
+#  define SYS_CNTRL_32S         (1 << 5)
+#  define SYS_CNTRL_T0S         (1 << 4)
+#  define SYS_CNTRL_M20         (1 << 3)
+#  define SYS_CNTRL_M10         (1 << 2)
+#  define SYS_CNTRL_M00         (1 << 1)
+#  define SYS_CNTRL_C0S         (1 << 0)
+
+/* Programmable Counter 0 Registers */
+#define AU1000_SYS_TOYTRIM      0x00
+#define AU1000_SYS_TOYWRITE     0x04
+#define AU1000_SYS_TOYMATCH0    0x08
+#define AU1000_SYS_TOYMATCH1    0x0c
+#define AU1000_SYS_TOYMATCH2    0x10
+#define AU1000_SYS_TOYREAD      0x40
+
+/* Programmable Counter 1 Registers */
+#define AU1000_SYS_RTCTRIM      0x44
+#define AU1000_SYS_RTCWRITE     0x48
+#define AU1000_SYS_RTCMATCH0    0x4c
+#define AU1000_SYS_RTCMATCH1    0x50
+#define AU1000_SYS_RTCMATCH2    0x54
+#define AU1000_SYS_RTCREAD      0x58
+
+
+/* GPIO */
+#define AU1000_SYS_PINFUNC      0x2C
+#  define SYS_PF_USB            (1 << 15)       /* 2nd USB device/host */
+#  define SYS_PF_U3             (1 << 14)       /* GPIO23/U3TXD */
+#  define SYS_PF_U2             (1 << 13)       /* GPIO22/U2TXD */
+#  define SYS_PF_U1             (1 << 12)       /* GPIO21/U1TXD */
+#  define SYS_PF_SRC            (1 << 11)       /* GPIO6/SROMCKE */
+#  define SYS_PF_CK5            (1 << 10)       /* GPIO3/CLK5 */
+#  define SYS_PF_CK4            (1 << 9)        /* GPIO2/CLK4 */
+#  define SYS_PF_IRF            (1 << 8)        /* GPIO15/IRFIRSEL */
+#  define SYS_PF_UR3            (1 << 7)        /* GPIO[14:9]/UART3 */
+#  define SYS_PF_I2D            (1 << 6)        /* GPIO8/I2SDI */
+#  define SYS_PF_I2S            (1 << 5)        /* I2S/GPIO[29:31] */
+#  define SYS_PF_NI2            (1 << 4)        /* NI2/GPIO[24:28] */
+#  define SYS_PF_U0             (1 << 3)        /* U0TXD/GPIO20 */
+#  define SYS_PF_RD             (1 << 2)        /* IRTXD/GPIO19 */
+#  define SYS_PF_A97            (1 << 1)        /* AC97/SSL1 */
+#  define SYS_PF_S0             (1 << 0)        /* SSI_0/GPIO[16:18] */
+
+/* Au1100 only */
+#  define SYS_PF_PC             (1 << 18)       /* PCMCIA/GPIO[207:204] */
+#  define SYS_PF_LCD            (1 << 17)       /* extern lcd/GPIO[203:200] */
+#  define SYS_PF_CS             (1 << 16)       /* EXTCLK0/32KHz to gpio2 */
+#  define SYS_PF_EX0            (1 << 9)        /* GPIO2/clock */
+
+/* Au1550 only.  Redefines lots of pins */
+#  define SYS_PF_PSC2_MASK      (7 << 17)
+#  define SYS_PF_PSC2_AC97      0
+#  define SYS_PF_PSC2_SPI       0
+#  define SYS_PF_PSC2_I2S       (1 << 17)
+#  define SYS_PF_PSC2_SMBUS     (3 << 17)
+#  define SYS_PF_PSC2_GPIO      (7 << 17)
+#  define SYS_PF_PSC3_MASK      (7 << 20)
+#  define SYS_PF_PSC3_AC97      0
+#  define SYS_PF_PSC3_SPI       0
+#  define SYS_PF_PSC3_I2S       (1 << 20)
+#  define SYS_PF_PSC3_SMBUS     (3 << 20)
+#  define SYS_PF_PSC3_GPIO      (7 << 20)
+#  define SYS_PF_PSC1_S1        (1 << 1)
+#  define SYS_PF_MUST_BE_SET    ((1 << 5) | (1 << 2))
+
+/* Au1200 only */
+#define SYS_PINFUNC_DMA         (1 << 31)
+#define SYS_PINFUNC_S0A         (1 << 30)
+#define SYS_PINFUNC_S1A         (1 << 29)
+#define SYS_PINFUNC_LP0         (1 << 28)
+#define SYS_PINFUNC_LP1         (1 << 27)
+#define SYS_PINFUNC_LD16        (1 << 26)
+#define SYS_PINFUNC_LD8         (1 << 25)
+#define SYS_PINFUNC_LD1         (1 << 24)
+#define SYS_PINFUNC_LD0         (1 << 23)
+#define SYS_PINFUNC_P1A         (3 << 21)
+#define SYS_PINFUNC_P1B         (1 << 20)
+#define SYS_PINFUNC_FS3         (1 << 19)
+#define SYS_PINFUNC_P0A         (3 << 17)
+#define SYS_PINFUNC_CS          (1 << 16)
+#define SYS_PINFUNC_CIM         (1 << 15)
+#define SYS_PINFUNC_P1C         (1 << 14)
+#define SYS_PINFUNC_U1T         (1 << 12)
+#define SYS_PINFUNC_U1R         (1 << 11)
+#define SYS_PINFUNC_EX1         (1 << 10)
+#define SYS_PINFUNC_EX0         (1 << 9)
+#define SYS_PINFUNC_U0R         (1 << 8)
+#define SYS_PINFUNC_MC          (1 << 7)
+#define SYS_PINFUNC_S0B         (1 << 6)
+#define SYS_PINFUNC_S0C         (1 << 5)
+#define SYS_PINFUNC_P0B         (1 << 4)
+#define SYS_PINFUNC_U0T         (1 << 3)
+#define SYS_PINFUNC_S1B         (1 << 2)
+
+/* Power Management */
+#define AU1000_SYS_SCRATCH0     0x18
+#define AU1000_SYS_SCRATCH1     0x1c
+#define AU1000_SYS_WAKEMSK      0x34
+#define AU1000_SYS_ENDIAN       0x38
+#define AU1000_SYS_POWERCTRL    0x3c
+#define AU1000_SYS_WAKESRC      0x5c
+#define AU1000_SYS_SLPPWR       0x78
+#define AU1000_SYS_SLEEP        0x7c
+
+#define SYS_WAKEMSK_D2          (1 << 9)
+#define SYS_WAKEMSK_M2          (1 << 8)
+#define SYS_WAKEMSK_GPIO(x)     (1 << (x))
+
+/* Clock Controller */
+#define AU1000_SYS_FREQCTRL0    0x20
+#define AU1000_SYS_FREQCTRL1    0x24
+#define AU1000_SYS_CLKSRC       0x28
+#define AU1000_SYS_CPUPLL       0x60
+#define AU1000_SYS_AUXPLL       0x64
+#define AU1300_SYS_AUXPLL2      0x68
+
+
+/**********************************************************************/
+
+
+/* The PCI chip selects are outside the 32bit space, and since we can't
+ * just program the 36bit addresses into BARs, we have to take a chunk
+ * out of the 32bit space and reserve it for PCI.  When these addresses
+ * are ioremap()ed, they'll be fixed up to the real 36bit address before
+ * being passed to the real ioremap function.
+ */
+#define ALCHEMY_PCI_MEMWIN_START        (AU1500_PCI_MEM_PHYS_ADDR >> 4)
+#define ALCHEMY_PCI_MEMWIN_END          (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
+
+/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
+ * adjust the device's resources.
+ */
+#define ALCHEMY_PCI_IOWIN_START         0x00001000
+#define ALCHEMY_PCI_IOWIN_END           0x0000FFFF
+
+#ifdef CONFIG_PCI
+
+#define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xfffffffffULL
+
+#else
+
+/* Don't allow any legacy ports probing */
+#define IOPORT_RESOURCE_START   0x10000000
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xfffffffffULL
+
+#endif
+
+/* PCI controller block register offsets */
+#define PCI_REG_CMEM            0x0000
+#define PCI_REG_CONFIG          0x0004
+#define PCI_REG_B2BMASK_CCH     0x0008
+#define PCI_REG_B2BBASE0_VID    0x000C
+#define PCI_REG_B2BBASE1_SID    0x0010
+#define PCI_REG_MWMASK_DEV      0x0014
+#define PCI_REG_MWBASE_REV_CCL  0x0018
+#define PCI_REG_ERR_ADDR        0x001C
+#define PCI_REG_SPEC_INTACK     0x0020
+#define PCI_REG_ID              0x0100
+#define PCI_REG_STATCMD         0x0104
+#define PCI_REG_CLASSREV        0x0108
+#define PCI_REG_PARAM           0x010C
+#define PCI_REG_MBAR            0x0110
+#define PCI_REG_TIMEOUT         0x0140
+
+/* PCI controller block register bits */
+#define PCI_CMEM_E              (1 << 28)       /* enable cacheable memory */
+#define PCI_CMEM_CMBASE(x)      (((x) & 0x3fff) << 14)
+#define PCI_CMEM_CMMASK(x)      ((x) & 0x3fff)
+#define PCI_CONFIG_ERD          (1 << 27) /* pci error during R/W */
+#define PCI_CONFIG_ET           (1 << 26) /* error in target mode */
+#define PCI_CONFIG_EF           (1 << 25) /* fatal error */
+#define PCI_CONFIG_EP           (1 << 24) /* parity error */
+#define PCI_CONFIG_EM           (1 << 23) /* multiple errors */
+#define PCI_CONFIG_BM           (1 << 22) /* bad master error */
+#define PCI_CONFIG_PD           (1 << 20) /* PCI Disable */
+#define PCI_CONFIG_BME          (1 << 19) /* Byte Mask Enable for reads */
+#define PCI_CONFIG_NC           (1 << 16) /* mark mem access non-coherent */
+#define PCI_CONFIG_IA           (1 << 15) /* INTA# enabled (target mode) */
+#define PCI_CONFIG_IP           (1 << 13) /* int on PCI_PERR# */
+#define PCI_CONFIG_IS           (1 << 12) /* int on PCI_SERR# */
+#define PCI_CONFIG_IMM          (1 << 11) /* int on master abort */
+#define PCI_CONFIG_ITM          (1 << 10) /* int on target abort (as master) */
+#define PCI_CONFIG_ITT          (1 << 9)  /* int on target abort (as target) */
+#define PCI_CONFIG_IPB          (1 << 8)  /* int on PERR# in bus master acc */
+#define PCI_CONFIG_SIC_NO       (0 << 6)  /* no byte mask changes */
+#define PCI_CONFIG_SIC_BA_ADR   (1 << 6)  /* on byte/hw acc, invert adr bits */
+#define PCI_CONFIG_SIC_HWA_DAT  (2 << 6)  /* on halfword acc, swap data */
+#define PCI_CONFIG_SIC_ALL      (3 << 6)  /* swap data bytes on all accesses */
+#define PCI_CONFIG_ST           (1 << 5)  /* swap data by target transactions */
+#define PCI_CONFIG_SM           (1 << 4)  /* swap data from PCI ctl */
+#define PCI_CONFIG_AEN          (1 << 3)  /* enable internal arbiter */
+#define PCI_CONFIG_R2H          (1 << 2)  /* REQ2# to hi-prio arbiter */
+#define PCI_CONFIG_R1H          (1 << 1)  /* REQ1# to hi-prio arbiter */
+#define PCI_CONFIG_CH           (1 << 0)  /* PCI ctl to hi-prio arbiter */
+#define PCI_B2BMASK_B2BMASK(x)  (((x) & 0xffff) << 16)
+#define PCI_B2BMASK_CCH(x)      ((x) & 0xffff) /* 16 upper bits of class code */
+#define PCI_B2BBASE0_VID_B0(x)  (((x) & 0xffff) << 16)
+#define PCI_B2BBASE0_VID_SV(x)  ((x) & 0xffff)
+#define PCI_B2BBASE1_SID_B1(x)  (((x) & 0xffff) << 16)
+#define PCI_B2BBASE1_SID_SI(x)  ((x) & 0xffff)
+#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
+#define PCI_MWMASKDEV_DEVID(x)  ((x) & 0xffff)
+#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
+#define PCI_MWBASEREVCCL_REV(x)  (((x) & 0xff) << 8)
+#define PCI_MWBASEREVCCL_CCL(x)  ((x) & 0xff)
+#define PCI_ID_DID(x)           (((x) & 0xffff) << 16)
+#define PCI_ID_VID(x)           ((x) & 0xffff)
+#define PCI_STATCMD_STATUS(x)   (((x) & 0xffff) << 16)
+#define PCI_STATCMD_CMD(x)      ((x) & 0xffff)
+#define PCI_CLASSREV_CLASS(x)   (((x) & 0x00ffffff) << 8)
+#define PCI_CLASSREV_REV(x)     ((x) & 0xff)
+#define PCI_PARAM_BIST(x)       (((x) & 0xff) << 24)
+#define PCI_PARAM_HT(x)         (((x) & 0xff) << 16)
+#define PCI_PARAM_LT(x)         (((x) & 0xff) << 8)
+#define PCI_PARAM_CLS(x)        ((x) & 0xff)
+#define PCI_TIMEOUT_RETRIES(x)  (((x) & 0xff) << 8)     /* max retries */
+#define PCI_TIMEOUT_TO(x)       ((x) & 0xff)    /* target ready timeout */
+
+
+/**********************************************************************/
+
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/cpu.h>
+
+/* helpers to access the SYS_* registers */
+static inline unsigned long alchemy_rdsys(int regofs)
+{
+        void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
+
+        return __raw_readl(b + regofs);
+}
+
+static inline void alchemy_wrsys(unsigned long v, int regofs)
+{
+        void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
+
+        __raw_writel(v, b + regofs);
+        wmb(); /* drain writebuffer */
+}
+
+/* helpers to access static memctrl registers */
+static inline unsigned long alchemy_rdsmem(int regofs)
+{
+        void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
+
+        return __raw_readl(b + regofs);
+}
+
+static inline void alchemy_wrsmem(unsigned long v, int regofs)
+{
+        void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
+
+        __raw_writel(v, b + regofs);
+        wmb(); /* drain writebuffer */
+}
+
+/* Early Au1000 have a write-only SYS_CPUPLL register. */
+static inline int au1xxx_cpu_has_pll_wo(void)
+{
+        switch (read_c0_prid()) {
+        case 0x00030100:        /* Au1000 DA */
+        case 0x00030201:        /* Au1000 HA */
+        case 0x00030202:        /* Au1000 HB */
+                return 1;
+        }
+        return 0;
+}
+
+/* does CPU need CONFIG[OD] set to fix tons of errata? */
+static inline int au1xxx_cpu_needs_config_od(void)
+{
+        /*
+         * c0_config.od (bit 19) was write only (and read as 0) on the
+         * early revisions of Alchemy SOCs.  It disables the bus trans-
+         * action overlapping and needs to be set to fix various errata.
+         */
+        switch (read_c0_prid()) {
+        case 0x00030100: /* Au1000 DA */
+        case 0x00030201: /* Au1000 HA */
+        case 0x00030202: /* Au1000 HB */
+        case 0x01030200: /* Au1500 AB */
+        /*
+         * Au1100/Au1200 errata actually keep silence about this bit,
+         * so we set it just in case for those revisions that require
+         * it to be set according to the (now gone) cpu_table.
+         */
+        case 0x02030200: /* Au1100 AB */
+        case 0x02030201: /* Au1100 BA */
+        case 0x02030202: /* Au1100 BC */
+        case 0x04030201: /* Au1200 AC */
+                return 1;
+        }
+        return 0;
+}
+
+#define ALCHEMY_CPU_UNKNOWN     -1
+#define ALCHEMY_CPU_AU1000      0
+#define ALCHEMY_CPU_AU1500      1
+#define ALCHEMY_CPU_AU1100      2
+#define ALCHEMY_CPU_AU1550      3
+#define ALCHEMY_CPU_AU1200      4
+#define ALCHEMY_CPU_AU1300      5
+
+static inline int alchemy_get_cputype(void)
+{
+        switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
+        case 0x00030000:
+                return ALCHEMY_CPU_AU1000;
+                break;
+        case 0x01030000:
+                return ALCHEMY_CPU_AU1500;
+                break;
+        case 0x02030000:
+                return ALCHEMY_CPU_AU1100;
+                break;
+        case 0x03030000:
+                return ALCHEMY_CPU_AU1550;
+                break;
+        case 0x04030000:
+        case 0x05030000:
+                return ALCHEMY_CPU_AU1200;
+                break;
+        case 0x800c0000:
+                return ALCHEMY_CPU_AU1300;
+                break;
+        }
+
+        return ALCHEMY_CPU_UNKNOWN;
+}
+
+/* return number of uarts on a given cputype */
+static inline int alchemy_get_uarts(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1300:
+                return 4;
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1200:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1550:
+                return 3;
+        }
+        return 0;
+}
+
+/* enable an UART block if it isn't already */
+static inline void alchemy_uart_enable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+
+        /* reset, enable clock, deassert reset */
+        if ((__raw_readl(addr + 0x100) & 3) != 3) {
+                __raw_writel(0, addr + 0x100);
+                wmb(); /* drain writebuffer */
+                __raw_writel(1, addr + 0x100);
+                wmb(); /* drain writebuffer */
+        }
+        __raw_writel(3, addr + 0x100);
+        wmb(); /* drain writebuffer */
+}
+
+static inline void alchemy_uart_disable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+
+        __raw_writel(0, addr + 0x100);  /* UART_MOD_CNTRL */
+        wmb(); /* drain writebuffer */
+}
+
+static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
+        int timeout, i;
+
+        /* check LSR TX_EMPTY bit */
+        timeout = 0xffffff;
+        do {
+                if (__raw_readl(base + 0x1c) & 0x20)
+                        break;
+                /* slow down */
+                for (i = 10000; i; i--)
+                        asm volatile ("nop");
+        } while (--timeout);
+
+        __raw_writel(c, base + 0x04);   /* tx */
+        wmb(); /* drain writebuffer */
+}
+
+/* return number of ethernet MACs on a given cputype */
+static inline int alchemy_get_macs(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1550:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+                return 1;
+        }
+        return 0;
+}
+
+/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
+void alchemy_sleep_au1000(void);
+void alchemy_sleep_au1550(void);
+void alchemy_sleep_au1300(void);
+void au_sleep(void);
+
+/* USB: arch/mips/alchemy/common/usb.c */
+enum alchemy_usb_block {
+        ALCHEMY_USB_OHCI0,
+        ALCHEMY_USB_UDC0,
+        ALCHEMY_USB_EHCI0,
+        ALCHEMY_USB_OTG0,
+        ALCHEMY_USB_OHCI1,
+};
+int alchemy_usb_control(int block, int enable);
+
+/* PCI controller platform data */
+struct alchemy_pci_platdata {
+        int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
+        int (*board_pci_idsel)(unsigned int devsel, int assert);
+        /* bits to set/clear in PCI_CONFIG register */
+        unsigned long pci_cfg_set;
+        unsigned long pci_cfg_clr;
+};
+
+/* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
+ * not used to select FIR/SIR mode on the transceiver but as a GPIO.
+ * Instead a CPLD has to be told about the mode.  The driver calls the
+ * set_phy_mode() function in addition to driving the IRFIRSEL pin.
+ */
+#define AU1000_IRDA_PHY_MODE_OFF        0
+#define AU1000_IRDA_PHY_MODE_SIR        1
+#define AU1000_IRDA_PHY_MODE_FIR        2
+
+struct au1k_irda_platform_data {
+        void (*set_phy_mode)(int mode);
+};
+
+
+/* Multifunction pins: Each of these pins can either be assigned to the
+ * GPIO controller or a on-chip peripheral.
+ * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
+ * assign one of these to either the GPIO controller or the device.
+ */
+enum au1300_multifunc_pins {
+        /* wake-from-str pins 0-3 */
+        AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
+        AU1300_PIN_WAKE3,
+        /* external clock sources for PSCs: 4-5 */
+        AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
+        /* 8bit MMC interface on SD0: 6-9 */
+        AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
+        AU1300_PIN_SD0DAT7,
+        /* aux clk input for freqgen 3: 10 */
+        AU1300_PIN_FG3AUX,
+        /* UART1 pins: 11-18 */
+        AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
+        AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
+        AU1300_PIN_U1RX, AU1300_PIN_U1TX,
+        /* UART0 pins: 19-24 */
+        AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
+        AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
+        /* UART2: 25-26 */
+        AU1300_PIN_U2RX, AU1300_PIN_U2TX,
+        /* UART3: 27-28 */
+        AU1300_PIN_U3RX, AU1300_PIN_U3TX,
+        /* LCD controller PWMs, ext pixclock: 29-31 */
+        AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
+        /* SD1 interface: 32-37 */
+        AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
+        AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
+        /* SD2 interface: 38-43 */
+        AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
+        AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
+        /* PSC0/1 clocks: 44-45 */
+        AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
+        /* PSCs: 46-49/50-53/54-57/58-61 */
+        AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
+        AU1300_PIN_PSC0D1,
+        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
+        AU1300_PIN_PSC1D1,
+        AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
+        AU1300_PIN_PSC2D1,
+        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
+        AU1300_PIN_PSC3D1,
+        /* PCMCIA interface: 62-70 */
+        AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
+        AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
+        AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
+        /* camera interface H/V sync inputs: 71-72 */
+        AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
+        /* PSC2/3 clocks: 73-74 */
+        AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
+};
+
+/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
+extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
+extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
+extern void au1300_set_irq_priority(unsigned int irq, int p);
+extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
+
+/* Au1300 allows to disconnect certain blocks from internal power supply */
+enum au1300_vss_block {
+        AU1300_VSS_MPE = 0,
+        AU1300_VSS_BSA,
+        AU1300_VSS_GPE,
+        AU1300_VSS_MGP,
+};
+
+extern void au1300_vss_block_control(int block, int enable);
+
+enum soc_au1000_ints {
+        AU1000_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1000_UART0_INT        = AU1000_FIRST_INT,
+        AU1000_UART1_INT,
+        AU1000_UART2_INT,
+        AU1000_UART3_INT,
+        AU1000_SSI0_INT,
+        AU1000_SSI1_INT,
+        AU1000_DMA_INT_BASE,
+
+        AU1000_TOY_INT          = AU1000_FIRST_INT + 14,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+        AU1000_IRDA_TX_INT,
+        AU1000_IRDA_RX_INT,
+        AU1000_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_SUS_INT,
+        AU1000_USB_HOST_INT,
+        AU1000_ACSYNC_INT,
+        AU1000_MAC0_DMA_INT,
+        AU1000_MAC1_DMA_INT,
+        AU1000_I2S_UO_INT,
+        AU1000_AC97C_INT,
+        AU1000_GPIO0_INT,
+        AU1000_GPIO1_INT,
+        AU1000_GPIO2_INT,
+        AU1000_GPIO3_INT,
+        AU1000_GPIO4_INT,
+        AU1000_GPIO5_INT,
+        AU1000_GPIO6_INT,
+        AU1000_GPIO7_INT,
+        AU1000_GPIO8_INT,
+        AU1000_GPIO9_INT,
+        AU1000_GPIO10_INT,
+        AU1000_GPIO11_INT,
+        AU1000_GPIO12_INT,
+        AU1000_GPIO13_INT,
+        AU1000_GPIO14_INT,
+        AU1000_GPIO15_INT,
+        AU1000_GPIO16_INT,
+        AU1000_GPIO17_INT,
+        AU1000_GPIO18_INT,
+        AU1000_GPIO19_INT,
+        AU1000_GPIO20_INT,
+        AU1000_GPIO21_INT,
+        AU1000_GPIO22_INT,
+        AU1000_GPIO23_INT,
+        AU1000_GPIO24_INT,
+        AU1000_GPIO25_INT,
+        AU1000_GPIO26_INT,
+        AU1000_GPIO27_INT,
+        AU1000_GPIO28_INT,
+        AU1000_GPIO29_INT,
+        AU1000_GPIO30_INT,
+        AU1000_GPIO31_INT,
+};
+
+enum soc_au1100_ints {
+        AU1100_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1100_UART0_INT        = AU1100_FIRST_INT,
+        AU1100_UART1_INT,
+        AU1100_SD_INT,
+        AU1100_UART3_INT,
+        AU1100_SSI0_INT,
+        AU1100_SSI1_INT,
+        AU1100_DMA_INT_BASE,
+
+        AU1100_TOY_INT          = AU1100_FIRST_INT + 14,
+        AU1100_TOY_MATCH0_INT,
+        AU1100_TOY_MATCH1_INT,
+        AU1100_TOY_MATCH2_INT,
+        AU1100_RTC_INT,
+        AU1100_RTC_MATCH0_INT,
+        AU1100_RTC_MATCH1_INT,
+        AU1100_RTC_MATCH2_INT,
+        AU1100_IRDA_TX_INT,
+        AU1100_IRDA_RX_INT,
+        AU1100_USB_DEV_REQ_INT,
+        AU1100_USB_DEV_SUS_INT,
+        AU1100_USB_HOST_INT,
+        AU1100_ACSYNC_INT,
+        AU1100_MAC0_DMA_INT,
+        AU1100_GPIO208_215_INT,
+        AU1100_LCD_INT,
+        AU1100_AC97C_INT,
+        AU1100_GPIO0_INT,
+        AU1100_GPIO1_INT,
+        AU1100_GPIO2_INT,
+        AU1100_GPIO3_INT,
+        AU1100_GPIO4_INT,
+        AU1100_GPIO5_INT,
+        AU1100_GPIO6_INT,
+        AU1100_GPIO7_INT,
+        AU1100_GPIO8_INT,
+        AU1100_GPIO9_INT,
+        AU1100_GPIO10_INT,
+        AU1100_GPIO11_INT,
+        AU1100_GPIO12_INT,
+        AU1100_GPIO13_INT,
+        AU1100_GPIO14_INT,
+        AU1100_GPIO15_INT,
+        AU1100_GPIO16_INT,
+        AU1100_GPIO17_INT,
+        AU1100_GPIO18_INT,
+        AU1100_GPIO19_INT,
+        AU1100_GPIO20_INT,
+        AU1100_GPIO21_INT,
+        AU1100_GPIO22_INT,
+        AU1100_GPIO23_INT,
+        AU1100_GPIO24_INT,
+        AU1100_GPIO25_INT,
+        AU1100_GPIO26_INT,
+        AU1100_GPIO27_INT,
+        AU1100_GPIO28_INT,
+        AU1100_GPIO29_INT,
+        AU1100_GPIO30_INT,
+        AU1100_GPIO31_INT,
+};
+
+enum soc_au1500_ints {
+        AU1500_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1500_UART0_INT        = AU1500_FIRST_INT,
+        AU1500_PCI_INTA,
+        AU1500_PCI_INTB,
+        AU1500_UART3_INT,
+        AU1500_PCI_INTC,
+        AU1500_PCI_INTD,
+        AU1500_DMA_INT_BASE,
+
+        AU1500_TOY_INT          = AU1500_FIRST_INT + 14,
+        AU1500_TOY_MATCH0_INT,
+        AU1500_TOY_MATCH1_INT,
+        AU1500_TOY_MATCH2_INT,
+        AU1500_RTC_INT,
+        AU1500_RTC_MATCH0_INT,
+        AU1500_RTC_MATCH1_INT,
+        AU1500_RTC_MATCH2_INT,
+        AU1500_PCI_ERR_INT,
+        AU1500_RESERVED_INT,
+        AU1500_USB_DEV_REQ_INT,
+        AU1500_USB_DEV_SUS_INT,
+        AU1500_USB_HOST_INT,
+        AU1500_ACSYNC_INT,
+        AU1500_MAC0_DMA_INT,
+        AU1500_MAC1_DMA_INT,
+        AU1500_AC97C_INT        = AU1500_FIRST_INT + 31,
+        AU1500_GPIO0_INT,
+        AU1500_GPIO1_INT,
+        AU1500_GPIO2_INT,
+        AU1500_GPIO3_INT,
+        AU1500_GPIO4_INT,
+        AU1500_GPIO5_INT,
+        AU1500_GPIO6_INT,
+        AU1500_GPIO7_INT,
+        AU1500_GPIO8_INT,
+        AU1500_GPIO9_INT,
+        AU1500_GPIO10_INT,
+        AU1500_GPIO11_INT,
+        AU1500_GPIO12_INT,
+        AU1500_GPIO13_INT,
+        AU1500_GPIO14_INT,
+        AU1500_GPIO15_INT,
+        AU1500_GPIO200_INT,
+        AU1500_GPIO201_INT,
+        AU1500_GPIO202_INT,
+        AU1500_GPIO203_INT,
+        AU1500_GPIO20_INT,
+        AU1500_GPIO204_INT,
+        AU1500_GPIO205_INT,
+        AU1500_GPIO23_INT,
+        AU1500_GPIO24_INT,
+        AU1500_GPIO25_INT,
+        AU1500_GPIO26_INT,
+        AU1500_GPIO27_INT,
+        AU1500_GPIO28_INT,
+        AU1500_GPIO206_INT,
+        AU1500_GPIO207_INT,
+        AU1500_GPIO208_215_INT,
+};
+
+enum soc_au1550_ints {
+        AU1550_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1550_UART0_INT        = AU1550_FIRST_INT,
+        AU1550_PCI_INTA,
+        AU1550_PCI_INTB,
+        AU1550_DDMA_INT,
+        AU1550_CRYPTO_INT,
+        AU1550_PCI_INTC,
+        AU1550_PCI_INTD,
+        AU1550_PCI_RST_INT,
+        AU1550_UART1_INT,
+        AU1550_UART3_INT,
+        AU1550_PSC0_INT,
+        AU1550_PSC1_INT,
+        AU1550_PSC2_INT,
+        AU1550_PSC3_INT,
+        AU1550_TOY_INT,
+        AU1550_TOY_MATCH0_INT,
+        AU1550_TOY_MATCH1_INT,
+        AU1550_TOY_MATCH2_INT,
+        AU1550_RTC_INT,
+        AU1550_RTC_MATCH0_INT,
+        AU1550_RTC_MATCH1_INT,
+        AU1550_RTC_MATCH2_INT,
+
+        AU1550_NAND_INT         = AU1550_FIRST_INT + 23,
+        AU1550_USB_DEV_REQ_INT,
+        AU1550_USB_DEV_SUS_INT,
+        AU1550_USB_HOST_INT,
+        AU1550_MAC0_DMA_INT,
+        AU1550_MAC1_DMA_INT,
+        AU1550_GPIO0_INT        = AU1550_FIRST_INT + 32,
+        AU1550_GPIO1_INT,
+        AU1550_GPIO2_INT,
+        AU1550_GPIO3_INT,
+        AU1550_GPIO4_INT,
+        AU1550_GPIO5_INT,
+        AU1550_GPIO6_INT,
+        AU1550_GPIO7_INT,
+        AU1550_GPIO8_INT,
+        AU1550_GPIO9_INT,
+        AU1550_GPIO10_INT,
+        AU1550_GPIO11_INT,
+        AU1550_GPIO12_INT,
+        AU1550_GPIO13_INT,
+        AU1550_GPIO14_INT,
+        AU1550_GPIO15_INT,
+        AU1550_GPIO200_INT,
+        AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
+        AU1550_GPIO16_INT,
+        AU1550_GPIO17_INT,
+        AU1550_GPIO20_INT,
+        AU1550_GPIO21_INT,
+        AU1550_GPIO22_INT,
+        AU1550_GPIO23_INT,
+        AU1550_GPIO24_INT,
+        AU1550_GPIO25_INT,
+        AU1550_GPIO26_INT,
+        AU1550_GPIO27_INT,
+        AU1550_GPIO28_INT,
+        AU1550_GPIO206_INT,
+        AU1550_GPIO207_INT,
+        AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
+};
+
+enum soc_au1200_ints {
+        AU1200_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1200_UART0_INT        = AU1200_FIRST_INT,
+        AU1200_SWT_INT,
+        AU1200_SD_INT,
+        AU1200_DDMA_INT,
+        AU1200_MAE_BE_INT,
+        AU1200_GPIO200_INT,
+        AU1200_GPIO201_INT,
+        AU1200_GPIO202_INT,
+        AU1200_UART1_INT,
+        AU1200_MAE_FE_INT,
+        AU1200_PSC0_INT,
+        AU1200_PSC1_INT,
+        AU1200_AES_INT,
+        AU1200_CAMERA_INT,
+        AU1200_TOY_INT,
+        AU1200_TOY_MATCH0_INT,
+        AU1200_TOY_MATCH1_INT,
+        AU1200_TOY_MATCH2_INT,
+        AU1200_RTC_INT,
+        AU1200_RTC_MATCH0_INT,
+        AU1200_RTC_MATCH1_INT,
+        AU1200_RTC_MATCH2_INT,
+        AU1200_GPIO203_INT,
+        AU1200_NAND_INT,
+        AU1200_GPIO204_INT,
+        AU1200_GPIO205_INT,
+        AU1200_GPIO206_INT,
+        AU1200_GPIO207_INT,
+        AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
+        AU1200_USB_INT,
+        AU1200_LCD_INT,
+        AU1200_MAE_BOTH_INT,
+        AU1200_GPIO0_INT,
+        AU1200_GPIO1_INT,
+        AU1200_GPIO2_INT,
+        AU1200_GPIO3_INT,
+        AU1200_GPIO4_INT,
+        AU1200_GPIO5_INT,
+        AU1200_GPIO6_INT,
+        AU1200_GPIO7_INT,
+        AU1200_GPIO8_INT,
+        AU1200_GPIO9_INT,
+        AU1200_GPIO10_INT,
+        AU1200_GPIO11_INT,
+        AU1200_GPIO12_INT,
+        AU1200_GPIO13_INT,
+        AU1200_GPIO14_INT,
+        AU1200_GPIO15_INT,
+        AU1200_GPIO16_INT,
+        AU1200_GPIO17_INT,
+        AU1200_GPIO18_INT,
+        AU1200_GPIO19_INT,
+        AU1200_GPIO20_INT,
+        AU1200_GPIO21_INT,
+        AU1200_GPIO22_INT,
+        AU1200_GPIO23_INT,
+        AU1200_GPIO24_INT,
+        AU1200_GPIO25_INT,
+        AU1200_GPIO26_INT,
+        AU1200_GPIO27_INT,
+        AU1200_GPIO28_INT,
+        AU1200_GPIO29_INT,
+        AU1200_GPIO30_INT,
+        AU1200_GPIO31_INT,
+};
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
new file mode 100644
index 000000000..0a0cd4270
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -0,0 +1,453 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using and allocating DMA channels on the Alchemy
+ *      Au1x00 MIPS processors.
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_AU1000_DMA_H
+#define __ASM_AU1000_DMA_H
+
+#include <linux/io.h>           /* need byte IO */
+#include <linux/spinlock.h>     /* And spinlocks */
+#include <linux/delay.h>
+
+#define NUM_AU1000_DMA_CHANNELS 8
+
+/* DMA Channel Register Offsets */
+#define DMA_MODE_SET            0x00000000
+#define DMA_MODE_READ           DMA_MODE_SET
+#define DMA_MODE_CLEAR          0x00000004
+/* DMA Mode register bits follow */
+#define DMA_DAH_MASK            (0x0f << 20)
+#define DMA_DID_BIT             16
+#define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
+#define DMA_DS                  (1 << 15)
+#define DMA_BE                  (1 << 13)
+#define DMA_DR                  (1 << 12)
+#define DMA_TS8                 (1 << 11)
+#define DMA_DW_BIT              9
+#define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
+#define DMA_DW8                 (0 << DMA_DW_BIT)
+#define DMA_DW16                (1 << DMA_DW_BIT)
+#define DMA_DW32                (2 << DMA_DW_BIT)
+#define DMA_NC                  (1 << 8)
+#define DMA_IE                  (1 << 7)
+#define DMA_HALT                (1 << 6)
+#define DMA_GO                  (1 << 5)
+#define DMA_AB                  (1 << 4)
+#define DMA_D1                  (1 << 3)
+#define DMA_BE1                 (1 << 2)
+#define DMA_D0                  (1 << 1)
+#define DMA_BE0                 (1 << 0)
+
+#define DMA_PERIPHERAL_ADDR     0x00000008
+#define DMA_BUFFER0_START       0x0000000C
+#define DMA_BUFFER1_START       0x00000014
+#define DMA_BUFFER0_COUNT       0x00000010
+#define DMA_BUFFER1_COUNT       0x00000018
+#define DMA_BAH_BIT     16
+#define DMA_BAH_MASK    (0x0f << DMA_BAH_BIT)
+#define DMA_COUNT_BIT   0
+#define DMA_COUNT_MASK  (0xffff << DMA_COUNT_BIT)
+
+/* DMA Device IDs follow */
+enum {
+        DMA_ID_UART0_TX = 0,
+        DMA_ID_UART0_RX,
+        DMA_ID_GP04,
+        DMA_ID_GP05,
+        DMA_ID_AC97C_TX,
+        DMA_ID_AC97C_RX,
+        DMA_ID_UART3_TX,
+        DMA_ID_UART3_RX,
+        DMA_ID_USBDEV_EP0_RX,
+        DMA_ID_USBDEV_EP0_TX,
+        DMA_ID_USBDEV_EP2_TX,
+        DMA_ID_USBDEV_EP3_TX,
+        DMA_ID_USBDEV_EP4_RX,
+        DMA_ID_USBDEV_EP5_RX,
+        DMA_ID_I2S_TX,
+        DMA_ID_I2S_RX,
+        DMA_NUM_DEV
+};
+
+/* DMA Device ID's for 2nd bank (AU1100) follow */
+enum {
+        DMA_ID_SD0_TX = 0,
+        DMA_ID_SD0_RX,
+        DMA_ID_SD1_TX,
+        DMA_ID_SD1_RX,
+        DMA_NUM_DEV_BANK2
+};
+
+struct dma_chan {
+        int dev_id;             /* this channel is allocated if >= 0, */
+                                /* free otherwise */
+        void __iomem *io;
+        const char *dev_str;
+        int irq;
+        void *irq_dev;
+        unsigned int fifo_addr;
+        unsigned int mode;
+};
+
+/* These are in arch/mips/au1000/common/dma.c */
+extern struct dma_chan au1000_dma_table[];
+extern int request_au1000_dma(int dev_id,
+                              const char *dev_str,
+                              irq_handler_t irqhandler,
+                              unsigned long irqflags,
+                              void *irq_dev_id);
+extern void free_au1000_dma(unsigned int dmanr);
+extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
+                                int length, int *eof, void *data);
+extern void dump_au1000_dma_channel(unsigned int dmanr);
+extern spinlock_t au1000_dma_spin_lock;
+
+static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
+{
+        if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
+            au1000_dma_table[dmanr].dev_id < 0)
+                return NULL;
+        return &au1000_dma_table[dmanr];
+}
+
+static inline unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&au1000_dma_spin_lock, flags);
+        return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
+}
+
+/*
+ * Set the DMA buffer enable bits in the mode register.
+ */
+static inline void enable_dma_buffer0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
+}
+
+static inline void enable_dma_buffer1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
+}
+static inline void enable_dma_buffers(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
+}
+
+static inline void start_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
+}
+
+#define DMA_HALT_POLL 0x5000
+
+static inline void halt_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        int i;
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
+
+        /* Poll the halt bit */
+        for (i = 0; i < DMA_HALT_POLL; i++)
+                if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
+                        break;
+        if (i == DMA_HALT_POLL)
+                printk(KERN_INFO "halt_dma: HALT poll expired!\n");
+}
+
+static inline void disable_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+
+        halt_dma(dmanr);
+
+        /* Now we can disable the buffers */
+        __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
+}
+
+static inline int dma_halted(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 1;
+        return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
+}
+
+/* Initialize a DMA channel. */
+static inline void init_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        u32 mode;
+
+        if (!chan)
+                return;
+
+        disable_dma(dmanr);
+
+        /* Set device FIFO address */
+        __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
+
+        mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
+        if (chan->irq)
+                mode |= DMA_IE;
+
+        __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(mode,       chan->io + DMA_MODE_SET);
+}
+
+/*
+ * Set mode for a specific DMA channel
+ */
+static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        /*
+         * set_dma_mode is only allowed to change endianess, direction,
+         * transfer size, device FIFO width, and coherency settings.
+         * Make sure anything else is masked off.
+         */
+        mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode |= mode;
+}
+
+static inline unsigned int get_dma_mode(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+        return chan->mode;
+}
+
+static inline int get_dma_active_buffer(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return -1;
+        return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
+}
+
+/*
+ * Set the device FIFO address for a specific DMA channel - only
+ * applicable to GPO4 and GPO5. All the other devices have fixed
+ * FIFO addresses.
+ */
+static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+
+        if (chan->mode & DMA_DS)        /* second bank of device IDs */
+                return;
+
+        if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
+                return;
+
+        __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
+}
+
+/*
+ * Clear the DMA buffer done bits in the mode register.
+ */
+static inline void clear_dma_done0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
+}
+
+static inline void clear_dma_done1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
+}
+
+/*
+ * This does nothing - not applicable to Au1000 DMA.
+ */
+static inline void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+/*
+ * Set Buffer 0 transfer address for specific DMA channel.
+ */
+static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(a, chan->io + DMA_BUFFER0_START);
+}
+
+/*
+ * Set Buffer 1 transfer address for specific DMA channel.
+ */
+static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        __raw_writel(a, chan->io + DMA_BUFFER1_START);
+}
+
+
+/*
+ * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
+}
+
+/*
+ * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
+        __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Returns which buffer has its done bit set in the mode register.
+ * Returns -1 if neither or both done bits set.
+ */
+static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+        return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
+}
+
+
+/*
+ * Returns the DMA channel's Buffer Done IRQ number.
+ */
+static inline int get_dma_done_irq(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return -1;
+        return chan->irq;
+}
+
+/*
+ * Get DMA residue count. Returns the number of _bytes_ left to transfer.
+ */
+static inline int get_dma_residue(unsigned int dmanr)
+{
+        int curBufCntReg, count;
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+
+        curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
+            DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
+
+        count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
+
+        if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
+                count <<= 1;
+        else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
+                count <<= 2;
+
+        return count;
+}
+
+#endif /* __ASM_AU1000_DMA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
new file mode 100644
index 000000000..cadab91ce
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -0,0 +1,210 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using the MMC/SD controllers on the
+ *      Alchemy Au1100 mips processor.
+ *
+ * Copyright (c) 2003 Embedded Edge, LLC.
+ * Author: Embedded Edge, LLC.
+ *              dan@embeddededge.com or tim@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+/*
+ * AU1100 MMC/SD definitions.
+ *
+ * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
+ *    June, 2003
+ */
+
+#ifndef __ASM_AU1100_MMC_H
+#define __ASM_AU1100_MMC_H
+
+#include <linux/leds.h>
+
+struct au1xmmc_platform_data {
+        int(*cd_setup)(void *mmc_host, int on);
+        int(*card_inserted)(void *mmc_host);
+        int(*card_readonly)(void *mmc_host);
+        void(*set_power)(void *mmc_host, int state);
+        struct led_classdev *led;
+        unsigned long mask_host_caps;
+};
+
+#define SD0_BASE        0xB0600000
+#define SD1_BASE        0xB0680000
+
+
+/*
+ *  Register offsets.
+ */
+#define SD_TXPORT       (0x0000)
+#define SD_RXPORT       (0x0004)
+#define SD_CONFIG       (0x0008)
+#define SD_ENABLE       (0x000C)
+#define SD_CONFIG2      (0x0010)
+#define SD_BLKSIZE      (0x0014)
+#define SD_STATUS       (0x0018)
+#define SD_DEBUG        (0x001C)
+#define SD_CMD          (0x0020)
+#define SD_CMDARG       (0x0024)
+#define SD_RESP3        (0x0028)
+#define SD_RESP2        (0x002C)
+#define SD_RESP1        (0x0030)
+#define SD_RESP0        (0x0034)
+#define SD_TIMEOUT      (0x0038)
+
+
+/*
+ *  SD_TXPORT bit definitions.
+ */
+#define SD_TXPORT_TXD   (0x000000ff)
+
+
+/*
+ *  SD_RXPORT bit definitions.
+ */
+#define SD_RXPORT_RXD   (0x000000ff)
+
+
+/*
+ *  SD_CONFIG bit definitions.
+ */
+#define SD_CONFIG_DIV   (0x000001ff)
+#define SD_CONFIG_DE    (0x00000200)
+#define SD_CONFIG_NE    (0x00000400)
+#define SD_CONFIG_TU    (0x00000800)
+#define SD_CONFIG_TO    (0x00001000)
+#define SD_CONFIG_RU    (0x00002000)
+#define SD_CONFIG_RO    (0x00004000)
+#define SD_CONFIG_I     (0x00008000)
+#define SD_CONFIG_CR    (0x00010000)
+#define SD_CONFIG_RAT   (0x00020000)
+#define SD_CONFIG_DD    (0x00040000)
+#define SD_CONFIG_DT    (0x00080000)
+#define SD_CONFIG_SC    (0x00100000)
+#define SD_CONFIG_RC    (0x00200000)
+#define SD_CONFIG_WC    (0x00400000)
+#define SD_CONFIG_xxx   (0x00800000)
+#define SD_CONFIG_TH    (0x01000000)
+#define SD_CONFIG_TE    (0x02000000)
+#define SD_CONFIG_TA    (0x04000000)
+#define SD_CONFIG_RH    (0x08000000)
+#define SD_CONFIG_RA    (0x10000000)
+#define SD_CONFIG_RF    (0x20000000)
+#define SD_CONFIG_CD    (0x40000000)
+#define SD_CONFIG_SI    (0x80000000)
+
+
+/*
+ *  SD_ENABLE bit definitions.
+ */
+#define SD_ENABLE_CE    (0x00000001)
+#define SD_ENABLE_R     (0x00000002)
+
+
+/*
+ *  SD_CONFIG2 bit definitions.
+ */
+#define SD_CONFIG2_EN   (0x00000001)
+#define SD_CONFIG2_FF   (0x00000002)
+#define SD_CONFIG2_xx1  (0x00000004)
+#define SD_CONFIG2_DF   (0x00000008)
+#define SD_CONFIG2_DC   (0x00000010)
+#define SD_CONFIG2_xx2  (0x000000e0)
+#define SD_CONFIG2_BB   (0x00000080)
+#define SD_CONFIG2_WB   (0x00000100)
+#define SD_CONFIG2_RW   (0x00000200)
+#define SD_CONFIG2_DP   (0x00000400)
+
+
+/*
+ *  SD_BLKSIZE bit definitions.
+ */
+#define SD_BLKSIZE_BS   (0x000007ff)
+#define SD_BLKSIZE_BS_SHIFT      (0)
+#define SD_BLKSIZE_BC   (0x01ff0000)
+#define SD_BLKSIZE_BC_SHIFT     (16)
+
+
+/*
+ *  SD_STATUS bit definitions.
+ */
+#define SD_STATUS_DCRCW (0x00000007)
+#define SD_STATUS_xx1   (0x00000008)
+#define SD_STATUS_CB    (0x00000010)
+#define SD_STATUS_DB    (0x00000020)
+#define SD_STATUS_CF    (0x00000040)
+#define SD_STATUS_D3    (0x00000080)
+#define SD_STATUS_xx2   (0x00000300)
+#define SD_STATUS_NE    (0x00000400)
+#define SD_STATUS_TU    (0x00000800)
+#define SD_STATUS_TO    (0x00001000)
+#define SD_STATUS_RU    (0x00002000)
+#define SD_STATUS_RO    (0x00004000)
+#define SD_STATUS_I     (0x00008000)
+#define SD_STATUS_CR    (0x00010000)
+#define SD_STATUS_RAT   (0x00020000)
+#define SD_STATUS_DD    (0x00040000)
+#define SD_STATUS_DT    (0x00080000)
+#define SD_STATUS_SC    (0x00100000)
+#define SD_STATUS_RC    (0x00200000)
+#define SD_STATUS_WC    (0x00400000)
+#define SD_STATUS_xx3   (0x00800000)
+#define SD_STATUS_TH    (0x01000000)
+#define SD_STATUS_TE    (0x02000000)
+#define SD_STATUS_TA    (0x04000000)
+#define SD_STATUS_RH    (0x08000000)
+#define SD_STATUS_RA    (0x10000000)
+#define SD_STATUS_RF    (0x20000000)
+#define SD_STATUS_CD    (0x40000000)
+#define SD_STATUS_SI    (0x80000000)
+
+
+/*
+ *  SD_CMD bit definitions.
+ */
+#define SD_CMD_GO       (0x00000001)
+#define SD_CMD_RY       (0x00000002)
+#define SD_CMD_xx1      (0x0000000c)
+#define SD_CMD_CT_MASK  (0x000000f0)
+#define SD_CMD_CT_0     (0x00000000)
+#define SD_CMD_CT_1     (0x00000010)
+#define SD_CMD_CT_2     (0x00000020)
+#define SD_CMD_CT_3     (0x00000030)
+#define SD_CMD_CT_4     (0x00000040)
+#define SD_CMD_CT_5     (0x00000050)
+#define SD_CMD_CT_6     (0x00000060)
+#define SD_CMD_CT_7     (0x00000070)
+#define SD_CMD_CI       (0x0000ff00)
+#define SD_CMD_CI_SHIFT         (8)
+#define SD_CMD_RT_MASK  (0x00ff0000)
+#define SD_CMD_RT_0     (0x00000000)
+#define SD_CMD_RT_1     (0x00010000)
+#define SD_CMD_RT_2     (0x00020000)
+#define SD_CMD_RT_3     (0x00030000)
+#define SD_CMD_RT_4     (0x00040000)
+#define SD_CMD_RT_5     (0x00050000)
+#define SD_CMD_RT_6     (0x00060000)
+#define SD_CMD_RT_1B    (0x00810000)
+
+
+#endif /* __ASM_AU1100_MMC_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000..e0e98f06c
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * platform data for au1200fb driver.
+ */
+
+#ifndef _AU1200FB_PLAT_H_
+#define _AU1200FB_PLAT_H_
+
+struct au1200fb_platdata {
+        int (*panel_index)(void);
+        int (*panel_init)(void);
+        int (*panel_shutdown)(void);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550_spi.h b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
new file mode 100644
index 000000000..fe6ca4606
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
+ */
+
+#ifndef _AU1550_SPI_H_
+#define _AU1550_SPI_H_
+
+struct au1550_spi_info {
+        u32 mainclk_hz;         /* main input clock frequency of PSC */
+        u16 num_chipselect;     /* number of chipselects supported */
+        void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+        void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000..d26dc1dad
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * platform data for the Au1550 NAND driver
+ */
+
+#ifndef _AU1550ND_H_
+#define _AU1550ND_H_
+
+#include <linux/mtd/partitions.h>
+
+struct au1550nd_platdata {
+        struct mtd_partition *parts;
+        int num_parts;
+        int devwidth;   /* 0 = 8bit device, 1 = 16bit device */
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
new file mode 100644
index 000000000..456ddba15
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -0,0 +1,388 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1550 Descriptor
+ *      Based DMA Controller.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Specifics for the Au1xxx Descriptor-Based DMA Controller,
+ * first seen in the AU1550 part.
+ */
+#ifndef _AU1000_DBDMA_H_
+#define _AU1000_DBDMA_H_
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+typedef volatile struct dbdma_global {
+        u32     ddma_config;
+        u32     ddma_intstat;
+        u32     ddma_throttle;
+        u32     ddma_inten;
+} dbdma_global_t;
+
+/* General Configuration. */
+#define DDMA_CONFIG_AF          (1 << 2)
+#define DDMA_CONFIG_AH          (1 << 1)
+#define DDMA_CONFIG_AL          (1 << 0)
+
+#define DDMA_THROTTLE_EN        (1 << 31)
+
+/* The structure of a DMA Channel. */
+typedef volatile struct au1xxx_dma_channel {
+        u32     ddma_cfg;       /* See below */
+        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
+        u32     ddma_statptr;   /* word aligned pointer to status word */
+        u32     ddma_dbell;     /* A write activates channel operation */
+        u32     ddma_irq;       /* If bit 0 set, interrupt pending */
+        u32     ddma_stat;      /* See below */
+        u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
+        /* Remainder, up to the 256 byte boundary, is reserved. */
+} au1x_dma_chan_t;
+
+#define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
+#define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
+#define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
+#define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
+#define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
+#define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
+#define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
+#define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
+#define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
+#define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
+
+/*
+ * Always set when descriptor processing done, regardless of
+ * interrupt enable state.  Reflected in global intstat, don't
+ * clear this until global intstat is read/used.
+ */
+#define DDMA_IRQ_IN     (1 << 0)
+
+#define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
+#define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
+#define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
+
+/*
+ * "Standard" DDMA Descriptor.
+ * Must be 32-byte aligned.
+ */
+typedef volatile struct au1xxx_ddma_desc {
+        u32     dscr_cmd0;              /* See below */
+        u32     dscr_cmd1;              /* See below */
+        u32     dscr_source0;           /* source phys address */
+        u32     dscr_source1;           /* See below */
+        u32     dscr_dest0;             /* Destination address */
+        u32     dscr_dest1;             /* See below */
+        u32     dscr_stat;              /* completion status */
+        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+        /*
+         * First 32 bytes are HW specific!!!
+         * Let's have some SW data following -- make sure it's 32 bytes.
+         */
+        u32     sw_status;
+        u32     sw_context;
+        u32     sw_reserved[6];
+} au1x_ddma_desc_t;
+
+#define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
+#define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
+#define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
+#define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
+#define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
+#define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
+#define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
+#define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
+#define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
+#define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
+#define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
+#define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
+#define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
+#define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
+#define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
+
+#define SW_STATUS_INUSE         (1 << 0)
+
+/* Command 0 device IDs. */
+#define AU1550_DSCR_CMD0_UART0_TX       0
+#define AU1550_DSCR_CMD0_UART0_RX       1
+#define AU1550_DSCR_CMD0_UART3_TX       2
+#define AU1550_DSCR_CMD0_UART3_RX       3
+#define AU1550_DSCR_CMD0_DMA_REQ0       4
+#define AU1550_DSCR_CMD0_DMA_REQ1       5
+#define AU1550_DSCR_CMD0_DMA_REQ2       6
+#define AU1550_DSCR_CMD0_DMA_REQ3       7
+#define AU1550_DSCR_CMD0_USBDEV_RX0     8
+#define AU1550_DSCR_CMD0_USBDEV_TX0     9
+#define AU1550_DSCR_CMD0_USBDEV_TX1     10
+#define AU1550_DSCR_CMD0_USBDEV_TX2     11
+#define AU1550_DSCR_CMD0_USBDEV_RX3     12
+#define AU1550_DSCR_CMD0_USBDEV_RX4     13
+#define AU1550_DSCR_CMD0_PSC0_TX        14
+#define AU1550_DSCR_CMD0_PSC0_RX        15
+#define AU1550_DSCR_CMD0_PSC1_TX        16
+#define AU1550_DSCR_CMD0_PSC1_RX        17
+#define AU1550_DSCR_CMD0_PSC2_TX        18
+#define AU1550_DSCR_CMD0_PSC2_RX        19
+#define AU1550_DSCR_CMD0_PSC3_TX        20
+#define AU1550_DSCR_CMD0_PSC3_RX        21
+#define AU1550_DSCR_CMD0_PCI_WRITE      22
+#define AU1550_DSCR_CMD0_NAND_FLASH     23
+#define AU1550_DSCR_CMD0_MAC0_RX        24
+#define AU1550_DSCR_CMD0_MAC0_TX        25
+#define AU1550_DSCR_CMD0_MAC1_RX        26
+#define AU1550_DSCR_CMD0_MAC1_TX        27
+
+#define AU1200_DSCR_CMD0_UART0_TX       0
+#define AU1200_DSCR_CMD0_UART0_RX       1
+#define AU1200_DSCR_CMD0_UART1_TX       2
+#define AU1200_DSCR_CMD0_UART1_RX       3
+#define AU1200_DSCR_CMD0_DMA_REQ0       4
+#define AU1200_DSCR_CMD0_DMA_REQ1       5
+#define AU1200_DSCR_CMD0_MAE_BE         6
+#define AU1200_DSCR_CMD0_MAE_FE         7
+#define AU1200_DSCR_CMD0_SDMS_TX0       8
+#define AU1200_DSCR_CMD0_SDMS_RX0       9
+#define AU1200_DSCR_CMD0_SDMS_TX1       10
+#define AU1200_DSCR_CMD0_SDMS_RX1       11
+#define AU1200_DSCR_CMD0_AES_TX         13
+#define AU1200_DSCR_CMD0_AES_RX         12
+#define AU1200_DSCR_CMD0_PSC0_TX        14
+#define AU1200_DSCR_CMD0_PSC0_RX        15
+#define AU1200_DSCR_CMD0_PSC1_TX        16
+#define AU1200_DSCR_CMD0_PSC1_RX        17
+#define AU1200_DSCR_CMD0_CIM_RXA        18
+#define AU1200_DSCR_CMD0_CIM_RXB        19
+#define AU1200_DSCR_CMD0_CIM_RXC        20
+#define AU1200_DSCR_CMD0_MAE_BOTH       21
+#define AU1200_DSCR_CMD0_LCD            22
+#define AU1200_DSCR_CMD0_NAND_FLASH     23
+#define AU1200_DSCR_CMD0_PSC0_SYNC      24
+#define AU1200_DSCR_CMD0_PSC1_SYNC      25
+#define AU1200_DSCR_CMD0_CIM_SYNC       26
+
+#define AU1300_DSCR_CMD0_UART0_TX      0
+#define AU1300_DSCR_CMD0_UART0_RX      1
+#define AU1300_DSCR_CMD0_UART1_TX      2
+#define AU1300_DSCR_CMD0_UART1_RX      3
+#define AU1300_DSCR_CMD0_UART2_TX      4
+#define AU1300_DSCR_CMD0_UART2_RX      5
+#define AU1300_DSCR_CMD0_UART3_TX      6
+#define AU1300_DSCR_CMD0_UART3_RX      7
+#define AU1300_DSCR_CMD0_SDMS_TX0      8
+#define AU1300_DSCR_CMD0_SDMS_RX0      9
+#define AU1300_DSCR_CMD0_SDMS_TX1      10
+#define AU1300_DSCR_CMD0_SDMS_RX1      11
+#define AU1300_DSCR_CMD0_AES_TX        12
+#define AU1300_DSCR_CMD0_AES_RX        13
+#define AU1300_DSCR_CMD0_PSC0_TX       14
+#define AU1300_DSCR_CMD0_PSC0_RX       15
+#define AU1300_DSCR_CMD0_PSC1_TX       16
+#define AU1300_DSCR_CMD0_PSC1_RX       17
+#define AU1300_DSCR_CMD0_PSC2_TX       18
+#define AU1300_DSCR_CMD0_PSC2_RX       19
+#define AU1300_DSCR_CMD0_PSC3_TX       20
+#define AU1300_DSCR_CMD0_PSC3_RX       21
+#define AU1300_DSCR_CMD0_LCD           22
+#define AU1300_DSCR_CMD0_NAND_FLASH    23
+#define AU1300_DSCR_CMD0_SDMS_TX2      24
+#define AU1300_DSCR_CMD0_SDMS_RX2      25
+#define AU1300_DSCR_CMD0_CIM_SYNC      26
+#define AU1300_DSCR_CMD0_UDMA          27
+#define AU1300_DSCR_CMD0_DMA_REQ0      28
+#define AU1300_DSCR_CMD0_DMA_REQ1      29
+
+#define DSCR_CMD0_THROTTLE      30
+#define DSCR_CMD0_ALWAYS        31
+#define DSCR_NDEV_IDS           32
+/* This macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
+                                  ((d) & 0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)   ((x) & 0xFF)
+
+#define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
+#define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
+
+/* Source/Destination transfer width. */
+#define DSCR_CMD0_BYTE          0
+#define DSCR_CMD0_HALFWORD      1
+#define DSCR_CMD0_WORD          2
+
+#define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
+#define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
+
+/* DDMA Descriptor Type. */
+#define DSCR_CMD0_STANDARD      0
+#define DSCR_CMD0_LITERAL       1
+#define DSCR_CMD0_CMP_BRANCH    2
+
+#define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
+
+/* Status Instruction. */
+#define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
+#define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
+#define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
+#define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
+
+#define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
+
+/* Descriptor Command 1. */
+#define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
+#define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
+#define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
+#define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
+
+/* Flag description. */
+#define DSCR_CMD1_FL_MEM_STRIDE0        0
+#define DSCR_CMD1_FL_MEM_STRIDE1        1
+#define DSCR_CMD1_FL_MEM_STRIDE2        2
+
+#define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
+
+/* Source1, 1-dimensional stride. */
+#define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
+#define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
+#define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
+#define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
+#define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
+#define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
+
+/* Dest1, 1-dimensional stride. */
+#define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
+#define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
+#define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
+#define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
+#define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
+#define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
+
+#define DSCR_xTS_SIZE1          0
+#define DSCR_xTS_SIZE2          1
+#define DSCR_xTS_SIZE4          2
+#define DSCR_xTS_SIZE8          3
+#define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
+#define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
+
+#define DSCR_xAM_INCREMENT      0
+#define DSCR_xAM_DECREMENT      1
+#define DSCR_xAM_STATIC         2
+#define DSCR_xAM_BURST          3
+#define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
+#define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
+
+/* The next descriptor pointer. */
+#define DSCR_NXTPTR_MASK        (0x07ffffff)
+#define DSCR_NXTPTR(x)          ((x) >> 5)
+#define DSCR_GET_NXTPTR(x)      ((x) << 5)
+#define DSCR_NXTPTR_MS          (1 << 27)
+
+/* The number of DBDMA channels. */
+#define NUM_DBDMA_CHANS 16
+
+/*
+ * DDMA API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+        u32     dev_id;
+        u32     dev_flags;
+        u32     dev_tsize;
+        u32     dev_devwidth;
+        u32     dev_physaddr;           /* If FIFO */
+        u32     dev_intlevel;
+        u32     dev_intpolarity;
+} dbdev_tab_t;
+
+
+typedef struct dbdma_chan_config {
+        spinlock_t      lock;
+
+        u32                     chan_flags;
+        u32                     chan_index;
+        dbdev_tab_t             *chan_src;
+        dbdev_tab_t             *chan_dest;
+        au1x_dma_chan_t         *chan_ptr;
+        au1x_ddma_desc_t        *chan_desc_base;
+        u32                     cdb_membase; /* kmalloc base of above */
+        au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+        void                    *chan_callparam;
+        void                    (*chan_callback)(int, void *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE         (1 << 0)
+#define DEV_FLAGS_ANYUSE        (1 << 1)
+#define DEV_FLAGS_OUT           (1 << 2)
+#define DEV_FLAGS_IN            (1 << 3)
+#define DEV_FLAGS_BURSTABLE     (1 << 4)
+#define DEV_FLAGS_SYNC          (1 << 5)
+/* end DDMA API definitions */
+
+/*
+ * External functions for drivers to use.
+ * Use this to allocate a DBDMA channel.  The device IDs are one of
+ * the DSCR_CMD0 devices IDs, which is usually redefined to a more
+ * meaningful name.  The 'callback' is called during DMA completion
+ * interrupt.
+ */
+extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
+                                   void (*callback)(int, void *),
+                                   void *callparam);
+
+#define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
+
+/* Set the device width of an in/out FIFO. */
+u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
+
+/* Allocate a ring of descriptors for DBDMA. */
+u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
+
+/* Put buffers on source/destination descriptors. */
+u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
+u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
+
+/* Get a buffer from the destination descriptor. */
+u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
+
+void au1xxx_dbdma_stop(u32 chanid);
+void au1xxx_dbdma_start(u32 chanid);
+void au1xxx_dbdma_reset(u32 chanid);
+u32 au1xxx_get_dma_residue(u32 chanid);
+
+void au1xxx_dbdma_chan_free(u32 chanid);
+void au1xxx_dbdma_dump(u32 chanid);
+
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
+
+u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
+extern void au1xxx_ddma_del_device(u32 devid);
+void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
+
+/*
+ *      Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE   (1 << 0)
+#define DDMA_FLAGS_NOIE (1 << 1)
+
+#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* _AU1000_DBDMA_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
new file mode 100644
index 000000000..9d1c8d5ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __AU1X00_ETH_DATA_H
+#define __AU1X00_ETH_DATA_H
+
+/* Platform specific PHY configuration passed to the MAC driver */
+struct au1000_eth_platform_data {
+        int phy_static_config;
+        int phy_search_highest_addr;
+        int phy1_search_mac0;
+        int phy_addr;
+        int phy_busid;
+        int phy_irq;
+        char mac[6];
+};
+
+void __init au1xxx_override_eth_cfg(unsigned port,
+                        struct au1000_eth_platform_data *eth_data);
+
+#endif /* __AU1X00_ETH_DATA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
new file mode 100644
index 000000000..8a9cd754b
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -0,0 +1,466 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Specifics for the Au1xxx Programmable Serial Controllers, first
+ * seen in the AU1550 part.
+ */
+#ifndef _AU1000_PSC_H_
+#define _AU1000_PSC_H_
+
+/*
+ * The PSC select and control registers are common to all protocols.
+ */
+#define PSC_SEL_OFFSET          0x00000000
+#define PSC_CTRL_OFFSET         0x00000004
+
+#define PSC_SEL_CLK_MASK        (3 << 4)
+#define PSC_SEL_CLK_INTCLK      (0 << 4)
+#define PSC_SEL_CLK_EXTCLK      (1 << 4)
+#define PSC_SEL_CLK_SERCLK      (2 << 4)
+
+#define PSC_SEL_PS_MASK         0x00000007
+#define PSC_SEL_PS_DISABLED     0
+#define PSC_SEL_PS_SPIMODE      2
+#define PSC_SEL_PS_I2SMODE      3
+#define PSC_SEL_PS_AC97MODE     4
+#define PSC_SEL_PS_SMBUSMODE    5
+
+#define PSC_CTRL_DISABLE        0
+#define PSC_CTRL_SUSPEND        2
+#define PSC_CTRL_ENABLE         3
+
+/* AC97 Registers. */
+#define PSC_AC97CFG_OFFSET      0x00000008
+#define PSC_AC97MSK_OFFSET      0x0000000c
+#define PSC_AC97PCR_OFFSET      0x00000010
+#define PSC_AC97STAT_OFFSET     0x00000014
+#define PSC_AC97EVNT_OFFSET     0x00000018
+#define PSC_AC97TXRX_OFFSET     0x0000001c
+#define PSC_AC97CDC_OFFSET      0x00000020
+#define PSC_AC97RST_OFFSET      0x00000024
+#define PSC_AC97GPO_OFFSET      0x00000028
+#define PSC_AC97GPI_OFFSET      0x0000002c
+
+/* AC97 Config Register. */
+#define PSC_AC97CFG_RT_MASK     (3 << 30)
+#define PSC_AC97CFG_RT_FIFO1    (0 << 30)
+#define PSC_AC97CFG_RT_FIFO2    (1 << 30)
+#define PSC_AC97CFG_RT_FIFO4    (2 << 30)
+#define PSC_AC97CFG_RT_FIFO8    (3 << 30)
+
+#define PSC_AC97CFG_TT_MASK     (3 << 28)
+#define PSC_AC97CFG_TT_FIFO1    (0 << 28)
+#define PSC_AC97CFG_TT_FIFO2    (1 << 28)
+#define PSC_AC97CFG_TT_FIFO4    (2 << 28)
+#define PSC_AC97CFG_TT_FIFO8    (3 << 28)
+
+#define PSC_AC97CFG_DD_DISABLE  (1 << 27)
+#define PSC_AC97CFG_DE_ENABLE   (1 << 26)
+#define PSC_AC97CFG_SE_ENABLE   (1 << 25)
+
+#define PSC_AC97CFG_LEN_MASK    (0xf << 21)
+#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
+#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
+#define PSC_AC97CFG_GE_ENABLE   (1)
+
+/* Enable slots 3-12. */
+#define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
+#define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
+
+/*
+ * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
+ * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
+ * arithmetic in the macro.
+ */
+#define PSC_AC97CFG_SET_LEN(x)  (((((x) - 2) / 2) & 0xf) << 21)
+#define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
+
+/* AC97 Mask Register. */
+#define PSC_AC97MSK_GR          (1 << 25)
+#define PSC_AC97MSK_CD          (1 << 24)
+#define PSC_AC97MSK_RR          (1 << 13)
+#define PSC_AC97MSK_RO          (1 << 12)
+#define PSC_AC97MSK_RU          (1 << 11)
+#define PSC_AC97MSK_TR          (1 << 10)
+#define PSC_AC97MSK_TO          (1 << 9)
+#define PSC_AC97MSK_TU          (1 << 8)
+#define PSC_AC97MSK_RD          (1 << 5)
+#define PSC_AC97MSK_TD          (1 << 4)
+#define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
+                                 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
+                                 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
+                                 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
+                                 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
+
+/* AC97 Protocol Control Register. */
+#define PSC_AC97PCR_RC          (1 << 6)
+#define PSC_AC97PCR_RP          (1 << 5)
+#define PSC_AC97PCR_RS          (1 << 4)
+#define PSC_AC97PCR_TC          (1 << 2)
+#define PSC_AC97PCR_TP          (1 << 1)
+#define PSC_AC97PCR_TS          (1 << 0)
+
+/* AC97 Status register (read only). */
+#define PSC_AC97STAT_CB         (1 << 26)
+#define PSC_AC97STAT_CP         (1 << 25)
+#define PSC_AC97STAT_CR         (1 << 24)
+#define PSC_AC97STAT_RF         (1 << 13)
+#define PSC_AC97STAT_RE         (1 << 12)
+#define PSC_AC97STAT_RR         (1 << 11)
+#define PSC_AC97STAT_TF         (1 << 10)
+#define PSC_AC97STAT_TE         (1 << 9)
+#define PSC_AC97STAT_TR         (1 << 8)
+#define PSC_AC97STAT_RB         (1 << 5)
+#define PSC_AC97STAT_TB         (1 << 4)
+#define PSC_AC97STAT_DI         (1 << 2)
+#define PSC_AC97STAT_DR         (1 << 1)
+#define PSC_AC97STAT_SR         (1 << 0)
+
+/* AC97 Event Register. */
+#define PSC_AC97EVNT_GR         (1 << 25)
+#define PSC_AC97EVNT_CD         (1 << 24)
+#define PSC_AC97EVNT_RR         (1 << 13)
+#define PSC_AC97EVNT_RO         (1 << 12)
+#define PSC_AC97EVNT_RU         (1 << 11)
+#define PSC_AC97EVNT_TR         (1 << 10)
+#define PSC_AC97EVNT_TO         (1 << 9)
+#define PSC_AC97EVNT_TU         (1 << 8)
+#define PSC_AC97EVNT_RD         (1 << 5)
+#define PSC_AC97EVNT_TD         (1 << 4)
+
+/* CODEC Command Register. */
+#define PSC_AC97CDC_RD          (1 << 25)
+#define PSC_AC97CDC_ID_MASK     (3 << 23)
+#define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
+#define PSC_AC97CDC_ID(x)       (((x) & 0x03) << 23)
+#define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
+
+/* AC97 Reset Control Register. */
+#define PSC_AC97RST_RST         (1 << 1)
+#define PSC_AC97RST_SNC         (1 << 0)
+
+/* PSC in I2S Mode. */
+typedef struct  psc_i2s {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_i2scfg;
+        u32     psc_i2smsk;
+        u32     psc_i2spcr;
+        u32     psc_i2sstat;
+        u32     psc_i2sevent;
+        u32     psc_i2stxrx;
+        u32     psc_i2sudf;
+} psc_i2s_t;
+
+#define PSC_I2SCFG_OFFSET       0x08
+#define PSC_I2SMASK_OFFSET      0x0C
+#define PSC_I2SPCR_OFFSET       0x10
+#define PSC_I2SSTAT_OFFSET      0x14
+#define PSC_I2SEVENT_OFFSET     0x18
+#define PSC_I2SRXTX_OFFSET      0x1C
+#define PSC_I2SUDF_OFFSET       0x20
+
+/* I2S Config Register. */
+#define PSC_I2SCFG_RT_MASK      (3 << 30)
+#define PSC_I2SCFG_RT_FIFO1     (0 << 30)
+#define PSC_I2SCFG_RT_FIFO2     (1 << 30)
+#define PSC_I2SCFG_RT_FIFO4     (2 << 30)
+#define PSC_I2SCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_I2SCFG_TT_MASK      (3 << 28)
+#define PSC_I2SCFG_TT_FIFO1     (0 << 28)
+#define PSC_I2SCFG_TT_FIFO2     (1 << 28)
+#define PSC_I2SCFG_TT_FIFO4     (2 << 28)
+#define PSC_I2SCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_I2SCFG_DD_DISABLE   (1 << 27)
+#define PSC_I2SCFG_DE_ENABLE    (1 << 26)
+#define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
+#define PSC_I2SCFG_WS(n)        ((n & 0xFF) << 16)
+#define PSC_I2SCFG_WS_MASK      (PSC_I2SCFG_WS(0x3F))
+#define PSC_I2SCFG_WI           (1 << 15)
+
+#define PSC_I2SCFG_DIV_MASK     (3 << 13)
+#define PSC_I2SCFG_DIV2         (0 << 13)
+#define PSC_I2SCFG_DIV4         (1 << 13)
+#define PSC_I2SCFG_DIV8         (2 << 13)
+#define PSC_I2SCFG_DIV16        (3 << 13)
+
+#define PSC_I2SCFG_BI           (1 << 12)
+#define PSC_I2SCFG_BUF          (1 << 11)
+#define PSC_I2SCFG_MLJ          (1 << 10)
+#define PSC_I2SCFG_XM           (1 << 9)
+
+/* The word length equation is simply LEN+1. */
+#define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
+#define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
+
+#define PSC_I2SCFG_LB           (1 << 2)
+#define PSC_I2SCFG_MLF          (1 << 1)
+#define PSC_I2SCFG_MS           (1 << 0)
+
+/* I2S Mask Register. */
+#define PSC_I2SMSK_RR           (1 << 13)
+#define PSC_I2SMSK_RO           (1 << 12)
+#define PSC_I2SMSK_RU           (1 << 11)
+#define PSC_I2SMSK_TR           (1 << 10)
+#define PSC_I2SMSK_TO           (1 << 9)
+#define PSC_I2SMSK_TU           (1 << 8)
+#define PSC_I2SMSK_RD           (1 << 5)
+#define PSC_I2SMSK_TD           (1 << 4)
+#define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
+                                 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
+                                 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
+                                 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
+
+/* I2S Protocol Control Register. */
+#define PSC_I2SPCR_RC           (1 << 6)
+#define PSC_I2SPCR_RP           (1 << 5)
+#define PSC_I2SPCR_RS           (1 << 4)
+#define PSC_I2SPCR_TC           (1 << 2)
+#define PSC_I2SPCR_TP           (1 << 1)
+#define PSC_I2SPCR_TS           (1 << 0)
+
+/* I2S Status register (read only). */
+#define PSC_I2SSTAT_RF          (1 << 13)
+#define PSC_I2SSTAT_RE          (1 << 12)
+#define PSC_I2SSTAT_RR          (1 << 11)
+#define PSC_I2SSTAT_TF          (1 << 10)
+#define PSC_I2SSTAT_TE          (1 << 9)
+#define PSC_I2SSTAT_TR          (1 << 8)
+#define PSC_I2SSTAT_RB          (1 << 5)
+#define PSC_I2SSTAT_TB          (1 << 4)
+#define PSC_I2SSTAT_DI          (1 << 2)
+#define PSC_I2SSTAT_DR          (1 << 1)
+#define PSC_I2SSTAT_SR          (1 << 0)
+
+/* I2S Event Register. */
+#define PSC_I2SEVNT_RR          (1 << 13)
+#define PSC_I2SEVNT_RO          (1 << 12)
+#define PSC_I2SEVNT_RU          (1 << 11)
+#define PSC_I2SEVNT_TR          (1 << 10)
+#define PSC_I2SEVNT_TO          (1 << 9)
+#define PSC_I2SEVNT_TU          (1 << 8)
+#define PSC_I2SEVNT_RD          (1 << 5)
+#define PSC_I2SEVNT_TD          (1 << 4)
+
+/* PSC in SPI Mode. */
+typedef struct  psc_spi {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_spicfg;
+        u32     psc_spimsk;
+        u32     psc_spipcr;
+        u32     psc_spistat;
+        u32     psc_spievent;
+        u32     psc_spitxrx;
+} psc_spi_t;
+
+/* SPI Config Register. */
+#define PSC_SPICFG_RT_MASK      (3 << 30)
+#define PSC_SPICFG_RT_FIFO1     (0 << 30)
+#define PSC_SPICFG_RT_FIFO2     (1 << 30)
+#define PSC_SPICFG_RT_FIFO4     (2 << 30)
+#define PSC_SPICFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SPICFG_TT_MASK      (3 << 28)
+#define PSC_SPICFG_TT_FIFO1     (0 << 28)
+#define PSC_SPICFG_TT_FIFO2     (1 << 28)
+#define PSC_SPICFG_TT_FIFO4     (2 << 28)
+#define PSC_SPICFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SPICFG_DD_DISABLE   (1 << 27)
+#define PSC_SPICFG_DE_ENABLE    (1 << 26)
+#define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
+#define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
+
+#define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SPICFG_DIV2         0
+#define PSC_SPICFG_DIV4         1
+#define PSC_SPICFG_DIV8         2
+#define PSC_SPICFG_DIV16        3
+
+#define PSC_SPICFG_BI           (1 << 12)
+#define PSC_SPICFG_PSE          (1 << 11)
+#define PSC_SPICFG_CGE          (1 << 10)
+#define PSC_SPICFG_CDE          (1 << 9)
+
+#define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
+#define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
+
+#define PSC_SPICFG_LB           (1 << 3)
+#define PSC_SPICFG_MLF          (1 << 1)
+#define PSC_SPICFG_MO           (1 << 0)
+
+/* SPI Mask Register. */
+#define PSC_SPIMSK_MM           (1 << 16)
+#define PSC_SPIMSK_RR           (1 << 13)
+#define PSC_SPIMSK_RO           (1 << 12)
+#define PSC_SPIMSK_RU           (1 << 11)
+#define PSC_SPIMSK_TR           (1 << 10)
+#define PSC_SPIMSK_TO           (1 << 9)
+#define PSC_SPIMSK_TU           (1 << 8)
+#define PSC_SPIMSK_SD           (1 << 5)
+#define PSC_SPIMSK_MD           (1 << 4)
+#define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
+                                 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
+                                 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
+                                 PSC_SPIMSK_MD)
+
+/* SPI Protocol Control Register. */
+#define PSC_SPIPCR_RC           (1 << 6)
+#define PSC_SPIPCR_SP           (1 << 5)
+#define PSC_SPIPCR_SS           (1 << 4)
+#define PSC_SPIPCR_TC           (1 << 2)
+#define PSC_SPIPCR_MS           (1 << 0)
+
+/* SPI Status register (read only). */
+#define PSC_SPISTAT_RF          (1 << 13)
+#define PSC_SPISTAT_RE          (1 << 12)
+#define PSC_SPISTAT_RR          (1 << 11)
+#define PSC_SPISTAT_TF          (1 << 10)
+#define PSC_SPISTAT_TE          (1 << 9)
+#define PSC_SPISTAT_TR          (1 << 8)
+#define PSC_SPISTAT_SB          (1 << 5)
+#define PSC_SPISTAT_MB          (1 << 4)
+#define PSC_SPISTAT_DI          (1 << 2)
+#define PSC_SPISTAT_DR          (1 << 1)
+#define PSC_SPISTAT_SR          (1 << 0)
+
+/* SPI Event Register. */
+#define PSC_SPIEVNT_MM          (1 << 16)
+#define PSC_SPIEVNT_RR          (1 << 13)
+#define PSC_SPIEVNT_RO          (1 << 12)
+#define PSC_SPIEVNT_RU          (1 << 11)
+#define PSC_SPIEVNT_TR          (1 << 10)
+#define PSC_SPIEVNT_TO          (1 << 9)
+#define PSC_SPIEVNT_TU          (1 << 8)
+#define PSC_SPIEVNT_SD          (1 << 5)
+#define PSC_SPIEVNT_MD          (1 << 4)
+
+/* Transmit register control. */
+#define PSC_SPITXRX_LC          (1 << 29)
+#define PSC_SPITXRX_SR          (1 << 28)
+
+/* SMBus Config Register. */
+#define PSC_SMBCFG_RT_MASK      (3 << 30)
+#define PSC_SMBCFG_RT_FIFO1     (0 << 30)
+#define PSC_SMBCFG_RT_FIFO2     (1 << 30)
+#define PSC_SMBCFG_RT_FIFO4     (2 << 30)
+#define PSC_SMBCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SMBCFG_TT_MASK      (3 << 28)
+#define PSC_SMBCFG_TT_FIFO1     (0 << 28)
+#define PSC_SMBCFG_TT_FIFO2     (1 << 28)
+#define PSC_SMBCFG_TT_FIFO4     (2 << 28)
+#define PSC_SMBCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SMBCFG_DD_DISABLE   (1 << 27)
+#define PSC_SMBCFG_DE_ENABLE    (1 << 26)
+
+#define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SMBCFG_DIV2         0
+#define PSC_SMBCFG_DIV4         1
+#define PSC_SMBCFG_DIV8         2
+#define PSC_SMBCFG_DIV16        3
+
+#define PSC_SMBCFG_GCE          (1 << 9)
+#define PSC_SMBCFG_SFM          (1 << 8)
+
+#define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
+
+/* SMBus Mask Register. */
+#define PSC_SMBMSK_DN           (1 << 30)
+#define PSC_SMBMSK_AN           (1 << 29)
+#define PSC_SMBMSK_AL           (1 << 28)
+#define PSC_SMBMSK_RR           (1 << 13)
+#define PSC_SMBMSK_RO           (1 << 12)
+#define PSC_SMBMSK_RU           (1 << 11)
+#define PSC_SMBMSK_TR           (1 << 10)
+#define PSC_SMBMSK_TO           (1 << 9)
+#define PSC_SMBMSK_TU           (1 << 8)
+#define PSC_SMBMSK_SD           (1 << 5)
+#define PSC_SMBMSK_MD           (1 << 4)
+#define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
+                                 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
+                                 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
+                                 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
+                                 PSC_SMBMSK_MD)
+
+/* SMBus Protocol Control Register. */
+#define PSC_SMBPCR_DC           (1 << 2)
+#define PSC_SMBPCR_MS           (1 << 0)
+
+/* SMBus Status register (read only). */
+#define PSC_SMBSTAT_BB          (1 << 28)
+#define PSC_SMBSTAT_RF          (1 << 13)
+#define PSC_SMBSTAT_RE          (1 << 12)
+#define PSC_SMBSTAT_RR          (1 << 11)
+#define PSC_SMBSTAT_TF          (1 << 10)
+#define PSC_SMBSTAT_TE          (1 << 9)
+#define PSC_SMBSTAT_TR          (1 << 8)
+#define PSC_SMBSTAT_SB          (1 << 5)
+#define PSC_SMBSTAT_MB          (1 << 4)
+#define PSC_SMBSTAT_DI          (1 << 2)
+#define PSC_SMBSTAT_DR          (1 << 1)
+#define PSC_SMBSTAT_SR          (1 << 0)
+
+/* SMBus Event Register. */
+#define PSC_SMBEVNT_DN          (1 << 30)
+#define PSC_SMBEVNT_AN          (1 << 29)
+#define PSC_SMBEVNT_AL          (1 << 28)
+#define PSC_SMBEVNT_RR          (1 << 13)
+#define PSC_SMBEVNT_RO          (1 << 12)
+#define PSC_SMBEVNT_RU          (1 << 11)
+#define PSC_SMBEVNT_TR          (1 << 10)
+#define PSC_SMBEVNT_TO          (1 << 9)
+#define PSC_SMBEVNT_TU          (1 << 8)
+#define PSC_SMBEVNT_SD          (1 << 5)
+#define PSC_SMBEVNT_MD          (1 << 4)
+#define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
+                                 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
+                                 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
+                                 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
+                                 PSC_SMBEVNT_MD)
+
+/* Transmit register control. */
+#define PSC_SMBTXRX_RSR         (1 << 28)
+#define PSC_SMBTXRX_STP         (1 << 29)
+#define PSC_SMBTXRX_DATAMASK    0xff
+
+/* SMBus protocol timers register. */
+#define PSC_SMBTMR_SET_TH(x)    (((x) & 0x03) << 30)
+#define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
+#define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
+#define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
+#define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
+#define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
+#define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
+
+#endif /* _AU1000_PSC_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
new file mode 100644
index 000000000..e6e527224
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -0,0 +1,94 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb                     1
+#define cpu_has_ftlb                    0
+#define cpu_has_tlbinv                  0
+#define cpu_has_segments                0
+#define cpu_has_eva                     0
+#define cpu_has_htw                     0
+#define cpu_has_ldpte                   0
+#define cpu_has_rixiex                  0
+#define cpu_has_maar                    0
+#define cpu_has_rw_llb                  0
+#define cpu_has_3kex                    0
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+#define cpu_has_guestctl0ext            0
+#define cpu_has_guestctl1               0
+#define cpu_has_guestctl2               0
+#define cpu_has_guestid                 0
+#define cpu_has_drg                     0
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+#define cpu_has_rixi                    0
+#define cpu_has_mmips                   0
+#define cpu_has_lpa                     0
+#define cpu_has_mhv                     0
+#define cpu_has_vtag_icache             0
+#define cpu_has_dc_aliases              0
+#define cpu_has_ic_fills_f_dc           1
+#define cpu_has_pindexed_dcache         0
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips32r6                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+#define cpu_has_mips64r6                0
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_dsp3                    0
+#define cpu_has_mipsmt                  0
+#define cpu_has_vp                      0
+#define cpu_has_userlocal               0
+#define cpu_has_nofpuex                 0
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#define cpu_has_vint                    0
+#define cpu_has_veic                    0
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()          32
+#define cpu_icache_line_size()          32
+#define cpu_scache_line_size()          0
+#define cpu_tcache_line_size()          0
+
+#define cpu_has_perf_cntr_intr_bit      0
+#define cpu_has_vz                      0
+#define cpu_has_msa                     0
+#define cpu_has_ufr                     0
+#define cpu_has_fre                     0
+#define cpu_has_cdmm                    0
+#define cpu_has_small_pages             0
+#define cpu_has_nan_legacy              1
+#define cpu_has_nan_2008                1
+#define cpu_has_ebase_wg                0
+#define cpu_has_badinstr                0
+#define cpu_has_badinstrp               0
+#define cpu_has_contextconfig           0
+#define cpu_has_perf                    0
+
+#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
new file mode 100644
index 000000000..adde1fa50
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -0,0 +1,532 @@
+/*
+ * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
+ *
+ * Copyright (c) 2009 Manuel Lauss.
+ *
+ * Licensed under the terms outlined in the file COPYING.
+ */
+
+#ifndef _ALCHEMY_GPIO_AU1000_H_
+#define _ALCHEMY_GPIO_AU1000_H_
+
+#include <asm/mach-au1x00/au1000.h>
+
+/* The default GPIO numberspace as documented in the Alchemy manuals.
+ * GPIO0-31 from GPIO1 block,   GPIO200-215 from GPIO2 block.
+ */
+#define ALCHEMY_GPIO1_BASE      0
+#define ALCHEMY_GPIO2_BASE      200
+
+#define ALCHEMY_GPIO1_NUM       32
+#define ALCHEMY_GPIO2_NUM       16
+#define ALCHEMY_GPIO1_MAX       (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
+#define ALCHEMY_GPIO2_MAX       (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
+
+#define MAKE_IRQ(intc, off)     (AU1000_INTC##intc##_INT_BASE + (off))
+
+/* GPIO1 registers within SYS_ area */
+#define AU1000_SYS_TRIOUTRD     0x100
+#define AU1000_SYS_TRIOUTCLR    0x100
+#define AU1000_SYS_OUTPUTRD     0x108
+#define AU1000_SYS_OUTPUTSET    0x108
+#define AU1000_SYS_OUTPUTCLR    0x10C
+#define AU1000_SYS_PINSTATERD   0x110
+#define AU1000_SYS_PININPUTEN   0x110
+
+/* register offsets within GPIO2 block */
+#define AU1000_GPIO2_DIR        0x00
+#define AU1000_GPIO2_OUTPUT     0x08
+#define AU1000_GPIO2_PINSTATE   0x0C
+#define AU1000_GPIO2_INTENABLE  0x10
+#define AU1000_GPIO2_ENABLE     0x14
+
+struct gpio;
+
+static inline int au1000_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1000_gpio2_to_irq(int gpio)
+{
+        return -ENXIO;
+}
+
+static inline int au1000_irq_to_gpio(int irq)
+{
+        if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
+
+        return -ENXIO;
+}
+
+static inline int au1500_gpio1_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO1_BASE;
+
+        switch (gpio) {
+        case 0 ... 15:
+        case 20:
+        case 23 ... 28: return MAKE_IRQ(1, gpio);
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1500_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0 ... 3:   return MAKE_IRQ(1, 16 + gpio - 0);
+        case 4 ... 5:   return MAKE_IRQ(1, 21 + gpio - 4);
+        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1500_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
+        case AU1500_GPIO20_INT:
+        case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
+        case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
+        case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
+        case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
+        case AU1500_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + 8;
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1100_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1100_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        if ((gpio >= 8) && (gpio <= 15))
+                return MAKE_IRQ(0, 29);         /* shared GPIO208_215 */
+
+        return -ENXIO;
+}
+
+static inline int au1100_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
+        case AU1100_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + 8;
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1550_gpio1_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO1_BASE;
+
+        switch (gpio) {
+        case 0 ... 15:
+        case 20 ... 28: return MAKE_IRQ(1, gpio);
+        case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1550_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0:         return MAKE_IRQ(1, 16);
+        case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
+        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
+        case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1550_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
+        case AU1550_GPIO200_INT:
+        case AU1550_GPIO201_205_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
+        case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
+        case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1200_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1200_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
+        case 3:         return MAKE_IRQ(0, 22);
+        case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);
+        case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1200_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
+        case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
+        case AU1200_GPIO203_INT:
+                return ALCHEMY_GPIO2_BASE + 3;
+        case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
+        }
+
+        return -ENXIO;
+}
+
+/*
+ * GPIO1 block macros for common linux gpio functions.
+ */
+static inline void alchemy_gpio1_set_value(int gpio, int v)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
+        alchemy_wrsys(mask, r);
+}
+
+static inline int alchemy_gpio1_get_value(int gpio)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
+}
+
+static inline int alchemy_gpio1_direction_input(int gpio)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
+        return 0;
+}
+
+static inline int alchemy_gpio1_direction_output(int gpio, int v)
+{
+        /* hardware switches to "output" mode when one of the two
+         * "set_value" registers is accessed.
+         */
+        alchemy_gpio1_set_value(gpio, v);
+        return 0;
+}
+
+static inline int alchemy_gpio1_is_valid(int gpio)
+{
+        return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
+}
+
+static inline int alchemy_gpio1_to_irq(int gpio)
+{
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_gpio1_to_irq(gpio);
+        }
+        return -ENXIO;
+}
+
+/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
+ * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200/Au1300 this
+ * register enables use of GPIOs as wake source.
+ */
+static inline void alchemy_gpio1_input_enable(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
+        __raw_writel(0, base + 0x110);          /* the write op is key */
+        wmb();
+}
+
+/*
+ * GPIO2 block macros for common linux GPIO functions. The 'gpio'
+ * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
+ */
+static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
+        unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
+
+        if (to_out)
+                d |= mask;
+        else
+                d &= ~mask;
+        __raw_writel(d, base + AU1000_GPIO2_DIR);
+        wmb();
+}
+
+static inline void alchemy_gpio2_set_value(int gpio, int v)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        unsigned long mask;
+        mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
+        __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
+        wmb();
+}
+
+static inline int alchemy_gpio2_get_value(int gpio)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
+                                (1 << (gpio - ALCHEMY_GPIO2_BASE));
+}
+
+static inline int alchemy_gpio2_direction_input(int gpio)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_dir(gpio, 0);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static inline int alchemy_gpio2_direction_output(int gpio, int v)
+{
+        unsigned long flags;
+        alchemy_gpio2_set_value(gpio, v);
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_dir(gpio, 1);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static inline int alchemy_gpio2_is_valid(int gpio)
+{
+        return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
+}
+
+static inline int alchemy_gpio2_to_irq(int gpio)
+{
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_gpio2_to_irq(gpio);
+        }
+        return -ENXIO;
+}
+
+/**********************************************************************/
+
+/* GPIO2 shared interrupts and control */
+
+static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
+        if (en)
+                r |= 1 << gpio2;
+        else
+                r &= ~(1 << gpio2);
+        __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
+        wmb();
+}
+
+/**
+ * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
+ * @gpio2:      The GPIO2 pin to activate (200...215).
+ *
+ * GPIO208-215 have one shared interrupt line to the INTC.  They are
+ * and'ed with a per-pin enable bit and finally or'ed together to form
+ * a single irq request (useful for active-high sources).
+ * With this function, a pins' individual contribution to the int request
+ * can be enabled.  As with all other GPIO-based interrupts, the INTC
+ * must be programmed to accept the GPIO208_215 interrupt as well.
+ *
+ * NOTE: Calling this macro is only necessary for GPIO208-215; all other
+ * GPIO2-based interrupts have their own request to the INTC.  Please
+ * consult your Alchemy databook for more information!
+ *
+ * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
+ * line to the INTC, GPIO201_205.  This function can be used for those
+ * as well.
+ *
+ * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
+ * (200-215 by default). No sanity checks are made,
+ */
+static inline void alchemy_gpio2_enable_int(int gpio2)
+{
+        unsigned long flags;
+
+        gpio2 -= ALCHEMY_GPIO2_BASE;
+
+        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1500:
+                gpio2 -= 8;
+        }
+
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_int(gpio2, 1);
+        local_irq_restore(flags);
+}
+
+/**
+ * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
+ * @gpio2:      The GPIO2 pin to activate (200...215).
+ *
+ * see function alchemy_gpio2_enable_int() for more information.
+ */
+static inline void alchemy_gpio2_disable_int(int gpio2)
+{
+        unsigned long flags;
+
+        gpio2 -= ALCHEMY_GPIO2_BASE;
+
+        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1500:
+                gpio2 -= 8;
+        }
+
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_int(gpio2, 0);
+        local_irq_restore(flags);
+}
+
+/**
+ * alchemy_gpio2_enable -  Activate GPIO2 block.
+ *
+ * The GPIO2 block must be enabled excplicitly to work.  On systems
+ * where this isn't done by the bootloader, this macro can be used.
+ */
+static inline void alchemy_gpio2_enable(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        __raw_writel(3, base + AU1000_GPIO2_ENABLE);    /* reset, clock enabled */
+        wmb();
+        __raw_writel(1, base + AU1000_GPIO2_ENABLE);    /* clock enabled */
+        wmb();
+}
+
+/**
+ * alchemy_gpio2_disable - disable GPIO2 block.
+ *
+ * Disable and put GPIO2 block in low-power mode.
+ */
+static inline void alchemy_gpio2_disable(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        __raw_writel(2, base + AU1000_GPIO2_ENABLE);    /* reset, clock disabled */
+        wmb();
+}
+
+/**********************************************************************/
+
+/* wrappers for on-chip gpios; can be used before gpio chips have been
+ * registered with gpiolib.
+ */
+static inline int alchemy_gpio_direction_input(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_direction_input(gpio) :
+                alchemy_gpio1_direction_input(gpio);
+}
+
+static inline int alchemy_gpio_direction_output(int gpio, int v)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_direction_output(gpio, v) :
+                alchemy_gpio1_direction_output(gpio, v);
+}
+
+static inline int alchemy_gpio_get_value(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_get_value(gpio) :
+                alchemy_gpio1_get_value(gpio);
+}
+
+static inline void alchemy_gpio_set_value(int gpio, int v)
+{
+        if (gpio >= ALCHEMY_GPIO2_BASE)
+                alchemy_gpio2_set_value(gpio, v);
+        else
+                alchemy_gpio1_set_value(gpio, v);
+}
+
+static inline int alchemy_gpio_is_valid(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_is_valid(gpio) :
+                alchemy_gpio1_is_valid(gpio);
+}
+
+static inline int alchemy_gpio_cansleep(int gpio)
+{
+        return 0;       /* Alchemy never gets tired */
+}
+
+static inline int alchemy_gpio_to_irq(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_to_irq(gpio) :
+                alchemy_gpio1_to_irq(gpio);
+}
+
+static inline int alchemy_irq_to_gpio(int irq)
+{
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_irq_to_gpio(irq);
+        }
+        return -ENXIO;
+}
+
+#endif /* _ALCHEMY_GPIO_AU1000_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000..d16add7ba
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
+ *
+ * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
+ */
+
+#ifndef _GPIO_AU1300_H_
+#define _GPIO_AU1300_H_
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+struct gpio;
+struct gpio_chip;
+
+/* with the current GPIC design, up to 128 GPIOs are possible.
+ * The only implementation so far is in the Au1300, which has 75 externally
+ * available GPIOs.
+ */
+#define AU1300_GPIO_BASE        0
+#define AU1300_GPIO_NUM         75
+#define AU1300_GPIO_MAX         (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
+
+#define AU1300_GPIC_ADDR        \
+        (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
+
+static inline int au1300_gpio_get_value(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        int bit;
+
+        gpio -= AU1300_GPIO_BASE;
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
+}
+
+static inline int au1300_gpio_direction_input(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_set_value(unsigned int gpio, int v)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
+                                    : AU1300_GPIC_PINVALCLR));
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
+{
+        /* hw switches to output automatically */
+        return au1300_gpio_set_value(gpio, v);
+}
+
+static inline int au1300_gpio_to_irq(unsigned int gpio)
+{
+        return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
+}
+
+static inline int au1300_irq_to_gpio(unsigned int irq)
+{
+        return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
+}
+
+static inline int au1300_gpio_is_valid(unsigned int gpio)
+{
+        int ret;
+
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1300:
+                ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
+                break;
+        default:
+                ret = 0;
+        }
+        return ret;
+}
+
+static inline int au1300_gpio_cansleep(unsigned int gpio)
+{
+        return 0;
+}
+
+/* hardware remembers gpio 0-63 levels on powerup */
+static inline int au1300_gpio_getinitlvl(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long v;
+
+        if (unlikely(gpio > 63))
+                return 0;
+        else if (gpio > 31) {
+                gpio -= 32;
+                roff += 4;
+        }
+
+        v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
+        return (v >> gpio) & 1;
+}
+
+#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
new file mode 100644
index 000000000..c62ee0246
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __AU1X00_PROM_H
+#define __AU1X00_PROM_H
+
+extern int prom_argc;
+extern char **prom_argv;
+extern char **prom_envp;
+
+extern void prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+extern int prom_get_ethernet_addr(char *ethernet_addr);
+
+#endif
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
new file mode 100644
index 000000000..93817bfb7
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ */
+
+#ifndef __ASM_BCM47XX_H
+#define __ASM_BCM47XX_H
+
+#include <linux/ssb/ssb.h>
+#include <linux/bcma/bcma.h>
+#include <linux/bcma/bcma_soc.h>
+#include <linux/bcm47xx_nvram.h>
+#include <linux/bcm47xx_sprom.h>
+
+enum bcm47xx_bus_type {
+#ifdef CONFIG_BCM47XX_SSB
+        BCM47XX_BUS_TYPE_SSB,
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+        BCM47XX_BUS_TYPE_BCMA,
+#endif
+};
+
+union bcm47xx_bus {
+#ifdef CONFIG_BCM47XX_SSB
+        struct ssb_bus ssb;
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+        struct bcma_soc bcma;
+#endif
+};
+
+extern union bcm47xx_bus bcm47xx_bus;
+extern enum bcm47xx_bus_type bcm47xx_bus_type;
+
+void bcm47xx_set_system_type(u16 chip_id);
+
+#endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
new file mode 100644
index 000000000..f879be3e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __BCM47XX_BOARD_H
+#define __BCM47XX_BOARD_H
+
+enum bcm47xx_board {
+        BCM47XX_BOARD_ASUS_RTAC66U,
+        BCM47XX_BOARD_ASUS_RTN10,
+        BCM47XX_BOARD_ASUS_RTN10D,
+        BCM47XX_BOARD_ASUS_RTN10U,
+        BCM47XX_BOARD_ASUS_RTN12,
+        BCM47XX_BOARD_ASUS_RTN12B1,
+        BCM47XX_BOARD_ASUS_RTN12C1,
+        BCM47XX_BOARD_ASUS_RTN12D1,
+        BCM47XX_BOARD_ASUS_RTN12HP,
+        BCM47XX_BOARD_ASUS_RTN15U,
+        BCM47XX_BOARD_ASUS_RTN16,
+        BCM47XX_BOARD_ASUS_RTN53,
+        BCM47XX_BOARD_ASUS_RTN66U,
+        BCM47XX_BOARD_ASUS_WL300G,
+        BCM47XX_BOARD_ASUS_WL320GE,
+        BCM47XX_BOARD_ASUS_WL330GE,
+        BCM47XX_BOARD_ASUS_WL500G,
+        BCM47XX_BOARD_ASUS_WL500GD,
+        BCM47XX_BOARD_ASUS_WL500GPV1,
+        BCM47XX_BOARD_ASUS_WL500GPV2,
+        BCM47XX_BOARD_ASUS_WL500W,
+        BCM47XX_BOARD_ASUS_WL520GC,
+        BCM47XX_BOARD_ASUS_WL520GU,
+        BCM47XX_BOARD_ASUS_WL700GE,
+        BCM47XX_BOARD_ASUS_WLHDD,
+
+        BCM47XX_BOARD_BELKIN_F7D3301,
+        BCM47XX_BOARD_BELKIN_F7D3302,
+        BCM47XX_BOARD_BELKIN_F7D4301,
+        BCM47XX_BOARD_BELKIN_F7D4302,
+        BCM47XX_BOARD_BELKIN_F7D4401,
+
+        BCM47XX_BOARD_BUFFALO_WBR2_G54,
+        BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
+        BCM47XX_BOARD_BUFFALO_WHR_G125,
+        BCM47XX_BOARD_BUFFALO_WHR_G54S,
+        BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
+        BCM47XX_BOARD_BUFFALO_WLA2_G54L,
+        BCM47XX_BOARD_BUFFALO_WZR_G300N,
+        BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
+        BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
+
+        BCM47XX_BOARD_CISCO_M10V1,
+        BCM47XX_BOARD_CISCO_M20V1,
+
+        BCM47XX_BOARD_DELL_TM2300,
+
+        BCM47XX_BOARD_DLINK_DIR130,
+        BCM47XX_BOARD_DLINK_DIR330,
+
+        BCM47XX_BOARD_HUAWEI_E970,
+
+        BCM47XX_BOARD_LINKSYS_E900V1,
+        BCM47XX_BOARD_LINKSYS_E1000V1,
+        BCM47XX_BOARD_LINKSYS_E1000V2,
+        BCM47XX_BOARD_LINKSYS_E1000V21,
+        BCM47XX_BOARD_LINKSYS_E1200V2,
+        BCM47XX_BOARD_LINKSYS_E2000V1,
+        BCM47XX_BOARD_LINKSYS_E3000V1,
+        BCM47XX_BOARD_LINKSYS_E3200V1,
+        BCM47XX_BOARD_LINKSYS_E4200V1,
+        BCM47XX_BOARD_LINKSYS_WRT150NV1,
+        BCM47XX_BOARD_LINKSYS_WRT150NV11,
+        BCM47XX_BOARD_LINKSYS_WRT160NV1,
+        BCM47XX_BOARD_LINKSYS_WRT160NV3,
+        BCM47XX_BOARD_LINKSYS_WRT300N_V1,
+        BCM47XX_BOARD_LINKSYS_WRT300NV11,
+        BCM47XX_BOARD_LINKSYS_WRT310NV1,
+        BCM47XX_BOARD_LINKSYS_WRT310NV2,
+        BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
+        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
+        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
+        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
+        BCM47XX_BOARD_LINKSYS_WRT600N_V11,
+        BCM47XX_BOARD_LINKSYS_WRT610NV1,
+        BCM47XX_BOARD_LINKSYS_WRT610NV2,
+        BCM47XX_BOARD_LINKSYS_WRTSL54GS,
+
+        BCM47XX_BOARD_LUXUL_ABR_4400_V1,
+        BCM47XX_BOARD_LUXUL_XAP_310_V1,
+        BCM47XX_BOARD_LUXUL_XAP_1210_V1,
+        BCM47XX_BOARD_LUXUL_XAP_1230_V1,
+        BCM47XX_BOARD_LUXUL_XAP_1240_V1,
+        BCM47XX_BOARD_LUXUL_XAP_1500_V1,
+        BCM47XX_BOARD_LUXUL_XBR_4400_V1,
+        BCM47XX_BOARD_LUXUL_XVW_P30_V1,
+        BCM47XX_BOARD_LUXUL_XWR_600_V1,
+        BCM47XX_BOARD_LUXUL_XWR_1750_V1,
+
+        BCM47XX_BOARD_MICROSOFT_MN700,
+
+        BCM47XX_BOARD_MOTOROLA_WE800G,
+        BCM47XX_BOARD_MOTOROLA_WR850GP,
+        BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
+
+        BCM47XX_BOARD_NETGEAR_R6200_V1,
+        BCM47XX_BOARD_NETGEAR_WGR614V8,
+        BCM47XX_BOARD_NETGEAR_WGR614V9,
+        BCM47XX_BOARD_NETGEAR_WGR614_V10,
+        BCM47XX_BOARD_NETGEAR_WNDR3300,
+        BCM47XX_BOARD_NETGEAR_WNDR3400V1,
+        BCM47XX_BOARD_NETGEAR_WNDR3400V2,
+        BCM47XX_BOARD_NETGEAR_WNDR3400_V3,
+        BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
+        BCM47XX_BOARD_NETGEAR_WNDR3700V3,
+        BCM47XX_BOARD_NETGEAR_WNDR4000,
+        BCM47XX_BOARD_NETGEAR_WNDR4500V1,
+        BCM47XX_BOARD_NETGEAR_WNDR4500V2,
+        BCM47XX_BOARD_NETGEAR_WNR1000_V3,
+        BCM47XX_BOARD_NETGEAR_WNR2000,
+        BCM47XX_BOARD_NETGEAR_WNR3500L,
+        BCM47XX_BOARD_NETGEAR_WNR3500U,
+        BCM47XX_BOARD_NETGEAR_WNR3500V2,
+        BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
+        BCM47XX_BOARD_NETGEAR_WNR834BV2,
+
+        BCM47XX_BOARD_PHICOMM_M1,
+
+        BCM47XX_BOARD_SIEMENS_SE505V2,
+
+        BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
+
+        BCM47XX_BOARD_ZTE_H218N,
+
+        BCM47XX_BOARD_UNKNOWN,
+        BCM47XX_BOARD_NO,
+};
+
+#define BCM47XX_BOARD_MAX_NAME 30
+
+void bcm47xx_board_detect(void);
+enum bcm47xx_board bcm47xx_board_get(void);
+const char *bcm47xx_board_get_name(void);
+
+#endif /* __BCM47XX_BOARD_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
new file mode 100644
index 000000000..b23ff47ea
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_watch                   1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_watch                   0
+#endif
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+
+/* cpu_has_mips16 */
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_rixi                    0
+#define cpu_has_mmips                   0
+#define cpu_has_smartmips               0
+#define cpu_has_vtag_icache             0
+/* cpu_has_dc_aliases */
+#define cpu_has_ic_fills_f_dc           0
+#define cpu_has_pindexed_dcache         0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_mips_2                  1
+#define cpu_has_mips_3                  0
+#define cpu_has_mips32r1                1
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_mips32r2                1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_mips32r2                0
+#endif
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_dsp                     1
+#define cpu_has_dsp2                    1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#endif
+#define cpu_has_mipsmt                  0
+/* cpu_has_userlocal */
+
+#define cpu_has_nofpuex                 0
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_vint                    1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_vint                    0
+#endif
+#define cpu_has_veic                    0
+#define cpu_has_inclusive_pcaches       0
+
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_dcache_line_size()          32
+#define cpu_icache_line_size()          32
+#define cpu_has_perf_cntr_intr_bit      1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+#define cpu_has_perf_cntr_intr_bit      0
+#endif
+#define cpu_scache_line_size()          0
+#define cpu_has_vz                      0
+
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
new file mode 100644
index 000000000..1d19a726f
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_BOARD_H_
+#define BCM63XX_BOARD_H_
+
+const char *board_get_name(void);
+
+void board_prom_init(void);
+
+void board_setup(void);
+
+int board_register_devices(void);
+
+#endif /* ! BCM63XX_BOARD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
new file mode 100644
index 000000000..1cad18e66
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -0,0 +1,1068 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_CPU_H_
+#define BCM63XX_CPU_H_
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+/*
+ * Macro to fetch bcm63xx cpu id and revision, should be optimized at
+ * compile time if only one CPU support is enabled (idea stolen from
+ * arm mach-types)
+ */
+#define BCM3368_CPU_ID          0x3368
+#define BCM6328_CPU_ID          0x6328
+#define BCM6338_CPU_ID          0x6338
+#define BCM6345_CPU_ID          0x6345
+#define BCM6348_CPU_ID          0x6348
+#define BCM6358_CPU_ID          0x6358
+#define BCM6362_CPU_ID          0x6362
+#define BCM6368_CPU_ID          0x6368
+
+void __init bcm63xx_cpu_init(void);
+u8 bcm63xx_get_cpu_rev(void);
+unsigned int bcm63xx_get_cpu_freq(void);
+
+static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
+{
+        switch (cpu_id) {
+#ifdef CONFIG_BCM63XX_CPU_3368
+                case BCM3368_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6328
+                case BCM6328_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6338
+                case BCM6338_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6345
+                case BCM6345_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6348
+                case BCM6348_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6358
+                case BCM6358_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6362
+                case BCM6362_CPU_ID:
+#endif
+
+#ifdef CONFIG_BCM63XX_CPU_6368
+                case BCM6368_CPU_ID:
+#endif
+                break;
+        default:
+                unreachable();
+        }
+
+        return cpu_id;
+}
+
+extern u16 bcm63xx_cpu_id;
+
+static inline u16 __pure bcm63xx_get_cpu_id(void)
+{
+        const u16 cpu_id = bcm63xx_cpu_id;
+
+        return __bcm63xx_get_cpu_id(cpu_id);
+}
+
+#define BCMCPU_IS_3368()        (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
+#define BCMCPU_IS_6328()        (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
+#define BCMCPU_IS_6338()        (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+#define BCMCPU_IS_6345()        (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+#define BCMCPU_IS_6348()        (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
+#define BCMCPU_IS_6358()        (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
+#define BCMCPU_IS_6362()        (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
+#define BCMCPU_IS_6368()        (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+
+/*
+ * While registers sets are (mostly) the same across 63xx CPU, base
+ * address of these sets do change.
+ */
+enum bcm63xx_regs_set {
+        RSET_DSL_LMEM = 0,
+        RSET_PERF,
+        RSET_TIMER,
+        RSET_WDT,
+        RSET_UART0,
+        RSET_UART1,
+        RSET_GPIO,
+        RSET_SPI,
+        RSET_HSSPI,
+        RSET_UDC0,
+        RSET_OHCI0,
+        RSET_OHCI_PRIV,
+        RSET_USBH_PRIV,
+        RSET_USBD,
+        RSET_USBDMA,
+        RSET_MPI,
+        RSET_PCMCIA,
+        RSET_PCIE,
+        RSET_DSL,
+        RSET_ENET0,
+        RSET_ENET1,
+        RSET_ENETDMA,
+        RSET_ENETDMAC,
+        RSET_ENETDMAS,
+        RSET_ENETSW,
+        RSET_EHCI0,
+        RSET_SDRAM,
+        RSET_MEMC,
+        RSET_DDR,
+        RSET_M2M,
+        RSET_ATM,
+        RSET_XTM,
+        RSET_XTMDMA,
+        RSET_XTMDMAC,
+        RSET_XTMDMAS,
+        RSET_PCM,
+        RSET_PCMDMA,
+        RSET_PCMDMAC,
+        RSET_PCMDMAS,
+        RSET_RNG,
+        RSET_MISC
+};
+
+#define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
+#define RSET_DSL_SIZE                   4096
+#define RSET_WDT_SIZE                   12
+#define BCM_6338_RSET_SPI_SIZE          64
+#define BCM_6348_RSET_SPI_SIZE          64
+#define BCM_6358_RSET_SPI_SIZE          1804
+#define BCM_6368_RSET_SPI_SIZE          1804
+#define RSET_ENET_SIZE                  2048
+#define RSET_ENETDMA_SIZE               256
+#define RSET_6345_ENETDMA_SIZE          64
+#define RSET_ENETDMAC_SIZE(chans)       (16 * (chans))
+#define RSET_ENETDMAS_SIZE(chans)       (16 * (chans))
+#define RSET_ENETSW_SIZE                65536
+#define RSET_UART_SIZE                  24
+#define RSET_HSSPI_SIZE                 1536
+#define RSET_UDC_SIZE                   256
+#define RSET_OHCI_SIZE                  256
+#define RSET_EHCI_SIZE                  256
+#define RSET_USBD_SIZE                  256
+#define RSET_USBDMA_SIZE                1280
+#define RSET_PCMCIA_SIZE                12
+#define RSET_M2M_SIZE                   256
+#define RSET_ATM_SIZE                   4096
+#define RSET_XTM_SIZE                   10240
+#define RSET_XTMDMA_SIZE                256
+#define RSET_XTMDMAC_SIZE(chans)        (16 * (chans))
+#define RSET_XTMDMAS_SIZE(chans)        (16 * (chans))
+#define RSET_RNG_SIZE                   20
+
+/*
+ * 3368 register sets base address
+ */
+#define BCM_3368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_3368_PERF_BASE              (0xfff8c000)
+#define BCM_3368_TIMER_BASE             (0xfff8c040)
+#define BCM_3368_WDT_BASE               (0xfff8c080)
+#define BCM_3368_UART0_BASE             (0xfff8c100)
+#define BCM_3368_UART1_BASE             (0xfff8c120)
+#define BCM_3368_GPIO_BASE              (0xfff8c080)
+#define BCM_3368_SPI_BASE               (0xfff8c800)
+#define BCM_3368_HSSPI_BASE             (0xdeadbeef)
+#define BCM_3368_UDC0_BASE              (0xdeadbeef)
+#define BCM_3368_USBDMA_BASE            (0xdeadbeef)
+#define BCM_3368_OHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_3368_USBD_BASE              (0xdeadbeef)
+#define BCM_3368_MPI_BASE               (0xfff80000)
+#define BCM_3368_PCMCIA_BASE            (0xfff80054)
+#define BCM_3368_PCIE_BASE              (0xdeadbeef)
+#define BCM_3368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_3368_DSL_BASE               (0xdeadbeef)
+#define BCM_3368_UBUS_BASE              (0xdeadbeef)
+#define BCM_3368_ENET0_BASE             (0xfff98000)
+#define BCM_3368_ENET1_BASE             (0xfff98800)
+#define BCM_3368_ENETDMA_BASE           (0xfff99800)
+#define BCM_3368_ENETDMAC_BASE          (0xfff99900)
+#define BCM_3368_ENETDMAS_BASE          (0xfff99a00)
+#define BCM_3368_ENETSW_BASE            (0xdeadbeef)
+#define BCM_3368_EHCI0_BASE             (0xdeadbeef)
+#define BCM_3368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_3368_MEMC_BASE              (0xfff84000)
+#define BCM_3368_DDR_BASE               (0xdeadbeef)
+#define BCM_3368_M2M_BASE               (0xdeadbeef)
+#define BCM_3368_ATM_BASE               (0xdeadbeef)
+#define BCM_3368_XTM_BASE               (0xdeadbeef)
+#define BCM_3368_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_PCM_BASE               (0xfff9c200)
+#define BCM_3368_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_3368_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_3368_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_3368_RNG_BASE               (0xdeadbeef)
+#define BCM_3368_MISC_BASE              (0xdeadbeef)
+
+/*
+ * 6328 register sets base address
+ */
+#define BCM_6328_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6328_PERF_BASE              (0xb0000000)
+#define BCM_6328_TIMER_BASE             (0xb0000040)
+#define BCM_6328_WDT_BASE               (0xb000005c)
+#define BCM_6328_UART0_BASE             (0xb0000100)
+#define BCM_6328_UART1_BASE             (0xb0000120)
+#define BCM_6328_GPIO_BASE              (0xb0000080)
+#define BCM_6328_SPI_BASE               (0xdeadbeef)
+#define BCM_6328_HSSPI_BASE             (0xb0001000)
+#define BCM_6328_UDC0_BASE              (0xdeadbeef)
+#define BCM_6328_USBDMA_BASE            (0xb000c000)
+#define BCM_6328_OHCI0_BASE             (0xb0002600)
+#define BCM_6328_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6328_USBH_PRIV_BASE         (0xb0002700)
+#define BCM_6328_USBD_BASE              (0xb0002400)
+#define BCM_6328_MPI_BASE               (0xdeadbeef)
+#define BCM_6328_PCMCIA_BASE            (0xdeadbeef)
+#define BCM_6328_PCIE_BASE              (0xb0e40000)
+#define BCM_6328_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6328_DSL_BASE               (0xb0001900)
+#define BCM_6328_UBUS_BASE              (0xdeadbeef)
+#define BCM_6328_ENET0_BASE             (0xdeadbeef)
+#define BCM_6328_ENET1_BASE             (0xdeadbeef)
+#define BCM_6328_ENETDMA_BASE           (0xb000d800)
+#define BCM_6328_ENETDMAC_BASE          (0xb000da00)
+#define BCM_6328_ENETDMAS_BASE          (0xb000dc00)
+#define BCM_6328_ENETSW_BASE            (0xb0e00000)
+#define BCM_6328_EHCI0_BASE             (0xb0002500)
+#define BCM_6328_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6328_MEMC_BASE              (0xdeadbeef)
+#define BCM_6328_DDR_BASE               (0xb0003000)
+#define BCM_6328_M2M_BASE               (0xdeadbeef)
+#define BCM_6328_ATM_BASE               (0xdeadbeef)
+#define BCM_6328_XTM_BASE               (0xdeadbeef)
+#define BCM_6328_XTMDMA_BASE            (0xb000b800)
+#define BCM_6328_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6328_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6328_PCM_BASE               (0xb000a800)
+#define BCM_6328_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6328_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6328_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6328_RNG_BASE               (0xdeadbeef)
+#define BCM_6328_MISC_BASE              (0xb0001800)
+#define BCM_6328_OTP_BASE               (0xb0000600)
+
+/*
+ * 6338 register sets base address
+ */
+#define BCM_6338_DSL_LMEM_BASE          (0xfff00000)
+#define BCM_6338_PERF_BASE              (0xfffe0000)
+#define BCM_6338_BB_BASE                (0xfffe0100)
+#define BCM_6338_TIMER_BASE             (0xfffe0200)
+#define BCM_6338_WDT_BASE               (0xfffe021c)
+#define BCM_6338_UART0_BASE             (0xfffe0300)
+#define BCM_6338_UART1_BASE             (0xdeadbeef)
+#define BCM_6338_GPIO_BASE              (0xfffe0400)
+#define BCM_6338_SPI_BASE               (0xfffe0c00)
+#define BCM_6338_HSSPI_BASE             (0xdeadbeef)
+#define BCM_6338_UDC0_BASE              (0xdeadbeef)
+#define BCM_6338_USBDMA_BASE            (0xfffe2400)
+#define BCM_6338_OHCI0_BASE             (0xdeadbeef)
+#define BCM_6338_OHCI_PRIV_BASE         (0xfffe3000)
+#define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6338_USBD_BASE              (0xdeadbeef)
+#define BCM_6338_MPI_BASE               (0xfffe3160)
+#define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
+#define BCM_6338_PCIE_BASE              (0xdeadbeef)
+#define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
+#define BCM_6338_DSL_BASE               (0xfffe1000)
+#define BCM_6338_UBUS_BASE              (0xdeadbeef)
+#define BCM_6338_ENET0_BASE             (0xfffe2800)
+#define BCM_6338_ENET1_BASE             (0xdeadbeef)
+#define BCM_6338_ENETDMA_BASE           (0xfffe2400)
+#define BCM_6338_ENETDMAC_BASE          (0xfffe2500)
+#define BCM_6338_ENETDMAS_BASE          (0xfffe2600)
+#define BCM_6338_ENETSW_BASE            (0xdeadbeef)
+#define BCM_6338_EHCI0_BASE             (0xdeadbeef)
+#define BCM_6338_SDRAM_BASE             (0xfffe3100)
+#define BCM_6338_MEMC_BASE              (0xdeadbeef)
+#define BCM_6338_DDR_BASE               (0xdeadbeef)
+#define BCM_6338_M2M_BASE               (0xdeadbeef)
+#define BCM_6338_ATM_BASE               (0xfffe2000)
+#define BCM_6338_XTM_BASE               (0xdeadbeef)
+#define BCM_6338_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6338_PCM_BASE               (0xdeadbeef)
+#define BCM_6338_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6338_RNG_BASE               (0xdeadbeef)
+#define BCM_6338_MISC_BASE              (0xdeadbeef)
+
+/*
+ * 6345 register sets base address
+ */
+#define BCM_6345_DSL_LMEM_BASE          (0xfff00000)
+#define BCM_6345_PERF_BASE              (0xfffe0000)
+#define BCM_6345_BB_BASE                (0xfffe0100)
+#define BCM_6345_TIMER_BASE             (0xfffe0200)
+#define BCM_6345_WDT_BASE               (0xfffe021c)
+#define BCM_6345_UART0_BASE             (0xfffe0300)
+#define BCM_6345_UART1_BASE             (0xdeadbeef)
+#define BCM_6345_GPIO_BASE              (0xfffe0400)
+#define BCM_6345_SPI_BASE               (0xdeadbeef)
+#define BCM_6345_HSSPI_BASE             (0xdeadbeef)
+#define BCM_6345_UDC0_BASE              (0xdeadbeef)
+#define BCM_6345_USBDMA_BASE            (0xfffe2800)
+#define BCM_6345_ENET0_BASE             (0xfffe1800)
+#define BCM_6345_ENETDMA_BASE           (0xfffe2800)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2840)
+#define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
+#define BCM_6345_ENETSW_BASE            (0xdeadbeef)
+#define BCM_6345_PCMCIA_BASE            (0xfffe2028)
+#define BCM_6345_MPI_BASE               (0xfffe2000)
+#define BCM_6345_PCIE_BASE              (0xdeadbeef)
+#define BCM_6345_OHCI0_BASE             (0xfffe2100)
+#define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
+#define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6345_USBD_BASE              (0xdeadbeef)
+#define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6345_DSL_BASE               (0xdeadbeef)
+#define BCM_6345_UBUS_BASE              (0xdeadbeef)
+#define BCM_6345_ENET1_BASE             (0xdeadbeef)
+#define BCM_6345_EHCI0_BASE             (0xdeadbeef)
+#define BCM_6345_SDRAM_BASE             (0xfffe2300)
+#define BCM_6345_MEMC_BASE              (0xdeadbeef)
+#define BCM_6345_DDR_BASE               (0xdeadbeef)
+#define BCM_6345_M2M_BASE               (0xdeadbeef)
+#define BCM_6345_ATM_BASE               (0xfffe4000)
+#define BCM_6345_XTM_BASE               (0xdeadbeef)
+#define BCM_6345_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6345_PCM_BASE               (0xdeadbeef)
+#define BCM_6345_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6345_RNG_BASE               (0xdeadbeef)
+#define BCM_6345_MISC_BASE              (0xdeadbeef)
+
+/*
+ * 6348 register sets base address
+ */
+#define BCM_6348_DSL_LMEM_BASE          (0xfff00000)
+#define BCM_6348_PERF_BASE              (0xfffe0000)
+#define BCM_6348_TIMER_BASE             (0xfffe0200)
+#define BCM_6348_WDT_BASE               (0xfffe021c)
+#define BCM_6348_UART0_BASE             (0xfffe0300)
+#define BCM_6348_UART1_BASE             (0xdeadbeef)
+#define BCM_6348_GPIO_BASE              (0xfffe0400)
+#define BCM_6348_SPI_BASE               (0xfffe0c00)
+#define BCM_6348_HSSPI_BASE             (0xdeadbeef)
+#define BCM_6348_UDC0_BASE              (0xfffe1000)
+#define BCM_6348_USBDMA_BASE            (0xdeadbeef)
+#define BCM_6348_OHCI0_BASE             (0xfffe1b00)
+#define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
+#define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6348_USBD_BASE              (0xdeadbeef)
+#define BCM_6348_MPI_BASE               (0xfffe2000)
+#define BCM_6348_PCMCIA_BASE            (0xfffe2054)
+#define BCM_6348_PCIE_BASE              (0xdeadbeef)
+#define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6348_M2M_BASE               (0xfffe2800)
+#define BCM_6348_DSL_BASE               (0xfffe3000)
+#define BCM_6348_ENET0_BASE             (0xfffe6000)
+#define BCM_6348_ENET1_BASE             (0xfffe6800)
+#define BCM_6348_ENETDMA_BASE           (0xfffe7000)
+#define BCM_6348_ENETDMAC_BASE          (0xfffe7100)
+#define BCM_6348_ENETDMAS_BASE          (0xfffe7200)
+#define BCM_6348_ENETSW_BASE            (0xdeadbeef)
+#define BCM_6348_EHCI0_BASE             (0xdeadbeef)
+#define BCM_6348_SDRAM_BASE             (0xfffe2300)
+#define BCM_6348_MEMC_BASE              (0xdeadbeef)
+#define BCM_6348_DDR_BASE               (0xdeadbeef)
+#define BCM_6348_ATM_BASE               (0xfffe4000)
+#define BCM_6348_XTM_BASE               (0xdeadbeef)
+#define BCM_6348_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6348_PCM_BASE               (0xdeadbeef)
+#define BCM_6348_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6348_RNG_BASE               (0xdeadbeef)
+#define BCM_6348_MISC_BASE              (0xdeadbeef)
+
+/*
+ * 6358 register sets base address
+ */
+#define BCM_6358_DSL_LMEM_BASE          (0xfff00000)
+#define BCM_6358_PERF_BASE              (0xfffe0000)
+#define BCM_6358_TIMER_BASE             (0xfffe0040)
+#define BCM_6358_WDT_BASE               (0xfffe005c)
+#define BCM_6358_UART0_BASE             (0xfffe0100)
+#define BCM_6358_UART1_BASE             (0xfffe0120)
+#define BCM_6358_GPIO_BASE              (0xfffe0080)
+#define BCM_6358_SPI_BASE               (0xfffe0800)
+#define BCM_6358_HSSPI_BASE             (0xdeadbeef)
+#define BCM_6358_UDC0_BASE              (0xfffe0800)
+#define BCM_6358_USBDMA_BASE            (0xdeadbeef)
+#define BCM_6358_OHCI0_BASE             (0xfffe1400)
+#define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
+#define BCM_6358_USBD_BASE              (0xdeadbeef)
+#define BCM_6358_MPI_BASE               (0xfffe1000)
+#define BCM_6358_PCMCIA_BASE            (0xfffe1054)
+#define BCM_6358_PCIE_BASE              (0xdeadbeef)
+#define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6358_M2M_BASE               (0xdeadbeef)
+#define BCM_6358_DSL_BASE               (0xfffe3000)
+#define BCM_6358_ENET0_BASE             (0xfffe4000)
+#define BCM_6358_ENET1_BASE             (0xfffe4800)
+#define BCM_6358_ENETDMA_BASE           (0xfffe5000)
+#define BCM_6358_ENETDMAC_BASE          (0xfffe5100)
+#define BCM_6358_ENETDMAS_BASE          (0xfffe5200)
+#define BCM_6358_ENETSW_BASE            (0xdeadbeef)
+#define BCM_6358_EHCI0_BASE             (0xfffe1300)
+#define BCM_6358_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6358_MEMC_BASE              (0xfffe1200)
+#define BCM_6358_DDR_BASE               (0xfffe12a0)
+#define BCM_6358_ATM_BASE               (0xfffe2000)
+#define BCM_6358_XTM_BASE               (0xdeadbeef)
+#define BCM_6358_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6358_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6358_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6358_PCM_BASE               (0xfffe1600)
+#define BCM_6358_PCMDMA_BASE            (0xfffe1800)
+#define BCM_6358_PCMDMAC_BASE           (0xfffe1900)
+#define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
+#define BCM_6358_RNG_BASE               (0xdeadbeef)
+#define BCM_6358_MISC_BASE              (0xdeadbeef)
+
+
+/*
+ * 6362 register sets base address
+ */
+#define BCM_6362_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6362_PERF_BASE              (0xb0000000)
+#define BCM_6362_TIMER_BASE             (0xb0000040)
+#define BCM_6362_WDT_BASE               (0xb000005c)
+#define BCM_6362_UART0_BASE             (0xb0000100)
+#define BCM_6362_UART1_BASE             (0xb0000120)
+#define BCM_6362_GPIO_BASE              (0xb0000080)
+#define BCM_6362_SPI_BASE               (0xb0000800)
+#define BCM_6362_HSSPI_BASE             (0xb0001000)
+#define BCM_6362_UDC0_BASE              (0xdeadbeef)
+#define BCM_6362_USBDMA_BASE            (0xb000c000)
+#define BCM_6362_OHCI0_BASE             (0xb0002600)
+#define BCM_6362_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6362_USBH_PRIV_BASE         (0xb0002700)
+#define BCM_6362_USBD_BASE              (0xb0002400)
+#define BCM_6362_MPI_BASE               (0xdeadbeef)
+#define BCM_6362_PCMCIA_BASE            (0xdeadbeef)
+#define BCM_6362_PCIE_BASE              (0xb0e40000)
+#define BCM_6362_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6362_DSL_BASE               (0xdeadbeef)
+#define BCM_6362_UBUS_BASE              (0xdeadbeef)
+#define BCM_6362_ENET0_BASE             (0xdeadbeef)
+#define BCM_6362_ENET1_BASE             (0xdeadbeef)
+#define BCM_6362_ENETDMA_BASE           (0xb000d800)
+#define BCM_6362_ENETDMAC_BASE          (0xb000da00)
+#define BCM_6362_ENETDMAS_BASE          (0xb000dc00)
+#define BCM_6362_ENETSW_BASE            (0xb0e00000)
+#define BCM_6362_EHCI0_BASE             (0xb0002500)
+#define BCM_6362_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6362_MEMC_BASE              (0xdeadbeef)
+#define BCM_6362_DDR_BASE               (0xb0003000)
+#define BCM_6362_M2M_BASE               (0xdeadbeef)
+#define BCM_6362_ATM_BASE               (0xdeadbeef)
+#define BCM_6362_XTM_BASE               (0xb0007800)
+#define BCM_6362_XTMDMA_BASE            (0xb000b800)
+#define BCM_6362_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6362_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6362_PCM_BASE               (0xb000a800)
+#define BCM_6362_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6362_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6362_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6362_RNG_BASE               (0xdeadbeef)
+#define BCM_6362_MISC_BASE              (0xb0001800)
+
+#define BCM_6362_NAND_REG_BASE          (0xb0000200)
+#define BCM_6362_NAND_CACHE_BASE        (0xb0000600)
+#define BCM_6362_LED_BASE               (0xb0001900)
+#define BCM_6362_IPSEC_BASE             (0xb0002800)
+#define BCM_6362_IPSEC_DMA_BASE         (0xb000d000)
+#define BCM_6362_WLAN_CHIPCOMMON_BASE   (0xb0004000)
+#define BCM_6362_WLAN_D11_BASE          (0xb0005000)
+#define BCM_6362_WLAN_SHIM_BASE         (0xb0007000)
+
+/*
+ * 6368 register sets base address
+ */
+#define BCM_6368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6368_PERF_BASE              (0xb0000000)
+#define BCM_6368_TIMER_BASE             (0xb0000040)
+#define BCM_6368_WDT_BASE               (0xb000005c)
+#define BCM_6368_UART0_BASE             (0xb0000100)
+#define BCM_6368_UART1_BASE             (0xb0000120)
+#define BCM_6368_GPIO_BASE              (0xb0000080)
+#define BCM_6368_SPI_BASE               (0xb0000800)
+#define BCM_6368_HSSPI_BASE             (0xdeadbeef)
+#define BCM_6368_UDC0_BASE              (0xdeadbeef)
+#define BCM_6368_USBDMA_BASE            (0xb0004800)
+#define BCM_6368_OHCI0_BASE             (0xb0001600)
+#define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
+#define BCM_6368_USBD_BASE              (0xb0001400)
+#define BCM_6368_MPI_BASE               (0xb0001000)
+#define BCM_6368_PCMCIA_BASE            (0xb0001054)
+#define BCM_6368_PCIE_BASE              (0xdeadbeef)
+#define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6368_M2M_BASE               (0xdeadbeef)
+#define BCM_6368_DSL_BASE               (0xdeadbeef)
+#define BCM_6368_ENET0_BASE             (0xdeadbeef)
+#define BCM_6368_ENET1_BASE             (0xdeadbeef)
+#define BCM_6368_ENETDMA_BASE           (0xb0006800)
+#define BCM_6368_ENETDMAC_BASE          (0xb0006a00)
+#define BCM_6368_ENETDMAS_BASE          (0xb0006c00)
+#define BCM_6368_ENETSW_BASE            (0xb0f00000)
+#define BCM_6368_EHCI0_BASE             (0xb0001500)
+#define BCM_6368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6368_MEMC_BASE              (0xb0001200)
+#define BCM_6368_DDR_BASE               (0xb0001280)
+#define BCM_6368_ATM_BASE               (0xdeadbeef)
+#define BCM_6368_XTM_BASE               (0xb0001800)
+#define BCM_6368_XTMDMA_BASE            (0xb0005000)
+#define BCM_6368_XTMDMAC_BASE           (0xb0005200)
+#define BCM_6368_XTMDMAS_BASE           (0xb0005400)
+#define BCM_6368_PCM_BASE               (0xb0004000)
+#define BCM_6368_PCMDMA_BASE            (0xb0005800)
+#define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
+#define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
+#define BCM_6368_RNG_BASE               (0xb0004180)
+#define BCM_6368_MISC_BASE              (0xdeadbeef)
+
+
+extern const unsigned long *bcm63xx_regs_base;
+
+#define __GEN_CPU_REGS_TABLE(__cpu)                                     \
+        [RSET_DSL_LMEM]         = BCM_## __cpu ##_DSL_LMEM_BASE,        \
+        [RSET_PERF]             = BCM_## __cpu ##_PERF_BASE,            \
+        [RSET_TIMER]            = BCM_## __cpu ##_TIMER_BASE,           \
+        [RSET_WDT]              = BCM_## __cpu ##_WDT_BASE,             \
+        [RSET_UART0]            = BCM_## __cpu ##_UART0_BASE,           \
+        [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
+        [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
+        [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
+        [RSET_HSSPI]            = BCM_## __cpu ##_HSSPI_BASE,           \
+        [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
+        [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
+        [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
+        [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
+        [RSET_USBD]             = BCM_## __cpu ##_USBD_BASE,            \
+        [RSET_USBDMA]           = BCM_## __cpu ##_USBDMA_BASE,          \
+        [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
+        [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
+        [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
+        [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
+        [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
+        [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
+        [RSET_ENETDMA]          = BCM_## __cpu ##_ENETDMA_BASE,         \
+        [RSET_ENETDMAC]         = BCM_## __cpu ##_ENETDMAC_BASE,        \
+        [RSET_ENETDMAS]         = BCM_## __cpu ##_ENETDMAS_BASE,        \
+        [RSET_ENETSW]           = BCM_## __cpu ##_ENETSW_BASE,          \
+        [RSET_EHCI0]            = BCM_## __cpu ##_EHCI0_BASE,           \
+        [RSET_SDRAM]            = BCM_## __cpu ##_SDRAM_BASE,           \
+        [RSET_MEMC]             = BCM_## __cpu ##_MEMC_BASE,            \
+        [RSET_DDR]              = BCM_## __cpu ##_DDR_BASE,             \
+        [RSET_M2M]              = BCM_## __cpu ##_M2M_BASE,             \
+        [RSET_ATM]              = BCM_## __cpu ##_ATM_BASE,             \
+        [RSET_XTM]              = BCM_## __cpu ##_XTM_BASE,             \
+        [RSET_XTMDMA]           = BCM_## __cpu ##_XTMDMA_BASE,          \
+        [RSET_XTMDMAC]          = BCM_## __cpu ##_XTMDMAC_BASE,         \
+        [RSET_XTMDMAS]          = BCM_## __cpu ##_XTMDMAS_BASE,         \
+        [RSET_PCM]              = BCM_## __cpu ##_PCM_BASE,             \
+        [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
+        [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
+        [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
+        [RSET_RNG]              = BCM_## __cpu ##_RNG_BASE,             \
+        [RSET_MISC]             = BCM_## __cpu ##_MISC_BASE,            \
+
+
+static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
+{
+        return bcm63xx_regs_base[set];
+}
+
+/*
+ * IRQ number changes across CPU too
+ */
+enum bcm63xx_irq {
+        IRQ_TIMER = 0,
+        IRQ_SPI,
+        IRQ_UART0,
+        IRQ_UART1,
+        IRQ_DSL,
+        IRQ_ENET0,
+        IRQ_ENET1,
+        IRQ_ENET_PHY,
+        IRQ_HSSPI,
+        IRQ_OHCI0,
+        IRQ_EHCI0,
+        IRQ_USBD,
+        IRQ_USBD_RXDMA0,
+        IRQ_USBD_TXDMA0,
+        IRQ_USBD_RXDMA1,
+        IRQ_USBD_TXDMA1,
+        IRQ_USBD_RXDMA2,
+        IRQ_USBD_TXDMA2,
+        IRQ_ENET0_RXDMA,
+        IRQ_ENET0_TXDMA,
+        IRQ_ENET1_RXDMA,
+        IRQ_ENET1_TXDMA,
+        IRQ_PCI,
+        IRQ_PCMCIA,
+        IRQ_ATM,
+        IRQ_ENETSW_RXDMA0,
+        IRQ_ENETSW_RXDMA1,
+        IRQ_ENETSW_RXDMA2,
+        IRQ_ENETSW_RXDMA3,
+        IRQ_ENETSW_TXDMA0,
+        IRQ_ENETSW_TXDMA1,
+        IRQ_ENETSW_TXDMA2,
+        IRQ_ENETSW_TXDMA3,
+        IRQ_XTM,
+        IRQ_XTM_DMA0,
+};
+
+/*
+ * 3368 irqs
+ */
+#define BCM_3368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_3368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_3368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_3368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_3368_DSL_IRQ                0
+#define BCM_3368_UDC0_IRQ               0
+#define BCM_3368_OHCI0_IRQ              0
+#define BCM_3368_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_3368_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_3368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_3368_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
+#define BCM_3368_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
+#define BCM_3368_HSSPI_IRQ              0
+#define BCM_3368_EHCI0_IRQ              0
+#define BCM_3368_USBD_IRQ               0
+#define BCM_3368_USBD_RXDMA0_IRQ        0
+#define BCM_3368_USBD_TXDMA0_IRQ        0
+#define BCM_3368_USBD_RXDMA1_IRQ        0
+#define BCM_3368_USBD_TXDMA1_IRQ        0
+#define BCM_3368_USBD_RXDMA2_IRQ        0
+#define BCM_3368_USBD_TXDMA2_IRQ        0
+#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
+#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
+#define BCM_3368_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
+#define BCM_3368_PCMCIA_IRQ             0
+#define BCM_3368_ATM_IRQ                0
+#define BCM_3368_ENETSW_RXDMA0_IRQ      0
+#define BCM_3368_ENETSW_RXDMA1_IRQ      0
+#define BCM_3368_ENETSW_RXDMA2_IRQ      0
+#define BCM_3368_ENETSW_RXDMA3_IRQ      0
+#define BCM_3368_ENETSW_TXDMA0_IRQ      0
+#define BCM_3368_ENETSW_TXDMA1_IRQ      0
+#define BCM_3368_ENETSW_TXDMA2_IRQ      0
+#define BCM_3368_ENETSW_TXDMA3_IRQ      0
+#define BCM_3368_XTM_IRQ                0
+#define BCM_3368_XTM_DMA0_IRQ           0
+
+#define BCM_3368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_3368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_3368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_3368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+
+/*
+ * 6328 irqs
+ */
+#define BCM_6328_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6328_TIMER_IRQ              (IRQ_INTERNAL_BASE + 31)
+#define BCM_6328_SPI_IRQ                0
+#define BCM_6328_UART0_IRQ              (IRQ_INTERNAL_BASE + 28)
+#define BCM_6328_UART1_IRQ              (BCM_6328_HIGH_IRQ_BASE + 7)
+#define BCM_6328_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6328_UDC0_IRQ               0
+#define BCM_6328_ENET0_IRQ              0
+#define BCM_6328_ENET1_IRQ              0
+#define BCM_6328_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6328_HSSPI_IRQ              (IRQ_INTERNAL_BASE + 29)
+#define BCM_6328_OHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 9)
+#define BCM_6328_EHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 10)
+#define BCM_6328_USBD_IRQ               (IRQ_INTERNAL_BASE + 4)
+#define BCM_6328_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 5)
+#define BCM_6328_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 6)
+#define BCM_6328_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 7)
+#define BCM_6328_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 8)
+#define BCM_6328_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 9)
+#define BCM_6328_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 10)
+#define BCM_6328_PCMCIA_IRQ             0
+#define BCM_6328_ENET0_RXDMA_IRQ        0
+#define BCM_6328_ENET0_TXDMA_IRQ        0
+#define BCM_6328_ENET1_RXDMA_IRQ        0
+#define BCM_6328_ENET1_TXDMA_IRQ        0
+#define BCM_6328_PCI_IRQ                (IRQ_INTERNAL_BASE + 23)
+#define BCM_6328_ATM_IRQ                0
+#define BCM_6328_ENETSW_RXDMA0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 0)
+#define BCM_6328_ENETSW_RXDMA1_IRQ      (BCM_6328_HIGH_IRQ_BASE + 1)
+#define BCM_6328_ENETSW_RXDMA2_IRQ      (BCM_6328_HIGH_IRQ_BASE + 2)
+#define BCM_6328_ENETSW_RXDMA3_IRQ      (BCM_6328_HIGH_IRQ_BASE + 3)
+#define BCM_6328_ENETSW_TXDMA0_IRQ      0
+#define BCM_6328_ENETSW_TXDMA1_IRQ      0
+#define BCM_6328_ENETSW_TXDMA2_IRQ      0
+#define BCM_6328_ENETSW_TXDMA3_IRQ      0
+#define BCM_6328_XTM_IRQ                (BCM_6328_HIGH_IRQ_BASE + 31)
+#define BCM_6328_XTM_DMA0_IRQ           (BCM_6328_HIGH_IRQ_BASE + 11)
+
+#define BCM_6328_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 2)
+#define BCM_6328_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 3)
+#define BCM_6328_EXT_IRQ0               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6328_EXT_IRQ1               (IRQ_INTERNAL_BASE + 25)
+#define BCM_6328_EXT_IRQ2               (IRQ_INTERNAL_BASE + 26)
+#define BCM_6328_EXT_IRQ3               (IRQ_INTERNAL_BASE + 27)
+
+/*
+ * 6338 irqs
+ */
+#define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6338_UART1_IRQ              0
+#define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET1_IRQ              0
+#define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6338_HSSPI_IRQ              0
+#define BCM_6338_OHCI0_IRQ              0
+#define BCM_6338_EHCI0_IRQ              0
+#define BCM_6338_USBD_IRQ               0
+#define BCM_6338_USBD_RXDMA0_IRQ        0
+#define BCM_6338_USBD_TXDMA0_IRQ        0
+#define BCM_6338_USBD_RXDMA1_IRQ        0
+#define BCM_6338_USBD_TXDMA1_IRQ        0
+#define BCM_6338_USBD_RXDMA2_IRQ        0
+#define BCM_6338_USBD_TXDMA2_IRQ        0
+#define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
+#define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
+#define BCM_6338_ENET1_RXDMA_IRQ        0
+#define BCM_6338_ENET1_TXDMA_IRQ        0
+#define BCM_6338_PCI_IRQ                0
+#define BCM_6338_PCMCIA_IRQ             0
+#define BCM_6338_ATM_IRQ                0
+#define BCM_6338_ENETSW_RXDMA0_IRQ      0
+#define BCM_6338_ENETSW_RXDMA1_IRQ      0
+#define BCM_6338_ENETSW_RXDMA2_IRQ      0
+#define BCM_6338_ENETSW_RXDMA3_IRQ      0
+#define BCM_6338_ENETSW_TXDMA0_IRQ      0
+#define BCM_6338_ENETSW_TXDMA1_IRQ      0
+#define BCM_6338_ENETSW_TXDMA2_IRQ      0
+#define BCM_6338_ENETSW_TXDMA3_IRQ      0
+#define BCM_6338_XTM_IRQ                0
+#define BCM_6338_XTM_DMA0_IRQ           0
+
+/*
+ * 6345 irqs
+ */
+#define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_SPI_IRQ                0
+#define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_UART1_IRQ              0
+#define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
+#define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET1_IRQ              0
+#define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6345_HSSPI_IRQ              0
+#define BCM_6345_OHCI0_IRQ              0
+#define BCM_6345_EHCI0_IRQ              0
+#define BCM_6345_USBD_IRQ               0
+#define BCM_6345_USBD_RXDMA0_IRQ        0
+#define BCM_6345_USBD_TXDMA0_IRQ        0
+#define BCM_6345_USBD_RXDMA1_IRQ        0
+#define BCM_6345_USBD_TXDMA1_IRQ        0
+#define BCM_6345_USBD_RXDMA2_IRQ        0
+#define BCM_6345_USBD_TXDMA2_IRQ        0
+#define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
+#define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
+#define BCM_6345_ENET1_RXDMA_IRQ        0
+#define BCM_6345_ENET1_TXDMA_IRQ        0
+#define BCM_6345_PCI_IRQ                0
+#define BCM_6345_PCMCIA_IRQ             0
+#define BCM_6345_ATM_IRQ                0
+#define BCM_6345_ENETSW_RXDMA0_IRQ      0
+#define BCM_6345_ENETSW_RXDMA1_IRQ      0
+#define BCM_6345_ENETSW_RXDMA2_IRQ      0
+#define BCM_6345_ENETSW_RXDMA3_IRQ      0
+#define BCM_6345_ENETSW_TXDMA0_IRQ      0
+#define BCM_6345_ENETSW_TXDMA1_IRQ      0
+#define BCM_6345_ENETSW_TXDMA2_IRQ      0
+#define BCM_6345_ENETSW_TXDMA3_IRQ      0
+#define BCM_6345_XTM_IRQ                0
+#define BCM_6345_XTM_DMA0_IRQ           0
+
+/*
+ * 6348 irqs
+ */
+#define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6348_UART1_IRQ              0
+#define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6348_HSSPI_IRQ              0
+#define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
+#define BCM_6348_EHCI0_IRQ              0
+#define BCM_6348_USBD_IRQ               0
+#define BCM_6348_USBD_RXDMA0_IRQ        0
+#define BCM_6348_USBD_TXDMA0_IRQ        0
+#define BCM_6348_USBD_RXDMA1_IRQ        0
+#define BCM_6348_USBD_TXDMA1_IRQ        0
+#define BCM_6348_USBD_RXDMA2_IRQ        0
+#define BCM_6348_USBD_TXDMA2_IRQ        0
+#define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
+#define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
+#define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
+#define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
+#define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_ATM_IRQ                (IRQ_INTERNAL_BASE + 5)
+#define BCM_6348_ENETSW_RXDMA0_IRQ      0
+#define BCM_6348_ENETSW_RXDMA1_IRQ      0
+#define BCM_6348_ENETSW_RXDMA2_IRQ      0
+#define BCM_6348_ENETSW_RXDMA3_IRQ      0
+#define BCM_6348_ENETSW_TXDMA0_IRQ      0
+#define BCM_6348_ENETSW_TXDMA1_IRQ      0
+#define BCM_6348_ENETSW_TXDMA2_IRQ      0
+#define BCM_6348_ENETSW_TXDMA3_IRQ      0
+#define BCM_6348_XTM_IRQ                0
+#define BCM_6348_XTM_DMA0_IRQ           0
+
+/*
+ * 6358 irqs
+ */
+#define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6358_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
+#define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6358_HSSPI_IRQ              0
+#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6358_USBD_IRQ               0
+#define BCM_6358_USBD_RXDMA0_IRQ        0
+#define BCM_6358_USBD_TXDMA0_IRQ        0
+#define BCM_6358_USBD_RXDMA1_IRQ        0
+#define BCM_6358_USBD_TXDMA1_IRQ        0
+#define BCM_6358_USBD_RXDMA2_IRQ        0
+#define BCM_6358_USBD_TXDMA2_IRQ        0
+#define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
+#define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
+#define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
+#define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
+#define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
+#define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_ATM_IRQ                (IRQ_INTERNAL_BASE + 19)
+#define BCM_6358_ENETSW_RXDMA0_IRQ      0
+#define BCM_6358_ENETSW_RXDMA1_IRQ      0
+#define BCM_6358_ENETSW_RXDMA2_IRQ      0
+#define BCM_6358_ENETSW_RXDMA3_IRQ      0
+#define BCM_6358_ENETSW_TXDMA0_IRQ      0
+#define BCM_6358_ENETSW_TXDMA1_IRQ      0
+#define BCM_6358_ENETSW_TXDMA2_IRQ      0
+#define BCM_6358_ENETSW_TXDMA3_IRQ      0
+#define BCM_6358_XTM_IRQ                0
+#define BCM_6358_XTM_DMA0_IRQ           0
+
+#define BCM_6358_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 23)
+#define BCM_6358_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_6358_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_6358_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_6358_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+/*
+ * 6362 irqs
+ */
+#define BCM_6362_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6362_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6362_SPI_IRQ                (IRQ_INTERNAL_BASE + 2)
+#define BCM_6362_UART0_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6362_UART1_IRQ              (IRQ_INTERNAL_BASE + 4)
+#define BCM_6362_DSL_IRQ                (IRQ_INTERNAL_BASE + 28)
+#define BCM_6362_UDC0_IRQ               0
+#define BCM_6362_ENET0_IRQ              0
+#define BCM_6362_ENET1_IRQ              0
+#define BCM_6362_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 14)
+#define BCM_6362_HSSPI_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6362_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 9)
+#define BCM_6362_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6362_USBD_IRQ               (IRQ_INTERNAL_BASE + 11)
+#define BCM_6362_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 20)
+#define BCM_6362_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 21)
+#define BCM_6362_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 22)
+#define BCM_6362_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 23)
+#define BCM_6362_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 24)
+#define BCM_6362_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 25)
+#define BCM_6362_PCMCIA_IRQ             0
+#define BCM_6362_ENET0_RXDMA_IRQ        0
+#define BCM_6362_ENET0_TXDMA_IRQ        0
+#define BCM_6362_ENET1_RXDMA_IRQ        0
+#define BCM_6362_ENET1_TXDMA_IRQ        0
+#define BCM_6362_PCI_IRQ                (IRQ_INTERNAL_BASE + 30)
+#define BCM_6362_ATM_IRQ                0
+#define BCM_6362_ENETSW_RXDMA0_IRQ      (BCM_6362_HIGH_IRQ_BASE + 0)
+#define BCM_6362_ENETSW_RXDMA1_IRQ      (BCM_6362_HIGH_IRQ_BASE + 1)
+#define BCM_6362_ENETSW_RXDMA2_IRQ      (BCM_6362_HIGH_IRQ_BASE + 2)
+#define BCM_6362_ENETSW_RXDMA3_IRQ      (BCM_6362_HIGH_IRQ_BASE + 3)
+#define BCM_6362_ENETSW_TXDMA0_IRQ      0
+#define BCM_6362_ENETSW_TXDMA1_IRQ      0
+#define BCM_6362_ENETSW_TXDMA2_IRQ      0
+#define BCM_6362_ENETSW_TXDMA3_IRQ      0
+#define BCM_6362_XTM_IRQ                0
+#define BCM_6362_XTM_DMA0_IRQ           (BCM_6362_HIGH_IRQ_BASE + 12)
+
+#define BCM_6362_RING_OSC_IRQ           (IRQ_INTERNAL_BASE + 1)
+#define BCM_6362_WLAN_GPIO_IRQ          (IRQ_INTERNAL_BASE + 6)
+#define BCM_6362_WLAN_IRQ               (IRQ_INTERNAL_BASE + 7)
+#define BCM_6362_IPSEC_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6362_NAND_IRQ               (IRQ_INTERNAL_BASE + 12)
+#define BCM_6362_PCM_IRQ                (IRQ_INTERNAL_BASE + 13)
+#define BCM_6362_DG_IRQ                 (IRQ_INTERNAL_BASE + 15)
+#define BCM_6362_EPHY_ENERGY0_IRQ       (IRQ_INTERNAL_BASE + 16)
+#define BCM_6362_EPHY_ENERGY1_IRQ       (IRQ_INTERNAL_BASE + 17)
+#define BCM_6362_EPHY_ENERGY2_IRQ       (IRQ_INTERNAL_BASE + 18)
+#define BCM_6362_EPHY_ENERGY3_IRQ       (IRQ_INTERNAL_BASE + 19)
+#define BCM_6362_IPSEC_DMA0_IRQ         (IRQ_INTERNAL_BASE + 26)
+#define BCM_6362_IPSEC_DMA1_IRQ         (IRQ_INTERNAL_BASE + 27)
+#define BCM_6362_FAP0_IRQ               (IRQ_INTERNAL_BASE + 29)
+#define BCM_6362_PCM_DMA0_IRQ           (BCM_6362_HIGH_IRQ_BASE + 4)
+#define BCM_6362_PCM_DMA1_IRQ           (BCM_6362_HIGH_IRQ_BASE + 5)
+#define BCM_6362_DECT0_IRQ              (BCM_6362_HIGH_IRQ_BASE + 6)
+#define BCM_6362_DECT1_IRQ              (BCM_6362_HIGH_IRQ_BASE + 7)
+#define BCM_6362_EXT_IRQ0               (BCM_6362_HIGH_IRQ_BASE + 8)
+#define BCM_6362_EXT_IRQ1               (BCM_6362_HIGH_IRQ_BASE + 9)
+#define BCM_6362_EXT_IRQ2               (BCM_6362_HIGH_IRQ_BASE + 10)
+#define BCM_6362_EXT_IRQ3               (BCM_6362_HIGH_IRQ_BASE + 11)
+
+/*
+ * 6368 irqs
+ */
+#define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
+#define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6368_ENET0_IRQ              0
+#define BCM_6368_ENET1_IRQ              0
+#define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_HSSPI_IRQ              0
+#define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_USBD_IRQ               (IRQ_INTERNAL_BASE + 8)
+#define BCM_6368_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 26)
+#define BCM_6368_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 27)
+#define BCM_6368_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 28)
+#define BCM_6368_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 29)
+#define BCM_6368_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 30)
+#define BCM_6368_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 31)
+#define BCM_6368_PCMCIA_IRQ             0
+#define BCM_6368_ENET0_RXDMA_IRQ        0
+#define BCM_6368_ENET0_TXDMA_IRQ        0
+#define BCM_6368_ENET1_RXDMA_IRQ        0
+#define BCM_6368_ENET1_TXDMA_IRQ        0
+#define BCM_6368_PCI_IRQ                (IRQ_INTERNAL_BASE + 13)
+#define BCM_6368_ATM_IRQ                0
+#define BCM_6368_ENETSW_RXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 0)
+#define BCM_6368_ENETSW_RXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 1)
+#define BCM_6368_ENETSW_RXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 2)
+#define BCM_6368_ENETSW_RXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 3)
+#define BCM_6368_ENETSW_TXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 4)
+#define BCM_6368_ENETSW_TXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 5)
+#define BCM_6368_ENETSW_TXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 6)
+#define BCM_6368_ENETSW_TXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 7)
+#define BCM_6368_XTM_IRQ                (IRQ_INTERNAL_BASE + 11)
+#define BCM_6368_XTM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 8)
+
+#define BCM_6368_PCM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 30)
+#define BCM_6368_PCM_DMA1_IRQ           (BCM_6368_HIGH_IRQ_BASE + 31)
+#define BCM_6368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 20)
+#define BCM_6368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 21)
+#define BCM_6368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 22)
+#define BCM_6368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 23)
+#define BCM_6368_EXT_IRQ4               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6368_EXT_IRQ5               (IRQ_INTERNAL_BASE + 25)
+
+extern const int *bcm63xx_irqs;
+
+#define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
+        [IRQ_TIMER]             = BCM_## __cpu ##_TIMER_IRQ,            \
+        [IRQ_SPI]               = BCM_## __cpu ##_SPI_IRQ,              \
+        [IRQ_UART0]             = BCM_## __cpu ##_UART0_IRQ,            \
+        [IRQ_UART1]             = BCM_## __cpu ##_UART1_IRQ,            \
+        [IRQ_DSL]               = BCM_## __cpu ##_DSL_IRQ,              \
+        [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
+        [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
+        [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
+        [IRQ_HSSPI]             = BCM_## __cpu ##_HSSPI_IRQ,            \
+        [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
+        [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+        [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
+        [IRQ_USBD_RXDMA0]       = BCM_## __cpu ##_USBD_RXDMA0_IRQ,      \
+        [IRQ_USBD_TXDMA0]       = BCM_## __cpu ##_USBD_TXDMA0_IRQ,      \
+        [IRQ_USBD_RXDMA1]       = BCM_## __cpu ##_USBD_RXDMA1_IRQ,      \
+        [IRQ_USBD_TXDMA1]       = BCM_## __cpu ##_USBD_TXDMA1_IRQ,      \
+        [IRQ_USBD_RXDMA2]       = BCM_## __cpu ##_USBD_RXDMA2_IRQ,      \
+        [IRQ_USBD_TXDMA2]       = BCM_## __cpu ##_USBD_TXDMA2_IRQ,      \
+        [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
+        [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
+        [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
+        [IRQ_ENET1_TXDMA]       = BCM_## __cpu ##_ENET1_TXDMA_IRQ,      \
+        [IRQ_PCI]               = BCM_## __cpu ##_PCI_IRQ,              \
+        [IRQ_PCMCIA]            = BCM_## __cpu ##_PCMCIA_IRQ,           \
+        [IRQ_ATM]               = BCM_## __cpu ##_ATM_IRQ,              \
+        [IRQ_ENETSW_RXDMA0]     = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,    \
+        [IRQ_ENETSW_RXDMA1]     = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,    \
+        [IRQ_ENETSW_RXDMA2]     = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,    \
+        [IRQ_ENETSW_RXDMA3]     = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,    \
+        [IRQ_ENETSW_TXDMA0]     = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,    \
+        [IRQ_ENETSW_TXDMA1]     = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,    \
+        [IRQ_ENETSW_TXDMA2]     = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,    \
+        [IRQ_ENETSW_TXDMA3]     = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,    \
+        [IRQ_XTM]               = BCM_## __cpu ##_XTM_IRQ,              \
+        [IRQ_XTM_DMA0]          = BCM_## __cpu ##_XTM_DMA0_IRQ,         \
+
+static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
+{
+        return bcm63xx_irqs[irq];
+}
+
+/*
+ * return installed memory size
+ */
+unsigned int bcm63xx_get_memory_size(void);
+
+void bcm63xx_machine_halt(void);
+
+void bcm63xx_machine_reboot(void);
+
+#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
new file mode 100644
index 000000000..1c634d7c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_CS_H
+#define BCM63XX_CS_H
+
+int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
+int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
+                           unsigned int setup, unsigned int hold);
+int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
+int bcm63xx_set_cs_status(unsigned int cs, int enable);
+
+#endif /* !BCM63XX_CS_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
new file mode 100644
index 000000000..da39e4d32
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_ENET_H_
+#define BCM63XX_DEV_ENET_H_
+
+#include <linux/if_ether.h>
+#include <linux/init.h>
+
+#include <bcm63xx_regs.h>
+
+/*
+ * on board ethernet platform data
+ */
+struct bcm63xx_enet_platform_data {
+        char mac_addr[ETH_ALEN];
+
+        int has_phy;
+
+        /* if has_phy, then set use_internal_phy */
+        int use_internal_phy;
+
+        /* or fill phy info to use an external one */
+        int phy_id;
+        int has_phy_interrupt;
+        int phy_interrupt;
+
+        /* if has_phy, use autonegotiated pause parameters or force
+         * them */
+        int pause_auto;
+        int pause_rx;
+        int pause_tx;
+
+        /* if !has_phy, set desired forced speed/duplex */
+        int force_speed_100;
+        int force_duplex_full;
+
+        /* if !has_phy, set callback to perform mii device
+         * init/remove */
+        int (*mii_config)(struct net_device *dev, int probe,
+                          int (*mii_read)(struct net_device *dev,
+                                          int phy_id, int reg),
+                          void (*mii_write)(struct net_device *dev,
+                                            int phy_id, int reg, int val));
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA descriptor shift */
+        unsigned int dma_desc_shift;
+
+        /* dma channel ids */
+        int rx_chan;
+        int tx_chan;
+};
+
+/*
+ * on board ethernet switch platform data
+ */
+#define ENETSW_MAX_PORT 8
+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
+
+#define ENETSW_RGMII_PORT0      4
+
+struct bcm63xx_enetsw_port {
+        int             used;
+        int             phy_id;
+
+        int             bypass_link;
+        int             force_speed;
+        int             force_duplex_full;
+
+        const char      *name;
+};
+
+struct bcm63xx_enetsw_platform_data {
+        char mac_addr[ETH_ALEN];
+        int num_ports;
+        struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
+};
+
+int __init bcm63xx_enet_register(int unit,
+                                 const struct bcm63xx_enet_platform_data *pd);
+
+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
+enum bcm63xx_regs_enetdmac {
+        ENETDMAC_CHANCFG,
+        ENETDMAC_IR,
+        ENETDMAC_IRMASK,
+        ENETDMAC_MAXBURST,
+        ENETDMAC_BUFALLOC,
+        ENETDMAC_RSTART,
+        ENETDMAC_FC,
+        ENETDMAC_LEN,
+};
+
+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
+{
+        extern const unsigned long *bcm63xx_regs_enetdmac;
+
+        return bcm63xx_regs_enetdmac[reg];
+}
+
+
+#endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
new file mode 100644
index 000000000..4d5005f2b
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __BCM63XX_FLASH_H
+#define __BCM63XX_FLASH_H
+
+enum {
+        BCM63XX_FLASH_TYPE_PARALLEL,
+        BCM63XX_FLASH_TYPE_SERIAL,
+        BCM63XX_FLASH_TYPE_NAND,
+};
+
+int __init bcm63xx_flash_register(void);
+
+#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
new file mode 100644
index 000000000..f93f176c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_HSSPI_H
+#define BCM63XX_DEV_HSSPI_H
+
+#include <linux/types.h>
+
+int bcm63xx_hsspi_register(void);
+
+#endif /* BCM63XX_DEV_HSSPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
new file mode 100644
index 000000000..1951c125c
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_PCI_H_
+#define BCM63XX_DEV_PCI_H_
+
+extern int bcm63xx_pci_enabled;
+
+#endif /* BCM63XX_DEV_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h
new file mode 100644
index 000000000..01674ac58
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_PCMCIA_H_
+#define BCM63XX_DEV_PCMCIA_H_
+
+/*
+ * PCMCIA driver platform data
+ */
+struct bcm63xx_pcmcia_platform_data {
+        unsigned int ready_gpio;
+};
+
+int bcm63xx_pcmcia_register(void);
+
+#endif /* BCM63XX_DEV_PCMCIA_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 000000000..0ab750522
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_SPI_H
+#define BCM63XX_DEV_SPI_H
+
+#include <linux/types.h>
+#include <bcm63xx_io.h>
+#include <bcm63xx_regs.h>
+
+int __init bcm63xx_spi_register(void);
+
+#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
new file mode 100644
index 000000000..88f8cf1c7
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_UART_H_
+#define BCM63XX_DEV_UART_H_
+
+int bcm63xx_uart_register(unsigned int id);
+
+#endif /* BCM63XX_DEV_UART_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
new file mode 100644
index 000000000..3f920baff
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_DEV_USB_USBD_H_
+#define BCM63XX_DEV_USB_USBD_H_
+
+/*
+ * usb device platform data
+ */
+struct bcm63xx_usbd_platform_data {
+        /* board can only support full speed (USB 1.1) */
+        int use_fullspeed;
+
+        /* 0-based port index, for chips with >1 USB PHY */
+        int port_no;
+};
+
+int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd);
+
+#endif /* BCM63XX_DEV_USB_USBD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
new file mode 100644
index 000000000..9212429d5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_GPIO_H
+#define BCM63XX_GPIO_H
+
+#include <linux/init.h>
+#include <bcm63xx_cpu.h>
+
+int __init bcm63xx_gpio_init(void);
+
+static inline unsigned long bcm63xx_gpio_count(void)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                return 32;
+        case BCM3368_CPU_ID:
+                return 40;
+        case BCM6338_CPU_ID:
+                return 8;
+        case BCM6345_CPU_ID:
+                return 16;
+        case BCM6358_CPU_ID:
+        case BCM6368_CPU_ID:
+                return 38;
+        case BCM6362_CPU_ID:
+                return 48;
+        case BCM6348_CPU_ID:
+        default:
+                return 37;
+        }
+}
+
+#define BCM63XX_GPIO_DIR_OUT    0x0
+#define BCM63XX_GPIO_DIR_IN     0x1
+
+#endif /* !BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
new file mode 100644
index 000000000..31c692433
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_IO_H_
+#define BCM63XX_IO_H_
+
+#include <asm/mach-bcm63xx/bcm63xx_cpu.h>
+
+/*
+ * Physical memory map, RAM is mapped at 0x0.
+ *
+ * Note that size MUST be a power of two.
+ */
+#define BCM_PCMCIA_COMMON_BASE_PA       (0x20000000)
+#define BCM_PCMCIA_COMMON_SIZE          (16 * 1024 * 1024)
+#define BCM_PCMCIA_COMMON_END_PA        (BCM_PCMCIA_COMMON_BASE_PA +    \
+                                         BCM_PCMCIA_COMMON_SIZE - 1)
+
+#define BCM_PCMCIA_ATTR_BASE_PA         (0x21000000)
+#define BCM_PCMCIA_ATTR_SIZE            (16 * 1024 * 1024)
+#define BCM_PCMCIA_ATTR_END_PA          (BCM_PCMCIA_ATTR_BASE_PA +      \
+                                         BCM_PCMCIA_ATTR_SIZE - 1)
+
+#define BCM_PCMCIA_IO_BASE_PA           (0x22000000)
+#define BCM_PCMCIA_IO_SIZE              (64 * 1024)
+#define BCM_PCMCIA_IO_END_PA            (BCM_PCMCIA_IO_BASE_PA +        \
+                                        BCM_PCMCIA_IO_SIZE - 1)
+
+#define BCM_PCI_MEM_BASE_PA             (0x30000000)
+#define BCM_PCI_MEM_SIZE                (128 * 1024 * 1024)
+#define BCM_PCI_MEM_END_PA              (BCM_PCI_MEM_BASE_PA +          \
+                                        BCM_PCI_MEM_SIZE - 1)
+
+#define BCM_PCI_IO_BASE_PA              (0x08000000)
+#define BCM_PCI_IO_SIZE                 (64 * 1024)
+#define BCM_PCI_IO_END_PA               (BCM_PCI_IO_BASE_PA +           \
+                                        BCM_PCI_IO_SIZE - 1)
+#define BCM_PCI_IO_HALF_PA              (BCM_PCI_IO_BASE_PA +           \
+                                        (BCM_PCI_IO_SIZE / 2) - 1)
+
+#define BCM_CB_MEM_BASE_PA              (0x38000000)
+#define BCM_CB_MEM_SIZE                 (128 * 1024 * 1024)
+#define BCM_CB_MEM_END_PA               (BCM_CB_MEM_BASE_PA +           \
+                                        BCM_CB_MEM_SIZE - 1)
+
+#define BCM_PCIE_MEM_BASE_PA            0x10f00000
+#define BCM_PCIE_MEM_SIZE               (16 * 1024 * 1024)
+#define BCM_PCIE_MEM_END_PA             (BCM_PCIE_MEM_BASE_PA +         \
+                                        BCM_PCIE_MEM_SIZE - 1)
+
+/*
+ * Internal registers are accessed through KSEG3
+ */
+#define BCM_REGS_VA(x)  ((void __iomem *)(x))
+
+#define bcm_readb(a)    (*(volatile unsigned char *)    BCM_REGS_VA(a))
+#define bcm_readw(a)    (*(volatile unsigned short *)   BCM_REGS_VA(a))
+#define bcm_readl(a)    (*(volatile unsigned int *)     BCM_REGS_VA(a))
+#define bcm_readq(a)    (*(volatile u64 *)              BCM_REGS_VA(a))
+#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
+#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
+#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
+#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
+
+/*
+ * IO helpers to access register set for current CPU
+ */
+#define bcm_rset_readb(s, o)    bcm_readb(bcm63xx_regset_address(s) + (o))
+#define bcm_rset_readw(s, o)    bcm_readw(bcm63xx_regset_address(s) + (o))
+#define bcm_rset_readl(s, o)    bcm_readl(bcm63xx_regset_address(s) + (o))
+#define bcm_rset_writeb(s, v, o)        bcm_writeb((v), \
+                                        bcm63xx_regset_address(s) + (o))
+#define bcm_rset_writew(s, v, o)        bcm_writew((v), \
+                                        bcm63xx_regset_address(s) + (o))
+#define bcm_rset_writel(s, v, o)        bcm_writel((v), \
+                                        bcm63xx_regset_address(s) + (o))
+
+/*
+ * helpers for frequently used register sets
+ */
+#define bcm_perf_readl(o)       bcm_rset_readl(RSET_PERF, (o))
+#define bcm_perf_writel(v, o)   bcm_rset_writel(RSET_PERF, (v), (o))
+#define bcm_timer_readl(o)      bcm_rset_readl(RSET_TIMER, (o))
+#define bcm_timer_writel(v, o)  bcm_rset_writel(RSET_TIMER, (v), (o))
+#define bcm_wdt_readl(o)        bcm_rset_readl(RSET_WDT, (o))
+#define bcm_wdt_writel(v, o)    bcm_rset_writel(RSET_WDT, (v), (o))
+#define bcm_gpio_readl(o)       bcm_rset_readl(RSET_GPIO, (o))
+#define bcm_gpio_writel(v, o)   bcm_rset_writel(RSET_GPIO, (v), (o))
+#define bcm_uart0_readl(o)      bcm_rset_readl(RSET_UART0, (o))
+#define bcm_uart0_writel(v, o)  bcm_rset_writel(RSET_UART0, (v), (o))
+#define bcm_mpi_readl(o)        bcm_rset_readl(RSET_MPI, (o))
+#define bcm_mpi_writel(v, o)    bcm_rset_writel(RSET_MPI, (v), (o))
+#define bcm_pcmcia_readl(o)     bcm_rset_readl(RSET_PCMCIA, (o))
+#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
+#define bcm_pcie_readl(o)       bcm_rset_readl(RSET_PCIE, (o))
+#define bcm_pcie_writel(v, o)   bcm_rset_writel(RSET_PCIE, (v), (o))
+#define bcm_sdram_readl(o)      bcm_rset_readl(RSET_SDRAM, (o))
+#define bcm_sdram_writel(v, o)  bcm_rset_writel(RSET_SDRAM, (v), (o))
+#define bcm_memc_readl(o)       bcm_rset_readl(RSET_MEMC, (o))
+#define bcm_memc_writel(v, o)   bcm_rset_writel(RSET_MEMC, (v), (o))
+#define bcm_ddr_readl(o)        bcm_rset_readl(RSET_DDR, (o))
+#define bcm_ddr_writel(v, o)    bcm_rset_writel(RSET_DDR, (v), (o))
+#define bcm_misc_readl(o)       bcm_rset_readl(RSET_MISC, (o))
+#define bcm_misc_writel(v, o)   bcm_rset_writel(RSET_MISC, (v), (o))
+
+#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
new file mode 100644
index 000000000..7887bc690
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_IRQ_H_
+#define BCM63XX_IRQ_H_
+
+#include <bcm63xx_cpu.h>
+
+#define IRQ_INTERNAL_BASE               8
+#define IRQ_EXTERNAL_BASE               100
+#define IRQ_EXT_0                       (IRQ_EXTERNAL_BASE + 0)
+#define IRQ_EXT_1                       (IRQ_EXTERNAL_BASE + 1)
+#define IRQ_EXT_2                       (IRQ_EXTERNAL_BASE + 2)
+#define IRQ_EXT_3                       (IRQ_EXTERNAL_BASE + 3)
+
+#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
new file mode 100644
index 000000000..73df916e4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_IUDMA_H_
+#define BCM63XX_IUDMA_H_
+
+#include <linux/types.h>
+
+/*
+ * rx/tx dma descriptor
+ */
+struct bcm_enet_desc {
+        u32 len_stat;
+        u32 address;
+};
+
+/* control */
+#define DMADESC_LENGTH_SHIFT    16
+#define DMADESC_LENGTH_MASK     (0xfff << DMADESC_LENGTH_SHIFT)
+#define DMADESC_OWNER_MASK      (1 << 15)
+#define DMADESC_EOP_MASK        (1 << 14)
+#define DMADESC_SOP_MASK        (1 << 13)
+#define DMADESC_ESOP_MASK       (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
+#define DMADESC_WRAP_MASK       (1 << 12)
+#define DMADESC_USB_NOZERO_MASK (1 << 1)
+#define DMADESC_USB_ZERO_MASK   (1 << 0)
+
+/* status */
+#define DMADESC_UNDER_MASK      (1 << 9)
+#define DMADESC_APPEND_CRC      (1 << 8)
+#define DMADESC_OVSIZE_MASK     (1 << 4)
+#define DMADESC_RXER_MASK       (1 << 2)
+#define DMADESC_CRC_MASK        (1 << 1)
+#define DMADESC_OV_MASK         (1 << 0)
+#define DMADESC_ERR_MASK        (DMADESC_UNDER_MASK | \
+                                DMADESC_OVSIZE_MASK | \
+                                DMADESC_RXER_MASK | \
+                                DMADESC_CRC_MASK | \
+                                DMADESC_OV_MASK)
+
+#endif /* ! BCM63XX_IUDMA_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
new file mode 100644
index 000000000..f78d725f2
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_NVRAM_H
+#define BCM63XX_NVRAM_H
+
+#include <linux/types.h>
+
+/**
+ * bcm63xx_nvram_init() - initializes nvram
+ * @nvram:      address of the nvram data
+ *
+ * Initialized the local nvram copy from the target address and checks
+ * its checksum.
+ */
+void bcm63xx_nvram_init(void *nvram);
+
+/**
+ * bcm63xx_nvram_get_name() - returns the board name according to nvram
+ *
+ * Returns the board name field from nvram. Note that it might not be
+ * null terminated if it is exactly 16 bytes long.
+ */
+u8 *bcm63xx_nvram_get_name(void);
+
+/**
+ * bcm63xx_nvram_get_mac_address() - register & return a new mac address
+ * @mac:        pointer to array for allocated mac
+ *
+ * Registers and returns a mac address from the allocated macs from nvram.
+ *
+ * Returns 0 on success.
+ */
+int bcm63xx_nvram_get_mac_address(u8 *mac);
+
+int bcm63xx_nvram_get_psi_size(void);
+
+#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
new file mode 100644
index 000000000..9ceb5e728
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -0,0 +1,1431 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_REGS_H_
+#define BCM63XX_REGS_H_
+
+/*************************************************************************
+ * _REG relative to RSET_PERF
+ *************************************************************************/
+
+/* Chip Identifier / Revision register */
+#define PERF_REV_REG                    0x0
+#define REV_CHIPID_SHIFT                16
+#define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
+#define REV_REVID_SHIFT                 0
+#define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
+
+/* Clock Control register */
+#define PERF_CKCTL_REG                  0x4
+
+#define CKCTL_3368_MAC_EN               (1 << 3)
+#define CKCTL_3368_TC_EN                (1 << 5)
+#define CKCTL_3368_US_TOP_EN            (1 << 6)
+#define CKCTL_3368_DS_TOP_EN            (1 << 7)
+#define CKCTL_3368_APM_EN               (1 << 8)
+#define CKCTL_3368_SPI_EN               (1 << 9)
+#define CKCTL_3368_USBS_EN              (1 << 10)
+#define CKCTL_3368_BMU_EN               (1 << 11)
+#define CKCTL_3368_PCM_EN               (1 << 12)
+#define CKCTL_3368_NTP_EN               (1 << 13)
+#define CKCTL_3368_ACP_B_EN             (1 << 14)
+#define CKCTL_3368_ACP_A_EN             (1 << 15)
+#define CKCTL_3368_EMUSB_EN             (1 << 17)
+#define CKCTL_3368_ENET0_EN             (1 << 18)
+#define CKCTL_3368_ENET1_EN             (1 << 19)
+#define CKCTL_3368_USBU_EN              (1 << 20)
+#define CKCTL_3368_EPHY_EN              (1 << 21)
+
+#define CKCTL_3368_ALL_SAFE_EN          (CKCTL_3368_MAC_EN | \
+                                         CKCTL_3368_TC_EN | \
+                                         CKCTL_3368_US_TOP_EN | \
+                                         CKCTL_3368_DS_TOP_EN | \
+                                         CKCTL_3368_APM_EN | \
+                                         CKCTL_3368_SPI_EN | \
+                                         CKCTL_3368_USBS_EN | \
+                                         CKCTL_3368_BMU_EN | \
+                                         CKCTL_3368_PCM_EN | \
+                                         CKCTL_3368_NTP_EN | \
+                                         CKCTL_3368_ACP_B_EN | \
+                                         CKCTL_3368_ACP_A_EN | \
+                                         CKCTL_3368_EMUSB_EN | \
+                                         CKCTL_3368_USBU_EN)
+
+#define CKCTL_6328_PHYMIPS_EN           (1 << 0)
+#define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
+#define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
+#define CKCTL_6328_ADSL_EN              (1 << 3)
+#define CKCTL_6328_MIPS_EN              (1 << 4)
+#define CKCTL_6328_SAR_EN               (1 << 5)
+#define CKCTL_6328_PCM_EN               (1 << 6)
+#define CKCTL_6328_USBD_EN              (1 << 7)
+#define CKCTL_6328_USBH_EN              (1 << 8)
+#define CKCTL_6328_HSSPI_EN             (1 << 9)
+#define CKCTL_6328_PCIE_EN              (1 << 10)
+#define CKCTL_6328_ROBOSW_EN            (1 << 11)
+
+#define CKCTL_6328_ALL_SAFE_EN          (CKCTL_6328_PHYMIPS_EN |        \
+                                        CKCTL_6328_ADSL_QPROC_EN |      \
+                                        CKCTL_6328_ADSL_AFE_EN |        \
+                                        CKCTL_6328_ADSL_EN |            \
+                                        CKCTL_6328_SAR_EN  |            \
+                                        CKCTL_6328_PCM_EN  |            \
+                                        CKCTL_6328_USBD_EN |            \
+                                        CKCTL_6328_USBH_EN |            \
+                                        CKCTL_6328_ROBOSW_EN |          \
+                                        CKCTL_6328_PCIE_EN)
+
+#define CKCTL_6338_ADSLPHY_EN           (1 << 0)
+#define CKCTL_6338_MPI_EN               (1 << 1)
+#define CKCTL_6338_DRAM_EN              (1 << 2)
+#define CKCTL_6338_ENET_EN              (1 << 4)
+#define CKCTL_6338_USBS_EN              (1 << 4)
+#define CKCTL_6338_SAR_EN               (1 << 5)
+#define CKCTL_6338_SPI_EN               (1 << 9)
+
+#define CKCTL_6338_ALL_SAFE_EN          (CKCTL_6338_ADSLPHY_EN |        \
+                                        CKCTL_6338_MPI_EN |             \
+                                        CKCTL_6338_ENET_EN |            \
+                                        CKCTL_6338_SAR_EN |             \
+                                        CKCTL_6338_SPI_EN)
+
+/* BCM6345 clock bits are shifted by 16 on the left, because of the test
+ * control register which is 16-bits wide. That way we do not have any
+ * specific BCM6345 code for handling clocks, and writing 0 to the test
+ * control register is fine.
+ */
+#define CKCTL_6345_CPU_EN               (1 << 16)
+#define CKCTL_6345_BUS_EN               (1 << 17)
+#define CKCTL_6345_EBI_EN               (1 << 18)
+#define CKCTL_6345_UART_EN              (1 << 19)
+#define CKCTL_6345_ADSLPHY_EN           (1 << 20)
+#define CKCTL_6345_ENET_EN              (1 << 23)
+#define CKCTL_6345_USBH_EN              (1 << 24)
+
+#define CKCTL_6345_ALL_SAFE_EN          (CKCTL_6345_ENET_EN |   \
+                                        CKCTL_6345_USBH_EN |    \
+                                        CKCTL_6345_ADSLPHY_EN)
+
+#define CKCTL_6348_ADSLPHY_EN           (1 << 0)
+#define CKCTL_6348_MPI_EN               (1 << 1)
+#define CKCTL_6348_SDRAM_EN             (1 << 2)
+#define CKCTL_6348_M2M_EN               (1 << 3)
+#define CKCTL_6348_ENET_EN              (1 << 4)
+#define CKCTL_6348_SAR_EN               (1 << 5)
+#define CKCTL_6348_USBS_EN              (1 << 6)
+#define CKCTL_6348_USBH_EN              (1 << 8)
+#define CKCTL_6348_SPI_EN               (1 << 9)
+
+#define CKCTL_6348_ALL_SAFE_EN          (CKCTL_6348_ADSLPHY_EN |        \
+                                        CKCTL_6348_M2M_EN |             \
+                                        CKCTL_6348_ENET_EN |            \
+                                        CKCTL_6348_SAR_EN |             \
+                                        CKCTL_6348_USBS_EN |            \
+                                        CKCTL_6348_USBH_EN |            \
+                                        CKCTL_6348_SPI_EN)
+
+#define CKCTL_6358_ENET_EN              (1 << 4)
+#define CKCTL_6358_ADSLPHY_EN           (1 << 5)
+#define CKCTL_6358_PCM_EN               (1 << 8)
+#define CKCTL_6358_SPI_EN               (1 << 9)
+#define CKCTL_6358_USBS_EN              (1 << 10)
+#define CKCTL_6358_SAR_EN               (1 << 11)
+#define CKCTL_6358_EMUSB_EN             (1 << 17)
+#define CKCTL_6358_ENET0_EN             (1 << 18)
+#define CKCTL_6358_ENET1_EN             (1 << 19)
+#define CKCTL_6358_USBSU_EN             (1 << 20)
+#define CKCTL_6358_EPHY_EN              (1 << 21)
+
+#define CKCTL_6358_ALL_SAFE_EN          (CKCTL_6358_ENET_EN |           \
+                                        CKCTL_6358_ADSLPHY_EN |         \
+                                        CKCTL_6358_PCM_EN |             \
+                                        CKCTL_6358_SPI_EN |             \
+                                        CKCTL_6358_USBS_EN |            \
+                                        CKCTL_6358_SAR_EN |             \
+                                        CKCTL_6358_EMUSB_EN |           \
+                                        CKCTL_6358_ENET0_EN |           \
+                                        CKCTL_6358_ENET1_EN |           \
+                                        CKCTL_6358_USBSU_EN |           \
+                                        CKCTL_6358_EPHY_EN)
+
+#define CKCTL_6362_ADSL_QPROC_EN        (1 << 1)
+#define CKCTL_6362_ADSL_AFE_EN          (1 << 2)
+#define CKCTL_6362_ADSL_EN              (1 << 3)
+#define CKCTL_6362_MIPS_EN              (1 << 4)
+#define CKCTL_6362_WLAN_OCP_EN          (1 << 5)
+#define CKCTL_6362_SWPKT_USB_EN         (1 << 7)
+#define CKCTL_6362_SWPKT_SAR_EN         (1 << 8)
+#define CKCTL_6362_SAR_EN               (1 << 9)
+#define CKCTL_6362_ROBOSW_EN            (1 << 10)
+#define CKCTL_6362_PCM_EN               (1 << 11)
+#define CKCTL_6362_USBD_EN              (1 << 12)
+#define CKCTL_6362_USBH_EN              (1 << 13)
+#define CKCTL_6362_IPSEC_EN             (1 << 14)
+#define CKCTL_6362_SPI_EN               (1 << 15)
+#define CKCTL_6362_HSSPI_EN             (1 << 16)
+#define CKCTL_6362_PCIE_EN              (1 << 17)
+#define CKCTL_6362_FAP_EN               (1 << 18)
+#define CKCTL_6362_PHYMIPS_EN           (1 << 19)
+#define CKCTL_6362_NAND_EN              (1 << 20)
+
+#define CKCTL_6362_ALL_SAFE_EN          (CKCTL_6362_PHYMIPS_EN |        \
+                                        CKCTL_6362_ADSL_QPROC_EN |      \
+                                        CKCTL_6362_ADSL_AFE_EN |        \
+                                        CKCTL_6362_ADSL_EN |            \
+                                        CKCTL_6362_SAR_EN  |            \
+                                        CKCTL_6362_PCM_EN  |            \
+                                        CKCTL_6362_IPSEC_EN |           \
+                                        CKCTL_6362_USBD_EN |            \
+                                        CKCTL_6362_USBH_EN |            \
+                                        CKCTL_6362_ROBOSW_EN |          \
+                                        CKCTL_6362_PCIE_EN)
+
+
+#define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
+#define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
+#define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
+#define CKCTL_6368_VDSL_EN              (1 << 5)
+#define CKCTL_6368_PHYMIPS_EN           (1 << 6)
+#define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
+#define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
+#define CKCTL_6368_SPI_EN               (1 << 9)
+#define CKCTL_6368_USBD_EN              (1 << 10)
+#define CKCTL_6368_SAR_EN               (1 << 11)
+#define CKCTL_6368_ROBOSW_EN            (1 << 12)
+#define CKCTL_6368_UTOPIA_EN            (1 << 13)
+#define CKCTL_6368_PCM_EN               (1 << 14)
+#define CKCTL_6368_USBH_EN              (1 << 15)
+#define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
+#define CKCTL_6368_NAND_EN              (1 << 17)
+#define CKCTL_6368_IPSEC_EN             (1 << 18)
+
+#define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
+                                        CKCTL_6368_SWPKT_SAR_EN |       \
+                                        CKCTL_6368_SPI_EN |             \
+                                        CKCTL_6368_USBD_EN |            \
+                                        CKCTL_6368_SAR_EN |             \
+                                        CKCTL_6368_ROBOSW_EN |          \
+                                        CKCTL_6368_UTOPIA_EN |          \
+                                        CKCTL_6368_PCM_EN |             \
+                                        CKCTL_6368_USBH_EN |            \
+                                        CKCTL_6368_DISABLE_GLESS_EN |   \
+                                        CKCTL_6368_NAND_EN |            \
+                                        CKCTL_6368_IPSEC_EN)
+
+/* System PLL Control register  */
+#define PERF_SYS_PLL_CTL_REG            0x8
+#define SYS_PLL_SOFT_RESET              0x1
+
+/* Interrupt Mask register */
+#define PERF_IRQMASK_3368_REG           0xc
+#define PERF_IRQMASK_6328_REG(x)        (0x20 + (x) * 0x10)
+#define PERF_IRQMASK_6338_REG           0xc
+#define PERF_IRQMASK_6345_REG           0xc
+#define PERF_IRQMASK_6348_REG           0xc
+#define PERF_IRQMASK_6358_REG(x)        (0xc + (x) * 0x2c)
+#define PERF_IRQMASK_6362_REG(x)        (0x20 + (x) * 0x10)
+#define PERF_IRQMASK_6368_REG(x)        (0x20 + (x) * 0x10)
+
+/* Interrupt Status register */
+#define PERF_IRQSTAT_3368_REG           0x10
+#define PERF_IRQSTAT_6328_REG(x)        (0x28 + (x) * 0x10)
+#define PERF_IRQSTAT_6338_REG           0x10
+#define PERF_IRQSTAT_6345_REG           0x10
+#define PERF_IRQSTAT_6348_REG           0x10
+#define PERF_IRQSTAT_6358_REG(x)        (0x10 + (x) * 0x2c)
+#define PERF_IRQSTAT_6362_REG(x)        (0x28 + (x) * 0x10)
+#define PERF_IRQSTAT_6368_REG(x)        (0x28 + (x) * 0x10)
+
+/* External Interrupt Configuration register */
+#define PERF_EXTIRQ_CFG_REG_3368        0x14
+#define PERF_EXTIRQ_CFG_REG_6328        0x18
+#define PERF_EXTIRQ_CFG_REG_6338        0x14
+#define PERF_EXTIRQ_CFG_REG_6345        0x14
+#define PERF_EXTIRQ_CFG_REG_6348        0x14
+#define PERF_EXTIRQ_CFG_REG_6358        0x14
+#define PERF_EXTIRQ_CFG_REG_6362        0x18
+#define PERF_EXTIRQ_CFG_REG_6368        0x18
+
+#define PERF_EXTIRQ_CFG_REG2_6368       0x1c
+
+/* for 6348 only */
+#define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
+#define EXTIRQ_CFG_STAT_6348(x)         (1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR_6348(x)        (1 << (x + 10))
+#define EXTIRQ_CFG_MASK_6348(x)         (1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE_6348(x)     (1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
+#define EXTIRQ_CFG_CLEAR_ALL_6348       (0xf << 10)
+#define EXTIRQ_CFG_MASK_ALL_6348        (0xf << 15)
+
+/* for all others */
+#define EXTIRQ_CFG_SENSE(x)             (1 << (x))
+#define EXTIRQ_CFG_STAT(x)              (1 << (x + 4))
+#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 8))
+#define EXTIRQ_CFG_MASK(x)              (1 << (x + 12))
+#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 16))
+#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 20))
+#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 8)
+#define EXTIRQ_CFG_MASK_ALL             (0xf << 12)
+
+/* Soft Reset register */
+#define PERF_SOFTRESET_REG              0x28
+#define PERF_SOFTRESET_6328_REG         0x10
+#define PERF_SOFTRESET_6358_REG         0x34
+#define PERF_SOFTRESET_6362_REG         0x10
+#define PERF_SOFTRESET_6368_REG         0x10
+
+#define SOFTRESET_3368_SPI_MASK         (1 << 0)
+#define SOFTRESET_3368_ENET_MASK        (1 << 2)
+#define SOFTRESET_3368_MPI_MASK         (1 << 3)
+#define SOFTRESET_3368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_3368_USBS_MASK        (1 << 11)
+#define SOFTRESET_3368_PCM_MASK         (1 << 13)
+
+#define SOFTRESET_6328_SPI_MASK         (1 << 0)
+#define SOFTRESET_6328_EPHY_MASK        (1 << 1)
+#define SOFTRESET_6328_SAR_MASK         (1 << 2)
+#define SOFTRESET_6328_ENETSW_MASK      (1 << 3)
+#define SOFTRESET_6328_USBS_MASK        (1 << 4)
+#define SOFTRESET_6328_USBH_MASK        (1 << 5)
+#define SOFTRESET_6328_PCM_MASK         (1 << 6)
+#define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)
+#define SOFTRESET_6328_PCIE_MASK        (1 << 8)
+#define SOFTRESET_6328_PCIE_EXT_MASK    (1 << 9)
+#define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)
+
+#define SOFTRESET_6338_SPI_MASK         (1 << 0)
+#define SOFTRESET_6338_ENET_MASK        (1 << 2)
+#define SOFTRESET_6338_USBH_MASK        (1 << 3)
+#define SOFTRESET_6338_USBS_MASK        (1 << 4)
+#define SOFTRESET_6338_ADSL_MASK        (1 << 5)
+#define SOFTRESET_6338_DMAMEM_MASK      (1 << 6)
+#define SOFTRESET_6338_SAR_MASK         (1 << 7)
+#define SOFTRESET_6338_ACLC_MASK        (1 << 8)
+#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
+#define SOFTRESET_6338_ALL       (SOFTRESET_6338_SPI_MASK |             \
+                                  SOFTRESET_6338_ENET_MASK |            \
+                                  SOFTRESET_6338_USBH_MASK |            \
+                                  SOFTRESET_6338_USBS_MASK |            \
+                                  SOFTRESET_6338_ADSL_MASK |            \
+                                  SOFTRESET_6338_DMAMEM_MASK |          \
+                                  SOFTRESET_6338_SAR_MASK |             \
+                                  SOFTRESET_6338_ACLC_MASK |            \
+                                  SOFTRESET_6338_ADSLMIPSPLL_MASK)
+
+#define SOFTRESET_6348_SPI_MASK         (1 << 0)
+#define SOFTRESET_6348_ENET_MASK        (1 << 2)
+#define SOFTRESET_6348_USBH_MASK        (1 << 3)
+#define SOFTRESET_6348_USBS_MASK        (1 << 4)
+#define SOFTRESET_6348_ADSL_MASK        (1 << 5)
+#define SOFTRESET_6348_DMAMEM_MASK      (1 << 6)
+#define SOFTRESET_6348_SAR_MASK         (1 << 7)
+#define SOFTRESET_6348_ACLC_MASK        (1 << 8)
+#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
+
+#define SOFTRESET_6348_ALL       (SOFTRESET_6348_SPI_MASK |             \
+                                  SOFTRESET_6348_ENET_MASK |            \
+                                  SOFTRESET_6348_USBH_MASK |            \
+                                  SOFTRESET_6348_USBS_MASK |            \
+                                  SOFTRESET_6348_ADSL_MASK |            \
+                                  SOFTRESET_6348_DMAMEM_MASK |          \
+                                  SOFTRESET_6348_SAR_MASK |             \
+                                  SOFTRESET_6348_ACLC_MASK |            \
+                                  SOFTRESET_6348_ADSLMIPSPLL_MASK)
+
+#define SOFTRESET_6358_SPI_MASK         (1 << 0)
+#define SOFTRESET_6358_ENET_MASK        (1 << 2)
+#define SOFTRESET_6358_MPI_MASK         (1 << 3)
+#define SOFTRESET_6358_EPHY_MASK        (1 << 6)
+#define SOFTRESET_6358_SAR_MASK         (1 << 7)
+#define SOFTRESET_6358_USBH_MASK        (1 << 12)
+#define SOFTRESET_6358_PCM_MASK         (1 << 13)
+#define SOFTRESET_6358_ADSL_MASK        (1 << 14)
+
+#define SOFTRESET_6362_SPI_MASK         (1 << 0)
+#define SOFTRESET_6362_IPSEC_MASK       (1 << 1)
+#define SOFTRESET_6362_EPHY_MASK        (1 << 2)
+#define SOFTRESET_6362_SAR_MASK         (1 << 3)
+#define SOFTRESET_6362_ENETSW_MASK      (1 << 4)
+#define SOFTRESET_6362_USBS_MASK        (1 << 5)
+#define SOFTRESET_6362_USBH_MASK        (1 << 6)
+#define SOFTRESET_6362_PCM_MASK         (1 << 7)
+#define SOFTRESET_6362_PCIE_CORE_MASK   (1 << 8)
+#define SOFTRESET_6362_PCIE_MASK        (1 << 9)
+#define SOFTRESET_6362_PCIE_EXT_MASK    (1 << 10)
+#define SOFTRESET_6362_WLAN_SHIM_MASK   (1 << 11)
+#define SOFTRESET_6362_DDR_PHY_MASK     (1 << 12)
+#define SOFTRESET_6362_FAP_MASK         (1 << 13)
+#define SOFTRESET_6362_WLAN_UBUS_MASK   (1 << 14)
+
+#define SOFTRESET_6368_SPI_MASK         (1 << 0)
+#define SOFTRESET_6368_MPI_MASK         (1 << 3)
+#define SOFTRESET_6368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_6368_SAR_MASK         (1 << 7)
+#define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
+#define SOFTRESET_6368_USBS_MASK        (1 << 11)
+#define SOFTRESET_6368_USBH_MASK        (1 << 12)
+#define SOFTRESET_6368_PCM_MASK         (1 << 13)
+
+/* MIPS PLL control register */
+#define PERF_MIPSPLLCTL_REG             0x34
+#define MIPSPLLCTL_N1_SHIFT             20
+#define MIPSPLLCTL_N1_MASK              (0x7 << MIPSPLLCTL_N1_SHIFT)
+#define MIPSPLLCTL_N2_SHIFT             15
+#define MIPSPLLCTL_N2_MASK              (0x1f << MIPSPLLCTL_N2_SHIFT)
+#define MIPSPLLCTL_M1REF_SHIFT          12
+#define MIPSPLLCTL_M1REF_MASK           (0x7 << MIPSPLLCTL_M1REF_SHIFT)
+#define MIPSPLLCTL_M2REF_SHIFT          9
+#define MIPSPLLCTL_M2REF_MASK           (0x7 << MIPSPLLCTL_M2REF_SHIFT)
+#define MIPSPLLCTL_M1CPU_SHIFT          6
+#define MIPSPLLCTL_M1CPU_MASK           (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
+#define MIPSPLLCTL_M1BUS_SHIFT          3
+#define MIPSPLLCTL_M1BUS_MASK           (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
+#define MIPSPLLCTL_M2BUS_SHIFT          0
+#define MIPSPLLCTL_M2BUS_MASK           (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
+
+/* ADSL PHY PLL Control register */
+#define PERF_ADSLPLLCTL_REG             0x38
+#define ADSLPLLCTL_N1_SHIFT             20
+#define ADSLPLLCTL_N1_MASK              (0x7 << ADSLPLLCTL_N1_SHIFT)
+#define ADSLPLLCTL_N2_SHIFT             15
+#define ADSLPLLCTL_N2_MASK              (0x1f << ADSLPLLCTL_N2_SHIFT)
+#define ADSLPLLCTL_M1REF_SHIFT          12
+#define ADSLPLLCTL_M1REF_MASK           (0x7 << ADSLPLLCTL_M1REF_SHIFT)
+#define ADSLPLLCTL_M2REF_SHIFT          9
+#define ADSLPLLCTL_M2REF_MASK           (0x7 << ADSLPLLCTL_M2REF_SHIFT)
+#define ADSLPLLCTL_M1CPU_SHIFT          6
+#define ADSLPLLCTL_M1CPU_MASK           (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
+#define ADSLPLLCTL_M1BUS_SHIFT          3
+#define ADSLPLLCTL_M1BUS_MASK           (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
+#define ADSLPLLCTL_M2BUS_SHIFT          0
+#define ADSLPLLCTL_M2BUS_MASK           (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
+
+#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus)       \
+                                (((n1) << ADSLPLLCTL_N1_SHIFT) |        \
+                                ((n2) << ADSLPLLCTL_N2_SHIFT) |         \
+                                ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |   \
+                                ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |   \
+                                ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |   \
+                                ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |   \
+                                ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
+
+
+/*************************************************************************
+ * _REG relative to RSET_TIMER
+ *************************************************************************/
+
+#define BCM63XX_TIMER_COUNT             4
+#define TIMER_T0_ID                     0
+#define TIMER_T1_ID                     1
+#define TIMER_T2_ID                     2
+#define TIMER_WDT_ID                    3
+
+/* Timer irqstat register */
+#define TIMER_IRQSTAT_REG               0
+#define TIMER_IRQSTAT_TIMER_CAUSE(x)    (1 << (x))
+#define TIMER_IRQSTAT_TIMER0_CAUSE      (1 << 0)
+#define TIMER_IRQSTAT_TIMER1_CAUSE      (1 << 1)
+#define TIMER_IRQSTAT_TIMER2_CAUSE      (1 << 2)
+#define TIMER_IRQSTAT_WDT_CAUSE         (1 << 3)
+#define TIMER_IRQSTAT_TIMER_IR_EN(x)    (1 << ((x) + 8))
+#define TIMER_IRQSTAT_TIMER0_IR_EN      (1 << 8)
+#define TIMER_IRQSTAT_TIMER1_IR_EN      (1 << 9)
+#define TIMER_IRQSTAT_TIMER2_IR_EN      (1 << 10)
+
+/* Timer control register */
+#define TIMER_CTLx_REG(x)               (0x4 + (x * 4))
+#define TIMER_CTL0_REG                  0x4
+#define TIMER_CTL1_REG                  0x8
+#define TIMER_CTL2_REG                  0xC
+#define TIMER_CTL_COUNTDOWN_MASK        (0x3fffffff)
+#define TIMER_CTL_MONOTONIC_MASK        (1 << 30)
+#define TIMER_CTL_ENABLE_MASK           (1 << 31)
+
+
+/*************************************************************************
+ * _REG relative to RSET_WDT
+ *************************************************************************/
+
+/* Watchdog default count register */
+#define WDT_DEFVAL_REG                  0x0
+
+/* Watchdog control register */
+#define WDT_CTL_REG                     0x4
+
+/* Watchdog control register constants */
+#define WDT_START_1                     (0xff00)
+#define WDT_START_2                     (0x00ff)
+#define WDT_STOP_1                      (0xee00)
+#define WDT_STOP_2                      (0x00ee)
+
+/* Watchdog reset length register */
+#define WDT_RSTLEN_REG                  0x8
+
+/* Watchdog soft reset register (BCM6328 only) */
+#define WDT_SOFTRESET_REG               0xc
+
+/*************************************************************************
+ * _REG relative to RSET_GPIO
+ *************************************************************************/
+
+/* GPIO registers */
+#define GPIO_CTL_HI_REG                 0x0
+#define GPIO_CTL_LO_REG                 0x4
+#define GPIO_DATA_HI_REG                0x8
+#define GPIO_DATA_LO_REG                0xC
+#define GPIO_DATA_LO_REG_6345           0x8
+
+/* GPIO mux registers and constants */
+#define GPIO_MODE_REG                   0x18
+
+#define GPIO_MODE_6348_G4_DIAG          0x00090000
+#define GPIO_MODE_6348_G4_UTOPIA        0x00080000
+#define GPIO_MODE_6348_G4_LEGACY_LED    0x00030000
+#define GPIO_MODE_6348_G4_MII_SNOOP     0x00020000
+#define GPIO_MODE_6348_G4_EXT_EPHY      0x00010000
+#define GPIO_MODE_6348_G3_DIAG          0x00009000
+#define GPIO_MODE_6348_G3_UTOPIA        0x00008000
+#define GPIO_MODE_6348_G3_EXT_MII       0x00007000
+#define GPIO_MODE_6348_G2_DIAG          0x00000900
+#define GPIO_MODE_6348_G2_PCI           0x00000500
+#define GPIO_MODE_6348_G1_DIAG          0x00000090
+#define GPIO_MODE_6348_G1_UTOPIA        0x00000080
+#define GPIO_MODE_6348_G1_SPI_UART      0x00000060
+#define GPIO_MODE_6348_G1_SPI_MASTER    0x00000060
+#define GPIO_MODE_6348_G1_MII_PCCARD    0x00000040
+#define GPIO_MODE_6348_G1_MII_SNOOP     0x00000020
+#define GPIO_MODE_6348_G1_EXT_EPHY      0x00000010
+#define GPIO_MODE_6348_G0_DIAG          0x00000009
+#define GPIO_MODE_6348_G0_EXT_MII       0x00000007
+
+#define GPIO_MODE_6358_EXTRACS          (1 << 5)
+#define GPIO_MODE_6358_UART1            (1 << 6)
+#define GPIO_MODE_6358_EXTRA_SPI_SS     (1 << 7)
+#define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
+#define GPIO_MODE_6358_UTOPIA           (1 << 12)
+
+#define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
+#define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
+#define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
+#define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
+#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
+#define GPIO_MODE_6368_INET_LED         (1 << 5)
+#define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
+#define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
+#define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
+#define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
+#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
+#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
+#define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
+#define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
+#define GPIO_MODE_6368_USBD_LED         (1 << 14)
+#define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
+#define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
+#define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
+#define GPIO_MODE_6368_PCI_INTB         (1 << 18)
+#define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
+#define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
+#define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
+#define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
+#define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
+#define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
+#define GPIO_MODE_6368_EBI_CS2          (1 << 26)
+#define GPIO_MODE_6368_EBI_CS3          (1 << 27)
+#define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
+#define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
+#define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
+#define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
+
+
+#define GPIO_PINMUX_OTHR_REG            0x24
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
+#define GPIO_PINMUX_OTHR_6328_USB_MASK  (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_HOST  (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+
+#define GPIO_BASEMODE_6368_REG          0x38
+#define GPIO_BASEMODE_6368_UART2        0x1
+#define GPIO_BASEMODE_6368_GPIO         0x0
+#define GPIO_BASEMODE_6368_MASK         0x7
+/* those bits must be kept as read in gpio basemode register*/
+
+#define GPIO_STRAPBUS_REG               0x40
+#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
+#define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)
+#define STRAPBUS_6368_BOOT_SEL_MASK     0x3
+#define STRAPBUS_6368_BOOT_SEL_NAND     0
+#define STRAPBUS_6368_BOOT_SEL_SERIAL   1
+#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENET
+ *************************************************************************/
+
+/* Receiver Configuration register */
+#define ENET_RXCFG_REG                  0x0
+#define ENET_RXCFG_ALLMCAST_SHIFT       1
+#define ENET_RXCFG_ALLMCAST_MASK        (1 << ENET_RXCFG_ALLMCAST_SHIFT)
+#define ENET_RXCFG_PROMISC_SHIFT        3
+#define ENET_RXCFG_PROMISC_MASK         (1 << ENET_RXCFG_PROMISC_SHIFT)
+#define ENET_RXCFG_LOOPBACK_SHIFT       4
+#define ENET_RXCFG_LOOPBACK_MASK        (1 << ENET_RXCFG_LOOPBACK_SHIFT)
+#define ENET_RXCFG_ENFLOW_SHIFT         5
+#define ENET_RXCFG_ENFLOW_MASK          (1 << ENET_RXCFG_ENFLOW_SHIFT)
+
+/* Receive Maximum Length register */
+#define ENET_RXMAXLEN_REG               0x4
+#define ENET_RXMAXLEN_SHIFT             0
+#define ENET_RXMAXLEN_MASK              (0x7ff << ENET_RXMAXLEN_SHIFT)
+
+/* Transmit Maximum Length register */
+#define ENET_TXMAXLEN_REG               0x8
+#define ENET_TXMAXLEN_SHIFT             0
+#define ENET_TXMAXLEN_MASK              (0x7ff << ENET_TXMAXLEN_SHIFT)
+
+/* MII Status/Control register */
+#define ENET_MIISC_REG                  0x10
+#define ENET_MIISC_MDCFREQDIV_SHIFT     0
+#define ENET_MIISC_MDCFREQDIV_MASK      (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
+#define ENET_MIISC_PREAMBLEEN_SHIFT     7
+#define ENET_MIISC_PREAMBLEEN_MASK      (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
+
+/* MII Data register */
+#define ENET_MIIDATA_REG                0x14
+#define ENET_MIIDATA_DATA_SHIFT         0
+#define ENET_MIIDATA_DATA_MASK          (0xffff << ENET_MIIDATA_DATA_SHIFT)
+#define ENET_MIIDATA_TA_SHIFT           16
+#define ENET_MIIDATA_TA_MASK            (0x3 << ENET_MIIDATA_TA_SHIFT)
+#define ENET_MIIDATA_REG_SHIFT          18
+#define ENET_MIIDATA_REG_MASK           (0x1f << ENET_MIIDATA_REG_SHIFT)
+#define ENET_MIIDATA_PHYID_SHIFT        23
+#define ENET_MIIDATA_PHYID_MASK         (0x1f << ENET_MIIDATA_PHYID_SHIFT)
+#define ENET_MIIDATA_OP_READ_MASK       (0x6 << 28)
+#define ENET_MIIDATA_OP_WRITE_MASK      (0x5 << 28)
+
+/* Ethernet Interrupt Mask register */
+#define ENET_IRMASK_REG                 0x18
+
+/* Ethernet Interrupt register */
+#define ENET_IR_REG                     0x1c
+#define ENET_IR_MII                     (1 << 0)
+#define ENET_IR_MIB                     (1 << 1)
+#define ENET_IR_FLOWC                   (1 << 2)
+
+/* Ethernet Control register */
+#define ENET_CTL_REG                    0x2c
+#define ENET_CTL_ENABLE_SHIFT           0
+#define ENET_CTL_ENABLE_MASK            (1 << ENET_CTL_ENABLE_SHIFT)
+#define ENET_CTL_DISABLE_SHIFT          1
+#define ENET_CTL_DISABLE_MASK           (1 << ENET_CTL_DISABLE_SHIFT)
+#define ENET_CTL_SRESET_SHIFT           2
+#define ENET_CTL_SRESET_MASK            (1 << ENET_CTL_SRESET_SHIFT)
+#define ENET_CTL_EPHYSEL_SHIFT          3
+#define ENET_CTL_EPHYSEL_MASK           (1 << ENET_CTL_EPHYSEL_SHIFT)
+
+/* Transmit Control register */
+#define ENET_TXCTL_REG                  0x30
+#define ENET_TXCTL_FD_SHIFT             0
+#define ENET_TXCTL_FD_MASK              (1 << ENET_TXCTL_FD_SHIFT)
+
+/* Transmit Watermask register */
+#define ENET_TXWMARK_REG                0x34
+#define ENET_TXWMARK_WM_SHIFT           0
+#define ENET_TXWMARK_WM_MASK            (0x3f << ENET_TXWMARK_WM_SHIFT)
+
+/* MIB Control register */
+#define ENET_MIBCTL_REG                 0x38
+#define ENET_MIBCTL_RDCLEAR_SHIFT       0
+#define ENET_MIBCTL_RDCLEAR_MASK        (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
+
+/* Perfect Match Data Low register */
+#define ENET_PML_REG(x)                 (0x58 + (x) * 8)
+#define ENET_PMH_REG(x)                 (0x5c + (x) * 8)
+#define ENET_PMH_DATAVALID_SHIFT        16
+#define ENET_PMH_DATAVALID_MASK         (1 << ENET_PMH_DATAVALID_SHIFT)
+
+/* MIB register */
+#define ENET_MIB_REG(x)                 (0x200 + (x) * 4)
+#define ENET_MIB_REG_COUNT              55
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMA
+ *************************************************************************/
+#define ENETDMA_CHAN_WIDTH              0x10
+#define ENETDMA_6345_CHAN_WIDTH         0x40
+
+/* Controller Configuration Register */
+#define ENETDMA_CFG_REG                 (0x0)
+#define ENETDMA_CFG_EN_SHIFT            0
+#define ENETDMA_CFG_EN_MASK             (1 << ENETDMA_CFG_EN_SHIFT)
+#define ENETDMA_CFG_FLOWCH_MASK(x)      (1 << ((x >> 1) + 1))
+
+/* Flow Control Descriptor Low Threshold register */
+#define ENETDMA_FLOWCL_REG(x)           (0x4 + (x) * 6)
+
+/* Flow Control Descriptor High Threshold register */
+#define ENETDMA_FLOWCH_REG(x)           (0x8 + (x) * 6)
+
+/* Flow Control Descriptor Buffer Alloca Threshold register */
+#define ENETDMA_BUFALLOC_REG(x)         (0xc + (x) * 6)
+#define ENETDMA_BUFALLOC_FORCE_SHIFT    31
+#define ENETDMA_BUFALLOC_FORCE_MASK     (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
+
+/* Global interrupt status */
+#define ENETDMA_GLB_IRQSTAT_REG         (0x40)
+
+/* Global interrupt mask */
+#define ENETDMA_GLB_IRQMASK_REG         (0x44)
+
+/* Channel Configuration register */
+#define ENETDMA_CHANCFG_REG(x)          (0x100 + (x) * 0x10)
+#define ENETDMA_CHANCFG_EN_SHIFT        0
+#define ENETDMA_CHANCFG_EN_MASK         (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMA_CHANCFG_PKTHALT_SHIFT   1
+#define ENETDMA_CHANCFG_PKTHALT_MASK    (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+
+/* Interrupt Control/Status register */
+#define ENETDMA_IR_REG(x)               (0x104 + (x) * 0x10)
+#define ENETDMA_IR_BUFDONE_MASK         (1 << 0)
+#define ENETDMA_IR_PKTDONE_MASK         (1 << 1)
+#define ENETDMA_IR_NOTOWNER_MASK        (1 << 2)
+
+/* Interrupt Mask register */
+#define ENETDMA_IRMASK_REG(x)           (0x108 + (x) * 0x10)
+
+/* Maximum Burst Length */
+#define ENETDMA_MAXBURST_REG(x)         (0x10C + (x) * 0x10)
+
+/* Ring Start Address register */
+#define ENETDMA_RSTART_REG(x)           (0x200 + (x) * 0x10)
+
+/* State Ram Word 2 */
+#define ENETDMA_SRAM2_REG(x)            (0x204 + (x) * 0x10)
+
+/* State Ram Word 3 */
+#define ENETDMA_SRAM3_REG(x)            (0x208 + (x) * 0x10)
+
+/* State Ram Word 4 */
+#define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
+
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG        (0x00)
+
+#define ENETDMA_6345_MAXBURST_REG       (0x04)
+
+#define ENETDMA_6345_RSTART_REG         (0x08)
+
+#define ENETDMA_6345_LEN_REG            (0x0C)
+
+#define ENETDMA_6345_IR_REG             (0x14)
+
+#define ENETDMA_6345_IRMASK_REG         (0x18)
+
+#define ENETDMA_6345_FC_REG             (0x1C)
+
+#define ENETDMA_6345_BUFALLOC_REG       (0x20)
+
+/* Shift down for EOP, SOP and WRAP bits */
+#define ENETDMA_6345_DESC_SHIFT         (3)
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMAC
+ *************************************************************************/
+
+/* Channel Configuration register */
+#define ENETDMAC_CHANCFG_REG            (0x0)
+#define ENETDMAC_CHANCFG_EN_SHIFT       0
+#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
+#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
+#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
+#define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
+#define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
+
+/* Interrupt Control/Status register */
+#define ENETDMAC_IR_REG                 (0x4)
+#define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
+#define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
+#define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
+
+/* Interrupt Mask register */
+#define ENETDMAC_IRMASK_REG             (0x8)
+
+/* Maximum Burst Length */
+#define ENETDMAC_MAXBURST_REG           (0xc)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMAS
+ *************************************************************************/
+
+/* Ring Start Address register */
+#define ENETDMAS_RSTART_REG             (0x0)
+
+/* State Ram Word 2 */
+#define ENETDMAS_SRAM2_REG              (0x4)
+
+/* State Ram Word 3 */
+#define ENETDMAS_SRAM3_REG              (0x8)
+
+/* State Ram Word 4 */
+#define ENETDMAS_SRAM4_REG              (0xc)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETSW
+ *************************************************************************/
+
+/* Port traffic control */
+#define ENETSW_PTCTRL_REG(x)            (0x0 + (x))
+#define ENETSW_PTCTRL_RXDIS_MASK        (1 << 0)
+#define ENETSW_PTCTRL_TXDIS_MASK        (1 << 1)
+
+/* Switch mode register */
+#define ENETSW_SWMODE_REG               (0xb)
+#define ENETSW_SWMODE_FWD_EN_MASK       (1 << 1)
+
+/* IMP override Register */
+#define ENETSW_IMPOV_REG                (0xe)
+#define ENETSW_IMPOV_FORCE_MASK         (1 << 7)
+#define ENETSW_IMPOV_TXFLOW_MASK        (1 << 5)
+#define ENETSW_IMPOV_RXFLOW_MASK        (1 << 4)
+#define ENETSW_IMPOV_1000_MASK          (1 << 3)
+#define ENETSW_IMPOV_100_MASK           (1 << 2)
+#define ENETSW_IMPOV_FDX_MASK           (1 << 1)
+#define ENETSW_IMPOV_LINKUP_MASK        (1 << 0)
+
+/* Port override Register */
+#define ENETSW_PORTOV_REG(x)            (0x58 + (x))
+#define ENETSW_PORTOV_ENABLE_MASK       (1 << 6)
+#define ENETSW_PORTOV_TXFLOW_MASK       (1 << 5)
+#define ENETSW_PORTOV_RXFLOW_MASK       (1 << 4)
+#define ENETSW_PORTOV_1000_MASK         (1 << 3)
+#define ENETSW_PORTOV_100_MASK          (1 << 2)
+#define ENETSW_PORTOV_FDX_MASK          (1 << 1)
+#define ENETSW_PORTOV_LINKUP_MASK       (1 << 0)
+
+/* MDIO control register */
+#define ENETSW_MDIOC_REG                (0xb0)
+#define ENETSW_MDIOC_EXT_MASK           (1 << 16)
+#define ENETSW_MDIOC_REG_SHIFT          20
+#define ENETSW_MDIOC_PHYID_SHIFT        25
+#define ENETSW_MDIOC_RD_MASK            (1 << 30)
+#define ENETSW_MDIOC_WR_MASK            (1 << 31)
+
+/* MDIO data register */
+#define ENETSW_MDIOD_REG                (0xb4)
+
+/* Global Management Configuration Register */
+#define ENETSW_GMCR_REG                 (0x200)
+#define ENETSW_GMCR_RST_MIB_MASK        (1 << 0)
+
+/* MIB register */
+#define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
+#define ENETSW_MIB_REG_COUNT            47
+
+/* Jumbo control register port mask register */
+#define ENETSW_JMBCTL_PORT_REG          (0x4004)
+
+/* Jumbo control mib good frame register */
+#define ENETSW_JMBCTL_MAXSIZE_REG       (0x4008)
+
+
+/*************************************************************************
+ * _REG relative to RSET_OHCI_PRIV
+ *************************************************************************/
+
+#define OHCI_PRIV_REG                   0x0
+#define OHCI_PRIV_PORT1_HOST_SHIFT      0
+#define OHCI_PRIV_PORT1_HOST_MASK       (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
+#define OHCI_PRIV_REG_SWAP_SHIFT        3
+#define OHCI_PRIV_REG_SWAP_MASK         (1 << OHCI_PRIV_REG_SWAP_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_USBH_PRIV
+ *************************************************************************/
+
+#define USBH_PRIV_SWAP_6358_REG         0x0
+#define USBH_PRIV_SWAP_6368_REG         0x1c
+
+#define USBH_PRIV_SWAP_USBD_SHIFT       6
+#define USBH_PRIV_SWAP_USBD_MASK        (1 << USBH_PRIV_SWAP_USBD_SHIFT)
+#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
+#define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
+#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
+#define USBH_PRIV_SWAP_EHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
+#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT  1
+#define USBH_PRIV_SWAP_OHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
+#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
+#define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
+
+#define USBH_PRIV_UTMI_CTL_6368_REG     0x10
+#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
+#define USBH_PRIV_UTMI_CTL_NODRIV_MASK  (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
+#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT  0
+#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
+
+#define USBH_PRIV_TEST_6358_REG         0x24
+#define USBH_PRIV_TEST_6368_REG         0x14
+
+#define USBH_PRIV_SETUP_6368_REG        0x28
+#define USBH_PRIV_SETUP_IOC_SHIFT       4
+#define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_USBD
+ *************************************************************************/
+
+/* General control */
+#define USBD_CONTROL_REG                0x00
+#define USBD_CONTROL_TXZLENINS_SHIFT    14
+#define USBD_CONTROL_TXZLENINS_MASK     (1 << USBD_CONTROL_TXZLENINS_SHIFT)
+#define USBD_CONTROL_AUTO_CSRS_SHIFT    13
+#define USBD_CONTROL_AUTO_CSRS_MASK     (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
+#define USBD_CONTROL_RXZSCFG_SHIFT      12
+#define USBD_CONTROL_RXZSCFG_MASK       (1 << USBD_CONTROL_RXZSCFG_SHIFT)
+#define USBD_CONTROL_INIT_SEL_SHIFT     8
+#define USBD_CONTROL_INIT_SEL_MASK      (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
+#define USBD_CONTROL_FIFO_RESET_SHIFT   6
+#define USBD_CONTROL_FIFO_RESET_MASK    (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
+#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
+#define USBD_CONTROL_SETUPERRLOCK_MASK  (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
+#define USBD_CONTROL_DONE_CSRS_SHIFT    0
+#define USBD_CONTROL_DONE_CSRS_MASK     (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
+
+/* Strap options */
+#define USBD_STRAPS_REG                 0x04
+#define USBD_STRAPS_APP_SELF_PWR_SHIFT  10
+#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
+#define USBD_STRAPS_APP_DISCON_SHIFT    9
+#define USBD_STRAPS_APP_DISCON_MASK     (1 << USBD_STRAPS_APP_DISCON_SHIFT)
+#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
+#define USBD_STRAPS_APP_CSRPRGSUP_MASK  (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
+#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
+#define USBD_STRAPS_APP_RMTWKUP_MASK    (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
+#define USBD_STRAPS_APP_RAM_IF_SHIFT    7
+#define USBD_STRAPS_APP_RAM_IF_MASK     (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
+#define USBD_STRAPS_APP_8BITPHY_SHIFT   2
+#define USBD_STRAPS_APP_8BITPHY_MASK    (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
+#define USBD_STRAPS_SPEED_SHIFT         0
+#define USBD_STRAPS_SPEED_MASK          (3 << USBD_STRAPS_SPEED_SHIFT)
+
+/* Stall control */
+#define USBD_STALL_REG                  0x08
+#define USBD_STALL_UPDATE_SHIFT         7
+#define USBD_STALL_UPDATE_MASK          (1 << USBD_STALL_UPDATE_SHIFT)
+#define USBD_STALL_ENABLE_SHIFT         6
+#define USBD_STALL_ENABLE_MASK          (1 << USBD_STALL_ENABLE_SHIFT)
+#define USBD_STALL_EPNUM_SHIFT          0
+#define USBD_STALL_EPNUM_MASK           (0xf << USBD_STALL_EPNUM_SHIFT)
+
+/* General status */
+#define USBD_STATUS_REG                 0x0c
+#define USBD_STATUS_SOF_SHIFT           16
+#define USBD_STATUS_SOF_MASK            (0x7ff << USBD_STATUS_SOF_SHIFT)
+#define USBD_STATUS_SPD_SHIFT           12
+#define USBD_STATUS_SPD_MASK            (3 << USBD_STATUS_SPD_SHIFT)
+#define USBD_STATUS_ALTINTF_SHIFT       8
+#define USBD_STATUS_ALTINTF_MASK        (0xf << USBD_STATUS_ALTINTF_SHIFT)
+#define USBD_STATUS_INTF_SHIFT          4
+#define USBD_STATUS_INTF_MASK           (0xf << USBD_STATUS_INTF_SHIFT)
+#define USBD_STATUS_CFG_SHIFT           0
+#define USBD_STATUS_CFG_MASK            (0xf << USBD_STATUS_CFG_SHIFT)
+
+/* Other events */
+#define USBD_EVENTS_REG                 0x10
+#define USBD_EVENTS_USB_LINK_SHIFT      10
+#define USBD_EVENTS_USB_LINK_MASK       (1 << USBD_EVENTS_USB_LINK_SHIFT)
+
+/* IRQ status */
+#define USBD_EVENT_IRQ_STATUS_REG       0x14
+
+/* IRQ level (2 bits per IRQ event) */
+#define USBD_EVENT_IRQ_CFG_HI_REG       0x18
+
+#define USBD_EVENT_IRQ_CFG_LO_REG       0x1c
+
+#define USBD_EVENT_IRQ_CFG_SHIFT(x)     ((x & 0xf) << 1)
+#define USBD_EVENT_IRQ_CFG_MASK(x)      (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_RISING(x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+
+/* IRQ mask (1=unmasked) */
+#define USBD_EVENT_IRQ_MASK_REG         0x20
+
+/* IRQ bits */
+#define USBD_EVENT_IRQ_USB_LINK         10
+#define USBD_EVENT_IRQ_SETCFG           9
+#define USBD_EVENT_IRQ_SETINTF          8
+#define USBD_EVENT_IRQ_ERRATIC_ERR      7
+#define USBD_EVENT_IRQ_SET_CSRS         6
+#define USBD_EVENT_IRQ_SUSPEND          5
+#define USBD_EVENT_IRQ_EARLY_SUSPEND    4
+#define USBD_EVENT_IRQ_SOF              3
+#define USBD_EVENT_IRQ_ENUM_ON          2
+#define USBD_EVENT_IRQ_SETUP            1
+#define USBD_EVENT_IRQ_USB_RESET        0
+
+/* TX FIFO partitioning */
+#define USBD_TXFIFO_CONFIG_REG          0x40
+#define USBD_TXFIFO_CONFIG_END_SHIFT    16
+#define USBD_TXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_TXFIFO_CONFIG_START_SHIFT  0
+#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* RX FIFO partitioning */
+#define USBD_RXFIFO_CONFIG_REG          0x44
+#define USBD_RXFIFO_CONFIG_END_SHIFT    16
+#define USBD_RXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_RXFIFO_CONFIG_START_SHIFT  0
+#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* TX FIFO/endpoint configuration */
+#define USBD_TXFIFO_EPSIZE_REG          0x48
+
+/* RX FIFO/endpoint configuration */
+#define USBD_RXFIFO_EPSIZE_REG          0x4c
+
+/* Endpoint<->DMA mappings */
+#define USBD_EPNUM_TYPEMAP_REG          0x50
+#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
+#define USBD_EPNUM_TYPEMAP_TYPE_MASK    (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
+#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
+#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK  (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
+
+/* Misc per-endpoint settings */
+#define USBD_CSR_SETUPADDR_REG          0x80
+#define USBD_CSR_SETUPADDR_DEF          0xb550
+
+#define USBD_CSR_EP_REG(x)              (0x84 + (x) * 4)
+#define USBD_CSR_EP_MAXPKT_SHIFT        19
+#define USBD_CSR_EP_MAXPKT_MASK         (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
+#define USBD_CSR_EP_ALTIFACE_SHIFT      15
+#define USBD_CSR_EP_ALTIFACE_MASK       (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
+#define USBD_CSR_EP_IFACE_SHIFT         11
+#define USBD_CSR_EP_IFACE_MASK          (0xf << USBD_CSR_EP_IFACE_SHIFT)
+#define USBD_CSR_EP_CFG_SHIFT           7
+#define USBD_CSR_EP_CFG_MASK            (0xf << USBD_CSR_EP_CFG_SHIFT)
+#define USBD_CSR_EP_TYPE_SHIFT          5
+#define USBD_CSR_EP_TYPE_MASK           (3 << USBD_CSR_EP_TYPE_SHIFT)
+#define USBD_CSR_EP_DIR_SHIFT           4
+#define USBD_CSR_EP_DIR_MASK            (1 << USBD_CSR_EP_DIR_SHIFT)
+#define USBD_CSR_EP_LOG_SHIFT           0
+#define USBD_CSR_EP_LOG_MASK            (0xf << USBD_CSR_EP_LOG_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_MPI
+ *************************************************************************/
+
+/* well known (hard wired) chip select */
+#define MPI_CS_PCMCIA_COMMON            4
+#define MPI_CS_PCMCIA_ATTR              5
+#define MPI_CS_PCMCIA_IO                6
+
+/* Chip select base register */
+#define MPI_CSBASE_REG(x)               (0x0 + (x) * 8)
+#define MPI_CSBASE_BASE_SHIFT           13
+#define MPI_CSBASE_BASE_MASK            (0x1ffff << MPI_CSBASE_BASE_SHIFT)
+#define MPI_CSBASE_SIZE_SHIFT           0
+#define MPI_CSBASE_SIZE_MASK            (0xf << MPI_CSBASE_SIZE_SHIFT)
+
+#define MPI_CSBASE_SIZE_8K              0
+#define MPI_CSBASE_SIZE_16K             1
+#define MPI_CSBASE_SIZE_32K             2
+#define MPI_CSBASE_SIZE_64K             3
+#define MPI_CSBASE_SIZE_128K            4
+#define MPI_CSBASE_SIZE_256K            5
+#define MPI_CSBASE_SIZE_512K            6
+#define MPI_CSBASE_SIZE_1M              7
+#define MPI_CSBASE_SIZE_2M              8
+#define MPI_CSBASE_SIZE_4M              9
+#define MPI_CSBASE_SIZE_8M              10
+#define MPI_CSBASE_SIZE_16M             11
+#define MPI_CSBASE_SIZE_32M             12
+#define MPI_CSBASE_SIZE_64M             13
+#define MPI_CSBASE_SIZE_128M            14
+#define MPI_CSBASE_SIZE_256M            15
+
+/* Chip select control register */
+#define MPI_CSCTL_REG(x)                (0x4 + (x) * 8)
+#define MPI_CSCTL_ENABLE_MASK           (1 << 0)
+#define MPI_CSCTL_WAIT_SHIFT            1
+#define MPI_CSCTL_WAIT_MASK             (0x7 << MPI_CSCTL_WAIT_SHIFT)
+#define MPI_CSCTL_DATA16_MASK           (1 << 4)
+#define MPI_CSCTL_SYNCMODE_MASK         (1 << 7)
+#define MPI_CSCTL_TSIZE_MASK            (1 << 8)
+#define MPI_CSCTL_ENDIANSWAP_MASK       (1 << 10)
+#define MPI_CSCTL_SETUP_SHIFT           16
+#define MPI_CSCTL_SETUP_MASK            (0xf << MPI_CSCTL_SETUP_SHIFT)
+#define MPI_CSCTL_HOLD_SHIFT            20
+#define MPI_CSCTL_HOLD_MASK             (0xf << MPI_CSCTL_HOLD_SHIFT)
+
+/* PCI registers */
+#define MPI_SP0_RANGE_REG               0x100
+#define MPI_SP0_REMAP_REG               0x104
+#define MPI_SP0_REMAP_ENABLE_MASK       (1 << 0)
+#define MPI_SP1_RANGE_REG               0x10C
+#define MPI_SP1_REMAP_REG               0x110
+#define MPI_SP1_REMAP_ENABLE_MASK       (1 << 0)
+
+#define MPI_L2PCFG_REG                  0x11C
+#define MPI_L2PCFG_CFG_TYPE_SHIFT       0
+#define MPI_L2PCFG_CFG_TYPE_MASK        (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
+#define MPI_L2PCFG_REG_SHIFT            2
+#define MPI_L2PCFG_REG_MASK             (0x3f << MPI_L2PCFG_REG_SHIFT)
+#define MPI_L2PCFG_FUNC_SHIFT           8
+#define MPI_L2PCFG_FUNC_MASK            (0x7 << MPI_L2PCFG_FUNC_SHIFT)
+#define MPI_L2PCFG_DEVNUM_SHIFT         11
+#define MPI_L2PCFG_DEVNUM_MASK          (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
+#define MPI_L2PCFG_CFG_USEREG_MASK      (1 << 30)
+#define MPI_L2PCFG_CFG_SEL_MASK         (1 << 31)
+
+#define MPI_L2PMEMRANGE1_REG            0x120
+#define MPI_L2PMEMBASE1_REG             0x124
+#define MPI_L2PMEMREMAP1_REG            0x128
+#define MPI_L2PMEMRANGE2_REG            0x12C
+#define MPI_L2PMEMBASE2_REG             0x130
+#define MPI_L2PMEMREMAP2_REG            0x134
+#define MPI_L2PIORANGE_REG              0x138
+#define MPI_L2PIOBASE_REG               0x13C
+#define MPI_L2PIOREMAP_REG              0x140
+#define MPI_L2P_BASE_MASK               (0xffff8000)
+#define MPI_L2PREMAP_ENABLED_MASK       (1 << 0)
+#define MPI_L2PREMAP_IS_CARDBUS_MASK    (1 << 2)
+
+#define MPI_PCIMODESEL_REG              0x144
+#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
+#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
+#define MPI_PCIMODESEL_EXT_ARB_MASK     (1 << 2)
+#define MPI_PCIMODESEL_PREFETCH_SHIFT   4
+#define MPI_PCIMODESEL_PREFETCH_MASK    (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
+
+#define MPI_LOCBUSCTL_REG               0x14C
+#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK  (1 << 0)
+#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
+
+#define MPI_LOCINT_REG                  0x150
+#define MPI_LOCINT_MASK(x)              (1 << (x + 16))
+#define MPI_LOCINT_STAT(x)              (1 << (x))
+#define MPI_LOCINT_DIR_FAILED           6
+#define MPI_LOCINT_EXT_PCI_INT          7
+#define MPI_LOCINT_SERR                 8
+#define MPI_LOCINT_CSERR                9
+
+#define MPI_PCICFGCTL_REG               0x178
+#define MPI_PCICFGCTL_CFGADDR_SHIFT     2
+#define MPI_PCICFGCTL_CFGADDR_MASK      (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
+#define MPI_PCICFGCTL_WRITEEN_MASK      (1 << 7)
+
+#define MPI_PCICFGDATA_REG              0x17C
+
+/* PCI host bridge custom register */
+#define BCMPCI_REG_TIMERS               0x40
+#define REG_TIMER_TRDY_SHIFT            0
+#define REG_TIMER_TRDY_MASK             (0xff << REG_TIMER_TRDY_SHIFT)
+#define REG_TIMER_RETRY_SHIFT           8
+#define REG_TIMER_RETRY_MASK            (0xff << REG_TIMER_RETRY_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_PCMCIA
+ *************************************************************************/
+
+#define PCMCIA_C1_REG                   0x0
+#define PCMCIA_C1_CD1_MASK              (1 << 0)
+#define PCMCIA_C1_CD2_MASK              (1 << 1)
+#define PCMCIA_C1_VS1_MASK              (1 << 2)
+#define PCMCIA_C1_VS2_MASK              (1 << 3)
+#define PCMCIA_C1_VS1OE_MASK            (1 << 6)
+#define PCMCIA_C1_VS2OE_MASK            (1 << 7)
+#define PCMCIA_C1_CBIDSEL_SHIFT         (8)
+#define PCMCIA_C1_CBIDSEL_MASK          (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
+#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
+#define PCMCIA_C1_EN_PCMCIA_MASK        (1 << 14)
+#define PCMCIA_C1_EN_CARDBUS_MASK       (1 << 15)
+#define PCMCIA_C1_RESET_MASK            (1 << 18)
+
+#define PCMCIA_C2_REG                   0x8
+#define PCMCIA_C2_DATA16_MASK           (1 << 0)
+#define PCMCIA_C2_BYTESWAP_MASK         (1 << 1)
+#define PCMCIA_C2_RWCOUNT_SHIFT         2
+#define PCMCIA_C2_RWCOUNT_MASK          (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
+#define PCMCIA_C2_INACTIVE_SHIFT        8
+#define PCMCIA_C2_INACTIVE_MASK         (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
+#define PCMCIA_C2_SETUP_SHIFT           16
+#define PCMCIA_C2_SETUP_MASK            (0x3f << PCMCIA_C2_SETUP_SHIFT)
+#define PCMCIA_C2_HOLD_SHIFT            24
+#define PCMCIA_C2_HOLD_MASK             (0x3f << PCMCIA_C2_HOLD_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_SDRAM
+ *************************************************************************/
+
+#define SDRAM_CFG_REG                   0x0
+#define SDRAM_CFG_ROW_SHIFT             4
+#define SDRAM_CFG_ROW_MASK              (0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_COL_SHIFT             6
+#define SDRAM_CFG_COL_MASK              (0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_32B_SHIFT             10
+#define SDRAM_CFG_32B_MASK              (1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT            13
+#define SDRAM_CFG_BANK_MASK             (1 << SDRAM_CFG_BANK_SHIFT)
+
+#define SDRAM_MBASE_REG                 0xc
+
+#define SDRAM_PRIO_REG                  0x2C
+#define SDRAM_PRIO_MIPS_SHIFT           29
+#define SDRAM_PRIO_MIPS_MASK            (1 << SDRAM_PRIO_MIPS_SHIFT)
+#define SDRAM_PRIO_ADSL_SHIFT           30
+#define SDRAM_PRIO_ADSL_MASK            (1 << SDRAM_PRIO_ADSL_SHIFT)
+#define SDRAM_PRIO_EN_SHIFT             31
+#define SDRAM_PRIO_EN_MASK              (1 << SDRAM_PRIO_EN_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_MEMC
+ *************************************************************************/
+
+#define MEMC_CFG_REG                    0x4
+#define MEMC_CFG_32B_SHIFT              1
+#define MEMC_CFG_32B_MASK               (1 << MEMC_CFG_32B_SHIFT)
+#define MEMC_CFG_COL_SHIFT              3
+#define MEMC_CFG_COL_MASK               (0x3 << MEMC_CFG_COL_SHIFT)
+#define MEMC_CFG_ROW_SHIFT              6
+#define MEMC_CFG_ROW_MASK               (0x3 << MEMC_CFG_ROW_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_DDR
+ *************************************************************************/
+
+#define DDR_CSEND_REG                   0x8
+
+#define DDR_DMIPSPLLCFG_REG             0x18
+#define DMIPSPLLCFG_M1_SHIFT            0
+#define DMIPSPLLCFG_M1_MASK             (0xff << DMIPSPLLCFG_M1_SHIFT)
+#define DMIPSPLLCFG_N1_SHIFT            23
+#define DMIPSPLLCFG_N1_MASK             (0x3f << DMIPSPLLCFG_N1_SHIFT)
+#define DMIPSPLLCFG_N2_SHIFT            29
+#define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
+
+#define DDR_DMIPSPLLCFG_6368_REG        0x20
+#define DMIPSPLLCFG_6368_P1_SHIFT       0
+#define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT       4
+#define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT     16
+#define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+
+#define DDR_DMIPSPLLDIV_6368_REG        0x24
+#define DMIPSPLLDIV_6368_MDIV_SHIFT     0
+#define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_M2M
+ *************************************************************************/
+
+#define M2M_RX                          0
+#define M2M_TX                          1
+
+#define M2M_SRC_REG(x)                  ((x) * 0x40 + 0x00)
+#define M2M_DST_REG(x)                  ((x) * 0x40 + 0x04)
+#define M2M_SIZE_REG(x)                 ((x) * 0x40 + 0x08)
+
+#define M2M_CTRL_REG(x)                 ((x) * 0x40 + 0x0c)
+#define M2M_CTRL_ENABLE_MASK            (1 << 0)
+#define M2M_CTRL_IRQEN_MASK             (1 << 1)
+#define M2M_CTRL_ERROR_CLR_MASK         (1 << 6)
+#define M2M_CTRL_DONE_CLR_MASK          (1 << 7)
+#define M2M_CTRL_NOINC_MASK             (1 << 8)
+#define M2M_CTRL_PCMCIASWAP_MASK        (1 << 9)
+#define M2M_CTRL_SWAPBYTE_MASK          (1 << 10)
+#define M2M_CTRL_ENDIAN_MASK            (1 << 11)
+
+#define M2M_STAT_REG(x)                 ((x) * 0x40 + 0x10)
+#define M2M_STAT_DONE                   (1 << 0)
+#define M2M_STAT_ERROR                  (1 << 1)
+
+#define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
+#define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
+
+/*************************************************************************
+ * _REG relative to RSET_SPI
+ *************************************************************************/
+
+/* BCM 6338/6348 SPI core */
+#define SPI_6348_CMD                    0x00    /* 16-bits register */
+#define SPI_6348_INT_STATUS             0x02
+#define SPI_6348_INT_MASK_ST            0x03
+#define SPI_6348_INT_MASK               0x04
+#define SPI_6348_ST                     0x05
+#define SPI_6348_CLK_CFG                0x06
+#define SPI_6348_FILL_BYTE              0x07
+#define SPI_6348_MSG_TAIL               0x09
+#define SPI_6348_RX_TAIL                0x0b
+#define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
+#define SPI_6348_MSG_CTL_WIDTH          8
+#define SPI_6348_MSG_DATA               0x41
+#define SPI_6348_MSG_DATA_SIZE          0x3f
+#define SPI_6348_RX_DATA                0x80
+#define SPI_6348_RX_DATA_SIZE           0x3f
+
+/* BCM 3368/6358/6262/6368 SPI core */
+#define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
+#define SPI_6358_MSG_CTL_WIDTH          16
+#define SPI_6358_MSG_DATA               0x02
+#define SPI_6358_MSG_DATA_SIZE          0x21e
+#define SPI_6358_RX_DATA                0x400
+#define SPI_6358_RX_DATA_SIZE           0x220
+#define SPI_6358_CMD                    0x700   /* 16-bits register */
+#define SPI_6358_INT_STATUS             0x702
+#define SPI_6358_INT_MASK_ST            0x703
+#define SPI_6358_INT_MASK               0x704
+#define SPI_6358_ST                     0x705
+#define SPI_6358_CLK_CFG                0x706
+#define SPI_6358_FILL_BYTE              0x707
+#define SPI_6358_MSG_TAIL               0x709
+#define SPI_6358_RX_TAIL                0x70B
+
+/* Shared SPI definitions */
+
+/* Message configuration */
+#define SPI_FD_RW                       0x00
+#define SPI_HD_W                        0x01
+#define SPI_HD_R                        0x02
+#define SPI_BYTE_CNT_SHIFT              0
+#define SPI_6348_MSG_TYPE_SHIFT         6
+#define SPI_6358_MSG_TYPE_SHIFT         14
+
+/* Command */
+#define SPI_CMD_NOOP                    0x00
+#define SPI_CMD_SOFT_RESET              0x01
+#define SPI_CMD_HARD_RESET              0x02
+#define SPI_CMD_START_IMMEDIATE         0x03
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+/* Interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_TX_UNDERFLOW           0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+/* Status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+/* Clock configuration */
+#define SPI_CLK_20MHZ                   0x00
+#define SPI_CLK_0_391MHZ                0x01
+#define SPI_CLK_0_781MHZ                0x02 /* default */
+#define SPI_CLK_1_563MHZ                0x03
+#define SPI_CLK_3_125MHZ                0x04
+#define SPI_CLK_6_250MHZ                0x05
+#define SPI_CLK_12_50MHZ                0x06
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+/*************************************************************************
+ * _REG relative to RSET_MISC
+ *************************************************************************/
+#define MISC_SERDES_CTRL_6328_REG       0x0
+#define MISC_SERDES_CTRL_6362_REG       0x4
+#define SERDES_PCIE_EN                  (1 << 0)
+#define SERDES_PCIE_EXD_EN              (1 << 15)
+
+#define MISC_STRAPBUS_6362_REG          0x14
+#define STRAPBUS_6362_FCVO_SHIFT        1
+#define STRAPBUS_6362_HSSPI_CLK_FAST    (1 << 13)
+#define STRAPBUS_6362_FCVO_MASK         (0x1f << STRAPBUS_6362_FCVO_SHIFT)
+#define STRAPBUS_6362_BOOT_SEL_SERIAL   (1 << 15)
+#define STRAPBUS_6362_BOOT_SEL_NAND     (0 << 15)
+
+#define MISC_STRAPBUS_6328_REG          0x240
+#define STRAPBUS_6328_FCVO_SHIFT        7
+#define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+#define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 18)
+#define STRAPBUS_6328_BOOT_SEL_NAND     (0 << 18)
+
+/*************************************************************************
+ * _REG relative to RSET_PCIE
+ *************************************************************************/
+
+#define PCIE_CONFIG2_REG                0x408
+#define CONFIG2_BAR1_SIZE_EN            1
+#define CONFIG2_BAR1_SIZE_MASK          0xf
+
+#define PCIE_IDVAL3_REG                 0x43c
+#define IDVAL3_CLASS_CODE_MASK          0xffffff
+#define IDVAL3_SUBCLASS_SHIFT           8
+#define IDVAL3_CLASS_SHIFT              16
+
+#define PCIE_DLSTATUS_REG               0x1048
+#define DLSTATUS_PHYLINKUP              (1 << 13)
+
+#define PCIE_BRIDGE_OPT1_REG            0x2820
+#define OPT1_RD_BE_OPT_EN               (1 << 7)
+#define OPT1_RD_REPLY_BE_FIX_EN         (1 << 9)
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN    (1 << 11)
+#define OPT1_L1_INT_STATUS_MASK_POL     (1 << 12)
+
+#define PCIE_BRIDGE_OPT2_REG            0x2824
+#define OPT2_UBUS_UR_DECODE_DIS         (1 << 2)
+#define OPT2_TX_CREDIT_CHK_EN           (1 << 4)
+#define OPT2_CFG_TYPE1_BD_SEL           (1 << 7)
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT     16
+#define OPT2_CFG_TYPE1_BUS_NO_MASK      (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828
+#define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830
+#define BASEMASK_REMAP_EN               (1 << 0)
+#define BASEMASK_SWAP_EN                (1 << 1)
+#define BASEMASK_MASK_SHIFT             4
+#define BASEMASK_MASK_MASK              (0xfff << BASEMASK_MASK_SHIFT)
+#define BASEMASK_BASE_SHIFT             20
+#define BASEMASK_BASE_MASK              (0xfff << BASEMASK_BASE_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
+#define REBASE_ADDR_BASE_SHIFT          20
+#define REBASE_ADDR_BASE_MASK           (0xfff << REBASE_ADDR_BASE_SHIFT)
+
+#define PCIE_BRIDGE_RC_INT_MASK_REG     0x2854
+#define PCIE_RC_INT_A                   (1 << 0)
+#define PCIE_RC_INT_B                   (1 << 1)
+#define PCIE_RC_INT_C                   (1 << 2)
+#define PCIE_RC_INT_D                   (1 << 3)
+
+#define PCIE_DEVICE_OFFSET              0x8000
+
+/*************************************************************************
+ * _REG relative to RSET_OTP
+ *************************************************************************/
+
+#define OTP_USER_BITS_6328_REG(i)       (0x20 + (i) * 4)
+#define   OTP_6328_REG3_TP1_DISABLED    BIT(9)
+
+#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
new file mode 100644
index 000000000..2c0645b7d
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __BCM63XX_RESET_H
+#define __BCM63XX_RESET_H
+
+enum bcm63xx_core_reset {
+        BCM63XX_RESET_SPI,
+        BCM63XX_RESET_ENET,
+        BCM63XX_RESET_USBH,
+        BCM63XX_RESET_USBD,
+        BCM63XX_RESET_SAR,
+        BCM63XX_RESET_DSL,
+        BCM63XX_RESET_EPHY,
+        BCM63XX_RESET_ENETSW,
+        BCM63XX_RESET_PCM,
+        BCM63XX_RESET_MPI,
+        BCM63XX_RESET_PCIE,
+        BCM63XX_RESET_PCIE_EXT,
+};
+
+void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
+
+#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
new file mode 100644
index 000000000..bcbece793
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_TIMER_H_
+#define BCM63XX_TIMER_H_
+
+int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
+void bcm63xx_timer_unregister(int id);
+int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
+int bcm63xx_timer_enable(int id);
+int bcm63xx_timer_disable(int id);
+unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
+
+#endif /* !BCM63XX_TIMER_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
new file mode 100644
index 000000000..830f53f28
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BOARD_BCM963XX_H_
+#define BOARD_BCM963XX_H_
+
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <bcm63xx_dev_enet.h>
+#include <bcm63xx_dev_usb_usbd.h>
+
+/*
+ * flash mapping
+ */
+#define BCM963XX_CFE_VERSION_OFFSET     0x570
+#define BCM963XX_NVRAM_OFFSET           0x580
+
+/*
+ * board definition
+ */
+struct board_info {
+        u8              name[16];
+        unsigned int    expected_cpu_id;
+
+        /* enabled feature/device */
+        unsigned int    has_enet0:1;
+        unsigned int    has_enet1:1;
+        unsigned int    has_enetsw:1;
+        unsigned int    has_pci:1;
+        unsigned int    has_pccard:1;
+        unsigned int    has_ohci0:1;
+        unsigned int    has_ehci0:1;
+        unsigned int    has_usbd:1;
+        unsigned int    has_uart0:1;
+        unsigned int    has_uart1:1;
+
+        /* ethernet config */
+        struct bcm63xx_enet_platform_data enet0;
+        struct bcm63xx_enet_platform_data enet1;
+        struct bcm63xx_enetsw_platform_data enetsw;
+
+        /* USB config */
+        struct bcm63xx_usbd_platform_data usbd;
+
+        /* GPIO LEDs */
+        struct gpio_led leds[5];
+
+        /* External PHY reset GPIO */
+        unsigned int ephy_reset_gpio;
+
+        /* External PHY reset GPIO flags from gpio.h */
+        unsigned long ephy_reset_gpio_flags;
+};
+
+#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
new file mode 100644
index 000000000..0ebecbdb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
+
+#include <bcm63xx_cpu.h>
+
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_4k_cache                1
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_watch                   0
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+#define cpu_has_vtag_icache             0
+
+#if !defined(CONFIG_SYS_HAS_CPU_BMIPS4350)
+#define cpu_has_dc_aliases              0
+#endif
+
+#define cpu_has_ic_fills_f_dc           0
+#define cpu_has_pindexed_dcache         0
+
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_mipsmt                  0
+#define cpu_has_userlocal               0
+
+#define cpu_has_nofpuex                 0
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+#define cpu_scache_line_size()          0
+
+#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 000000000..73f31825b
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef BCM63XX_IOREMAP_H_
+#define BCM63XX_IOREMAP_H_
+
+#include <bcm63xx_cpu.h>
+
+static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM3368_CPU_ID:
+                if (offset >= 0xfff80000)
+                        return 1;
+                break;
+        case BCM6338_CPU_ID:
+        case BCM6345_CPU_ID:
+        case BCM6348_CPU_ID:
+        case BCM6358_CPU_ID:
+                if (offset >= 0xfff00000)
+                        return 1;
+                break;
+        case BCM6328_CPU_ID:
+        case BCM6362_CPU_ID:
+        case BCM6368_CPU_ID:
+                if (offset >= 0xb0000000 && offset < 0xb1000000)
+                        return 1;
+                break;
+        }
+        return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+                                         unsigned long flags)
+{
+        if (is_bcm63xx_internal_registers(offset))
+                return (void __iomem *)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return is_bcm63xx_internal_registers((unsigned long)addr);
+}
+
+#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 000000000..b016f0615
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_BCM63XX_IRQ_H
+#define __ASM_MACH_BCM63XX_IRQ_H
+
+#define NR_IRQS 128
+#define MIPS_CPU_IRQ_BASE 0
+
+#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/spaces.h b/arch/mips/include/asm/mach-bcm63xx/spaces.h
new file mode 100644
index 000000000..1410ed0da
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/spaces.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BCM63XX_SPACES_H
+#define _ASM_BCM63XX_SPACES_H
+
+#include <asm/bmips-spaces.h>
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_BCM63XX_SPACES_H */
diff --git a/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
new file mode 100644
index 000000000..68a219d80
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/cpu-feature-overrides.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H
+
+/* Invariants across all BMIPS processors */
+#define cpu_has_vtag_icache             0
+#define cpu_icache_snoops_remote_store  1
+
+/* Processor ISA compatibility is MIPS32R1 */
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#endif /* __ASM_MACH_BMIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bmips/ioremap.h b/arch/mips/include/asm/mach-bmips/ioremap.h
new file mode 100644
index 000000000..63b4af991
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/ioremap.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_BMIPS_IOREMAP_H
+#define __ASM_MACH_BMIPS_IOREMAP_H
+
+#include <linux/types.h>
+
+static inline int is_bmips_internal_registers(phys_addr_t offset)
+{
+        if (offset >= 0xfff80000)
+                return 1;
+
+        return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+                                         unsigned long flags)
+{
+        if (is_bmips_internal_registers(offset))
+                return (void __iomem *)offset;
+
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return is_bmips_internal_registers((unsigned long)addr);
+}
+
+#endif /* __ASM_MACH_BMIPS_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-bmips/spaces.h b/arch/mips/include/asm/mach-bmips/spaces.h
new file mode 100644
index 000000000..c59b28fd9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/spaces.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BMIPS_SPACES_H
+#define _ASM_BMIPS_SPACES_H
+
+/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
+#include <asm/bmips-spaces.h>
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_BMIPS_SPACES_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 000000000..513270c8a
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Cavium Networks
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/types.h>
+#include <asm/mipsregs.h>
+
+/*
+ * Cavium Octeons are MIPS64v2 processors
+ */
+#define cpu_dcache_line_size()  128
+#define cpu_icache_line_size()  128
+
+
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        0
+#define cpu_has_tx39_cache      0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+
+#define cpu_has_llsc            1
+/*
+ * We Disable LL/SC on non SMP systems as it is faster to disable
+ * interrupts for atomic access than a LL/SC.
+ */
+#ifdef CONFIG_SMP
+# define kernel_uses_llsc       1
+#else
+# define kernel_uses_llsc       0
+#endif
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_64bits          1
+#define cpu_has_octeon_cache    1
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        1
+#define cpu_has_mips64r2        1
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_has_vint            0
+#define cpu_has_veic            0
+#define cpu_hwrena_impl_bits    (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
+#define cpu_has_wsbh            1
+
+#define cpu_has_rixi            (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
+
+#define ARCH_HAS_SPINLOCK_PREFETCH 1
+#define spin_lock_prefetch(x) prefetch(x)
+#define PREFETCH_STRIDE 128
+
+#ifdef __OCTEON__
+/*
+ * All gcc versions that have OCTEON support define __OCTEON__ and have the
+ *  __builtin_popcount support.
+ */
+#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
+#endif
+
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 000000000..64b86b9d3
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,58 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#ifndef __OCTEON_IRQ_H__
+#define __OCTEON_IRQ_H__
+
+#define NR_IRQS OCTEON_IRQ_LAST
+#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
+
+enum octeon_irq {
+/* 1 - 8 represent the 8 MIPS standard interrupt sources */
+        OCTEON_IRQ_SW0 = 1,
+        OCTEON_IRQ_SW1,
+/* CIU0, CUI2, CIU4 are 3, 4, 5 */
+        OCTEON_IRQ_5 = 6,
+        OCTEON_IRQ_PERF,
+        OCTEON_IRQ_TIMER,
+/* sources in CIU_INTX_EN0 */
+        OCTEON_IRQ_WORKQ0,
+        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
+        OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
+        OCTEON_IRQ_MBOX1,
+        OCTEON_IRQ_MBOX2,
+        OCTEON_IRQ_MBOX3,
+        OCTEON_IRQ_PCI_INT0,
+        OCTEON_IRQ_PCI_INT1,
+        OCTEON_IRQ_PCI_INT2,
+        OCTEON_IRQ_PCI_INT3,
+        OCTEON_IRQ_PCI_MSI0,
+        OCTEON_IRQ_PCI_MSI1,
+        OCTEON_IRQ_PCI_MSI2,
+        OCTEON_IRQ_PCI_MSI3,
+
+        OCTEON_IRQ_TWSI,
+        OCTEON_IRQ_TWSI2,
+        OCTEON_IRQ_RML,
+        OCTEON_IRQ_TIMER0,
+        OCTEON_IRQ_TIMER1,
+        OCTEON_IRQ_TIMER2,
+        OCTEON_IRQ_TIMER3,
+#ifndef CONFIG_PCI_MSI
+        OCTEON_IRQ_LAST = 127
+#endif
+};
+
+#ifdef CONFIG_PCI_MSI
+/* 256 - 511 represent the MSI interrupts 0-255 */
+#define OCTEON_IRQ_MSI_BIT0     (256)
+
+#define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
+#define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 000000000..c38b38ce5
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,160 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2008 Cavium Networks, Inc
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+
+#define CP0_CVMCTL_REG $9, 7
+#define CP0_CVMMEMCTL_REG $11,7
+#define CP0_PRID_REG $15, 0
+#define CP0_DCACHE_ERR_REG $27, 1
+#define CP0_PRID_OCTEON_PASS1 0x000d0000
+#define CP0_PRID_OCTEON_CN30XX 0x000d0200
+
+.macro  kernel_entry_setup
+        # Registers set by bootloader:
+        # (only 32 bits set by bootloader, all addresses are physical
+        # addresses, and need to have the appropriate memory region set
+        # by the kernel
+        # a0 = argc
+        # a1 = argv (kseg0 compat addr)
+        # a2 = 1 if init core, zero otherwise
+        # a3 = address of boot descriptor block
+        .set push
+        .set arch=octeon
+        # Read the cavium mem control register
+        dmfc0   v0, CP0_CVMMEMCTL_REG
+        # Clear the lower 6 bits, the CVMSEG size
+        dins    v0, $0, 0, 6
+        ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+        dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
+        dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
+        # Disable unaligned load/store support but leave HW fixup enabled
+        # Needed for octeon specific memcpy
+        or  v0, v0, 0x5001
+        xor v0, v0, 0x1001
+        # First clear off CvmCtl[IPPCI] bit and move the performance
+        # counters interrupt to IRQ 6
+        dli     v1, ~(7 << 7)
+        and     v0, v0, v1
+        ori     v0, v0, (6 << 7)
+
+        mfc0    v1, CP0_PRID_REG
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9000          # 63-P1
+        beqz    t1, 4f
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9008          # 63-P2
+        beqz    t1, 4f
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9100          # 68-P1
+        beqz    t1, 4f
+        and     t1, v1, 0xff00
+        xor     t1, t1, 0x9200          # 66-PX
+        bnez    t1, 5f                  # Skip WAR for others.
+        and     t1, v1, 0x00ff
+        slti    t1, t1, 2               # 66-P1.2 and later good.
+        beqz    t1, 5f
+
+4:      # core-16057 work around
+        or      v0, v0, 0x2000          # Set IPREF bit.
+
+5:      # No core-16057 work around
+        # Write the cavium control register
+        dmtc0   v0, CP0_CVMCTL_REG
+        sync
+        # Flush dcache after config change
+        cache   9, 0($0)
+        # Zero all of CVMSEG to make sure parity is correct
+        dli     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+        dsll    v0, 7
+        beqz    v0, 2f
+1:      dsubu   v0, 8
+        sd      $0, -32768(v0)
+        bnez    v0, 1b
+2:
+        mfc0    v0, CP0_PRID_REG
+        bbit0   v0, 15, 1f
+        # OCTEON II or better have bit 15 set.  Clear the error bits.
+        and     t1, v0, 0xff00
+        dli     v0, 0x9500
+        bge     t1, v0, 1f  # OCTEON III has no DCACHE_ERR_REG COP0
+        dli     v0, 0x27
+        dmtc0   v0, CP0_DCACHE_ERR_REG
+1:
+        # Get my core id
+        rdhwr   v0, $0
+        # Jump the master to kernel_entry
+        bne     a2, zero, octeon_main_processor
+        nop
+
+#ifdef CONFIG_SMP
+
+        #
+        # All cores other than the master need to wait here for SMP bootstrap
+        # to begin
+        #
+
+octeon_spin_wait_boot:
+#ifdef CONFIG_RELOCATABLE
+        PTR_LA  t0, octeon_processor_relocated_kernel_entry
+        LONG_L  t0, (t0)
+        beq     zero, t0, 1f
+        nop
+
+        jr      t0
+        nop
+1:
+#endif /* CONFIG_RELOCATABLE */
+
+        # This is the variable where the next core to boot is stored
+        PTR_LA  t0, octeon_processor_boot
+        # Get the core id of the next to be booted
+        LONG_L  t1, (t0)
+        # Keep looping if it isn't me
+        bne t1, v0, octeon_spin_wait_boot
+        nop
+        # Get my GP from the global variable
+        PTR_LA  t0, octeon_processor_gp
+        LONG_L  gp, (t0)
+        # Get my SP from the global variable
+        PTR_LA  t0, octeon_processor_sp
+        LONG_L  sp, (t0)
+        # Set the SP global variable to zero so the master knows we've started
+        LONG_S  zero, (t0)
+#ifdef __OCTEON__
+        syncw
+        syncw
+#else
+        sync
+#endif
+        # Jump to the normal Linux SMP entry point
+        j   smp_bootstrap
+        nop
+#else /* CONFIG_SMP */
+
+        #
+        # Someone tried to boot SMP with a non SMP kernel. All extra cores
+        # will halt here.
+        #
+octeon_wait_forever:
+        wait
+        b   octeon_wait_forever
+        nop
+
+#endif /* CONFIG_SMP */
+octeon_main_processor:
+        .set pop
+.endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
new file mode 100644
index 000000000..239fcc874
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+
+static inline bool __should_swizzle_bits(volatile void *a)
+{
+        extern const bool octeon_should_swizzle_table[];
+        u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
+
+        return octeon_should_swizzle_table[did];
+}
+
+# define __swizzle_addr_b(port) (port)
+# define __swizzle_addr_w(port) (port)
+# define __swizzle_addr_l(port) (port)
+# define __swizzle_addr_q(port) (port)
+
+#else /* __LITTLE_ENDIAN */
+
+#define __should_swizzle_bits(a)        false
+
+static inline bool __should_swizzle_addr(u64 p)
+{
+        /* boot bus? */
+        return ((p >> 40) & 0xff) == 0;
+}
+
+# define __swizzle_addr_b(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port) (port)
+
+#endif /* __BIG_ENDIAN */
+
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (__should_swizzle_bits(a) ?             \
+                                 le16_to_cpu((__force __le16)(x)) :     \
+                                 (x))
+# define __mem_ioswabw(a, x)    (x)
+# define ioswabl(a, x)          (__should_swizzle_bits(a) ?             \
+                                 le32_to_cpu((__force __le32)(x)) :     \
+                                 (x))
+# define __mem_ioswabl(a, x)    (x)
+# define ioswabq(a, x)          (__should_swizzle_bits(a) ?             \
+                                 le64_to_cpu((__force __le64)(x)) :     \
+                                 (x))
+# define __mem_ioswabq(a, x)    (x)
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
new file mode 100644
index 000000000..daa91accf
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Cavium, Inc.
+ */
+#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
+
+#include <linux/const.h>
+
+#ifdef CONFIG_64BIT
+/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
+#define CAC_BASE                _AC(0x8000000000000000, UL)
+#define UNCAC_BASE              _AC(0x8000000000000000, UL)
+#define IO_BASE                 _AC(0x8000000000000000, UL)
+
+
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cobalt.h b/arch/mips/include/asm/mach-cobalt/cobalt.h
new file mode 100644
index 000000000..5b9fce73f
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/cobalt.h
@@ -0,0 +1,22 @@
+/*
+ * The Cobalt board ID information.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
+ */
+#ifndef __ASM_COBALT_H
+#define __ASM_COBALT_H
+
+extern int cobalt_board_id;
+
+#define COBALT_BRD_ID_QUBE1    0x3
+#define COBALT_BRD_ID_RAQ1     0x4
+#define COBALT_BRD_ID_QUBE2    0x5
+#define COBALT_BRD_ID_RAQ2     0x6
+
+#endif /* __ASM_COBALT_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
new file mode 100644
index 000000000..291fe90aa
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -0,0 +1,57 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_watch           0
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_inclusive_pcaches       0
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  0
+
+#ifdef CONFIG_64BIT
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-cobalt/irq.h b/arch/mips/include/asm/mach-cobalt/irq.h
new file mode 100644
index 000000000..9da9acf5d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/irq.h
@@ -0,0 +1,57 @@
+/*
+ * Cobalt IRQ definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
+ * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef _ASM_COBALT_IRQ_H
+#define _ASM_COBALT_IRQ_H
+
+/*
+ * i8259 interrupts used on Cobalt:
+ *
+ *      8  - RTC
+ *      9  - PCI slot
+ *      14 - IDE0
+ *      15 - IDE1(no connector on board)
+ */
+#define I8259A_IRQ_BASE                 0
+
+#define PCISLOT_IRQ                     (I8259A_IRQ_BASE + 9)
+
+/*
+ * CPU interrupts used on Cobalt:
+ *
+ *      0 - Software interrupt 0 (unused)
+ *      1 - Software interrupt 0 (unused)
+ *      2 - cascade GT64111
+ *      3 - ethernet or SCSI host controller
+ *      4 - ethernet
+ *      5 - 16550 UART
+ *      6 - cascade i8259
+ *      7 - CP0 counter
+ */
+#define MIPS_CPU_IRQ_BASE               16
+
+#define GT641XX_CASCADE_IRQ             (MIPS_CPU_IRQ_BASE + 2)
+#define RAQ2_SCSI_IRQ                   (MIPS_CPU_IRQ_BASE + 3)
+#define ETH0_IRQ                        (MIPS_CPU_IRQ_BASE + 3)
+#define QUBE1_ETH0_IRQ                  (MIPS_CPU_IRQ_BASE + 4)
+#define ETH1_IRQ                        (MIPS_CPU_IRQ_BASE + 4)
+#define SERIAL_IRQ                      (MIPS_CPU_IRQ_BASE + 5)
+#define SCSI_IRQ                        (MIPS_CPU_IRQ_BASE + 5)
+#define I8259_CASCADE_IRQ               (MIPS_CPU_IRQ_BASE + 6)
+
+#define GT641XX_IRQ_BASE                24
+
+#include <asm/irq_gt641xx.h>
+
+#define NR_IRQS                                 (GT641XX_PCI_INT3_IRQ + 1)
+
+#endif /* _ASM_COBALT_IRQ_H */
diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
new file mode 100644
index 000000000..ddb968a55
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Copyright (C) 2006  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef _COBALT_MACH_GT64120_H
+#define _COBALT_MACH_GT64120_H
+
+/*
+ * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
+ */
+
+#define GT64120_BASE    CKSEG1ADDR(GT_DEF_BASE)
+
+#endif /* _COBALT_MACH_GT64120_H */
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
new file mode 100644
index 000000000..4a27738e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
+ *
+ * All Alchemy development boards (except, of course, the weird PB1000)
+ * have a few registers in a CPLD with standardised layout; they mostly
+ * only differ in base address and bit meanings in the RESETS and BOARD
+ * registers.
+ *
+ * All data taken from the official AMD board documentation sheets.
+ */
+
+#ifndef _DB1XXX_BCSR_H_
+#define _DB1XXX_BCSR_H_
+
+
+/* BCSR base addresses on various boards. BCSR base 2 refers to the
+ * physical address of the first HEXLEDS register, which is usually
+ * a variable offset from the WHOAMI register.
+ */
+
+/* DB1000, DB1100, DB1500, PB1100, PB1500 */
+#define DB1000_BCSR_PHYS_ADDR   0x0E000000
+#define DB1000_BCSR_HEXLED_OFS  0x01000000
+
+#define DB1550_BCSR_PHYS_ADDR   0x0F000000
+#define DB1550_BCSR_HEXLED_OFS  0x00400000
+
+#define PB1550_BCSR_PHYS_ADDR   0x0F000000
+#define PB1550_BCSR_HEXLED_OFS  0x00800000
+
+#define DB1200_BCSR_PHYS_ADDR   0x19800000
+#define DB1200_BCSR_HEXLED_OFS  0x00400000
+
+#define PB1200_BCSR_PHYS_ADDR   0x0D800000
+#define PB1200_BCSR_HEXLED_OFS  0x00400000
+
+#define DB1300_BCSR_PHYS_ADDR   0x19800000
+#define DB1300_BCSR_HEXLED_OFS  0x00400000
+
+enum bcsr_id {
+        /* BCSR base 1 */
+        BCSR_WHOAMI     = 0,
+        BCSR_STATUS,
+        BCSR_SWITCHES,
+        BCSR_RESETS,
+        BCSR_PCMCIA,
+        BCSR_BOARD,
+        BCSR_LEDS,
+        BCSR_SYSTEM,
+        /* Au1200/1300 based boards */
+        BCSR_INTCLR,
+        BCSR_INTSET,
+        BCSR_MASKCLR,
+        BCSR_MASKSET,
+        BCSR_SIGSTAT,
+        BCSR_INTSTAT,
+
+        /* BCSR base 2 */
+        BCSR_HEXLEDS,
+        BCSR_RSVD1,
+        BCSR_HEXCLEAR,
+
+        BCSR_CNT,
+};
+
+/* register offsets, valid for all Db1xxx/Pb1xxx boards */
+#define BCSR_REG_WHOAMI         0x00
+#define BCSR_REG_STATUS         0x04
+#define BCSR_REG_SWITCHES       0x08
+#define BCSR_REG_RESETS         0x0c
+#define BCSR_REG_PCMCIA         0x10
+#define BCSR_REG_BOARD          0x14
+#define BCSR_REG_LEDS           0x18
+#define BCSR_REG_SYSTEM         0x1c
+/* Au1200/Au1300 based boards: CPLD IRQ muxer */
+#define BCSR_REG_INTCLR         0x20
+#define BCSR_REG_INTSET         0x24
+#define BCSR_REG_MASKCLR        0x28
+#define BCSR_REG_MASKSET        0x2c
+#define BCSR_REG_SIGSTAT        0x30
+#define BCSR_REG_INTSTAT        0x34
+
+/* hexled control, offset from BCSR base 2 */
+#define BCSR_REG_HEXLEDS        0x00
+#define BCSR_REG_HEXCLEAR       0x08
+
+/*
+ * Register Bits and Pieces.
+ */
+#define BCSR_WHOAMI_DCID(x)             ((x) & 0xf)
+#define BCSR_WHOAMI_CPLD(x)             (((x) >> 4) & 0xf)
+#define BCSR_WHOAMI_BOARD(x)            (((x) >> 8) & 0xf)
+
+/* register "WHOAMI" bits 11:8 identify the board */
+enum bcsr_whoami_boards {
+        BCSR_WHOAMI_PB1500 = 1,
+        BCSR_WHOAMI_PB1500R2,
+        BCSR_WHOAMI_PB1100,
+        BCSR_WHOAMI_DB1000,
+        BCSR_WHOAMI_DB1100,
+        BCSR_WHOAMI_DB1500,
+        BCSR_WHOAMI_DB1550,
+        BCSR_WHOAMI_PB1550_DDR,
+        BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
+        BCSR_WHOAMI_PB1550_SDR,
+        BCSR_WHOAMI_PB1200_DDR1,
+        BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
+        BCSR_WHOAMI_PB1200_DDR2,
+        BCSR_WHOAMI_DB1200,
+        BCSR_WHOAMI_DB1300,
+};
+
+/* STATUS reg.  Unless otherwise noted, they're valid on all boards.
+ * PB1200 = DB1200.
+ */
+#define BCSR_STATUS_PC0VS               0x0003
+#define BCSR_STATUS_PC1VS               0x000C
+#define BCSR_STATUS_PC0FI               0x0010
+#define BCSR_STATUS_PC1FI               0x0020
+#define BCSR_STATUS_PB1550_SWAPBOOT     0x0040
+#define BCSR_STATUS_SRAMWIDTH           0x0080
+#define BCSR_STATUS_FLASHBUSY           0x0100
+#define BCSR_STATUS_ROMBUSY             0x0400
+#define BCSR_STATUS_SD0WP               0x0400  /* DB1200/DB1300:SD1 */
+#define BCSR_STATUS_SD1WP               0x0800
+#define BCSR_STATUS_USBOTGID            0x0800  /* PB/DB1550 */
+#define BCSR_STATUS_DB1000_SWAPBOOT     0x2000
+#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200/1300 */
+#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200/1300 */
+#define BCSR_STATUS_DB1200_U0RXD        0x1000  /* DB1200 */
+#define BCSR_STATUS_DB1200_U1RXD        0x2000  /* DB1200 */
+#define BCSR_STATUS_FLASHDEN            0xC000
+#define BCSR_STATUS_DB1550_U0RXD        0x1000  /* DB1550 */
+#define BCSR_STATUS_DB1550_U3RXD        0x2000  /* DB1550 */
+#define BCSR_STATUS_PB1550_U0RXD        0x1000  /* PB1550 */
+#define BCSR_STATUS_PB1550_U1RXD        0x2000  /* PB1550 */
+#define BCSR_STATUS_PB1550_U3RXD        0x8000  /* PB1550 */
+
+#define BCSR_STATUS_CFWP                0x4000  /* DB1300 */
+#define BCSR_STATUS_USBOCn              0x2000  /* DB1300 */
+#define BCSR_STATUS_OTGOCn              0x1000  /* DB1300 */
+#define BCSR_STATUS_DCDMARQ             0x0010  /* DB1300 */
+#define BCSR_STATUS_IDEDMARQ            0x0020  /* DB1300 */
+
+/* DB/PB1000,1100,1500,1550 */
+#define BCSR_RESETS_PHY0                0x0001
+#define BCSR_RESETS_PHY1                0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_FIR_SEL             0x2000
+#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
+#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
+#define BCSR_RESETS_PB1550_WSCFSM       0x2000
+#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
+#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
+#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
+#define BCSR_RESETS_DMAREQ              0x8000  /* PB1550 */
+
+#define BCSR_BOARD_PCIM66EN             0x0001
+#define BCSR_BOARD_SD0PWR               0x0040
+#define BCSR_BOARD_SD1PWR               0x0080
+#define BCSR_BOARD_PCIM33               0x0100
+#define BCSR_BOARD_PCIEXTARB            0x0200
+#define BCSR_BOARD_GPIO200RST           0x0400
+#define BCSR_BOARD_PCICLKOUT            0x0800
+#define BCSR_BOARD_PB1100_SD0PWR        0x0400
+#define BCSR_BOARD_PB1100_SD1PWR        0x0800
+#define BCSR_BOARD_PCICFG               0x1000
+#define BCSR_BOARD_SPISEL               0x2000  /* PB/DB1550 */
+#define BCSR_BOARD_SD0WP                0x4000  /* DB1100 */
+#define BCSR_BOARD_SD1WP                0x8000  /* DB1100 */
+
+
+/* DB/PB1200/1300 */
+#define BCSR_RESETS_ETH                 0x0001
+#define BCSR_RESETS_CAMERA              0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_IDE                 0x0008
+#define BCSR_RESETS_TV                  0x0010  /* DB1200/1300 */
+/* Not resets but in the same register */
+#define BCSR_RESETS_PWMR1MUX            0x0800  /* DB1200 */
+#define BCSR_RESETS_PB1200_WSCFSM       0x0800  /* PB1200 */
+#define BCSR_RESETS_PSC0MUX             0x1000
+#define BCSR_RESETS_PSC1MUX             0x2000
+#define BCSR_RESETS_SPISEL              0x4000
+#define BCSR_RESETS_SD1MUX              0x8000  /* PB1200 */
+
+#define BCSR_RESETS_VDDQSHDN            0x0200  /* DB1300 */
+#define BCSR_RESETS_OTPPGM              0x0400  /* DB1300 */
+#define BCSR_RESETS_OTPSCLK             0x0800  /* DB1300 */
+#define BCSR_RESETS_OTPWRPROT           0x1000  /* DB1300 */
+#define BCSR_RESETS_OTPCSB              0x2000  /* DB1300 */
+#define BCSR_RESETS_OTGPWR              0x4000  /* DB1300 */
+#define BCSR_RESETS_USBHPWR             0x8000  /* DB1300 */
+
+#define BCSR_BOARD_LCDVEE               0x0001
+#define BCSR_BOARD_LCDVDD               0x0002
+#define BCSR_BOARD_LCDBL                0x0004
+#define BCSR_BOARD_CAMSNAP              0x0010
+#define BCSR_BOARD_CAMPWR               0x0020
+#define BCSR_BOARD_SD0PWR               0x0040
+#define BCSR_BOARD_CAMCS                0x0010  /* DB1300 */
+#define BCSR_BOARD_HDMI_DE              0x0040  /* DB1300 */
+
+#define BCSR_SWITCHES_DIP               0x00FF
+#define BCSR_SWITCHES_DIP_1             0x0080
+#define BCSR_SWITCHES_DIP_2             0x0040
+#define BCSR_SWITCHES_DIP_3             0x0020
+#define BCSR_SWITCHES_DIP_4             0x0010
+#define BCSR_SWITCHES_DIP_5             0x0008
+#define BCSR_SWITCHES_DIP_6             0x0004
+#define BCSR_SWITCHES_DIP_7             0x0002
+#define BCSR_SWITCHES_DIP_8             0x0001
+#define BCSR_SWITCHES_ROTARY            0x0F00
+
+
+#define BCSR_PCMCIA_PC0VPP              0x0003
+#define BCSR_PCMCIA_PC0VCC              0x000C
+#define BCSR_PCMCIA_PC0DRVEN            0x0010
+#define BCSR_PCMCIA_PC0RST              0x0080
+#define BCSR_PCMCIA_PC1VPP              0x0300
+#define BCSR_PCMCIA_PC1VCC              0x0C00
+#define BCSR_PCMCIA_PC1DRVEN            0x1000
+#define BCSR_PCMCIA_PC1RST              0x8000
+
+
+#define BCSR_LEDS_DECIMALS              0x0003
+#define BCSR_LEDS_LED0                  0x0100
+#define BCSR_LEDS_LED1                  0x0200
+#define BCSR_LEDS_LED2                  0x0400
+#define BCSR_LEDS_LED3                  0x0800
+
+
+#define BCSR_SYSTEM_RESET               0x8000  /* clear to reset */
+#define BCSR_SYSTEM_PWROFF              0x4000  /* set to power off */
+#define BCSR_SYSTEM_VDDI                0x001F  /* PB1xxx boards */
+#define BCSR_SYSTEM_DEBUGCSMASK         0x003F  /* DB1300 */
+#define BCSR_SYSTEM_UDMAMODE            0x0100  /* DB1300 */
+#define BCSR_SYSTEM_WAKEONIRQ           0x0200  /* DB1300 */
+#define BCSR_SYSTEM_VDDI1300            0x3C00  /* DB1300 */
+
+
+
+/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
+ * BCSR spaces.
+ */
+void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
+
+/* read a board register */
+unsigned short bcsr_read(enum bcsr_id reg);
+
+/* write to a board register */
+void bcsr_write(enum bcsr_id reg, unsigned short val);
+
+/* modify a register. clear bits set in 'clr', set bits set in 'set' */
+void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
+
+/* install CPLD IRQ demuxer (DB1200/PB1200) */
+void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq);
+
+#endif
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000..15b266932
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+
+#ifdef NR_IRQS
+#undef NR_IRQS
+#endif
+
+#ifndef MIPS_CPU_IRQ_BASE
+#define MIPS_CPU_IRQ_BASE 0
+#endif
+
+/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
+#define NR_IRQS 152
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
new file mode 100644
index 000000000..1896e88f6
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      CPU feature overrides for DECstation systems.  Two variations
+ *      are generally applicable.
+ *
+ *      Copyright (C) 2013  Maciej W. Rozycki
+ */
+#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
+
+/* Generic ones first.  */
+#define cpu_has_tlb                     1
+#define cpu_has_tlbinv                  0
+#define cpu_has_segments                0
+#define cpu_has_eva                     0
+#define cpu_has_htw                     0
+#define cpu_has_rixiex                  0
+#define cpu_has_maar                    0
+#define cpu_has_rw_llb                  0
+#define cpu_has_tx39_cache              0
+#define cpu_has_divec                   0
+#define cpu_has_prefetch                0
+#define cpu_has_mcheck                  0
+#define cpu_has_ejtag                   0
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+#define cpu_has_rixi                    0
+#define cpu_has_xpa                     0
+#define cpu_has_vtag_icache             0
+#define cpu_has_ic_fills_f_dc           0
+#define cpu_has_pindexed_dcache         0
+#define cpu_icache_snoops_remote_store  1
+#define cpu_has_mips_4                  0
+#define cpu_has_mips_5                  0
+#define cpu_has_mips32r1                0
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_mipsmt                  0
+#define cpu_has_userlocal               0
+#define cpu_has_perf_cntr_intr_bit      0
+#define cpu_has_vz                      0
+#define cpu_has_fre                     0
+#define cpu_has_cdmm                    0
+
+/* R3k-specific ones.  */
+#ifdef CONFIG_CPU_R3000
+#define cpu_has_3kex                    1
+#define cpu_has_4kex                    0
+#define cpu_has_3k_cache                1
+#define cpu_has_4k_cache                0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 0
+#define cpu_has_watch                   0
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_llsc                    0
+#define cpu_has_dc_aliases              0
+#define cpu_has_mips_2                  0
+#define cpu_has_mips_3                  0
+#define cpu_has_nofpuex                 1
+#define cpu_has_inclusive_pcaches       0
+#define cpu_dcache_line_size()          4
+#define cpu_icache_line_size()          4
+#define cpu_scache_line_size()          0
+#endif /* CONFIG_CPU_R3000 */
+
+/* R4k-specific ones.  */
+#ifdef CONFIG_CPU_R4X00
+#define cpu_has_3kex                    0
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_32fpr                   1
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_vce                     1
+#define cpu_has_cache_cdex_p            1
+#define cpu_has_cache_cdex_s            1
+#define cpu_has_llsc                    1
+#define cpu_has_dc_aliases              (PAGE_SIZE < 0x4000)
+#define cpu_has_mips_2                  1
+#define cpu_has_mips_3                  1
+#define cpu_has_nofpuex                 0
+#define cpu_has_inclusive_pcaches       1
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+#define cpu_scache_line_size()          32
+#endif /* CONFIG_CPU_R4X00 */
+
+#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-dec/mc146818rtc.h b/arch/mips/include/asm/mach-dec/mc146818rtc.h
new file mode 100644
index 000000000..d4614e2a8
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/mc146818rtc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * RTC definitions for DECstation style attached Dallas DS1287 chip.
+ *
+ * Copyright (C) 1998, 2001 by Ralf Baechle
+ * Copyright (C) 1998 by Harald Koerfgen
+ * Copyright (C) 2002, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_RTC_DEC_H
+#define __ASM_MIPS_DEC_RTC_DEC_H
+
+#include <linux/types.h>
+#include <asm/addrspace.h>
+#include <asm/dec/system.h>
+
+extern volatile u8 *dec_rtc_base;
+
+#define ARCH_RTC_LOCATION
+
+#define RTC_PORT(x)     CPHYSADDR((long)dec_rtc_base)
+#define RTC_IO_EXTENT   dec_kn_slot_size
+#define RTC_IOMAPPED    0
+#undef RTC_IRQ
+
+#define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        return dec_rtc_base[addr * 4];
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        dec_rtc_base[addr * 4] = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MIPS_DEC_RTC_DEC_H */
diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 000000000..42be9e9ce
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ...  */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
new file mode 100644
index 000000000..e0c9cd41f
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -0,0 +1,133 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_FLOPPY_H
+#define __ASM_MACH_GENERIC_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+
+#include <asm/bootinfo.h>
+#include <asm/cachectl.h>
+#include <asm/dma.h>
+#include <asm/floppy.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+/*
+ * How to access the FDC's registers.
+ */
+static inline unsigned char fd_inb(unsigned int base, unsigned int reg)
+{
+        return inb_p(base + reg);
+}
+
+static inline void fd_outb(unsigned char value, unsigned int base, unsigned int reg)
+{
+        outb_p(value, base + reg);
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        enable_dma(FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        disable_dma(FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return request_dma(FLOPPY_DMA, "floppy");
+}
+
+static inline void fd_free_dma(void)
+{
+        free_dma(FLOPPY_DMA);
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+        clear_dma_ff(FLOPPY_DMA);
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        set_dma_mode(FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *addr)
+{
+        set_dma_addr(FLOPPY_DMA, (unsigned long) addr);
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        set_dma_count(FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return get_dma_residue(FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+        enable_irq(FLOPPY_IRQ);
+}
+
+static inline void fd_disable_irq(void)
+{
+        disable_irq(FLOPPY_IRQ);
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           0, "floppy", NULL);
+}
+
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return 0x3f0;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        return __get_dma_pages(GFP_KERNEL, get_order(size));
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_FLOPPY_H */
diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
new file mode 100644
index 000000000..4ae5fbcb1
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -0,0 +1,138 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994-1996  Linus Torvalds & authors
+ *
+ * Copied from i386; many of the especially older MIPS or ISA-based platforms
+ * are basically identical.  Using this file probably implies i8259 PIC
+ * support in a system but the very least interrupt numbers 0 - 15 need to
+ * be put aside for legacy devices.
+ */
+#ifndef __ASM_MACH_GENERIC_IDE_H
+#define __ASM_MACH_GENERIC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <linux/pci.h>
+#include <linux/stddef.h>
+#include <asm/processor.h>
+
+/* MIPS port and memory-mapped I/O string operations.  */
+static inline void __ide_flush_prologue(void)
+{
+#ifdef CONFIG_SMP
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+                preempt_disable();
+#endif
+}
+
+static inline void __ide_flush_epilogue(void)
+{
+#ifdef CONFIG_SMP
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+                preempt_enable();
+#endif
+}
+
+static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
+{
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
+                unsigned long end = addr + size;
+
+                while (addr < end) {
+                        local_flush_data_cache_page((void *)addr);
+                        addr += PAGE_SIZE;
+                }
+        }
+}
+
+/*
+ * insw() and gang might be called with interrupts disabled, so we can't
+ * send IPIs for flushing due to the potencial of deadlocks, see the comment
+ * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
+ * problem by disabling preemption so we know we actually perform the flush
+ * on the processor that actually has the lines to be flushed which hopefully
+ * is even better for performance anyway.
+ */
+static inline void __ide_insw(unsigned long port, void *addr,
+        unsigned int count)
+{
+        __ide_flush_prologue();
+        insw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+        __ide_flush_prologue();
+        insl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_outsw(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        __ide_flush_prologue();
+        outsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_outsl(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        __ide_flush_prologue();
+        outsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        readsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        readsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        writesw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        writesl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+/* ide_insw calls insw, not __ide_insw.  Why? */
+#undef insw
+#undef insl
+#undef outsw
+#undef outsl
+#define insw(port, addr, count) __ide_insw(port, addr, count)
+#define insl(port, addr, count) __ide_insl(port, addr, count)
+#define outsw(port, addr, count) __ide_outsw(port, addr, count)
+#define outsl(port, addr, count) __ide_outsl(port, addr, count)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_MACH_GENERIC_IDE_H */
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
new file mode 100644
index 000000000..f2442b845
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/mach-generic/ioremap.h
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
new file mode 100644
index 000000000..079889ced
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+#ifndef NR_IRQS
+#define NR_IRQS 256
+#endif
+
+#ifdef CONFIG_I8259
+#ifndef I8259A_IRQ_BASE
+#define I8259A_IRQ_BASE 0
+#endif
+#endif
+
+#ifdef CONFIG_IRQ_MIPS_CPU
+
+#ifndef MIPS_CPU_IRQ_BASE
+#ifdef CONFIG_I8259
+#define MIPS_CPU_IRQ_BASE 16
+#else
+#define MIPS_CPU_IRQ_BASE 0
+#endif /* CONFIG_I8259 */
+#endif
+
+#ifdef CONFIG_IRQ_CPU_RM7K
+#ifndef RM7K_CPU_IRQ_BASE
+#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
+#endif
+#endif
+
+#endif /* CONFIG_IRQ_MIPS_CPU */
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
new file mode 100644
index 000000000..a229297c8
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-generic/kmalloc.h b/arch/mips/include/asm/mach-generic/kmalloc.h
new file mode 100644
index 000000000..649a98338
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/kmalloc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_GENERIC_KMALLOC_H
+#define __ASM_MACH_GENERIC_KMALLOC_H
+
+#ifdef CONFIG_DMA_NONCOHERENT
+/*
+ * Total overkill for most systems but need as a safe default.
+ * Set this one if any device in the system might do non-coherent DMA.
+ */
+#define ARCH_DMA_MINALIGN       128
+#endif
+
+#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
new file mode 100644
index 000000000..77c65c294
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          le16_to_cpu((__force __le16)(x))
+# define __mem_ioswabw(a, x)    (x)
+# define ioswabl(a, x)          le32_to_cpu((__force __le32)(x))
+# define __mem_ioswabl(a, x)    (x)
+# define ioswabq(a, x)          le64_to_cpu((__force __le64)(x))
+# define __mem_ioswabq(a, x)    (x)
+
+#else
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    ((__force u16)cpu_to_le16(x))
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    ((__force u32)cpu_to_le32(x))
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    ((__force u64)cpu_to_le64(x))
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-generic/mc146818rtc.h b/arch/mips/include/asm/mach-generic/mc146818rtc.h
new file mode 100644
index 000000000..9c72e540f
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_GENERIC_MC146818RTC_H
+#define __ASM_MACH_GENERIC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
new file mode 100644
index 000000000..c3ac06a6a
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <linux/const.h>
+
+#include <asm/mipsregs.h>
+
+#ifndef IO_SPACE_LIMIT
+#define IO_SPACE_LIMIT 0xffff
+#endif
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef __ASSEMBLY__
+# if defined(CONFIG_MIPS_AUTO_PFN_OFFSET)
+#  define PHYS_OFFSET           ((unsigned long)PFN_PHYS(ARCH_PFN_OFFSET))
+# elif !defined(PHYS_OFFSET)
+#  define PHYS_OFFSET           _AC(0, UL)
+# endif
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+#define CAC_BASE                _AC(0x40000000, UL)
+#else
+#define CAC_BASE                _AC(0x80000000, UL)
+#endif
+#ifndef IO_BASE
+#define IO_BASE                 _AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE              _AC(0xa0000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#ifdef CONFIG_KVM_GUEST
+#define MAP_BASE                _AC(0x60000000, UL)
+#else
+#define MAP_BASE                _AC(0xc0000000, UL)
+#endif
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           _AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#define CAC_BASE        PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0)
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE                 _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE              _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE                _AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           (_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET             (CAC_BASE + PHYS_OFFSET)
+#endif
+
+#ifndef FIXADDR_TOP
+#ifdef CONFIG_KVM_GUEST
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0x7ffe0000)
+#else
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0xfffe0000)
+#endif
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/mach-generic/topology.h b/arch/mips/include/asm/mach-generic/topology.h
new file mode 100644
index 000000000..5428f333a
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/topology.h
@@ -0,0 +1 @@
+#include <asm-generic/topology.h>
diff --git a/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h
new file mode 100644
index 000000000..7c5e576f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_counter         0
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc            1
+#define cpu_has_mips16 0
+#define cpu_has_mips16e2        0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define kernel_uses_llsc        1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
new file mode 100644
index 000000000..b80d5eafc
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 07 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+
+#include <asm/cpu.h>
+
+/*
+ * IP22 with a variety of processors so we can't use defaults for everything.
+ */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0               /* Needs to change for R8000 */
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips_2          1
+#define cpu_has_mips_3          1
+#define cpu_has_mips_5          0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip22/spaces.h b/arch/mips/include/asm/mach-ip22/spaces.h
new file mode 100644
index 000000000..24fe92cb5
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/spaces.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP22_SPACES_H
+#define _ASM_MACH_IP22_SPACES_H
+
+#define PHYS_OFFSET     _AC(0x08000000, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
new file mode 100644
index 000000000..79d6fd249
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 07 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+
+#include <asm/cpu.h>
+
+/*
+ * IP27 only comes with R1x000 family processors, all using the same config
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_tlbinv                  0
+#define cpu_has_segments                0
+#define cpu_has_eva                     0
+#define cpu_has_htw                     0
+#define cpu_has_rixiex                  0
+#define cpu_has_maar                    0
+#define cpu_has_rw_llb                  0
+#define cpu_has_3kex                    0
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_nofpuex                 0
+#define cpu_has_32fpr                   1
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_64bits                  1
+#define cpu_has_divec                   0
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  0
+#define cpu_has_ejtag                   0
+#define cpu_has_llsc                    1
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+#define cpu_has_rixi                    0
+#define cpu_has_xpa                     0
+#define cpu_has_vtag_icache             0
+#define cpu_has_dc_aliases              0
+#define cpu_has_ic_fills_f_dc           0
+
+#define cpu_icache_snoops_remote_store  1
+
+#define cpu_has_mips32r1                0
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+#define cpu_has_mips32r6                0
+#define cpu_has_mips64r6                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_mipsmt                  0
+#define cpu_has_userlocal               0
+#define cpu_has_inclusive_pcaches       1
+#define cpu_has_perf_cntr_intr_bit      0
+#define cpu_has_vz                      0
+#define cpu_has_fre                     0
+#define cpu_has_cdmm                    0
+
+#define cpu_dcache_line_size()          32
+#define cpu_icache_line_size()          64
+#define cpu_scache_line_size()          128
+
+#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h
new file mode 100644
index 000000000..f45d7999f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/irq.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Kanoj Sarcar
+ */
+#ifndef __ASM_MACH_IP27_IRQ_H
+#define __ASM_MACH_IP27_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#define IP27_HUB_PEND0_IRQ      (MIPS_CPU_IRQ_BASE + 2)
+#define IP27_HUB_PEND1_IRQ      (MIPS_CPU_IRQ_BASE + 3)
+#define IP27_RT_TIMER_IRQ       (MIPS_CPU_IRQ_BASE + 4)
+
+#define IP27_HUB_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
+#define IP27_HUB_IRQ_COUNT      128
+
+#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000..3e54f605a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,96 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
+#define __ASM_MACH_IP27_KERNEL_ENTRY_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/agent.h>
+#include <asm/sn/klkernvars.h>
+
+/*
+ * TLB bits
+ */
+#define PAGE_GLOBAL             (1 << 6)
+#define PAGE_VALID              (1 << 7)
+#define PAGE_DIRTY              (1 << 8)
+#define CACHE_CACHABLE_COW      (5 << 9)
+
+        /*
+         * inputs are the text nasid in t1, data nasid in t2.
+         */
+        .macro MAPPED_KERNEL_SETUP_TLB
+#ifdef CONFIG_MAPPED_KERNEL
+        /*
+         * This needs to read the nasid - assume 0 for now.
+         * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
+         * 0+DVG in tlblo_1.
+         */
+        dli     t0, 0xffffffffc0000000
+        dmtc0   t0, CP0_ENTRYHI
+        li      t0, 0x1c000             # Offset of text into node memory
+        dsll    t1, NASID_SHFT          # Shift text nasid into place
+        dsll    t2, NASID_SHFT          # Same for data nasid
+        or      t1, t1, t0              # Physical load address of kernel text
+        or      t2, t2, t0              # Physical load address of kernel data
+        dsrl    t1, 12                  # 4K pfn
+        dsrl    t2, 12                  # 4K pfn
+        dsll    t1, 6                   # Get pfn into place
+        dsll    t2, 6                   # Get pfn into place
+        li      t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
+        or      t0, t0, t1
+        mtc0    t0, CP0_ENTRYLO0        # physaddr, VG, cach exlwr
+        li      t0, ((PAGE_GLOBAL | PAGE_VALID |  PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
+        or      t0, t0, t2
+        mtc0    t0, CP0_ENTRYLO1        # physaddr, DVG, cach exlwr
+        li      t0, 0x1ffe000           # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
+        mtc0    t0, CP0_PAGEMASK
+        li      t0, 0                   # KMAP_INX
+        mtc0    t0, CP0_INDEX
+        li      t0, 1
+        mtc0    t0, CP0_WIRED
+        tlbwi
+#else
+        mtc0    zero, CP0_WIRED
+#endif
+        .endm
+
+/*
+ * Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        GET_NASID_ASM   t1
+        move            t2, t1                  # text and data are here
+        MAPPED_KERNEL_SETUP_TLB
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        GET_NASID_ASM   t1
+        dli     t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+                    KLDIR_OFF_POINTER + CAC_BASE
+        dsll    t1, NASID_SHFT
+        or      t0, t0, t1
+        ld      t0, 0(t0)                       # t0 points to kern_vars struct
+        lh      t1, KV_RO_NASID_OFFSET(t0)
+        lh      t2, KV_RW_NASID_OFFSET(t0)
+        MAPPED_KERNEL_SETUP_TLB
+
+        /*
+         * We might not get launched at the address the kernel is linked to,
+         * so we jump there.
+         */
+        PTR_LA  t0, 0f
+        jr      t0
+0:
+        .endm
+
+#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ip27/mangle-port.h b/arch/mips/include/asm/mach-ip27/mangle-port.h
new file mode 100644
index 000000000..f71c38bbf
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mangle-port.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
+#define __ASM_MACH_IP27_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  ((port) ^ 3)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    ((__force u16)cpu_to_le16(x))
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    ((__force u32)cpu_to_le32(x))
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    ((__force u64)cpu_to_le64(x))
+
+#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
new file mode 100644
index 000000000..08c36e50a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MACH_MMZONE_H
+#define _ASM_MACH_MMZONE_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/agent.h>
+#include <asm/sn/klkernvars.h>
+
+#define pa_to_nid(addr)         NASID_GET(addr)
+
+struct hub_data {
+        kern_vars_t     kern_vars;
+        DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
+        cpumask_t       h_cpus;
+};
+
+struct node_data {
+        struct pglist_data pglist;
+        struct hub_data hub;
+};
+
+extern struct node_data *__node_data[];
+
+#define NODE_DATA(n)            (&__node_data[(n)]->pglist)
+#define hub_data(n)             (&__node_data[(n)]->hub)
+
+#endif /* _ASM_MACH_MMZONE_H */
diff --git a/arch/mips/include/asm/mach-ip27/spaces.h b/arch/mips/include/asm/mach-ip27/spaces.h
new file mode 100644
index 000000000..66421e9a6
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/spaces.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP27_SPACES_H
+#define _ASM_MACH_IP27_SPACES_H
+
+#include <linux/const.h>
+
+/*
+ * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
+ * uncached memory addressing. Hide the definitions on 32-bit compilation
+ * of the compat-vdso code.
+ */
+#ifdef CONFIG_64BIT
+#define HSPEC_BASE              _AC(0x9000000000000000, UL)
+#define IO_BASE                 _AC(0x9200000000000000, UL)
+#define MSPEC_BASE              _AC(0x9400000000000000, UL)
+#define UNCAC_BASE              _AC(0x9600000000000000, UL)
+#define CAC_BASE                _AC(0xa800000000000000, UL)
+#endif
+
+#define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
+
+#define HIGHMEM_START           (~0UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
new file mode 100644
index 000000000..d66cc53fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MACH_TOPOLOGY_H
+#define _ASM_MACH_TOPOLOGY_H    1
+
+#include <asm/sn/types.h>
+#include <asm/mmzone.h>
+
+struct cpuinfo_ip27 {
+        nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
+        unsigned short  p_speed;        /* cpu speed in MHz */
+        unsigned char   p_slice;        /* Physical position on node board */
+};
+
+extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
+
+#define cpu_to_node(cpu)        (cputonasid(cpu))
+#define cpumask_of_node(node)   ((node) == -1 ?                         \
+                                 cpu_all_mask :                         \
+                                 &hub_data(node)->h_cpus)
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *);
+
+#define cpumask_of_pcibus(bus)  (cpumask_of_node(pcibus_to_node(bus)))
+
+extern unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
+
+#define node_distance(from, to) (__node_distances[(from)][(to)])
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
new file mode 100644
index 000000000..613bbc10c
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -0,0 +1,54 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ * 6/2004       pf
+ */
+#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
+
+#include <asm/cpu.h>
+
+/*
+ * IP28 only comes with R10000 family processors all using the same config
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            0
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0 /* see probe_pcache() */
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_icache_snoops_remote_store  1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+
+#define cpu_has_inclusive_pcaches       1
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  64
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
new file mode 100644
index 000000000..c4a912733
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ * 2004 pf
+ */
+#ifndef _ASM_MACH_IP28_SPACES_H
+#define _ASM_MACH_IP28_SPACES_H
+
+#define PHYS_OFFSET     _AC(0x20000000, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
new file mode 100644
index 000000000..2635b6ba1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * IP30/Octane cpu-features overrides.
+ *
+ * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
+ *               2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
+ *               2009 Johannes Dickgreber <tanzy@gmx.de>
+ *               2015 Joshua Kinard <kumba@gentoo.org>
+ *
+ */
+#ifndef __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H
+
+#include <asm/cpu.h>
+
+/*
+ * IP30 only supports R1[024]000 processors, all using the same config
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_tlbinv                  0
+#define cpu_has_segments                0
+#define cpu_has_eva                     0
+#define cpu_has_htw                     0
+#define cpu_has_rixiex                  0
+#define cpu_has_maar                    0
+#define cpu_has_rw_llb                  0
+#define cpu_has_3kex                    0
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_nofpuex                 0
+#define cpu_has_32fpr                   1
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_64bits                  1
+#define cpu_has_divec                   0
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  0
+#define cpu_has_ejtag                   0
+#define cpu_has_llsc                    1
+#define cpu_has_mips16                  0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+#define cpu_has_rixi                    0
+#define cpu_has_xpa                     0
+#define cpu_has_vtag_icache             0
+#define cpu_has_dc_aliases              0
+#define cpu_has_ic_fills_f_dc           0
+
+#define cpu_icache_snoops_remote_store  1
+
+#define cpu_has_mips32r1                0
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+#define cpu_has_mips32r6                0
+#define cpu_has_mips64r6                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_mipsmt                  0
+#define cpu_has_userlocal               0
+#define cpu_has_inclusive_pcaches       1
+#define cpu_has_perf_cntr_intr_bit      0
+#define cpu_has_vz                      0
+#define cpu_has_fre                     0
+#define cpu_has_cdmm                    0
+
+#define cpu_dcache_line_size()          32
+#define cpu_icache_line_size()          64
+#define cpu_scache_line_size()          128
+
+#endif /* __ASM_MACH_IP30_CPU_FEATURE_OVERRIDES_H */
+
diff --git a/arch/mips/include/asm/mach-ip30/kernel-entry-init.h b/arch/mips/include/asm/mach-ip30/kernel-entry-init.h
new file mode 100644
index 000000000..be0472c97
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip30/kernel-entry-init.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_MACH_IP30_KERNEL_ENTRY_H
+#define __ASM_MACH_IP30_KERNEL_ENTRY_H
+
+        .macro  kernel_entry_setup
+        .endm
+
+        .macro  smp_slave_setup
+        move    gp, a0
+        .endm
+
+#endif /* __ASM_MACH_IP30_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ip30/mangle-port.h b/arch/mips/include/asm/mach-ip30/mangle-port.h
new file mode 100644
index 000000000..439c6a601
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip30/mangle-port.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP30_MANGLE_PORT_H
+#define __ASM_MACH_IP30_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  ((port)^3)
+#define __swizzle_addr_w(port)  ((port)^2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#define ioswabb(a, x)           (x)
+#define __mem_ioswabb(a, x)     (x)
+#define ioswabw(a, x)           (x)
+#define __mem_ioswabw(a, x)     ((__force u16)cpu_to_le16(x))
+#define ioswabl(a, x)           (x)
+#define __mem_ioswabl(a, x)     ((__force u32)cpu_to_le32(x))
+#define ioswabq(a, x)           (x)
+#define __mem_ioswabq(a, x)     ((__force u64)cpu_to_le64(x))
+
+#endif /* __ASM_MACH_IP30_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip30/spaces.h b/arch/mips/include/asm/mach-ip30/spaces.h
new file mode 100644
index 000000000..c8a302dfb
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip30/spaces.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Joshua Kinard <kumba@gentoo.org>
+ *
+ */
+#ifndef _ASM_MACH_IP30_SPACES_H
+#define _ASM_MACH_IP30_SPACES_H
+
+/*
+ * Memory in IP30/Octane is offset 512MB in the physical address space.
+ */
+#define PHYS_OFFSET     _AC(0x20000000, UL)
+
+#ifdef CONFIG_64BIT
+#define CAC_BASE        _AC(0xA800000000000000, UL)
+#endif
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_IP30_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
new file mode 100644
index 000000000..63b4c8890
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
+ * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * R5000 has an interesting "restriction":  ll(d)/sc(d)
+ * instructions to XKPHYS region simply do uncached bus
+ * requests. This breaks all the atomic bitops functions.
+ * so, for 64bit IP32 kernel we just don't use ll/sc.
+ * This does not affect luserland.
+ */
+#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+/* Settings which are common for all ip32 CPUs */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_4k_cache        1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip32/kmalloc.h b/arch/mips/include/asm/mach-ip32/kmalloc.h
new file mode 100644
index 000000000..07a0146ea
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/kmalloc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_IP32_KMALLOC_H
+#define __ASM_MACH_IP32_KMALLOC_H
+
+
+#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
+#define ARCH_DMA_MINALIGN       32
+#else
+#define ARCH_DMA_MINALIGN       128
+#endif
+
+#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-ip32/mangle-port.h b/arch/mips/include/asm/mach-ip32/mangle-port.h
new file mode 100644
index 000000000..4bc3d20e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/mangle-port.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ladislav Michl
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
+#define __ASM_MACH_IP32_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  ((port) ^ 3)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    ((__force u16)cpu_to_le16(x))
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    ((__force u32)cpu_to_le32(x))
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    ((__force u64)cpu_to_le64(x))
+
+#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
new file mode 100644
index 000000000..294ebb834
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -0,0 +1,133 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JAZZ_FLOPPY_H
+#define __ASM_MACH_JAZZ_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <asm/addrspace.h>
+#include <asm/jazz.h>
+#include <asm/jazzdma.h>
+
+static inline unsigned char fd_inb(unsigned int base, unsigned int reg)
+{
+        unsigned char c;
+
+        c = *(volatile unsigned char *) (base + reg);
+        udelay(1);
+
+        return c;
+}
+
+static inline void fd_outb(unsigned char value, unsigned int base, unsigned int reg)
+{
+        *(volatile unsigned char *) (base + reg) = value;
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        vdma_enable(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        vdma_disable(JAZZ_FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return 0;
+}
+
+static inline void fd_free_dma(void)
+{
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        vdma_set_mode(JAZZ_FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *a)
+{
+        vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a)));
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        vdma_set_count(JAZZ_FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return vdma_get_residue(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+}
+
+static inline void fd_disable_irq(void)
+{
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           0, "floppy", NULL);
+}
+
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return JAZZ_FDC_BASE;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        unsigned long mem;
+
+        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
+        if(!mem)
+                return 0;
+        vdma_alloc(CPHYSADDR(mem), size);       /* XXX error checking */
+
+        return mem;
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        vdma_free(vdma_phys2log(CPHYSADDR(addr)));
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        /* XXX This is wrong for machines with ED 2.88mb disk drives like the
+           Olivetti M700.  Anyway, we should suck this from the ARC
+           firmware.  */
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_JAZZ_FLOPPY_H */
diff --git a/arch/mips/include/asm/mach-jazz/mc146818rtc.h b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
new file mode 100644
index 000000000..987f727af
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ * Copyright (C) 2007 Thomas Bogendoerfer
+ *
+ * RTC routines for Jazz style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_JAZZ_MC146818RTC_H
+#define __ASM_MACH_JAZZ_MC146818RTC_H
+
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/jazz.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return *(volatile char *)JAZZ_RTC_BASE;
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        *(volatile char *)JAZZ_RTC_BASE = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) + 1980)
+
+#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
new file mode 100644
index 000000000..10226976f
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Lantiq FALCON specific CPU feature overrides
+ *
+ *  Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             1
+#define cpu_has_mipsmt          1
+
+#define cpu_has_vint            1
+#define cpu_has_veic            1
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
new file mode 100644
index 000000000..6eeda90f7
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ */
+
+#ifndef _FALCON_IRQ__
+#define _FALCON_IRQ__
+
+#define INT_NUM_IRQ0                    8
+#define INT_NUM_IM0_IRL0                (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0                (INT_NUM_IM0_IRL0 + 32)
+#define INT_NUM_IM2_IRL0                (INT_NUM_IM1_IRL0 + 32)
+#define INT_NUM_IM3_IRL0                (INT_NUM_IM2_IRL0 + 32)
+#define INT_NUM_IM4_IRL0                (INT_NUM_IM3_IRL0 + 32)
+#define INT_NUM_EXTRA_START             (INT_NUM_IM4_IRL0 + 32)
+#define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define MAX_IM                  5
+
+#endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
new file mode 100644
index 000000000..c14312fb0
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ */
+
+#ifndef __FALCON_IRQ_H
+#define __FALCON_IRQ_H
+
+#include <falcon_irq.h>
+
+#define NR_IRQS 328
+
+#include <asm/mach-generic/irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
new file mode 100644
index 000000000..5855ba1bd
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _LTQ_FALCON_H__
+#define _LTQ_FALCON_H__
+
+#ifdef CONFIG_SOC_FALCON
+
+#include <linux/pinctrl/pinctrl.h>
+#include <lantiq.h>
+
+/* Chip IDs */
+#define SOC_ID_FALCON           0x01B8
+
+/* SoC Types */
+#define SOC_TYPE_FALCON         0x01
+
+/*
+ * during early_printk no ioremap possible at this early stage
+ * let's use KSEG1 instead
+ */
+#define LTQ_ASC0_BASE_ADDR      0x1E100C00
+#define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
+
+/* WDT */
+#define LTQ_RST_CAUSE_WDTRST    0x0002
+
+/* CHIP ID */
+#define LTQ_STATUS_BASE_ADDR    0x1E802000
+
+#define FALCON_CHIPID           ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
+#define FALCON_CHIPTYPE         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
+#define FALCON_CHIPCONF         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
+
+/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
+#define SYSCTL_SYS1             0
+#define SYSCTL_SYSETH           1
+#define SYSCTL_SYSGPE           2
+
+/* BOOT_SEL - find what boot media we have */
+#define BS_FLASH                0x1
+#define BS_SPI                  0x4
+
+/* global register ranges */
+extern __iomem void *ltq_ebu_membase;
+extern __iomem void *ltq_sys1_membase;
+#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
+#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
+
+#define ltq_sys1_w32(x, y)      ltq_w32((x), ltq_sys1_membase + (y))
+#define ltq_sys1_r32(x)         ltq_r32(ltq_sys1_membase + (x))
+#define ltq_sys1_w32_mask(clear, set, reg)   \
+        ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
+
+/* allow the gpio and pinctrl drivers to talk to eachother */
+extern int pinctrl_falcon_get_range_size(int id);
+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
+
+/*
+ * to keep the irq code generic we need to define this to 0 as falcon
+ * has no EIU/EBU
+ */
+#define LTQ_EBU_PCC_ISTAT       0
+
+#endif /* CONFIG_SOC_FALCON */
+#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
new file mode 100644
index 000000000..6ceb0287d
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+#ifndef _LANTIQ_H__
+#define _LANTIQ_H__
+
+#include <linux/irq.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+
+/* generic reg access functions */
+#define ltq_r32(reg)            __raw_readl(reg)
+#define ltq_w32(val, reg)       __raw_writel(val, reg)
+#define ltq_w32_mask(clear, set, reg)   \
+        ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
+#define ltq_r8(reg)             __raw_readb(reg)
+#define ltq_w8(val, reg)        __raw_writeb(val, reg)
+
+/* register access macros for EBU and CGU */
+#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
+#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
+#define ltq_ebu_w32_mask(x, y, z) \
+        ltq_w32_mask(x, y, ltq_ebu_membase + (z))
+extern __iomem void *ltq_ebu_membase;
+
+/* spinlock all ebu i/o */
+extern spinlock_t ebu_lock;
+
+/* some irq helpers */
+extern void ltq_disable_irq(struct irq_data *data);
+extern void ltq_mask_and_ack_irq(struct irq_data *data);
+extern void ltq_enable_irq(struct irq_data *data);
+extern int ltq_eiu_get_irq(int exin);
+
+/* clock handling */
+extern int clk_activate(struct clk *clk);
+extern void clk_deactivate(struct clk *clk);
+extern struct clk *clk_get_cpu(void);
+extern struct clk *clk_get_fpi(void);
+extern struct clk *clk_get_io(void);
+extern struct clk *clk_get_ppe(void);
+
+/* find out what bootsource we have */
+extern unsigned char ltq_boot_select(void);
+/* find out the soc type */
+extern int ltq_soc_type(void);
+
+#define IOPORT_RESOURCE_START   0x10000000
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xffffffff
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
new file mode 100644
index 000000000..70ebb4d6f
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _LANTIQ_PLATFORM_H__
+#define _LANTIQ_PLATFORM_H__
+
+#include <linux/socket.h>
+
+/* struct used to pass info to network drivers */
+struct ltq_eth_data {
+        struct sockaddr mac;
+        int mii_mode;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
new file mode 100644
index 000000000..2980e7771
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+
+#ifndef __LANTIQ_IRQ_H
+#define __LANTIQ_IRQ_H
+
+#include <lantiq_irq.h>
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
new file mode 100644
index 000000000..5f0d0ba99
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _LANTIQ_XWAY_IRQ_H__
+#define _LANTIQ_XWAY_IRQ_H__
+
+#define INT_NUM_IRQ0            8
+#define INT_NUM_IM0_IRL0        (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0        (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0        (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0        (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0        (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET       (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define LTQ_DMA_CH0_INT         (INT_NUM_IM2_IRL0)
+
+#define MAX_IM                  5
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
new file mode 100644
index 000000000..4790cfa19
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _LTQ_XWAY_H__
+#define _LTQ_XWAY_H__
+
+#ifdef CONFIG_SOC_TYPE_XWAY
+
+#include <lantiq.h>
+
+/* Chip IDs */
+#define SOC_ID_DANUBE1          0x129
+#define SOC_ID_DANUBE2          0x12B
+#define SOC_ID_TWINPASS         0x12D
+#define SOC_ID_AMAZON_SE_1      0x152 /* 50601 */
+#define SOC_ID_AMAZON_SE_2      0x153 /* 50600 */
+#define SOC_ID_ARX188           0x16C
+#define SOC_ID_ARX168_1         0x16D
+#define SOC_ID_ARX168_2         0x16E
+#define SOC_ID_ARX182           0x16F
+#define SOC_ID_GRX188           0x170
+#define SOC_ID_GRX168           0x171
+
+#define SOC_ID_VRX288           0x1C0 /* v1.1 */
+#define SOC_ID_VRX282           0x1C1 /* v1.1 */
+#define SOC_ID_VRX268           0x1C2 /* v1.1 */
+#define SOC_ID_GRX268           0x1C8 /* v1.1 */
+#define SOC_ID_GRX288           0x1C9 /* v1.1 */
+#define SOC_ID_VRX288_2         0x00B /* v1.2 */
+#define SOC_ID_VRX268_2         0x00C /* v1.2 */
+#define SOC_ID_GRX288_2         0x00D /* v1.2 */
+#define SOC_ID_GRX282_2         0x00E /* v1.2 */
+#define SOC_ID_VRX220           0x000
+
+#define SOC_ID_ARX362           0x004
+#define SOC_ID_ARX368           0x005
+#define SOC_ID_ARX382           0x007
+#define SOC_ID_ARX388           0x008
+#define SOC_ID_URX388           0x009
+#define SOC_ID_GRX383           0x010
+#define SOC_ID_GRX369           0x011
+#define SOC_ID_GRX387           0x00F
+#define SOC_ID_GRX389           0x012
+
+ /* SoC Types */
+#define SOC_TYPE_DANUBE         0x01
+#define SOC_TYPE_TWINPASS       0x02
+#define SOC_TYPE_AR9            0x03
+#define SOC_TYPE_VR9            0x04 /* v1.1 */
+#define SOC_TYPE_VR9_2          0x05 /* v1.2 */
+#define SOC_TYPE_AMAZON_SE      0x06
+#define SOC_TYPE_AR10           0x07
+#define SOC_TYPE_GRX390         0x08
+#define SOC_TYPE_VRX220         0x09
+
+/* BOOT_SEL - find what boot media we have */
+#define BS_EXT_ROM              0x0
+#define BS_FLASH                0x1
+#define BS_MII0                 0x2
+#define BS_PCI                  0x3
+#define BS_UART1                0x4
+#define BS_SPI                  0x5
+#define BS_NAND                 0x6
+#define BS_RMII0                0x7
+
+/* helpers used to access the cgu */
+#define ltq_cgu_w32(x, y)       ltq_w32((x), ltq_cgu_membase + (y))
+#define ltq_cgu_r32(x)          ltq_r32(ltq_cgu_membase + (x))
+extern __iomem void *ltq_cgu_membase;
+
+/*
+ * during early_printk no ioremap is possible
+ * let's use KSEG1 instead
+ */
+#define LTQ_ASC1_BASE_ADDR      0x1E100C00
+#define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+
+/* EBU - external bus unit */
+#define LTQ_EBU_BUSCON0         0x0060
+#define LTQ_EBU_PCC_CON         0x0090
+#define LTQ_EBU_PCC_IEN         0x00A4
+#define LTQ_EBU_PCC_ISTAT       0x00A0
+#define LTQ_EBU_BUSCON1         0x0064
+#define LTQ_EBU_ADDRSEL1        0x0024
+#define EBU_WRDIS               0x80000000
+
+/* WDT */
+#define LTQ_RST_CAUSE_WDTRST    0x20
+
+/* MPS - multi processor unit (voice) */
+#define LTQ_MPS_BASE_ADDR       (KSEG1 + 0x1F107000)
+#define LTQ_MPS_CHIPID          ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
+
+/* allow booting xrx200 phys */
+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
+
+/* request a non-gpio and set the PIO config */
+#define PMU_PPE                  BIT(13)
+extern void ltq_pmu_enable(unsigned int module);
+extern void ltq_pmu_disable(unsigned int module);
+
+#endif /* CONFIG_SOC_TYPE_XWAY */
+#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
new file mode 100644
index 000000000..8218a1356
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ *   Copyright (C) 2011 John Crispin <john@phrozen.org>
+ */
+
+#ifndef LTQ_DMA_H__
+#define LTQ_DMA_H__
+
+#define LTQ_DESC_SIZE           0x08    /* each descriptor is 64bit */
+#define LTQ_DESC_NUM            0x40    /* 64 descriptors / channel */
+
+#define LTQ_DMA_OWN             BIT(31) /* owner bit */
+#define LTQ_DMA_C               BIT(30) /* complete bit */
+#define LTQ_DMA_SOP             BIT(29) /* start of packet */
+#define LTQ_DMA_EOP             BIT(28) /* end of packet */
+#define LTQ_DMA_TX_OFFSET(x)    ((x & 0x1f) << 23) /* data bytes offset */
+#define LTQ_DMA_RX_OFFSET(x)    ((x & 0x7) << 23) /* data bytes offset */
+#define LTQ_DMA_SIZE_MASK       (0xffff) /* the size field is 16 bit */
+
+struct ltq_dma_desc {
+        u32 ctl;
+        u32 addr;
+};
+
+struct ltq_dma_channel {
+        int nr;                         /* the channel number */
+        int irq;                        /* the mapped irq */
+        int desc;                       /* the current descriptor */
+        struct ltq_dma_desc *desc_base; /* the descriptor base */
+        int phys;                       /* physical addr */
+        struct device *dev;
+};
+
+enum {
+        DMA_PORT_ETOP = 0,
+        DMA_PORT_DEU,
+};
+
+extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_open(struct ltq_dma_channel *ch);
+extern void ltq_dma_close(struct ltq_dma_channel *ch);
+extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
+extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
+extern void ltq_dma_free(struct ltq_dma_channel *ch);
+extern void ltq_dma_init_port(int p);
+
+#endif
diff --git a/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
new file mode 100644
index 000000000..b2ee859ca
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
+ * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
+ * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
+ *
+ * reference: /proc/cpuinfo,
+ *      arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
+ *      arch/mips/kernel/proc.c(show_cpuinfo),
+ *      loongson2f user manual.
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_32fpr           1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_4kex            1
+#define cpu_has_64bits          1
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_counter         1
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_divec           0
+#define cpu_has_ejtag           0
+#define cpu_has_inclusive_pcaches       1
+#define cpu_has_llsc            1
+#define cpu_has_mcheck          0
+#define cpu_has_mdmx            0
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_mips3d          0
+#define cpu_has_mipsmt          0
+#define cpu_has_smartmips       0
+#define cpu_has_tlb             1
+#define cpu_has_tx39_cache      0
+#define cpu_has_vce             0
+#define cpu_has_veic            0
+#define cpu_has_vint            0
+#define cpu_has_vtag_icache     0
+#define cpu_has_watch           1
+
+#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
new file mode 100644
index 000000000..9795b3361
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
@@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * The header file of cs5536 south bridge.
+ *
+ * Copyright (C) 2007 Lemote, Inc.
+ * Author : jlliu <liujl@lemote.com>
+ */
+
+#ifndef _CS5536_H
+#define _CS5536_H
+
+#include <linux/types.h>
+
+extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
+extern void _wrmsr(u32 msr, u32 hi, u32 lo);
+
+/*
+ * MSR module base
+ */
+#define CS5536_SB_MSR_BASE      (0x00000000)
+#define CS5536_GLIU_MSR_BASE    (0x10000000)
+#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
+#define CS5536_USB_MSR_BASE     (0x40000000)
+#define CS5536_IDE_MSR_BASE     (0x60000000)
+#define CS5536_DIVIL_MSR_BASE   (0x80000000)
+#define CS5536_ACC_MSR_BASE     (0xa0000000)
+#define CS5536_UNUSED_MSR_BASE  (0xc0000000)
+#define CS5536_GLCP_MSR_BASE    (0xe0000000)
+
+#define SB_MSR_REG(offset)      (CS5536_SB_MSR_BASE     | (offset))
+#define GLIU_MSR_REG(offset)    (CS5536_GLIU_MSR_BASE   | (offset))
+#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
+#define USB_MSR_REG(offset)     (CS5536_USB_MSR_BASE    | (offset))
+#define IDE_MSR_REG(offset)     (CS5536_IDE_MSR_BASE    | (offset))
+#define DIVIL_MSR_REG(offset)   (CS5536_DIVIL_MSR_BASE  | (offset))
+#define ACC_MSR_REG(offset)     (CS5536_ACC_MSR_BASE    | (offset))
+#define UNUSED_MSR_REG(offset)  (CS5536_UNUSED_MSR_BASE | (offset))
+#define GLCP_MSR_REG(offset)    (CS5536_GLCP_MSR_BASE   | (offset))
+
+/*
+ * BAR SPACE OF VIRTUAL PCI :
+ * range for pci probe use, length is the actual size.
+ */
+/* IO space for all DIVIL modules */
+#define CS5536_IRQ_RANGE        0xffffffe0 /* USERD FOR PCI PROBE */
+#define CS5536_IRQ_LENGTH       0x20    /* THE REGS ACTUAL LENGTH */
+#define CS5536_SMB_RANGE        0xfffffff8
+#define CS5536_SMB_LENGTH       0x08
+#define CS5536_GPIO_RANGE       0xffffff00
+#define CS5536_GPIO_LENGTH      0x100
+#define CS5536_MFGPT_RANGE      0xffffffc0
+#define CS5536_MFGPT_LENGTH     0x40
+#define CS5536_ACPI_RANGE       0xffffffe0
+#define CS5536_ACPI_LENGTH      0x20
+#define CS5536_PMS_RANGE        0xffffff80
+#define CS5536_PMS_LENGTH       0x80
+/* IO space for IDE */
+#define CS5536_IDE_RANGE        0xfffffff0
+#define CS5536_IDE_LENGTH       0x10
+/* IO space for ACC */
+#define CS5536_ACC_RANGE        0xffffff80
+#define CS5536_ACC_LENGTH       0x80
+/* MEM space for ALL USB modules */
+#define CS5536_OHCI_RANGE       0xfffff000
+#define CS5536_OHCI_LENGTH      0x1000
+#define CS5536_EHCI_RANGE       0xfffff000
+#define CS5536_EHCI_LENGTH      0x1000
+
+/*
+ * PCI MSR ACCESS
+ */
+#define PCI_MSR_CTRL            0xF0
+#define PCI_MSR_ADDR            0xF4
+#define PCI_MSR_DATA_LO         0xF8
+#define PCI_MSR_DATA_HI         0xFC
+
+/**************** MSR *****************************/
+
+/*
+ * GLIU STANDARD MSR
+ */
+#define GLIU_CAP                0x00
+#define GLIU_CONFIG             0x01
+#define GLIU_SMI                0x02
+#define GLIU_ERROR              0x03
+#define GLIU_PM                 0x04
+#define GLIU_DIAG               0x05
+
+/*
+ * GLIU SPEC. MSR
+ */
+#define GLIU_P2D_BM0            0x20
+#define GLIU_P2D_BM1            0x21
+#define GLIU_P2D_BM2            0x22
+#define GLIU_P2D_BMK0           0x23
+#define GLIU_P2D_BMK1           0x24
+#define GLIU_P2D_BM3            0x25
+#define GLIU_P2D_BM4            0x26
+#define GLIU_COH                0x80
+#define GLIU_PAE                0x81
+#define GLIU_ARB                0x82
+#define GLIU_ASMI               0x83
+#define GLIU_AERR               0x84
+#define GLIU_DEBUG              0x85
+#define GLIU_PHY_CAP            0x86
+#define GLIU_NOUT_RESP          0x87
+#define GLIU_NOUT_WDATA         0x88
+#define GLIU_WHOAMI             0x8B
+#define GLIU_SLV_DIS            0x8C
+#define GLIU_IOD_BM0            0xE0
+#define GLIU_IOD_BM1            0xE1
+#define GLIU_IOD_BM2            0xE2
+#define GLIU_IOD_BM3            0xE3
+#define GLIU_IOD_BM4            0xE4
+#define GLIU_IOD_BM5            0xE5
+#define GLIU_IOD_BM6            0xE6
+#define GLIU_IOD_BM7            0xE7
+#define GLIU_IOD_BM8            0xE8
+#define GLIU_IOD_BM9            0xE9
+#define GLIU_IOD_SC0            0xEA
+#define GLIU_IOD_SC1            0xEB
+#define GLIU_IOD_SC2            0xEC
+#define GLIU_IOD_SC3            0xED
+#define GLIU_IOD_SC4            0xEE
+#define GLIU_IOD_SC5            0xEF
+#define GLIU_IOD_SC6            0xF0
+#define GLIU_IOD_SC7            0xF1
+
+/*
+ * SB STANDARD
+ */
+#define SB_CAP          0x00
+#define SB_CONFIG       0x01
+#define SB_SMI          0x02
+#define SB_ERROR        0x03
+#define SB_MAR_ERR_EN           0x00000001
+#define SB_TAR_ERR_EN           0x00000002
+#define SB_RSVD_BIT1            0x00000004
+#define SB_EXCEP_ERR_EN         0x00000008
+#define SB_SYSE_ERR_EN          0x00000010
+#define SB_PARE_ERR_EN          0x00000020
+#define SB_TAS_ERR_EN           0x00000040
+#define SB_MAR_ERR_FLAG         0x00010000
+#define SB_TAR_ERR_FLAG         0x00020000
+#define SB_RSVD_BIT2            0x00040000
+#define SB_EXCEP_ERR_FLAG       0x00080000
+#define SB_SYSE_ERR_FLAG        0x00100000
+#define SB_PARE_ERR_FLAG        0x00200000
+#define SB_TAS_ERR_FLAG         0x00400000
+#define SB_PM           0x04
+#define SB_DIAG         0x05
+
+/*
+ * SB SPEC.
+ */
+#define SB_CTRL         0x10
+#define SB_R0           0x20
+#define SB_R1           0x21
+#define SB_R2           0x22
+#define SB_R3           0x23
+#define SB_R4           0x24
+#define SB_R5           0x25
+#define SB_R6           0x26
+#define SB_R7           0x27
+#define SB_R8           0x28
+#define SB_R9           0x29
+#define SB_R10          0x2A
+#define SB_R11          0x2B
+#define SB_R12          0x2C
+#define SB_R13          0x2D
+#define SB_R14          0x2E
+#define SB_R15          0x2F
+
+/*
+ * GLCP STANDARD
+ */
+#define GLCP_CAP                0x00
+#define GLCP_CONFIG             0x01
+#define GLCP_SMI                0x02
+#define GLCP_ERROR              0x03
+#define GLCP_PM                 0x04
+#define GLCP_DIAG               0x05
+
+/*
+ * GLCP SPEC.
+ */
+#define GLCP_CLK_DIS_DELAY      0x08
+#define GLCP_PM_CLK_DISABLE     0x09
+#define GLCP_GLB_PM             0x0B
+#define GLCP_DBG_OUT            0x0C
+#define GLCP_RSVD1              0x0D
+#define GLCP_SOFT_COM           0x0E
+#define SOFT_BAR_SMB_FLAG       0x00000001
+#define SOFT_BAR_GPIO_FLAG      0x00000002
+#define SOFT_BAR_MFGPT_FLAG     0x00000004
+#define SOFT_BAR_IRQ_FLAG       0x00000008
+#define SOFT_BAR_PMS_FLAG       0x00000010
+#define SOFT_BAR_ACPI_FLAG      0x00000020
+#define SOFT_BAR_IDE_FLAG       0x00000400
+#define SOFT_BAR_ACC_FLAG       0x00000800
+#define SOFT_BAR_OHCI_FLAG      0x00001000
+#define SOFT_BAR_EHCI_FLAG      0x00002000
+#define GLCP_RSVD2              0x0F
+#define GLCP_CLK_OFF            0x10
+#define GLCP_CLK_ACTIVE         0x11
+#define GLCP_CLK_DISABLE        0x12
+#define GLCP_CLK4ACK            0x13
+#define GLCP_SYS_RST            0x14
+#define GLCP_RSVD3              0x15
+#define GLCP_DBG_CLK_CTRL       0x16
+#define GLCP_CHIP_REV_ID        0x17
+
+/* PIC */
+#define PIC_YSEL_LOW            0x20
+#define PIC_YSEL_LOW_USB_SHIFT          8
+#define PIC_YSEL_LOW_ACC_SHIFT          16
+#define PIC_YSEL_LOW_FLASH_SHIFT        24
+#define PIC_YSEL_HIGH           0x21
+#define PIC_ZSEL_LOW            0x22
+#define PIC_ZSEL_HIGH           0x23
+#define PIC_IRQM_PRIM           0x24
+#define PIC_IRQM_LPC            0x25
+#define PIC_XIRR_STS_LOW        0x26
+#define PIC_XIRR_STS_HIGH       0x27
+#define PCI_SHDW                0x34
+
+/*
+ * DIVIL STANDARD
+ */
+#define DIVIL_CAP               0x00
+#define DIVIL_CONFIG            0x01
+#define DIVIL_SMI               0x02
+#define DIVIL_ERROR             0x03
+#define DIVIL_PM                0x04
+#define DIVIL_DIAG              0x05
+
+/*
+ * DIVIL SPEC.
+ */
+#define DIVIL_LBAR_IRQ          0x08
+#define DIVIL_LBAR_KEL          0x09
+#define DIVIL_LBAR_SMB          0x0B
+#define DIVIL_LBAR_GPIO         0x0C
+#define DIVIL_LBAR_MFGPT        0x0D
+#define DIVIL_LBAR_ACPI         0x0E
+#define DIVIL_LBAR_PMS          0x0F
+#define DIVIL_LEG_IO            0x14
+#define DIVIL_BALL_OPTS         0x15
+#define DIVIL_SOFT_IRQ          0x16
+#define DIVIL_SOFT_RESET        0x17
+
+/* MFGPT */
+#define MFGPT_IRQ       0x28
+
+/*
+ * IDE STANDARD
+ */
+#define IDE_CAP         0x00
+#define IDE_CONFIG      0x01
+#define IDE_SMI         0x02
+#define IDE_ERROR       0x03
+#define IDE_PM          0x04
+#define IDE_DIAG        0x05
+
+/*
+ * IDE SPEC.
+ */
+#define IDE_IO_BAR      0x08
+#define IDE_CFG         0x10
+#define IDE_DTC         0x12
+#define IDE_CAST        0x13
+#define IDE_ETC         0x14
+#define IDE_INTERNAL_PM 0x15
+
+/*
+ * ACC STANDARD
+ */
+#define ACC_CAP         0x00
+#define ACC_CONFIG      0x01
+#define ACC_SMI         0x02
+#define ACC_ERROR       0x03
+#define ACC_PM          0x04
+#define ACC_DIAG        0x05
+
+/*
+ * USB STANDARD
+ */
+#define USB_CAP         0x00
+#define USB_CONFIG      0x01
+#define USB_SMI         0x02
+#define USB_ERROR       0x03
+#define USB_PM          0x04
+#define USB_DIAG        0x05
+
+/*
+ * USB SPEC.
+ */
+#define USB_OHCI        0x08
+#define USB_EHCI        0x09
+
+/****************** NATIVE ***************************/
+/* GPIO : I/O SPACE; REG : 32BITS */
+#define GPIOL_OUT_VAL           0x00
+#define GPIOL_OUT_EN            0x04
+
+#endif                          /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000..52e8bb0fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * cs5536 mfgpt header file
+ */
+
+#ifndef _CS5536_MFGPT_H
+#define _CS5536_MFGPT_H
+
+#include <cs5536/cs5536.h>
+#include <cs5536/cs5536_pci.h>
+
+#ifdef CONFIG_CS5536_MFGPT
+extern void setup_mfgpt0_timer(void);
+extern void disable_mfgpt0_counter(void);
+extern void enable_mfgpt0_counter(void);
+#else
+static inline void __maybe_unused setup_mfgpt0_timer(void)
+{
+}
+static inline void __maybe_unused disable_mfgpt0_counter(void)
+{
+}
+static inline void __maybe_unused enable_mfgpt0_counter(void)
+{
+}
+#endif
+
+#define MFGPT_TICK_RATE 14318000
+#define COMPARE  ((MFGPT_TICK_RATE + HZ/2) / HZ)
+
+#define MFGPT_BASE      mfgpt_base
+#define MFGPT0_CMP2     (MFGPT_BASE + 2)
+#define MFGPT0_CNT      (MFGPT_BASE + 4)
+#define MFGPT0_SETUP    (MFGPT_BASE + 6)
+
+#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
new file mode 100644
index 000000000..a0d4b7528
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * the definition file of cs5536 Virtual Support Module(VSM).
+ * pci configuration space can be accessed through the VSM, so
+ * there is no need of the MSR read/write now, except the spec.
+ * MSR registers which are not implemented yet.
+ *
+ * Copyright (C) 2007 Lemote Inc.
+ * Author : jlliu, liujl@lemote.com
+ */
+
+#ifndef _CS5536_PCI_H
+#define _CS5536_PCI_H
+
+#include <linux/types.h>
+#include <linux/pci_regs.h>
+
+extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
+extern u32 cs5536_pci_conf_read4(int function, int reg);
+
+#define CS5536_ACC_INTR         9
+#define CS5536_IDE_INTR         14
+#define CS5536_USB_INTR         11
+#define CS5536_MFGPT_INTR       5
+#define CS5536_UART1_INTR       4
+#define CS5536_UART2_INTR       3
+
+/************** PCI BUS DEVICE FUNCTION ***************/
+
+/*
+ * PCI bus device function
+ */
+#define PCI_BUS_CS5536          0
+#define PCI_IDSEL_CS5536        14
+
+/********** STANDARD PCI-2.2 EXPANSION ****************/
+
+/*
+ * PCI configuration space
+ * we have to virtualize the PCI configure space head, so we should
+ * define the necessary IDs and some others.
+ */
+
+/* CONFIG of PCI VENDOR ID*/
+#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
+        (((mod_dev_id) << 16) | (sys_vendor_id))
+
+/* VENDOR ID */
+#define CS5536_VENDOR_ID        0x1022
+
+/* DEVICE ID */
+#define CS5536_ISA_DEVICE_ID            0x2090
+#define CS5536_IDE_DEVICE_ID            0x209a
+#define CS5536_ACC_DEVICE_ID            0x2093
+#define CS5536_OHCI_DEVICE_ID           0x2094
+#define CS5536_EHCI_DEVICE_ID           0x2095
+
+/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
+#define CS5536_ISA_CLASS_CODE           0x060100
+#define CS5536_IDE_CLASS_CODE           0x010180
+#define CS5536_ACC_CLASS_CODE           0x040100
+#define CS5536_OHCI_CLASS_CODE          0x0C0310
+#define CS5536_EHCI_CLASS_CODE          0x0C0320
+
+/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
+
+#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer)     \
+        ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
+                | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
+
+#define PCI_NONE_BIST                   0x00    /* RO not implemented yet. */
+#define PCI_BRIDGE_HEADER_TYPE          0x80    /* RO */
+#define PCI_NORMAL_HEADER_TYPE          0x00
+#define PCI_NORMAL_LATENCY_TIMER        0x00
+#define PCI_NORMAL_CACHE_LINE_SIZE      0x08    /* RW */
+
+/* BAR */
+#define PCI_BAR0_REG                    0x10
+#define PCI_BAR1_REG                    0x14
+#define PCI_BAR2_REG                    0x18
+#define PCI_BAR3_REG                    0x1c
+#define PCI_BAR4_REG                    0x20
+#define PCI_BAR5_REG                    0x24
+#define PCI_BAR_RANGE_MASK              0xFFFFFFFF
+
+/* CARDBUS CIS POINTER */
+#define PCI_CARDBUS_CIS_POINTER         0x00000000
+
+/* SUBSYSTEM VENDOR ID  */
+#define CS5536_SUB_VENDOR_ID            CS5536_VENDOR_ID
+
+/* SUBSYSTEM ID */
+#define CS5536_ISA_SUB_ID               CS5536_ISA_DEVICE_ID
+#define CS5536_IDE_SUB_ID               CS5536_IDE_DEVICE_ID
+#define CS5536_ACC_SUB_ID               CS5536_ACC_DEVICE_ID
+#define CS5536_OHCI_SUB_ID              CS5536_OHCI_DEVICE_ID
+#define CS5536_EHCI_SUB_ID              CS5536_EHCI_DEVICE_ID
+
+/* EXPANSION ROM BAR */
+#define PCI_EXPANSION_ROM_BAR           0x00000000
+
+/* CAPABILITIES POINTER */
+#define PCI_CAPLIST_POINTER             0x00000000
+#define PCI_CAPLIST_USB_POINTER         0x40
+/* INTERRUPT */
+
+#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
+        ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
+                ((pin) << 8) | (mod_intr))
+
+#define PCI_MAX_LATENCY                 0x40
+#define PCI_MIN_GRANT                   0x00
+#define PCI_DEFAULT_PIN                 0x01
+
+/*********** EXPANSION PCI REG ************************/
+
+/*
+ * ISA EXPANSION
+ */
+#define PCI_UART1_INT_REG       0x50
+#define PCI_UART2_INT_REG       0x54
+#define PCI_ISA_FIXUP_REG       0x58
+
+/*
+ * IDE EXPANSION
+ */
+#define PCI_IDE_CFG_REG         0x40
+#define CS5536_IDE_FLASH_SIGNATURE      0xDEADBEEF
+#define PCI_IDE_DTC_REG         0x48
+#define PCI_IDE_CAST_REG        0x4C
+#define PCI_IDE_ETC_REG         0x50
+#define PCI_IDE_PM_REG          0x54
+#define PCI_IDE_INT_REG         0x60
+
+/*
+ * ACC EXPANSION
+ */
+#define PCI_ACC_INT_REG         0x50
+
+/*
+ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
+ */
+#define PCI_OHCI_PM_REG         0x40
+#define PCI_OHCI_INT_REG        0x50
+
+/*
+ * EHCI EXPANSION
+ */
+#define PCI_EHCI_LEGSMIEN_REG   0x50
+#define PCI_EHCI_LEGSMISTS_REG  0x54
+#define PCI_EHCI_FLADJ_REG      0x60
+
+#endif                          /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000..70d0153cc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * the read/write interfaces for Virtual Support Module(VSM)
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef _CS5536_VSM_H
+#define _CS5536_VSM_H
+
+#include <linux/types.h>
+
+typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
+typedef u32 (*cs5536_pci_vsm_read)(int reg);
+
+#define DECLARE_CS5536_MODULE(name) \
+extern void pci_##name##_write_reg(int reg, u32 value); \
+extern u32 pci_##name##_read_reg(int reg);
+
+/* ide module */
+DECLARE_CS5536_MODULE(ide)
+/* acc module */
+DECLARE_CS5536_MODULE(acc)
+/* ohci module */
+DECLARE_CS5536_MODULE(ohci)
+/* isa module */
+DECLARE_CS5536_MODULE(isa)
+/* ehci module */
+DECLARE_CS5536_MODULE(ehci)
+
+#endif                          /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/loongson.h b/arch/mips/include/asm/mach-loongson2ef/loongson.h
new file mode 100644
index 000000000..57e571128
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/loongson.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H
+#define __ASM_MACH_LOONGSON2EF_LOONGSON_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+/* loongson internal northbridge initialization */
+extern void bonito_irq_init(void);
+
+/* machine-specific reboot/halt operation */
+extern void mach_prepare_reboot(void);
+extern void mach_prepare_shutdown(void);
+
+/* environment arguments from bootloader */
+extern u32 cpu_clock_freq;
+extern u32 memsize, highmemsize;
+
+/* loongson-specific command line, env and memory initialization */
+extern void __init prom_init_memory(void);
+extern void __init prom_init_machtype(void);
+extern void __init prom_init_env(void);
+#ifdef CONFIG_LOONGSON_UART_BASE
+extern unsigned long _loongson_uart_base, loongson_uart_base;
+extern void prom_init_loongson_uart_base(void);
+#endif
+
+static inline void prom_init_uart_base(void)
+{
+#ifdef CONFIG_LOONGSON_UART_BASE
+        prom_init_loongson_uart_base();
+#endif
+}
+
+/* irq operation functions */
+extern void bonito_irqdispatch(void);
+extern void __init bonito_irq_init(void);
+extern void __init mach_init_irq(void);
+extern void mach_irq_dispatch(unsigned int pending);
+extern int mach_i8259_irq(void);
+
+/* We need this in some places... */
+#define delay() ({              \
+        int x;                          \
+        for (x = 0; x < 100000; x++)    \
+                __asm__ __volatile__(""); \
+})
+
+#define LOONGSON_REG(x) \
+        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON_IRQ_BASE       32
+#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
+
+#include <linux/interrupt.h>
+static inline void do_perfcnt_IRQ(void)
+{
+#if IS_ENABLED(CONFIG_OPROFILE)
+        do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+}
+
+#define LOONGSON_FLASH_BASE     0x1c000000
+#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
+#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
+
+#define LOONGSON_LIO0_BASE      0x1e000000
+#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
+#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
+
+#define LOONGSON_BOOT_BASE      0x1fc00000
+#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
+#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE       0x1fe00000
+#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+
+#define LOONGSON_LIO1_BASE      0x1ff00000
+#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
+#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
+
+#define LOONGSON_PCILO0_BASE    0x10000000
+#define LOONGSON_PCILO1_BASE    0x14000000
+#define LOONGSON_PCILO2_BASE    0x18000000
+#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
+#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
+#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
+
+#define LOONGSON_PCICFG_BASE    0x1fe80000
+#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
+#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+#define LOONGSON_PCIIO_BASE     0x1fd00000
+
+#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
+#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+
+/* Loongson Register Bases */
+
+#define LOONGSON_PCICONFIGBASE  0x00
+#define LOONGSON_REGBASE        0x100
+
+/* PCI Configuration Registers */
+
+#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
+#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
+#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
+#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
+#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
+#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
+
+#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
+
+#define LOONGSON_PCICMD_PERR_CLR        0x80000000
+#define LOONGSON_PCICMD_SERR_CLR        0x40000000
+#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
+#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
+#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
+#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
+#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
+#define LOONGSON_PCICMD_ASTEPEN         0x00000080
+#define LOONGSON_PCICMD_SERREN          0x00000100
+#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
+
+/* Loongson h/w Configuration */
+
+#define LOONGSON_GENCFG_OFFSET          0x4
+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+
+#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
+#define LOONGSON_GENCFG_SNOOPEN         0x00000002
+#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
+
+#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
+#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
+#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
+#define LOONGSON_GENCFG_BYTESWAP        0x00000040
+
+#define LOONGSON_GENCFG_UNCACHED        0x00000080
+#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
+#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
+#define LOONGSON_GENCFG_CACHEALG        0x00000c00
+#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
+#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
+#define LOONGSON_GENCFG_CACHESTOP       0x00002000
+#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
+#define LOONGSON_GENCFG_BUSERREN        0x00008000
+#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
+
+/* PCI address map control */
+
+#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
+#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
+#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
+
+/* GPIO Regs - r/w */
+
+#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
+/* ICU */
+#define LOONGSON_ICU_MBOXES             0x0000000f
+#define LOONGSON_ICU_MBOXES_SHIFT       0
+#define LOONGSON_ICU_DMARDY             0x00000010
+#define LOONGSON_ICU_DMAEMPTY           0x00000020
+#define LOONGSON_ICU_COPYRDY            0x00000040
+#define LOONGSON_ICU_COPYEMPTY          0x00000080
+#define LOONGSON_ICU_COPYERR            0x00000100
+#define LOONGSON_ICU_PCIIRQ             0x00000200
+#define LOONGSON_ICU_MASTERERR          0x00000400
+#define LOONGSON_ICU_SYSTEMERR          0x00000800
+#define LOONGSON_ICU_DRAMPERR           0x00001000
+#define LOONGSON_ICU_RETRYERR           0x00002000
+#define LOONGSON_ICU_GPIOS              0x01ff0000
+#define LOONGSON_ICU_GPIOS_SHIFT                16
+#define LOONGSON_ICU_GPINS              0x7e000000
+#define LOONGSON_ICU_GPINS_SHIFT                25
+#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
+#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
+#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
+
+/* PCI prefetch window base & mask */
+
+#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
+
+/* PCI_Hit*_Sel_* */
+
+#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
+#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
+#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
+#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
+#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
+#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
+
+/* PXArb Config & Status */
+
+#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
+#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+
+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
+#define LOONGSON_CHIPCFG        (void __iomem *)TO_UNCAC(0x1fc00180)
+
+/* pcimap */
+
+#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
+#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
+#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
+#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
+#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
+        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
+#include <linux/cpufreq.h>
+extern struct cpufreq_frequency_table loongson2_clockmod_table[];
+extern int loongson2_cpu_set_rate(unsigned long rate_khz);
+#endif
+
+/*
+ * address windows configuration module
+ *
+ * loongson2e do not have this module
+ */
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/* address window config module base address */
+#define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
+#define LOONGSON_ADDRWINCFG_SIZE                0x180
+
+extern unsigned long _loongson_addrwincfg_base;
+#define LOONGSON_ADDRWINCFG(offset) \
+        (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
+
+#define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
+#define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
+#define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
+#define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
+
+#define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
+#define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
+#define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
+#define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
+
+#define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
+#define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
+#define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
+#define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
+
+#define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
+#define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
+#define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
+#define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
+
+#define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
+#define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
+#define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
+#define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
+
+#define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
+#define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
+#define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
+#define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
+
+#define ADDRWIN_WIN0    0
+#define ADDRWIN_WIN1    1
+#define ADDRWIN_WIN2    2
+#define ADDRWIN_WIN3    3
+
+#define ADDRWIN_MAP_DST_DDR     0
+#define ADDRWIN_MAP_DST_PCI     1
+#define ADDRWIN_MAP_DST_LIO     1
+
+/*
+ * s: CPU, PCIDMA
+ * d: DDR, PCI, LIO
+ * win: 0, 1, 2, 3
+ * src: map source
+ * dst: map destination
+ * size: ~mask + 1
+ */
+#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
+        s##_WIN##w##_BASE = (src); \
+        s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
+        s##_WIN##w##_MASK = ~(size-1); \
+} while (0)
+
+#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
+#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
+#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
+        LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
+
+#endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
+#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/machine.h b/arch/mips/include/asm/mach-loongson2ef/machine.h
new file mode 100644
index 000000000..4097267ef
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/machine.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_MACHINE_H
+#define __ASM_MACH_LOONGSON2EF_MACHINE_H
+
+#ifdef CONFIG_LEMOTE_FULOONG2E
+
+#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
+
+#endif
+
+/* use fuloong2f as the default machine of LEMOTE_MACH2F */
+#ifdef CONFIG_LEMOTE_MACH2F
+
+#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
+
+#endif
+
+#endif /* __ASM_MACH_LOONGSON2EF_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/mem.h b/arch/mips/include/asm/mach-loongson2ef/mem.h
new file mode 100644
index 000000000..d1d759b89
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/mem.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_MEM_H
+#define __ASM_MACH_LOONGSON2EF_MEM_H
+
+/*
+ * high memory space
+ *
+ * in loongson2e, starts from 512M
+ * in loongson2f, starts from 2G 256M
+ */
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_HIGHMEM_START  0x20000000
+#else
+#define LOONGSON_HIGHMEM_START  0x90000000
+#endif
+
+/*
+ * the peripheral registers(MMIO):
+ *
+ * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
+ * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
+ */
+
+#define LOONGSON_MMIO_MEM_START 0x10000000
+
+#ifdef CONFIG_CPU_LOONGSON2E
+#define LOONGSON_MMIO_MEM_END   0x20000000
+#else
+#define LOONGSON_MMIO_MEM_END   0x80000000
+#endif
+
+#endif /* __ASM_MACH_LOONGSON2EF_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/pci.h b/arch/mips/include/asm/mach-loongson2ef/pci.h
new file mode 100644
index 000000000..5588c5bc5
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/pci.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
+#define __ASM_MACH_LOONGSON2EF_PCI_H_
+
+extern struct pci_ops loongson_pci_ops;
+
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START   0x00004000UL
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/*
+ * we use address window2 to map cpu address space to pci space
+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
+ * why not use window 0 & 1? because they are used by cpu when booting.
+ * window0: cpu [0, 256M] -> ddr [0, 256M]
+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
+ */
+
+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
+#define LOONGSON_CPU_MEM_SRC    0x40000000ul            /* 1G */
+#define LOONGSON_PCI_MEM_DST    LOONGSON_CPU_MEM_SRC
+
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCI_MEM_DST
+#define LOONGSON_PCI_MEM_END    (0x80000000ul-1)        /* 2G */
+
+#define MMAP_CPUTOPCI_SIZE      (LOONGSON_PCI_MEM_END - \
+                                        LOONGSON_PCI_MEM_START + 1)
+
+#else   /* loongson2f/32bit & loongson2e */
+
+/* this pci memory space is mapped by pcimap in pci.c */
+#define LOONGSON_PCI_MEM_START  LOONGSON_PCILO1_BASE
+#define LOONGSON_PCI_MEM_END    (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
+
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START   0x00004000UL
+
+#endif  /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
+#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson2ef/spaces.h b/arch/mips/include/asm/mach-loongson2ef/spaces.h
new file mode 100644
index 000000000..ba4e8e9b6
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/spaces.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON2EF_SPACES_H_
+#define __ASM_MACH_LOONGSON2EF_SPACES_H_
+
+#if defined(CONFIG_64BIT)
+#define CAC_BASE        _AC(0x9800000000000000, UL)
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/mach-loongson32/cpufreq.h b/arch/mips/include/asm/mach-loongson32/cpufreq.h
new file mode 100644
index 000000000..e422a3288
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/cpufreq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 CPUFreq platform support.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H
+#define __ASM_MACH_LOONGSON32_CPUFREQ_H
+
+struct plat_ls1x_cpufreq {
+        const char      *clk_name;      /* CPU clk */
+        const char      *osc_clk_name;  /* OSC clk */
+        unsigned int    max_freq;       /* in kHz */
+        unsigned int    min_freq;       /* in kHz */
+};
+
+#endif /* __ASM_MACH_LOONGSON32_CPUFREQ_H */
diff --git a/arch/mips/include/asm/mach-loongson32/dma.h b/arch/mips/include/asm/mach-loongson32/dma.h
new file mode 100644
index 000000000..e917b3ccb
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/dma.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 NAND platform support.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_DMA_H
+#define __ASM_MACH_LOONGSON32_DMA_H
+
+#define LS1X_DMA_CHANNEL0       0
+#define LS1X_DMA_CHANNEL1       1
+#define LS1X_DMA_CHANNEL2       2
+
+struct plat_ls1x_dma {
+        int nr_channels;
+};
+
+extern struct plat_ls1x_dma ls1b_dma_pdata;
+
+#endif /* __ASM_MACH_LOONGSON32_DMA_H */
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
new file mode 100644
index 000000000..6115f025b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * IRQ mappings for Loongson 1
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_IRQ_H
+#define __ASM_MACH_LOONGSON32_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE               0
+#define MIPS_CPU_IRQ(x)                 (MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ                    MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ                    MIPS_CPU_IRQ(1)
+#define INT0_IRQ                        MIPS_CPU_IRQ(2)
+#define INT1_IRQ                        MIPS_CPU_IRQ(3)
+#define INT2_IRQ                        MIPS_CPU_IRQ(4)
+#define INT3_IRQ                        MIPS_CPU_IRQ(5)
+#define INT4_IRQ                        MIPS_CPU_IRQ(6)
+#define TIMER_IRQ                       MIPS_CPU_IRQ(7)         /* cpu timer */
+
+#define MIPS_CPU_IRQS           (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE                   MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x)                  (LS1X_IRQ_BASE + (n << 5) + (x))
+
+#define LS1X_UART0_IRQ                  LS1X_IRQ(0, 2)
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define LS1X_UART1_IRQ                  LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ                  LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ                  LS1X_IRQ(0, 5)
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define LS1X_UART1_IRQ                  LS1X_IRQ(0, 4)
+#define LS1X_UART2_IRQ                  LS1X_IRQ(0, 5)
+#endif
+#define LS1X_CAN0_IRQ                   LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ                   LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ                   LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ                   LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ                   LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ                   LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ                   LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ                   LS1X_IRQ(0, 15)
+#if defined(CONFIG_LOONGSON1_LS1C)
+#define LS1X_NAND_IRQ                   LS1X_IRQ(0, 16)
+#endif
+#define LS1X_PWM0_IRQ                   LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ                   LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ                   LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ                   LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ               LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ               LS1X_IRQ(0, 22)
+#define LS1X_RTC_INT2_IRQ               LS1X_IRQ(0, 23)
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define LS1X_TOY_INT0_IRQ               LS1X_IRQ(0, 24)
+#define LS1X_TOY_INT1_IRQ               LS1X_IRQ(0, 25)
+#define LS1X_TOY_INT2_IRQ               LS1X_IRQ(0, 26)
+#define LS1X_RTC_TICK_IRQ               LS1X_IRQ(0, 27)
+#define LS1X_TOY_TICK_IRQ               LS1X_IRQ(0, 28)
+#define LS1X_UART4_IRQ                  LS1X_IRQ(0, 29)
+#define LS1X_UART5_IRQ                  LS1X_IRQ(0, 30)
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define LS1X_UART3_IRQ                  LS1X_IRQ(0, 29)
+#define LS1X_ADC_IRQ                    LS1X_IRQ(0, 30)
+#define LS1X_SDIO_IRQ                   LS1X_IRQ(0, 31)
+#endif
+
+#define LS1X_EHCI_IRQ                   LS1X_IRQ(1, 0)
+#define LS1X_OHCI_IRQ                   LS1X_IRQ(1, 1)
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define LS1X_GMAC0_IRQ                  LS1X_IRQ(1, 2)
+#define LS1X_GMAC1_IRQ                  LS1X_IRQ(1, 3)
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define LS1X_OTG_IRQ                    LS1X_IRQ(1, 2)
+#define LS1X_GMAC0_IRQ                  LS1X_IRQ(1, 3)
+#define LS1X_CAM_IRQ                    LS1X_IRQ(1, 4)
+#define LS1X_UART4_IRQ                  LS1X_IRQ(1, 5)
+#define LS1X_UART5_IRQ                  LS1X_IRQ(1, 6)
+#define LS1X_UART6_IRQ                  LS1X_IRQ(1, 7)
+#define LS1X_UART7_IRQ                  LS1X_IRQ(1, 8)
+#define LS1X_UART8_IRQ                  LS1X_IRQ(1, 9)
+#define LS1X_UART9_IRQ                  LS1X_IRQ(1, 13)
+#define LS1X_UART10_IRQ                 LS1X_IRQ(1, 14)
+#define LS1X_UART11_IRQ                 LS1X_IRQ(1, 15)
+#define LS1X_I2C0_IRQ                   LS1X_IRQ(1, 17)
+#define LS1X_I2C1_IRQ                   LS1X_IRQ(1, 18)
+#define LS1X_I2C2_IRQ                   LS1X_IRQ(1, 19)
+#endif
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define INTN    4
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define INTN    5
+#endif
+
+#define LS1X_IRQS               (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
+
+#define NR_IRQS                 (MIPS_CPU_IRQS + LS1X_IRQS)
+
+#endif /* __ASM_MACH_LOONGSON32_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
new file mode 100644
index 000000000..eb3ddbec1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Register mappings for Loongson 1
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
+#define __ASM_MACH_LOONGSON32_LOONGSON1_H
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define DEFAULT_MEMSIZE                 64      /* If no memsize provided */
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define DEFAULT_MEMSIZE                 32
+#endif
+
+/* Loongson 1 Register Bases */
+#define LS1X_MUX_BASE                   0x1fd00420
+#define LS1X_INTC_BASE                  0x1fd01040
+#define LS1X_GPIO0_BASE                 0x1fd010c0
+#define LS1X_GPIO1_BASE                 0x1fd010c4
+#define LS1X_DMAC_BASE                  0x1fd01160
+#define LS1X_CBUS_BASE                  0x1fd011c0
+#define LS1X_EHCI_BASE                  0x1fe00000
+#define LS1X_OHCI_BASE                  0x1fe08000
+#define LS1X_GMAC0_BASE                 0x1fe10000
+#define LS1X_GMAC1_BASE                 0x1fe20000
+
+#define LS1X_UART0_BASE                 0x1fe40000
+#define LS1X_UART1_BASE                 0x1fe44000
+#define LS1X_UART2_BASE                 0x1fe48000
+#define LS1X_UART3_BASE                 0x1fe4c000
+#define LS1X_CAN0_BASE                  0x1fe50000
+#define LS1X_CAN1_BASE                  0x1fe54000
+#define LS1X_I2C0_BASE                  0x1fe58000
+#define LS1X_I2C1_BASE                  0x1fe68000
+#define LS1X_I2C2_BASE                  0x1fe70000
+#define LS1X_PWM0_BASE                  0x1fe5c000
+#define LS1X_PWM1_BASE                  0x1fe5c010
+#define LS1X_PWM2_BASE                  0x1fe5c020
+#define LS1X_PWM3_BASE                  0x1fe5c030
+#define LS1X_WDT_BASE                   0x1fe5c060
+#define LS1X_RTC_BASE                   0x1fe64000
+#define LS1X_AC97_BASE                  0x1fe74000
+#define LS1X_NAND_BASE                  0x1fe78000
+#define LS1X_CLK_BASE                   0x1fe78030
+
+#include <regs-clk.h>
+#include <regs-mux.h>
+#include <regs-pwm.h>
+#include <regs-rtc.h>
+#include <regs-wdt.h>
+
+#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson32/nand.h b/arch/mips/include/asm/mach-loongson32/nand.h
new file mode 100644
index 000000000..aaf5ed19d
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/nand.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 NAND platform support.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_NAND_H
+#define __ASM_MACH_LOONGSON32_NAND_H
+
+#include <linux/dmaengine.h>
+#include <linux/mtd/partitions.h>
+
+struct plat_ls1x_nand {
+        struct mtd_partition *parts;
+        unsigned int nr_parts;
+
+        int hold_cycle;
+        int wait_cycle;
+};
+
+extern struct plat_ls1x_nand ls1b_nand_pdata;
+
+bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param);
+
+#endif /* __ASM_MACH_LOONGSON32_NAND_H */
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
new file mode 100644
index 000000000..eb83e2741
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
+#define __ASM_MACH_LOONGSON32_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+#include <dma.h>
+#include <nand.h>
+
+extern struct platform_device ls1x_uart_pdev;
+extern struct platform_device ls1x_cpufreq_pdev;
+extern struct platform_device ls1x_eth0_pdev;
+extern struct platform_device ls1x_eth1_pdev;
+extern struct platform_device ls1x_ehci_pdev;
+extern struct platform_device ls1x_gpio0_pdev;
+extern struct platform_device ls1x_gpio1_pdev;
+extern struct platform_device ls1x_rtc_pdev;
+extern struct platform_device ls1x_wdt_pdev;
+
+void __init ls1x_clk_init(void);
+void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
+void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
+
+#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
new file mode 100644
index 000000000..98136fa8b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Clock Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
+#define __ASM_MACH_LOONGSON32_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
+
+#define LS1X_CLK_PLL_FREQ               LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV                LS1X_CLK_REG(0x4)
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN                       BIT(31)
+#define DIV_DC_RST                      BIT(30)
+#define DIV_CPU_EN                      BIT(25)
+#define DIV_CPU_RST                     BIT(24)
+#define DIV_DDR_EN                      BIT(19)
+#define DIV_DDR_RST                     BIT(18)
+#define RST_DC_EN                       BIT(5)
+#define RST_DC                          BIT(4)
+#define RST_DDR_EN                      BIT(3)
+#define RST_DDR                         BIT(2)
+#define RST_CPU_EN                      BIT(1)
+#define RST_CPU                         BIT(0)
+
+#define DIV_DC_SHIFT                    26
+#define DIV_CPU_SHIFT                   20
+#define DIV_DDR_SHIFT                   14
+
+#define DIV_DC_WIDTH                    4
+#define DIV_CPU_WIDTH                   4
+#define DIV_DDR_WIDTH                   4
+
+#define BYPASS_DC_SHIFT                 12
+#define BYPASS_DDR_SHIFT                10
+#define BYPASS_CPU_SHIFT                8
+
+#define BYPASS_DC_WIDTH                 1
+#define BYPASS_DDR_WIDTH                1
+#define BYPASS_CPU_WIDTH                1
+
+#elif defined(CONFIG_LOONGSON1_LS1C)
+/* PLL/SDRAM Frequency configuration register Bits */
+#define PLL_VALID                       BIT(31)
+#define FRAC_N                          GENMASK(23, 16)
+#define RST_TIME                        GENMASK(3, 2)
+#define SDRAM_DIV                       GENMASK(1, 0)
+
+/* CPU/CAMERA/DC Frequency configuration register Bits */
+#define DIV_DC_EN                       BIT(31)
+#define DIV_DC                          GENMASK(30, 24)
+#define DIV_CAM_EN                      BIT(23)
+#define DIV_CAM                         GENMASK(22, 16)
+#define DIV_CPU_EN                      BIT(15)
+#define DIV_CPU                         GENMASK(14, 8)
+#define DIV_DC_SEL_EN                   BIT(5)
+#define DIV_DC_SEL                      BIT(4)
+#define DIV_CAM_SEL_EN                  BIT(3)
+#define DIV_CAM_SEL                     BIT(2)
+#define DIV_CPU_SEL_EN                  BIT(1)
+#define DIV_CPU_SEL                     BIT(0)
+
+#define DIV_DC_SHIFT                    24
+#define DIV_CAM_SHIFT                   16
+#define DIV_CPU_SHIFT                   8
+#define DIV_DDR_SHIFT                   0
+
+#define DIV_DC_WIDTH                    7
+#define DIV_CAM_WIDTH                   7
+#define DIV_CPU_WIDTH                   7
+#define DIV_DDR_WIDTH                   2
+
+#endif
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
new file mode 100644
index 000000000..95788a4f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 MUX Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
+#define __ASM_MACH_LOONGSON32_REGS_MUX_H
+
+#define LS1X_MUX_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
+
+#define LS1X_MUX_CTRL0                  LS1X_MUX_REG(0x0)
+#define LS1X_MUX_CTRL1                  LS1X_MUX_REG(0x4)
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+/* MUX CTRL0 Register Bits */
+#define UART0_USE_PWM23                 BIT(28)
+#define UART0_USE_PWM01                 BIT(27)
+#define UART1_USE_LCD0_5_6_11           BIT(26)
+#define I2C2_USE_CAN1                   BIT(25)
+#define I2C1_USE_CAN0                   BIT(24)
+#define NAND3_USE_UART5                 BIT(23)
+#define NAND3_USE_UART4                 BIT(22)
+#define NAND3_USE_UART1_DAT             BIT(21)
+#define NAND3_USE_UART1_CTS             BIT(20)
+#define NAND3_USE_PWM23                 BIT(19)
+#define NAND3_USE_PWM01                 BIT(18)
+#define NAND2_USE_UART5                 BIT(17)
+#define NAND2_USE_UART4                 BIT(16)
+#define NAND2_USE_UART1_DAT             BIT(15)
+#define NAND2_USE_UART1_CTS             BIT(14)
+#define NAND2_USE_PWM23                 BIT(13)
+#define NAND2_USE_PWM01                 BIT(12)
+#define NAND1_USE_UART5                 BIT(11)
+#define NAND1_USE_UART4                 BIT(10)
+#define NAND1_USE_UART1_DAT             BIT(9)
+#define NAND1_USE_UART1_CTS             BIT(8)
+#define NAND1_USE_PWM23                 BIT(7)
+#define NAND1_USE_PWM01                 BIT(6)
+#define GMAC1_USE_UART1                 BIT(4)
+#define GMAC1_USE_UART0                 BIT(3)
+#define LCD_USE_UART0_DAT               BIT(2)
+#define LCD_USE_UART15                  BIT(1)
+#define LCD_USE_UART0                   BIT(0)
+
+/* MUX CTRL1 Register Bits */
+#define USB_RESET                       BIT(31)
+#define SPI1_CS_USE_PWM01               BIT(24)
+#define SPI1_USE_CAN                    BIT(23)
+#define DISABLE_DDR_CONFSPACE           BIT(20)
+#define DDR32TO16EN                     BIT(16)
+#define GMAC1_SHUT                      BIT(13)
+#define GMAC0_SHUT                      BIT(12)
+#define USB_SHUT                        BIT(11)
+#define UART1_3_USE_CAN1                BIT(5)
+#define UART1_2_USE_CAN0                BIT(4)
+#define GMAC1_USE_TXCLK                 BIT(3)
+#define GMAC0_USE_TXCLK                 BIT(2)
+#define GMAC1_USE_PWM23                 BIT(1)
+#define GMAC0_USE_PWM01                 BIT(0)
+
+#elif defined(CONFIG_LOONGSON1_LS1C)
+
+/* SHUT_CTRL Register Bits */
+#define UART_SPLIT                      GENMASK(31, 30)
+#define OUTPUT_CLK                      GENMASK(29, 26)
+#define ADC_SHUT                        BIT(25)
+#define SDIO_SHUT                       BIT(24)
+#define DMA2_SHUT                       BIT(23)
+#define DMA1_SHUT                       BIT(22)
+#define DMA0_SHUT                       BIT(21)
+#define SPI1_SHUT                       BIT(20)
+#define SPI0_SHUT                       BIT(19)
+#define I2C2_SHUT                       BIT(18)
+#define I2C1_SHUT                       BIT(17)
+#define I2C0_SHUT                       BIT(16)
+#define AC97_SHUT                       BIT(15)
+#define I2S_SHUT                        BIT(14)
+#define UART3_SHUT                      BIT(13)
+#define UART2_SHUT                      BIT(12)
+#define UART1_SHUT                      BIT(11)
+#define UART0_SHUT                      BIT(10)
+#define CAN1_SHUT                       BIT(9)
+#define CAN0_SHUT                       BIT(8)
+#define ECC_SHUT                        BIT(7)
+#define GMAC_SHUT                       BIT(6)
+#define USBHOST_SHUT                    BIT(5)
+#define USBOTG_SHUT                     BIT(4)
+#define SDRAM_SHUT                      BIT(3)
+#define SRAM_SHUT                       BIT(2)
+#define CAM_SHUT                        BIT(1)
+#define LCD_SHUT                        BIT(0)
+
+#define UART_SPLIT_SHIFT                        30
+#define OUTPUT_CLK_SHIFT                        26
+
+/* MISC_CTRL Register Bits */
+#define USBHOST_RSTN                    BIT(31)
+#define PHY_INTF_SELI                   GENMASK(30, 28)
+#define AC97_EN                         BIT(25)
+#define SDIO_DMA_EN                     GENMASK(24, 23)
+#define ADC_DMA_EN                      BIT(22)
+#define SDIO_USE_SPI1                   BIT(17)
+#define SDIO_USE_SPI0                   BIT(16)
+#define SRAM_CTRL                       GENMASK(15, 0)
+
+#define PHY_INTF_SELI_SHIFT                     28
+#define SDIO_DMA_EN_SHIFT                       23
+#define SRAM_CTRL_SHIFT                         0
+
+#define LS1X_CBUS_REG(n, x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
+
+#define LS1X_CBUS_FIRST(n)              LS1X_CBUS_REG(n, 0x00)
+#define LS1X_CBUS_SECOND(n)             LS1X_CBUS_REG(n, 0x10)
+#define LS1X_CBUS_THIRD(n)              LS1X_CBUS_REG(n, 0x20)
+#define LS1X_CBUS_FOURTHT(n)            LS1X_CBUS_REG(n, 0x30)
+#define LS1X_CBUS_FIFTHT(n)             LS1X_CBUS_REG(n, 0x40)
+
+#endif
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-pwm.h b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
new file mode 100644
index 000000000..ec870c82d
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 PWM Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_PWM_H
+#define __ASM_MACH_LOONGSON32_REGS_PWM_H
+
+/* Loongson 1 PWM Timer Register Definitions */
+#define PWM_CNT                 0x0
+#define PWM_HRC                 0x4
+#define PWM_LRC                 0x8
+#define PWM_CTRL                0xc
+
+/* PWM Control Register Bits */
+#define CNT_RST                 BIT(7)
+#define INT_SR                  BIT(6)
+#define INT_EN                  BIT(5)
+#define PWM_SINGLE              BIT(4)
+#define PWM_OE                  BIT(3)
+#define CNT_EN                  BIT(0)
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-rtc.h b/arch/mips/include/asm/mach-loongson32/regs-rtc.h
new file mode 100644
index 000000000..a3d096be1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/regs-rtc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
+ *
+ * Loongson 1 RTC timer Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_RTC_H
+#define __ASM_MACH_LOONGSON32_REGS_RTC_H
+
+#define LS1X_RTC_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_RTC_BASE + (x)))
+
+#define LS1X_RTC_CTRL   LS1X_RTC_REG(0x40)
+
+#define RTC_EXTCLK_OK   (BIT(5) | BIT(8))
+#define RTC_EXTCLK_EN   BIT(8)
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_RTC_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-wdt.h b/arch/mips/include/asm/mach-loongson32/regs-wdt.h
new file mode 100644
index 000000000..c6d345fe1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/regs-wdt.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Watchdog Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_WDT_H
+#define __ASM_MACH_LOONGSON32_REGS_WDT_H
+
+#define WDT_EN                  0x0
+#define WDT_TIMER               0x4
+#define WDT_SET                 0x8
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
new file mode 100644
index 000000000..afc92b7a6
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+
+#include <linux/types.h>
+
+#define SYSTEM_RAM_LOW          1
+#define SYSTEM_RAM_HIGH         2
+#define SYSTEM_RAM_RESERVED     3
+#define PCI_IO                  4
+#define PCI_MEM                 5
+#define LOONGSON_CFG_REG        6
+#define VIDEO_ROM               7
+#define ADAPTER_ROM             8
+#define ACPI_TABLE              9
+#define SMBIOS_TABLE            10
+#define MAX_MEMORY_TYPE         11
+
+#define LOONGSON3_BOOT_MEM_MAP_MAX 128
+struct efi_memory_map_loongson {
+        u16 vers;       /* version of efi_memory_map */
+        u32 nr_map;     /* number of memory_maps */
+        u32 mem_freq;   /* memory frequence */
+        struct mem_map {
+                u32 node_id;    /* node_id which memory attached to */
+                u32 mem_type;   /* system memory, pci memory, pci io, etc. */
+                u64 mem_start;  /* memory map start address */
+                u32 mem_size;   /* each memory_map size, not the total size */
+        } map[LOONGSON3_BOOT_MEM_MAP_MAX];
+} __packed;
+
+enum loongson_cpu_type {
+        Legacy_2E = 0x0,
+        Legacy_2F = 0x1,
+        Legacy_3A = 0x2,
+        Legacy_3B = 0x3,
+        Legacy_1A = 0x4,
+        Legacy_1B = 0x5,
+        Legacy_2G = 0x6,
+        Legacy_2H = 0x7,
+        Loongson_1A = 0x100,
+        Loongson_1B = 0x101,
+        Loongson_2E = 0x200,
+        Loongson_2F = 0x201,
+        Loongson_2G = 0x202,
+        Loongson_2H = 0x203,
+        Loongson_3A = 0x300,
+        Loongson_3B = 0x301
+};
+
+/*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+struct efi_cpuinfo_loongson {
+        u16 vers;     /* version of efi_cpuinfo_loongson */
+        u32 processor_id; /* PRID, e.g. 6305, 6306 */
+        u32 cputype;  /* Loongson_3A/3B, etc. */
+        u32 total_node;   /* num of total numa nodes */
+        u16 cpu_startup_core_id; /* Boot core id */
+        u16 reserved_cores_mask;
+        u32 cpu_clock_freq; /* cpu_clock */
+        u32 nr_cpus;
+} __packed;
+
+#define MAX_UARTS 64
+struct uart_device {
+        u32 iotype; /* see include/linux/serial_core.h */
+        u32 uartclk;
+        u32 int_offset;
+        u64 uart_base;
+} __packed;
+
+#define MAX_SENSORS 64
+#define SENSOR_TEMPER  0x00000001
+#define SENSOR_VOLTAGE 0x00000002
+#define SENSOR_FAN     0x00000004
+struct sensor_device {
+        char name[32];  /* a formal name */
+        char label[64]; /* a flexible description */
+        u32 type;       /* SENSOR_* */
+        u32 id;         /* instance id of a sensor-class */
+        u32 fan_policy; /* see loongson_hwmon.h */
+        u32 fan_percent;/* only for constant speed policy */
+        u64 base_addr;  /* base address of device registers */
+} __packed;
+
+struct system_loongson {
+        u16 vers;     /* version of system_loongson */
+        u32 ccnuma_smp; /* 0: no numa; 1: has numa */
+        u32 sing_double_channel; /* 1:single; 2:double */
+        u32 nr_uarts;
+        struct uart_device uarts[MAX_UARTS];
+        u32 nr_sensors;
+        struct sensor_device sensors[MAX_SENSORS];
+        char has_ec;
+        char ec_name[32];
+        u64 ec_base_addr;
+        char has_tcm;
+        char tcm_name[32];
+        u64 tcm_base_addr;
+        u64 workarounds; /* see workarounds.h */
+} __packed;
+
+struct irq_source_routing_table {
+        u16 vers;
+        u16 size;
+        u16 rtr_bus;
+        u16 rtr_devfn;
+        u32 vendor;
+        u32 device;
+        u32 PIC_type;   /* conform use HT or PCI to route to CPU-PIC */
+        u64 ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
+        u64 ht_enable;  /* irqs used in this PIC */
+        u32 node_id;    /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
+        u64 pci_mem_start_addr;
+        u64 pci_mem_end_addr;
+        u64 pci_io_start_addr;
+        u64 pci_io_end_addr;
+        u64 pci_config_addr;
+        u32 dma_mask_bits;
+} __packed;
+
+struct interface_info {
+        u16 vers; /* version of the specificition */
+        u16 size;
+        u8  flag;
+        char description[64];
+} __packed;
+
+#define MAX_RESOURCE_NUMBER 128
+struct resource_loongson {
+        u64 start; /* resource start address */
+        u64 end;   /* resource end address */
+        char name[64];
+        u32 flags;
+};
+
+struct archdev_data {};  /* arch specific additions */
+
+struct board_devices {
+        char name[64];    /* hold the device name */
+        u32 num_resources; /* number of device_resource */
+        /* for each device's resource */
+        struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+        /* arch specific additions */
+        struct archdev_data archdata;
+};
+
+struct loongson_special_attribute {
+        u16 vers;     /* version of this special */
+        char special_name[64]; /* special_atribute_name */
+        u32 loongson_special_type; /* type of special device */
+        /* for each device's resource */
+        struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+};
+
+struct loongson_params {
+        u64 memory_offset;      /* efi_memory_map_loongson struct offset */
+        u64 cpu_offset;         /* efi_cpuinfo_loongson struct offset */
+        u64 system_offset;      /* system_loongson struct offset */
+        u64 irq_offset;         /* irq_source_routing_table struct offset */
+        u64 interface_offset;   /* interface_info struct offset */
+        u64 special_offset;     /* loongson_special_attribute struct offset */
+        u64 boarddev_table_offset;  /* board_devices offset */
+};
+
+struct smbios_tables {
+        u16 vers;     /* version of smbios */
+        u64 vga_bios; /* vga_bios address */
+        struct loongson_params lp;
+};
+
+struct efi_reset_system_t {
+        u64 ResetCold;
+        u64 ResetWarm;
+        u64 ResetType;
+        u64 Shutdown;
+        u64 DoSuspend; /* NULL if not support */
+};
+
+struct efi_loongson {
+        u64 mps;        /* MPS table */
+        u64 acpi;       /* ACPI table (IA64 ext 0.71) */
+        u64 acpi20;     /* ACPI table (ACPI 2.0) */
+        struct smbios_tables smbios;    /* SM BIOS table */
+        u64 sal_systab; /* SAL system table */
+        u64 boot_info;  /* boot info table */
+};
+
+struct boot_params {
+        struct efi_loongson efi;
+        struct efi_reset_system_t reset_system;
+};
+
+enum loongson_bridge_type {
+        LS7A = 1,
+        RS780E = 2,
+        VIRTUAL = 3
+};
+
+struct loongson_system_configuration {
+        u32 nr_cpus;
+        u32 nr_nodes;
+        int cores_per_node;
+        int cores_per_package;
+        u16 boot_cpu_id;
+        u16 reserved_cpus_mask;
+        enum loongson_cpu_type cputype;
+        enum loongson_bridge_type bridgetype;
+        u64 ht_control_base;
+        u64 pci_mem_start_addr;
+        u64 pci_mem_end_addr;
+        u64 pci_io_base;
+        u64 restart_addr;
+        u64 poweroff_addr;
+        u64 suspend_addr;
+        u64 vgabios_addr;
+        u32 dma_mask_bits;
+        char ecname[32];
+        u32 nr_uarts;
+        struct uart_device uarts[MAX_UARTS];
+        u32 nr_sensors;
+        struct sensor_device sensors[MAX_SENSORS];
+        u64 workarounds;
+        void (*early_config)(void);
+};
+
+extern struct efi_memory_map_loongson *loongson_memmap;
+extern struct loongson_system_configuration loongson_sysconf;
+
+extern u32 node_id_offset;
+extern void ls7a_early_config(void);
+extern void rs780e_early_config(void);
+extern void virtual_early_config(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000..839410cda
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson64c_4core_ls7a_begin[];
+extern u32 __dtb_loongson64c_4core_rs780e_begin[];
+extern u32 __dtb_loongson64c_8core_rs780e_begin[];
+extern u32 __dtb_loongson64g_4core_ls7a_begin[];
+extern u32 __dtb_loongson64v_4core_virtio_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
new file mode 100644
index 000000000..eb181224e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
+ * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
+ * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
+ *
+ * reference: /proc/cpuinfo,
+ *      arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
+ *      arch/mips/kernel/proc.c(show_cpuinfo),
+ *      loongson2f user manual.
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_32fpr           1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_4kex            1
+#define cpu_has_64bits          1
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_counter         1
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_divec           0
+#define cpu_has_inclusive_pcaches       1
+#define cpu_has_llsc            1
+#define cpu_has_mcheck          0
+#define cpu_has_mdmx            0
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_mips3d          0
+#define cpu_has_mipsmt          0
+#define cpu_has_smartmips       0
+#define cpu_has_tlb             1
+#define cpu_has_tx39_cache      0
+#define cpu_has_vce             0
+#define cpu_has_veic            0
+#define cpu_has_vint            0
+#define cpu_has_vtag_icache     0
+#define cpu_has_wsbh            1
+#define cpu_has_ic_fills_f_dc   1
+#define cpu_hwrena_impl_bits    0xc0000000
+#define cpu_has_mac2008_only    1
+#define cpu_has_mips_r2_exec_hazard 0
+#define cpu_has_perf_cntr_intr_bit      0
+
+#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
new file mode 100644
index 000000000..d64af19c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
+#define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_
+
+#include <asm/cpu-info.h>
+
+#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
+
+#include <loongson_regs.h>
+
+#define LOONGSON_FPREV_MASK 0x7
+
+void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);
+
+static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
+{
+        /* All supported cores have non-zero LOONGSON_CFG1 data. */
+        return c->loongson3_cpucfg_data[0] != 0;
+}
+
+static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
+        __u64 sel)
+{
+        switch (sel) {
+        case LOONGSON_CFG0:
+                return c->processor_id;
+        case LOONGSON_CFG1:
+        case LOONGSON_CFG2:
+        case LOONGSON_CFG3:
+                return c->loongson3_cpucfg_data[sel - 1];
+        case LOONGSON_CFG4:
+        case LOONGSON_CFG5:
+                /* CPUCFG selects 4 and 5 are related to the input clock
+                 * signal.
+                 *
+                 * Unimplemented for now.
+                 */
+                return 0;
+        case LOONGSON_CFG6:
+                /* CPUCFG select 6 is for the undocumented Safe Extension. */
+                return 0;
+        case LOONGSON_CFG7:
+                /* CPUCFG select 7 is for the virtualization extension.
+                 * We don't know if the two currently known features are
+                 * supported on older cores according to the public
+                 * documentation, so leave this at zero.
+                 */
+                return 0;
+        }
+
+        /*
+         * Return 0 for unrecognized CPUCFG selects, which is real hardware
+         * behavior observed on Loongson 3A R4.
+         */
+        return 0;
+}
+#else
+static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
+{
+}
+
+static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c)
+{
+        return false;
+}
+
+static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,
+        __u64 sel)
+{
+        return 0;
+}
+#endif
+
+#endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
new file mode 100644
index 000000000..98ea977cf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
+#define __ASM_MACH_LOONGSON64_IRQ_H_
+
+/* cpu core interrupt numbers */
+#define NR_IRQS_LEGACY          16
+#define NR_MIPS_CPU_IRQS        8
+#define NR_MAX_CHAINED_IRQS     40 /* Chained IRQs means those not directly used by devices */
+#define NR_IRQS                 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
+
+#define MIPS_CPU_IRQ_BASE       NR_IRQS_LEGACY
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
new file mode 100644
index 000000000..28572ddfb
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn)
+ * Copyright (C) 2012 Huacai Chen (chenhc@lemote.com)
+ */
+#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
+#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
+
+#include <asm/cpu.h>
+
+/*
+ * Override macros used in arch/mips/kernel/head.S.
+ */
+        .macro  kernel_entry_setup
+        .set    push
+        .set    mips64
+        /* Set LPA on LOONGSON3 config3 */
+        mfc0    t0, CP0_CONFIG3
+        or      t0, (0x1 << 7)
+        mtc0    t0, CP0_CONFIG3
+        /* Set ELPA on LOONGSON3 pagegrain */
+        mfc0    t0, CP0_PAGEGRAIN
+        or      t0, (0x1 << 29)
+        mtc0    t0, CP0_PAGEGRAIN
+        /* Enable STFill Buffer */
+        mfc0    t0, CP0_PRID
+        /* Loongson-3A R4+ */
+        andi    t1, t0, PRID_IMP_MASK
+        li      t2, PRID_IMP_LOONGSON_64G
+        beq     t1, t2, 1f
+        nop
+        /* Loongson-3A R2/R3 */
+        andi    t0, (PRID_IMP_MASK | PRID_REV_MASK)
+        slti    t0, t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
+        bnez    t0, 2f
+        nop
+1:
+        mfc0    t0, CP0_CONFIG6
+        or      t0, 0x100
+        mtc0    t0, CP0_CONFIG6
+2:
+        _ehb
+        .set    pop
+        .endm
+
+/*
+ * Do SMP slave processor setup.
+ */
+        .macro  smp_slave_setup
+        .set    push
+        .set    mips64
+        /* Set LPA on LOONGSON3 config3 */
+        mfc0    t0, CP0_CONFIG3
+        or      t0, (0x1 << 7)
+        mtc0    t0, CP0_CONFIG3
+        /* Set ELPA on LOONGSON3 pagegrain */
+        mfc0    t0, CP0_PAGEGRAIN
+        or      t0, (0x1 << 29)
+        mtc0    t0, CP0_PAGEGRAIN
+        /* Enable STFill Buffer */
+        mfc0    t0, CP0_PRID
+        /* Loongson-3A R4+ */
+        andi    t1, t0, PRID_IMP_MASK
+        li      t2, PRID_IMP_LOONGSON_64G
+        beq     t1, t2, 1f
+        nop
+        /* Loongson-3A R2/R3 */
+        andi    t0, (PRID_IMP_MASK | PRID_REV_MASK)
+        slti    t0, t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)
+        bnez    t0, 2f
+        nop
+1:
+        mfc0    t0, CP0_CONFIG6
+        or      t0, 0x100
+        mtc0    t0, CP0_CONFIG6
+2:
+        _ehb
+        .set    pop
+        .endm
+
+#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
new file mode 100644
index 000000000..fde1b75c4
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
+#define __ASM_MACH_LOONGSON64_LOONGSON_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <boot_param.h>
+
+
+/* machine-specific reboot/halt operation */
+extern void mach_prepare_reboot(void);
+extern void mach_prepare_shutdown(void);
+
+/* environment arguments from bootloader */
+extern u32 cpu_clock_freq;
+extern u32 memsize, highmemsize;
+extern const struct plat_smp_ops loongson3_smp_ops;
+
+/* loongson-specific command line, env and memory initialization */
+extern void __init prom_init_memory(void);
+extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
+
+/* irq operation functions */
+extern void mach_irq_dispatch(unsigned int pending);
+extern int mach_i8259_irq(void);
+
+/* We need this in some places... */
+#define delay() ({              \
+        int x;                          \
+        for (x = 0; x < 100000; x++)    \
+                __asm__ __volatile__(""); \
+})
+
+#define LOONGSON_REG(x) \
+        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON3_REG8(base, x) \
+        (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
+
+#define LOONGSON3_REG32(base, x) \
+        (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
+
+#define LOONGSON_FLASH_BASE     0x1c000000
+#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
+#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
+
+#define LOONGSON_LIO0_BASE      0x1e000000
+#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
+#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
+
+#define LOONGSON_BOOT_BASE      0x1fc00000
+#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
+#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE       0x1fe00000
+#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+/* Loongson-3 specific registers */
+#define LOONGSON3_REG_BASE      0x3ff00000
+#define LOONGSON3_REG_SIZE      0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON3_REG_TOP       (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
+
+#define LOONGSON_LIO1_BASE      0x1ff00000
+#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
+#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
+
+#define LOONGSON_PCILO0_BASE    0x10000000
+#define LOONGSON_PCILO1_BASE    0x14000000
+#define LOONGSON_PCILO2_BASE    0x18000000
+#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
+#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
+#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
+
+#define LOONGSON_PCICFG_BASE    0x1fe80000
+#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
+#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+
+#define LOONGSON_PCIIO_BASE     loongson_sysconf.pci_io_base
+
+#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
+#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+
+/* Loongson Register Bases */
+
+#define LOONGSON_PCICONFIGBASE  0x00
+#define LOONGSON_REGBASE        0x100
+
+/* PCI Configuration Registers */
+
+#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
+#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
+#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
+#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
+#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
+#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
+
+#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
+
+#define LOONGSON_PCICMD_PERR_CLR        0x80000000
+#define LOONGSON_PCICMD_SERR_CLR        0x40000000
+#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
+#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
+#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
+#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
+#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
+#define LOONGSON_PCICMD_ASTEPEN         0x00000080
+#define LOONGSON_PCICMD_SERREN          0x00000100
+#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
+
+/* Loongson h/w Configuration */
+
+#define LOONGSON_GENCFG_OFFSET          0x4
+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+
+#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
+#define LOONGSON_GENCFG_SNOOPEN         0x00000002
+#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
+
+#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
+#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
+#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
+#define LOONGSON_GENCFG_BYTESWAP        0x00000040
+
+#define LOONGSON_GENCFG_UNCACHED        0x00000080
+#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
+#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
+#define LOONGSON_GENCFG_CACHEALG        0x00000c00
+#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
+#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
+#define LOONGSON_GENCFG_CACHESTOP       0x00002000
+#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
+#define LOONGSON_GENCFG_BUSERREN        0x00008000
+#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
+
+/* PCI address map control */
+
+#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
+#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
+#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
+
+/* GPIO Regs - r/w */
+
+#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
+/* ICU */
+#define LOONGSON_ICU_MBOXES             0x0000000f
+#define LOONGSON_ICU_MBOXES_SHIFT       0
+#define LOONGSON_ICU_DMARDY             0x00000010
+#define LOONGSON_ICU_DMAEMPTY           0x00000020
+#define LOONGSON_ICU_COPYRDY            0x00000040
+#define LOONGSON_ICU_COPYEMPTY          0x00000080
+#define LOONGSON_ICU_COPYERR            0x00000100
+#define LOONGSON_ICU_PCIIRQ             0x00000200
+#define LOONGSON_ICU_MASTERERR          0x00000400
+#define LOONGSON_ICU_SYSTEMERR          0x00000800
+#define LOONGSON_ICU_DRAMPERR           0x00001000
+#define LOONGSON_ICU_RETRYERR           0x00002000
+#define LOONGSON_ICU_GPIOS              0x01ff0000
+#define LOONGSON_ICU_GPIOS_SHIFT                16
+#define LOONGSON_ICU_GPINS              0x7e000000
+#define LOONGSON_ICU_GPINS_SHIFT                25
+#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
+#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
+#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
+
+/* PCI prefetch window base & mask */
+
+#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
+
+/* PCI_Hit*_Sel_* */
+
+#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
+#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
+#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
+#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
+#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
+#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
+
+/* PXArb Config & Status */
+
+#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
+#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+
+#define MAX_PACKAGES 4
+
+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
+extern u64 loongson_chipcfg[MAX_PACKAGES];
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
+
+/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
+extern u64 loongson_chiptemp[MAX_PACKAGES];
+#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
+
+/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
+extern u64 loongson_freqctrl[MAX_PACKAGES];
+#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
+
+/* pcimap */
+
+#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
+#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
+#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
+#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
+#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
+        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
new file mode 100644
index 000000000..545f91f2a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LOONGSON_HWMON_H_
+#define __LOONGSON_HWMON_H_
+
+#include <linux/types.h>
+
+#define MIN_TEMP        0
+#define MAX_TEMP        255
+#define NOT_VALID_TEMP  999
+
+typedef int (*get_temp_fun)(int);
+extern int loongson3_cpu_temp(int);
+
+/* 0:Max speed, 1:Manual, 2:Auto */
+enum fan_control_mode {
+        FAN_FULL_MODE = 0,
+        FAN_MANUAL_MODE = 1,
+        FAN_AUTO_MODE = 2,
+        FAN_MODE_END
+};
+
+struct temp_range {
+        u8 low;
+        u8 high;
+        u8 level;
+};
+
+#define CONSTANT_SPEED_POLICY   0  /* at constant speed */
+#define STEP_SPEED_POLICY       1  /* use up/down arrays to describe policy */
+#define KERNEL_HELPER_POLICY    2  /* kernel as a helper to fan control */
+
+#define MAX_STEP_NUM    16
+#define MAX_FAN_LEVEL   255
+
+/* loongson_fan_policy works when fan work at FAN_AUTO_MODE */
+struct loongson_fan_policy {
+        u8      type;
+
+        /* percent only used when type is CONSTANT_SPEED_POLICY */
+        u8      percent;
+
+        /* period between two check. (Unit: S) */
+        u8      adjust_period;
+
+        /* fan adjust usually depend on a temprature input */
+        get_temp_fun    depend_temp;
+
+        /* up_step/down_step used when type is STEP_SPEED_POLICY */
+        u8      up_step_num;
+        u8      down_step_num;
+        struct temp_range up_step[MAX_STEP_NUM];
+        struct temp_range down_step[MAX_STEP_NUM];
+        struct delayed_work work;
+};
+
+#endif /* __LOONGSON_HWMON_H_*/
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
new file mode 100644
index 000000000..83dbb9fdf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
@@ -0,0 +1,246 @@
+/*
+ * Read/Write Loongson Extension Registers
+ */
+
+#ifndef _LOONGSON_REGS_H_
+#define _LOONGSON_REGS_H_
+
+#include <linux/types.h>
+#include <linux/bits.h>
+
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+
+static inline bool cpu_has_cfg(void)
+{
+        return ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G);
+}
+
+static inline u32 read_cpucfg(u32 reg)
+{
+        u32 __res;
+
+        __asm__ __volatile__(
+                "parse_r __res,%0\n\t"
+                "parse_r reg,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
+                :"=r"(__res)
+                :"r"(reg)
+                :
+                );
+        return __res;
+}
+
+/* Bit Domains for CFG registers */
+#define LOONGSON_CFG0   0x0
+#define LOONGSON_CFG0_PRID GENMASK(31, 0)
+
+#define LOONGSON_CFG1 0x1
+#define LOONGSON_CFG1_FP        BIT(0)
+#define LOONGSON_CFG1_FPREV     GENMASK(3, 1)
+#define LOONGSON_CFG1_MMI       BIT(4)
+#define LOONGSON_CFG1_MSA1      BIT(5)
+#define LOONGSON_CFG1_MSA2      BIT(6)
+#define LOONGSON_CFG1_CGP       BIT(7)
+#define LOONGSON_CFG1_WRP       BIT(8)
+#define LOONGSON_CFG1_LSX1      BIT(9)
+#define LOONGSON_CFG1_LSX2      BIT(10)
+#define LOONGSON_CFG1_LASX      BIT(11)
+#define LOONGSON_CFG1_R6FXP     BIT(12)
+#define LOONGSON_CFG1_R6CRCP    BIT(13)
+#define LOONGSON_CFG1_R6FPP     BIT(14)
+#define LOONGSON_CFG1_CNT64     BIT(15)
+#define LOONGSON_CFG1_LSLDR0    BIT(16)
+#define LOONGSON_CFG1_LSPREF    BIT(17)
+#define LOONGSON_CFG1_LSPREFX   BIT(18)
+#define LOONGSON_CFG1_LSSYNCI   BIT(19)
+#define LOONGSON_CFG1_LSUCA     BIT(20)
+#define LOONGSON_CFG1_LLSYNC    BIT(21)
+#define LOONGSON_CFG1_TGTSYNC   BIT(22)
+#define LOONGSON_CFG1_LLEXC     BIT(23)
+#define LOONGSON_CFG1_SCRAND    BIT(24)
+#define LOONGSON_CFG1_MUALP     BIT(25)
+#define LOONGSON_CFG1_KMUALEN   BIT(26)
+#define LOONGSON_CFG1_ITLBT     BIT(27)
+#define LOONGSON_CFG1_LSUPERF   BIT(28)
+#define LOONGSON_CFG1_SFBP      BIT(29)
+#define LOONGSON_CFG1_CDMAP     BIT(30)
+
+#define LOONGSON_CFG1_FPREV_OFFSET      1
+
+#define LOONGSON_CFG2 0x2
+#define LOONGSON_CFG2_LEXT1     BIT(0)
+#define LOONGSON_CFG2_LEXT2     BIT(1)
+#define LOONGSON_CFG2_LEXT3     BIT(2)
+#define LOONGSON_CFG2_LSPW      BIT(3)
+#define LOONGSON_CFG2_LBT1      BIT(4)
+#define LOONGSON_CFG2_LBT2      BIT(5)
+#define LOONGSON_CFG2_LBT3      BIT(6)
+#define LOONGSON_CFG2_LBTMMU    BIT(7)
+#define LOONGSON_CFG2_LPMP      BIT(8)
+#define LOONGSON_CFG2_LPMREV    GENMASK(11, 9)
+#define LOONGSON_CFG2_LAMO      BIT(12)
+#define LOONGSON_CFG2_LPIXU     BIT(13)
+#define LOONGSON_CFG2_LPIXNU    BIT(14)
+#define LOONGSON_CFG2_LVZP      BIT(15)
+#define LOONGSON_CFG2_LVZREV    GENMASK(18, 16)
+#define LOONGSON_CFG2_LGFTP     BIT(19)
+#define LOONGSON_CFG2_LGFTPREV  GENMASK(22, 20)
+#define LOONGSON_CFG2_LLFTP     BIT(23)
+#define LOONGSON_CFG2_LLFTPREV  GENMASK(26, 24)
+#define LOONGSON_CFG2_LCSRP     BIT(27)
+#define LOONGSON_CFG2_LDISBLIKELY       BIT(28)
+
+#define LOONGSON_CFG2_LPMREV_OFFSET     9
+#define LOONGSON_CFG2_LPM_REV1          (1 << LOONGSON_CFG2_LPMREV_OFFSET)
+#define LOONGSON_CFG2_LPM_REV2          (2 << LOONGSON_CFG2_LPMREV_OFFSET)
+#define LOONGSON_CFG2_LVZREV_OFFSET     16
+#define LOONGSON_CFG2_LVZ_REV1          (1 << LOONGSON_CFG2_LVZREV_OFFSET)
+#define LOONGSON_CFG2_LVZ_REV2          (2 << LOONGSON_CFG2_LVZREV_OFFSET)
+
+#define LOONGSON_CFG3 0x3
+#define LOONGSON_CFG3_LCAMP     BIT(0)
+#define LOONGSON_CFG3_LCAMREV   GENMASK(3, 1)
+#define LOONGSON_CFG3_LCAMNUM   GENMASK(11, 4)
+#define LOONGSON_CFG3_LCAMKW    GENMASK(19, 12)
+#define LOONGSON_CFG3_LCAMVW    GENMASK(27, 20)
+
+#define LOONGSON_CFG3_LCAMREV_OFFSET    1
+#define LOONGSON_CFG3_LCAM_REV1         (1 << LOONGSON_CFG3_LCAMREV_OFFSET)
+#define LOONGSON_CFG3_LCAM_REV2         (2 << LOONGSON_CFG3_LCAMREV_OFFSET)
+#define LOONGSON_CFG3_LCAMNUM_OFFSET    4
+#define LOONGSON_CFG3_LCAMNUM_REV1      (0x3f << LOONGSON_CFG3_LCAMNUM_OFFSET)
+#define LOONGSON_CFG3_LCAMKW_OFFSET     12
+#define LOONGSON_CFG3_LCAMKW_REV1       (0x27 << LOONGSON_CFG3_LCAMKW_OFFSET)
+#define LOONGSON_CFG3_LCAMVW_OFFSET     20
+#define LOONGSON_CFG3_LCAMVW_REV1       (0x3f << LOONGSON_CFG3_LCAMVW_OFFSET)
+
+#define LOONGSON_CFG4 0x4
+#define LOONGSON_CFG4_CCFREQ    GENMASK(31, 0)
+
+#define LOONGSON_CFG5 0x5
+#define LOONGSON_CFG5_CFM       GENMASK(15, 0)
+#define LOONGSON_CFG5_CFD       GENMASK(31, 16)
+
+#define LOONGSON_CFG6 0x6
+
+#define LOONGSON_CFG7 0x7
+#define LOONGSON_CFG7_GCCAEQRP  BIT(0)
+#define LOONGSON_CFG7_UCAWINP   BIT(1)
+
+static inline bool cpu_has_csr(void)
+{
+        if (cpu_has_cfg())
+                return (read_cpucfg(LOONGSON_CFG2) & LOONGSON_CFG2_LCSRP);
+
+        return false;
+}
+
+static inline u32 csr_readl(u32 reg)
+{
+        u32 __res;
+
+        /* RDCSR reg, val */
+        __asm__ __volatile__(
+                "parse_r __res,%0\n\t"
+                "parse_r reg,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t"
+                :"=r"(__res)
+                :"r"(reg)
+                :
+                );
+        return __res;
+}
+
+static inline u64 csr_readq(u32 reg)
+{
+        u64 __res;
+
+        /* DRDCSR reg, val */
+        __asm__ __volatile__(
+                "parse_r __res,%0\n\t"
+                "parse_r reg,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t"
+                :"=r"(__res)
+                :"r"(reg)
+                :
+                );
+        return __res;
+}
+
+static inline void csr_writel(u32 val, u32 reg)
+{
+        /* WRCSR reg, val */
+        __asm__ __volatile__(
+                "parse_r reg,%0\n\t"
+                "parse_r val,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8010118 | (reg << 21) | (val << 11))\n\t"
+                :
+                :"r"(reg),"r"(val)
+                :
+                );
+}
+
+static inline void csr_writeq(u64 val, u32 reg)
+{
+        /* DWRCSR reg, val */
+        __asm__ __volatile__(
+                "parse_r reg,%0\n\t"
+                "parse_r val,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8030118 | (reg << 21) | (val << 11))\n\t"
+                :
+                :"r"(reg),"r"(val)
+                :
+                );
+}
+
+/* Public CSR Register can also be accessed with regular addresses */
+#define CSR_PUBLIC_MMIO_BASE 0x1fe00000
+
+#define MMIO_CSR(x)             (void *)TO_UNCAC(CSR_PUBLIC_MMIO_BASE + x)
+
+#define LOONGSON_CSR_FEATURES   0x8
+#define LOONGSON_CSRF_TEMP      BIT(0)
+#define LOONGSON_CSRF_NODECNT   BIT(1)
+#define LOONGSON_CSRF_MSI       BIT(2)
+#define LOONGSON_CSRF_EXTIOI    BIT(3)
+#define LOONGSON_CSRF_IPI       BIT(4)
+#define LOONGSON_CSRF_FREQ      BIT(5)
+
+#define LOONGSON_CSR_VENDOR     0x10 /* Vendor name string, should be "Loongson" */
+#define LOONGSON_CSR_CPUNAME    0x20 /* Processor name string */
+#define LOONGSON_CSR_NODECNT    0x408
+#define LOONGSON_CSR_CPUTEMP    0x428
+
+/* PerCore CSR, only accessable by local cores */
+#define LOONGSON_CSR_IPI_STATUS 0x1000
+#define LOONGSON_CSR_IPI_EN     0x1004
+#define LOONGSON_CSR_IPI_SET    0x1008
+#define LOONGSON_CSR_IPI_CLEAR  0x100c
+#define LOONGSON_CSR_IPI_SEND   0x1040
+#define CSR_IPI_SEND_IP_SHIFT   0
+#define CSR_IPI_SEND_CPU_SHIFT  16
+#define CSR_IPI_SEND_BLOCK      BIT(31)
+
+static inline u64 drdtime(void)
+{
+        int rID = 0;
+        u64 val = 0;
+
+        __asm__ __volatile__(
+                "parse_r rID,%0\n\t"
+                "parse_r val,%1\n\t"
+                ".insn \n\t"
+                ".word (0xc8090118 | (rID << 21) | (val << 11))\n\t"
+                :"=r"(rID),"=r"(val)
+                :
+                );
+        return val;
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h
new file mode 100644
index 000000000..ebb1deaa7
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/mmzone.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
+ *                    Institute of Computing Technology
+ * Author:  Xiang Gao, gaoxiang@ict.ac.cn
+ *          Huacai Chen, chenhc@lemote.com
+ *          Xiaofu Meng, Shuangshuang Zhang
+ */
+#ifndef _ASM_MACH_LOONGSON64_MMZONE_H
+#define _ASM_MACH_LOONGSON64_MMZONE_H
+
+#define NODE_ADDRSPACE_SHIFT 44
+
+#define pa_to_nid(addr)  (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
+#define nid_to_addrbase(nid) ((unsigned long)(nid) << NODE_ADDRSPACE_SHIFT)
+
+extern struct pglist_data *__node_data[];
+
+#define NODE_DATA(n)            (__node_data[n])
+
+extern void setup_zero_pages(void);
+extern void __init prom_init_numa_memory(void);
+
+#endif /* _ASM_MACH_MMZONE_H */
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
new file mode 100644
index 000000000..8b59d64a2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
+ * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_PCI_H_
+#define __ASM_MACH_LOONGSON64_PCI_H_
+
+extern struct pci_ops loongson_pci_ops;
+
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START   0x00004000UL
+
+#define LOONGSON_PCI_MEM_START  0x40000000UL
+#define LOONGSON_PCI_MEM_END    0x7effffffUL
+
+
+#endif /* !__ASM_MACH_LOONGSON64_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/spaces.h b/arch/mips/include/asm/mach-loongson64/spaces.h
new file mode 100644
index 000000000..ce04e998a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/spaces.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON64_SPACES_H_
+#define __ASM_MACH_LOONGSON64_SPACES_H_
+
+#if defined(CONFIG_64BIT)
+#define CAC_BASE        _AC(0x9800000000000000, UL)
+#endif /* CONFIG_64BIT */
+
+/* Skip 128k to trap NULL pointer dereferences */
+#define PCI_IOBASE      _AC(0xc000000000000000 + SZ_128K, UL)
+#define PCI_IOSIZE      SZ_16M
+#define MAP_BASE        (PCI_IOBASE + PCI_IOSIZE)
+
+#define IO_SPACE_LIMIT  (PCI_IOSIZE - 1)
+
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/topology.h b/arch/mips/include/asm/mach-loongson64/topology.h
new file mode 100644
index 000000000..3414a1fd1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/topology.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MACH_TOPOLOGY_H
+#define _ASM_MACH_TOPOLOGY_H
+
+#ifdef CONFIG_NUMA
+
+#define cpu_to_node(cpu)        (cpu_logical_map(cpu) >> 2)
+
+extern cpumask_t __node_cpumask[];
+#define cpumask_of_node(node)   (&__node_cpumask[node])
+
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *);
+
+#define cpumask_of_pcibus(bus)  (cpu_online_mask)
+
+extern unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
+
+#define node_distance(from, to) (__node_distances[(from)][(to)])
+
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-loongson64/workarounds.h b/arch/mips/include/asm/mach-loongson64/workarounds.h
new file mode 100644
index 000000000..17b71172a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/workarounds.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
+#define __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
+
+#define WORKAROUND_CPUFREQ      0x00000001
+#define WORKAROUND_CPUHOTPLUG   0x00000002
+
+#endif
diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
new file mode 100644
index 000000000..de3b66a37
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_clo_clz         1
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_clo_clz         1
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
new file mode 100644
index 000000000..e1bd4298b
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
new file mode 100644
index 000000000..ab03eb3fa
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -0,0 +1,145 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+        /*
+         * Prepare segments for EVA boot:
+         *
+         * This is in case the processor boots in legacy configuration
+         * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
+         *
+         * ========================= Mappings =============================
+         * Virtual memory           Physical memory           Mapping
+         * 0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
+         *                          Flat 2GB physical memory
+         *
+         * 0x80000000 - 0x9fffffff  0x00000000 - 0x1ffffffff   MUSUK (kseg0)
+         * 0xa0000000 - 0xbf000000  0x00000000 - 0x1ffffffff   MUSUK (kseg1)
+         * 0xc0000000 - 0xdfffffff             -                 MK  (kseg2)
+         * 0xe0000000 - 0xffffffff             -                 MK  (kseg3)
+         *
+         *
+         * Lowmem is expanded to 2GB
+         *
+         * The following code uses the t0, t1, t2 and ra registers without
+         * previously preserving them.
+         *
+         */
+        .macro  platform_eva_init
+
+        .set    push
+        .set    reorder
+        /*
+         * Get Config.K0 value and use it to program
+         * the segmentation registers
+         */
+        mfc0    t1, CP0_CONFIG
+        andi    t1, 0x7 /* CCA */
+        move    t2, t1
+        ins     t2, t1, 16, 3
+        /* SegCtl0 */
+        li      t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |            \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        or      t0, t2
+        mtc0    t0, CP0_SEGCTL0
+
+        /* SegCtl1 */
+        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (2 << MIPS_SEGCFG_C_SHIFT) |                            \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        ins     t0, t1, 16, 3
+        mtc0    t0, CP0_SEGCTL1
+
+        /* SegCtl2 */
+        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
+                (6 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (4 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        or      t0, t2
+        mtc0    t0, CP0_SEGCTL2
+
+        jal     mips_ihb
+        mfc0    t0, $16, 5
+        li      t2, 0x40000000      /* K bit */
+        or      t0, t0, t2
+        mtc0    t0, $16, 5
+        sync
+        jal     mips_ihb
+
+        .set    pop
+        .endm
+
+        .macro  kernel_entry_setup
+
+#ifdef CONFIG_EVA
+        sync
+        ehb
+
+        mfc0    t1, CP0_CONFIG
+        bgez    t1, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        sll     t0, t0, 6   /* SC bit */
+        bgez    t0, 9f
+
+        platform_eva_init
+        b       0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonsc_processor
+        jal     v0
+
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+
+1:      b       1b
+        nop
+        __INITDATA
+nonsc_processor:
+        .asciz  "EVA kernel requires a MIPS core with Segment Control implemented\n"
+        __FINIT
+#endif /* CONFIG_EVA */
+0:
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+#ifdef CONFIG_EVA
+        sync
+        ehb
+        platform_eva_init
+#endif
+        .endm
+
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h
new file mode 100644
index 000000000..b9dee7c3e
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+
+#define MIPS_GT_BASE    0x1be00000
+
+extern unsigned long _pcictrl_gt64120;
+/*
+ *   GT64120 config space base address
+ */
+#define GT64120_BASE    _pcictrl_gt64120
+
+#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/arch/mips/include/asm/mach-malta/mc146818rtc.h b/arch/mips/include/asm/mach-malta/mc146818rtc.h
new file mode 100644
index 000000000..e8cc7fdf7
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mc146818rtc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2003 by Ralf Baechle
+ *
+ * RTC routines for Malta style attached PIIX4 device, which contains a
+ * Motorola MC146818A-compatible Real Time Clock.
+ */
+#ifndef __ASM_MACH_MALTA_MC146818RTC_H
+#define __ASM_MACH_MALTA_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/malta.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        return inb(MALTA_RTC_DAT_REG);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        outb(data, MALTA_RTC_DAT_REG);
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+
+#endif /* __ASM_MACH_MALTA_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-malta/spaces.h b/arch/mips/include/asm/mach-malta/spaces.h
new file mode 100644
index 000000000..d7e54971e
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/spaces.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+
+#ifndef _ASM_MALTA_SPACES_H
+#define _ASM_MALTA_SPACES_H
+
+#ifdef CONFIG_EVA
+
+/*
+ * Traditional Malta Board Memory Map for EVA
+ *
+ * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
+ * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
+ * 0x1c000000 - 0x1fffffff: I/O And Flash
+ * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
+ * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
+ *
+ * The kernel is still located in 0x80000000(kseg0). However,
+ * the physical mask has been shifted to 0x80000000 which exploits the alias
+ * on the Malta board. As a result of which, we override the __pa_symbol
+ * to peform direct mapping from virtual to physical addresses. In other
+ * words, the 0x80000000 virtual address maps to 0x80000000 physical address
+ * which in turn aliases to 0x0. We do this in order to be able to use a flat
+ * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
+ * 0x10000000 - 0x1fffffff.
+ * The last 64KB of physical memory are reserved for correct HIGHMEM
+ * macros arithmetics.
+ *
+ */
+
+#define PAGE_OFFSET     _AC(0x0, UL)
+#define PHYS_OFFSET     _AC(0x80000000, UL)
+#define HIGHMEM_START   _AC(0xffff0000, UL)
+
+#define __pa_symbol(x)  (RELOC_HIDE((unsigned long)(x), 0))
+
+#endif /* CONFIG_EVA */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MALTA_SPACES_H */
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
new file mode 100644
index 000000000..0c29ff820
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -0,0 +1,57 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_counter         1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          1
+#define cpu_has_ejtag           1
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   1
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_icache_snoops_remote_store  1
+
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips64r1        1
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal       0
+#define cpu_has_dc_aliases      0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r2        0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal       1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r2        1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
+#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
new file mode 100644
index 000000000..c0dbd530c
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems.
+ */
+#ifndef __ASM_NETLOGIC_IRQ_H
+#define __ASM_NETLOGIC_IRQ_H
+
+#include <asm/mach-netlogic/multi-node.h>
+#define NLM_IRQS_PER_NODE       1024
+#define NR_IRQS                 (NLM_IRQS_PER_NODE * NLM_NR_NODES)
+
+#define MIPS_CPU_IRQ_BASE       0
+
+#endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
new file mode 100644
index 000000000..8bdf47e29
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NETLOGIC_MULTI_NODE_H_
+#define _NETLOGIC_MULTI_NODE_H_
+
+#ifndef CONFIG_NLM_MULTINODE
+#define NLM_NR_NODES            1
+#else
+#if defined(CONFIG_NLM_MULTINODE_2)
+#define NLM_NR_NODES            2
+#elif defined(CONFIG_NLM_MULTINODE_4)
+#define NLM_NR_NODES            4
+#else
+#define NLM_NR_NODES            1
+#endif
+#endif
+
+#define NLM_THREADS_PER_CORE    4
+
+struct nlm_soc_info {
+        unsigned long   coremask;       /* cores enabled on the soc */
+        unsigned long   ebase;          /* not used now */
+        uint64_t        irqmask;        /* EIMR for the node */
+        uint64_t        sysbase;        /* only for XLP - sys block base */
+        uint64_t        picbase;        /* PIC block base */
+        spinlock_t      piclock;        /* lock for PIC access */
+        cpumask_t       cpumask;        /* logical cpu mask for node */
+        unsigned int    socbus;
+};
+
+extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
+#define nlm_get_node(i)         (&nlm_nodes[i])
+#define nlm_node_present(n)     ((n) >= 0 && (n) < NLM_NR_NODES && \
+                                        nlm_get_node(n)->coremask != 0)
+#ifdef CONFIG_CPU_XLR
+#define nlm_current_node()      (&nlm_nodes[0])
+#else
+#define nlm_current_node()      (&nlm_nodes[nlm_nodeid()])
+#endif
+void nlm_node_init(int node);
+
+#endif
diff --git a/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h
new file mode 100644
index 000000000..468230834
--- /dev/null
+++ b/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h
@@ -0,0 +1,32 @@
+/*
+ * Joshua Henderson <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * CPU feature overrides for PIC32 boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_vint            1
+#define cpu_has_veic            0
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_fpu             0
+#define cpu_has_counter         1
+#define cpu_has_llsc            1
+#define cpu_has_nofpuex         0
+#define cpu_icache_snoops_remote_store 1
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#error This platform does not support 64bit.
+#endif
+
+#endif /* __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-pic32/irq.h b/arch/mips/include/asm/mach-pic32/irq.h
new file mode 100644
index 000000000..ddaf999bc
--- /dev/null
+++ b/arch/mips/include/asm/mach-pic32/irq.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Joshua Henderson <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ */
+#ifndef __ASM_MACH_PIC32_IRQ_H
+#define __ASM_MACH_PIC32_IRQ_H
+
+#define NR_IRQS 256
+#define MIPS_CPU_IRQ_BASE 0
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_PIC32_IRQ_H */
diff --git a/arch/mips/include/asm/mach-pic32/pic32.h b/arch/mips/include/asm/mach-pic32/pic32.h
new file mode 100644
index 000000000..53918a671
--- /dev/null
+++ b/arch/mips/include/asm/mach-pic32/pic32.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Joshua Henderson <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ */
+#ifndef _ASM_MACH_PIC32_H
+#define _ASM_MACH_PIC32_H
+
+#include <linux/io.h>
+
+/*
+ * PIC32 register offsets for SET/CLR/INV where supported.
+ */
+#define PIC32_CLR(_reg)         ((_reg) + 0x04)
+#define PIC32_SET(_reg)         ((_reg) + 0x08)
+#define PIC32_INV(_reg)         ((_reg) + 0x0C)
+
+/*
+ * PIC32 Base Register Offsets
+ */
+#define PIC32_BASE_CONFIG       0x1f800000
+#define PIC32_BASE_OSC          0x1f801200
+#define PIC32_BASE_RESET        0x1f801240
+#define PIC32_BASE_PPS          0x1f801400
+#define PIC32_BASE_UART         0x1f822000
+#define PIC32_BASE_PORT         0x1f860000
+#define PIC32_BASE_DEVCFG2      0x1fc4ff44
+
+/*
+ * Register unlock sequence required for some register access.
+ */
+void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
+#define pic32_syskey_unlock()   \
+        pic32_syskey_unlock_debug(__func__, __LINE__)
+
+#endif /* _ASM_MACH_PIC32_H */
diff --git a/arch/mips/include/asm/mach-pic32/spaces.h b/arch/mips/include/asm/mach-pic32/spaces.h
new file mode 100644
index 000000000..eb557b52c
--- /dev/null
+++ b/arch/mips/include/asm/mach-pic32/spaces.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Joshua Henderson <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ */
+#ifndef _ASM_MACH_PIC32_SPACES_H
+#define _ASM_MACH_PIC32_SPACES_H
+
+#ifdef CONFIG_PIC32MZDA
+#define PHYS_OFFSET     _AC(0x08000000, UL)
+#endif
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_MACH_PIC32_SPACES_H */
diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h
new file mode 100644
index 000000000..74ac01650
--- /dev/null
+++ b/arch/mips/include/asm/mach-pistachio/irq.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Pistachio IRQ setup
+ *
+ * Copyright (C) 2014 Google, Inc.
+ */
+
+#ifndef __ASM_MACH_PISTACHIO_IRQ_H
+#define __ASM_MACH_PISTACHIO_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_PISTACHIO_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h
new file mode 100644
index 000000000..2262243d1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/irq.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_RALINK_IRQ_H
+#define __ASM_MACH_RALINK_IRQ_H
+
+#define GIC_NUM_INTRS   64
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
new file mode 100644
index 000000000..757ce53d0
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _MT7620_REGS_H_
+#define _MT7620_REGS_H_
+
+#define MT7620_SYSC_BASE                0x10000000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_EFUSE_CFG              0x08
+#define SYSC_REG_CHIP_REV               0x0c
+#define SYSC_REG_SYSTEM_CONFIG0         0x10
+#define SYSC_REG_SYSTEM_CONFIG1         0x14
+#define SYSC_REG_CLKCFG0                0x2c
+#define SYSC_REG_CPU_SYS_CLKCFG         0x3c
+#define SYSC_REG_CPLL_CONFIG0           0x54
+#define SYSC_REG_CPLL_CONFIG1           0x58
+
+#define MT7620_CHIP_NAME0               0x3637544d
+#define MT7620_CHIP_NAME1               0x20203032
+#define MT7628_CHIP_NAME1               0x20203832
+
+#define SYSCFG0_XTAL_FREQ_SEL           BIT(6)
+
+#define CHIP_REV_PKG_MASK               0x1
+#define CHIP_REV_PKG_SHIFT              16
+#define CHIP_REV_VER_MASK               0xf
+#define CHIP_REV_VER_SHIFT              8
+#define CHIP_REV_ECO_MASK               0xf
+
+#define CLKCFG0_PERI_CLK_SEL            BIT(4)
+
+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT  16
+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK   0xf
+#define CPU_SYS_CLKCFG_OCP_RATIO_1      0       /* 1:1   (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5    1       /* 1:1.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_2      2       /* 1:2   */
+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5    3       /* 1:2.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_3      4       /* 1:3   */
+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5    5       /* 1:3.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_4      6       /* 1:4   */
+#define CPU_SYS_CLKCFG_OCP_RATIO_5      7       /* 1:5   */
+#define CPU_SYS_CLKCFG_OCP_RATIO_10     8       /* 1:10  */
+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT   8
+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK    0x1f
+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT  0
+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK   0x1f
+
+#define CPLL_CFG0_SW_CFG                BIT(31)
+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT  16
+#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
+#define CPLL_CFG0_LC_CURFCK             BIT(15)
+#define CPLL_CFG0_BYPASS_REF_CLK        BIT(14)
+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT   10
+#define CPLL_CFG0_PLL_DIV_RATIO_MASK    0x3
+
+#define CPLL_CFG1_CPU_AUX1              BIT(25)
+#define CPLL_CFG1_CPU_AUX0              BIT(24)
+
+#define SYSCFG0_DRAM_TYPE_MASK          0x3
+#define SYSCFG0_DRAM_TYPE_SHIFT         4
+#define SYSCFG0_DRAM_TYPE_SDRAM         0
+#define SYSCFG0_DRAM_TYPE_DDR1          1
+#define SYSCFG0_DRAM_TYPE_DDR2          2
+#define SYSCFG0_DRAM_TYPE_UNKNOWN       3
+
+#define SYSCFG0_DRAM_TYPE_DDR2_MT7628   0
+#define SYSCFG0_DRAM_TYPE_DDR1_MT7628   1
+
+#define MT7620_DRAM_BASE                0x0
+#define MT7620_SDRAM_SIZE_MIN           2
+#define MT7620_SDRAM_SIZE_MAX           64
+#define MT7620_DDR1_SIZE_MIN            32
+#define MT7620_DDR1_SIZE_MAX            128
+#define MT7620_DDR2_SIZE_MIN            32
+#define MT7620_DDR2_SIZE_MAX            256
+
+#define MT7620_GPIO_MODE_UART0_SHIFT    2
+#define MT7620_GPIO_MODE_UART0_MASK     0x7
+#define MT7620_GPIO_MODE_UART0(x)       ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
+#define MT7620_GPIO_MODE_UARTF          0x0
+#define MT7620_GPIO_MODE_PCM_UARTF      0x1
+#define MT7620_GPIO_MODE_PCM_I2S        0x2
+#define MT7620_GPIO_MODE_I2S_UARTF      0x3
+#define MT7620_GPIO_MODE_PCM_GPIO       0x4
+#define MT7620_GPIO_MODE_GPIO_UARTF     0x5
+#define MT7620_GPIO_MODE_GPIO_I2S       0x6
+#define MT7620_GPIO_MODE_GPIO           0x7
+
+#define MT7620_GPIO_MODE_NAND           0
+#define MT7620_GPIO_MODE_SD             1
+#define MT7620_GPIO_MODE_ND_SD_GPIO     2
+#define MT7620_GPIO_MODE_ND_SD_MASK     0x3
+#define MT7620_GPIO_MODE_ND_SD_SHIFT    18
+
+#define MT7620_GPIO_MODE_PCIE_RST       0
+#define MT7620_GPIO_MODE_PCIE_REF       1
+#define MT7620_GPIO_MODE_PCIE_GPIO      2
+#define MT7620_GPIO_MODE_PCIE_MASK      0x3
+#define MT7620_GPIO_MODE_PCIE_SHIFT     16
+
+#define MT7620_GPIO_MODE_WDT_RST        0
+#define MT7620_GPIO_MODE_WDT_REF        1
+#define MT7620_GPIO_MODE_WDT_GPIO       2
+#define MT7620_GPIO_MODE_WDT_MASK       0x3
+#define MT7620_GPIO_MODE_WDT_SHIFT      21
+
+#define MT7620_GPIO_MODE_MDIO           0
+#define MT7620_GPIO_MODE_MDIO_REFCLK    1
+#define MT7620_GPIO_MODE_MDIO_GPIO      2
+#define MT7620_GPIO_MODE_MDIO_MASK      0x3
+#define MT7620_GPIO_MODE_MDIO_SHIFT     7
+
+#define MT7620_GPIO_MODE_I2C            0
+#define MT7620_GPIO_MODE_UART1          5
+#define MT7620_GPIO_MODE_RGMII1         9
+#define MT7620_GPIO_MODE_RGMII2         10
+#define MT7620_GPIO_MODE_SPI            11
+#define MT7620_GPIO_MODE_SPI_REF_CLK    12
+#define MT7620_GPIO_MODE_WLED           13
+#define MT7620_GPIO_MODE_JTAG           15
+#define MT7620_GPIO_MODE_EPHY           15
+#define MT7620_GPIO_MODE_PA             20
+
+static inline int mt7620_get_eco(void)
+{
+        return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
new file mode 100644
index 000000000..c4579f170
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink MT7620 specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
+#define _MT7620_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             1
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
new file mode 100644
index 000000000..e1af1ba50
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Copyright (C) 2015 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _MT7621_REGS_H_
+#define _MT7621_REGS_H_
+
+#define MT7621_PALMBUS_BASE             0x1C000000
+#define MT7621_PALMBUS_SIZE             0x03FFFFFF
+
+#define MT7621_SYSC_BASE                0x1E000000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_CHIP_REV               0x0c
+#define SYSC_REG_SYSTEM_CONFIG0         0x10
+#define SYSC_REG_SYSTEM_CONFIG1         0x14
+
+#define CHIP_REV_PKG_MASK               0x1
+#define CHIP_REV_PKG_SHIFT              16
+#define CHIP_REV_VER_MASK               0xf
+#define CHIP_REV_VER_SHIFT              8
+#define CHIP_REV_ECO_MASK               0xf
+
+#define MT7621_DRAM_BASE                0x0
+#define MT7621_DDR2_SIZE_MIN            32
+#define MT7621_DDR2_SIZE_MAX            256
+
+#define MT7621_CHIP_NAME0               0x3637544D
+#define MT7621_CHIP_NAME1               0x20203132
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
new file mode 100644
index 000000000..168359a0a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink MT7621 specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
+#define _MT7621_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             1
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          1
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#define cpu_has_dc_aliases      0
+#define cpu_has_vtag_icache     0
+
+#define cpu_has_rixi            0
+#define cpu_has_tlbinv          0
+#define cpu_has_userlocal       1
+
+#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h
new file mode 100644
index 000000000..048309348
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Copyright (C) 2012 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _RT288X_PINMUX_H__
+#define _RT288X_PINMUX_H__
+
+#define FUNC(name, value, pin_first, pin_count) \
+        { name, value, pin_first, pin_count }
+
+#define GRP(_name, _func, _mask, _shift) \
+        { .name = _name, .mask = _mask, .shift = _shift, \
+          .func = _func, .gpio = _mask, \
+          .func_count = ARRAY_SIZE(_func) }
+
+#define GRP_G(_name, _func, _mask, _gpio, _shift) \
+        { .name = _name, .mask = _mask, .shift = _shift, \
+          .func = _func, .gpio = _gpio, \
+          .func_count = ARRAY_SIZE(_func) }
+
+struct rt2880_pmx_group;
+
+struct rt2880_pmx_func {
+        const char *name;
+        const char value;
+
+        int pin_first;
+        int pin_count;
+        int *pins;
+
+        int *groups;
+        int group_count;
+
+        int enabled;
+};
+
+struct rt2880_pmx_group {
+        const char *name;
+        int enabled;
+
+        const u32 shift;
+        const char mask;
+        const char gpio;
+
+        struct rt2880_pmx_func *func;
+        int func_count;
+};
+
+extern struct rt2880_pmx_group *rt2880_pinmux_data;
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
new file mode 100644
index 000000000..9dbd9f087
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  Ralink SoC register definitions
+ *
+ *  Copyright (C) 2013 John Crispin <john@phrozen.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ */
+
+#ifndef _RALINK_REGS_H_
+#define _RALINK_REGS_H_
+
+#include <linux/io.h>
+
+enum ralink_soc_type {
+        RALINK_UNKNOWN = 0,
+        RT2880_SOC,
+        RT3883_SOC,
+        RT305X_SOC_RT3050,
+        RT305X_SOC_RT3052,
+        RT305X_SOC_RT3350,
+        RT305X_SOC_RT3352,
+        RT305X_SOC_RT5350,
+        MT762X_SOC_MT7620A,
+        MT762X_SOC_MT7620N,
+        MT762X_SOC_MT7621AT,
+        MT762X_SOC_MT7628AN,
+        MT762X_SOC_MT7688,
+};
+extern enum ralink_soc_type ralink_soc;
+
+extern __iomem void *rt_sysc_membase;
+extern __iomem void *rt_memc_membase;
+
+static inline void rt_sysc_w32(u32 val, unsigned reg)
+{
+        __raw_writel(val, rt_sysc_membase + reg);
+}
+
+static inline u32 rt_sysc_r32(unsigned reg)
+{
+        return __raw_readl(rt_sysc_membase + reg);
+}
+
+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
+{
+        u32 val = rt_sysc_r32(reg) & ~clr;
+
+        __raw_writel(val | set, rt_sysc_membase + reg);
+}
+
+static inline void rt_memc_w32(u32 val, unsigned reg)
+{
+        __raw_writel(val, rt_memc_membase + reg);
+}
+
+static inline u32 rt_memc_r32(unsigned reg)
+{
+        return __raw_readl(rt_memc_membase + reg);
+}
+
+#endif /* _RALINK_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
new file mode 100644
index 000000000..5d10178f2
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _RT288X_REGS_H_
+#define _RT288X_REGS_H_
+
+#define RT2880_SYSC_BASE                0x00300000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_CHIP_ID                0x0c
+#define SYSC_REG_SYSTEM_CONFIG          0x10
+#define SYSC_REG_CLKCFG                 0x30
+
+#define RT2880_CHIP_NAME0               0x38325452
+#define RT2880_CHIP_NAME1               0x20203038
+
+#define CHIP_ID_ID_MASK                 0xff
+#define CHIP_ID_ID_SHIFT                8
+#define CHIP_ID_REV_MASK                0xff
+
+#define SYSTEM_CONFIG_CPUCLK_SHIFT      20
+#define SYSTEM_CONFIG_CPUCLK_MASK       0x3
+#define SYSTEM_CONFIG_CPUCLK_250        0x0
+#define SYSTEM_CONFIG_CPUCLK_266        0x1
+#define SYSTEM_CONFIG_CPUCLK_280        0x2
+#define SYSTEM_CONFIG_CPUCLK_300        0x3
+
+#define RT2880_GPIO_MODE_I2C            BIT(0)
+#define RT2880_GPIO_MODE_UART0          BIT(1)
+#define RT2880_GPIO_MODE_SPI            BIT(2)
+#define RT2880_GPIO_MODE_UART1          BIT(3)
+#define RT2880_GPIO_MODE_JTAG           BIT(4)
+#define RT2880_GPIO_MODE_MDIO           BIT(5)
+#define RT2880_GPIO_MODE_SDRAM          BIT(6)
+#define RT2880_GPIO_MODE_PCI            BIT(7)
+
+#define CLKCFG_SRAM_CS_N_WDT            BIT(9)
+
+#define RT2880_SDRAM_BASE               0x08000000
+#define RT2880_MEM_SIZE_MIN             2
+#define RT2880_MEM_SIZE_MAX             128
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
new file mode 100644
index 000000000..fdaf8c918
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink RT288x specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
+#define _RT288X_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  16
+#define cpu_icache_line_size()  16
+
+#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
new file mode 100644
index 000000000..b54619dc4
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <john@phrozen.org>
+ */
+
+#ifndef _RT305X_REGS_H_
+#define _RT305X_REGS_H_
+
+extern enum ralink_soc_type ralink_soc;
+
+static inline int soc_is_rt3050(void)
+{
+        return ralink_soc == RT305X_SOC_RT3050;
+}
+
+static inline int soc_is_rt3052(void)
+{
+        return ralink_soc == RT305X_SOC_RT3052;
+}
+
+static inline int soc_is_rt305x(void)
+{
+        return soc_is_rt3050() || soc_is_rt3052();
+}
+
+static inline int soc_is_rt3350(void)
+{
+        return ralink_soc == RT305X_SOC_RT3350;
+}
+
+static inline int soc_is_rt3352(void)
+{
+        return ralink_soc == RT305X_SOC_RT3352;
+}
+
+static inline int soc_is_rt5350(void)
+{
+        return ralink_soc == RT305X_SOC_RT5350;
+}
+
+#define RT305X_SYSC_BASE                0x10000000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_CHIP_ID                0x0c
+#define SYSC_REG_SYSTEM_CONFIG          0x10
+
+#define RT3052_CHIP_NAME0               0x30335452
+#define RT3052_CHIP_NAME1               0x20203235
+
+#define RT3350_CHIP_NAME0               0x33335452
+#define RT3350_CHIP_NAME1               0x20203035
+
+#define RT3352_CHIP_NAME0               0x33335452
+#define RT3352_CHIP_NAME1               0x20203235
+
+#define RT5350_CHIP_NAME0               0x33355452
+#define RT5350_CHIP_NAME1               0x20203035
+
+#define CHIP_ID_ID_MASK                 0xff
+#define CHIP_ID_ID_SHIFT                8
+#define CHIP_ID_REV_MASK                0xff
+
+#define RT305X_SYSCFG_CPUCLK_SHIFT              18
+#define RT305X_SYSCFG_CPUCLK_MASK               0x1
+#define RT305X_SYSCFG_CPUCLK_LOW                0x0
+#define RT305X_SYSCFG_CPUCLK_HIGH               0x1
+
+#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT       2
+#define RT305X_SYSCFG_CPUCLK_MASK               0x1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT         0x1
+
+#define RT3352_SYSCFG0_CPUCLK_SHIFT     8
+#define RT3352_SYSCFG0_CPUCLK_MASK      0x1
+#define RT3352_SYSCFG0_CPUCLK_LOW       0x0
+#define RT3352_SYSCFG0_CPUCLK_HIGH      0x1
+
+#define RT5350_SYSCFG0_CPUCLK_SHIFT     8
+#define RT5350_SYSCFG0_CPUCLK_MASK      0x3
+#define RT5350_SYSCFG0_CPUCLK_360       0x0
+#define RT5350_SYSCFG0_CPUCLK_320       0x2
+#define RT5350_SYSCFG0_CPUCLK_300       0x3
+
+#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
+#define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
+#define RT5350_SYSCFG0_DRAM_SIZE_2M     0
+#define RT5350_SYSCFG0_DRAM_SIZE_8M     1
+#define RT5350_SYSCFG0_DRAM_SIZE_16M    2
+#define RT5350_SYSCFG0_DRAM_SIZE_32M    3
+#define RT5350_SYSCFG0_DRAM_SIZE_64M    4
+
+/* multi function gpio pins */
+#define RT305X_GPIO_I2C_SD              1
+#define RT305X_GPIO_I2C_SCLK            2
+#define RT305X_GPIO_SPI_EN              3
+#define RT305X_GPIO_SPI_CLK             4
+/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
+#define RT305X_GPIO_7                   7
+#define RT305X_GPIO_10                  10
+#define RT305X_GPIO_14                  14
+#define RT305X_GPIO_UART1_TXD           15
+#define RT305X_GPIO_UART1_RXD           16
+#define RT305X_GPIO_JTAG_TDO            17
+#define RT305X_GPIO_JTAG_TDI            18
+#define RT305X_GPIO_MDIO_MDC            22
+#define RT305X_GPIO_MDIO_MDIO           23
+#define RT305X_GPIO_SDRAM_MD16          24
+#define RT305X_GPIO_SDRAM_MD31          39
+#define RT305X_GPIO_GE0_TXD0            40
+#define RT305X_GPIO_GE0_RXCLK           51
+
+#define RT305X_GPIO_MODE_UART0_SHIFT    2
+#define RT305X_GPIO_MODE_UART0_MASK     0x7
+#define RT305X_GPIO_MODE_UART0(x)       ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF          0
+#define RT305X_GPIO_MODE_PCM_UARTF      1
+#define RT305X_GPIO_MODE_PCM_I2S        2
+#define RT305X_GPIO_MODE_I2S_UARTF      3
+#define RT305X_GPIO_MODE_PCM_GPIO       4
+#define RT305X_GPIO_MODE_GPIO_UARTF     5
+#define RT305X_GPIO_MODE_GPIO_I2S       6
+#define RT305X_GPIO_MODE_GPIO           7
+
+#define RT305X_GPIO_MODE_I2C            0
+#define RT305X_GPIO_MODE_SPI            1
+#define RT305X_GPIO_MODE_UART1          5
+#define RT305X_GPIO_MODE_JTAG           6
+#define RT305X_GPIO_MODE_MDIO           7
+#define RT305X_GPIO_MODE_SDRAM          8
+#define RT305X_GPIO_MODE_RGMII          9
+#define RT5350_GPIO_MODE_PHY_LED        14
+#define RT5350_GPIO_MODE_SPI_CS1        21
+#define RT3352_GPIO_MODE_LNA            18
+#define RT3352_GPIO_MODE_PA             20
+
+#define RT3352_SYSC_REG_SYSCFG0         0x010
+#define RT3352_SYSC_REG_SYSCFG1         0x014
+#define RT3352_SYSC_REG_CLKCFG1         0x030
+#define RT3352_SYSC_REG_RSTCTRL         0x034
+#define RT3352_SYSC_REG_USB_PS          0x05c
+
+#define RT3352_CLKCFG0_XTAL_SEL         BIT(20)
+#define RT3352_CLKCFG1_UPHY0_CLK_EN     BIT(18)
+#define RT3352_CLKCFG1_UPHY1_CLK_EN     BIT(20)
+#define RT3352_RSTCTRL_UHST             BIT(22)
+#define RT3352_RSTCTRL_UDEV             BIT(25)
+#define RT3352_SYSCFG1_USB0_HOST_MODE   BIT(10)
+
+#define RT305X_SDRAM_BASE               0x00000000
+#define RT305X_MEM_SIZE_MIN             2
+#define RT305X_MEM_SIZE_MAX             64
+#define RT3352_MEM_SIZE_MIN             2
+#define RT3352_MEM_SIZE_MAX             256
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
new file mode 100644
index 000000000..7a385fe78
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink RT305x specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
+#define _RT305X_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             1
+#define cpu_has_mipsmt          0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
new file mode 100644
index 000000000..565f25484
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink RT3662/RT3883 SoC register definitions
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef _RT3883_REGS_H_
+#define _RT3883_REGS_H_
+
+#include <linux/bitops.h>
+
+#define RT3883_SDRAM_BASE       0x00000000
+#define RT3883_SYSC_BASE        0x10000000
+#define RT3883_TIMER_BASE       0x10000100
+#define RT3883_INTC_BASE        0x10000200
+#define RT3883_MEMC_BASE        0x10000300
+#define RT3883_UART0_BASE       0x10000500
+#define RT3883_PIO_BASE         0x10000600
+#define RT3883_FSCC_BASE        0x10000700
+#define RT3883_NANDC_BASE       0x10000810
+#define RT3883_I2C_BASE         0x10000900
+#define RT3883_I2S_BASE         0x10000a00
+#define RT3883_SPI_BASE         0x10000b00
+#define RT3883_UART1_BASE       0x10000c00
+#define RT3883_PCM_BASE         0x10002000
+#define RT3883_GDMA_BASE        0x10002800
+#define RT3883_CODEC1_BASE      0x10003000
+#define RT3883_CODEC2_BASE      0x10003800
+#define RT3883_FE_BASE          0x10100000
+#define RT3883_ROM_BASE         0x10118000
+#define RT3883_USBDEV_BASE      0x10112000
+#define RT3883_PCI_BASE         0x10140000
+#define RT3883_WLAN_BASE        0x10180000
+#define RT3883_USBHOST_BASE     0x101c0000
+#define RT3883_BOOT_BASE        0x1c000000
+#define RT3883_SRAM_BASE        0x1e000000
+#define RT3883_PCIMEM_BASE      0x20000000
+
+#define RT3883_EHCI_BASE        (RT3883_USBHOST_BASE)
+#define RT3883_OHCI_BASE        (RT3883_USBHOST_BASE + 0x1000)
+
+#define RT3883_SYSC_SIZE        0x100
+#define RT3883_TIMER_SIZE       0x100
+#define RT3883_INTC_SIZE        0x100
+#define RT3883_MEMC_SIZE        0x100
+#define RT3883_UART0_SIZE       0x100
+#define RT3883_UART1_SIZE       0x100
+#define RT3883_PIO_SIZE         0x100
+#define RT3883_FSCC_SIZE        0x100
+#define RT3883_NANDC_SIZE       0x0f0
+#define RT3883_I2C_SIZE         0x100
+#define RT3883_I2S_SIZE         0x100
+#define RT3883_SPI_SIZE         0x100
+#define RT3883_PCM_SIZE         0x800
+#define RT3883_GDMA_SIZE        0x800
+#define RT3883_CODEC1_SIZE      0x800
+#define RT3883_CODEC2_SIZE      0x800
+#define RT3883_FE_SIZE          0x10000
+#define RT3883_ROM_SIZE         0x4000
+#define RT3883_USBDEV_SIZE      0x4000
+#define RT3883_PCI_SIZE         0x40000
+#define RT3883_WLAN_SIZE        0x40000
+#define RT3883_USBHOST_SIZE     0x40000
+#define RT3883_BOOT_SIZE        (32 * 1024 * 1024)
+#define RT3883_SRAM_SIZE        (32 * 1024 * 1024)
+
+/* SYSC registers */
+#define RT3883_SYSC_REG_CHIPID0_3       0x00    /* Chip ID 0 */
+#define RT3883_SYSC_REG_CHIPID4_7       0x04    /* Chip ID 1 */
+#define RT3883_SYSC_REG_REVID           0x0c    /* Chip Revision Identification */
+#define RT3883_SYSC_REG_SYSCFG0         0x10    /* System Configuration 0 */
+#define RT3883_SYSC_REG_SYSCFG1         0x14    /* System Configuration 1 */
+#define RT3883_SYSC_REG_CLKCFG0         0x2c    /* Clock Configuration 0 */
+#define RT3883_SYSC_REG_CLKCFG1         0x30    /* Clock Configuration 1 */
+#define RT3883_SYSC_REG_RSTCTRL         0x34    /* Reset Control*/
+#define RT3883_SYSC_REG_RSTSTAT         0x38    /* Reset Status*/
+#define RT3883_SYSC_REG_USB_PS          0x5c    /* USB Power saving control */
+#define RT3883_SYSC_REG_GPIO_MODE       0x60    /* GPIO Purpose Select */
+#define RT3883_SYSC_REG_PCIE_CLK_GEN0   0x7c
+#define RT3883_SYSC_REG_PCIE_CLK_GEN1   0x80
+#define RT3883_SYSC_REG_PCIE_CLK_GEN2   0x84
+#define RT3883_SYSC_REG_PMU             0x88
+#define RT3883_SYSC_REG_PMU1            0x8c
+
+#define RT3883_CHIP_NAME0               0x38335452
+#define RT3883_CHIP_NAME1               0x20203338
+
+#define RT3883_REVID_VER_ID_MASK        0x0f
+#define RT3883_REVID_VER_ID_SHIFT       8
+#define RT3883_REVID_ECO_ID_MASK        0x0f
+
+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2   BIT(17)
+#define RT3883_SYSCFG0_CPUCLK_SHIFT     8
+#define RT3883_SYSCFG0_CPUCLK_MASK      0x3
+#define RT3883_SYSCFG0_CPUCLK_250       0x0
+#define RT3883_SYSCFG0_CPUCLK_384       0x1
+#define RT3883_SYSCFG0_CPUCLK_480       0x2
+#define RT3883_SYSCFG0_CPUCLK_500       0x3
+
+#define RT3883_SYSCFG1_USB0_HOST_MODE   BIT(10)
+#define RT3883_SYSCFG1_PCIE_RC_MODE     BIT(8)
+#define RT3883_SYSCFG1_PCI_HOST_MODE    BIT(7)
+#define RT3883_SYSCFG1_PCI_66M_MODE     BIT(6)
+#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
+
+#define RT3883_CLKCFG1_PCIE_CLK_EN      BIT(21)
+#define RT3883_CLKCFG1_UPHY1_CLK_EN     BIT(20)
+#define RT3883_CLKCFG1_PCI_CLK_EN       BIT(19)
+#define RT3883_CLKCFG1_UPHY0_CLK_EN     BIT(18)
+
+#define RT3883_GPIO_MODE_UART0_SHIFT    2
+#define RT3883_GPIO_MODE_UART0_MASK     0x7
+#define RT3883_GPIO_MODE_UART0(x)       ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
+#define RT3883_GPIO_MODE_UARTF          0x0
+#define RT3883_GPIO_MODE_PCM_UARTF      0x1
+#define RT3883_GPIO_MODE_PCM_I2S        0x2
+#define RT3883_GPIO_MODE_I2S_UARTF      0x3
+#define RT3883_GPIO_MODE_PCM_GPIO       0x4
+#define RT3883_GPIO_MODE_GPIO_UARTF     0x5
+#define RT3883_GPIO_MODE_GPIO_I2S       0x6
+#define RT3883_GPIO_MODE_GPIO           0x7
+
+#define RT3883_GPIO_MODE_I2C            0
+#define RT3883_GPIO_MODE_SPI            1
+#define RT3883_GPIO_MODE_UART1          5
+#define RT3883_GPIO_MODE_JTAG           6
+#define RT3883_GPIO_MODE_MDIO           7
+#define RT3883_GPIO_MODE_GE1            9
+#define RT3883_GPIO_MODE_GE2            10
+
+#define RT3883_GPIO_MODE_PCI_SHIFT      11
+#define RT3883_GPIO_MODE_PCI_MASK       0x7
+#define RT3883_GPIO_MODE_PCI            (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
+#define RT3883_GPIO_MODE_LNA_A_SHIFT    16
+#define RT3883_GPIO_MODE_LNA_A_MASK     0x3
+#define _RT3883_GPIO_MODE_LNA_A(_x)     ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
+#define RT3883_GPIO_MODE_LNA_A_GPIO     0x3
+#define RT3883_GPIO_MODE_LNA_A          _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
+#define RT3883_GPIO_MODE_LNA_G_SHIFT    18
+#define RT3883_GPIO_MODE_LNA_G_MASK     0x3
+#define _RT3883_GPIO_MODE_LNA_G(_x)     ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
+#define RT3883_GPIO_MODE_LNA_G_GPIO     0x3
+#define RT3883_GPIO_MODE_LNA_G          _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
+
+#define RT3883_GPIO_I2C_SD              1
+#define RT3883_GPIO_I2C_SCLK            2
+#define RT3883_GPIO_SPI_CS0             3
+#define RT3883_GPIO_SPI_CLK             4
+#define RT3883_GPIO_SPI_MOSI            5
+#define RT3883_GPIO_SPI_MISO            6
+#define RT3883_GPIO_7                   7
+#define RT3883_GPIO_10                  10
+#define RT3883_GPIO_11                  11
+#define RT3883_GPIO_14                  14
+#define RT3883_GPIO_UART1_TXD           15
+#define RT3883_GPIO_UART1_RXD           16
+#define RT3883_GPIO_JTAG_TDO            17
+#define RT3883_GPIO_JTAG_TDI            18
+#define RT3883_GPIO_JTAG_TMS            19
+#define RT3883_GPIO_JTAG_TCLK           20
+#define RT3883_GPIO_JTAG_TRST_N         21
+#define RT3883_GPIO_MDIO_MDC            22
+#define RT3883_GPIO_MDIO_MDIO           23
+#define RT3883_GPIO_LNA_PE_A0           32
+#define RT3883_GPIO_LNA_PE_A1           33
+#define RT3883_GPIO_LNA_PE_A2           34
+#define RT3883_GPIO_LNA_PE_G0           35
+#define RT3883_GPIO_LNA_PE_G1           36
+#define RT3883_GPIO_LNA_PE_G2           37
+#define RT3883_GPIO_PCI_AD0             40
+#define RT3883_GPIO_PCI_AD31            71
+#define RT3883_GPIO_GE2_TXD0            72
+#define RT3883_GPIO_GE2_TXD1            73
+#define RT3883_GPIO_GE2_TXD2            74
+#define RT3883_GPIO_GE2_TXD3            75
+#define RT3883_GPIO_GE2_TXEN            76
+#define RT3883_GPIO_GE2_TXCLK           77
+#define RT3883_GPIO_GE2_RXD0            78
+#define RT3883_GPIO_GE2_RXD1            79
+#define RT3883_GPIO_GE2_RXD2            80
+#define RT3883_GPIO_GE2_RXD3            81
+#define RT3883_GPIO_GE2_RXDV            82
+#define RT3883_GPIO_GE2_RXCLK           83
+#define RT3883_GPIO_GE1_TXD0            84
+#define RT3883_GPIO_GE1_TXD1            85
+#define RT3883_GPIO_GE1_TXD2            86
+#define RT3883_GPIO_GE1_TXD3            87
+#define RT3883_GPIO_GE1_TXEN            88
+#define RT3883_GPIO_GE1_TXCLK           89
+#define RT3883_GPIO_GE1_RXD0            90
+#define RT3883_GPIO_GE1_RXD1            91
+#define RT3883_GPIO_GE1_RXD2            92
+#define RT3883_GPIO_GE1_RXD3            93
+#define RT3883_GPIO_GE1_RXDV            94
+#define RT3883_GPIO_GE1_RXCLK   95
+
+#define RT3883_RSTCTRL_PCIE_PCI_PDM     BIT(27)
+#define RT3883_RSTCTRL_FLASH            BIT(26)
+#define RT3883_RSTCTRL_UDEV             BIT(25)
+#define RT3883_RSTCTRL_PCI              BIT(24)
+#define RT3883_RSTCTRL_PCIE             BIT(23)
+#define RT3883_RSTCTRL_UHST             BIT(22)
+#define RT3883_RSTCTRL_FE               BIT(21)
+#define RT3883_RSTCTRL_WLAN             BIT(20)
+#define RT3883_RSTCTRL_UART1            BIT(29)
+#define RT3883_RSTCTRL_SPI              BIT(18)
+#define RT3883_RSTCTRL_I2S              BIT(17)
+#define RT3883_RSTCTRL_I2C              BIT(16)
+#define RT3883_RSTCTRL_NAND             BIT(15)
+#define RT3883_RSTCTRL_DMA              BIT(14)
+#define RT3883_RSTCTRL_PIO              BIT(13)
+#define RT3883_RSTCTRL_UART             BIT(12)
+#define RT3883_RSTCTRL_PCM              BIT(11)
+#define RT3883_RSTCTRL_MC               BIT(10)
+#define RT3883_RSTCTRL_INTC             BIT(9)
+#define RT3883_RSTCTRL_TIMER            BIT(8)
+#define RT3883_RSTCTRL_SYS              BIT(0)
+
+#define RT3883_INTC_INT_SYSCTL  BIT(0)
+#define RT3883_INTC_INT_TIMER0  BIT(1)
+#define RT3883_INTC_INT_TIMER1  BIT(2)
+#define RT3883_INTC_INT_IA      BIT(3)
+#define RT3883_INTC_INT_PCM     BIT(4)
+#define RT3883_INTC_INT_UART0   BIT(5)
+#define RT3883_INTC_INT_PIO     BIT(6)
+#define RT3883_INTC_INT_DMA     BIT(7)
+#define RT3883_INTC_INT_NAND    BIT(8)
+#define RT3883_INTC_INT_PERFC   BIT(9)
+#define RT3883_INTC_INT_I2S     BIT(10)
+#define RT3883_INTC_INT_UART1   BIT(12)
+#define RT3883_INTC_INT_UHST    BIT(18)
+#define RT3883_INTC_INT_UDEV    BIT(19)
+
+/* FLASH/SRAM/Codec Controller registers */
+#define RT3883_FSCC_REG_FLASH_CFG0      0x00
+#define RT3883_FSCC_REG_FLASH_CFG1      0x04
+#define RT3883_FSCC_REG_CODEC_CFG0      0x40
+#define RT3883_FSCC_REG_CODEC_CFG1      0x44
+
+#define RT3883_FLASH_CFG_WIDTH_SHIFT    26
+#define RT3883_FLASH_CFG_WIDTH_MASK     0x3
+#define RT3883_FLASH_CFG_WIDTH_8BIT     0x0
+#define RT3883_FLASH_CFG_WIDTH_16BIT    0x1
+#define RT3883_FLASH_CFG_WIDTH_32BIT    0x2
+
+#define RT3883_SDRAM_BASE               0x00000000
+#define RT3883_MEM_SIZE_MIN             2
+#define RT3883_MEM_SIZE_MAX             256
+
+#endif /* _RT3883_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
new file mode 100644
index 000000000..0a61910f6
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Ralink RT3662/RT3883 specific CPU feature overrides
+ *
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
+#define _RT3883_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             1
+#define cpu_has_mipsmt          0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000..8539ccfb6
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  IDT RC32434 specific CPU feature overrides
+ *
+ *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_sb1_cache               0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+
+#define cpu_has_mips16                  0
+#define cpu_has_mips16e2                0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+
+#define cpu_has_vtag_icache             0
+
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#define cpu_has_mipsmt                  0
+
+/* #define cpu_has_nofpuex              ? */
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#define cpu_has_64bit_gp_regs           0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+
+#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h
new file mode 100644
index 000000000..e1cad0c7f
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
+/*
+ *  Definitions for the DDR registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _ASM_RC32434_DDR_H_
+#define _ASM_RC32434_DDR_H_
+
+#include <asm/mach-rc32434/rb.h>
+
+/* DDR register structure */
+struct ddr_ram {
+        u32 ddrbase;
+        u32 ddrmask;
+        u32 res1;
+        u32 res2;
+        u32 ddrc;
+        u32 ddrabase;
+        u32 ddramask;
+        u32 ddramap;
+        u32 ddrcust;
+        u32 ddrrdc;
+        u32 ddrspare;
+};
+
+#define DDR0_PHYS_ADDR          0x18018000
+
+/* DDR banks masks */
+#define DDR_MASK                0xffff0000
+#define DDR0_BASE_MSK           DDR_MASK
+#define DDR1_BASE_MSK           DDR_MASK
+
+/* DDR bank0 registers */
+#define RC32434_DDR0_ATA_BIT            5
+#define RC32434_DDR0_ATA_MSK            0x000000E0
+#define RC32434_DDR0_DBW_BIT            8
+#define RC32434_DDR0_DBW_MSK            0x00000100
+#define RC32434_DDR0_WR_BIT             9
+#define RC32434_DDR0_WR_MSK             0x00000600
+#define RC32434_DDR0_PS_BIT             11
+#define RC32434_DDR0_PS_MSK             0x00001800
+#define RC32434_DDR0_DTYPE_BIT          13
+#define RC32434_DDR0_DTYPE_MSK          0x0000e000
+#define RC32434_DDR0_RFC_BIT            16
+#define RC32434_DDR0_RFC_MSK            0x000f0000
+#define RC32434_DDR0_RP_BIT             20
+#define RC32434_DDR0_RP_MSK             0x00300000
+#define RC32434_DDR0_AP_BIT             22
+#define RC32434_DDR0_AP_MSK             0x00400000
+#define RC32434_DDR0_RCD_BIT            23
+#define RC32434_DDR0_RCD_MSK            0x01800000
+#define RC32434_DDR0_CL_BIT             25
+#define RC32434_DDR0_CL_MSK             0x06000000
+#define RC32434_DDR0_DBM_BIT            27
+#define RC32434_DDR0_DBM_MSK            0x08000000
+#define RC32434_DDR0_SDS_BIT            28
+#define RC32434_DDR0_SDS_MSK            0x10000000
+#define RC32434_DDR0_ATP_BIT            29
+#define RC32434_DDR0_ATP_MSK            0x60000000
+#define RC32434_DDR0_RE_BIT             31
+#define RC32434_DDR0_RE_MSK             0x80000000
+
+/* DDR bank C registers */
+#define RC32434_DDRC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DDRC_CES_BIT            0
+#define RC32434_DDRC_ACE_BIT            1
+
+/* Custom DDR bank registers */
+#define RC32434_DCST_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DCST_CS_BIT             0
+#define RC32434_DCST_CS_MSK             0x00000003
+#define RC32434_DCST_WE_BIT             2
+#define RC32434_DCST_RAS_BIT            3
+#define RC32434_DCST_CAS_BIT            4
+#define RC32434_DSCT_CKE_BIT            5
+#define RC32434_DSCT_BA_BIT             6
+#define RC32434_DSCT_BA_MSK             0x000000c0
+
+/* DDR QSC registers */
+#define RC32434_QSC_DM_BIT              0
+#define RC32434_QSC_DM_MSK              0x00000003
+#define RC32434_QSC_DQSBS_BIT           2
+#define RC32434_QSC_DQSBS_MSK           0x000000fc
+#define RC32434_QSC_DB_BIT              8
+#define RC32434_QSC_DB_MSK              0x00000100
+#define RC32434_QSC_DBSP_BIT            9
+#define RC32434_QSC_DBSP_MSK            0x01fffe00
+#define RC32434_QSC_BDP_BIT             25
+#define RC32434_QSC_BDP_MSK             0x7e000000
+
+/* DDR LLC registers */
+#define RC32434_LLC_EAO_BIT             0
+#define RC32434_LLC_EAO_MSK             0x00000001
+#define RC32434_LLC_EO_BIT              1
+#define RC32434_LLC_EO_MSK              0x0000003e
+#define RC32434_LLC_FS_BIT              6
+#define RC32434_LLC_FS_MSK              0x000000c0
+#define RC32434_LLC_AS_BIT              8
+#define RC32434_LLC_AS_MSK              0x00000700
+#define RC32434_LLC_SP_BIT              11
+#define RC32434_LLC_SP_MSK              0x001ff800
+
+/* DDR LLFC registers */
+#define RC32434_LLFC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_LLFC_MEN_BIT            0
+#define RC32434_LLFC_EAN_BIT            1
+#define RC32434_LLFC_FF_BIT             2
+
+/* DDR DLLTA registers */
+#define RC32434_DLLTA_ADDR_BIT          2
+#define RC32434_DLLTA_ADDR_MSK          0xfffffffc
+
+/* DDR DLLED registers */
+#define RC32434_DLLED_MSK(x)            BIT_TO_MASK(x)
+#define RC32434_DLLED_DBE_BIT           0
+#define RC32434_DLLED_DTE_BIT           1
+
+#endif  /* _ASM_RC32434_DDR_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h
new file mode 100644
index 000000000..44dc87bb8
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef __ASM_RC32434_DMA_H
+#define __ASM_RC32434_DMA_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define DMA0_BASE_ADDR                  0x18040000
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+struct dma_desc {
+        u32 control;                    /* Control. use DMAD_* */
+        u32 ca;                         /* Current Address. */
+        u32 devcs;                      /* Device control and status. */
+        u32 link;                       /* Next descriptor in chain. */
+};
+
+#define DMA_DESC_SIZ                    sizeof(struct dma_desc)
+#define DMA_DESC_COUNT_BIT              0
+#define DMA_DESC_COUNT_MSK              0x0003ffff
+#define DMA_DESC_DS_BIT                 20
+#define DMA_DESC_DS_MSK                 0x00300000
+
+#define DMA_DESC_DEV_CMD_BIT            22
+#define DMA_DESC_DEV_CMD_MSK            0x01c00000
+
+/* DMA command sizes */
+#define DMA_DESC_DEV_CMD_BYTE           0
+#define DMA_DESC_DEV_CMD_HLF_WD         1
+#define DMA_DESC_DEV_CMD_WORD           2
+#define DMA_DESC_DEV_CMD_2WORDS         3
+#define DMA_DESC_DEV_CMD_4WORDS         4
+#define DMA_DESC_DEV_CMD_6WORDS         5
+#define DMA_DESC_DEV_CMD_8WORDS         6
+#define DMA_DESC_DEV_CMD_16WORDS        7
+
+/* DMA descriptors interrupts */
+#define DMA_DESC_COF                    (1 << 25) /* Chain on finished */
+#define DMA_DESC_COD                    (1 << 26) /* Chain on done */
+#define DMA_DESC_IOF                    (1 << 27) /* Interrupt on finished */
+#define DMA_DESC_IOD                    (1 << 28) /* Interrupt on done */
+#define DMA_DESC_TERM                   (1 << 29) /* Terminated */
+#define DMA_DESC_DONE                   (1 << 30) /* Done */
+#define DMA_DESC_FINI                   (1 << 31) /* Finished */
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct dma_reg {
+        u32 dmac;               /* Control. */
+        u32 dmas;               /* Status. */
+        u32 dmasm;              /* Mask. */
+        u32 dmadptr;            /* Descriptor pointer. */
+        u32 dmandptr;           /* Next descriptor pointer. */
+};
+
+/* DMA channels specific registers */
+#define DMA_CHAN_RUN_BIT                (1 << 0)
+#define DMA_CHAN_DONE_BIT               (1 << 1)
+#define DMA_CHAN_MODE_BIT               (1 << 2)
+#define DMA_CHAN_MODE_MSK               0x0000000c
+#define  DMA_CHAN_MODE_AUTO             0
+#define  DMA_CHAN_MODE_BURST            1
+#define  DMA_CHAN_MODE_XFRT             2
+#define  DMA_CHAN_MODE_RSVD             3
+#define DMA_CHAN_ACT_BIT                (1 << 4)
+
+/* DMA status registers */
+#define DMA_STAT_FINI                   (1 << 0)
+#define DMA_STAT_DONE                   (1 << 1)
+#define DMA_STAT_CHAIN                  (1 << 2)
+#define DMA_STAT_ERR                    (1 << 3)
+#define DMA_STAT_HALT                   (1 << 4)
+
+/*
+ * DMA channel definitions
+ */
+
+#define DMA_CHAN_ETH_RCV                0
+#define DMA_CHAN_ETH_XMT                1
+#define DMA_CHAN_MEM_TO_FIFO            2
+#define DMA_CHAN_FIFO_TO_MEM            3
+#define DMA_CHAN_PCI_TO_MEM             4
+#define DMA_CHAN_MEM_TO_PCI             5
+#define DMA_CHAN_COUNT                  6
+
+struct dma_channel {
+        struct dma_reg ch[DMA_CHAN_COUNT];
+};
+
+#endif  /* __ASM_RC32434_DMA_H */
diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h
new file mode 100644
index 000000000..37d73b987
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma_v.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef _ASM_RC32434_DMA_V_H_
+#define _ASM_RC32434_DMA_V_H_
+
+#include  <asm/mach-rc32434/dma.h>
+#include  <asm/mach-rc32434/rc32434.h>
+
+#define DMA_CHAN_OFFSET         0x14
+#define IS_DMA_USED(X)          (((X) & \
+                                (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
+                                != 0)
+#define DMA_COUNT(count)        ((count) & DMA_DESC_COUNT_MSK)
+
+#define DMA_HALT_TIMEOUT        500
+
+static inline int rc32434_halt_dma(struct dma_reg *ch)
+{
+        int timeout = 1;
+        if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
+                __raw_writel(0, &ch->dmac);
+                for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+                        if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
+                                __raw_writel(0, &ch->dmas);
+                                break;
+                        }
+                }
+        }
+
+        return timeout ? 0 : 1;
+}
+
+static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(0, &ch->dmandptr);
+        __raw_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(dma_addr, &ch->dmandptr);
+}
+
+#endif  /* _ASM_RC32434_DMA_V_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h
new file mode 100644
index 000000000..c2645faad
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
+/*
+ *  Definitions for the Ethernet registers
+ *
+ *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_ETH_H
+#define __ASM_RC32434_ETH_H
+
+
+#define ETH0_BASE_ADDR          0x18060000
+
+struct eth_regs {
+        u32 ethintfc;
+        u32 ethfifott;
+        u32 etharc;
+        u32 ethhash0;
+        u32 ethhash1;
+        u32 ethu0[4];           /* Reserved. */
+        u32 ethpfs;
+        u32 ethmcp;
+        u32 eth_u1[10];         /* Reserved. */
+        u32 ethspare;
+        u32 eth_u2[42];         /* Reserved. */
+        u32 ethsal0;
+        u32 ethsah0;
+        u32 ethsal1;
+        u32 ethsah1;
+        u32 ethsal2;
+        u32 ethsah2;
+        u32 ethsal3;
+        u32 ethsah3;
+        u32 ethrbc;
+        u32 ethrpc;
+        u32 ethrupc;
+        u32 ethrfc;
+        u32 ethtbc;
+        u32 ethgpf;
+        u32 eth_u9[50];         /* Reserved. */
+        u32 ethmac1;
+        u32 ethmac2;
+        u32 ethipgt;
+        u32 ethipgr;
+        u32 ethclrt;
+        u32 ethmaxf;
+        u32 eth_u10;            /* Reserved. */
+        u32 ethmtest;
+        u32 miimcfg;
+        u32 miimcmd;
+        u32 miimaddr;
+        u32 miimwtd;
+        u32 miimrdd;
+        u32 miimind;
+        u32 eth_u11;            /* Reserved. */
+        u32 eth_u12;            /* Reserved. */
+        u32 ethcfsa0;
+        u32 ethcfsa1;
+        u32 ethcfsa2;
+};
+
+/* Ethernet interrupt registers */
+#define ETH_INT_FC_EN           (1 << 0)
+#define ETH_INT_FC_ITS          (1 << 1)
+#define ETH_INT_FC_RIP          (1 << 2)
+#define ETH_INT_FC_JAM          (1 << 3)
+#define ETH_INT_FC_OVR          (1 << 4)
+#define ETH_INT_FC_UND          (1 << 5)
+#define ETH_INT_FC_IOC          0x000000c0
+
+/* Ethernet FIFO registers */
+#define ETH_FIFI_TT_TTH_BIT     0
+#define ETH_FIFO_TT_TTH         0x0000007f
+
+/* Ethernet ARC/multicast registers */
+#define ETH_ARC_PRO             (1 << 0)
+#define ETH_ARC_AM              (1 << 1)
+#define ETH_ARC_AFM             (1 << 2)
+#define ETH_ARC_AB              (1 << 3)
+
+/* Ethernet SAL registers */
+#define ETH_SAL_BYTE_5          0x000000ff
+#define ETH_SAL_BYTE_4          0x0000ff00
+#define ETH_SAL_BYTE_3          0x00ff0000
+#define ETH_SAL_BYTE_2          0xff000000
+
+/* Ethernet SAH registers */
+#define ETH_SAH_BYTE1           0x000000ff
+#define ETH_SAH_BYTE0           0x0000ff00
+
+/* Ethernet GPF register */
+#define ETH_GPF_PTV             0x0000ffff
+
+/* Ethernet PFG register */
+#define ETH_PFS_PFD             (1 << 0)
+
+/* Ethernet CFSA[0-3] registers */
+#define ETH_CFSA0_CFSA4         0x000000ff
+#define ETH_CFSA0_CFSA5         0x0000ff00
+#define ETH_CFSA1_CFSA2         0x000000ff
+#define ETH_CFSA1_CFSA3         0x0000ff00
+#define ETH_CFSA1_CFSA0         0x000000ff
+#define ETH_CFSA1_CFSA1         0x0000ff00
+
+/* Ethernet MAC1 registers */
+#define ETH_MAC1_RE             (1 << 0)
+#define ETH_MAC1_PAF            (1 << 1)
+#define ETH_MAC1_RFC            (1 << 2)
+#define ETH_MAC1_TFC            (1 << 3)
+#define ETH_MAC1_LB             (1 << 4)
+#define ETH_MAC1_MR             (1 << 31)
+
+/* Ethernet MAC2 registers */
+#define ETH_MAC2_FD             (1 << 0)
+#define ETH_MAC2_FLC            (1 << 1)
+#define ETH_MAC2_HFE            (1 << 2)
+#define ETH_MAC2_DC             (1 << 3)
+#define ETH_MAC2_CEN            (1 << 4)
+#define ETH_MAC2_PE             (1 << 5)
+#define ETH_MAC2_VPE            (1 << 6)
+#define ETH_MAC2_APE            (1 << 7)
+#define ETH_MAC2_PPE            (1 << 8)
+#define ETH_MAC2_LPE            (1 << 9)
+#define ETH_MAC2_NB             (1 << 12)
+#define ETH_MAC2_BP             (1 << 13)
+#define ETH_MAC2_ED             (1 << 14)
+
+/* Ethernet IPGT register */
+#define ETH_IPGT                0x0000007f
+
+/* Ethernet IPGR registers */
+#define ETH_IPGR_IPGR2          0x0000007f
+#define ETH_IPGR_IPGR1          0x00007f00
+
+/* Ethernet CLRT registers */
+#define ETH_CLRT_MAX_RET        0x0000000f
+#define ETH_CLRT_COL_WIN        0x00003f00
+
+/* Ethernet MAXF register */
+#define ETH_MAXF                0x0000ffff
+
+/* Ethernet test registers */
+#define ETH_TEST_REG            (1 << 2)
+#define ETH_MCP_DIV             0x000000ff
+
+/* MII registers */
+#define ETH_MII_CFG_RSVD        0x0000000c
+#define ETH_MII_CMD_RD          (1 << 0)
+#define ETH_MII_CMD_SCN         (1 << 1)
+#define ETH_MII_REG_ADDR        0x0000001f
+#define ETH_MII_PHY_ADDR        0x00001f00
+#define ETH_MII_WTD_DATA        0x0000ffff
+#define ETH_MII_RDD_DATA        0x0000ffff
+#define ETH_MII_IND_BSY         (1 << 0)
+#define ETH_MII_IND_SCN         (1 << 1)
+#define ETH_MII_IND_NV          (1 << 2)
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+
+#define ETH_RX_FD               (1 << 0)
+#define ETH_RX_LD               (1 << 1)
+#define ETH_RX_ROK              (1 << 2)
+#define ETH_RX_FM               (1 << 3)
+#define ETH_RX_MP               (1 << 4)
+#define ETH_RX_BP               (1 << 5)
+#define ETH_RX_VLT              (1 << 6)
+#define ETH_RX_CF               (1 << 7)
+#define ETH_RX_OVR              (1 << 8)
+#define ETH_RX_CRC              (1 << 9)
+#define ETH_RX_CV               (1 << 10)
+#define ETH_RX_DB               (1 << 11)
+#define ETH_RX_LE               (1 << 12)
+#define ETH_RX_LOR              (1 << 13)
+#define ETH_RX_CES              (1 << 14)
+#define ETH_RX_LEN_BIT          16
+#define ETH_RX_LEN              0xffff0000
+
+#define ETH_TX_FD               (1 << 0)
+#define ETH_TX_LD               (1 << 1)
+#define ETH_TX_OEN              (1 << 2)
+#define ETH_TX_PEN              (1 << 3)
+#define ETH_TX_CEN              (1 << 4)
+#define ETH_TX_HEN              (1 << 5)
+#define ETH_TX_TOK              (1 << 6)
+#define ETH_TX_MP               (1 << 7)
+#define ETH_TX_BP               (1 << 8)
+#define ETH_TX_UND              (1 << 9)
+#define ETH_TX_OF               (1 << 10)
+#define ETH_TX_ED               (1 << 11)
+#define ETH_TX_EC               (1 << 12)
+#define ETH_TX_LC               (1 << 13)
+#define ETH_TX_TD               (1 << 14)
+#define ETH_TX_CRC              (1 << 15)
+#define ETH_TX_LE               (1 << 16)
+#define ETH_TX_CC               0x001E0000
+
+#endif  /* __ASM_RC32434_ETH_H */
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
new file mode 100644
index 000000000..a3192da9f
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *      All rights reserved.
+ *
+ * GPIO register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ */
+
+#ifndef _RC32434_GPIO_H_
+#define _RC32434_GPIO_H_
+
+struct rb532_gpio_reg {
+        u32   gpiofunc;   /* GPIO Function Register
+                           * gpiofunc[x]==0 bit = gpio
+                           * func[x]==1  bit = altfunc
+                           */
+        u32   gpiocfg;    /* GPIO Configuration Register
+                           * gpiocfg[x]==0 bit = input
+                           * gpiocfg[x]==1 bit = output
+                           */
+        u32   gpiod;      /* GPIO Data Register
+                           * gpiod[x] read/write gpio pinX status
+                           */
+        u32   gpioilevel; /* GPIO Interrupt Status Register
+                           * interrupt level (see gpioistat)
+                           */
+        u32   gpioistat;  /* Gpio Interrupt Status Register
+                           * istat[x] = (gpiod[x] == level[x])
+                           * cleared in ISR (STICKY bits)
+                           */
+        u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+};
+
+/* UART GPIO signals */
+#define RC32434_UART0_SOUT      (1 << 0)
+#define RC32434_UART0_SIN       (1 << 1)
+#define RC32434_UART0_RTS       (1 << 2)
+#define RC32434_UART0_CTS       (1 << 3)
+
+/* M & P bus GPIO signals */
+#define RC32434_MP_BIT_22       (1 << 4)
+#define RC32434_MP_BIT_23       (1 << 5)
+#define RC32434_MP_BIT_24       (1 << 6)
+#define RC32434_MP_BIT_25       (1 << 7)
+
+/* CPU GPIO signals */
+#define RC32434_CPU_GPIO        (1 << 8)
+
+/* Reserved GPIO signals */
+#define RC32434_AF_SPARE_6      (1 << 9)
+#define RC32434_AF_SPARE_4      (1 << 10)
+#define RC32434_AF_SPARE_3      (1 << 11)
+#define RC32434_AF_SPARE_2      (1 << 12)
+
+/* PCI messaging unit */
+#define RC32434_PCI_MSU_GPIO    (1 << 13)
+
+/* NAND GPIO signals */
+#define GPIO_RDY                8
+#define GPIO_WPX        9
+#define GPIO_ALE                10
+#define GPIO_CLE                11
+
+/* Compact Flash GPIO pin */
+#define CF_GPIO_NUM             13
+
+/* S1 button GPIO (shared with UART0_SIN) */
+#define GPIO_BTN_S1             1
+
+extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
+extern void rb532_gpio_set_istat(int bit, unsigned gpio);
+extern void rb532_gpio_set_func(unsigned gpio);
+
+#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/integ.h b/arch/mips/include/asm/mach-rc32434/integ.h
new file mode 100644
index 000000000..fa65bc3d8
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
+/*
+ *  Definitions for the Watchdog registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __RC32434_INTEG_H__
+#define __RC32434_INTEG_H__
+
+#include <asm/mach-rc32434/rb.h>
+
+#define INTEG0_BASE_ADDR        0x18030030
+
+struct integ {
+        u32 errcs;                      /* sticky use ERRCS_ */
+        u32 wtcount;                    /* Watchdog timer count reg. */
+        u32 wtcompare;                  /* Watchdog timer timeout value. */
+        u32 wtc;                        /* Watchdog timer control. use WTC_ */
+};
+
+/* Error counters */
+#define RC32434_ERR_WTO         0
+#define RC32434_ERR_WNE         1
+#define RC32434_ERR_UCW         2
+#define RC32434_ERR_UCR         3
+#define RC32434_ERR_UPW         4
+#define RC32434_ERR_UPR         5
+#define RC32434_ERR_UDW         6
+#define RC32434_ERR_UDR         7
+#define RC32434_ERR_SAE         8
+#define RC32434_ERR_WRE         9
+
+/* Watchdog control bits */
+#define RC32434_WTC_EN          0
+#define RC32434_WTC_TO          1
+
+#endif  /* __RC32434_INTEG_H__ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
new file mode 100644
index 000000000..ebe32bd5a
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_RC32434_IRQ_H
+#define __ASM_RC32434_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+#include <asm/mach-rc32434/rb.h>
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND          (REGBASE + 0x38000)
+#define IC_GROUP0_MASK          (REGBASE + 0x38008)
+#define IC_GROUP_OFFSET         0x0C
+
+#define NUM_INTR_GROUPS         5
+
+/* 16550 UARTs */
+#define GROUP0_IRQ_BASE         8       /* GRP2 IRQ numbers start here */
+                                        /* GRP3 IRQ numbers start here */
+#define GROUP1_IRQ_BASE         (GROUP0_IRQ_BASE + 32)
+                                        /* GRP4 IRQ numbers start here */
+#define GROUP2_IRQ_BASE         (GROUP1_IRQ_BASE + 32)
+                                        /* GRP5 IRQ numbers start here */
+#define GROUP3_IRQ_BASE         (GROUP2_IRQ_BASE + 32)
+#define GROUP4_IRQ_BASE         (GROUP3_IRQ_BASE + 32)
+
+#define UART0_IRQ               (GROUP3_IRQ_BASE + 0)
+
+#define ETH0_DMA_RX_IRQ         (GROUP1_IRQ_BASE + 0)
+#define ETH0_DMA_TX_IRQ         (GROUP1_IRQ_BASE + 1)
+#define ETH0_RX_OVR_IRQ         (GROUP3_IRQ_BASE + 9)
+#define ETH0_TX_UND_IRQ         (GROUP3_IRQ_BASE + 10)
+
+#define GPIO_MAPPED_IRQ_BASE    GROUP4_IRQ_BASE
+#define GPIO_MAPPED_IRQ_GROUP   4
+
+#endif  /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
new file mode 100644
index 000000000..9a6eefd12
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/pci.h
@@ -0,0 +1,478 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * Initial Release
+ */
+
+#ifndef _ASM_RC32434_PCI_H_
+#define _ASM_RC32434_PCI_H_
+
+#define epld_mask ((volatile unsigned char *)0xB900000d)
+
+#define PCI0_BASE_ADDR          0x18080000
+#define PCI_LBA_COUNT           4
+
+struct pci_map {
+        u32 address;            /* Address. */
+        u32 control;            /* Control. */
+        u32 mapping;            /* mapping. */
+};
+
+struct pci_reg {
+        u32 pcic;
+        u32 pcis;
+        u32 pcism;
+        u32 pcicfga;
+        u32 pcicfgd;
+        volatile struct pci_map pcilba[PCI_LBA_COUNT];
+        u32 pcidac;
+        u32 pcidas;
+        u32 pcidasm;
+        u32 pcidad;
+        u32 pcidma8c;
+        u32 pcidma9c;
+        u32 pcitc;
+};
+
+#define PCI_MSU_COUNT           2
+
+struct pci_msu {
+        u32 pciim[PCI_MSU_COUNT];
+        u32 pciom[PCI_MSU_COUNT];
+        u32 pciid;
+        u32 pciiic;
+        u32 pciiim;
+        u32 pciiod;
+        u32 pciioic;
+        u32 pciioim;
+};
+
+/*
+ * PCI Control Register
+ */
+
+#define PCI_CTL_EN              (1 << 0)
+#define PCI_CTL_TNR             (1 << 1)
+#define PCI_CTL_SCE             (1 << 2)
+#define PCI_CTL_IEN             (1 << 3)
+#define PCI_CTL_AAA             (1 << 4)
+#define PCI_CTL_EAP             (1 << 5)
+#define PCI_CTL_PCIM_BIT        6
+#define PCI_CTL_PCIM            0x000001c0
+
+#define PCI_CTL_PCIM_DIS        0
+#define PCI_CTL_PCIM_TNR        1 /* Satellite - target not ready */
+#define PCI_CTL_PCIM_SUS        2 /* Satellite - suspended CPU. */
+#define PCI_CTL_PCIM_EXT        3 /* Host - external arbiter. */
+#define PCI_CTL PCIM_PRIO       4 /* Host - fixed priority arb. */
+#define PCI_CTL_PCIM_RR         5 /* Host - round robin priority. */
+#define PCI_CTL_PCIM_RSVD6      6
+#define PCI_CTL_PCIM_RSVD7      7
+
+#define PCI_CTL_IGM             (1 << 9)
+
+/*
+ * PCI Status Register
+ */
+
+#define PCI_STAT_EED            (1 << 0)
+#define PCI_STAT_WR             (1 << 1)
+#define PCI_STAT_NMI            (1 << 2)
+#define PCI_STAT_II             (1 << 3)
+#define PCI_STAT_CWE            (1 << 4)
+#define PCI_STAT_CRE            (1 << 5)
+#define PCI_STAT_MDPE           (1 << 6)
+#define PCI_STAT_STA            (1 << 7)
+#define PCI_STAT_RTA            (1 << 8)
+#define PCI_STAT_RMA            (1 << 9)
+#define PCI_STAT_SSE            (1 << 10)
+#define PCI_STAT_OSE            (1 << 11)
+#define PCI_STAT_PE             (1 << 12)
+#define PCI_STAT_TAE            (1 << 13)
+#define PCI_STAT_RLE            (1 << 14)
+#define PCI_STAT_BME            (1 << 15)
+#define PCI_STAT_PRD            (1 << 16)
+#define PCI_STAT_RIP            (1 << 17)
+
+/*
+ * PCI Status Mask Register
+ */
+
+#define PCI_STATM_EED           PCI_STAT_EED
+#define PCI_STATM_WR            PCI_STAT_WR
+#define PCI_STATM_NMI           PCI_STAT_NMI
+#define PCI_STATM_II            PCI_STAT_II
+#define PCI_STATM_CWE           PCI_STAT_CWE
+#define PCI_STATM_CRE           PCI_STAT_CRE
+#define PCI_STATM_MDPE          PCI_STAT_MDPE
+#define PCI_STATM_STA           PCI_STAT_STA
+#define PCI_STATM_RTA           PCI_STAT_RTA
+#define PCI_STATM_RMA           PCI_STAT_RMA
+#define PCI_STATM_SSE           PCI_STAT_SSE
+#define PCI_STATM_OSE           PCI_STAT_OSE
+#define PCI_STATM_PE            PCI_STAT_PE
+#define PCI_STATM_TAE           PCI_STAT_TAE
+#define PCI_STATM_RLE           PCI_STAT_RLE
+#define PCI_STATM_BME           PCI_STAT_BME
+#define PCI_STATM_PRD           PCI_STAT_PRD
+#define PCI_STATM_RIP           PCI_STAT_RIP
+
+/*
+ * PCI Configuration Address Register
+ */
+#define PCI_CFGA_REG_BIT        2
+#define PCI_CFGA_REG            0x000000fc
+#define  PCI_CFGA_REG_ID        (0x00 >> 2)     /* use PCFGID */
+#define  PCI_CFGA_REG_04        (0x04 >> 2)     /* use PCFG04_ */
+#define  PCI_CFGA_REG_08        (0x08 >> 2)     /* use PCFG08_ */
+#define  PCI_CFGA_REG_0C        (0x0C >> 2)     /* use PCFG0C_ */
+#define  PCI_CFGA_REG_PBA0      (0x10 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA1      (0x14 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */
+#define  PCI_CFGA_REG_3C        (0x3C >> 2)     /* use PCFG3C_ */
+#define  PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA0M     (0x48 >> 2)
+#define  PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA1M     (0x50 >> 2)
+#define  PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA2M     (0x58 >> 2)
+#define  PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA3M     (0x60 >> 2)
+#define  PCI_CFGA_REG_PMGT      (0x64 >> 2)
+#define PCI_CFGA_FUNC_BIT       8
+#define PCI_CFGA_FUNC           0x00000700
+#define PCI_CFGA_DEV_BIT        11
+#define PCI_CFGA_DEV            0x0000f800
+#define PCI_CFGA_DEV_INTERN     0
+#define PCI_CFGA_BUS_BIT        16
+#define PCI CFGA_BUS            0x00ff0000
+#define PCI_CFGA_BUS_TYPE0      0
+#define PCI_CFGA_EN             (1 << 31)
+
+/* PCI CFG04 commands */
+#define PCI_CFG04_CMD_IO_ENA    (1 << 0)
+#define PCI_CFG04_CMD_MEM_ENA   (1 << 1)
+#define PCI_CFG04_CMD_BM_ENA    (1 << 2)
+#define PCI_CFG04_CMD_MW_INV    (1 << 4)
+#define PCI_CFG04_CMD_PAR_ENA   (1 << 6)
+#define PCI_CFG04_CMD_SER_ENA   (1 << 8)
+#define PCI_CFG04_CMD_FAST_ENA  (1 << 9)
+
+/* PCI CFG04 status fields */
+#define PCI_CFG04_STAT_BIT      16
+#define PCI_CFG04_STAT          0xffff0000
+#define PCI_CFG04_STAT_66_MHZ   (1 << 21)
+#define PCI_CFG04_STAT_FBB      (1 << 23)
+#define PCI_CFG04_STAT_MDPE     (1 << 24)
+#define PCI_CFG04_STAT_DST      (1 << 25)
+#define PCI_CFG04_STAT_STA      (1 << 27)
+#define PCI_CFG04_STAT_RTA      (1 << 28)
+#define PCI_CFG04_STAT_RMA      (1 << 29)
+#define PCI_CFG04_STAT_SSE      (1 << 30)
+#define PCI_CFG04_STAT_PE       (1 << 31)
+
+#define PCI_PBA_MSI             (1 << 0)
+#define PCI_PBA_P               (1 << 2)
+
+/* PCI PBAC registers */
+#define PCI_PBAC_MSI            (1 << 0)
+#define PCI_PBAC_P              (1 << 1)
+#define PCI_PBAC_SIZE_BIT       2
+#define PCI_PBAC_SIZE           0x0000007c
+#define PCI_PBAC_SB             (1 << 7)
+#define PCI_PBAC_PP             (1 << 8)
+#define PCI_PBAC_MR_BIT         9
+#define PCI_PBAC_MR             0x00000600
+#define  PCI_PBAC_MR_RD         0
+#define  PCI_PBAC_MR_RD_LINE    1
+#define  PCI_PBAC_MR_RD_MULT    2
+#define PCI_PBAC_MRL            (1 << 11)
+#define PCI_PBAC_MRM            (1 << 12)
+#define PCI_PBAC_TRP            (1 << 13)
+
+#define PCI_CFG40_TRDY_TIM      0x000000ff
+#define PCI_CFG40_RET_LIM       0x0000ff00
+
+/*
+ * PCI Local Base Address [0|1|2|3] Register
+ */
+
+#define PCI_LBA_BADDR_BIT       0
+#define PCI_LBA_BADDR           0xffffff00
+
+/*
+ * PCI Local Base Address Control Register
+ */
+
+#define PCI_LBAC_MSI            (1 << 0)
+#define  PCI_LBAC_MSI_MEM       0
+#define  PCI_LBAC_MSI_IO        1
+#define PCI_LBAC_SIZE_BIT       2
+#define PCI_LBAC_SIZE           0x0000007c
+#define PCI_LBAC_SB             (1 << 7)
+#define PCI_LBAC_RT             (1 << 8)
+#define  PCI_LBAC_RT_NO_PREF    0
+#define  PCI_LBAC_RT_PREF       1
+
+/*
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ */
+#define PCI_LBAM_MADDR_BIT      8
+#define PCI_LBAM_MADDR          0xffffff00
+
+/*
+ * PCI Decoupled Access Control Register
+ */
+#define PCI_DAC_DEN             (1 << 0)
+
+/*
+ * PCI Decoupled Access Status Register
+ */
+#define PCI_DAS_D               (1 << 0)
+#define PCI_DAS_B               (1 << 1)
+#define PCI_DAS_E               (1 << 2)
+#define PCI_DAS_OFE             (1 << 3)
+#define PCI_DAS_OFF             (1 << 4)
+#define PCI_DAS_IFE             (1 << 5)
+#define PCI_DAS_IFF             (1 << 6)
+
+/*
+ * PCI DMA Channel 8 Configuration Register
+ */
+#define PCI_DMA8C_MBS_BIT       0
+#define PCI_DMA8C_MBS           0x00000fff /* Maximum Burst Size. */
+#define PCI_DMA8C_OUR           (1 << 12)
+
+/*
+ * PCI DMA Channel 9 Configuration Register
+ */
+#define PCI_DMA9C_MBS_BIT       0       /* Maximum Burst Size. */
+#define PCI_DMA9C_MBS           0x00000fff
+
+/*
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ */
+
+#define PCI_DMAD_PT_BIT         22              /* in DEVCMD field (descriptor) */
+#define PCI_DMAD_PT             0x00c00000      /* preferred transaction field */
+/* These are for reads (DMA channel 8) */
+#define PCI_DMAD_DEVCMD_MR      0               /* memory read */
+#define PCI_DMAD_DEVCMD_MRL     1               /* memory read line */
+#define PCI_DMAD_DEVCMD_MRM     2               /* memory read multiple */
+#define PCI_DMAD_DEVCMD_IOR     3               /* I/O read */
+/* These are for writes (DMA channel 9) */
+#define PCI_DMAD_DEVCMD_MW      0               /* memory write */
+#define PCI_DMAD_DEVCMD_MWI     1               /* memory write invalidate */
+#define PCI_DMAD_DEVCMD_IOW     3               /* I/O write */
+
+/* Swap byte field applies to both DMA channel 8 and 9 */
+#define PCI_DMAD_SB             (1 << 24)       /* swap byte field */
+
+
+/*
+ * PCI Target Control Register
+ */
+
+#define PCI_TC_RTIMER_BIT       0
+#define PCI_TC_RTIMER           0x000000ff
+#define PCI_TC_DTIMER_BIT       8
+#define PCI_TC_DTIMER           0x0000ff00
+#define PCI_TC_RDR              (1 << 18)
+#define PCI_TC_DDT              (1 << 19)
+
+/*
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ */
+#define PCI_MSU_M0              (1 << 0)
+#define PCI_MSU_M1              (1 << 1)
+#define PCI_MSU_DB              (1 << 2)
+
+#define PCI_MSG_ADDR            0xB8088010
+#define PCI0_ADDR               0xB8080000
+#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
+#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
+
+#define PCIM_SHFT               0x6
+#define PCIM_BIT_LEN            0x7
+#define PCIM_H_EA               0x3
+#define PCIM_H_IA_FIX           0x4
+#define PCIM_H_IA_RR            0x5
+
+#define PCI_ADDR_START          0x50000000
+
+#define CPUTOPCI_MEM_WIN        0x02000000
+#define CPUTOPCI_IO_WIN         0x00100000
+#define PCILBA_SIZE_SHFT        2
+#define PCILBA_SIZE_MASK        0x1F
+#define SIZE_256MB              0x1C
+#define SIZE_128MB              0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB               0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB                0x16
+#define SIZE_2MB                0x15
+#define SIZE_1MB                0x14
+#define KORINA_CONFIG0_ADDR     0x80000000
+#define KORINA_CONFIG1_ADDR     0x80000004
+#define KORINA_CONFIG2_ADDR     0x80000008
+#define KORINA_CONFIG3_ADDR     0x8000000C
+#define KORINA_CONFIG4_ADDR     0x80000010
+#define KORINA_CONFIG5_ADDR     0x80000014
+#define KORINA_CONFIG6_ADDR     0x80000018
+#define KORINA_CONFIG7_ADDR     0x8000001C
+#define KORINA_CONFIG8_ADDR     0x80000020
+#define KORINA_CONFIG9_ADDR     0x80000024
+#define KORINA_CONFIG10_ADDR    0x80000028
+#define KORINA_CONFIG11_ADDR    0x8000002C
+#define KORINA_CONFIG12_ADDR    0x80000030
+#define KORINA_CONFIG13_ADDR    0x80000034
+#define KORINA_CONFIG14_ADDR    0x80000038
+#define KORINA_CONFIG15_ADDR    0x8000003C
+#define KORINA_CONFIG16_ADDR    0x80000040
+#define KORINA_CONFIG17_ADDR    0x80000044
+#define KORINA_CONFIG18_ADDR    0x80000048
+#define KORINA_CONFIG19_ADDR    0x8000004C
+#define KORINA_CONFIG20_ADDR    0x80000050
+#define KORINA_CONFIG21_ADDR    0x80000054
+#define KORINA_CONFIG22_ADDR    0x80000058
+#define KORINA_CONFIG23_ADDR    0x8000005C
+#define KORINA_CONFIG24_ADDR    0x80000060
+#define KORINA_CONFIG25_ADDR    0x80000064
+#define KORINA_CMD              (PCI_CFG04_CMD_IO_ENA | \
+                                 PCI_CFG04_CMD_MEM_ENA | \
+                                 PCI_CFG04_CMD_BM_ENA | \
+                                 PCI_CFG04_CMD_MW_INV | \
+                                 PCI_CFG04_CMD_PAR_ENA | \
+                                 PCI_CFG04_CMD_SER_ENA)
+
+#define KORINA_STAT             (PCI_CFG04_STAT_MDPE | \
+                                 PCI_CFG04_STAT_STA | \
+                                 PCI_CFG04_STAT_RTA | \
+                                 PCI_CFG04_STAT_RMA | \
+                                 PCI_CFG04_STAT_SSE | \
+                                 PCI_CFG04_STAT_PE)
+
+#define KORINA_CNFG1            ((KORINA_STAT<<16)|KORINA_CMD)
+
+#define KORINA_REVID            0
+#define KORINA_CLASS_CODE       0
+#define KORINA_CNFG2            ((KORINA_CLASS_CODE<<8) | \
+                                  KORINA_REVID)
+
+#define KORINA_CACHE_LINE_SIZE  4
+#define KORINA_MASTER_LAT       0x3c
+#define KORINA_HEADER_TYPE      0
+#define KORINA_BIST             0
+
+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
+                      (KORINA_HEADER_TYPE<<16) | \
+                      (KORINA_MASTER_LAT<<8) | \
+                      KORINA_CACHE_LINE_SIZE)
+
+#define KORINA_BAR0     0x00000008      /* 128 MB Memory */
+#define KORINA_BAR1     0x18800001      /* 1 MB IO */
+#define KORINA_BAR2     0x18000001      /* 2 MB IO window for Korina
+                                           internal Registers */
+#define KORINA_BAR3     0x48000008      /* Spare 128 MB Memory */
+
+#define KORINA_CNFG4    KORINA_BAR0
+#define KORINA_CNFG5    KORINA_BAR1
+#define KORINA_CNFG6    KORINA_BAR2
+#define KORINA_CNFG7    KORINA_BAR3
+
+#define KORINA_SUBSYS_VENDOR_ID 0x011d
+#define KORINA_SUBSYSTEM_ID     0x0214
+#define KORINA_CNFG8            0
+#define KORINA_CNFG9            0
+#define KORINA_CNFG10           0
+#define KORINA_CNFG11   ((KORINA_SUBSYS_VENDOR_ID<<16) | \
+                          KORINA_SUBSYSTEM_ID)
+#define KORINA_INT_LINE         1
+#define KORINA_INT_PIN          1
+#define KORINA_MIN_GNT          8
+#define KORINA_MAX_LAT          0x38
+#define KORINA_CNFG12           0
+#define KORINA_CNFG13           0
+#define KORINA_CNFG14           0
+#define KORINA_CNFG15   ((KORINA_MAX_LAT<<24) | \
+                         (KORINA_MIN_GNT<<16) | \
+                         (KORINA_INT_PIN<<8)  | \
+                          KORINA_INT_LINE)
+#define KORINA_RETRY_LIMIT      0x80
+#define KORINA_TRDY_LIMIT       0x80
+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
+                        KORINA_TRDY_LIMIT)
+#define PCI_PBAxC_R             0x0
+#define PCI_PBAxC_RL            0x1
+#define PCI_PBAxC_RM            0x2
+#define SIZE_SHFT               2
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA0C    (PCI_PBAC_MRL | PCI_PBAC_SB | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#else
+#define KORINA_PBA0C    (PCI_PBAC_MRL | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#endif
+#define KORINA_CNFG17   KORINA_PBA0C
+#define KORINA_PBA0M    0x0
+#define KORINA_CNFG18   KORINA_PBA0M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG19   KORINA_PBA1C
+#define KORINA_PBA1M    0x0
+#define KORINA_CNFG20   KORINA_PBA1M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG21   KORINA_PBA2C
+#define KORINA_PBA2M    0x18000000
+#define KORINA_CNFG22   KORINA_PBA2M
+#define KORINA_PBA3C    0
+#define KORINA_CNFG23   KORINA_PBA3C
+#define KORINA_PBA3M    0
+#define KORINA_CNFG24   KORINA_PBA3M
+
+#define PCITC_DTIMER_VAL        8
+#define PCITC_RTIMER_VAL        0x10
+
+#endif  /* __ASM_RC32434_PCI_H */
diff --git a/arch/mips/include/asm/mach-rc32434/prom.h b/arch/mips/include/asm/mach-rc32434/prom.h
new file mode 100644
index 000000000..660707f1b
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/prom.h
@@ -0,0 +1,40 @@
+/*
+ *  Definitions for the PROM
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#define PROM_ENTRY(x)           (0xbfc00000 + ((x) * 8))
+
+#define SR_NMI                  0x00180000
+#define SERIAL_SPEED_ENTRY      0x00000001
+
+#define FREQ_TAG                "HZ="
+#define KMAC_TAG                "kmac="
+#define MEM_TAG                 "mem="
+#define BOARD_TAG               "board="
+
+#define BOARD_RB532             "500"
+#define BOARD_RB532A            "500r5"
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
new file mode 100644
index 000000000..d502673a4
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *
+ *  Copyright (C) 2004 IDT Inc.
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ */
+#ifndef __ASM_RC32434_RB_H
+#define __ASM_RC32434_RB_H
+
+#include <linux/genhd.h>
+
+#define REGBASE         0x18000000
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
+#define UART0BASE       0x58000
+#define RST             (1 << 15)
+#define DEV0BASE        0x010000
+#define DEV0MASK        0x010004
+#define DEV0C           0x010008
+#define DEV0T           0x01000C
+#define DEV1BASE        0x010010
+#define DEV1MASK        0x010014
+#define DEV1C           0x010018
+#define DEV1TC          0x01001C
+#define DEV2BASE        0x010020
+#define DEV2MASK        0x010024
+#define DEV2C           0x010028
+#define DEV2TC          0x01002C
+#define DEV3BASE        0x010030
+#define DEV3MASK        0x010034
+#define DEV3C           0x010038
+#define DEV3TC          0x01003C
+#define BTCS            0x010040
+#define BTCOMPARE       0x010044
+#define GPIOBASE        0x050000
+/* Offsets relative to GPIOBASE */
+#define GPIOFUNC        0x00
+#define GPIOCFG         0x04
+#define GPIOD           0x08
+#define GPIOILEVEL      0x0C
+#define GPIOISTAT       0x10
+#define GPIONMIEN       0x14
+#define IMASK6          0x38
+#define LO_WPX          (1 << 0)
+#define LO_ALE          (1 << 1)
+#define LO_CLE          (1 << 2)
+#define LO_CEX          (1 << 3)
+#define LO_FOFF         (1 << 5)
+#define LO_SPICS        (1 << 6)
+#define LO_ULED         (1 << 7)
+
+#define BIT_TO_MASK(x)  (1 << x)
+
+struct dev_reg {
+        u32     base;
+        u32     mask;
+        u32     ctl;
+        u32     timing;
+};
+
+struct korina_device {
+        char *name;
+        unsigned char mac[6];
+        struct net_device *dev;
+};
+
+struct mpmc_device {
+        unsigned char   state;
+        spinlock_t      lock;
+        void __iomem    *base;
+};
+
+extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
+extern unsigned char get_latch_u5(void);
+
+#endif  /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h
new file mode 100644
index 000000000..1bec6cc8a
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rc32434.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Definitions for IDT RC323434 CPU.
+ */
+
+#ifndef _ASM_RC32434_RC32434_H_
+#define _ASM_RC32434_RC32434_H_
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#define IDT_CLOCK_MULT          2
+
+/* cpu pipeline flush */
+static inline void rc32434_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+#endif  /* _ASM_RC32434_RC32434_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h
new file mode 100644
index 000000000..cda26bb9e
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
+/*
+ *  Definitions for timer registers
+ *
+ *  Copyright 2004 Philip Rischel <rischelp@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_TIMER_H
+#define __ASM_RC32434_TIMER_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define TIMER0_BASE_ADDR                0x18028000
+#define TIMER_COUNT                     3
+
+struct timer_counter {
+        u32 count;
+        u32 compare;
+        u32 ctc;                /*use CTC_ */
+};
+
+struct timer {
+        struct timer_counter tim[TIMER_COUNT];
+        u32 rcount;     /* use RCOUNT_ */
+        u32 rcompare;   /* use RCOMPARE_ */
+        u32 rtc;        /* use RTC_ */
+};
+
+#define RC32434_CTC_EN_BIT              0
+#define RC32434_CTC_TO_BIT              1
+
+/* Real time clock registers */
+#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
+#define RC32434_RTC_CE_BIT              0
+#define RC32434_RTC_TO_BIT              1
+#define RC32434_RTC_RQE_BIT             2
+
+/* Counter registers */
+#define RC32434_RCOUNT_BIT              0
+#define RC32434_RCOUNT_MSK              0x0000ffff
+#define RC32434_RCOMP_BIT               0
+#define RC32434_RCOMP_MSK               0x0000ffff
+
+#endif  /* __ASM_RC32434_TIMER_H */
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
new file mode 100644
index 000000000..e1e182300
--- /dev/null
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
+ */
+#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_watch           0
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rm/mc146818rtc.h b/arch/mips/include/asm/mach-rm/mc146818rtc.h
new file mode 100644
index 000000000..a074f4f84
--- /dev/null
+++ b/arch/mips/include/asm/mach-rm/mc146818rtc.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip with ARC epoch.
+ */
+#ifndef __ASM_MACH_RM_MC146818RTC_H
+#define __ASM_MACH_RM_MC146818RTC_H
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+#else
+#define mc146818_decode_year(year) ((year) + 1980)
+#endif
+
+#include <asm/mach-generic/mc146818rtc.h>
+
+#endif /* __ASM_MACH_RM_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
new file mode 100644
index 000000000..702235805
--- /dev/null
+++ b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
@@ -0,0 +1,49 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Sibyte are MIPS64 processors wired to a specific configuration
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          1
+#define cpu_has_ejtag           1
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        1
+#define cpu_has_mips64r2        0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h
new file mode 100644
index 000000000..157a72923
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/mach-tx39xx/ioremap.h
+ */
+#ifndef __ASM_MACH_TX39XX_IOREMAP_H
+#define __ASM_MACH_TX39XX_IOREMAP_H
+
+#include <linux/types.h>
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+        unsigned long flags)
+{
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0xff0000)
+                return (void __iomem *)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
+}
+
+#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/mangle-port.h b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
new file mode 100644
index 000000000..95be45995
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
+#define __ASM_MACH_TX39XX_MANGLE_PORT_H
+
+#if defined(CONFIG_TOSHIBA_JMR3927)
+extern unsigned long (*__swizzle_addr_b)(unsigned long port);
+#define NEEDS_TXX9_SWIZZLE_ADDR_B
+#else
+#define __swizzle_addr_b(port)  (port)
+#endif
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#define ioswabb(a, x)           (x)
+#define __mem_ioswabb(a, x)     (x)
+#define ioswabw(a, x)           le16_to_cpu((__force __le16)(x))
+#define __mem_ioswabw(a, x)     (x)
+#define ioswabl(a, x)           le32_to_cpu((__force __le32)(x))
+#define __mem_ioswabl(a, x)     (x)
+#define ioswabq(a, x)           le64_to_cpu((__force __le64)(x))
+#define __mem_ioswabq(a, x)     (x)
+
+#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/spaces.h b/arch/mips/include/asm/mach-tx39xx/spaces.h
new file mode 100644
index 000000000..151fe7a1c
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/spaces.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TX39XX_SPACES_H
+#define _ASM_TX39XX_SPACES_H
+
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0xfefe0000)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_TX39XX_SPACES_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
new file mode 100644
index 000000000..04e424725
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_llsc    1
+#define cpu_has_64bits  1
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_has_mips16          0
+#define cpu_has_mips16e2        0
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp     0
+#define cpu_has_dsp2            0
+#define cpu_has_mipsmt  0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h
new file mode 100644
index 000000000..b1f3710ac
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      include/asm-mips/mach-tx49xx/ioremap.h
+ */
+#ifndef __ASM_MACH_TX49XX_IOREMAP_H
+#define __ASM_MACH_TX49XX_IOREMAP_H
+
+#include <linux/types.h>
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+        unsigned long flags)
+{
+#ifdef CONFIG_64BIT
+#define TXX9_DIRECTMAP_BASE     0xfff000000ul
+#else
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+#endif
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0x400000)
+                return (void __iomem *)(unsigned long)(int)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >=
+                (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff);
+}
+
+#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
new file mode 100644
index 000000000..c2a0a6fa4
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_TX49XX_KMALLOC_H
+#define __ASM_MACH_TX49XX_KMALLOC_H
+
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
new file mode 100644
index 000000000..98c7abf44
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H
+#define __ASM_MACH_TX49XX_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#define ioswabb(a, x)           (x)
+#define __mem_ioswabb(a, x)     (x)
+#if defined(CONFIG_TOSHIBA_RBTX4939) && \
+        IS_ENABLED(CONFIG_SMC91X) && \
+        defined(__BIG_ENDIAN)
+#define NEEDS_TXX9_IOSWABW
+extern u16 (*ioswabw)(volatile u16 *a, u16 x);
+extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
+#else
+#define ioswabw(a, x)           le16_to_cpu((__force __le16)(x))
+#define __mem_ioswabw(a, x)     (x)
+#endif
+#define ioswabl(a, x)           le32_to_cpu((__force __le32)(x))
+#define __mem_ioswabl(a, x)     (x)
+#define ioswabq(a, x)           le64_to_cpu((__force __le64)(x))
+#define __mem_ioswabq(a, x)     (x)
+
+#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/spaces.h b/arch/mips/include/asm/mach-tx49xx/spaces.h
new file mode 100644
index 000000000..0cb10a6f4
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/spaces.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TX49XX_SPACES_H
+#define _ASM_TX49XX_SPACES_H
+
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0xfefe0000)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_TX49XX_SPACES_H */
diff --git a/arch/mips/include/asm/mach-vr41xx/irq.h b/arch/mips/include/asm/mach-vr41xx/irq.h
new file mode 100644
index 000000000..4281b2b93
--- /dev/null
+++ b/arch/mips/include/asm/mach-vr41xx/irq.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_VR41XX_IRQ_H
+#define __ASM_MACH_VR41XX_IRQ_H
+
+#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
+
+#include <asm/mach-generic/irq.h>
+
+#endif /* __ASM_MACH_VR41XX_IRQ_H */
diff --git a/arch/mips/include/asm/machine.h b/arch/mips/include/asm/machine.h
new file mode 100644
index 000000000..fc64cce27
--- /dev/null
+++ b/arch/mips/include/asm/machine.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MACHINE_H__
+#define __MIPS_ASM_MACHINE_H__
+
+#include <linux/libfdt.h>
+#include <linux/of.h>
+
+struct mips_machine {
+        const struct of_device_id *matches;
+        const void *fdt;
+        bool (*detect)(void);
+        const void *(*fixup_fdt)(const void *fdt, const void *match_data);
+        unsigned int (*measure_hpt_freq)(void);
+};
+
+extern long __mips_machines_start;
+extern long __mips_machines_end;
+
+#define MIPS_MACHINE(name)                                              \
+        static const struct mips_machine __mips_mach_##name             \
+                __used __section(".mips.machines.init")
+
+#define for_each_mips_machine(mach)                                     \
+        for ((mach) = (struct mips_machine *)&__mips_machines_start;    \
+             (mach) < (struct mips_machine *)&__mips_machines_end;      \
+             (mach)++)
+
+/**
+ * mips_machine_is_compatible() - check if a machine is compatible with an FDT
+ * @mach: the machine struct to check
+ * @fdt: the FDT to check for compatibility with
+ *
+ * Check whether the given machine @mach is compatible with the given flattened
+ * device tree @fdt, based upon the compatibility property of the root node.
+ *
+ * Return: the device id matched if any, else NULL
+ */
+static inline const struct of_device_id *
+mips_machine_is_compatible(const struct mips_machine *mach, const void *fdt)
+{
+        const struct of_device_id *match;
+
+        if (!mach->matches)
+                return NULL;
+
+        for (match = mach->matches; match->compatible[0]; match++) {
+                if (fdt_node_check_compatible(fdt, 0, match->compatible) == 0)
+                        return match;
+        }
+
+        return NULL;
+}
+
+/**
+ * struct mips_fdt_fixup - Describe a fixup to apply to an FDT
+ * @apply: applies the fixup to @fdt, returns zero on success else -errno
+ * @description: a short description of the fixup
+ *
+ * Describes a fixup applied to an FDT blob by the @apply function. The
+ * @description field provides a short description of the fixup intended for
+ * use in error messages if the @apply function returns non-zero.
+ */
+struct mips_fdt_fixup {
+        int (*apply)(void *fdt);
+        const char *description;
+};
+
+/**
+ * apply_mips_fdt_fixups() - apply fixups to an FDT blob
+ * @fdt_out: buffer in which to place the fixed-up FDT
+ * @fdt_out_size: the size of the @fdt_out buffer
+ * @fdt_in: the FDT blob
+ * @fixups: pointer to an array of fixups to be applied
+ *
+ * Loop through the array of fixups pointed to by @fixups, calling the apply
+ * function on each until either one returns an error or we reach the end of
+ * the list as indicated by an entry with a NULL apply field.
+ *
+ * Return: zero on success, else -errno
+ */
+extern int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
+                                        const void *fdt_in,
+                                        const struct mips_fdt_fixup *fixups);
+
+#endif /* __MIPS_ASM_MACHINE_H__ */
diff --git a/arch/mips/include/asm/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h
new file mode 100644
index 000000000..cbf5cec34
--- /dev/null
+++ b/arch/mips/include/asm/mc146818-time.h
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_MC146818_TIME_H
+#define __ASM_MC146818_TIME_H
+
+#include <linux/bcd.h>
+#include <linux/mc146818rtc.h>
+#include <linux/time.h>
+
+/*
+ * For check timing call set_rtc_mmss() 500ms; used in timer interrupt.
+ */
+#define USEC_AFTER      500000
+#define USEC_BEFORE     500000
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ *      sets the minutes. Usually you'll only notice that after reboot!
+ */
+static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
+{
+        int real_seconds, real_minutes, cmos_minutes;
+        unsigned char save_control, save_freq_select;
+        int retval = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
+        CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+
+        save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
+        CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+
+        cmos_minutes = CMOS_READ(RTC_MINUTES);
+        if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
+                cmos_minutes = bcd2bin(cmos_minutes);
+
+        /*
+         * since we're only adjusting minutes and seconds,
+         * don't interfere with hour overflow. This avoids
+         * messing with unknown time zones but requires your
+         * RTC not to be off by more than 15 minutes
+         */
+        real_seconds = nowtime % 60;
+        real_minutes = nowtime / 60;
+        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
+                real_minutes += 30;             /* correct for half hour time zone */
+        real_minutes %= 60;
+
+        if (abs(real_minutes - cmos_minutes) < 30) {
+                if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                        real_seconds = bin2bcd(real_seconds);
+                        real_minutes = bin2bcd(real_minutes);
+                }
+                CMOS_WRITE(real_seconds, RTC_SECONDS);
+                CMOS_WRITE(real_minutes, RTC_MINUTES);
+        } else {
+                printk_once(KERN_NOTICE
+                       "set_rtc_mmss: can't update from %d to %d\n",
+                       cmos_minutes, real_minutes);
+                retval = -1;
+        }
+
+        /* The following flags have to be released exactly in this order,
+         * otherwise the DS12887 (popular MC146818A clone with integrated
+         * battery and quartz) will not reset the oscillator and will not
+         * update precisely 500 ms later. You won't find this mentioned in
+         * the Dallas Semiconductor data sheets, but who believes data
+         * sheets anyway ...                           -- Markus Kuhn
+         */
+        CMOS_WRITE(save_control, RTC_CONTROL);
+        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
+        return retval;
+}
+
+static inline time64_t mc146818_get_cmos_time(void)
+{
+        unsigned int year, mon, day, hour, min, sec;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+
+        do {
+                sec = CMOS_READ(RTC_SECONDS);
+                min = CMOS_READ(RTC_MINUTES);
+                hour = CMOS_READ(RTC_HOURS);
+                day = CMOS_READ(RTC_DAY_OF_MONTH);
+                mon = CMOS_READ(RTC_MONTH);
+                year = CMOS_READ(RTC_YEAR);
+        } while (sec != CMOS_READ(RTC_SECONDS));
+
+        if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                sec = bcd2bin(sec);
+                min = bcd2bin(min);
+                hour = bcd2bin(hour);
+                day = bcd2bin(day);
+                mon = bcd2bin(mon);
+                year = bcd2bin(year);
+        }
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        year = mc146818_decode_year(year);
+
+        return mktime64(year, mon, day, hour, min, sec);
+}
+
+#endif /* __ASM_MC146818_TIME_H */
diff --git a/arch/mips/include/asm/mc146818rtc.h b/arch/mips/include/asm/mc146818rtc.h
new file mode 100644
index 000000000..68b4da6d5
--- /dev/null
+++ b/arch/mips/include/asm/mc146818rtc.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2000 Ralf Baechle
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <mc146818rtc.h>
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
new file mode 100644
index 000000000..5368891d4
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -0,0 +1,430 @@
+/*
+ * Bonito Register Map
+ *
+ * This file is the original bonito.h from Algorithmics with minor changes
+ * to fit into linux.
+ *
+ * Copyright (c) 1999 Algorithmics Ltd
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2001 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * Algorithmics gives permission for anyone to use and modify this file
+ * without any obligation or license condition except that you retain
+ * this copyright message in any source redistribution in whole or part.
+ *
+ */
+
+/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
+/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
+
+#ifndef _ASM_MIPS_BOARDS_BONITO64_H
+#define _ASM_MIPS_BOARDS_BONITO64_H
+
+#ifdef __ASSEMBLY__
+
+/* offsets from base register */
+#define BONITO(x)       (x)
+
+#else
+
+/*
+ * Algorithmics Bonito64 system controller register base.
+ */
+extern unsigned long _pcictrl_bonito;
+extern unsigned long _pcictrl_bonito_pcicfg;
+
+#define BONITO(x)               *(volatile u32 *)(_pcictrl_bonito + (x))
+
+#endif /* __ASSEMBLY__ */
+
+
+#define BONITO_BOOT_BASE                0x1fc00000
+#define BONITO_BOOT_SIZE                0x00100000
+#define BONITO_BOOT_TOP                 (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
+#define BONITO_FLASH_BASE               0x1c000000
+#define BONITO_FLASH_SIZE               0x03000000
+#define BONITO_FLASH_TOP                (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
+#define BONITO_SOCKET_BASE              0x1f800000
+#define BONITO_SOCKET_SIZE              0x00400000
+#define BONITO_SOCKET_TOP               (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
+#define BONITO_REG_BASE                 0x1fe00000
+#define BONITO_REG_SIZE                 0x00040000
+#define BONITO_REG_TOP                  (BONITO_REG_BASE+BONITO_REG_SIZE-1)
+#define BONITO_DEV_BASE                 0x1ff00000
+#define BONITO_DEV_SIZE                 0x00100000
+#define BONITO_DEV_TOP                  (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
+#define BONITO_PCILO_BASE               0x10000000
+#define BONITO_PCILO_SIZE               0x0c000000
+#define BONITO_PCILO_TOP                (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
+#define BONITO_PCILO0_BASE              0x10000000
+#define BONITO_PCILO1_BASE              0x14000000
+#define BONITO_PCILO2_BASE              0x18000000
+#define BONITO_PCIHI_BASE               0x20000000
+#define BONITO_PCIHI_SIZE               0x20000000
+#define BONITO_PCIHI_TOP                (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
+#define BONITO_PCIIO_BASE               0x1fd00000
+#define BONITO_PCIIO_SIZE               0x00100000
+#define BONITO_PCIIO_TOP                (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
+#define BONITO_PCICFG_BASE              0x1fe80000
+#define BONITO_PCICFG_SIZE              0x00080000
+#define BONITO_PCICFG_TOP               (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
+
+
+/* Bonito Register Bases */
+
+#define BONITO_PCICONFIGBASE            0x00
+#define BONITO_REGBASE                  0x100
+
+
+/* PCI Configuration  Registers */
+
+#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
+#define BONITO_PCIDID                   BONITO_PCI_REG(0x00)
+#define BONITO_PCICMD                   BONITO_PCI_REG(0x04)
+#define BONITO_PCICLASS                 BONITO_PCI_REG(0x08)
+#define BONITO_PCILTIMER                BONITO_PCI_REG(0x0c)
+#define BONITO_PCIBASE0                 BONITO_PCI_REG(0x10)
+#define BONITO_PCIBASE1                 BONITO_PCI_REG(0x14)
+#define BONITO_PCIBASE2                 BONITO_PCI_REG(0x18)
+#define BONITO_PCIEXPRBASE              BONITO_PCI_REG(0x30)
+#define BONITO_PCIINT                   BONITO_PCI_REG(0x3c)
+
+#define BONITO_PCICMD_PERR_CLR          0x80000000
+#define BONITO_PCICMD_SERR_CLR          0x40000000
+#define BONITO_PCICMD_MABORT_CLR        0x20000000
+#define BONITO_PCICMD_MTABORT_CLR       0x10000000
+#define BONITO_PCICMD_TABORT_CLR        0x08000000
+#define BONITO_PCICMD_MPERR_CLR         0x01000000
+#define BONITO_PCICMD_PERRRESPEN        0x00000040
+#define BONITO_PCICMD_ASTEPEN           0x00000080
+#define BONITO_PCICMD_SERREN            0x00000100
+#define BONITO_PCILTIMER_BUSLATENCY     0x0000ff00
+#define BONITO_PCILTIMER_BUSLATENCY_SHIFT       8
+
+
+
+
+/* 1. Bonito h/w Configuration */
+/* Power on register */
+
+#define BONITO_BONPONCFG                BONITO(BONITO_REGBASE + 0x00)
+
+#define BONITO_BONPONCFG_SYSCONTROLLERRD        0x00040000
+#define BONITO_BONPONCFG_ROMCS1SAMP     0x00020000
+#define BONITO_BONPONCFG_ROMCS0SAMP     0x00010000
+#define BONITO_BONPONCFG_CPUBIGEND      0x00004000
+/* Added by RPF 11-9-00 */
+#define BONITO_BONPONCFG_BURSTORDER     0x00001000
+/* --- */
+#define BONITO_BONPONCFG_CPUPARITY      0x00002000
+#define BONITO_BONPONCFG_CPUTYPE        0x00000007
+#define BONITO_BONPONCFG_CPUTYPE_SHIFT  0
+#define BONITO_BONPONCFG_PCIRESET_OUT   0x00000008
+#define BONITO_BONPONCFG_IS_ARBITER     0x00000010
+#define BONITO_BONPONCFG_ROMBOOT        0x000000c0
+#define BONITO_BONPONCFG_ROMBOOT_SHIFT  6
+
+#define BONITO_BONPONCFG_ROMBOOT_FLASH  (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SDRAM  (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_CPURESET       (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+
+#define BONITO_BONPONCFG_ROMCS0WIDTH    0x00000100
+#define BONITO_BONPONCFG_ROMCS1WIDTH    0x00000200
+#define BONITO_BONPONCFG_ROMCS0FAST     0x00000400
+#define BONITO_BONPONCFG_ROMCS1FAST     0x00000800
+#define BONITO_BONPONCFG_CONFIG_DIS     0x00000020
+
+
+/* Other Bonito configuration */
+
+#define BONITO_BONGENCFG_OFFSET         0x4
+#define BONITO_BONGENCFG                BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
+
+#define BONITO_BONGENCFG_DEBUGMODE      0x00000001
+#define BONITO_BONGENCFG_SNOOPEN        0x00000002
+#define BONITO_BONGENCFG_CPUSELFRESET   0x00000004
+
+#define BONITO_BONGENCFG_FORCE_IRQA     0x00000008
+#define BONITO_BONGENCFG_IRQA_ISOUT     0x00000010
+#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
+#define BONITO_BONGENCFG_BYTESWAP       0x00000040
+
+#define BONITO_BONGENCFG_UNCACHED       0x00000080
+#define BONITO_BONGENCFG_PREFETCHEN     0x00000100
+#define BONITO_BONGENCFG_WBEHINDEN      0x00000200
+#define BONITO_BONGENCFG_CACHEALG       0x00000c00
+#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
+#define BONITO_BONGENCFG_PCIQUEUE       0x00001000
+#define BONITO_BONGENCFG_CACHESTOP      0x00002000
+#define BONITO_BONGENCFG_MSTRBYTESWAP   0x00004000
+#define BONITO_BONGENCFG_BUSERREN       0x00008000
+#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
+#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT       0x00020000
+
+/* 2. IO & IDE configuration */
+
+#define BONITO_IODEVCFG                 BONITO(BONITO_REGBASE + 0x08)
+
+/* 3. IO & IDE configuration */
+
+#define BONITO_SDCFG                    BONITO(BONITO_REGBASE + 0x0c)
+
+/* 4. PCI address map control */
+
+#define BONITO_PCIMAP                   BONITO(BONITO_REGBASE + 0x10)
+#define BONITO_PCIMEMBASECFG            BONITO(BONITO_REGBASE + 0x14)
+#define BONITO_PCIMAP_CFG               BONITO(BONITO_REGBASE + 0x18)
+
+/* 5. ICU & GPIO regs */
+
+/* GPIO Regs - r/w */
+
+#define BONITO_GPIODATA_OFFSET          0x1c
+#define BONITO_GPIODATA                 BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
+#define BONITO_GPIOIE                   BONITO(BONITO_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define BONITO_INTEDGE                  BONITO(BONITO_REGBASE + 0x24)
+#define BONITO_INTSTEER                 BONITO(BONITO_REGBASE + 0x28)
+#define BONITO_INTPOL                   BONITO(BONITO_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define BONITO_INTENSET                 BONITO(BONITO_REGBASE + 0x30)
+#define BONITO_INTENCLR                 BONITO(BONITO_REGBASE + 0x34)
+#define BONITO_INTEN                    BONITO(BONITO_REGBASE + 0x38)
+#define BONITO_INTISR                   BONITO(BONITO_REGBASE + 0x3c)
+
+/* PCI mail boxes */
+
+#define BONITO_PCIMAIL0_OFFSET          0x40
+#define BONITO_PCIMAIL1_OFFSET          0x44
+#define BONITO_PCIMAIL2_OFFSET          0x48
+#define BONITO_PCIMAIL3_OFFSET          0x4c
+#define BONITO_PCIMAIL0                 BONITO(BONITO_REGBASE + 0x40)
+#define BONITO_PCIMAIL1                 BONITO(BONITO_REGBASE + 0x44)
+#define BONITO_PCIMAIL2                 BONITO(BONITO_REGBASE + 0x48)
+#define BONITO_PCIMAIL3                 BONITO(BONITO_REGBASE + 0x4c)
+
+
+/* 6. PCI cache */
+
+#define BONITO_PCICACHECTRL             BONITO(BONITO_REGBASE + 0x50)
+#define BONITO_PCICACHETAG              BONITO(BONITO_REGBASE + 0x54)
+
+#define BONITO_PCIBADADDR               BONITO(BONITO_REGBASE + 0x58)
+#define BONITO_PCIMSTAT                 BONITO(BONITO_REGBASE + 0x5c)
+
+
+/*
+#define BONITO_PCIRDPOST                BONITO(BONITO_REGBASE + 0x60)
+#define BONITO_PCIDATA                  BONITO(BONITO_REGBASE + 0x64)
+*/
+
+/* 7. IDE DMA & Copier */
+
+#define BONITO_CONFIGBASE               0x000
+#define BONITO_BONITOBASE               0x100
+#define BONITO_LDMABASE                 0x200
+#define BONITO_COPBASE                  0x300
+#define BONITO_REG_BLOCKMASK            0x300
+
+#define BONITO_LDMACTRL                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMASTAT                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMAADDR                 BONITO(BONITO_LDMABASE + 0x4)
+#define BONITO_LDMAGO                   BONITO(BONITO_LDMABASE + 0x8)
+#define BONITO_LDMADATA                 BONITO(BONITO_LDMABASE + 0xc)
+
+#define BONITO_COPCTRL                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPSTAT                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPPADDR                 BONITO(BONITO_COPBASE + 0x4)
+#define BONITO_COPDADDR                 BONITO(BONITO_COPBASE + 0x8)
+#define BONITO_COPGO                    BONITO(BONITO_COPBASE + 0xc)
+
+
+/* ###### Bit Definitions for individual Registers #### */
+
+/* Gen DMA. */
+
+#define BONITO_IDECOPDADDR_DMA_DADDR    0x0ffffffc
+#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT      2
+#define BONITO_IDECOPPADDR_DMA_PADDR    0xfffffffc
+#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT      2
+#define BONITO_IDECOPGO_DMA_SIZE        0x0000fffe
+#define BONITO_IDECOPGO_DMA_SIZE_SHIFT  0
+#define BONITO_IDECOPGO_DMA_WRITE       0x00010000
+#define BONITO_IDECOPGO_DMAWCOUNT       0x000f0000
+#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
+
+#define BONITO_IDECOPCTRL_DMA_STARTBIT  0x80000000
+#define BONITO_IDECOPCTRL_DMA_RSTBIT    0x40000000
+
+/* DRAM - sdCfg */
+
+#define BONITO_SDCFG_AROWBITS           0x00000003
+#define BONITO_SDCFG_AROWBITS_SHIFT     0
+#define BONITO_SDCFG_ACOLBITS           0x0000000c
+#define BONITO_SDCFG_ACOLBITS_SHIFT     2
+#define BONITO_SDCFG_ABANKBIT           0x00000010
+#define BONITO_SDCFG_ASIDES             0x00000020
+#define BONITO_SDCFG_AABSENT            0x00000040
+#define BONITO_SDCFG_AWIDTH64           0x00000080
+
+#define BONITO_SDCFG_BROWBITS           0x00000300
+#define BONITO_SDCFG_BROWBITS_SHIFT     8
+#define BONITO_SDCFG_BCOLBITS           0x00000c00
+#define BONITO_SDCFG_BCOLBITS_SHIFT     10
+#define BONITO_SDCFG_BBANKBIT           0x00001000
+#define BONITO_SDCFG_BSIDES             0x00002000
+#define BONITO_SDCFG_BABSENT            0x00004000
+#define BONITO_SDCFG_BWIDTH64           0x00008000
+
+#define BONITO_SDCFG_EXTRDDATA          0x00010000
+#define BONITO_SDCFG_EXTRASCAS          0x00020000
+#define BONITO_SDCFG_EXTPRECH           0x00040000
+#define BONITO_SDCFG_EXTRASWIDTH        0x00180000
+#define BONITO_SDCFG_EXTRASWIDTH_SHIFT  19
+/* Changed by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMMODESET        0x00200000
+/* --- */
+#define BONITO_SDCFG_DRAMEXTREGS        0x00400000
+#define BONITO_SDCFG_DRAMPARITY         0x00800000
+/* Added by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMBURSTLEN       0x03000000
+#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
+#define BONITO_SDCFG_DRAMMODESET_DONE   0x80000000
+/* --- */
+
+/* PCI Cache - pciCacheCtrl */
+
+#define BONITO_PCICACHECTRL_CACHECMD    0x00000007
+#define BONITO_PCICACHECTRL_CACHECMD_SHIFT      0
+#define BONITO_PCICACHECTRL_CACHECMDLINE        0x00000018
+#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT  3
+#define BONITO_PCICACHECTRL_CMDEXEC     0x00000020
+
+#define BONITO_PCICACHECTRL_IOBCCOH_PRES        0x00000100
+#define BONITO_PCICACHECTRL_IOBCCOH_EN  0x00000200
+#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
+#define BONITO_PCICACHECTRL_CPUCOH_EN   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_CS0     0x00000001
+#define BONITO_IODEVCFG_SPEEDBIT_CS0    0x00000002
+#define BONITO_IODEVCFG_MOREABITS_CS0   0x00000004
+
+#define BONITO_IODEVCFG_BUFFBIT_CS1     0x00000008
+#define BONITO_IODEVCFG_SPEEDBIT_CS1    0x00000010
+#define BONITO_IODEVCFG_MOREABITS_CS1   0x00000020
+
+#define BONITO_IODEVCFG_BUFFBIT_CS2     0x00000040
+#define BONITO_IODEVCFG_SPEEDBIT_CS2    0x00000080
+#define BONITO_IODEVCFG_MOREABITS_CS2   0x00000100
+
+#define BONITO_IODEVCFG_BUFFBIT_CS3     0x00000200
+#define BONITO_IODEVCFG_SPEEDBIT_CS3    0x00000400
+#define BONITO_IODEVCFG_MOREABITS_CS3   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_IDE     0x00001000
+#define BONITO_IODEVCFG_SPEEDBIT_IDE    0x00002000
+#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
+#define BONITO_IODEVCFG_MODEBIT_IDE     0x00008000
+#define BONITO_IODEVCFG_DMAON_IDE       0x001f0000
+#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
+#define BONITO_IODEVCFG_DMAOFF_IDE      0x01e00000
+#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT        21
+#define BONITO_IODEVCFG_EPROMSPLIT      0x02000000
+/* Added by RPF 11-9-00 */
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD  0xfc000000
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
+/* --- */
+
+/* gpio */
+#define BONITO_GPIO_GPIOW               0x000003ff
+#define BONITO_GPIO_GPIOW_SHIFT         0
+#define BONITO_GPIO_GPIOR               0x01ff0000
+#define BONITO_GPIO_GPIOR_SHIFT         16
+#define BONITO_GPIO_GPINR               0xfe000000
+#define BONITO_GPIO_GPINR_SHIFT         25
+#define BONITO_GPIO_IOW(N)              (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
+#define BONITO_GPIO_IOR(N)              (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
+#define BONITO_GPIO_INR(N)              (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
+
+/* ICU */
+#define BONITO_ICU_MBOXES               0x0000000f
+#define BONITO_ICU_MBOXES_SHIFT         0
+#define BONITO_ICU_DMARDY               0x00000010
+#define BONITO_ICU_DMAEMPTY             0x00000020
+#define BONITO_ICU_COPYRDY              0x00000040
+#define BONITO_ICU_COPYEMPTY            0x00000080
+#define BONITO_ICU_COPYERR              0x00000100
+#define BONITO_ICU_PCIIRQ               0x00000200
+#define BONITO_ICU_MASTERERR            0x00000400
+#define BONITO_ICU_SYSTEMERR            0x00000800
+#define BONITO_ICU_DRAMPERR             0x00001000
+#define BONITO_ICU_RETRYERR             0x00002000
+#define BONITO_ICU_GPIOS                0x01ff0000
+#define BONITO_ICU_GPIOS_SHIFT          16
+#define BONITO_ICU_GPINS                0x7e000000
+#define BONITO_ICU_GPINS_SHIFT          25
+#define BONITO_ICU_MBOX(N)              (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
+#define BONITO_ICU_GPIO(N)              (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
+#define BONITO_ICU_GPIN(N)              (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
+
+/* pcimap */
+
+#define BONITO_PCIMAP_PCIMAP_LO0        0x0000003f
+#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT  0
+#define BONITO_PCIMAP_PCIMAP_LO1        0x00000fc0
+#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT  6
+#define BONITO_PCIMAP_PCIMAP_LO2        0x0003f000
+#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT  12
+#define BONITO_PCIMAP_PCIMAP_2          0x00040000
+#define BONITO_PCIMAP_WIN(WIN, ADDR)    ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#define BONITO_PCIMAP_WINSIZE           (1<<26)
+#define BONITO_PCIMAP_WINOFFSET(ADDR)   ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
+#define BONITO_PCIMAP_WINBASE(ADDR)     ((ADDR) << 26)
+
+/* pcimembaseCfg */
+
+#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK      0x0000001f
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT        0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS     0x000003e0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT       5
+#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED    0x00000400
+#define BONITO_PCIMEMBASECFG_MEMBASE0_IO        0x00000800
+
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK      0x0001f000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT        12
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS     0x003e0000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT       17
+#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED    0x00400000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_IO        0x00800000
+
+#define BONITO_PCIMEMBASECFG_ASHIFT     23
+#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
+#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)     (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
+#define BONITO_PCIMEMBASECFGBASE(WIN, BASE)     (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
+
+#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
+
+
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+
+#define BONITO_PCITOPHYS(WIN, ADDR, CFG)          ( \
+                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
+                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
+                                                )
+
+/* PCICmd */
+
+#define BONITO_PCICMD_MEMEN             0x00000002
+#define BONITO_PCICMD_MSTREN            0x00000004
+
+
+#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
new file mode 100644
index 000000000..c904c2455
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -0,0 +1,79 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Defines of the MIPS boards specific address-MAP, registers, etc.
+ *
+ * Copyright (C) 2000,2012 MIPS Technologies, Inc.
+ * All rights reserved.
+ * Authors: Carsten Langgaard <carstenl@mips.com>
+ *          Steven J. Hill <sjhill@mips.com>
+ */
+#ifndef __ASM_MIPS_BOARDS_GENERIC_H
+#define __ASM_MIPS_BOARDS_GENERIC_H
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+#include <asm/mips-boards/bonito64.h>
+
+/*
+ * Display register base.
+ */
+#define ASCII_DISPLAY_WORD_BASE    0x1f000410
+#define ASCII_DISPLAY_POS_BASE     0x1f000418
+
+/*
+ * Revision register.
+ */
+#define MIPS_REVISION_REG                  0x1fc00010
+#define MIPS_REVISION_CORID_QED_RM5261     0
+#define MIPS_REVISION_CORID_CORE_LV        1
+#define MIPS_REVISION_CORID_BONITO64       2
+#define MIPS_REVISION_CORID_CORE_20K       3
+#define MIPS_REVISION_CORID_CORE_FPGA      4
+#define MIPS_REVISION_CORID_CORE_MSC       5
+#define MIPS_REVISION_CORID_CORE_EMUL      6
+#define MIPS_REVISION_CORID_CORE_FPGA2     7
+#define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
+#define MIPS_REVISION_CORID_CORE_24K       10
+#define MIPS_REVISION_CORID_CORE_FPGA4     11
+#define MIPS_REVISION_CORID_CORE_FPGA5     12
+
+/**** Artificial corid defines ****/
+/*
+ *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
+ *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
+ */
+#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
+
+#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
+
+#define MIPS_REVISION_SCON_OTHER           0
+#define MIPS_REVISION_SCON_SOCITSC         1
+#define MIPS_REVISION_SCON_SOCITSCP        2
+
+/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
+#define MIPS_REVISION_SCON_UNKNOWN         -1
+#define MIPS_REVISION_SCON_GT64120         -2
+#define MIPS_REVISION_SCON_BONITO          -3
+#define MIPS_REVISION_SCON_BRTL            -4
+#define MIPS_REVISION_SCON_SOCIT           -5
+#define MIPS_REVISION_SCON_ROCIT           -6
+
+#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
+
+extern int mips_revision_sconid;
+
+#ifdef CONFIG_PCI
+extern void mips_pcibios_init(void);
+#else
+#define mips_pcibios_init() do { } while (0)
+#endif
+
+extern void mips_scroll_message(void);
+extern void mips_display_message(const char *str);
+
+#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/arch/mips/include/asm/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h
new file mode 100644
index 000000000..f93aa5ee2
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/launch.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *
+ */
+
+#ifndef _ASSEMBLER_
+
+struct cpulaunch {
+    unsigned long       pc;
+    unsigned long       gp;
+    unsigned long       sp;
+    unsigned long       a0;
+    unsigned long       _pad[3]; /* pad to cache line size to avoid thrashing */
+    unsigned long       flags;
+};
+
+#else
+
+#define LOG2CPULAUNCH   5
+#define LAUNCH_PC       0
+#define LAUNCH_GP       4
+#define LAUNCH_SP       8
+#define LAUNCH_A0       12
+#define LAUNCH_FLAGS    28
+
+#endif
+
+#define LAUNCH_FREADY   1
+#define LAUNCH_FGO      2
+#define LAUNCH_FGONE    4
+
+#define CPULAUNCH       0x00000f00
+#define NCPULAUNCH      8
+
+/* Polling period in count cycles for secondary CPU's */
+#define LAUNCHPERIOD    10000
diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
new file mode 100644
index 000000000..254be3d62
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * Defines of the Malta board specific address-MAP, registers, etc.
+ */
+#ifndef __ASM_MIPS_BOARDS_MALTA_H
+#define __ASM_MIPS_BOARDS_MALTA_H
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mips-boards/msc01_pci.h>
+#include <asm/gt64120.h>
+
+/* Mips interrupt controller found in SOCit variations */
+#define MIPS_MSC01_IC_REG_BASE          0x1bc40000
+#define MIPS_SOCITSC_IC_REG_BASE        0x1ffa0000
+
+/*
+ * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
+ * Bonito system controllers.
+ */
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
+#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        addr = GT_READ(reg);
+        return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        MSC_READ(reg, addr);
+        return (unsigned long) ioremap(addr, 0x10000);
+}
+
+/*
+ * GCMP Specific definitions
+ */
+#define GCMP_BASE_ADDR                  0x1fbf8000
+#define GCMP_ADDRSPACE_SZ               (256 * 1024)
+
+/*
+ * GIC Specific definitions
+ */
+#define GIC_BASE_ADDR                   0x1bdc0000
+#define GIC_ADDRSPACE_SZ                (128 * 1024)
+
+/*
+ * CPC Specific definitions
+ */
+#define CPC_BASE_ADDR                   0x1bde0000
+
+/*
+ * MSC01 BIU Specific definitions
+ * FIXME : These should be elsewhere ?
+ */
+#define MSC01_BIU_REG_BASE              0x1bc80000
+#define MSC01_BIU_ADDRSPACE_SZ          (256 * 1024)
+#define MSC01_SC_CFG_OFS                0x0110
+#define MSC01_SC_CFG_GICPRES_MSK        0x00000004
+#define MSC01_SC_CFG_GICPRES_SHF        2
+#define MSC01_SC_CFG_GICENA_SHF         3
+
+/*
+ * Malta RTC-device indirect register access.
+ */
+#define MALTA_RTC_ADR_REG       0x70
+#define MALTA_RTC_DAT_REG       0x71
+
+/*
+ * Malta SMSC FDC37M817 Super I/O Controller register.
+ */
+#define SMSC_CONFIG_REG         0x3f0
+#define SMSC_DATA_REG           0x3f1
+
+#define SMSC_CONFIG_DEVNUM      0x7
+#define SMSC_CONFIG_ACTIVATE    0x30
+#define SMSC_CONFIG_ENTER       0x55
+#define SMSC_CONFIG_EXIT        0xaa
+
+#define SMSC_CONFIG_DEVNUM_FLOPPY     0
+
+#define SMSC_CONFIG_ACTIVATE_ENABLE   1
+
+#define SMSC_WRITE(x, a)     outb(x, a)
+
+#define MALTA_JMPRS_REG         0x1f000210
+
+extern void __init *malta_dt_shim(void *fdt);
+
+#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
new file mode 100644
index 000000000..817698abf
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
+ *      Carsten Langgaard <carstenl@mips.com>
+ *      Steven J. Hill <sjhill@mips.com>
+ */
+#ifndef _MIPS_MALTAINT_H
+#define _MIPS_MALTAINT_H
+
+/*
+ * Interrupts 0..15 are used for Malta ISA compatible interrupts
+ */
+#define MALTA_INT_BASE          0
+
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0         0
+#define MIPSCPU_INT_SW1         1
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
+#define MIPSCPU_INT_GIC         MIPSCPU_INT_MB0 /* GIC chained interrupt */
+#define MIPSCPU_INT_MB1         3
+#define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
+#define MIPSCPU_INT_MB2         4
+#define MIPSCPU_INT_MB3         5
+#define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
+#define MIPSCPU_INT_MB4         6
+#define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
+
+/*
+ * Interrupts 96..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE         96
+
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR          0
+#define MSC01C_INT_PCI          1
+
+/*
+ * Interrupts 96..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE         96
+
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0          1
+#define MSC01E_INT_SW1          2
+#define MSC01E_INT_MB0          3
+#define MSC01E_INT_I8259A       MSC01E_INT_MB0
+#define MSC01E_INT_MB1          4
+#define MSC01E_INT_SMI          MSC01E_INT_MB1
+#define MSC01E_INT_MB2          5
+#define MSC01E_INT_MB3          6
+#define MSC01E_INT_COREHI       MSC01E_INT_MB3
+#define MSC01E_INT_MB4          7
+#define MSC01E_INT_CORELO       MSC01E_INT_MB4
+#define MSC01E_INT_TMR          8
+#define MSC01E_INT_PCI          9
+#define MSC01E_INT_PERFCTR      10
+#define MSC01E_INT_CPUCTR       11
+
+#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-boards/msc01_pci.h b/arch/mips/include/asm/mips-boards/msc01_pci.h
new file mode 100644
index 000000000..e036b7dd6
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/msc01_pci.h
@@ -0,0 +1,258 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
+#define __ASM_MIPS_BOARDS_MSC01_PCI_H
+
+/*
+ * Register offset addresses
+ */
+
+#define MSC01_PCI_ID_OFS                0x0000
+#define MSC01_PCI_SC2PMBASL_OFS         0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS         0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS         0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS        0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS        0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS        0x0268
+#define MSC01_PCI_P2SCMSKL_OFS          0x0308
+#define MSC01_PCI_P2SCMAPL_OFS          0x0318
+#define MSC01_PCI_INTCFG_OFS            0x0600
+#define MSC01_PCI_INTSTAT_OFS           0x0608
+#define MSC01_PCI_CFGADDR_OFS           0x0610
+#define MSC01_PCI_CFGDATA_OFS           0x0618
+#define MSC01_PCI_IACK_OFS              0x0620
+#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
+#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_BAR0_OFS              0x2220
+#define MSC01_PCI_CFG_OFS               0x2380
+#define MSC01_PCI_SWAP_OFS              0x2388
+
+
+/*****************************************************************************
+ * Register encodings
+ ****************************************************************************/
+
+#define MSC01_PCI_ID_ID_SHF             16
+#define MSC01_PCI_ID_ID_MSK             0x00ff0000
+#define MSC01_PCI_ID_ID_HOSTBRIDGE      82
+#define MSC01_PCI_ID_MAR_SHF            8
+#define MSC01_PCI_ID_MAR_MSK            0x0000ff00
+#define MSC01_PCI_ID_MIR_SHF            0
+#define MSC01_PCI_ID_MIR_MSK            0x000000ff
+
+#define MSC01_PCI_SC2PMBASL_BAS_SHF     24
+#define MSC01_PCI_SC2PMBASL_BAS_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMSKL_MSK_SHF     24
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMAPL_MAP_SHF     24
+#define MSC01_PCI_SC2PMMAPL_MAP_MSK     0xff000000
+
+#define MSC01_PCI_SC2PIOBASL_BAS_SHF    24
+#define MSC01_PCI_SC2PIOBASL_BAS_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMSKL_MSK_SHF    24
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMAPL_MAP_SHF    24
+#define MSC01_PCI_SC2PIOMAPL_MAP_MSK    0xff000000
+
+#define MSC01_PCI_P2SCMSKL_MSK_SHF      24
+#define MSC01_PCI_P2SCMSKL_MSK_MSK      0xff000000
+
+#define MSC01_PCI_P2SCMAPL_MAP_SHF      24
+#define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
+
+#define MSC01_PCI_INTCFG_RST_SHF        10
+#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
+#define MSC01_PCI_INTCFG_MWE_SHF        9
+#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
+#define MSC01_PCI_INTCFG_DTO_SHF        8
+#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
+#define MSC01_PCI_INTCFG_MA_SHF         7
+#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
+#define MSC01_PCI_INTCFG_TA_SHF         6
+#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
+#define MSC01_PCI_INTCFG_RTY_SHF        5
+#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
+#define MSC01_PCI_INTCFG_MWP_SHF        4
+#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
+#define MSC01_PCI_INTCFG_MRP_SHF        3
+#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
+#define MSC01_PCI_INTCFG_SWP_SHF        2
+#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
+#define MSC01_PCI_INTCFG_SRP_SHF        1
+#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
+#define MSC01_PCI_INTCFG_SE_SHF         0
+#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
+
+#define MSC01_PCI_INTSTAT_RST_SHF       10
+#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
+#define MSC01_PCI_INTSTAT_MWE_SHF       9
+#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
+#define MSC01_PCI_INTSTAT_DTO_SHF       8
+#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
+#define MSC01_PCI_INTSTAT_MA_SHF        7
+#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
+#define MSC01_PCI_INTSTAT_TA_SHF        6
+#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
+#define MSC01_PCI_INTSTAT_RTY_SHF       5
+#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
+#define MSC01_PCI_INTSTAT_MWP_SHF       4
+#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
+#define MSC01_PCI_INTSTAT_MRP_SHF       3
+#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
+#define MSC01_PCI_INTSTAT_SWP_SHF       2
+#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
+#define MSC01_PCI_INTSTAT_SRP_SHF       1
+#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
+#define MSC01_PCI_INTSTAT_SE_SHF        0
+#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF      16
+#define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
+#define MSC01_PCI_CFGADDR_DNUM_SHF      11
+#define MSC01_PCI_CFGADDR_DNUM_MSK      0x0000f800
+#define MSC01_PCI_CFGADDR_FNUM_SHF      8
+#define MSC01_PCI_CFGADDR_FNUM_MSK      0x00000700
+#define MSC01_PCI_CFGADDR_RNUM_SHF      2
+#define MSC01_PCI_CFGADDR_RNUM_MSK      0x000000fc
+
+#define MSC01_PCI_CFGDATA_DATA_SHF      0
+#define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
+
+/* The defines below are ONLY valid for a MEM bar! */
+#define MSC01_PCI_BAR0_SIZE_SHF         4
+#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
+#define MSC01_PCI_BAR0_P_SHF            3
+#define MSC01_PCI_BAR0_P_MSK            0x00000008
+#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_D_SHF            1
+#define MSC01_PCI_BAR0_D_MSK            0x00000006
+#define MSC01_PCI_BAR0_T_SHF            0
+#define MSC01_PCI_BAR0_T_MSK            0x00000001
+#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
+
+
+#define MSC01_PCI_CFG_RA_SHF            17
+#define MSC01_PCI_CFG_RA_MSK            0x00020000
+#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_G_SHF             16
+#define MSC01_PCI_CFG_G_MSK             0x00010000
+#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_EN_SHF            15
+#define MSC01_PCI_CFG_EN_MSK            0x00008000
+#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_MAXRTRY_SHF       0
+#define MSC01_PCI_CFG_MAXRTRY_MSK       0x00000fff
+
+#define MSC01_PCI_SWAP_IO_SHF           18
+#define MSC01_PCI_SWAP_IO_MSK           0x000c0000
+#define MSC01_PCI_SWAP_MEM_SHF          16
+#define MSC01_PCI_SWAP_MEM_MSK          0x00030000
+#define MSC01_PCI_SWAP_BAR0_SHF         0
+#define MSC01_PCI_SWAP_BAR0_MSK         0x00000003
+#define MSC01_PCI_SWAP_NOSWAP           0
+#define MSC01_PCI_SWAP_BYTESWAP         1
+
+/*
+ * MIPS System controller PCI register base.
+ *
+ * FIXME - are these macros specific to Malta and co or to the MSC?  If the
+ * latter, they should be moved elsewhere.
+ */
+#define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
+#define MIPS_SOCITSC_PCI_REG_BASE       0x1ff10000
+
+extern unsigned long _pcictrl_msc;
+
+#define MSC01_PCI_REG_BASE      _pcictrl_msc
+
+#define MSC_WRITE(reg, data)    do { *(volatile u32 *)(reg) = data; } while (0)
+#define MSC_READ(reg, data)     do { data = *(volatile u32 *)(reg); } while (0)
+
+/*
+ * Registers absolute addresses
+ */
+
+#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
+#define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
+#define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
+#define MSC01_PCI_HEAD2         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
+#define MSC01_PCI_HEAD3         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
+#define MSC01_PCI_HEAD4         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
+#define MSC01_PCI_HEAD5         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
+#define MSC01_PCI_HEAD6         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
+#define MSC01_PCI_HEAD7         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
+#define MSC01_PCI_HEAD8         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
+#define MSC01_PCI_HEAD9         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
+#define MSC01_PCI_HEAD10        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
+#define MSC01_PCI_HEAD11        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
+#define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
+#define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
new file mode 100644
index 000000000..e174bc7c8
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * Register definitions for Intel PIIX4 South Bridge Device.
+ */
+#ifndef __ASM_MIPS_BOARDS_PIIX4_H
+#define __ASM_MIPS_BOARDS_PIIX4_H
+
+/* PIRQX Route Control */
+#define PIIX4_FUNC0_PIRQRC                      0x60
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE        (1 << 7)
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK           0xf
+#define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX            16
+/* SERIRQ Control */
+#define PIIX4_FUNC0_SERIRQC                     0x64
+#define   PIIX4_FUNC0_SERIRQC_EN                        (1 << 7)
+#define   PIIX4_FUNC0_SERIRQC_CONT                      (1 << 6)
+/* Top Of Memory */
+#define PIIX4_FUNC0_TOM                         0x69
+#define   PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK            0xf0
+/* Deterministic Latency Control */
+#define PIIX4_FUNC0_DLC                         0x82
+#define   PIIX4_FUNC0_DLC_USBPR_EN                      (1 << 2)
+#define   PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN            (1 << 1)
+#define   PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN        (1 << 0)
+/* General Configuration */
+#define PIIX4_FUNC0_GENCFG                      0xb0
+#define   PIIX4_FUNC0_GENCFG_SERIRQ                     (1 << 16)
+
+/* IDE Timing */
+#define PIIX4_FUNC1_IDETIM_PRIMARY_LO           0x40
+#define PIIX4_FUNC1_IDETIM_PRIMARY_HI           0x41
+#define   PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN   (1 << 7)
+#define PIIX4_FUNC1_IDETIM_SECONDARY_LO         0x42
+#define PIIX4_FUNC1_IDETIM_SECONDARY_HI         0x43
+#define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
+
+/* Power Management Configuration Space */
+#define PIIX4_FUNC3_PMBA                        0x40
+#define PIIX4_FUNC3_PMREGMISC                   0x80
+#define   PIIX4_FUNC3_PMREGMISC_EN                      (1 << 0)
+
+/* Power Management IO Space */
+#define PIIX4_FUNC3IO_PMSTS                     0x00
+#define   PIIX4_FUNC3IO_PMSTS_PWRBTN_STS                (1 << 8)
+#define PIIX4_FUNC3IO_PMCNTRL                   0x04
+#define   PIIX4_FUNC3IO_PMCNTRL_SUS_EN                  (1 << 13)
+#define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP                 (0x7 << 10)
+#define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF            (0x0 << 10)
+#define   PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR             (0x1 << 10)
+
+/* Data for magic special PCI cycle */
+#define PIIX4_SUSPEND_MAGIC                     0x00120002
+
+#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mips-boards/sead3-addr.h b/arch/mips/include/asm/mips-boards/sead3-addr.h
new file mode 100644
index 000000000..c0db57802
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/sead3-addr.h
@@ -0,0 +1,83 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2015 Imagination Technologies, Inc.
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H
+#define __ASM_MIPS_BOARDS_SEAD3_ADDR_H
+
+/*
+ * Target #0 Register Decode
+ */
+#define SEAD3_SD_SPDCNF                         0xbb000040
+#define SEAD3_SD_SPADDR                         0xbb000048
+#define SEAD3_SD_DATA                           0xbb000050
+
+/*
+ * Target #1 Register Decode
+ */
+#define SEAD3_CFG                               0xbb100110
+#define SEAD3_GIC_BASE_ADDRESS                  0xbb1c0000
+#define SEAD3_SHARED_SECTION                    0xbb1c0000
+#define SEAD3_VPE_LOCAL_SECTION                 0xbb1c8000
+#define SEAD3_VPE_OTHER_SECTION                 0xbb1cc000
+#define SEAD3_USER_MODE_VISIBLE_SECTION         0xbb1d0000
+
+/*
+ * Target #3 Register Decode
+ */
+#define SEAD3_USB_HS_BASE                       0xbb200000
+#define SEAD3_USB_HS_IDENTIFICATION_REGS        0xbb200000
+#define SEAD3_USB_HS_CAPABILITY_REGS            0xbb200100
+#define SEAD3_USB_HS_OPERATIONAL_REGS           0xbb200140
+#define SEAD3_RESERVED                          0xbe800000
+
+/*
+ * Target #3 Register Decode
+ */
+#define SEAD3_SRAM                              0xbe000000
+#define SEAD3_OPTIONAL_SRAM                     0xbe400000
+#define SEAD3_FPGA                              0xbf000000
+
+#define SEAD3_PI_PIC32_USB_STATUS               0xbf000060
+#define   SEAD3_PI_PIC32_USB_STATUS_IO_RDY      (1 << 0)
+#define   SEAD3_PI_PIC32_USB_STATUS_SPL_INT     (1 << 1)
+#define   SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT   (1 << 2)
+#define   SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT   (1 << 3)
+
+#define SEAD3_PI_SOFT_ENDIAN                    0xbf000070
+
+#define SEAD3_CPLD_P_SWITCH                     0xbf000200
+#define SEAD3_CPLD_F_SWITCH                     0xbf000208
+#define SEAD3_CPLD_P_LED                        0xbf000210
+#define SEAD3_CPLD_F_LED                        0xbf000218
+#define SEAD3_NEWSC_LIVE                        0xbf000220
+#define SEAD3_NEWSC_REG                         0xbf000228
+#define SEAD3_NEWSC_CTRL                        0xbf000230
+
+#define SEAD3_LCD_CONTROL                       0xbf000400
+#define SEAD3_LCD_DATA                          0xbf000408
+#define SEAD3_CPLD_LCD_STATUS                   0xbf000410
+#define SEAD3_CPLD_LCD_DATA                     0xbf000418
+
+#define SEAD3_CPLD_PI_DEVRST                    0xbf000480
+#define SEAD3_CPLD_PI_DEVRST_IC32_RST           (1 << 0)
+#define SEAD3_RESERVED_0                        0xbf000500
+
+#define SEAD3_PIC32_REGISTERS                   0xbf000600
+#define SEAD3_RESERVED_1                        0xbf000700
+#define SEAD3_UART_CH_0                         0xbf000800
+#define SEAD3_UART_CH_1                         0xbf000900
+#define SEAD3_RESERVED_2                        0xbf000a00
+#define SEAD3_ETHERNET                          0xbf010000
+#define SEAD3_RESERVED_3                        0xbf020000
+#define SEAD3_USER_EXPANSION                    0xbf400000
+#define SEAD3_RESERVED_4                        0xbf800000
+#define SEAD3_BOOT_FLASH_EXTENSION              0xbfa00000
+#define SEAD3_BOOT_FLASH                        0xbfc00000
+#define SEAD3_REVISION_REGISTER                 0xbfc00010
+
+#endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H  */
diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
new file mode 100644
index 000000000..ca37a4f32
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/sim.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_MIPS_BOARDS_SIM_H
+#define _ASM_MIPS_BOARDS_SIM_H
+
+#define STATS_ON        1
+#define STATS_OFF       2
+#define STATS_CLEAR     3
+#define STATS_DUMP      4
+#define TRACE_ON                5
+#define TRACE_OFF       6
+
+
+#define simcfg(code)                                            \
+({                                         \
+        __asm__  __volatile__( \
+        "sltiu $0,$0, %0" \
+                ::"i"(code)                                     \
+                ); \
+})
+
+
+
+#endif
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
new file mode 100644
index 000000000..23c67c087
--- /dev/null
+++ b/arch/mips/include/asm/mips-cm.h
@@ -0,0 +1,459 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-cm.h
+#endif
+
+#ifndef __MIPS_ASM_MIPS_CM_H__
+#define __MIPS_ASM_MIPS_CM_H__
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+
+/* The base address of the CM GCR block */
+extern void __iomem *mips_gcr_base;
+
+/* The base address of the CM L2-only sync region */
+extern void __iomem *mips_cm_l2sync_base;
+
+/**
+ * __mips_cm_phys_base - retrieve the physical base address of the CM
+ *
+ * This function returns the physical base address of the Coherence Manager
+ * global control block, or 0 if no Coherence Manager is present. It provides
+ * a default implementation which reads the CMGCRBase register where available,
+ * and may be overridden by platforms which determine this address in a
+ * different way by defining a function with the same prototype except for the
+ * name mips_cm_phys_base (without underscores).
+ */
+extern phys_addr_t __mips_cm_phys_base(void);
+
+/*
+ * mips_cm_is64 - determine CM register width
+ *
+ * The CM register width is determined by the version of the CM, with CM3
+ * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
+ * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
+ * or vice-versa. This variable indicates the width of the memory accesses
+ * that the kernel will perform to GCRs, which may differ from the actual
+ * width of the GCRs.
+ *
+ * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
+ */
+extern int mips_cm_is64;
+
+/**
+ * mips_cm_error_report - Report CM cache errors
+ */
+#ifdef CONFIG_MIPS_CM
+extern void mips_cm_error_report(void);
+#else
+static inline void mips_cm_error_report(void) {}
+#endif
+
+/**
+ * mips_cm_probe - probe for a Coherence Manager
+ *
+ * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
+ * is successfully detected, else -errno.
+ */
+#ifdef CONFIG_MIPS_CM
+extern int mips_cm_probe(void);
+#else
+static inline int mips_cm_probe(void)
+{
+        return -ENODEV;
+}
+#endif
+
+/**
+ * mips_cm_present - determine whether a Coherence Manager is present
+ *
+ * Returns true if a CM is present in the system, else false.
+ */
+static inline bool mips_cm_present(void)
+{
+#ifdef CONFIG_MIPS_CM
+        return mips_gcr_base != NULL;
+#else
+        return false;
+#endif
+}
+
+/**
+ * mips_cm_has_l2sync - determine whether an L2-only sync region is present
+ *
+ * Returns true if the system implements an L2-only sync region, else false.
+ */
+static inline bool mips_cm_has_l2sync(void)
+{
+#ifdef CONFIG_MIPS_CM
+        return mips_cm_l2sync_base != NULL;
+#else
+        return false;
+#endif
+}
+
+/* Offsets to register blocks from the CM base address */
+#define MIPS_CM_GCB_OFS         0x0000 /* Global Control Block */
+#define MIPS_CM_CLCB_OFS        0x2000 /* Core Local Control Block */
+#define MIPS_CM_COCB_OFS        0x4000 /* Core Other Control Block */
+#define MIPS_CM_GDB_OFS         0x6000 /* Global Debug Block */
+
+/* Total size of the CM memory mapped registers */
+#define MIPS_CM_GCR_SIZE        0x8000
+
+/* Size of the L2-only sync region */
+#define MIPS_CM_L2SYNC_SIZE     0x1000
+
+#define GCR_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)           \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
+
+#define GCR_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)           \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
+
+#define GCR_CX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)     \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
+
+#define GCR_CX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)     \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
+
+/* GCR_CONFIG - Information about the system */
+GCR_ACCESSOR_RO(64, 0x000, config)
+#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE       BIT_ULL(43)
+#define CM_GCR_CONFIG_CLUSTER_ID                GENMASK_ULL(39, 32)
+#define CM_GCR_CONFIG_NUM_CLUSTERS              GENMASK(29, 23)
+#define CM_GCR_CONFIG_NUMIOCU                   GENMASK(15, 8)
+#define CM_GCR_CONFIG_PCORES                    GENMASK(7, 0)
+
+/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
+GCR_ACCESSOR_RW(64, 0x008, base)
+#define CM_GCR_BASE_GCRBASE                     GENMASK_ULL(47, 15)
+#define CM_GCR_BASE_CMDEFTGT                    GENMASK(1, 0)
+#define  CM_GCR_BASE_CMDEFTGT_MEM               0
+#define  CM_GCR_BASE_CMDEFTGT_RESERVED          1
+#define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
+#define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
+
+/* GCR_ACCESS - Controls core/IOCU access to GCRs */
+GCR_ACCESSOR_RW(32, 0x020, access)
+#define CM_GCR_ACCESS_ACCESSEN                  GENMASK(7, 0)
+
+/* GCR_REV - Indicates the Coherence Manager revision */
+GCR_ACCESSOR_RO(32, 0x030, rev)
+#define CM_GCR_REV_MAJOR                        GENMASK(15, 8)
+#define CM_GCR_REV_MINOR                        GENMASK(7, 0)
+
+#define CM_ENCODE_REV(major, minor) \
+                (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
+                 FIELD_PREP(CM_GCR_REV_MINOR, minor))
+
+#define CM_REV_CM2                              CM_ENCODE_REV(6, 0)
+#define CM_REV_CM2_5                            CM_ENCODE_REV(7, 0)
+#define CM_REV_CM3                              CM_ENCODE_REV(8, 0)
+#define CM_REV_CM3_5                            CM_ENCODE_REV(9, 0)
+
+/* GCR_ERR_CONTROL - Control error checking logic */
+GCR_ACCESSOR_RW(32, 0x038, err_control)
+#define CM_GCR_ERR_CONTROL_L2_ECC_EN            BIT(1)
+#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT       BIT(0)
+
+/* GCR_ERR_MASK - Control which errors are reported as interrupts */
+GCR_ACCESSOR_RW(64, 0x040, error_mask)
+
+/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
+GCR_ACCESSOR_RW(64, 0x048, error_cause)
+#define CM_GCR_ERROR_CAUSE_ERRTYPE              GENMASK(31, 27)
+#define CM3_GCR_ERROR_CAUSE_ERRTYPE             GENMASK_ULL(63, 58)
+#define CM_GCR_ERROR_CAUSE_ERRINFO              GENMASK(26, 0)
+
+/* GCR_ERR_ADDR - Indicates the address associated with an error */
+GCR_ACCESSOR_RW(64, 0x050, error_addr)
+
+/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
+GCR_ACCESSOR_RW(64, 0x058, error_mult)
+#define CM_GCR_ERROR_MULT_ERR2ND                GENMASK(4, 0)
+
+/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
+GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE       GENMASK(31, 12)
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN         BIT(0)
+
+/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
+GCR_ACCESSOR_RW(64, 0x080, gic_base)
+#define CM_GCR_GIC_BASE_GICBASE                 GENMASK(31, 17)
+#define CM_GCR_GIC_BASE_GICEN                   BIT(0)
+
+/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
+GCR_ACCESSOR_RW(64, 0x088, cpc_base)
+#define CM_GCR_CPC_BASE_CPCBASE                 GENMASK(31, 15)
+#define CM_GCR_CPC_BASE_CPCEN                   BIT(0)
+
+/* GCR_REGn_BASE - Base addresses of CM address regions */
+GCR_ACCESSOR_RW(64, 0x090, reg0_base)
+GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
+GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
+GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
+#define CM_GCR_REGn_BASE_BASEADDR               GENMASK(31, 16)
+
+/* GCR_REGn_MASK - Size & destination of CM address regions */
+GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
+GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
+GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
+GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
+#define CM_GCR_REGn_MASK_ADDRMASK               GENMASK(31, 16)
+#define CM_GCR_REGn_MASK_CCAOVR                 GENMASK(7, 5)
+#define CM_GCR_REGn_MASK_CCAOVREN               BIT(4)
+#define CM_GCR_REGn_MASK_DROPL2                 BIT(2)
+#define CM_GCR_REGn_MASK_CMTGT                  GENMASK(1, 0)
+#define  CM_GCR_REGn_MASK_CMTGT_DISABLED        0x0
+#define  CM_GCR_REGn_MASK_CMTGT_MEM             0x1
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU0           0x2
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU1           0x3
+
+/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
+GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
+#define CM_GCR_GIC_STATUS_EX                    BIT(0)
+
+/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
+GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
+#define CM_GCR_CPC_STATUS_EX                    BIT(0)
+
+/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
+GCR_ACCESSOR_RW(32, 0x130, l2_config)
+#define CM_GCR_L2_CONFIG_BYPASS                 BIT(20)
+#define CM_GCR_L2_CONFIG_SET_SIZE               GENMASK(15, 12)
+#define CM_GCR_L2_CONFIG_LINE_SIZE              GENMASK(11, 8)
+#define CM_GCR_L2_CONFIG_ASSOC                  GENMASK(7, 0)
+
+/* GCR_SYS_CONFIG2 - Further information about the system */
+GCR_ACCESSOR_RO(32, 0x150, sys_config2)
+#define CM_GCR_SYS_CONFIG2_MAXVPW               GENMASK(3, 0)
+
+/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
+GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
+#define CM_GCR_L2_PFT_CONTROL_PAGEMASK          GENMASK(31, 12)
+#define CM_GCR_L2_PFT_CONTROL_PFTEN             BIT(8)
+#define CM_GCR_L2_PFT_CONTROL_NPFT              GENMASK(7, 0)
+
+/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
+GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
+#define CM_GCR_L2_PFT_CONTROL_B_CEN             BIT(8)
+#define CM_GCR_L2_PFT_CONTROL_B_PORTID          GENMASK(7, 0)
+
+/* GCR_L2SM_COP - L2 cache op state machine control */
+GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
+#define CM_GCR_L2SM_COP_PRESENT                 BIT(31)
+#define CM_GCR_L2SM_COP_RESULT                  GENMASK(8, 6)
+#define  CM_GCR_L2SM_COP_RESULT_DONTCARE        0
+#define  CM_GCR_L2SM_COP_RESULT_DONE_OK         1
+#define  CM_GCR_L2SM_COP_RESULT_DONE_ERROR      2
+#define  CM_GCR_L2SM_COP_RESULT_ABORT_OK        3
+#define  CM_GCR_L2SM_COP_RESULT_ABORT_ERROR     4
+#define CM_GCR_L2SM_COP_RUNNING                 BIT(5)
+#define CM_GCR_L2SM_COP_TYPE                    GENMASK(4, 2)
+#define  CM_GCR_L2SM_COP_TYPE_IDX_WBINV         0
+#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAG      1
+#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA  2
+#define  CM_GCR_L2SM_COP_TYPE_HIT_INV           4
+#define  CM_GCR_L2SM_COP_TYPE_HIT_WBINV         5
+#define  CM_GCR_L2SM_COP_TYPE_HIT_WB            6
+#define  CM_GCR_L2SM_COP_TYPE_FETCHLOCK         7
+#define CM_GCR_L2SM_COP_CMD                     GENMASK(1, 0)
+#define  CM_GCR_L2SM_COP_CMD_START              1       /* only when idle */
+#define  CM_GCR_L2SM_COP_CMD_ABORT              3       /* only when running */
+
+/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
+GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
+#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES      GENMASK_ULL(63, 48)
+#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG      GENMASK_ULL(47, 6)
+
+/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
+GCR_ACCESSOR_RW(64, 0x680, bev_base)
+
+/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
+GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
+
+/* GCR_Cx_COHERENCE - Controls core coherence */
+GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN         GENMASK(7, 0)
+#define CM3_GCR_Cx_COHERENCE_COHEN              BIT(0)
+
+/* GCR_Cx_CONFIG - Information about a core's configuration */
+GCR_CX_ACCESSOR_RO(32, 0x010, config)
+#define CM_GCR_Cx_CONFIG_IOCUTYPE               GENMASK(11, 10)
+#define CM_GCR_Cx_CONFIG_PVPE                   GENMASK(9, 0)
+
+/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
+GCR_CX_ACCESSOR_RW(32, 0x018, other)
+#define CM_GCR_Cx_OTHER_CORENUM                 GENMASK(31, 16) /* CM < 3 */
+#define CM_GCR_Cx_OTHER_CLUSTER_EN              BIT(31)         /* CM >= 3.5 */
+#define CM_GCR_Cx_OTHER_GIC_EN                  BIT(30)         /* CM >= 3.5 */
+#define CM_GCR_Cx_OTHER_BLOCK                   GENMASK(25, 24) /* CM >= 3.5 */
+#define  CM_GCR_Cx_OTHER_BLOCK_LOCAL            0
+#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL           1
+#define  CM_GCR_Cx_OTHER_BLOCK_USER             2
+#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH      3
+#define CM_GCR_Cx_OTHER_CLUSTER                 GENMASK(21, 16) /* CM >= 3.5 */
+#define CM3_GCR_Cx_OTHER_CORE                   GENMASK(13, 8)  /* CM >= 3 */
+#define  CM_GCR_Cx_OTHER_CORE_CM                32
+#define CM3_GCR_Cx_OTHER_VP                     GENMASK(2, 0)   /* CM >= 3 */
+
+/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
+GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE         GENMASK(31, 12)
+
+/* GCR_Cx_ID - Identify the current core */
+GCR_CX_ACCESSOR_RO(32, 0x028, id)
+#define CM_GCR_Cx_ID_CLUSTER                    GENMASK(15, 8)
+#define CM_GCR_Cx_ID_CORE                       GENMASK(7, 0)
+
+/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
+GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET       BIT(31)
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB            BIT(30)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK     GENMASK(27, 20)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA       GENMASK(7, 1)
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT        BIT(0)
+
+/**
+ * mips_cm_l2sync - perform an L2-only sync operation
+ *
+ * If an L2-only sync region is present in the system then this function
+ * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
+ */
+static inline int mips_cm_l2sync(void)
+{
+        if (!mips_cm_has_l2sync())
+                return -ENODEV;
+
+        writel(0, mips_cm_l2sync_base);
+        return 0;
+}
+
+/**
+ * mips_cm_revision() - return CM revision
+ *
+ * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
+ * return value should be checked against the CM_REV_* macros.
+ */
+static inline int mips_cm_revision(void)
+{
+        if (!mips_cm_present())
+                return 0;
+
+        return read_gcr_rev();
+}
+
+/**
+ * mips_cm_max_vp_width() - return the width in bits of VP indices
+ *
+ * Return: the width, in bits, of VP indices in fields that combine core & VP
+ * indices.
+ */
+static inline unsigned int mips_cm_max_vp_width(void)
+{
+        extern int smp_num_siblings;
+
+        if (mips_cm_revision() >= CM_REV_CM3)
+                return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
+                                 read_gcr_sys_config2());
+
+        if (mips_cm_present()) {
+                /*
+                 * We presume that all cores in the system will have the same
+                 * number of VP(E)s, and if that ever changes then this will
+                 * need revisiting.
+                 */
+                return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
+        }
+
+        if (IS_ENABLED(CONFIG_SMP))
+                return smp_num_siblings;
+
+        return 1;
+}
+
+/**
+ * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
+ * @cpu: the CPU whose VP ID to calculate
+ *
+ * Hardware such as the GIC uses identifiers for VPs which may not match the
+ * CPU numbers used by Linux. This function calculates the hardware VP
+ * identifier corresponding to a given CPU.
+ *
+ * Return: the VP ID for the CPU.
+ */
+static inline unsigned int mips_cm_vp_id(unsigned int cpu)
+{
+        unsigned int core = cpu_core(&cpu_data[cpu]);
+        unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
+
+        return (core * mips_cm_max_vp_width()) + vp;
+}
+
+#ifdef CONFIG_MIPS_CM
+
+/**
+ * mips_cm_lock_other - lock access to redirect/other region
+ * @cluster: the other cluster to be accessed
+ * @core: the other core to be accessed
+ * @vp: the VP within the other core to be accessed
+ * @block: the register block to be accessed
+ *
+ * Configure the redirect/other region for the local core/VP (depending upon
+ * the CM revision) to target the specified @cluster, @core, @vp & register
+ * @block. Must be called before using the redirect/other region, and followed
+ * by a call to mips_cm_unlock_other() when access to the redirect/other region
+ * is complete.
+ *
+ * This function acquires a spinlock such that code between it &
+ * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
+ * reconfigure the redirect/other region, and cannot be interfered with by
+ * another VP in the core. As such calls to this function should not be nested.
+ */
+extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
+                               unsigned int vp, unsigned int block);
+
+/**
+ * mips_cm_unlock_other - unlock access to redirect/other region
+ *
+ * Must be called after mips_cm_lock_other() once all required access to the
+ * redirect/other region has been completed.
+ */
+extern void mips_cm_unlock_other(void);
+
+#else /* !CONFIG_MIPS_CM */
+
+static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
+                                      unsigned int vp, unsigned int block) { }
+static inline void mips_cm_unlock_other(void) { }
+
+#endif /* !CONFIG_MIPS_CM */
+
+/**
+ * mips_cm_lock_other_cpu - lock access to redirect/other region
+ * @cpu: the other CPU whose register we want to access
+ *
+ * Configure the redirect/other region for the local core/VP (depending upon
+ * the CM revision) to target the specified @cpu & register @block. This is
+ * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
+ * for convenience.
+ */
+static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
+{
+        struct cpuinfo_mips *d = &cpu_data[cpu];
+
+        mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
+}
+
+#endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
new file mode 100644
index 000000000..b54453f16
--- /dev/null
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
+#endif
+
+#ifndef __MIPS_ASM_MIPS_CPC_H__
+#define __MIPS_ASM_MIPS_CPC_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+
+/* The base address of the CPC registers */
+extern void __iomem *mips_cpc_base;
+
+/**
+ * mips_cpc_default_phys_base - retrieve the default physical base address of
+ *                              the CPC
+ *
+ * Returns the default physical base address of the Cluster Power Controller
+ * memory mapped registers. This is platform dependant & must therefore be
+ * implemented per-platform.
+ */
+extern phys_addr_t mips_cpc_default_phys_base(void);
+
+/**
+ * mips_cpc_probe - probe for a Cluster Power Controller
+ *
+ * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
+ * a CPC is successfully detected, else -errno.
+ */
+#ifdef CONFIG_MIPS_CPC
+extern int mips_cpc_probe(void);
+#else
+static inline int mips_cpc_probe(void)
+{
+        return -ENODEV;
+}
+#endif
+
+/**
+ * mips_cpc_present - determine whether a Cluster Power Controller is present
+ *
+ * Returns true if a CPC is present in the system, else false.
+ */
+static inline bool mips_cpc_present(void)
+{
+#ifdef CONFIG_MIPS_CPC
+        return mips_cpc_base != NULL;
+#else
+        return false;
+#endif
+}
+
+/* Offsets from the CPC base address to various control blocks */
+#define MIPS_CPC_GCB_OFS        0x0000
+#define MIPS_CPC_CLCB_OFS       0x2000
+#define MIPS_CPC_COCB_OFS       0x4000
+
+#define CPC_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name)          \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
+
+#define CPC_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name)          \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
+
+#define CPC_CX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
+
+#define CPC_CX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
+
+/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
+CPC_ACCESSOR_RW(32, 0x000, access)
+
+/* CPC_SEQDEL - Configure delays between command sequencer steps */
+CPC_ACCESSOR_RW(32, 0x008, seqdel)
+
+/* CPC_RAIL - Configure the delay from rail power-up to stability */
+CPC_ACCESSOR_RW(32, 0x010, rail)
+
+/* CPC_RESETLEN - Configure the length of reset sequences */
+CPC_ACCESSOR_RW(32, 0x018, resetlen)
+
+/* CPC_REVISION - Indicates the revisison of the CPC */
+CPC_ACCESSOR_RO(32, 0x020, revision)
+
+/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
+CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
+#define CPC_PWRUP_CTL_CM_PWRUP                  BIT(0)
+
+/* CPC_CONFIG - Mirrors GCR_CONFIG */
+CPC_ACCESSOR_RW(64, 0x138, config)
+
+/* CPC_SYS_CONFIG - Control cluster endianness */
+CPC_ACCESSOR_RW(32, 0x140, sys_config)
+#define CPC_SYS_CONFIG_BE_IMMEDIATE             BIT(2)
+#define CPC_SYS_CONFIG_BE_STATUS                BIT(1)
+#define CPC_SYS_CONFIG_BE                       BIT(0)
+
+/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
+CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
+#define CPC_Cx_CMD                              GENMASK(3, 0)
+#define  CPC_Cx_CMD_CLOCKOFF                    0x1
+#define  CPC_Cx_CMD_PWRDOWN                     0x2
+#define  CPC_Cx_CMD_PWRUP                       0x3
+#define  CPC_Cx_CMD_RESET                       0x4
+
+/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
+CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
+#define CPC_Cx_STAT_CONF_PWRUPE                 BIT(23)
+#define CPC_Cx_STAT_CONF_SEQSTATE               GENMASK(22, 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D0           0x0
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U0           0x1
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U1           0x2
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U2           0x3
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U3           0x4
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U4           0x5
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U5           0x6
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U6           0x7
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D1           0x8
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D3           0x9
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D2           0xa
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL            BIT(17)
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL             BIT(16)
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE            BIT(15)
+
+/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
+CPC_CX_ACCESSOR_RW(32, 0x010, other)
+#define CPC_Cx_OTHER_CORENUM                    GENMASK(23, 16)
+
+/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
+CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
+
+/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
+CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
+
+/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
+CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
+
+/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
+CPC_CX_ACCESSOR_RW(32, 0x090, config)
+
+#ifdef CONFIG_MIPS_CPC
+
+/**
+ * mips_cpc_lock_other - lock access to another core
+ * core: the other core to be accessed
+ *
+ * Call before operating upon a core via the 'other' register region in
+ * order to prevent the region being moved during access. Must be called
+ * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
+ * by a call to mips_cpc_unlock_other.
+ */
+extern void mips_cpc_lock_other(unsigned int core);
+
+/**
+ * mips_cpc_unlock_other - unlock access to another core
+ *
+ * Call after operating upon another core via the 'other' register region.
+ * Must be called after mips_cpc_lock_other.
+ */
+extern void mips_cpc_unlock_other(void);
+
+#else /* !CONFIG_MIPS_CPC */
+
+static inline void mips_cpc_lock_other(unsigned int core) { }
+static inline void mips_cpc_unlock_other(void) { }
+
+#endif /* !CONFIG_MIPS_CPC */
+
+#endif /* __MIPS_ASM_MIPS_CPC_H__ */
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
new file mode 100644
index 000000000..fd43d8768
--- /dev/null
+++ b/arch/mips/include/asm/mips-cps.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+#define __MIPS_ASM_MIPS_CPS_H__
+
+#include <linux/io.h>
+#include <linux/types.h>
+
+extern unsigned long __cps_access_bad_size(void)
+        __compiletime_error("Bad size for CPS accessor");
+
+#define CPS_ACCESSOR_A(unit, off, name)                                 \
+static inline void *addr_##unit##_##name(void)                          \
+{                                                                       \
+        return mips_##unit##_base + (off);                              \
+}
+
+#define CPS_ACCESSOR_R(unit, sz, name)                                  \
+static inline uint##sz##_t read_##unit##_##name(void)                   \
+{                                                                       \
+        uint64_t val64;                                                 \
+                                                                        \
+        switch (sz) {                                                   \
+        case 32:                                                        \
+                return __raw_readl(addr_##unit##_##name());             \
+                                                                        \
+        case 64:                                                        \
+                if (mips_cm_is64)                                       \
+                        return __raw_readq(addr_##unit##_##name());     \
+                                                                        \
+                val64 = __raw_readl(addr_##unit##_##name() + 4);        \
+                val64 <<= 32;                                           \
+                val64 |= __raw_readl(addr_##unit##_##name());           \
+                return val64;                                           \
+                                                                        \
+        default:                                                        \
+                return __cps_access_bad_size();                         \
+        }                                                               \
+}
+
+#define CPS_ACCESSOR_W(unit, sz, name)                                  \
+static inline void write_##unit##_##name(uint##sz##_t val)              \
+{                                                                       \
+        switch (sz) {                                                   \
+        case 32:                                                        \
+                __raw_writel(val, addr_##unit##_##name());              \
+                break;                                                  \
+                                                                        \
+        case 64:                                                        \
+                if (mips_cm_is64) {                                     \
+                        __raw_writeq(val, addr_##unit##_##name());      \
+                        break;                                          \
+                }                                                       \
+                                                                        \
+                __raw_writel((uint64_t)val >> 32,                       \
+                             addr_##unit##_##name() + 4);               \
+                __raw_writel(val, addr_##unit##_##name());              \
+                break;                                                  \
+                                                                        \
+        default:                                                        \
+                __cps_access_bad_size();                                \
+                break;                                                  \
+        }                                                               \
+}
+
+#define CPS_ACCESSOR_M(unit, sz, name)                                  \
+static inline void change_##unit##_##name(uint##sz##_t mask,            \
+                                          uint##sz##_t val)             \
+{                                                                       \
+        uint##sz##_t reg_val = read_##unit##_##name();                  \
+        reg_val &= ~mask;                                               \
+        reg_val |= val;                                                 \
+        write_##unit##_##name(reg_val);                                 \
+}                                                                       \
+                                                                        \
+static inline void set_##unit##_##name(uint##sz##_t val)                \
+{                                                                       \
+        change_##unit##_##name(val, val);                               \
+}                                                                       \
+                                                                        \
+static inline void clear_##unit##_##name(uint##sz##_t val)              \
+{                                                                       \
+        change_##unit##_##name(val, 0);                                 \
+}
+
+#define CPS_ACCESSOR_RO(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_R(unit, sz, name)
+
+#define CPS_ACCESSOR_WO(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_W(unit, sz, name)
+
+#define CPS_ACCESSOR_RW(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_R(unit, sz, name)                                  \
+        CPS_ACCESSOR_W(unit, sz, name)                                  \
+        CPS_ACCESSOR_M(unit, sz, name)
+
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+#include <asm/mips-gic.h>
+
+/**
+ * mips_cps_numclusters - return the number of clusters present in the system
+ *
+ * Returns the number of clusters in the system.
+ */
+static inline unsigned int mips_cps_numclusters(void)
+{
+        unsigned int num_clusters;
+
+        if (mips_cm_revision() < CM_REV_CM3_5)
+                return 1;
+
+        num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
+        num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
+        return num_clusters;
+}
+
+/**
+ * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
+ * @cluster: the ID of the cluster whose config we want
+ *
+ * Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
+ *
+ * Returns the value of GCR_CONFIG.
+ */
+static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
+{
+        uint64_t config;
+
+        if (mips_cm_revision() < CM_REV_CM3_5) {
+                /*
+                 * Prior to CM 3.5 we don't have the notion of multiple
+                 * clusters so we can trivially read the GCR_CONFIG register
+                 * within this cluster.
+                 */
+                WARN_ON(cluster != 0);
+                config = read_gcr_config();
+        } else {
+                /*
+                 * From CM 3.5 onwards we read the CPC_CONFIG mirror of
+                 * GCR_CONFIG via the redirect region, since the CPC is always
+                 * powered up allowing us not to need to power up the CM.
+                 */
+                mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
+                config = read_cpc_redir_config();
+                mips_cm_unlock_other();
+        }
+
+        return config;
+}
+
+/**
+ * mips_cps_numcores - return the number of cores present in a cluster
+ * @cluster: the ID of the cluster whose core count we want
+ *
+ * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
+ * zero if no Coherence Manager is present.
+ */
+static inline unsigned int mips_cps_numcores(unsigned int cluster)
+{
+        if (!mips_cm_present())
+                return 0;
+
+        /* Add one before masking to handle 0xff indicating no cores */
+        return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+}
+
+/**
+ * mips_cps_numiocu - return the number of IOCUs present in a cluster
+ * @cluster: the ID of the cluster whose IOCU count we want
+ *
+ * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
+ * if no Coherence Manager is present.
+ */
+static inline unsigned int mips_cps_numiocu(unsigned int cluster)
+{
+        unsigned int num_iocu;
+
+        if (!mips_cm_present())
+                return 0;
+
+        num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
+        num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
+        return num_iocu;
+}
+
+/**
+ * mips_cps_numvps - return the number of VPs (threads) supported by a core
+ * @cluster: the ID of the cluster containing the core we want to examine
+ * @core: the ID of the core whose VP count we want
+ *
+ * Returns the number of Virtual Processors (VPs, ie. hardware threads) that
+ * are supported by the given @core in the given @cluster. If the core or the
+ * kernel do not support hardware mutlti-threading this returns 1.
+ */
+static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
+{
+        unsigned int cfg;
+
+        if (!mips_cm_present())
+                return 1;
+
+        if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
+                && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
+                return 1;
+
+        mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
+
+        if (mips_cm_revision() < CM_REV_CM3_5) {
+                /*
+                 * Prior to CM 3.5 we can only have one cluster & don't have
+                 * CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
+                 */
+                cfg = read_gcr_co_config();
+        } else {
+                /*
+                 * From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
+                 * always powered, which allows us to not worry about powering
+                 * up the cluster's CM here.
+                 */
+                cfg = read_cpc_co_config();
+        }
+
+        mips_cm_unlock_other();
+
+        return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
+}
+
+#endif /* __MIPS_ASM_MIPS_CPS_H__ */
diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h
new file mode 100644
index 000000000..084cac1c5
--- /dev/null
+++ b/arch/mips/include/asm/mips-gic.h
@@ -0,0 +1,373 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-gic.h
+#endif
+
+#ifndef __MIPS_ASM_MIPS_GIC_H__
+#define __MIPS_ASM_MIPS_GIC_H__
+
+#include <linux/bitops.h>
+
+/* The base address of the GIC registers */
+extern void __iomem *mips_gic_base;
+
+/* Offsets from the GIC base address to various control blocks */
+#define MIPS_GIC_SHARED_OFS     0x00000
+#define MIPS_GIC_SHARED_SZ      0x08000
+#define MIPS_GIC_LOCAL_OFS      0x08000
+#define MIPS_GIC_LOCAL_SZ       0x04000
+#define MIPS_GIC_REDIR_OFS      0x0c000
+#define MIPS_GIC_REDIR_SZ       0x04000
+#define MIPS_GIC_USER_OFS       0x10000
+#define MIPS_GIC_USER_SZ        0x10000
+
+/* For read-only shared registers */
+#define GIC_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
+
+/* For read-write shared registers */
+#define GIC_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
+
+/* For read-only local registers */
+#define GIC_VX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)   \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
+
+/* For read-write local registers */
+#define GIC_VX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)   \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
+
+/* For read-only shared per-interrupt registers */
+#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)                 \
+static inline void __iomem *addr_gic_##name(unsigned int intr)          \
+{                                                                       \
+        return mips_gic_base + (off) + (intr * (stride));               \
+}                                                                       \
+                                                                        \
+static inline unsigned int read_gic_##name(unsigned int intr)           \
+{                                                                       \
+        BUILD_BUG_ON(sz != 32);                                         \
+        return __raw_readl(addr_gic_##name(intr));                      \
+}
+
+/* For read-write shared per-interrupt registers */
+#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)                 \
+        GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)                 \
+                                                                        \
+static inline void write_gic_##name(unsigned int intr,                  \
+                                    unsigned int val)                   \
+{                                                                       \
+        BUILD_BUG_ON(sz != 32);                                         \
+        __raw_writel(val, addr_gic_##name(intr));                       \
+}
+
+/* For read-only local per-interrupt registers */
+#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name)              \
+        GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 stride, vl_##name)                     \
+        GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 stride, vo_##name)
+
+/* For read-write local per-interrupt registers */
+#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name)              \
+        GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 stride, vl_##name)                     \
+        GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 stride, vo_##name)
+
+/* For read-only shared bit-per-interrupt registers */
+#define GIC_ACCESSOR_RO_INTR_BIT(off, name)                             \
+static inline void __iomem *addr_gic_##name(void)                       \
+{                                                                       \
+        return mips_gic_base + (off);                                   \
+}                                                                       \
+                                                                        \
+static inline unsigned int read_gic_##name(unsigned int intr)           \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+        unsigned int val;                                               \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                val = __raw_readq(addr) >> intr % 64;                   \
+        } else {                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                val = __raw_readl(addr) >> intr % 32;                   \
+        }                                                               \
+                                                                        \
+        return val & 0x1;                                               \
+}
+
+/* For read-write shared bit-per-interrupt registers */
+#define GIC_ACCESSOR_RW_INTR_BIT(off, name)                             \
+        GIC_ACCESSOR_RO_INTR_BIT(off, name)                             \
+                                                                        \
+static inline void write_gic_##name(unsigned int intr)                  \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                __raw_writeq(BIT(intr % 64), addr);                     \
+        } else {                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                __raw_writel(BIT(intr % 32), addr);                     \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void change_gic_##name(unsigned int intr,                 \
+                                     unsigned int val)                  \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                uint64_t _val;                                          \
+                                                                        \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                _val = __raw_readq(addr);                               \
+                _val &= ~BIT_ULL(intr % 64);                            \
+                _val |= (uint64_t)val << (intr % 64);                   \
+                __raw_writeq(_val, addr);                               \
+        } else {                                                        \
+                uint32_t _val;                                          \
+                                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                _val = __raw_readl(addr);                               \
+                _val &= ~BIT(intr % 32);                                \
+                _val |= val << (intr % 32);                             \
+                __raw_writel(_val, addr);                               \
+        }                                                               \
+}
+
+/* For read-only local bit-per-interrupt registers */
+#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name)                      \
+        GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 vl_##name)                             \
+        GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 vo_##name)
+
+/* For read-write local bit-per-interrupt registers */
+#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name)                      \
+        GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 vl_##name)                             \
+        GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 vo_##name)
+
+/* GIC_SH_CONFIG - Information about the GIC configuration */
+GIC_ACCESSOR_RW(32, 0x000, config)
+#define GIC_CONFIG_COUNTSTOP            BIT(28)
+#define GIC_CONFIG_COUNTBITS            GENMASK(27, 24)
+#define GIC_CONFIG_NUMINTERRUPTS        GENMASK(23, 16)
+#define GIC_CONFIG_PVPS                 GENMASK(6, 0)
+
+/* GIC_SH_COUNTER - Shared global counter value */
+GIC_ACCESSOR_RW(64, 0x010, counter)
+GIC_ACCESSOR_RW(32, 0x010, counter_32l)
+GIC_ACCESSOR_RW(32, 0x014, counter_32h)
+
+/* GIC_SH_POL_* - Configures interrupt polarity */
+GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
+#define GIC_POL_ACTIVE_LOW              0       /* when level triggered */
+#define GIC_POL_ACTIVE_HIGH             1       /* when level triggered */
+#define GIC_POL_FALLING_EDGE            0       /* when single-edge triggered */
+#define GIC_POL_RISING_EDGE             1       /* when single-edge triggered */
+
+/* GIC_SH_TRIG_* - Configures interrupts to be edge or level triggered */
+GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
+#define GIC_TRIG_LEVEL                  0
+#define GIC_TRIG_EDGE                   1
+
+/* GIC_SH_DUAL_* - Configures whether interrupts trigger on both edges */
+GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
+#define GIC_DUAL_SINGLE                 0       /* when edge-triggered */
+#define GIC_DUAL_DUAL                   1       /* when edge-triggered */
+
+/* GIC_SH_WEDGE - Write an 'edge', ie. trigger an interrupt */
+GIC_ACCESSOR_RW(32, 0x280, wedge)
+#define GIC_WEDGE_RW                    BIT(31)
+#define GIC_WEDGE_INTR                  GENMASK(7, 0)
+
+/* GIC_SH_RMASK_* - Reset/clear shared interrupt mask bits */
+GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)
+
+/* GIC_SH_SMASK_* - Set shared interrupt mask bits */
+GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)
+
+/* GIC_SH_MASK_* - Read the current shared interrupt mask */
+GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)
+
+/* GIC_SH_PEND_* - Read currently pending shared interrupts */
+GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)
+
+/* GIC_SH_MAPx_PIN - Map shared interrupts to a particular CPU pin */
+GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
+#define GIC_MAP_PIN_MAP_TO_PIN          BIT(31)
+#define GIC_MAP_PIN_MAP_TO_NMI          BIT(30)
+#define GIC_MAP_PIN_MAP                 GENMASK(5, 0)
+
+/* GIC_SH_MAPx_VP - Map shared interrupts to a particular Virtual Processor */
+GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
+
+/* GIC_Vx_CTL - VP-level interrupt control */
+GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
+#define GIC_VX_CTL_FDC_ROUTABLE         BIT(4)
+#define GIC_VX_CTL_SWINT_ROUTABLE       BIT(3)
+#define GIC_VX_CTL_PERFCNT_ROUTABLE     BIT(2)
+#define GIC_VX_CTL_TIMER_ROUTABLE       BIT(1)
+#define GIC_VX_CTL_EIC                  BIT(0)
+
+/* GIC_Vx_PEND - Read currently pending local interrupts */
+GIC_VX_ACCESSOR_RO(32, 0x004, pend)
+
+/* GIC_Vx_MASK - Read the current local interrupt mask */
+GIC_VX_ACCESSOR_RO(32, 0x008, mask)
+
+/* GIC_Vx_RMASK - Reset/clear local interrupt mask bits */
+GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
+
+/* GIC_Vx_SMASK - Set local interrupt mask bits */
+GIC_VX_ACCESSOR_RW(32, 0x010, smask)
+
+/* GIC_Vx_*_MAP - Route local interrupts to the desired pins */
+GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
+
+/* GIC_Vx_WD_MAP - Route the local watchdog timer interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
+
+/* GIC_Vx_COMPARE_MAP - Route the local count/compare interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
+
+/* GIC_Vx_TIMER_MAP - Route the local CPU timer (cp0 count/compare) interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
+
+/* GIC_Vx_FDC_MAP - Route the local fast debug channel interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
+
+/* GIC_Vx_PERFCTR_MAP - Route the local performance counter interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
+
+/* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
+GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
+
+/* GIC_Vx_SWINT1_MAP - Route the local software interrupt 1 */
+GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
+
+/* GIC_Vx_OTHER - Configure access to other Virtual Processor registers */
+GIC_VX_ACCESSOR_RW(32, 0x080, other)
+#define GIC_VX_OTHER_VPNUM              GENMASK(5, 0)
+
+/* GIC_Vx_IDENT - Retrieve the local Virtual Processor's ID */
+GIC_VX_ACCESSOR_RO(32, 0x088, ident)
+#define GIC_VX_IDENT_VPNUM              GENMASK(5, 0)
+
+/* GIC_Vx_COMPARE - Value to compare with GIC_SH_COUNTER */
+GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)
+
+/* GIC_Vx_EIC_SHADOW_SET_BASE - Set shadow register set for each interrupt */
+GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)
+
+/**
+ * enum mips_gic_local_interrupt - GIC local interrupts
+ * @GIC_LOCAL_INT_WD: GIC watchdog timer interrupt
+ * @GIC_LOCAL_INT_COMPARE: GIC count/compare interrupt
+ * @GIC_LOCAL_INT_TIMER: CP0 count/compare interrupt
+ * @GIC_LOCAL_INT_PERFCTR: Performance counter interrupt
+ * @GIC_LOCAL_INT_SWINT0: Software interrupt 0
+ * @GIC_LOCAL_INT_SWINT1: Software interrupt 1
+ * @GIC_LOCAL_INT_FDC: Fast debug channel interrupt
+ * @GIC_NUM_LOCAL_INTRS: The number of local interrupts
+ *
+ * Enumerates interrupts provided by the GIC that are local to a VP.
+ */
+enum mips_gic_local_interrupt {
+        GIC_LOCAL_INT_WD,
+        GIC_LOCAL_INT_COMPARE,
+        GIC_LOCAL_INT_TIMER,
+        GIC_LOCAL_INT_PERFCTR,
+        GIC_LOCAL_INT_SWINT0,
+        GIC_LOCAL_INT_SWINT1,
+        GIC_LOCAL_INT_FDC,
+        GIC_NUM_LOCAL_INTRS
+};
+
+/**
+ * mips_gic_present() - Determine whether a GIC is present
+ *
+ * Determines whether a MIPS Global Interrupt Controller (GIC) is present in
+ * the system that the kernel is running on.
+ *
+ * Return true if a GIC is present, else false.
+ */
+static inline bool mips_gic_present(void)
+{
+        return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base;
+}
+
+/**
+ * mips_gic_vx_map_reg() - Return GIC_Vx_<intr>_MAP register offset
+ * @intr: A GIC local interrupt
+ *
+ * Determine the index of the GIC_VL_<intr>_MAP or GIC_VO_<intr>_MAP register
+ * within the block of GIC map registers. This is almost the same as the order
+ * of interrupts in the pending & mask registers, as used by enum
+ * mips_gic_local_interrupt, but moves the FDC interrupt & thus offsets the
+ * interrupts after it...
+ *
+ * Return: The map register index corresponding to @intr.
+ *
+ * The return value is suitable for use with the (read|write)_gic_v[lo]_map
+ * accessor functions.
+ */
+static inline unsigned int
+mips_gic_vx_map_reg(enum mips_gic_local_interrupt intr)
+{
+        /* WD, Compare & Timer are 1:1 */
+        if (intr <= GIC_LOCAL_INT_TIMER)
+                return intr;
+
+        /* FDC moves to after Timer... */
+        if (intr == GIC_LOCAL_INT_FDC)
+                return GIC_LOCAL_INT_TIMER + 1;
+
+        /* As a result everything else is offset by 1 */
+        return intr + 1;
+}
+
+/**
+ * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq
+ *
+ * Determine the virq number to use for the coprocessor 0 count/compare
+ * interrupt, which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_compare_int(void);
+
+/**
+ * gic_get_c0_perfcount_int() - Return performance counter interrupt virq
+ *
+ * Determine the virq number to use for CPU performance counter interrupts,
+ * which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_perfcount_int(void);
+
+/**
+ * gic_get_c0_fdc_int() - Return fast debug channel interrupt virq
+ *
+ * Determine the virq number to use for fast debug channel (FDC) interrupts,
+ * which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_fdc_int(void);
+
+#endif /* __MIPS_ASM_MIPS_CPS_H__ */
diff --git a/arch/mips/include/asm/mips-r2-to-r6-emul.h b/arch/mips/include/asm/mips-r2-to-r6-emul.h
new file mode 100644
index 000000000..20621e1ca
--- /dev/null
+++ b/arch/mips/include/asm/mips-r2-to-r6-emul.h
@@ -0,0 +1,101 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2014 Imagination Technologies Ltd.
+ * Author: Markos Chandras <markos.chandras@imgtec.com>
+ */
+
+#ifndef __ASM_MIPS_R2_TO_R6_EMUL_H
+#define __ASM_MIPS_R2_TO_R6_EMUL_H
+
+struct mips_r2_emulator_stats {
+        u64 movs;
+        u64 hilo;
+        u64 muls;
+        u64 divs;
+        u64 dsps;
+        u64 bops;
+        u64 traps;
+        u64 fpus;
+        u64 loads;
+        u64 stores;
+        u64 llsc;
+        u64 dsemul;
+};
+
+struct mips_r2br_emulator_stats {
+        u64 jrs;
+        u64 bltzl;
+        u64 bgezl;
+        u64 bltzll;
+        u64 bgezll;
+        u64 bltzall;
+        u64 bgezall;
+        u64 bltzal;
+        u64 bgezal;
+        u64 beql;
+        u64 bnel;
+        u64 blezl;
+        u64 bgtzl;
+};
+
+#ifdef CONFIG_DEBUG_FS
+
+#define MIPS_R2_STATS(M)                                                \
+do {                                                                    \
+        u32 nir;                                                        \
+        int err;                                                        \
+                                                                        \
+        preempt_disable();                                              \
+        __this_cpu_inc(mipsr2emustats.M);                               \
+        err = __get_user(nir, (u32 __user *)regs->cp0_epc);             \
+        if (!err) {                                                     \
+                if (nir == BREAK_MATH(0))                               \
+                        __this_cpu_inc(mipsr2bdemustats.M);             \
+        }                                                               \
+        preempt_enable();                                               \
+} while (0)
+
+#define MIPS_R2BR_STATS(M)                                      \
+do {                                                            \
+        preempt_disable();                                      \
+        __this_cpu_inc(mipsr2bremustats.M);                     \
+        preempt_enable();                                       \
+} while (0)
+
+#else
+
+#define MIPS_R2_STATS(M)          do { } while (0)
+#define MIPS_R2BR_STATS(M)        do { } while (0)
+
+#endif /* CONFIG_DEBUG_FS */
+
+struct r2_decoder_table {
+        u32     mask;
+        u32     code;
+        int     (*func)(struct pt_regs *regs, u32 inst);
+};
+
+
+extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
+                          const char *str);
+
+#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
+static int mipsr2_emulation;
+static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst,
+                                 unsigned long *fcr31)
+{
+        return 0;
+};
+#else
+/* MIPS R2 Emulator ON/OFF */
+extern int mipsr2_emulation;
+extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
+                          unsigned long *fcr31);
+#endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
+
+#define NO_R6EMU        (cpu_has_mips_r6 && !mipsr2_emulation)
+
+#endif /* __ASM_MIPS_R2_TO_R6_EMUL_H */
diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h
new file mode 100644
index 000000000..b444523ec
--- /dev/null
+++ b/arch/mips/include/asm/mips_mt.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Definitions and declarations for MIPS MT support that are common between
+ * the VSMP, and AP/SP kernel models.
+ */
+#ifndef __ASM_MIPS_MT_H
+#define __ASM_MIPS_MT_H
+
+#include <linux/cpumask.h>
+
+/*
+ * How many VPEs and TCs is Linux allowed to use?  0 means no limit.
+ */
+extern int tclimit;
+extern int vpelimit;
+
+extern cpumask_t mt_fpu_cpumask;
+extern unsigned long mt_fpemul_threshold;
+
+extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
+
+#ifdef CONFIG_MIPS_MT
+extern void mips_mt_set_cpuoptions(void);
+#else
+static inline void mips_mt_set_cpuoptions(void) { }
+#endif
+
+struct class;
+extern struct class *mt_class;
+
+#endif /* __ASM_MIPS_MT_H */
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
new file mode 100644
index 000000000..be4cf9d47
--- /dev/null
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -0,0 +1,423 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MT regs definitions, follows on from mipsregs.h
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Elizabeth Clarke et. al.
+ *
+ */
+#ifndef _ASM_MIPSMTREGS_H
+#define _ASM_MIPSMTREGS_H
+
+#include <asm/mipsregs.h>
+#include <asm/war.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
+#define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
+
+#define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
+#define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
+
+#define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
+#define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
+
+#define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
+#define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
+
+#define read_c0_vpeconf1()              __read_32bit_c0_register($1, 3)
+#define write_c0_vpeconf1(val)          __write_32bit_c0_register($1, 3, val)
+
+#define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
+#define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
+
+#define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
+
+#define write_c0_tchalt(val)            __write_32bit_c0_register($2, 4, val)
+
+#define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
+#define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
+
+#else /* Assembly */
+/*
+ * Macros for use in assembly language code
+ */
+
+#define CP0_MVPCONTROL          $0, 1
+#define CP0_MVPCONF0            $0, 2
+#define CP0_MVPCONF1            $0, 3
+#define CP0_VPECONTROL          $1, 1
+#define CP0_VPECONF0            $1, 2
+#define CP0_VPECONF1            $1, 3
+#define CP0_YQMASK              $1, 4
+#define CP0_VPESCHEDULE         $1, 5
+#define CP0_VPESCHEFBK          $1, 6
+#define CP0_TCSTATUS            $2, 1
+#define CP0_TCBIND              $2, 2
+#define CP0_TCRESTART           $2, 3
+#define CP0_TCHALT              $2, 4
+#define CP0_TCCONTEXT           $2, 5
+#define CP0_TCSCHEDULE          $2, 6
+#define CP0_TCSCHEFBK           $2, 7
+#define CP0_SRSCONF0            $6, 1
+#define CP0_SRSCONF1            $6, 2
+#define CP0_SRSCONF2            $6, 3
+#define CP0_SRSCONF3            $6, 4
+#define CP0_SRSCONF4            $6, 5
+
+#endif
+
+/* MVPControl fields */
+#define MVPCONTROL_EVP          (_ULCAST_(1))
+
+#define MVPCONTROL_VPC_SHIFT    1
+#define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
+
+#define MVPCONTROL_STLB_SHIFT   2
+#define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
+
+
+/* MVPConf0 fields */
+#define MVPCONF0_PTC_SHIFT      0
+#define MVPCONF0_PTC            ( _ULCAST_(0xff))
+#define MVPCONF0_PVPE_SHIFT     10
+#define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
+#define MVPCONF0_TCA_SHIFT      15
+#define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
+#define MVPCONF0_PTLBE_SHIFT    16
+#define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
+#define MVPCONF0_TLBS_SHIFT     29
+#define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
+#define MVPCONF0_M_SHIFT        31
+#define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
+
+
+/* config3 fields */
+#define CONFIG3_MT_SHIFT        2
+#define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
+
+
+/* VPEControl fields (per VPE) */
+#define VPECONTROL_TARGTC       (_ULCAST_(0xff))
+
+#define VPECONTROL_TE_SHIFT     15
+#define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
+#define VPECONTROL_EXCPT_SHIFT  16
+#define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
+
+/* Thread Exception Codes for EXCPT field */
+#define THREX_TU                0
+#define THREX_TO                1
+#define THREX_IYQ               2
+#define THREX_GSX               3
+#define THREX_YSCH              4
+#define THREX_GSSCH             5
+
+#define VPECONTROL_GSI_SHIFT    20
+#define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
+#define VPECONTROL_YSI_SHIFT    21
+#define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
+
+/* VPEConf0 fields (per VPE) */
+#define VPECONF0_VPA_SHIFT      0
+#define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
+#define VPECONF0_MVP_SHIFT      1
+#define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
+#define VPECONF0_XTC_SHIFT      21
+#define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
+
+/* VPEConf1 fields (per VPE) */
+#define VPECONF1_NCP1_SHIFT     0
+#define VPECONF1_NCP1           (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
+#define VPECONF1_NCP2_SHIFT     10
+#define VPECONF1_NCP2           (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
+#define VPECONF1_NCX_SHIFT      20
+#define VPECONF1_NCX            (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
+
+/* TCStatus fields (per TC) */
+#define TCSTATUS_TASID          (_ULCAST_(0xff))
+#define TCSTATUS_IXMT_SHIFT     10
+#define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
+#define TCSTATUS_TKSU_SHIFT     11
+#define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
+#define TCSTATUS_A_SHIFT        13
+#define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
+#define TCSTATUS_DA_SHIFT       15
+#define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
+#define TCSTATUS_DT_SHIFT       20
+#define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
+#define TCSTATUS_TDS_SHIFT      21
+#define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
+#define TCSTATUS_TSST_SHIFT     22
+#define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
+#define TCSTATUS_RNST_SHIFT     23
+#define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
+/* Codes for RNST */
+#define TC_RUNNING              0
+#define TC_WAITING              1
+#define TC_YIELDING             2
+#define TC_GATED                3
+
+#define TCSTATUS_TMX_SHIFT      27
+#define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
+
+/* TCBind */
+#define TCBIND_CURVPE_SHIFT     0
+#define TCBIND_CURVPE           (_ULCAST_(0xf))
+
+#define TCBIND_CURTC_SHIFT      21
+
+#define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
+
+/* TCHalt */
+#define TCHALT_H                (_ULCAST_(1))
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned core_nvpes(void)
+{
+        unsigned conf0;
+
+        if (!cpu_has_mipsmt)
+                return 1;
+
+        conf0 = read_c0_mvpconf0();
+        return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+}
+
+static inline unsigned int dvpe(void)
+{
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41610001              # dvpe $1               \n"
+        "       move    %0, $1                                          \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_evpe(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600021              # evpe                  \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n");
+}
+
+/* Enable virtual processor execution if previous suggested it should be.
+   EVPE_ENABLE to force */
+
+#define EVPE_ENABLE MVPCONTROL_EVP
+
+static inline void evpe(int previous)
+{
+        if ((previous & MVPCONTROL_EVP))
+                __raw_evpe();
+}
+
+static inline unsigned int dmt(void)
+{
+        int res;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .set    noat                                            \n"
+        "       .word   0x41610BC1                      # dmt $1        \n"
+        "       ehb                                                     \n"
+        "       move    %0, $1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_emt(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600be1                      # emt           \n"
+        "       ehb                                                     \n"
+        "       .set    pop");
+}
+
+/* enable multi-threaded execution if previous suggested it should be.
+   EMT_ENABLE to force */
+
+#define EMT_ENABLE VPECONTROL_TE
+
+static inline void emt(int previous)
+{
+        if ((previous & EMT_ENABLE))
+                __raw_emt();
+}
+
+static inline void ehb(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    mips32r2                                \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n");
+}
+
+#define mftc0(rt,sel)                                                   \
+({                                                                      \
+         unsigned long  __res;                                          \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
+        "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftgpr(rt)                                                      \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       # mftgpr $1," #rt "                             \n"     \
+        "       .word   0x41000820 | (" #rt " << 16)            \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftr(rt, u, sel)                                                        \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       mftr    %0, " #rt ", " #u ", " #sel "           \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mttgpr(rd,v)                                                    \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttgpr $1, " #rd "                            \n"     \
+        "       .word   0x41810020 | (" #rd " << 11)            \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (v));                                                   \
+} while (0)
+
+#define mttc0(rd, sel, v)                                                       \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
+        "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (v));                                                     \
+})
+
+
+#define mttr(rd, u, sel, v)                                             \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "mttr   %0," #rd ", " #u ", " #sel                              \
+        : : "r" (v));                                                   \
+})
+
+
+#define settc(tc)                                                       \
+do {                                                                    \
+        write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
+        ehb();                                                          \
+} while (0)
+
+
+/* you *must* set the target tc (settc) before trying to use these */
+#define read_vpe_c0_vpecontrol()        mftc0(1, 1)
+#define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
+#define read_vpe_c0_vpeconf0()          mftc0(1, 2)
+#define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
+#define read_vpe_c0_vpeconf1()          mftc0(1, 3)
+#define write_vpe_c0_vpeconf1(val)      mttc0(1, 3, val)
+#define read_vpe_c0_count()             mftc0(9, 0)
+#define write_vpe_c0_count(val)         mttc0(9, 0, val)
+#define read_vpe_c0_status()            mftc0(12, 0)
+#define write_vpe_c0_status(val)        mttc0(12, 0, val)
+#define read_vpe_c0_cause()             mftc0(13, 0)
+#define write_vpe_c0_cause(val)         mttc0(13, 0, val)
+#define read_vpe_c0_config()            mftc0(16, 0)
+#define write_vpe_c0_config(val)        mttc0(16, 0, val)
+#define read_vpe_c0_config1()           mftc0(16, 1)
+#define write_vpe_c0_config1(val)       mttc0(16, 1, val)
+#define read_vpe_c0_config7()           mftc0(16, 7)
+#define write_vpe_c0_config7(val)       mttc0(16, 7, val)
+#define read_vpe_c0_ebase()             mftc0(15, 1)
+#define write_vpe_c0_ebase(val)         mttc0(15, 1, val)
+#define write_vpe_c0_compare(val)       mttc0(11, 0, val)
+#define read_vpe_c0_badvaddr()          mftc0(8, 0)
+#define read_vpe_c0_epc()               mftc0(14, 0)
+#define write_vpe_c0_epc(val)           mttc0(14, 0, val)
+
+
+/* TC */
+#define read_tc_c0_tcstatus()           mftc0(2, 1)
+#define write_tc_c0_tcstatus(val)       mttc0(2, 1, val)
+#define read_tc_c0_tcbind()             mftc0(2, 2)
+#define write_tc_c0_tcbind(val)         mttc0(2, 2, val)
+#define read_tc_c0_tcrestart()          mftc0(2, 3)
+#define write_tc_c0_tcrestart(val)      mttc0(2, 3, val)
+#define read_tc_c0_tchalt()             mftc0(2, 4)
+#define write_tc_c0_tchalt(val)         mttc0(2, 4, val)
+#define read_tc_c0_tccontext()          mftc0(2, 5)
+#define write_tc_c0_tccontext(val)      mttc0(2, 5, val)
+
+/* GPR */
+#define read_tc_gpr_sp()                mftgpr(29)
+#define write_tc_gpr_sp(val)            mttgpr(29, val)
+#define read_tc_gpr_gp()                mftgpr(28)
+#define write_tc_gpr_gp(val)            mttgpr(28, val)
+
+__BUILD_SET_C0(mvpcontrol)
+
+#endif /* Not __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/mipsprom.h b/arch/mips/include/asm/mipsprom.h
new file mode 100644
index 000000000..2eda19f8f
--- /dev/null
+++ b/arch/mips/include/asm/mipsprom.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MIPSPROM_H
+#define __ASM_MIPSPROM_H
+
+#define PROM_RESET              0
+#define PROM_EXEC               1
+#define PROM_RESTART            2
+#define PROM_REINIT             3
+#define PROM_REBOOT             4
+#define PROM_AUTOBOOT           5
+#define PROM_OPEN               6
+#define PROM_READ               7
+#define PROM_WRITE              8
+#define PROM_IOCTL              9
+#define PROM_CLOSE              10
+#define PROM_GETCHAR            11
+#define PROM_PUTCHAR            12
+#define PROM_SHOWCHAR           13      /* XXX */
+#define PROM_GETS               14      /* XXX */
+#define PROM_PUTS               15      /* XXX */
+#define PROM_PRINTF             16      /* XXX */
+
+/* What are these for? */
+#define PROM_INITPROTO          17      /* XXX */
+#define PROM_PROTOENABLE        18      /* XXX */
+#define PROM_PROTODISABLE       19      /* XXX */
+#define PROM_GETPKT             20      /* XXX */
+#define PROM_PUTPKT             21      /* XXX */
+
+/* More PROM shit.  Probably has to do with VME RMW cycles??? */
+#define PROM_ORW_RMW            22      /* XXX */
+#define PROM_ORH_RMW            23      /* XXX */
+#define PROM_ORB_RMW            24      /* XXX */
+#define PROM_ANDW_RMW           25      /* XXX */
+#define PROM_ANDH_RMW           26      /* XXX */
+#define PROM_ANDB_RMW           27      /* XXX */
+
+/* Cache handling stuff */
+#define PROM_FLUSHCACHE         28      /* XXX */
+#define PROM_CLEARCACHE         29      /* XXX */
+
+/* Libc alike stuff */
+#define PROM_SETJMP             30      /* XXX */
+#define PROM_LONGJMP            31      /* XXX */
+#define PROM_BEVUTLB            32      /* XXX */
+#define PROM_GETENV             33      /* XXX */
+#define PROM_SETENV             34      /* XXX */
+#define PROM_ATOB               35      /* XXX */
+#define PROM_STRCMP             36      /* XXX */
+#define PROM_STRLEN             37      /* XXX */
+#define PROM_STRCPY             38      /* XXX */
+#define PROM_STRCAT             39      /* XXX */
+
+/* Misc stuff */
+#define PROM_PARSER             40      /* XXX */
+#define PROM_RANGE              41      /* XXX */
+#define PROM_ARGVIZE            42      /* XXX */
+#define PROM_HELP               43      /* XXX */
+
+/* Entry points for some PROM commands */
+#define PROM_DUMPCMD            44      /* XXX */
+#define PROM_SETENVCMD          45      /* XXX */
+#define PROM_UNSETENVCMD        46      /* XXX */
+#define PROM_PRINTENVCMD        47      /* XXX */
+#define PROM_BEVEXCEPT          48      /* XXX */
+#define PROM_ENABLECMD          49      /* XXX */
+#define PROM_DISABLECMD         50      /* XXX */
+
+#define PROM_CLEARNOFAULT       51      /* XXX */
+#define PROM_NOTIMPLEMENT       52      /* XXX */
+
+#define PROM_NV_GET             53      /* XXX */
+#define PROM_NV_SET             54      /* XXX */
+
+extern char *prom_getenv(char *);
+
+#endif /* __ASM_MIPSPROM_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
new file mode 100644
index 000000000..7a7467d3f
--- /dev/null
+++ b/arch/mips/include/asm/mipsregs.h
@@ -0,0 +1,2927 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <asm/hazards.h>
+#include <asm/isa-rev.h>
+#include <asm/war.h>
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#define _U64CAST_
+#else
+#define _ULCAST_ (unsigned long)
+#define _U64CAST_ (u64)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_GLOBALNUMBER $3, 1
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_PAGEGRAIN $5, 1
+#define CP0_SEGCTL0 $5, 2
+#define CP0_SEGCTL1 $5, 3
+#define CP0_SEGCTL2 $5, 4
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_HWRENA $7
+#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_GUESTCTL1 $10, 4
+#define CP0_GUESTCTL2 $10, 5
+#define CP0_GUESTCTL3 $10, 6
+#define CP0_COMPARE $11
+#define CP0_GUESTCTL0EXT $11, 4
+#define CP0_STATUS $12
+#define CP0_GUESTCTL0 $12, 6
+#define CP0_GTOFFSET $12, 7
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
+#define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
+#define CP0_CONFIG6 $16, 6
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DIAGNOSTIC1 $22, 1
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL     $12   /* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP     $12   /* MIPSR2 */
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE  $7
+
+
+/* Generic EntryLo bit definitions */
+#define ENTRYLO_G               (_ULCAST_(1) << 0)
+#define ENTRYLO_V               (_ULCAST_(1) << 1)
+#define ENTRYLO_D               (_ULCAST_(1) << 2)
+#define ENTRYLO_C_SHIFT         3
+#define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
+
+/* R3000 EntryLo bit definitions */
+#define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
+#define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
+#define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
+#define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
+
+/* MIPS32/64 EntryLo bit definitions */
+#define MIPS_ENTRYLO_PFN_SHIFT  6
+#define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
+
+/*
+ * MIPSr6+ GlobalNumber register definitions
+ */
+#define MIPS_GLOBALNUMBER_VP_SHF        0
+#define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
+#define MIPS_GLOBALNUMBER_CORE_SHF      8
+#define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
+#define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
+#define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K           0x00000000
+#define PM_4K           0x00001800
+#define PM_16K          0x00007800
+#define PM_64K          0x0001f800
+#define PM_256K         0x0007f800
+
+#else
+
+#define PM_4K           0x00000000
+#define PM_8K           0x00002000
+#define PM_16K          0x00006000
+#define PM_32K          0x0000e000
+#define PM_64K          0x0001e000
+#define PM_128K         0x0003e000
+#define PM_256K         0x0007e000
+#define PM_512K         0x000fe000
+#define PM_1M           0x001fe000
+#define PM_2M           0x003fe000
+#define PM_4M           0x007fe000
+#define PM_8M           0x00ffe000
+#define PM_16M          0x01ffe000
+#define PM_32M          0x03ffe000
+#define PM_64M          0x07ffe000
+#define PM_256M         0x1fffe000
+#define PM_1G           0x7fffe000
+
+#endif
+
+/*
+ * Default page size for a given kernel configuration
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PM_DEFAULT_MASK PM_4K
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+#define PM_DEFAULT_MASK PM_8K
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define PM_DEFAULT_MASK PM_16K
+#elif defined(CONFIG_PAGE_SIZE_32KB)
+#define PM_DEFAULT_MASK PM_32K
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define PM_DEFAULT_MASK PM_64K
+#else
+#error Bad page size configuration!
+#endif
+
+/*
+ * Default huge tlb size for a given kernel configuration
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PM_HUGE_MASK    PM_1M
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+#define PM_HUGE_MASK    PM_4M
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define PM_HUGE_MASK    PM_16M
+#elif defined(CONFIG_PAGE_SIZE_32KB)
+#define PM_HUGE_MASK    PM_64M
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define PM_HUGE_MASK    PM_256M
+#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#error Bad page size configuration for hugetlbfs!
+#endif
+
+/*
+ * Wired register bits
+ */
+#define MIPSR6_WIRED_LIMIT_SHIFT 16
+#define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
+#define MIPSR6_WIRED_WIRED_SHIFT 0
+#define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K           12
+#define PL_16K          14
+#define PL_64K          16
+#define PL_256K         18
+#define PL_1M           20
+#define PL_4M           22
+#define PL_16M          24
+#define PL_64M          26
+#define PL_256M         28
+
+/*
+ * PageGrain bits
+ */
+#define PG_RIE          (_ULCAST_(1) <<  31)
+#define PG_XIE          (_ULCAST_(1) <<  30)
+#define PG_ELPA         (_ULCAST_(1) <<  29)
+#define PG_ESP          (_ULCAST_(1) <<  28)
+#define PG_IEC          (_ULCAST_(1) <<  27)
+
+/* MIPS32/64 EntryHI bit definitions */
+#define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
+#define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
+#define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (_ULCAST_(1) <<  8)
+#define IE_SW1          (_ULCAST_(1) <<  9)
+#define IE_IRQ0         (_ULCAST_(1) << 10)
+#define IE_IRQ1         (_ULCAST_(1) << 11)
+#define IE_IRQ2         (_ULCAST_(1) << 12)
+#define IE_IRQ3         (_ULCAST_(1) << 13)
+#define IE_IRQ4         (_ULCAST_(1) << 14)
+#define IE_IRQ5         (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (_ULCAST_(1) <<  8)
+#define C_SW1           (_ULCAST_(1) <<  9)
+#define C_IRQ0          (_ULCAST_(1) << 10)
+#define C_IRQ1          (_ULCAST_(1) << 11)
+#define C_IRQ2          (_ULCAST_(1) << 12)
+#define C_IRQ3          (_ULCAST_(1) << 13)
+#define C_IRQ4          (_ULCAST_(1) << 14)
+#define C_IRQ5          (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE                  0x00000001
+#define ST0_EXL                 0x00000002
+#define ST0_ERL                 0x00000004
+#define ST0_KSU                 0x00000018
+#  define KSU_USER              0x00000010
+#  define KSU_SUPERVISOR        0x00000008
+#  define KSU_KERNEL            0x00000000
+#define ST0_UX                  0x00000020
+#define ST0_SX                  0x00000040
+#define ST0_KX                  0x00000080
+#define ST0_DE                  0x00010000
+#define ST0_CE                  0x00020000
+
+/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO                  0x08000000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC                 0x00000002
+#define ST0_IEP                 0x00000004
+#define ST0_KUP                 0x00000008
+#define ST0_IEO                 0x00000010
+#define ST0_KUO                 0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC                 0x00010000
+#define ST0_SWC                 0x00020000
+#define ST0_CM                  0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM                  (_ULCAST_(1) <<  4)
+#define ST0_IL                  (_ULCAST_(1) << 23)
+#define ST0_DL                  (_ULCAST_(1) << 24)
+
+/*
+ * Enable the MIPS MDMX and DSP ASEs
+ */
+#define ST0_MX                  0x01000000
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM                  0x0000ff00
+#define  STATUSB_IP0            8
+#define  STATUSF_IP0            (_ULCAST_(1) <<  8)
+#define  STATUSB_IP1            9
+#define  STATUSF_IP1            (_ULCAST_(1) <<  9)
+#define  STATUSB_IP2            10
+#define  STATUSF_IP2            (_ULCAST_(1) << 10)
+#define  STATUSB_IP3            11
+#define  STATUSF_IP3            (_ULCAST_(1) << 11)
+#define  STATUSB_IP4            12
+#define  STATUSF_IP4            (_ULCAST_(1) << 12)
+#define  STATUSB_IP5            13
+#define  STATUSF_IP5            (_ULCAST_(1) << 13)
+#define  STATUSB_IP6            14
+#define  STATUSF_IP6            (_ULCAST_(1) << 14)
+#define  STATUSB_IP7            15
+#define  STATUSF_IP7            (_ULCAST_(1) << 15)
+#define  STATUSB_IP8            0
+#define  STATUSF_IP8            (_ULCAST_(1) <<  0)
+#define  STATUSB_IP9            1
+#define  STATUSF_IP9            (_ULCAST_(1) <<  1)
+#define  STATUSB_IP10           2
+#define  STATUSF_IP10           (_ULCAST_(1) <<  2)
+#define  STATUSB_IP11           3
+#define  STATUSF_IP11           (_ULCAST_(1) <<  3)
+#define  STATUSB_IP12           4
+#define  STATUSF_IP12           (_ULCAST_(1) <<  4)
+#define  STATUSB_IP13           5
+#define  STATUSF_IP13           (_ULCAST_(1) <<  5)
+#define  STATUSB_IP14           6
+#define  STATUSF_IP14           (_ULCAST_(1) <<  6)
+#define  STATUSB_IP15           7
+#define  STATUSF_IP15           (_ULCAST_(1) <<  7)
+#define ST0_CH                  0x00040000
+#define ST0_NMI                 0x00080000
+#define ST0_SR                  0x00100000
+#define ST0_TS                  0x00200000
+#define ST0_BEV                 0x00400000
+#define ST0_RE                  0x02000000
+#define ST0_FR                  0x04000000
+#define ST0_CU                  0xf0000000
+#define ST0_CU0                 0x10000000
+#define ST0_CU1                 0x20000000
+#define ST0_CU2                 0x40000000
+#define ST0_CU3                 0x80000000
+#define ST0_XX                  0x80000000      /* MIPS IV naming */
+
+/* in-kernel enabled CUs */
+#ifdef CONFIG_CPU_LOONGSON64
+#define ST0_KERNEL_CUMASK      (ST0_CU0 | ST0_CU2)
+#else
+#define ST0_KERNEL_CUMASK      ST0_CU0
+#endif
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ */
+#define INTCTLB_IPFDC           23
+#define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
+#define INTCTLB_IPPCI           26
+#define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI            29
+#define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define CAUSEB_EXCCODE          2
+#define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
+#define CAUSEB_IP               8
+#define CAUSEF_IP               (_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0             8
+#define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1             9
+#define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2             10
+#define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3             11
+#define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4             12
+#define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5             13
+#define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6             14
+#define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7             15
+#define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
+#define CAUSEB_FDCI             21
+#define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
+#define CAUSEB_WP               22
+#define CAUSEF_WP               (_ULCAST_(1)   << 22)
+#define CAUSEB_IV               23
+#define CAUSEF_IV               (_ULCAST_(1)   << 23)
+#define CAUSEB_PCI              26
+#define CAUSEF_PCI              (_ULCAST_(1)   << 26)
+#define CAUSEB_DC               27
+#define CAUSEF_DC               (_ULCAST_(1)   << 27)
+#define CAUSEB_CE               28
+#define CAUSEF_CE               (_ULCAST_(3)   << 28)
+#define CAUSEB_TI               30
+#define CAUSEF_TI               (_ULCAST_(1)   << 30)
+#define CAUSEB_BD               31
+#define CAUSEF_BD               (_ULCAST_(1)   << 31)
+
+/*
+ * Cause.ExcCode trap codes.
+ */
+#define EXCCODE_INT             0       /* Interrupt pending */
+#define EXCCODE_MOD             1       /* TLB modified fault */
+#define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
+#define EXCCODE_TLBS            3       /* TLB miss on a store */
+#define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
+#define EXCCODE_ADES            5       /* Address error on a store */
+#define EXCCODE_IBE             6       /* Bus error on an ifetch */
+#define EXCCODE_DBE             7       /* Bus error on a load or store */
+#define EXCCODE_SYS             8       /* System call */
+#define EXCCODE_BP              9       /* Breakpoint */
+#define EXCCODE_RI              10      /* Reserved instruction exception */
+#define EXCCODE_CPU             11      /* Coprocessor unusable */
+#define EXCCODE_OV              12      /* Arithmetic overflow */
+#define EXCCODE_TR              13      /* Trap instruction */
+#define EXCCODE_MSAFPE          14      /* MSA floating point exception */
+#define EXCCODE_FPE             15      /* Floating point exception */
+#define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
+#define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
+#define EXCCODE_MSADIS          21      /* MSA disabled exception */
+#define EXCCODE_MDMX            22      /* MDMX unusable exception */
+#define EXCCODE_WATCH           23      /* Watch address reference */
+#define EXCCODE_MCHECK          24      /* Machine check */
+#define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
+#define EXCCODE_DSPDIS          26      /* DSP disabled exception */
+#define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
+#define EXCCODE_CACHEERR        30      /* Parity/ECC occured on a core */
+
+/* Implementation specific trap codes used by MIPS cores */
+#define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
+
+/* Implementation specific trap codes used by Loongson cores */
+#define LOONGSON_EXCCODE_GSEXC  16      /* Loongson-specific exception */
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA          0
+#define CONF_CM_CACHABLE_WA             1
+#define CONF_CM_UNCACHED                2
+#define CONF_CM_CACHABLE_NONCOHERENT    3
+#define CONF_CM_CACHABLE_CE             4
+#define CONF_CM_CACHABLE_COW            5
+#define CONF_CM_CACHABLE_CUW            6
+#define CONF_CM_CACHABLE_ACCELERATED    7
+#define CONF_CM_CMASK                   7
+#define CONF_BE                 (_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU                 (_ULCAST_(1) <<  3)
+#define CONF_DB                 (_ULCAST_(1) <<  4)
+#define CONF_IB                 (_ULCAST_(1) <<  5)
+#define CONF_DC                 (_ULCAST_(7) <<  6)
+#define CONF_IC                 (_ULCAST_(7) <<  9)
+#define CONF_EB                 (_ULCAST_(1) << 13)
+#define CONF_EM                 (_ULCAST_(1) << 14)
+#define CONF_SM                 (_ULCAST_(1) << 16)
+#define CONF_SC                 (_ULCAST_(1) << 17)
+#define CONF_EW                 (_ULCAST_(3) << 18)
+#define CONF_EP                 (_ULCAST_(15)<< 24)
+#define CONF_EC                 (_ULCAST_(7) << 28)
+#define CONF_CM                 (_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.  */
+#define R4K_CONF_SW             (_ULCAST_(1) << 20)
+#define R4K_CONF_SS             (_ULCAST_(1) << 21)
+#define R4K_CONF_SB             (_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.  */
+#define R5K_CONF_SE             (_ULCAST_(1) << 12)
+#define R5K_CONF_SS             (_ULCAST_(3) << 20)
+
+/* Bits specific to the RM7000.  */
+#define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE            (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC            (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI            (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC            (_ULCAST_(1) << 31)
+
+/* Bits specific to the R10000.  */
+#define R10K_CONF_DN            (_ULCAST_(3) <<  3)
+#define R10K_CONF_CT            (_ULCAST_(1) <<  5)
+#define R10K_CONF_PE            (_ULCAST_(1) <<  6)
+#define R10K_CONF_PM            (_ULCAST_(3) <<  7)
+#define R10K_CONF_EC            (_ULCAST_(15)<<  9)
+#define R10K_CONF_SB            (_ULCAST_(1) << 13)
+#define R10K_CONF_SK            (_ULCAST_(1) << 14)
+#define R10K_CONF_SS            (_ULCAST_(7) << 16)
+#define R10K_CONF_SC            (_ULCAST_(7) << 19)
+#define R10K_CONF_DC            (_ULCAST_(7) << 26)
+#define R10K_CONF_IC            (_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.  */
+#define VR41_CONF_CS            (_ULCAST_(1) << 12)
+#define VR41_CONF_P4K           (_ULCAST_(1) << 13)
+#define VR41_CONF_BP            (_ULCAST_(1) << 16)
+#define VR41_CONF_M16           (_ULCAST_(1) << 20)
+#define VR41_CONF_AD            (_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.  */
+#define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV          (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC           (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF           (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB           (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC            (_ULCAST_(1) << 16)
+#define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT          (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.  */
+#define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
+#define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
+#define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
+#define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
+#define MIPS_CONF_AR            (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT            (_ULCAST_(3) << 13)
+#define MIPS_CONF_BE            (_ULCAST_(1) << 15)
+#define MIPS_CONF_BM            (_ULCAST_(1) << 16)
+#define MIPS_CONF_MM            (_ULCAST_(3) << 17)
+#define MIPS_CONF_MM_SYSAD      (_ULCAST_(1) << 17)
+#define MIPS_CONF_MM_FULL       (_ULCAST_(2) << 17)
+#define MIPS_CONF_SB            (_ULCAST_(1) << 21)
+#define MIPS_CONF_UDI           (_ULCAST_(1) << 22)
+#define MIPS_CONF_DSP           (_ULCAST_(1) << 23)
+#define MIPS_CONF_ISP           (_ULCAST_(1) << 24)
+#define MIPS_CONF_KU            (_ULCAST_(3) << 25)
+#define MIPS_CONF_K23           (_ULCAST_(3) << 28)
+#define MIPS_CONF_M             (_ULCAST_(1) << 31)
+
+/*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA_SHF       7
+#define MIPS_CONF1_DA_SZ        3
+#define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL_SHF       10
+#define MIPS_CONF1_DL_SZ        3
+#define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF       13
+#define MIPS_CONF1_DS_SZ        3
+#define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF       16
+#define MIPS_CONF1_IA_SZ        3
+#define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHF       19
+#define MIPS_CONF1_IL_SZ        3
+#define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHF       22
+#define MIPS_CONF1_IS_SZ        3
+#define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS_SHIFT   (25)
+#define MIPS_CONF1_TLBS_SIZE    (6)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+
+#define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
+#define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
+#define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
+#define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
+#define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
+#define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
+#define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
+#define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT       (0)
+#define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
+#define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+#define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST_SHIFT      (16)
+#define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
+#define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
+#define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
+#define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
+#define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
+#define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
+#define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
+#define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
+#define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
+#define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
+#define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
+#define MIPS_CONF5_MI           (_ULCAST_(1) << 17)
+#define MIPS_CONF5_CRCP         (_ULCAST_(1) << 18)
+#define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
+#define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
+#define MIPS_CONF5_K            (_ULCAST_(1) << 30)
+
+/* Config6 feature bits for proAptiv/P5600 */
+
+/* Jump register cache prediction disable */
+#define MTI_CONF6_JRCD          (_ULCAST_(1) << 0)
+/* MIPSr6 extensions enable */
+#define MTI_CONF6_R6            (_ULCAST_(1) << 2)
+/* IFU Performance Control */
+#define MTI_CONF6_IFUPERFCTL    (_ULCAST_(3) << 10)
+#define MTI_CONF6_SYND          (_ULCAST_(1) << 13)
+/* Sleep state performance counter disable */
+#define MTI_CONF6_SPCD          (_ULCAST_(1) << 14)
+/* proAptiv FTLB on/off bit */
+#define MTI_CONF6_FTLBEN        (_ULCAST_(1) << 15)
+/* Disable load/store bonding */
+#define MTI_CONF6_DLSB          (_ULCAST_(1) << 21)
+/* FTLB probability bits */
+#define MTI_CONF6_FTLBP_SHIFT   (16)
+
+/* Config6 feature bits for Loongson-3 */
+
+/* Loongson-3 internal timer bit */
+#define LOONGSON_CONF6_INTIMER  (_ULCAST_(1) << 6)
+/* Loongson-3 external timer bit */
+#define LOONGSON_CONF6_EXTIMER  (_ULCAST_(1) << 7)
+/* Loongson-3 SFB on/off bit, STFill in manual */
+#define LOONGSON_CONF6_SFBEN    (_ULCAST_(1) << 8)
+/* Loongson-3's LL on exclusive cacheline */
+#define LOONGSON_CONF6_LLEXC    (_ULCAST_(1) << 16)
+/* Loongson-3's SC has a random delay */
+#define LOONGSON_CONF6_SCRAND   (_ULCAST_(1) << 17)
+/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
+#define LOONGSON_CONF6_FTLBDIS  (_ULCAST_(1) << 22)
+
+#define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
+
+#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
+
+#define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
+
+/* Ingenic HPTLB off bits */
+#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
+
+/* Ingenic Config7 bits */
+#define MIPS_CONF7_BTB_LOOP_EN  (_ULCAST_(1) << 4)
+
+/* Config7 Bits specific to MIPS Technologies. */
+
+/* Performance counters implemented Per TC */
+#define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
+
+/* WatchLo* register definitions */
+#define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
+
+/* WatchHi* register definitions */
+#define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
+#define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
+#define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
+#define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
+#define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
+#define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
+#define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
+#define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
+#define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
+#define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
+#define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
+#define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
+#define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
+
+/* PerfCnt control register definitions */
+#define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
+#define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
+#define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
+#define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
+#define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
+#define MIPS_PERFCTRL_EVENT_S   5
+#define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
+#define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
+#define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
+#define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
+#define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
+#define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
+#define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
+#define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
+#define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
+
+/* PerfCnt control register MT extensions used by MIPS cores */
+#define MIPS_PERFCTRL_VPEID_S   16
+#define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
+#define MIPS_PERFCTRL_TCID_S    22
+#define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
+#define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
+#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
+#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
+#define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
+
+/* PerfCnt control register MT extensions used by BMIPS5000 */
+#define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
+
+/* PerfCnt control register MT extensions used by Netlogic XLR */
+#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
+
+/* MAAR bit definitions */
+#define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
+#define MIPS_MAAR_ADDR          GENMASK_ULL(55, 12)
+#define MIPS_MAAR_ADDR_SHIFT    12
+#define MIPS_MAAR_S             (_ULCAST_(1) << 1)
+#define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
+#ifdef CONFIG_XPA
+#define MIPS_MAAR_V             (MIPS_MAAR_VH | MIPS_MAAR_VL)
+#else
+#define MIPS_MAAR_V             MIPS_MAAR_VL
+#endif
+#define MIPS_MAARX_VH           (_ULCAST_(1) << 31)
+#define MIPS_MAARX_ADDR         0xF
+#define MIPS_MAARX_ADDR_SHIFT   32
+
+/* MAARI bit definitions */
+#define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
+
+/* EBase bit definitions */
+#define MIPS_EBASE_CPUNUM_SHIFT 0
+#define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
+#define MIPS_EBASE_WG_SHIFT     11
+#define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
+#define MIPS_EBASE_BASE_SHIFT   12
+#define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
+
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE        11
+#define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/* LLAddr bit definitions */
+#define MIPS_LLADDR_LLB_SHIFT   0
+#define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT    9
+#define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT    4
+#define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT    3
+#define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT     0
+#define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK        _ULCAST_(7)
+#define MIPS_SEGCFG_USK         _ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
+#define MIPS_SEGCFG_MUSK        _ULCAST_(3)
+#define MIPS_SEGCFG_MSK         _ULCAST_(2)
+#define MIPS_SEGCFG_MK          _ULCAST_(1)
+#define MIPS_SEGCFG_UK          _ULCAST_(0)
+
+#define MIPS_PWFIELD_GDI_SHIFT  24
+#define MIPS_PWFIELD_GDI_MASK   0x3f000000
+#define MIPS_PWFIELD_UDI_SHIFT  18
+#define MIPS_PWFIELD_UDI_MASK   0x00fc0000
+#define MIPS_PWFIELD_MDI_SHIFT  12
+#define MIPS_PWFIELD_MDI_MASK   0x0003f000
+#define MIPS_PWFIELD_PTI_SHIFT  6
+#define MIPS_PWFIELD_PTI_MASK   0x00000fc0
+#define MIPS_PWFIELD_PTEI_SHIFT 0
+#define MIPS_PWFIELD_PTEI_MASK  0x0000003f
+
+#define MIPS_PWSIZE_PS_SHIFT    30
+#define MIPS_PWSIZE_PS_MASK     0x40000000
+#define MIPS_PWSIZE_GDW_SHIFT   24
+#define MIPS_PWSIZE_GDW_MASK    0x3f000000
+#define MIPS_PWSIZE_UDW_SHIFT   18
+#define MIPS_PWSIZE_UDW_MASK    0x00fc0000
+#define MIPS_PWSIZE_MDW_SHIFT   12
+#define MIPS_PWSIZE_MDW_MASK    0x0003f000
+#define MIPS_PWSIZE_PTW_SHIFT   6
+#define MIPS_PWSIZE_PTW_MASK    0x00000fc0
+#define MIPS_PWSIZE_PTEW_SHIFT  0
+#define MIPS_PWSIZE_PTEW_MASK   0x0000003f
+
+#define MIPS_PWCTL_PWEN_SHIFT   31
+#define MIPS_PWCTL_PWEN_MASK    0x80000000
+#define MIPS_PWCTL_XK_SHIFT     28
+#define MIPS_PWCTL_XK_MASK      0x10000000
+#define MIPS_PWCTL_XS_SHIFT     27
+#define MIPS_PWCTL_XS_MASK      0x08000000
+#define MIPS_PWCTL_XU_SHIFT     26
+#define MIPS_PWCTL_XU_MASK      0x04000000
+#define MIPS_PWCTL_DPH_SHIFT    7
+#define MIPS_PWCTL_DPH_MASK     0x00000080
+#define MIPS_PWCTL_HUGEPG_SHIFT 6
+#define MIPS_PWCTL_HUGEPG_MASK  0x00000060
+#define MIPS_PWCTL_PSN_SHIFT    0
+#define MIPS_PWCTL_PSN_MASK     0x0000003f
+
+/* GuestCtl0 fields */
+#define MIPS_GCTL0_GM_SHIFT     31
+#define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
+#define MIPS_GCTL0_RI_SHIFT     30
+#define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
+#define MIPS_GCTL0_MC_SHIFT     29
+#define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
+#define MIPS_GCTL0_CP0_SHIFT    28
+#define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
+#define MIPS_GCTL0_AT_SHIFT     26
+#define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
+#define MIPS_GCTL0_GT_SHIFT     25
+#define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
+#define MIPS_GCTL0_CG_SHIFT     24
+#define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
+#define MIPS_GCTL0_CF_SHIFT     23
+#define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
+#define MIPS_GCTL0_G1_SHIFT     22
+#define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
+#define MIPS_GCTL0_G0E_SHIFT    19
+#define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
+#define MIPS_GCTL0_PT_SHIFT     18
+#define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
+#define MIPS_GCTL0_RAD_SHIFT    9
+#define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
+#define MIPS_GCTL0_DRG_SHIFT    8
+#define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
+#define MIPS_GCTL0_G2_SHIFT     7
+#define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
+#define MIPS_GCTL0_GEXC_SHIFT   2
+#define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
+#define MIPS_GCTL0_SFC2_SHIFT   1
+#define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
+#define MIPS_GCTL0_SFC1_SHIFT   0
+#define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
+
+/* GuestCtl0.AT Guest address translation control */
+#define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
+#define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
+
+/* GuestCtl0.GExcCode Hypervisor exception cause codes */
+#define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
+#define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
+#define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
+#define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
+#define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
+#define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
+#define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
+
+/* GuestCtl0Ext fields */
+#define MIPS_GCTL0EXT_RPW_SHIFT 8
+#define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
+#define MIPS_GCTL0EXT_NCC_SHIFT 6
+#define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
+#define MIPS_GCTL0EXT_CGI_SHIFT 4
+#define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
+#define MIPS_GCTL0EXT_FCD_SHIFT 3
+#define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
+#define MIPS_GCTL0EXT_OG_SHIFT  2
+#define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
+#define MIPS_GCTL0EXT_BG_SHIFT  1
+#define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
+#define MIPS_GCTL0EXT_MG_SHIFT  0
+#define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
+
+/* GuestCtl0Ext.RPW Root page walk configuration */
+#define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
+#define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
+#define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
+
+/* GuestCtl0Ext.NCC Nested cache coherency attributes */
+#define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
+#define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
+
+/* GuestCtl1 fields */
+#define MIPS_GCTL1_ID_SHIFT     0
+#define MIPS_GCTL1_ID_WIDTH     8
+#define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
+#define MIPS_GCTL1_RID_SHIFT    16
+#define MIPS_GCTL1_RID_WIDTH    8
+#define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
+#define MIPS_GCTL1_EID_SHIFT    24
+#define MIPS_GCTL1_EID_WIDTH    8
+#define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
+
+/* GuestID reserved for root context */
+#define MIPS_GCTL1_ROOT_GUESTID 0
+
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
+/* RDHWR register numbers */
+#define MIPS_HWR_CPUNUM         0       /* CPU number */
+#define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
+#define MIPS_HWR_CC             2       /* Cycle counter */
+#define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
+#define MIPS_HWR_ULR            29      /* UserLocal */
+#define MIPS_HWR_IMPL1          30      /* Implementation dependent */
+#define MIPS_HWR_IMPL2          31      /* Implementation dependent */
+
+/* Bits in HWREna register */
+#define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
+#define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
+#define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
+#define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
+#define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
+#define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
+#define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT     19
+#define TX39_CONF_ICS_MASK      0x00380000
+#define TX39_CONF_ICS_1KB       0x00000000
+#define TX39_CONF_ICS_2KB       0x00080000
+#define TX39_CONF_ICS_4KB       0x00100000
+#define TX39_CONF_ICS_8KB       0x00180000
+#define TX39_CONF_ICS_16KB      0x00200000
+
+#define TX39_CONF_DCS_SHIFT     16
+#define TX39_CONF_DCS_MASK      0x00070000
+#define TX39_CONF_DCS_1KB       0x00000000
+#define TX39_CONF_DCS_2KB       0x00010000
+#define TX39_CONF_DCS_4KB       0x00020000
+#define TX39_CONF_DCS_8KB       0x00030000
+#define TX39_CONF_DCS_16KB      0x00040000
+
+#define TX39_CONF_CWFON         0x00004000
+#define TX39_CONF_WBON          0x00002000
+#define TX39_CONF_RF_SHIFT      10
+#define TX39_CONF_RF_MASK       0x00000c00
+#define TX39_CONF_DOZE          0x00000200
+#define TX39_CONF_HALT          0x00000100
+#define TX39_CONF_LOCK          0x00000080
+#define TX39_CONF_ICE           0x00000020
+#define TX39_CONF_DCE           0x00000010
+#define TX39_CONF_IRSIZE_SHIFT  2
+#define TX39_CONF_IRSIZE_MASK   0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT  0
+#define TX39_CONF_DRSIZE_MASK   0x00000003
+
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
+
+/* Flush BTB */
+#define LOONGSON_DIAG_BTB       (_ULCAST_(1) << 1)
+/* Flush ITLB */
+#define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
+/* Flush DTLB */
+#define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
+/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
+#define LOONGSON_DIAG_UCAC      (_ULCAST_(1) << 8)
+/* Flush VTLB */
+#define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
+/* Flush FTLB */
+#define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
+
+/*
+ * Diag1 (GSCause in Loongson-speak) fields
+ */
+/* Loongson-specific exception code (GSExcCode) */
+#define LOONGSON_DIAG1_EXCCODE_SHIFT    2
+#define LOONGSON_DIAG1_EXCCODE          GENMASK(6, 2)
+
+/* CvmCtl register field definitions */
+#define CVMCTL_IPPCI_SHIFT      7
+#define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
+#define CVMCTL_IPTI_SHIFT       4
+#define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
+
+/* CvmMemCtl2 register field definitions */
+#define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
+
+/* CvmVMConfig register field definitions */
+#define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
+#define CVMVMCONF_MMUSIZEM1_S   12
+#define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
+#define CVMVMCONF_RMMUSIZEM1_S  0
+#define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION    $0
+#define CP1_UFR         $1
+#define CP1_UNFR        $4
+#define CP1_FCCR        $25
+#define CP1_FEXR        $26
+#define CP1_FENR        $28
+#define CP1_STATUS      $31
+
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S       0
+#define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S       0
+#define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S       1
+#define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S       2
+#define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S       3
+#define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S       4
+#define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S       5
+#define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S       6
+#define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S       7
+#define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S          2
+#define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S  23                                      /* $fcc0 */
+#define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
+#define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
+#define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25                                      /* $fcc1 */
+#define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26                                      /* $fcc2 */
+#define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27                                      /* $fcc3 */
+#define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28                                      /* $fcc4 */
+#define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29                                      /* $fcc5 */
+#define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30                                      /* $fcc6 */
+#define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31                                      /* $fcc7 */
+#define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
+
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ * MAC2008 was removed in Release 5 so we still treat it as
+ * reserved.
+ */
+#define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
+
+#define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM      0x00000003
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
+ */
+#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
+    defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#define get_isa16_mode(x)               ((x) & 0x1)
+#define msk_isa16_mode(x)               ((x) & ~0x1)
+#define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
+#else
+#define get_isa16_mode(x)               0
+#define msk_isa16_mode(x)               (x)
+#define set_isa16_mode(x)               do { } while(0)
+#endif
+
+/*
+ * microMIPS instructions can be 16-bit or 32-bit in length. This
+ * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
+ */
+static inline int mm_insn_16bit(u16 insn)
+{
+        u16 opcode = (insn >> 10) & 0x7;
+
+        return (opcode >= 1 && opcode <= 3) ? 1 : 0;
+}
+
+/*
+ * Helper macros for generating raw instruction encodings in inline asm.
+ */
+#ifdef CONFIG_CPU_MICROMIPS
+#define _ASM_INSN16_IF_MM(_enc)                 \
+        ".insn\n\t"                             \
+        ".hword (" #_enc ")\n\t"
+#define _ASM_INSN32_IF_MM(_enc)                 \
+        ".insn\n\t"                             \
+        ".hword ((" #_enc ") >> 16)\n\t"        \
+        ".hword ((" #_enc ") & 0xffff)\n\t"
+#else
+#define _ASM_INSN_IF_MIPS(_enc)                 \
+        ".insn\n\t"                             \
+        ".word (" #_enc ")\n\t"
+#endif
+
+#ifndef _ASM_INSN16_IF_MM
+#define _ASM_INSN16_IF_MM(_enc)
+#endif
+#ifndef _ASM_INSN32_IF_MM
+#define _ASM_INSN32_IF_MM(_enc)
+#endif
+#ifndef _ASM_INSN_IF_MIPS
+#define _ASM_INSN_IF_MIPS(_enc)
+#endif
+
+/*
+ * parse_r var, r - Helper assembler macro for parsing register names.
+ *
+ * This converts the register name in $n form provided in \r to the
+ * corresponding register number, which is assigned to the variable \var. It is
+ * needed to allow explicit encoding of instructions in inline assembly where
+ * registers are chosen by the compiler in $n form, allowing us to avoid using
+ * fixed register numbers.
+ *
+ * It also allows newer instructions (not implemented by the assembler) to be
+ * transparently implemented using assembler macros, instead of needing separate
+ * cases depending on toolchain support.
+ *
+ * Simple usage example:
+ * __asm__ __volatile__("parse_r __rt, %0\n\t"
+ *                      ".insn\n\t"
+ *                      "# di    %0\n\t"
+ *                      ".word   (0x41606000 | (__rt << 16))"
+ *                      : "=r" (status);
+ */
+
+/* Match an individual register number and assign to \var */
+#define _IFC_REG(n)                             \
+        ".ifc   \\r, $" #n "\n\t"               \
+        "\\var  = " #n "\n\t"                   \
+        ".endif\n\t"
+
+__asm__(".macro parse_r var r\n\t"
+        "\\var  = -1\n\t"
+        _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
+        _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
+        _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
+        _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
+        _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
+        _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
+        _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
+        _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
+        ".iflt  \\var\n\t"
+        ".error \"Unable to parse register name \\r\"\n\t"
+        ".endif\n\t"
+        ".endm");
+
+#undef _IFC_REG
+
+/*
+ * C macros for generating assembler macros for common instruction formats.
+ *
+ * The names of the operands can be chosen by the caller, and the encoding of
+ * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
+ * the ENC encodings.
+ */
+
+/* Instructions with no operands */
+#define _ASM_MACRO_0(OP, ENC)                                           \
+        __asm__(".macro " #OP "\n\t"                                    \
+                ENC                                                     \
+                ".endm")
+
+/* Instructions with 1 register operand & 1 immediate operand */
+#define _ASM_MACRO_1R1I(OP, R1, I2, ENC)                                \
+        __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t"                   \
+                "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+                ENC                                                     \
+                ".endm")
+
+/* Instructions with 2 register operands */
+#define _ASM_MACRO_2R(OP, R1, R2, ENC)                                  \
+        __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
+                "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+                "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+                ENC                                                     \
+                ".endm")
+
+/* Instructions with 3 register operands */
+#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                              \
+        __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
+                "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+                "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+                "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
+                ENC                                                     \
+                ".endm")
+
+/* Instructions with 2 register operands and 1 optional select operand */
+#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                         \
+        __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
+                "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
+                "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
+                ENC                                                     \
+                ".endm")
+
+/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                "# tlbinvf\n\t"
+                _ASM_INSN_IF_MIPS(0x42000004)
+                _ASM_INSN32_IF_MM(0x0000537c)
+                ".set pop");
+}
+
+
+/*
+ * Functions to access the R10000 performance counters.  These are basically
+ * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
+ * performance counter number encoded into bits 1 ... 5 of the instruction.
+ * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
+ * disassembler these will look like an access to sel 0 or 1.
+ */
+#define read_r10k_perf_cntr(counter)                            \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfpc\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntr(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtpc\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+#define read_r10k_perf_event(counter)                           \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfps\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntl(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtps\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define ___read_32bit_c0_register(source, sel, vol)                     \
+({ unsigned int __res;                                                  \
+        if (sel == 0)                                                   \
+                __asm__ vol(                                            \
+                        "mfc0\t%0, " #source "\n\t"                     \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ vol(                                            \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips32\n\t"                              \
+                        "mfc0\t%0, " #source ", " #sel "\n\t"           \
+                        ".set\tpop\n\t"                                 \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define ___read_64bit_c0_register(source, sel, vol)                     \
+({ unsigned long long __res;                                            \
+        if (sizeof(unsigned long) == 4)                                 \
+                __res = __read_64bit_c0_split(source, sel, vol);        \
+        else if (sel == 0)                                              \
+                __asm__ vol(                                            \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips3\n\t"                               \
+                        "dmfc0\t%0, " #source "\n\t"                    \
+                        ".set\tpop"                                     \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ vol(                                            \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%0, " #source ", " #sel "\n\t"          \
+                        ".set\tpop"                                     \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __read_32bit_c0_register(source, sel)                           \
+        ___read_32bit_c0_register(source, sel, __volatile__)
+
+#define __read_const_32bit_c0_register(source, sel)                     \
+        ___read_32bit_c0_register(source, sel,)
+
+#define __read_64bit_c0_register(source, sel)                           \
+        ___read_64bit_c0_register(source, sel, __volatile__)
+
+#define __read_const_64bit_c0_register(source, sel)                     \
+        ___read_64bit_c0_register(source, sel,)
+
+#define __write_32bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        "mtc0\t%z0, " #register "\n\t"                  \
+                        : : "Jr" ((unsigned int)(value)));              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips32\n\t"                              \
+                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
+                        ".set\tpop"                                     \
+                        : : "Jr" ((unsigned int)(value)));              \
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_64bit_c0_split(register, sel, value);           \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips3\n\t"                               \
+                        "dmtc0\t%z0, " #register "\n\t"                 \
+                        ".set\tpop"                                     \
+                        : : "Jr" (value));                              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
+                        ".set\tpop"                                     \
+                        : : "Jr" (value));                              \
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)                              \
+        ((sizeof(unsigned long) == 4) ?                                 \
+        (unsigned long) __read_32bit_c0_register(reg, sel) :            \
+        (unsigned long) __read_64bit_c0_register(reg, sel))
+
+#define __read_const_ulong_c0_register(reg, sel)                        \
+        ((sizeof(unsigned long) == 4) ?                                 \
+        (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
+        (unsigned long) __read_const_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val)                        \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_32bit_c0_register(reg, sel, val);               \
+        else                                                            \
+                __write_64bit_c0_register(reg, sel, val);               \
+} while (0)
+
+/*
+ * On RM7000/RM9000 these are uses to access cop0 set 1 registers
+ */
+#define __read_32bit_c0_ctrl_register(source)                           \
+({ unsigned int __res;                                                  \
+        __asm__ __volatile__(                                           \
+                "cfc0\t%0, " #source "\n\t"                             \
+                : "=r" (__res));                                        \
+        __res;                                                          \
+})
+
+#define __write_32bit_c0_ctrl_register(register, value)                 \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+                "ctc0\t%z0, " #register "\n\t"                          \
+                : : "Jr" ((unsigned int)(value)));                      \
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel.  That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel, vol)                         \
+({                                                                      \
+        unsigned long long __val;                                       \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (sel == 0)                                                   \
+                __asm__ vol(                                            \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%L0, " #source "\n\t"                   \
+                        "dsra\t%M0, %L0, 32\n\t"                        \
+                        "sll\t%L0, %L0, 0\n\t"                          \
+                        ".set\tpop"                                     \
+                        : "=r" (__val));                                \
+        else                                                            \
+                __asm__ vol(                                            \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
+                        "dsra\t%M0, %L0, 32\n\t"                        \
+                        "sll\t%L0, %L0, 0\n\t"                          \
+                        ".set\tpop"                                     \
+                        : "=r" (__val));                                \
+        local_irq_restore(__flags);                                     \
+                                                                        \
+        __val;                                                          \
+})
+
+#define __write_64bit_c0_split(source, sel, val)                        \
+do {                                                                    \
+        unsigned long long __tmp = (val);                               \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (MIPS_ISA_REV >= 2)                                          \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\t" MIPS_ISA_LEVEL "\n\t"                  \
+                        "dins\t%L0, %M0, 32, 32\n\t"                    \
+                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
+                        ".set\tpop"                                     \
+                        : "+r" (__tmp));                                \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source "\n\t"                   \
+                        ".set\tpop"                                     \
+                        : "+r" (__tmp));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tpush\n\t"                                \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
+                        ".set\tpop"                                     \
+                        : "+r" (__tmp));                                \
+        local_irq_restore(__flags);                                     \
+} while (0)
+
+#ifndef TOOLCHAIN_SUPPORTS_XPA
+_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
+        _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
+        _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
+#define _ASM_SET_XPA ""
+#else   /* !TOOLCHAIN_SUPPORTS_XPA */
+#define _ASM_SET_XPA ".set\txpa\n\t"
+#endif
+
+#define __readx_32bit_c0_register(source, sel)                          \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        _ASM_SET_XPA                                                    \
+        "       mfhc0   %0, " #source ", %1                     \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res)                                                  \
+        : "i" (sel));                                                   \
+        __res;                                                          \
+})
+
+#define __writex_32bit_c0_register(register, sel, value)                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        _ASM_SET_XPA                                                    \
+        "       mthc0   %z0, " #register ", %1                  \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "Jr" (value), "i" (sel));                                     \
+} while (0)
+
+#define read_c0_index()         __read_32bit_c0_register($0, 0)
+#define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
+
+#define read_c0_random()        __read_32bit_c0_register($1, 0)
+#define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
+
+#define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
+
+#define readx_c0_entrylo0()     __readx_32bit_c0_register($2, 0)
+#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
+
+#define readx_c0_entrylo1()     __readx_32bit_c0_register($3, 0)
+#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
+
+#define read_c0_conf()          __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
+
+#define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
+
+#define read_c0_context()       __read_ulong_c0_register($4, 0)
+#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
+
+#define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
+#define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
+
+#define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+
+#define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
+#define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
+
+#define read_c0_memorymapid()           __read_32bit_c0_register($4, 5)
+#define write_c0_memorymapid(val)       __write_32bit_c0_register($4, 5, val)
+
+#define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
+
+#define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
+#define read_c0_wired()         __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()          __read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
+#define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
+
+#define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
+#define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
+
+#define read_c0_count()         __read_32bit_c0_register($9, 0)
+#define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
+
+#define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
+
+#define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
+#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
+
+#define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
+#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
+
+#define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
+#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
+
+#define read_c0_compare()       __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
+
+#define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
+#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
+
+#define read_c0_status()        __read_32bit_c0_register($12, 0)
+
+#define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
+
+#define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
+#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
+
+#define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
+#define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
+
+#define read_c0_cause()         __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()           __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid()          __read_const_32bit_c0_register($15, 0)
+
+#define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
+
+#define read_c0_config()        __read_32bit_c0_register($16, 0)
+#define read_c0_config1()       __read_32bit_c0_register($16, 1)
+#define read_c0_config2()       __read_32bit_c0_register($16, 2)
+#define read_c0_config3()       __read_32bit_c0_register($16, 3)
+#define read_c0_config4()       __read_32bit_c0_register($16, 4)
+#define read_c0_config5()       __read_32bit_c0_register($16, 5)
+#define read_c0_config6()       __read_32bit_c0_register($16, 6)
+#define read_c0_config7()       __read_32bit_c0_register($16, 7)
+#define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
+
+#define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
+#define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
+#define read_c0_maar()          __read_ulong_c0_register($17, 1)
+#define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
+#define readx_c0_maar()         __readx_32bit_c0_register($17, 1)
+#define writex_c0_maar(val)     __writex_32bit_c0_register($17, 1, val)
+#define read_c0_maari()         __read_32bit_c0_register($17, 2)
+#define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
+
+/*
+ * The WatchLo register.  There may be up to 8 of them.
+ */
+#define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register.  There may be up to 8 of them.
+ */
+#define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask()     __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+#define read_c0_diag()          __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
+
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
+
+#define read_c0_diag1()         __read_32bit_c0_register($22, 1)
+#define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_diag2()         __read_32bit_c0_register($22, 2)
+#define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_diag3()         __read_32bit_c0_register($22, 3)
+#define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_diag4()         __read_32bit_c0_register($22, 4)
+#define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_diag5()         __read_32bit_c0_register($22, 5)
+#define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_debug()         __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc()          __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
+
+#define read_c0_ecc()           __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo()         __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
+
+#define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
+#define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
+
+#define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo()        __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
+
+#define read_c0_taghi()         __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
+
+/* MIPSR2 */
+#define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
+#define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()        __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()         __read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
+
+#define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
+#define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
+
+#define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
+
+/* MIPSR3 */
+#define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
+
+/* Hardware Page Table Walker */
+#define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
+#define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
+
+#define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
+#define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
+
+#define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
+#define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
+
+#define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
+#define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
+
+#define read_c0_pgd()           __read_64bit_c0_register($9, 7)
+#define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
+#define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
+#define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
+
+#define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
+#define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
+
+#define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
+#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
+
+#define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
+#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
+
+/*
+ * The cacheerr registers are not standardized.  On OCTEON, they are
+ * 64 bits wide.
+ */
+#define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
+#define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
+
+#define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
+#define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
+
+/* BMIPS3300 */
+#define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS43xx */
+#define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
+
+/* Ingenic page ctrl register */
+#define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
+
+/*
+ * Macros to access the guest system control coprocessor
+ */
+
+#ifndef TOOLCHAIN_SUPPORTS_VIRT
+_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
+        _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
+        _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
+        _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
+_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
+        _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
+        _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
+_ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
+                       _ASM_INSN32_IF_MM(0x0000017c));
+_ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
+                       _ASM_INSN32_IF_MM(0x0000117c));
+_ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
+                       _ASM_INSN32_IF_MM(0x0000217c));
+_ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
+                       _ASM_INSN32_IF_MM(0x0000317c));
+_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
+                       _ASM_INSN32_IF_MM(0x0000517c));
+#define _ASM_SET_VIRT ""
+#else   /* !TOOLCHAIN_SUPPORTS_VIRT */
+#define _ASM_SET_VIRT ".set\tvirt\n\t"
+#endif
+
+#define __read_32bit_gc0_register(source, sel)                          \
+({ int __res;                                                           \
+        __asm__ __volatile__(                                           \
+                ".set\tpush\n\t"                                        \
+                ".set\tmips32r5\n\t"                                    \
+                _ASM_SET_VIRT                                           \
+                "mfgc0\t%0, " #source ", %1\n\t"                        \
+                ".set\tpop"                                             \
+                : "=r" (__res)                                          \
+                : "i" (sel));                                           \
+        __res;                                                          \
+})
+
+#define __read_64bit_gc0_register(source, sel)                          \
+({ unsigned long long __res;                                            \
+        __asm__ __volatile__(                                           \
+                ".set\tpush\n\t"                                        \
+                ".set\tmips64r5\n\t"                                    \
+                _ASM_SET_VIRT                                           \
+                "dmfgc0\t%0, " #source ", %1\n\t"                       \
+                ".set\tpop"                                             \
+                : "=r" (__res)                                          \
+                : "i" (sel));                                           \
+        __res;                                                          \
+})
+
+#define __write_32bit_gc0_register(register, sel, value)                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+                ".set\tpush\n\t"                                        \
+                ".set\tmips32r5\n\t"                                    \
+                _ASM_SET_VIRT                                           \
+                "mtgc0\t%z0, " #register ", %1\n\t"                     \
+                ".set\tpop"                                             \
+                : : "Jr" ((unsigned int)(value)),                       \
+                    "i" (sel));                                         \
+} while (0)
+
+#define __write_64bit_gc0_register(register, sel, value)                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+                ".set\tpush\n\t"                                        \
+                ".set\tmips64r5\n\t"                                    \
+                _ASM_SET_VIRT                                           \
+                "dmtgc0\t%z0, " #register ", %1\n\t"                    \
+                ".set\tpop"                                             \
+                : : "Jr" (value),                                       \
+                    "i" (sel));                                         \
+} while (0)
+
+#define __read_ulong_gc0_register(reg, sel)                             \
+        ((sizeof(unsigned long) == 4) ?                                 \
+        (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
+        (unsigned long) __read_64bit_gc0_register(reg, sel))
+
+#define __write_ulong_gc0_register(reg, sel, val)                       \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_32bit_gc0_register(reg, sel, val);              \
+        else                                                            \
+                __write_64bit_gc0_register(reg, sel, val);              \
+} while (0)
+
+#define read_gc0_index()                __read_32bit_gc0_register($0, 0)
+#define write_gc0_index(val)            __write_32bit_gc0_register($0, 0, val)
+
+#define read_gc0_entrylo0()             __read_ulong_gc0_register($2, 0)
+#define write_gc0_entrylo0(val)         __write_ulong_gc0_register($2, 0, val)
+
+#define read_gc0_entrylo1()             __read_ulong_gc0_register($3, 0)
+#define write_gc0_entrylo1(val)         __write_ulong_gc0_register($3, 0, val)
+
+#define read_gc0_context()              __read_ulong_gc0_register($4, 0)
+#define write_gc0_context(val)          __write_ulong_gc0_register($4, 0, val)
+
+#define read_gc0_contextconfig()        __read_32bit_gc0_register($4, 1)
+#define write_gc0_contextconfig(val)    __write_32bit_gc0_register($4, 1, val)
+
+#define read_gc0_userlocal()            __read_ulong_gc0_register($4, 2)
+#define write_gc0_userlocal(val)        __write_ulong_gc0_register($4, 2, val)
+
+#define read_gc0_xcontextconfig()       __read_ulong_gc0_register($4, 3)
+#define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register($4, 3, val)
+
+#define read_gc0_pagemask()             __read_32bit_gc0_register($5, 0)
+#define write_gc0_pagemask(val)         __write_32bit_gc0_register($5, 0, val)
+
+#define read_gc0_pagegrain()            __read_32bit_gc0_register($5, 1)
+#define write_gc0_pagegrain(val)        __write_32bit_gc0_register($5, 1, val)
+
+#define read_gc0_segctl0()              __read_ulong_gc0_register($5, 2)
+#define write_gc0_segctl0(val)          __write_ulong_gc0_register($5, 2, val)
+
+#define read_gc0_segctl1()              __read_ulong_gc0_register($5, 3)
+#define write_gc0_segctl1(val)          __write_ulong_gc0_register($5, 3, val)
+
+#define read_gc0_segctl2()              __read_ulong_gc0_register($5, 4)
+#define write_gc0_segctl2(val)          __write_ulong_gc0_register($5, 4, val)
+
+#define read_gc0_pwbase()               __read_ulong_gc0_register($5, 5)
+#define write_gc0_pwbase(val)           __write_ulong_gc0_register($5, 5, val)
+
+#define read_gc0_pwfield()              __read_ulong_gc0_register($5, 6)
+#define write_gc0_pwfield(val)          __write_ulong_gc0_register($5, 6, val)
+
+#define read_gc0_pwsize()               __read_ulong_gc0_register($5, 7)
+#define write_gc0_pwsize(val)           __write_ulong_gc0_register($5, 7, val)
+
+#define read_gc0_wired()                __read_32bit_gc0_register($6, 0)
+#define write_gc0_wired(val)            __write_32bit_gc0_register($6, 0, val)
+
+#define read_gc0_pwctl()                __read_32bit_gc0_register($6, 6)
+#define write_gc0_pwctl(val)            __write_32bit_gc0_register($6, 6, val)
+
+#define read_gc0_hwrena()               __read_32bit_gc0_register($7, 0)
+#define write_gc0_hwrena(val)           __write_32bit_gc0_register($7, 0, val)
+
+#define read_gc0_badvaddr()             __read_ulong_gc0_register($8, 0)
+#define write_gc0_badvaddr(val)         __write_ulong_gc0_register($8, 0, val)
+
+#define read_gc0_badinstr()             __read_32bit_gc0_register($8, 1)
+#define write_gc0_badinstr(val)         __write_32bit_gc0_register($8, 1, val)
+
+#define read_gc0_badinstrp()            __read_32bit_gc0_register($8, 2)
+#define write_gc0_badinstrp(val)        __write_32bit_gc0_register($8, 2, val)
+
+#define read_gc0_count()                __read_32bit_gc0_register($9, 0)
+
+#define read_gc0_entryhi()              __read_ulong_gc0_register($10, 0)
+#define write_gc0_entryhi(val)          __write_ulong_gc0_register($10, 0, val)
+
+#define read_gc0_compare()              __read_32bit_gc0_register($11, 0)
+#define write_gc0_compare(val)          __write_32bit_gc0_register($11, 0, val)
+
+#define read_gc0_status()               __read_32bit_gc0_register($12, 0)
+#define write_gc0_status(val)           __write_32bit_gc0_register($12, 0, val)
+
+#define read_gc0_intctl()               __read_32bit_gc0_register($12, 1)
+#define write_gc0_intctl(val)           __write_32bit_gc0_register($12, 1, val)
+
+#define read_gc0_cause()                __read_32bit_gc0_register($13, 0)
+#define write_gc0_cause(val)            __write_32bit_gc0_register($13, 0, val)
+
+#define read_gc0_epc()                  __read_ulong_gc0_register($14, 0)
+#define write_gc0_epc(val)              __write_ulong_gc0_register($14, 0, val)
+
+#define read_gc0_prid()                 __read_32bit_gc0_register($15, 0)
+
+#define read_gc0_ebase()                __read_32bit_gc0_register($15, 1)
+#define write_gc0_ebase(val)            __write_32bit_gc0_register($15, 1, val)
+
+#define read_gc0_ebase_64()             __read_64bit_gc0_register($15, 1)
+#define write_gc0_ebase_64(val)         __write_64bit_gc0_register($15, 1, val)
+
+#define read_gc0_config()               __read_32bit_gc0_register($16, 0)
+#define read_gc0_config1()              __read_32bit_gc0_register($16, 1)
+#define read_gc0_config2()              __read_32bit_gc0_register($16, 2)
+#define read_gc0_config3()              __read_32bit_gc0_register($16, 3)
+#define read_gc0_config4()              __read_32bit_gc0_register($16, 4)
+#define read_gc0_config5()              __read_32bit_gc0_register($16, 5)
+#define read_gc0_config6()              __read_32bit_gc0_register($16, 6)
+#define read_gc0_config7()              __read_32bit_gc0_register($16, 7)
+#define write_gc0_config(val)           __write_32bit_gc0_register($16, 0, val)
+#define write_gc0_config1(val)          __write_32bit_gc0_register($16, 1, val)
+#define write_gc0_config2(val)          __write_32bit_gc0_register($16, 2, val)
+#define write_gc0_config3(val)          __write_32bit_gc0_register($16, 3, val)
+#define write_gc0_config4(val)          __write_32bit_gc0_register($16, 4, val)
+#define write_gc0_config5(val)          __write_32bit_gc0_register($16, 5, val)
+#define write_gc0_config6(val)          __write_32bit_gc0_register($16, 6, val)
+#define write_gc0_config7(val)          __write_32bit_gc0_register($16, 7, val)
+
+#define read_gc0_lladdr()               __read_ulong_gc0_register($17, 0)
+#define write_gc0_lladdr(val)           __write_ulong_gc0_register($17, 0, val)
+
+#define read_gc0_watchlo0()             __read_ulong_gc0_register($18, 0)
+#define read_gc0_watchlo1()             __read_ulong_gc0_register($18, 1)
+#define read_gc0_watchlo2()             __read_ulong_gc0_register($18, 2)
+#define read_gc0_watchlo3()             __read_ulong_gc0_register($18, 3)
+#define read_gc0_watchlo4()             __read_ulong_gc0_register($18, 4)
+#define read_gc0_watchlo5()             __read_ulong_gc0_register($18, 5)
+#define read_gc0_watchlo6()             __read_ulong_gc0_register($18, 6)
+#define read_gc0_watchlo7()             __read_ulong_gc0_register($18, 7)
+#define write_gc0_watchlo0(val)         __write_ulong_gc0_register($18, 0, val)
+#define write_gc0_watchlo1(val)         __write_ulong_gc0_register($18, 1, val)
+#define write_gc0_watchlo2(val)         __write_ulong_gc0_register($18, 2, val)
+#define write_gc0_watchlo3(val)         __write_ulong_gc0_register($18, 3, val)
+#define write_gc0_watchlo4(val)         __write_ulong_gc0_register($18, 4, val)
+#define write_gc0_watchlo5(val)         __write_ulong_gc0_register($18, 5, val)
+#define write_gc0_watchlo6(val)         __write_ulong_gc0_register($18, 6, val)
+#define write_gc0_watchlo7(val)         __write_ulong_gc0_register($18, 7, val)
+
+#define read_gc0_watchhi0()             __read_32bit_gc0_register($19, 0)
+#define read_gc0_watchhi1()             __read_32bit_gc0_register($19, 1)
+#define read_gc0_watchhi2()             __read_32bit_gc0_register($19, 2)
+#define read_gc0_watchhi3()             __read_32bit_gc0_register($19, 3)
+#define read_gc0_watchhi4()             __read_32bit_gc0_register($19, 4)
+#define read_gc0_watchhi5()             __read_32bit_gc0_register($19, 5)
+#define read_gc0_watchhi6()             __read_32bit_gc0_register($19, 6)
+#define read_gc0_watchhi7()             __read_32bit_gc0_register($19, 7)
+#define write_gc0_watchhi0(val)         __write_32bit_gc0_register($19, 0, val)
+#define write_gc0_watchhi1(val)         __write_32bit_gc0_register($19, 1, val)
+#define write_gc0_watchhi2(val)         __write_32bit_gc0_register($19, 2, val)
+#define write_gc0_watchhi3(val)         __write_32bit_gc0_register($19, 3, val)
+#define write_gc0_watchhi4(val)         __write_32bit_gc0_register($19, 4, val)
+#define write_gc0_watchhi5(val)         __write_32bit_gc0_register($19, 5, val)
+#define write_gc0_watchhi6(val)         __write_32bit_gc0_register($19, 6, val)
+#define write_gc0_watchhi7(val)         __write_32bit_gc0_register($19, 7, val)
+
+#define read_gc0_xcontext()             __read_ulong_gc0_register($20, 0)
+#define write_gc0_xcontext(val)         __write_ulong_gc0_register($20, 0, val)
+
+#define read_gc0_perfctrl0()            __read_32bit_gc0_register($25, 0)
+#define write_gc0_perfctrl0(val)        __write_32bit_gc0_register($25, 0, val)
+#define read_gc0_perfcntr0()            __read_32bit_gc0_register($25, 1)
+#define write_gc0_perfcntr0(val)        __write_32bit_gc0_register($25, 1, val)
+#define read_gc0_perfcntr0_64()         __read_64bit_gc0_register($25, 1)
+#define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register($25, 1, val)
+#define read_gc0_perfctrl1()            __read_32bit_gc0_register($25, 2)
+#define write_gc0_perfctrl1(val)        __write_32bit_gc0_register($25, 2, val)
+#define read_gc0_perfcntr1()            __read_32bit_gc0_register($25, 3)
+#define write_gc0_perfcntr1(val)        __write_32bit_gc0_register($25, 3, val)
+#define read_gc0_perfcntr1_64()         __read_64bit_gc0_register($25, 3)
+#define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register($25, 3, val)
+#define read_gc0_perfctrl2()            __read_32bit_gc0_register($25, 4)
+#define write_gc0_perfctrl2(val)        __write_32bit_gc0_register($25, 4, val)
+#define read_gc0_perfcntr2()            __read_32bit_gc0_register($25, 5)
+#define write_gc0_perfcntr2(val)        __write_32bit_gc0_register($25, 5, val)
+#define read_gc0_perfcntr2_64()         __read_64bit_gc0_register($25, 5)
+#define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register($25, 5, val)
+#define read_gc0_perfctrl3()            __read_32bit_gc0_register($25, 6)
+#define write_gc0_perfctrl3(val)        __write_32bit_gc0_register($25, 6, val)
+#define read_gc0_perfcntr3()            __read_32bit_gc0_register($25, 7)
+#define write_gc0_perfcntr3(val)        __write_32bit_gc0_register($25, 7, val)
+#define read_gc0_perfcntr3_64()         __read_64bit_gc0_register($25, 7)
+#define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register($25, 7, val)
+
+#define read_gc0_errorepc()             __read_ulong_gc0_register($30, 0)
+#define write_gc0_errorepc(val)         __write_ulong_gc0_register($30, 0, val)
+
+#define read_gc0_kscratch1()            __read_ulong_gc0_register($31, 2)
+#define read_gc0_kscratch2()            __read_ulong_gc0_register($31, 3)
+#define read_gc0_kscratch3()            __read_ulong_gc0_register($31, 4)
+#define read_gc0_kscratch4()            __read_ulong_gc0_register($31, 5)
+#define read_gc0_kscratch5()            __read_ulong_gc0_register($31, 6)
+#define read_gc0_kscratch6()            __read_ulong_gc0_register($31, 7)
+#define write_gc0_kscratch1(val)        __write_ulong_gc0_register($31, 2, val)
+#define write_gc0_kscratch2(val)        __write_ulong_gc0_register($31, 3, val)
+#define write_gc0_kscratch3(val)        __write_ulong_gc0_register($31, 4, val)
+#define write_gc0_kscratch4(val)        __write_ulong_gc0_register($31, 5, val)
+#define write_gc0_kscratch5(val)        __write_ulong_gc0_register($31, 6, val)
+#define write_gc0_kscratch6(val)        __write_ulong_gc0_register($31, 7, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_gc0_cvmcount()             __read_ulong_gc0_register($9, 6)
+#define write_gc0_cvmcount(val)         __write_ulong_gc0_register($9, 6, val)
+
+#define read_gc0_cvmctl()               __read_64bit_gc0_register($9, 7)
+#define write_gc0_cvmctl(val)           __write_64bit_gc0_register($9, 7, val)
+
+#define read_gc0_cvmmemctl()            __read_64bit_gc0_register($11, 7)
+#define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register($11, 7, val)
+
+#define read_gc0_cvmmemctl2()           __read_64bit_gc0_register($16, 6)
+#define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register($16, 6, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define _read_32bit_cp1_register(source, gas_hardfloat)                 \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    reorder                                 \n"     \
+        "       # gas fails to assemble cfc1 for some archs,    \n"     \
+        "       # like Octeon.                                  \n"     \
+        "       .set    mips1                                   \n"     \
+        "       "STR(gas_hardfloat)"                            \n"     \
+        "       cfc1    %0,"STR(source)"                        \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+        __res;                                                          \
+})
+
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    reorder                                 \n"     \
+        "       "STR(gas_hardfloat)"                            \n"     \
+        "       ctc1    %0,"STR(dest)"                          \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (val));                                                 \
+} while (0)
+
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)                                 \
+        _read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val)                             \
+        _write_32bit_cp1_register(dest, val, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)                                 \
+        _read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val)                             \
+        _write_32bit_cp1_register(dest, val, )
+#endif
+
+#ifdef TOOLCHAIN_SUPPORTS_DSP
+#define rddsp(mask)                                                     \
+({                                                                      \
+        unsigned int __dspctl;                                          \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       rddsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (__dspctl)                                               \
+        : "i" (mask));                                                  \
+        __dspctl;                                                       \
+})
+
+#define wrdsp(val, mask)                                                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       wrdsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (val), "i" (mask));                                       \
+} while (0)
+
+#define mflo0()                                                         \
+({                                                                      \
+        long mflo0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo0));                                                \
+        mflo0;                                                          \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        long mflo1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo1));                                                \
+        mflo1;                                                          \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        long mflo2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo2));                                                \
+        mflo2;                                                          \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        long mflo3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo3));                                                \
+        mflo3;                                                          \
+})
+
+#define mfhi0()                                                         \
+({                                                                      \
+        long mfhi0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi0));                                                \
+        mfhi0;                                                          \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        long mfhi1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi1));                                                \
+        mfhi1;                                                          \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        long mfhi2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi2));                                                \
+        mfhi2;                                                          \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        long mfhi3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi3));                                                \
+        mfhi3;                                                          \
+})
+
+
+#define mtlo0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set " MIPS_ISA_LEVEL "                         \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#else
+
+#define rddsp(mask)                                                     \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       # rddsp $1, %x1                                 \n"     \
+        _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
+        _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res)                                                  \
+        : "i" (mask));                                                  \
+        __res;                                                          \
+})
+
+#define wrdsp(val, mask)                                                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # wrdsp $1, %x1                                 \n"     \
+        _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
+        _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (val), "i" (mask));                                       \
+} while (0)
+
+#define _dsp_mfxxx(ins)                                                 \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
+        _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__treg)                                                 \
+        : "i" (ins));                                                   \
+        __treg;                                                         \
+})
+
+#define _dsp_mtxxx(val, ins)                                            \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
+        _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (val), "i" (ins));                                        \
+} while (0)
+
+#ifdef CONFIG_CPU_MICROMIPS
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
+
+#else  /* !CONFIG_CPU_MICROMIPS */
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
+
+#endif /* CONFIG_CPU_MICROMIPS */
+
+#define mflo0() _dsp_mflo(0)
+#define mflo1() _dsp_mflo(1)
+#define mflo2() _dsp_mflo(2)
+#define mflo3() _dsp_mflo(3)
+
+#define mfhi0() _dsp_mfhi(0)
+#define mfhi1() _dsp_mfhi(1)
+#define mfhi2() _dsp_mfhi(2)
+#define mfhi3() _dsp_mfhi(3)
+
+#define mtlo0(x) _dsp_mtlo(x, 0)
+#define mtlo1(x) _dsp_mtlo(x, 1)
+#define mtlo2(x) _dsp_mtlo(x, 2)
+#define mtlo3(x) _dsp_mtlo(x, 3)
+
+#define mthi0(x) _dsp_mthi(x, 0)
+#define mthi1(x) _dsp_mthi(x, 1)
+#define mthi2(x) _dsp_mthi(x, 2)
+#define mthi3(x) _dsp_mthi(x, 3)
+
+#endif
+
+/*
+ * TLB operations.
+ *
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void tlb_probe(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbp\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    noreorder                               \n"
+        "       .set    noat                                    \n"
+        "       .set    mips32r2                                \n"
+        "       .word   0x41610001              # dvpe $1       \n"
+        "       move    %0, $1                                  \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n"
+        : "=r" (res));
+
+        instruction_hazard();
+#endif
+
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbr\n\t"
+                ".set reorder");
+
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
+        if ((res & _ULCAST_(1)))
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    noreorder                       \n"
+                "       .set    noat                            \n"
+                "       .set    mips32r2                        \n"
+                "       .word   0x41600021      # evpe          \n"
+                "       ehb                                     \n"
+                "       .set    pop                             \n");
+#endif
+}
+
+static inline void tlb_write_indexed(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwi\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwr\n\t"
+                ".set reorder");
+}
+
+/*
+ * Guest TLB operations.
+ *
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void guest_tlb_probe(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                _ASM_SET_VIRT
+                "tlbgp\n\t"
+                ".set pop");
+}
+
+static inline void guest_tlb_read(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                _ASM_SET_VIRT
+                "tlbgr\n\t"
+                ".set pop");
+}
+
+static inline void guest_tlb_write_indexed(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                _ASM_SET_VIRT
+                "tlbgwi\n\t"
+                ".set pop");
+}
+
+static inline void guest_tlb_write_random(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                _ASM_SET_VIRT
+                "tlbgwr\n\t"
+                ".set pop");
+}
+
+/*
+ * Guest TLB Invalidate Flush
+ */
+static inline void guest_tlbinvf(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                _ASM_SET_VIRT
+                "tlbginvf\n\t"
+                ".set pop");
+}
+
+/*
+ * Manipulate bits in a register.
+ */
+#define __BUILD_SET_COMMON(name)                                \
+static inline unsigned int                                      \
+set_##name(unsigned int set)                                    \
+{                                                               \
+        unsigned int res, new;                                  \
+                                                                \
+        res = read_##name();                                    \
+        new = res | set;                                        \
+        write_##name(new);                                      \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+clear_##name(unsigned int clear)                                \
+{                                                               \
+        unsigned int res, new;                                  \
+                                                                \
+        res = read_##name();                                    \
+        new = res & ~clear;                                     \
+        write_##name(new);                                      \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+change_##name(unsigned int change, unsigned int val)            \
+{                                                               \
+        unsigned int res, new;                                  \
+                                                                \
+        res = read_##name();                                    \
+        new = res & ~change;                                    \
+        new |= (val & change);                                  \
+        write_##name(new);                                      \
+                                                                \
+        return res;                                             \
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
+
+__BUILD_SET_C0(status)
+__BUILD_SET_C0(cause)
+__BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
+__BUILD_SET_C0(config6)
+__BUILD_SET_C0(config7)
+__BUILD_SET_C0(diag)
+__BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
+__BUILD_SET_C0(guestctl0)
+__BUILD_SET_C0(guestctl0ext)
+__BUILD_SET_C0(guestctl1)
+__BUILD_SET_C0(guestctl2)
+__BUILD_SET_C0(guestctl3)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
+
+/*
+ * Manipulate bits in a guest c0 register.
+ */
+#define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
+
+__BUILD_SET_GC0(wired)
+__BUILD_SET_GC0(status)
+__BUILD_SET_GC0(cause)
+__BUILD_SET_GC0(ebase)
+__BUILD_SET_GC0(config1)
+
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+        return read_c0_ebase() & MIPS_EBASE_CPUNUM;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h
new file mode 100644
index 000000000..a40824e3e
--- /dev/null
+++ b/arch/mips/include/asm/mmiowb.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MMIOWB_H
+#define _ASM_MMIOWB_H
+
+#include <asm/io.h>
+
+#define mmiowb()        iobarrier_w()
+
+#include <asm-generic/mmiowb.h>
+
+#endif  /* _ASM_MMIOWB_H */
diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
new file mode 100644
index 000000000..5df0238f6
--- /dev/null
+++ b/arch/mips/include/asm/mmu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+#include <linux/atomic.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+
+typedef struct {
+        union {
+                u64 asid[NR_CPUS];
+                atomic64_t mmid;
+        };
+
+        void *vdso;
+
+        /* lock to be held whilst modifying fp_bd_emupage_allocmap */
+        spinlock_t bd_emupage_lock;
+        /* bitmap tracking allocation of fp_bd_emupage */
+        unsigned long *bd_emupage_allocmap;
+        /* wait queue for threads requiring an emuframe */
+        wait_queue_head_t bd_emupage_queue;
+} mm_context_t;
+
+#endif /* __ASM_MMU_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
new file mode 100644
index 000000000..cddead91a
--- /dev/null
+++ b/arch/mips/include/asm/mmu_context.h
@@ -0,0 +1,240 @@
+/*
+ * Switch a MMU context.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MMU_CONTEXT_H
+#define _ASM_MMU_CONTEXT_H
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm_types.h>
+#include <linux/smp.h>
+#include <linux/slab.h>
+
+#include <asm/barrier.h>
+#include <asm/cacheflush.h>
+#include <asm/dsemul.h>
+#include <asm/ginvt.h>
+#include <asm/hazards.h>
+#include <asm/tlbflush.h>
+#include <asm-generic/mm_hooks.h>
+
+#define htw_set_pwbase(pgd)                                             \
+do {                                                                    \
+        if (cpu_has_htw) {                                              \
+                write_c0_pwbase(pgd);                                   \
+                back_to_back_c0_hazard();                               \
+        }                                                               \
+} while (0)
+
+extern void tlbmiss_handler_setup_pgd(unsigned long);
+extern char tlbmiss_handler_setup_pgd_end[];
+
+/* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
+#define TLBMISS_HANDLER_SETUP_PGD(pgd)                                  \
+do {                                                                    \
+        tlbmiss_handler_setup_pgd((unsigned long)(pgd));                \
+        htw_set_pwbase((unsigned long)pgd);                             \
+} while (0)
+
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+
+#define TLBMISS_HANDLER_RESTORE()                                       \
+        write_c0_xcontext((unsigned long) smp_processor_id() <<         \
+                          SMP_CPUID_REGSHIFT)
+
+#define TLBMISS_HANDLER_SETUP()                                         \
+        do {                                                            \
+                TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
+                TLBMISS_HANDLER_RESTORE();                              \
+        } while (0)
+
+#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
+
+/*
+ * For the fast tlb miss handlers, we keep a per cpu array of pointers
+ * to the current pgd for each processor. Also, the proc. id is stuffed
+ * into the context register.
+ */
+extern unsigned long pgd_current[];
+
+#define TLBMISS_HANDLER_RESTORE()                                       \
+        write_c0_context((unsigned long) smp_processor_id() <<          \
+                         SMP_CPUID_REGSHIFT)
+
+#define TLBMISS_HANDLER_SETUP()                                         \
+        TLBMISS_HANDLER_RESTORE();                                      \
+        back_to_back_c0_hazard();                                       \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
+
+/*
+ * The ginvt instruction will invalidate wired entries when its type field
+ * targets anything other than the entire TLB. That means that if we were to
+ * allow the kernel to create wired entries with the MMID of current->active_mm
+ * then those wired entries could be invalidated when we later use ginvt to
+ * invalidate TLB entries with that MMID.
+ *
+ * In order to prevent ginvt from trashing wired entries, we reserve one MMID
+ * for use by the kernel when creating wired entries. This MMID will never be
+ * assigned to a struct mm, and we'll never target it with a ginvt instruction.
+ */
+#define MMID_KERNEL_WIRED       0
+
+/*
+ *  All unused by hardware upper bits will be considered
+ *  as a software asid extension.
+ */
+static inline u64 asid_version_mask(unsigned int cpu)
+{
+        unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
+
+        return ~(u64)(asid_mask | (asid_mask - 1));
+}
+
+static inline u64 asid_first_version(unsigned int cpu)
+{
+        return ~asid_version_mask(cpu) + 1;
+}
+
+static inline u64 cpu_context(unsigned int cpu, const struct mm_struct *mm)
+{
+        if (cpu_has_mmid)
+                return atomic64_read(&mm->context.mmid);
+
+        return mm->context.asid[cpu];
+}
+
+static inline void set_cpu_context(unsigned int cpu,
+                                   struct mm_struct *mm, u64 ctx)
+{
+        if (cpu_has_mmid)
+                atomic64_set(&mm->context.mmid, ctx);
+        else
+                mm->context.asid[cpu] = ctx;
+}
+
+#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
+#define cpu_asid(cpu, mm) \
+        (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+extern void get_new_mmu_context(struct mm_struct *mm);
+extern void check_mmu_context(struct mm_struct *mm);
+extern void check_switch_mmu_context(struct mm_struct *mm);
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        int i;
+
+        if (cpu_has_mmid) {
+                set_cpu_context(0, mm, 0);
+        } else {
+                for_each_possible_cpu(i)
+                        set_cpu_context(i, mm, 0);
+        }
+
+        mm->context.bd_emupage_allocmap = NULL;
+        spin_lock_init(&mm->context.bd_emupage_lock);
+        init_waitqueue_head(&mm->context.bd_emupage_queue);
+
+        return 0;
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+        unsigned long flags;
+        local_irq_save(flags);
+
+        htw_stop();
+        check_switch_mmu_context(next);
+
+        /*
+         * Mark current->active_mm as not "active" anymore.
+         * We don't want to mislead possible IPI tlb flush routines.
+         */
+        cpumask_clear_cpu(cpu, mm_cpumask(prev));
+        cpumask_set_cpu(cpu, mm_cpumask(next));
+        htw_start();
+
+        local_irq_restore(flags);
+}
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        dsemul_mm_cleanup(mm);
+}
+
+#define activate_mm(prev, next) switch_mm(prev, next, current)
+#define deactivate_mm(tsk, mm)  do { } while (0)
+
+static inline void
+drop_mmu_context(struct mm_struct *mm)
+{
+        unsigned long flags;
+        unsigned int cpu;
+        u32 old_mmid;
+        u64 ctx;
+
+        local_irq_save(flags);
+
+        cpu = smp_processor_id();
+        ctx = cpu_context(cpu, mm);
+
+        if (!ctx) {
+                /* no-op */
+        } else if (cpu_has_mmid) {
+                /*
+                 * Globally invalidating TLB entries associated with the MMID
+                 * is pretty cheap using the GINVT instruction, so we'll do
+                 * that rather than incur the overhead of allocating a new
+                 * MMID. The latter would be especially difficult since MMIDs
+                 * are global & other CPUs may be actively using ctx.
+                 */
+                htw_stop();
+                old_mmid = read_c0_memorymapid();
+                write_c0_memorymapid(ctx & cpu_asid_mask(&cpu_data[cpu]));
+                mtc0_tlbw_hazard();
+                ginvt_mmid();
+                sync_ginv();
+                write_c0_memorymapid(old_mmid);
+                instruction_hazard();
+                htw_start();
+        } else if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
+                /*
+                 * mm is currently active, so we can't really drop it.
+                 * Instead we bump the ASID.
+                 */
+                htw_stop();
+                get_new_mmu_context(mm);
+                write_c0_entryhi(cpu_asid(cpu, mm));
+                htw_start();
+        } else {
+                /* will get a new context next time */
+                set_cpu_context(cpu, mm, 0);
+        }
+
+        local_irq_restore(flags);
+}
+
+#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/arch/mips/include/asm/mmzone.h b/arch/mips/include/asm/mmzone.h
new file mode 100644
index 000000000..b826b8473
--- /dev/null
+++ b/arch/mips/include/asm/mmzone.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
+ * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004
+ */
+#ifndef _ASM_MMZONE_H_
+#define _ASM_MMZONE_H_
+
+#include <asm/page.h>
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+# include <mmzone.h>
+#endif
+
+#ifndef pa_to_nid
+#define pa_to_nid(addr) 0
+#endif
+
+#ifndef nid_to_addrbase
+#define nid_to_addrbase(nid) 0
+#endif
+
+#ifdef CONFIG_DISCONTIGMEM
+
+#define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
new file mode 100644
index 000000000..724a08825
--- /dev/null
+++ b/arch/mips/include/asm/module.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MODULE_H
+#define _ASM_MODULE_H
+
+#include <linux/list.h>
+#include <linux/elf.h>
+#include <asm/extable.h>
+
+struct mod_arch_specific {
+        /* Data Bus Error exception tables */
+        struct list_head dbe_list;
+        const struct exception_table_entry *dbe_start;
+        const struct exception_table_entry *dbe_end;
+        struct mips_hi16 *r_mips_hi16_list;
+};
+
+typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
+
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+} Elf64_Mips_Rel;
+
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+        Elf64_Sxword r_addend;                  /* Addend.  */
+} Elf64_Mips_Rela;
+
+#ifdef CONFIG_32BIT
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+#define Elf_Addr        Elf32_Addr
+#define Elf_Rel         Elf32_Rel
+#define Elf_Rela        Elf32_Rela
+#define ELF_R_TYPE(X)   ELF32_R_TYPE(X)
+#define ELF_R_SYM(X)    ELF32_R_SYM(X)
+
+#define Elf_Mips_Rel    Elf32_Rel
+#define Elf_Mips_Rela   Elf32_Rela
+
+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM((rel).r_info)
+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE((rel).r_info)
+
+#endif
+
+#ifdef CONFIG_64BIT
+#define Elf_Shdr        Elf64_Shdr
+#define Elf_Sym         Elf64_Sym
+#define Elf_Ehdr        Elf64_Ehdr
+#define Elf_Addr        Elf64_Addr
+#define Elf_Rel         Elf64_Rel
+#define Elf_Rela        Elf64_Rela
+#define ELF_R_TYPE(X)   ELF64_R_TYPE(X)
+#define ELF_R_SYM(X)    ELF64_R_SYM(X)
+
+#define Elf_Mips_Rel    Elf64_Mips_Rel
+#define Elf_Mips_Rela   Elf64_Mips_Rela
+
+#define ELF_MIPS_R_SYM(rel) ((rel).r_sym)
+#define ELF_MIPS_R_TYPE(rel) ((rel).r_type)
+
+#endif
+
+#ifdef CONFIG_MODULES
+/* Given an address, look for it in the exception tables. */
+const struct exception_table_entry*search_module_dbetables(unsigned long addr);
+#else
+/* Given an address, look for it in the exception tables. */
+static inline const struct exception_table_entry *
+search_module_dbetables(unsigned long addr)
+{
+        return NULL;
+}
+#endif
+
+#endif /* _ASM_MODULE_H */
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
new file mode 100644
index 000000000..e0a3dd523
--- /dev/null
+++ b/arch/mips/include/asm/msa.h
@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+#ifndef _ASM_MSA_H
+#define _ASM_MSA_H
+
+#include <asm/mipsregs.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/inst.h>
+
+extern void _save_msa(struct task_struct *);
+extern void _restore_msa(struct task_struct *);
+extern void _init_msa_upper(void);
+
+extern void read_msa_wr_b(unsigned idx, union fpureg *to);
+extern void read_msa_wr_h(unsigned idx, union fpureg *to);
+extern void read_msa_wr_w(unsigned idx, union fpureg *to);
+extern void read_msa_wr_d(unsigned idx, union fpureg *to);
+
+/**
+ * read_msa_wr() - Read a single MSA vector register
+ * @idx:        The index of the vector register to read
+ * @to:         The FPU register union to store the registers value in
+ * @fmt:        The format of the data in the vector register
+ *
+ * Read the value of MSA vector register idx into the FPU register
+ * union to, using the format fmt.
+ */
+static inline void read_msa_wr(unsigned idx, union fpureg *to,
+                               enum msa_2b_fmt fmt)
+{
+        switch (fmt) {
+        case msa_fmt_b:
+                read_msa_wr_b(idx, to);
+                break;
+
+        case msa_fmt_h:
+                read_msa_wr_h(idx, to);
+                break;
+
+        case msa_fmt_w:
+                read_msa_wr_w(idx, to);
+                break;
+
+        case msa_fmt_d:
+                read_msa_wr_d(idx, to);
+                break;
+
+        default:
+                BUG();
+        }
+}
+
+extern void write_msa_wr_b(unsigned idx, union fpureg *from);
+extern void write_msa_wr_h(unsigned idx, union fpureg *from);
+extern void write_msa_wr_w(unsigned idx, union fpureg *from);
+extern void write_msa_wr_d(unsigned idx, union fpureg *from);
+
+/**
+ * write_msa_wr() - Write a single MSA vector register
+ * @idx:        The index of the vector register to write
+ * @from:       The FPU register union to take the registers value from
+ * @fmt:        The format of the data in the vector register
+ *
+ * Write the value from the FPU register union from into MSA vector
+ * register idx, using the format fmt.
+ */
+static inline void write_msa_wr(unsigned idx, union fpureg *from,
+                                enum msa_2b_fmt fmt)
+{
+        switch (fmt) {
+        case msa_fmt_b:
+                write_msa_wr_b(idx, from);
+                break;
+
+        case msa_fmt_h:
+                write_msa_wr_h(idx, from);
+                break;
+
+        case msa_fmt_w:
+                write_msa_wr_w(idx, from);
+                break;
+
+        case msa_fmt_d:
+                write_msa_wr_d(idx, from);
+                break;
+
+        default:
+                BUG();
+        }
+}
+
+static inline void enable_msa(void)
+{
+        if (cpu_has_msa) {
+                set_c0_config5(MIPS_CONF5_MSAEN);
+                enable_fpu_hazard();
+        }
+}
+
+static inline void disable_msa(void)
+{
+        if (cpu_has_msa) {
+                clear_c0_config5(MIPS_CONF5_MSAEN);
+                disable_fpu_hazard();
+        }
+}
+
+static inline int is_msa_enabled(void)
+{
+        if (!cpu_has_msa)
+                return 0;
+
+        return read_c0_config5() & MIPS_CONF5_MSAEN;
+}
+
+static inline int thread_msa_context_live(void)
+{
+        /*
+         * Check cpu_has_msa only if it's a constant. This will allow the
+         * compiler to optimise out code for CPUs without MSA without adding
+         * an extra redundant check for CPUs with MSA.
+         */
+        if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
+                return 0;
+
+        return test_thread_flag(TIF_MSA_CTX_LIVE);
+}
+
+static inline void save_msa(struct task_struct *t)
+{
+        if (cpu_has_msa)
+                _save_msa(t);
+}
+
+static inline void restore_msa(struct task_struct *t)
+{
+        if (cpu_has_msa)
+                _restore_msa(t);
+}
+
+static inline void init_msa_upper(void)
+{
+        /*
+         * Check cpu_has_msa only if it's a constant. This will allow the
+         * compiler to optimise out code for CPUs without MSA without adding
+         * an extra redundant check for CPUs with MSA.
+         */
+        if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
+                return;
+
+        _init_msa_upper();
+}
+
+#ifndef TOOLCHAIN_SUPPORTS_MSA
+/*
+ * Define assembler macros using .word for the c[ft]cmsa instructions in order
+ * to allow compilation with toolchains that do not support MSA. Once all
+ * toolchains in use support MSA these can be removed.
+ */
+_ASM_MACRO_2R(cfcmsa, rd, cs,
+        _ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6)
+        _ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6));
+_ASM_MACRO_2R(ctcmsa, cd, rs,
+        _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)
+        _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6));
+#define _ASM_SET_MSA ""
+#else /* TOOLCHAIN_SUPPORTS_MSA */
+#define _ASM_SET_MSA ".set\tfp=64\n\t"                          \
+                     ".set\tmsa\n\t"
+#endif
+
+#define __BUILD_MSA_CTL_REG(name, cs)                           \
+static inline unsigned int read_msa_##name(void)                \
+{                                                               \
+        unsigned int reg;                                       \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        _ASM_SET_MSA                                            \
+        "       cfcmsa  %0, $" #cs "\n"                         \
+        "       .set    pop\n"                                  \
+        : "=r"(reg));                                           \
+        return reg;                                             \
+}                                                               \
+                                                                \
+static inline void write_msa_##name(unsigned int val)           \
+{                                                               \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        _ASM_SET_MSA                                            \
+        "       ctcmsa  $" #cs ", %0\n"                         \
+        "       .set    pop\n"                                  \
+        : : "r"(val));                                          \
+}
+
+__BUILD_MSA_CTL_REG(ir, 0)
+__BUILD_MSA_CTL_REG(csr, 1)
+__BUILD_MSA_CTL_REG(access, 2)
+__BUILD_MSA_CTL_REG(save, 3)
+__BUILD_MSA_CTL_REG(modify, 4)
+__BUILD_MSA_CTL_REG(request, 5)
+__BUILD_MSA_CTL_REG(map, 6)
+__BUILD_MSA_CTL_REG(unmap, 7)
+
+#endif /* !__ASSEMBLY__ */
+
+#define MSA_IR          0
+#define MSA_CSR         1
+#define MSA_ACCESS      2
+#define MSA_SAVE        3
+#define MSA_MODIFY      4
+#define MSA_REQUEST     5
+#define MSA_MAP         6
+#define MSA_UNMAP       7
+
+/* MSA Implementation Register (MSAIR) */
+#define MSA_IR_REVB             0
+#define MSA_IR_REVF             (_ULCAST_(0xff) << MSA_IR_REVB)
+#define MSA_IR_PROCB            8
+#define MSA_IR_PROCF            (_ULCAST_(0xff) << MSA_IR_PROCB)
+#define MSA_IR_WRPB             16
+#define MSA_IR_WRPF             (_ULCAST_(0x1) << MSA_IR_WRPB)
+
+/* MSA Control & Status Register (MSACSR) */
+#define MSA_CSR_RMB             0
+#define MSA_CSR_RMF             (_ULCAST_(0x3) << MSA_CSR_RMB)
+#define MSA_CSR_RM_NEAREST      0
+#define MSA_CSR_RM_TO_ZERO      1
+#define MSA_CSR_RM_TO_POS       2
+#define MSA_CSR_RM_TO_NEG       3
+#define MSA_CSR_FLAGSB          2
+#define MSA_CSR_FLAGSF          (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
+#define MSA_CSR_FLAGS_IB        2
+#define MSA_CSR_FLAGS_IF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
+#define MSA_CSR_FLAGS_UB        3
+#define MSA_CSR_FLAGS_UF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
+#define MSA_CSR_FLAGS_OB        4
+#define MSA_CSR_FLAGS_OF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
+#define MSA_CSR_FLAGS_ZB        5
+#define MSA_CSR_FLAGS_ZF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
+#define MSA_CSR_FLAGS_VB        6
+#define MSA_CSR_FLAGS_VF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
+#define MSA_CSR_ENABLESB        7
+#define MSA_CSR_ENABLESF        (_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
+#define MSA_CSR_ENABLES_IB      7
+#define MSA_CSR_ENABLES_IF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
+#define MSA_CSR_ENABLES_UB      8
+#define MSA_CSR_ENABLES_UF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
+#define MSA_CSR_ENABLES_OB      9
+#define MSA_CSR_ENABLES_OF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
+#define MSA_CSR_ENABLES_ZB      10
+#define MSA_CSR_ENABLES_ZF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
+#define MSA_CSR_ENABLES_VB      11
+#define MSA_CSR_ENABLES_VF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
+#define MSA_CSR_CAUSEB          12
+#define MSA_CSR_CAUSEF          (_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
+#define MSA_CSR_CAUSE_IB        12
+#define MSA_CSR_CAUSE_IF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
+#define MSA_CSR_CAUSE_UB        13
+#define MSA_CSR_CAUSE_UF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
+#define MSA_CSR_CAUSE_OB        14
+#define MSA_CSR_CAUSE_OF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
+#define MSA_CSR_CAUSE_ZB        15
+#define MSA_CSR_CAUSE_ZF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
+#define MSA_CSR_CAUSE_VB        16
+#define MSA_CSR_CAUSE_VF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
+#define MSA_CSR_CAUSE_EB        17
+#define MSA_CSR_CAUSE_EF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
+#define MSA_CSR_NXB             18
+#define MSA_CSR_NXF             (_ULCAST_(0x1) << MSA_CSR_NXB)
+#define MSA_CSR_FSB             24
+#define MSA_CSR_FSF             (_ULCAST_(0x1) << MSA_CSR_FSB)
+
+#endif /* _ASM_MSA_H */
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
new file mode 100644
index 000000000..ff7f074d0
--- /dev/null
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -0,0 +1,147 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
+#define __ASM_MIPS_BOARDS_MSC01_IC_H
+
+/*****************************************************************************
+ * Register offset addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
+#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
+#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
+#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
+#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
+#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
+#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
+#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
+#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
+#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
+#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)         */
+#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
+#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
+#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
+#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
+#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
+#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
+#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
+#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
+#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
+#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
+#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
+#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
+#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
+#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
+#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
+
+/*****************************************************************************
+ * Register field encodings
+ *****************************************************************************/
+
+#define MSC01_IC_RST_RST_SHF      0
+#define MSC01_IC_RST_RST_MSK      0x00000001
+#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
+#define MSC01_IC_LVL_LVL_SHF      0
+#define MSC01_IC_LVL_LVL_MSK      0x000000ff
+#define MSC01_IC_LVL_SPUR_SHF     16
+#define MSC01_IC_LVL_SPUR_MSK     0x00010000
+#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
+#define MSC01_IC_RAMW_RIPL_SHF    0
+#define MSC01_IC_RAMW_RIPL_MSK    0x0000003f
+#define MSC01_IC_RAMW_DATA_SHF    6
+#define MSC01_IC_RAMW_DATA_MSK    0x00000fc0
+#define MSC01_IC_RAMW_ADDR_SHF    25
+#define MSC01_IC_RAMW_ADDR_MSK    0x7e000000
+#define MSC01_IC_RAMW_READ_SHF    31
+#define MSC01_IC_RAMW_READ_MSK    0x80000000
+#define MSC01_IC_RAMW_READ_BIT    MSC01_IC_RAMW_READ_MSK
+#define MSC01_IC_OSB_OSB_SHF      0
+#define MSC01_IC_OSB_OSB_MSK      0x000000ff
+#define MSC01_IC_OSA_OSA_SHF      0
+#define MSC01_IC_OSA_OSA_MSK      0x000000ff
+#define MSC01_IC_GENA_GENA_SHF    0
+#define MSC01_IC_GENA_GENA_MSK    0x00000001
+#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
+#define MSC01_IC_CFG_DIS_SHF      0
+#define MSC01_IC_CFG_DIS_MSK      0x00000001
+#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
+#define MSC01_IC_CFG_SHFT_SHF     8
+#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
+#define MSC01_IC_TCFG_ENA_SHF     0
+#define MSC01_IC_TCFG_ENA_MSK     0x00000001
+#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
+#define MSC01_IC_TCFG_INT_SHF     8
+#define MSC01_IC_TCFG_INT_MSK     0x00000100
+#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
+#define MSC01_IC_TCFG_EDGE_SHF    16
+#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
+#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
+#define MSC01_IC_SUP_PRI_SHF      0
+#define MSC01_IC_SUP_PRI_MSK      0x00000007
+#define MSC01_IC_SUP_EDGE_SHF     8
+#define MSC01_IC_SUP_EDGE_MSK     0x00000100
+#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
+#define MSC01_IC_SUP_STEP         8
+
+/*
+ * MIPS System controller interrupt register base.
+ *
+ */
+
+/*****************************************************************************
+ * Absolute register addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
+#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
+#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
+#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
+#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
+#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
+#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
+#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
+#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
+#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
+#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
+#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
+#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
+#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
+#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
+#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
+#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
+#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
+#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
+#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
+#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
+#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
+#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
+#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
+#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
+#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
+
+/*
+ * Soc-it interrupts are configurable.
+ * Every board describes its IRQ mapping with this table.
+ */
+typedef struct msc_irqmap {
+        int     im_irq;
+        int     im_type;
+        int     im_lvl;
+} msc_irqmap_t;
+
+/* im_type */
+#define MSC01_IRQ_LEVEL         0
+#define MSC01_IRQ_EDGE          1
+
+extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
+extern void ll_msc_irq(void);
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 000000000..57616649b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NETLOGIC_COMMON_H_
+#define _NETLOGIC_COMMON_H_
+
+/*
+ * Common SMP definitions
+ */
+#define RESET_VEC_PHYS          0x1fc00000
+#define RESET_VEC_SIZE          8192            /* 8KB reset code and data */
+#define RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
+
+/* Offsets of parameters in the RESET_DATA_PHYS area */
+#define BOOT_THREAD_MODE        0
+#define BOOT_NMI_LOCK           4
+#define BOOT_NMI_HANDLER        8
+
+/* CPU ready flags for each CPU */
+#define BOOT_CPU_READY          2048
+
+#ifndef __ASSEMBLY__
+#include <linux/cpumask.h>
+#include <linux/spinlock.h>
+#include <asm/irq.h>
+#include <asm/mach-netlogic/multi-node.h>
+
+struct irq_desc;
+void nlm_smp_function_ipi_handler(struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(struct irq_desc *desc);
+void nlm_smp_irq_init(int hwcpuid);
+void nlm_boot_secondary_cpus(void);
+int nlm_wakeup_secondary_cpus(void);
+void nlm_rmiboot_preboot(void);
+void nlm_percpu_init(int hwcpuid);
+
+static inline void *
+nlm_get_boot_data(int offset)
+{
+        return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
+}
+
+static inline void
+nlm_set_nmi_handler(void *handler)
+{
+        void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
+
+        *(int64_t *)nmih = (long)handler;
+}
+
+/*
+ * Misc.
+ */
+void nlm_init_boot_cpu(void);
+unsigned int nlm_get_cpu_frequency(void);
+extern const struct plat_smp_ops nlm_smp_ops;
+extern char nlm_reset_entry[], nlm_reset_entry_end[];
+
+extern unsigned int nlm_threads_per_core;
+extern cpumask_t nlm_cpumask;
+
+struct irq_data;
+uint64_t nlm_pci_irqmask(int node);
+void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
+void nlm_set_pic_extra_ack(int node, int irq,  void (*xack)(struct irq_data *));
+
+#ifdef CONFIG_PCI_MSI
+void nlm_dispatch_msi(int node, int lirq);
+void nlm_dispatch_msix(int node, int msixirq);
+#endif
+
+/*
+ * The NR_IRQs is divided between nodes, each of them has a separate irq space
+ */
+static inline int nlm_irq_to_xirq(int node, int irq)
+{
+        return node * NR_IRQS / NLM_NR_NODES + irq;
+}
+
+#ifdef CONFIG_CPU_XLR
+#define nlm_cores_per_node()    8
+#else
+static inline int nlm_cores_per_node(void)
+{
+        return ((read_c0_prid() & PRID_IMP_MASK)
+                                == PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
+}
+#endif
+static inline int nlm_threads_per_node(void)
+{
+        return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
+}
+
+static inline int nlm_hwtid_to_node(int hwtid)
+{
+        return hwtid / nlm_threads_per_node();
+}
+
+extern int nlm_cpu_ready[];
+#endif /* __ASSEMBLY__ */
+#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 000000000..79c7cccdc
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_HALDEFS_H__
+#define __NLM_HAL_HALDEFS_H__
+
+#include <linux/irqflags.h>     /* for local_irq_disable */
+
+/*
+ * This file contains platform specific memory mapped IO implementation
+ * and will provide a way to read 32/64 bit memory mapped registers in
+ * all ABIs
+ */
+static inline uint32_t
+nlm_read_reg(uint64_t base, uint32_t reg)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        return *addr;
+}
+
+static inline void
+nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        *addr = val;
+}
+
+/*
+ * For o32 compilation, we have to disable interrupts to access 64 bit
+ * registers
+ *
+ * We need to disable interrupts because we save just the lower 32 bits of
+ * registers in  interrupt handling. So if we get hit by an interrupt while
+ * using the upper 32 bits of a register, we lose.
+ */
+
+static inline uint64_t
+nlm_read_reg64(uint64_t base, uint32_t reg)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+        uint64_t val;
+
+        if (sizeof(unsigned long) == 4) {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                __asm__ __volatile__(
+                        ".set   push"                   "\n\t"
+                        ".set   mips64"                 "\n\t"
+                        "ld     %L0, %1"                "\n\t"
+                        "dsra32 %M0, %L0, 0"            "\n\t"
+                        "sll    %L0, %L0, 0"            "\n\t"
+                        ".set   pop"                    "\n"
+                        : "=r" (val)
+                        : "m" (*ptr));
+                local_irq_restore(flags);
+        } else
+                val = *ptr;
+
+        return val;
+}
+
+static inline void
+nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+
+        if (sizeof(unsigned long) == 4) {
+                unsigned long flags;
+                uint64_t tmp;
+
+                local_irq_save(flags);
+                __asm__ __volatile__(
+                        ".set   push"                   "\n\t"
+                        ".set   mips64"                 "\n\t"
+                        "dsll32 %L0, %L0, 0"            "\n\t"
+                        "dsrl32 %L0, %L0, 0"            "\n\t"
+                        "dsll32 %M0, %M0, 0"            "\n\t"
+                        "or     %L0, %L0, %M0"          "\n\t"
+                        "sd     %L0, %2"                "\n\t"
+                        ".set   pop"                    "\n"
+                        : "=r" (tmp)
+                        : "0" (val), "m" (*ptr));
+                local_irq_restore(flags);
+        } else
+                *ptr = val;
+}
+
+/*
+ * Routines to store 32/64 bit values to 64 bit addresses,
+ * used when going thru XKPHYS to access registers
+ */
+static inline uint32_t
+nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg(base, reg);
+}
+
+static inline void
+nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
+{
+        nlm_write_reg(base, reg, val);
+}
+
+static inline uint64_t
+nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg64(base, reg);
+}
+
+static inline void
+nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
+{
+        nlm_write_reg64(base, reg, val);
+}
+
+/* Location where IO base is mapped */
+extern uint64_t nlm_io_base;
+
+#if defined(CONFIG_CPU_XLP)
+static inline uint64_t
+nlm_pcicfg_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+
+#elif defined(CONFIG_CPU_XLR)
+
+static inline uint64_t
+nlm_mmio_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
new file mode 100644
index 000000000..ed5993d9b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_INTERRUPT_H
+#define _ASM_NLM_INTERRUPT_H
+
+/* Defines for the IRQ numbers */
+
+#define IRQ_IPI_SMP_FUNCTION    3
+#define IRQ_IPI_SMP_RESCHEDULE  4
+#define IRQ_FMN                 5
+#define IRQ_TIMER               7
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
new file mode 100644
index 000000000..788baf399
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_MIPS_EXTS_H
+#define _ASM_NLM_MIPS_EXTS_H
+
+/*
+ * XLR and XLP interrupt request and interrupt mask registers
+ */
+/*
+ * NOTE: Do not save/restore flags around write_c0_eimr().
+ * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
+ * register. Restoring flags will overwrite the lower 8 bits of EIMR.
+ *
+ * Call with interrupts disabled.
+ */
+#define write_c0_eimr(val)                                              \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4) {                               \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, $9, 7\n\t"                         \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+        } else                                                          \
+                __write_64bit_c0_register($9, 7, (val));                \
+} while (0)
+
+/*
+ * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
+ * standard functions will be very inefficient. This provides
+ * optimized functions for the normal operations on the registers.
+ *
+ * Call with interrupts disabled.
+ */
+static inline void ack_c0_eirr(int irq)
+{
+        __asm__ __volatile__(
+                ".set   push\n\t"
+                ".set   mips64\n\t"
+                ".set   noat\n\t"
+                "li     $1, 1\n\t"
+                "dsllv  $1, $1, %0\n\t"
+                "dmtc0  $1, $9, 6\n\t"
+                ".set   pop"
+                : : "r" (irq));
+}
+
+static inline void set_c0_eimr(int irq)
+{
+        __asm__ __volatile__(
+                ".set   push\n\t"
+                ".set   mips64\n\t"
+                ".set   noat\n\t"
+                "li     $1, 1\n\t"
+                "dsllv  %0, $1, %0\n\t"
+                "dmfc0  $1, $9, 7\n\t"
+                "or     $1, %0\n\t"
+                "dmtc0  $1, $9, 7\n\t"
+                ".set   pop"
+                : "+r" (irq));
+}
+
+static inline void clear_c0_eimr(int irq)
+{
+        __asm__ __volatile__(
+                ".set   push\n\t"
+                ".set   mips64\n\t"
+                ".set   noat\n\t"
+                "li     $1, 1\n\t"
+                "dsllv  %0, $1, %0\n\t"
+                "dmfc0  $1, $9, 7\n\t"
+                "or     $1, %0\n\t"
+                "xor    $1, %0\n\t"
+                "dmtc0  $1, $9, 7\n\t"
+                ".set   pop"
+                : "+r" (irq));
+}
+
+/*
+ * Read c0 eimr and c0 eirr, do AND of the two values, the result is
+ * the interrupts which are raised and are not masked.
+ */
+static inline uint64_t read_c0_eirr_and_eimr(void)
+{
+        uint64_t val;
+
+#ifdef CONFIG_64BIT
+        val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
+#else
+        __asm__ __volatile__(
+                ".set   push\n\t"
+                ".set   mips64\n\t"
+                ".set   noat\n\t"
+                "dmfc0  %M0, $9, 6\n\t"
+                "dmfc0  %L0, $9, 7\n\t"
+                "and    %M0, %L0\n\t"
+                "dsll   %L0, %M0, 32\n\t"
+                "dsra   %M0, %M0, 32\n\t"
+                "dsra   %L0, %L0, 32\n\t"
+                ".set   pop"
+                : "=r" (val));
+#endif
+        return val;
+}
+
+static inline int hard_smp_processor_id(void)
+{
+        return __read_32bit_c0_register($15, 1) & 0x3ff;
+}
+
+static inline int nlm_nodeid(void)
+{
+        uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
+
+        if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+                        (prid == PRID_IMP_NETLOGIC_XLP5XX))
+                return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
+        else
+                return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
+}
+
+static inline unsigned int nlm_core_id(void)
+{
+        uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
+
+        if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+                        (prid == PRID_IMP_NETLOGIC_XLP5XX))
+                return (read_c0_ebase() & 0x7c) >> 2;
+        else
+                return (read_c0_ebase() & 0x1c) >> 2;
+}
+
+static inline unsigned int nlm_thread_id(void)
+{
+        return read_c0_ebase() & 0x3;
+}
+
+#define __read_64bit_c2_split(source, sel)                              \
+({                                                                      \
+        unsigned long long __val;                                       \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc2\t%M0, " #source "\n\t"                   \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsra\t%M0, %M0, 32\n\t"                        \
+                        "dsra\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__val));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc2\t%M0, " #source ", " #sel "\n\t"         \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsra\t%M0, %M0, 32\n\t"                        \
+                        "dsra\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__val));                                \
+        local_irq_restore(__flags);                                     \
+                                                                        \
+        __val;                                                          \
+})
+
+#define __write_64bit_c2_split(source, sel, val)                        \
+do {                                                                    \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc2\t%L0, " #source "\n\t"                   \
+                        ".set\tmips0\n\t"                               \
+                        : : "r" (val));                                 \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc2\t%L0, " #source ", " #sel "\n\t"         \
+                        ".set\tmips0\n\t"                               \
+                        : : "r" (val));                                 \
+        local_irq_restore(__flags);                                     \
+} while (0)
+
+#define __read_32bit_c2_register(source, sel)                           \
+({ uint32_t __res;                                                      \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mfc2\t%0, " #source "\n\t"                     \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mfc2\t%0, " #source ", " #sel "\n\t"           \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __read_64bit_c2_register(source, sel)                           \
+({ unsigned long long __res;                                            \
+        if (sizeof(unsigned long) == 4)                                 \
+                __res = __read_64bit_c2_split(source, sel);             \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc2\t%0, " #source "\n\t"                    \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc2\t%0, " #source ", " #sel "\n\t"          \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __write_64bit_c2_register(register, sel, value)                 \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_64bit_c2_split(register, sel, value);           \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmtc2\t%z0, " #register "\n\t"                 \
+                        ".set\tmips0\n\t"                               \
+                        : : "Jr" (value));                              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmtc2\t%z0, " #register ", " #sel "\n\t"       \
+                        ".set\tmips0\n\t"                               \
+                        : : "Jr" (value));                              \
+} while (0)
+
+#define __write_32bit_c2_register(reg, sel, value)                      \
+({                                                                      \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mtc2\t%z0, " #reg "\n\t"                       \
+                        ".set\tmips0\n\t"                               \
+                        : : "Jr" (value));                              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mtc2\t%z0, " #reg ", " #sel "\n\t"             \
+                        ".set\tmips0\n\t"                               \
+                        : : "Jr" (value));                              \
+})
+
+#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h
new file mode 100644
index 000000000..c716e9397
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NETLOGIC_BOOTINFO_H
+#define _ASM_NETLOGIC_BOOTINFO_H
+
+struct psb_info {
+        uint64_t boot_level;
+        uint64_t io_base;
+        uint64_t output_device;
+        uint64_t uart_print;
+        uint64_t led_output;
+        uint64_t init;
+        uint64_t exit;
+        uint64_t warm_reset;
+        uint64_t wakeup;
+        uint64_t online_cpu_map;
+        uint64_t master_reentry_sp;
+        uint64_t master_reentry_gp;
+        uint64_t master_reentry_fn;
+        uint64_t slave_reentry_fn;
+        uint64_t magic_dword;
+        uint64_t uart_putchar;
+        uint64_t size;
+        uint64_t uart_getchar;
+        uint64_t nmi_handler;
+        uint64_t psb_version;
+        uint64_t mac_addr;
+        uint64_t cpu_frequency;
+        uint64_t board_version;
+        uint64_t malloc;
+        uint64_t free;
+        uint64_t global_shmem_addr;
+        uint64_t global_shmem_size;
+        uint64_t psb_os_cpu_map;
+        uint64_t userapp_cpu_map;
+        uint64_t wakeup_os;
+        uint64_t psb_mem_map;
+        uint64_t board_major_version;
+        uint64_t board_minor_version;
+        uint64_t board_manf_revision;
+        uint64_t board_serial_number;
+        uint64_t psb_physaddr_map;
+        uint64_t xlr_loaderip_config;
+        uint64_t bldr_envp;
+        uint64_t avail_mem_map;
+};
+
+/* This is what netlboot passes and linux boot_mem_map is subtly different */
+#define NLM_BOOT_MEM_MAP_MAX    32
+struct nlm_boot_mem_map {
+        int nr_map;
+        struct nlm_boot_mem_map_entry {
+                uint64_t addr;          /* start of memory segment */
+                uint64_t size;          /* size of memory segment */
+                uint32_t type;          /* type of memory segment */
+        } map[NLM_BOOT_MEM_MAP_MAX];
+};
+#define NLM_BOOT_MEM_RAM        1
+
+/* Pointer to saved boot loader info */
+extern struct psb_info nlm_prom_info;
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000..3067f9834
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
+
+/**
+* @file_name mio.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP memory and io subsystem
+*/
+
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE                     0x00
+#define BRIDGE_PCI_CFG_BASE             0x01
+#define BRIDGE_PCI_CFG_LIMIT            0x02
+#define BRIDGE_PCIE_CFG_BASE            0x03
+#define BRIDGE_PCIE_CFG_LIMIT           0x04
+#define BRIDGE_BUSNUM_BAR0              0x05
+#define BRIDGE_BUSNUM_BAR1              0x06
+#define BRIDGE_BUSNUM_BAR2              0x07
+#define BRIDGE_BUSNUM_BAR3              0x08
+#define BRIDGE_BUSNUM_BAR4              0x09
+#define BRIDGE_BUSNUM_BAR5              0x0a
+#define BRIDGE_BUSNUM_BAR6              0x0b
+#define BRIDGE_FLASH_BAR0               0x0c
+#define BRIDGE_FLASH_BAR1               0x0d
+#define BRIDGE_FLASH_BAR2               0x0e
+#define BRIDGE_FLASH_BAR3               0x0f
+#define BRIDGE_FLASH_LIMIT0             0x10
+#define BRIDGE_FLASH_LIMIT1             0x11
+#define BRIDGE_FLASH_LIMIT2             0x12
+#define BRIDGE_FLASH_LIMIT3             0x13
+
+#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
+#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
+#define BRIDGE_DRAM_NODE_TRANSLN(i)     (0x24 + (i))
+#define BRIDGE_DRAM_CHNL_TRANSLN(i)     (0x2c + (i))
+
+#define BRIDGE_PCIEMEM_BASE0            0x34
+#define BRIDGE_PCIEMEM_BASE1            0x35
+#define BRIDGE_PCIEMEM_BASE2            0x36
+#define BRIDGE_PCIEMEM_BASE3            0x37
+#define BRIDGE_PCIEMEM_LIMIT0           0x38
+#define BRIDGE_PCIEMEM_LIMIT1           0x39
+#define BRIDGE_PCIEMEM_LIMIT2           0x3a
+#define BRIDGE_PCIEMEM_LIMIT3           0x3b
+#define BRIDGE_PCIEIO_BASE0             0x3c
+#define BRIDGE_PCIEIO_BASE1             0x3d
+#define BRIDGE_PCIEIO_BASE2             0x3e
+#define BRIDGE_PCIEIO_BASE3             0x3f
+#define BRIDGE_PCIEIO_LIMIT0            0x40
+#define BRIDGE_PCIEIO_LIMIT1            0x41
+#define BRIDGE_PCIEIO_LIMIT2            0x42
+#define BRIDGE_PCIEIO_LIMIT3            0x43
+#define BRIDGE_PCIEMEM_BASE4            0x44
+#define BRIDGE_PCIEMEM_BASE5            0x45
+#define BRIDGE_PCIEMEM_BASE6            0x46
+#define BRIDGE_PCIEMEM_LIMIT4           0x47
+#define BRIDGE_PCIEMEM_LIMIT5           0x48
+#define BRIDGE_PCIEMEM_LIMIT6           0x49
+#define BRIDGE_PCIEIO_BASE4             0x4a
+#define BRIDGE_PCIEIO_BASE5             0x4b
+#define BRIDGE_PCIEIO_BASE6             0x4c
+#define BRIDGE_PCIEIO_LIMIT4            0x4d
+#define BRIDGE_PCIEIO_LIMIT5            0x4e
+#define BRIDGE_PCIEIO_LIMIT6            0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL        0x50
+#define BRIDGE_EVNTCTR1_LOW             0x51
+#define BRIDGE_EVNTCTR1_HI              0x52
+#define BRIDGE_EVNT_CNT_CTL2            0x53
+#define BRIDGE_EVNTCTR2_LOW             0x54
+#define BRIDGE_EVNTCTR2_HI              0x55
+#define BRIDGE_TRACEBUF_MATCH0          0x56
+#define BRIDGE_TRACEBUF_MATCH1          0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW       0x58
+#define BRIDGE_TRACEBUF_MATCH_HI        0x59
+#define BRIDGE_TRACEBUF_CTRL            0x5a
+#define BRIDGE_TRACEBUF_INIT            0x5b
+#define BRIDGE_TRACEBUF_ACCESS          0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2      0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3      0x60
+#define BRIDGE_TRACEBUF_STATUS          0x61
+#define BRIDGE_ADDRESS_ERROR0           0x62
+#define BRIDGE_ADDRESS_ERROR1           0x63
+#define BRIDGE_ADDRESS_ERROR2           0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0      0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1      0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2      0x67
+#define BRIDGE_LINE_FLUSH0              0x68
+#define BRIDGE_LINE_FLUSH1              0x69
+#define BRIDGE_NODE_ID                  0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN       0x6b
+#define BRIDGE_PCIE0_WEIGHT             0x2c0
+#define BRIDGE_PCIE1_WEIGHT             0x2c1
+#define BRIDGE_PCIE2_WEIGHT             0x2c2
+#define BRIDGE_PCIE3_WEIGHT             0x2c3
+#define BRIDGE_USB_WEIGHT               0x2c4
+#define BRIDGE_NET_WEIGHT               0x2c5
+#define BRIDGE_POE_WEIGHT               0x2c6
+#define BRIDGE_CMS_WEIGHT               0x2c7
+#define BRIDGE_DMAENG_WEIGHT            0x2c8
+#define BRIDGE_SEC_WEIGHT               0x2c9
+#define BRIDGE_COMP_WEIGHT              0x2ca
+#define BRIDGE_GIO_WEIGHT               0x2cb
+#define BRIDGE_FLASH_WEIGHT             0x2cc
+
+/* FIXME verify */
+#define BRIDGE_9XX_FLASH_BAR(i)         (0x11 + (i))
+#define BRIDGE_9XX_FLASH_BAR_LIMIT(i)   (0x15 + (i))
+
+#define BRIDGE_9XX_DRAM_BAR(i)          (0x19 + (i))
+#define BRIDGE_9XX_DRAM_LIMIT(i)        (0x29 + (i))
+#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
+#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
+
+#define BRIDGE_9XX_ADDRESS_ERROR0       0x9d
+#define BRIDGE_9XX_ADDRESS_ERROR1       0x9e
+#define BRIDGE_9XX_ADDRESS_ERROR2       0x9f
+
+#define BRIDGE_9XX_PCIEMEM_BASE0        0x59
+#define BRIDGE_9XX_PCIEMEM_BASE1        0x5a
+#define BRIDGE_9XX_PCIEMEM_BASE2        0x5b
+#define BRIDGE_9XX_PCIEMEM_BASE3        0x5c
+#define BRIDGE_9XX_PCIEMEM_LIMIT0       0x5d
+#define BRIDGE_9XX_PCIEMEM_LIMIT1       0x5e
+#define BRIDGE_9XX_PCIEMEM_LIMIT2       0x5f
+#define BRIDGE_9XX_PCIEMEM_LIMIT3       0x60
+#define BRIDGE_9XX_PCIEIO_BASE0         0x61
+#define BRIDGE_9XX_PCIEIO_BASE1         0x62
+#define BRIDGE_9XX_PCIEIO_BASE2         0x63
+#define BRIDGE_9XX_PCIEIO_BASE3         0x64
+#define BRIDGE_9XX_PCIEIO_LIMIT0        0x65
+#define BRIDGE_9XX_PCIEIO_LIMIT1        0x66
+#define BRIDGE_9XX_PCIEIO_LIMIT2        0x67
+#define BRIDGE_9XX_PCIEIO_LIMIT3        0x68
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
+#define nlm_get_bridge_pcibase(node)    nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_regbase(node)    \
+                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 000000000..a06b59292
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
+
+#define CPU_BLOCKID_IFU         0
+#define CPU_BLOCKID_ICU         1
+#define CPU_BLOCKID_IEU         2
+#define CPU_BLOCKID_LSU         3
+#define CPU_BLOCKID_MMU         4
+#define CPU_BLOCKID_PRF         5
+#define CPU_BLOCKID_SCH         7
+#define CPU_BLOCKID_SCU         8
+#define CPU_BLOCKID_FPU         9
+#define CPU_BLOCKID_MAP         10
+
+#define IFU_BRUB_RESERVE        0x007
+
+#define ICU_DEFEATURE           0x100
+
+#define LSU_DEFEATURE           0x304
+#define LSU_DEBUG_ADDR          0x305
+#define LSU_DEBUG_DATA0         0x306
+#define LSU_CERRLOG_REGID       0x309
+#define SCHED_DEFEATURE         0x700
+
+/* Offsets of interest from the 'MAP' Block */
+#define MAP_THREADMODE                  0x00
+#define MAP_EXT_EBASE_ENABLE            0x04
+#define MAP_CCDI_CONFIG                 0x08
+#define MAP_THRD0_CCDI_STATUS           0x0c
+#define MAP_THRD1_CCDI_STATUS           0x10
+#define MAP_THRD2_CCDI_STATUS           0x14
+#define MAP_THRD3_CCDI_STATUS           0x18
+#define MAP_THRD0_DEBUG_MODE            0x1c
+#define MAP_THRD1_DEBUG_MODE            0x20
+#define MAP_THRD2_DEBUG_MODE            0x24
+#define MAP_THRD3_DEBUG_MODE            0x28
+#define MAP_MISC_STATE                  0x60
+#define MAP_DEBUG_READ_CTL              0x64
+#define MAP_DEBUG_READ_REG0             0x68
+#define MAP_DEBUG_READ_REG1             0x6c
+
+#define MMU_SETUP               0x400
+#define MMU_LFSRSEED            0x401
+#define MMU_HPW_NUM_PAGE_LVL    0x410
+#define MMU_PGWKR_PGDBASE       0x411
+#define MMU_PGWKR_PGDSHFT       0x412
+#define MMU_PGWKR_PGDMASK       0x413
+#define MMU_PGWKR_PUDSHFT       0x414
+#define MMU_PGWKR_PUDMASK       0x415
+#define MMU_PGWKR_PMDSHFT       0x416
+#define MMU_PGWKR_PMDMASK       0x417
+#define MMU_PGWKR_PTESHFT       0x418
+#define MMU_PGWKR_PTEMASK       0x419
+
+#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 000000000..805bfd21f
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_IOMAP_H__
+#define __NLM_HAL_IOMAP_H__
+
+#define XLP_DEFAULT_IO_BASE             0x18000000
+#define XLP_DEFAULT_PCI_ECFG_BASE       XLP_DEFAULT_IO_BASE
+#define XLP_DEFAULT_PCI_CFG_BASE        0x1c000000
+
+#define NMI_BASE                        0xbfc00000
+#define XLP_IO_CLK                      133333333
+
+#define XLP_PCIE_CFG_SIZE               0x1000          /* 4K */
+#define XLP_PCIE_DEV_BLK_SIZE           (8 * XLP_PCIE_CFG_SIZE)
+#define XLP_PCIE_BUS_BLK_SIZE           (256 * XLP_PCIE_DEV_BLK_SIZE)
+#define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
+#define XLP_IO_PCI_HDRSZ                0x100
+#define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
+#define XLP_IO_PCI_OFFSET(b, d, f)      (((b) << 20) | ((d) << 15) | ((f) << 12))
+
+#define XLP_HDR_OFFSET(node, bus, dev, fn) \
+                XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
+
+#define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
+/* coherent inter chip */
+#define XLP_IO_CIC0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 1)
+#define XLP_IO_CIC1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 2)
+#define XLP_IO_CIC2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 3)
+#define XLP_IO_PIC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 0, 4)
+
+#define XLP_IO_PCIE_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 1, i)
+#define XLP_IO_PCIE0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 0)
+#define XLP_IO_PCIE1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 1)
+#define XLP_IO_PCIE2_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 2)
+#define XLP_IO_PCIE3_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 3)
+
+#define XLP_IO_USB_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 2, i)
+#define XLP_IO_USB_EHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 0)
+#define XLP_IO_USB_OHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 1)
+#define XLP_IO_USB_OHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 2)
+#define XLP_IO_USB_EHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 3)
+#define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
+#define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
+
+#define XLP_IO_SATA_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 3, 2)
+
+/* XLP2xx has an updated USB block */
+#define XLP2XX_IO_USB_OFFSET(node, i)   XLP_HDR_OFFSET(node, 0, 4, i)
+#define XLP2XX_IO_USB_XHCI0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 1)
+#define XLP2XX_IO_USB_XHCI1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 2)
+#define XLP2XX_IO_USB_XHCI2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 3)
+
+#define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
+#define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
+
+#define XLP_IO_CMS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 4, 0)
+
+#define XLP_IO_DMA_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 1)
+#define XLP_IO_SEC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 2)
+#define XLP_IO_CMP_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 3)
+
+#define XLP_IO_UART_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 6, i)
+#define XLP_IO_UART0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 0)
+#define XLP_IO_UART1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 1)
+#define XLP_IO_I2C_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 6, 2 + i)
+#define XLP_IO_I2C0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 2)
+#define XLP_IO_I2C1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 3)
+#define XLP_IO_GPIO_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 4)
+/* on 2XX, all I2C busses are on the same block */
+#define XLP2XX_IO_I2C_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 6, 7)
+
+/* system management */
+#define XLP_IO_SYS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 6, 5)
+#define XLP_IO_JTAG_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 6)
+
+/* Flash */
+#define XLP_IO_NOR_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 0)
+#define XLP_IO_NAND_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 7, 1)
+#define XLP_IO_SPI_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 2)
+#define XLP_IO_MMC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 3)
+
+/* Things have changed drastically in XLP 9XX */
+#define XLP9XX_HDR_OFFSET(n, d, f)      \
+                        XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
+
+#define XLP9XX_IO_BRIDGE_OFFSET(node)   XLP_IO_PCI_OFFSET(0, 0, node)
+#define XLP9XX_IO_PIC_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 2, 0)
+#define XLP9XX_IO_UART_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 2, 2)
+#define XLP9XX_IO_SYS_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 6, 0)
+#define XLP9XX_IO_FUSE_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 1)
+#define XLP9XX_IO_CLOCK_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 6, 2)
+#define XLP9XX_IO_POWER_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 6, 3)
+#define XLP9XX_IO_JTAG_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 4)
+
+#define XLP9XX_IO_PCIE_OFFSET(node, i)  XLP9XX_HDR_OFFSET(node, 1, i)
+#define XLP9XX_IO_PCIE0_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 0)
+#define XLP9XX_IO_PCIE2_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 2)
+#define XLP9XX_IO_PCIE3_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 3)
+
+/* XLP9xx USB block */
+#define XLP9XX_IO_USB_OFFSET(node, i)           XLP9XX_HDR_OFFSET(node, 4, i)
+#define XLP9XX_IO_USB_XHCI0_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 1)
+#define XLP9XX_IO_USB_XHCI1_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 2)
+
+/* XLP9XX on-chip SATA controller */
+#define XLP9XX_IO_SATA_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 3, 2)
+
+/* Flash */
+#define XLP9XX_IO_NOR_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 0)
+#define XLP9XX_IO_NAND_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 7, 1)
+#define XLP9XX_IO_SPI_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 2)
+#define XLP9XX_IO_MMC_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 3)
+
+/* PCI config header register id's */
+#define XLP_PCI_CFGREG0                 0x00
+#define XLP_PCI_CFGREG1                 0x01
+#define XLP_PCI_CFGREG2                 0x02
+#define XLP_PCI_CFGREG3                 0x03
+#define XLP_PCI_CFGREG4                 0x04
+#define XLP_PCI_CFGREG5                 0x05
+#define XLP_PCI_DEVINFO_REG0            0x30
+#define XLP_PCI_DEVINFO_REG1            0x31
+#define XLP_PCI_DEVINFO_REG2            0x32
+#define XLP_PCI_DEVINFO_REG3            0x33
+#define XLP_PCI_DEVINFO_REG4            0x34
+#define XLP_PCI_DEVINFO_REG5            0x35
+#define XLP_PCI_DEVINFO_REG6            0x36
+#define XLP_PCI_DEVINFO_REG7            0x37
+#define XLP_PCI_DEVSCRATCH_REG0         0x38
+#define XLP_PCI_DEVSCRATCH_REG1         0x39
+#define XLP_PCI_DEVSCRATCH_REG2         0x3a
+#define XLP_PCI_DEVSCRATCH_REG3         0x3b
+#define XLP_PCI_MSGSTN_REG              0x3c
+#define XLP_PCI_IRTINFO_REG             0x3d
+#define XLP_PCI_UCODEINFO_REG           0x3e
+#define XLP_PCI_SBB_WT_REG              0x3f
+
+/* PCI IDs for SoC device */
+#define PCI_VENDOR_NETLOGIC             0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT          0x1001
+#define PCI_DEVICE_ID_NLM_ICI           0x1002
+#define PCI_DEVICE_ID_NLM_PIC           0x1003
+#define PCI_DEVICE_ID_NLM_PCIE          0x1004
+#define PCI_DEVICE_ID_NLM_EHCI          0x1007
+#define PCI_DEVICE_ID_NLM_OHCI          0x1008
+#define PCI_DEVICE_ID_NLM_NAE           0x1009
+#define PCI_DEVICE_ID_NLM_POE           0x100A
+#define PCI_DEVICE_ID_NLM_FMN           0x100B
+#define PCI_DEVICE_ID_NLM_RAID          0x100D
+#define PCI_DEVICE_ID_NLM_SAE           0x100D
+#define PCI_DEVICE_ID_NLM_RSA           0x100E
+#define PCI_DEVICE_ID_NLM_CMP           0x100F
+#define PCI_DEVICE_ID_NLM_UART          0x1010
+#define PCI_DEVICE_ID_NLM_I2C           0x1011
+#define PCI_DEVICE_ID_NLM_NOR           0x1015
+#define PCI_DEVICE_ID_NLM_NAND          0x1016
+#define PCI_DEVICE_ID_NLM_MMC           0x1018
+#define PCI_DEVICE_ID_NLM_SATA          0x101A
+#define PCI_DEVICE_ID_NLM_XHCI          0x101D
+
+#define PCI_DEVICE_ID_XLP9XX_MMC        0x9018
+#define PCI_DEVICE_ID_XLP9XX_SATA       0x901A
+#define PCI_DEVICE_ID_XLP9XX_XHCI       0x901D
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
+
+static inline int xlp9xx_get_socbus(int node)
+{
+        uint64_t socbridge;
+
+        if (node == 0)
+                return 1;
+        socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
+        return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
+}
+#endif /* !__ASSEMBLY */
+
+#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
new file mode 100644
index 000000000..91540f41e
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_PCIBUS_H__
+#define __NLM_HAL_PCIBUS_H__
+
+/* PCIE Memory and IO regions */
+#define PCIE_MEM_BASE                   0xd0000000ULL
+#define PCIE_MEM_LIMIT                  0xdfffffffULL
+#define PCIE_IO_BASE                    0x14000000ULL
+#define PCIE_IO_LIMIT                   0x15ffffffULL
+
+#define PCIE_BRIDGE_CMD                 0x1
+#define PCIE_BRIDGE_MSI_CAP             0x14
+#define PCIE_BRIDGE_MSI_ADDRL           0x15
+#define PCIE_BRIDGE_MSI_ADDRH           0x16
+#define PCIE_BRIDGE_MSI_DATA            0x17
+
+/* XLP Global PCIE configuration space registers */
+#define PCIE_BYTE_SWAP_MEM_BASE         0x247
+#define PCIE_BYTE_SWAP_MEM_LIM          0x248
+#define PCIE_BYTE_SWAP_IO_BASE          0x249
+#define PCIE_BYTE_SWAP_IO_LIM           0x24A
+
+#define PCIE_BRIDGE_MSIX_ADDR_BASE      0x24F
+#define PCIE_BRIDGE_MSIX_ADDR_LIMIT     0x250
+#define PCIE_MSI_STATUS                 0x25A
+#define PCIE_MSI_EN                     0x25B
+#define PCIE_MSIX_STATUS                0x25D
+#define PCIE_INT_STATUS0                0x25F
+#define PCIE_INT_STATUS1                0x260
+#define PCIE_INT_EN0                    0x261
+#define PCIE_INT_EN1                    0x262
+
+/* XLP9XX has basic changes */
+#define PCIE_9XX_BYTE_SWAP_MEM_BASE     0x25c
+#define PCIE_9XX_BYTE_SWAP_MEM_LIM      0x25d
+#define PCIE_9XX_BYTE_SWAP_IO_BASE      0x25e
+#define PCIE_9XX_BYTE_SWAP_IO_LIM       0x25f
+
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE  0x264
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
+#define PCIE_9XX_MSI_STATUS             0x283
+#define PCIE_9XX_MSI_EN                 0x284
+/* 128 MSIX vectors available in 9xx */
+#define PCIE_9XX_MSIX_STATUS0           0x286
+#define PCIE_9XX_MSIX_STATUSX(n)        (n + 0x286)
+#define PCIE_9XX_MSIX_VEC               0x296
+#define PCIE_9XX_MSIX_VECX(n)           (n + 0x296)
+#define PCIE_9XX_INT_STATUS0            0x397
+#define PCIE_9XX_INT_STATUS1            0x398
+#define PCIE_9XX_INT_EN0                0x399
+#define PCIE_9XX_INT_EN1                0x39a
+
+/* other */
+#define PCIE_NLINKS                     4
+
+/* MSI addresses */
+#define MSI_ADDR_BASE                   0xfffee00000ULL
+#define MSI_ADDR_SZ                     0x10000
+#define MSI_LINK_ADDR(n, l)             (MSI_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
+#define MSIX_ADDR_BASE                  0xfffef00000ULL
+#define MSIX_LINK_ADDR(n, l)            (MSIX_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
+#ifndef __ASSEMBLY__
+
+#define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_pcie_base(node, inst)   nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+        XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
+
+#ifdef CONFIG_PCI_MSI
+void xlp_init_node_msi_irqs(int node, int link);
+#else
+static inline void xlp_init_node_msi_irqs(int node, int link) {}
+#endif
+
+struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
+
+#endif
+#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 000000000..41cefe94f
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NLM_HAL_PIC_H
+#define _NLM_HAL_PIC_H
+
+/* PIC Specific registers */
+#define PIC_CTRL                0x00
+
+/* PIC control register defines */
+#define PIC_CTRL_ITV            32 /* interrupt timeout value */
+#define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
+#define PIC_CTRL_ITE            18 /* interrupt timeout enable */
+#define PIC_CTRL_STE            10 /* system timer interrupt enable */
+#define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
+#define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
+#define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
+#define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
+#define PIC_CTRL_WTE            0  /* watchdog timer enable */
+
+/* PIC Status register defines */
+#define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
+#define PIC_ITE_STATUS          32 /* interrupt timeout status */
+#define PIC_STS_STATUS          4  /* System timer interrupt status */
+#define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
+#define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
+
+/* PIC IPI control register offsets */
+#define PIC_IPICTRL_NMI         32
+#define PIC_IPICTRL_RIV         20 /* received interrupt vector */
+#define PIC_IPICTRL_IDB         16 /* interrupt destination base */
+#define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
+
+/* PIC IRT register offsets */
+#define PIC_IRT_ENABLE          31
+#define PIC_IRT_NMI             29
+#define PIC_IRT_SCH             28 /* Scheduling scheme */
+#define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
+#define PIC_IRT_DT              19 /* Destination type */
+#define PIC_IRT_DB              16 /* Destination base */
+#define PIC_IRT_DTE             0  /* Destination thread enables */
+
+#define PIC_BYTESWAP            0x02
+#define PIC_STATUS              0x04
+#define PIC_INTR_TIMEOUT        0x06
+#define PIC_ICI0_INTR_TIMEOUT   0x08
+#define PIC_ICI1_INTR_TIMEOUT   0x0a
+#define PIC_ICI2_INTR_TIMEOUT   0x0c
+#define PIC_IPI_CTL             0x0e
+#define PIC_INT_ACK             0x10
+#define PIC_INT_PENDING0        0x12
+#define PIC_INT_PENDING1        0x14
+#define PIC_INT_PENDING2        0x16
+
+#define PIC_WDOG0_MAXVAL        0x18
+#define PIC_WDOG0_COUNT         0x1a
+#define PIC_WDOG0_ENABLE0       0x1c
+#define PIC_WDOG0_ENABLE1       0x1e
+#define PIC_WDOG0_BEATCMD       0x20
+#define PIC_WDOG0_BEAT0         0x22
+#define PIC_WDOG0_BEAT1         0x24
+
+#define PIC_WDOG1_MAXVAL        0x26
+#define PIC_WDOG1_COUNT         0x28
+#define PIC_WDOG1_ENABLE0       0x2a
+#define PIC_WDOG1_ENABLE1       0x2c
+#define PIC_WDOG1_BEATCMD       0x2e
+#define PIC_WDOG1_BEAT0         0x30
+#define PIC_WDOG1_BEAT1         0x32
+
+#define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
+#define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
+
+#define PIC_TIMER0_MAXVAL    0x34
+#define PIC_TIMER1_MAXVAL    0x36
+#define PIC_TIMER2_MAXVAL    0x38
+#define PIC_TIMER3_MAXVAL    0x3a
+#define PIC_TIMER4_MAXVAL    0x3c
+#define PIC_TIMER5_MAXVAL    0x3e
+#define PIC_TIMER6_MAXVAL    0x40
+#define PIC_TIMER7_MAXVAL    0x42
+#define PIC_TIMER_MAXVAL(i)  (PIC_TIMER0_MAXVAL + ((i) * 2))
+
+#define PIC_TIMER0_COUNT     0x44
+#define PIC_TIMER1_COUNT     0x46
+#define PIC_TIMER2_COUNT     0x48
+#define PIC_TIMER3_COUNT     0x4a
+#define PIC_TIMER4_COUNT     0x4c
+#define PIC_TIMER5_COUNT     0x4e
+#define PIC_TIMER6_COUNT     0x50
+#define PIC_TIMER7_COUNT     0x52
+#define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
+
+#define PIC_ITE0_N0_N1          0x54
+#define PIC_ITE1_N0_N1          0x58
+#define PIC_ITE2_N0_N1          0x5c
+#define PIC_ITE3_N0_N1          0x60
+#define PIC_ITE4_N0_N1          0x64
+#define PIC_ITE5_N0_N1          0x68
+#define PIC_ITE6_N0_N1          0x6c
+#define PIC_ITE7_N0_N1          0x70
+#define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
+
+#define PIC_ITE0_N2_N3          0x56
+#define PIC_ITE1_N2_N3          0x5a
+#define PIC_ITE2_N2_N3          0x5e
+#define PIC_ITE3_N2_N3          0x62
+#define PIC_ITE4_N2_N3          0x66
+#define PIC_ITE5_N2_N3          0x6a
+#define PIC_ITE6_N2_N3          0x6e
+#define PIC_ITE7_N2_N3          0x72
+#define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
+
+#define PIC_IRT0                0x74
+#define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
+
+#define PIC_9XX_PENDING_0       0x6
+#define PIC_9XX_PENDING_1       0x8
+#define PIC_9XX_PENDING_2       0xa
+#define PIC_9XX_PENDING_3       0xc
+
+#define PIC_9XX_IRT0            0x1c0
+#define PIC_9XX_IRT(i)          (PIC_9XX_IRT0 + ((i) * 2))
+
+/*
+ *    IRT Map
+ */
+#define PIC_NUM_IRTS            160
+#define PIC_9XX_NUM_IRTS        256
+
+#define PIC_IRT_WD_0_INDEX      0
+#define PIC_IRT_WD_1_INDEX      1
+#define PIC_IRT_WD_NMI_0_INDEX  2
+#define PIC_IRT_WD_NMI_1_INDEX  3
+#define PIC_IRT_TIMER_0_INDEX   4
+#define PIC_IRT_TIMER_1_INDEX   5
+#define PIC_IRT_TIMER_2_INDEX   6
+#define PIC_IRT_TIMER_3_INDEX   7
+#define PIC_IRT_TIMER_4_INDEX   8
+#define PIC_IRT_TIMER_5_INDEX   9
+#define PIC_IRT_TIMER_6_INDEX   10
+#define PIC_IRT_TIMER_7_INDEX   11
+#define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
+
+
+/* 11 and 12 */
+#define PIC_NUM_MSG_Q_IRTS      32
+#define PIC_IRT_MSG_Q0_INDEX    12
+#define PIC_IRT_MSG_Q_INDEX(qid)        ((qid) + PIC_IRT_MSG_Q0_INDEX)
+/* 12 to 43 */
+#define PIC_IRT_MSG_0_INDEX     44
+#define PIC_IRT_MSG_1_INDEX     45
+/* 44 and 45 */
+#define PIC_NUM_PCIE_MSIX_IRTS  32
+#define PIC_IRT_PCIE_MSIX_0_INDEX       46
+#define PIC_IRT_PCIE_MSIX_INDEX(num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
+/* 46 to 77 */
+#define PIC_NUM_PCIE_LINK_IRTS          4
+#define PIC_IRT_PCIE_LINK_0_INDEX       78
+#define PIC_IRT_PCIE_LINK_1_INDEX       79
+#define PIC_IRT_PCIE_LINK_2_INDEX       80
+#define PIC_IRT_PCIE_LINK_3_INDEX       81
+#define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
+
+#define PIC_9XX_IRT_PCIE_LINK_0_INDEX   191
+#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
+                                ((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
+
+#define PIC_CLOCK_TIMER                 7
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+/*
+ *   Misc
+ */
+#define PIC_IRT_VALID                   1
+#define PIC_LOCAL_SCHEDULING            1
+#define PIC_GLOBAL_SCHEDULING           0
+
+#define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
+#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
+#define nlm_get_pic_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+/* We use PIC on node 0 as a timer */
+#define pic_timer_freq()                nlm_get_pic_frequency(0)
+
+/* IRT and h/w interrupt routines */
+static inline void
+nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int cpu)
+{
+        uint64_t val;
+
+        val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
+                        ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
+                        ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
+                        (cpu & 0x3ff);
+
+        nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
+}
+
+static inline void
+nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int dte)
+{
+        uint64_t val;
+
+        val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
+                        ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
+                        ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
+                        (dte & 0xffff);
+
+        nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
+}
+
+static inline void
+nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int cpu)
+{
+        if (cpu_is_xlp9xx())
+                nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
+                                                        1, 0, cpu);
+        else
+                nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                        (cpu >> 4),             /* thread group */
+                        1 << (cpu & 0xf));      /* thread mask */
+}
+
+static inline uint64_t
+nlm_pic_read_timer(uint64_t base, int timer)
+{
+        return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
+}
+
+static inline uint32_t
+nlm_pic_read_timer32(uint64_t base, int timer)
+{
+        return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
+}
+
+static inline void
+nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
+{
+        nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
+}
+
+static inline void
+nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
+{
+        uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
+        int en;
+
+        en = (irq > 0);
+        nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
+        nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
+                en, 0, 0, irq, cpu);
+
+        /* enable the timer */
+        pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
+        nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
+}
+
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
+{
+        uint64_t reg;
+
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        }
+}
+
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
+{
+        uint64_t reg;
+
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                reg &= ~((uint64_t)1 << 22);
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                reg &= ~((uint64_t)1 << 31);
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg);
+        }
+}
+
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        uint64_t ipi;
+
+        if (cpu_is_xlp9xx())
+                ipi = (nmi << 23) | (irq << 24) |
+                        (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
+        else
+                ipi = ((uint64_t)nmi << 31) | (irq << 20) |
+                        ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
+
+        nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt_num)
+{
+        nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
+
+        /* Ack the Status register for Watchdog & System timers */
+        if (irt_num < 12)
+                nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
+}
+
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
+{
+        nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
+}
+
+int nlm_irq_to_irt(int irq);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 000000000..6bcf3952e
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_SYS_H__
+#define __NLM_HAL_SYS_H__
+
+/**
+* @file_name sys.h
+* @author Netlogic Microsystems
+* @brief HAL for System configuration registers
+*/
+#define SYS_CHIP_RESET                          0x00
+#define SYS_POWER_ON_RESET_CFG                  0x01
+#define SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
+#define SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
+#define SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
+#define SYS_EFUSE_DEVICE_CFG3                   0x05
+#define SYS_EFUSE_DEVICE_CFG4                   0x06
+#define SYS_EFUSE_DEVICE_CFG5                   0x07
+#define SYS_EFUSE_DEVICE_CFG6                   0x08
+#define SYS_EFUSE_DEVICE_CFG7                   0x09
+#define SYS_PLL_CTRL                            0x0a
+#define SYS_CPU_RESET                           0x0b
+#define SYS_CPU_NONCOHERENT_MODE                0x0d
+#define SYS_CORE_DFS_DIS_CTRL                   0x0e
+#define SYS_CORE_DFS_RST_CTRL                   0x0f
+#define SYS_CORE_DFS_BYP_CTRL                   0x10
+#define SYS_CORE_DFS_PHA_CTRL                   0x11
+#define SYS_CORE_DFS_DIV_INC_CTRL               0x12
+#define SYS_CORE_DFS_DIV_DEC_CTRL               0x13
+#define SYS_CORE_DFS_DIV_VALUE                  0x14
+#define SYS_RESET                               0x15
+#define SYS_DFS_DIS_CTRL                        0x16
+#define SYS_DFS_RST_CTRL                        0x17
+#define SYS_DFS_BYP_CTRL                        0x18
+#define SYS_DFS_DIV_INC_CTRL                    0x19
+#define SYS_DFS_DIV_DEC_CTRL                    0x1a
+#define SYS_DFS_DIV_VALUE0                      0x1b
+#define SYS_DFS_DIV_VALUE1                      0x1c
+#define SYS_SENSE_AMP_DLY                       0x1d
+#define SYS_SOC_SENSE_AMP_DLY                   0x1e
+#define SYS_CTRL0                               0x1f
+#define SYS_CTRL1                               0x20
+#define SYS_TIMEOUT_BS1                         0x21
+#define SYS_BYTE_SWAP                           0x22
+#define SYS_VRM_VID                             0x23
+#define SYS_PWR_RAM_CMD                         0x24
+#define SYS_PWR_RAM_ADDR                        0x25
+#define SYS_PWR_RAM_DATA0                       0x26
+#define SYS_PWR_RAM_DATA1                       0x27
+#define SYS_PWR_RAM_DATA2                       0x28
+#define SYS_PWR_UCODE                           0x29
+#define SYS_CPU0_PWR_STATUS                     0x2a
+#define SYS_CPU1_PWR_STATUS                     0x2b
+#define SYS_CPU2_PWR_STATUS                     0x2c
+#define SYS_CPU3_PWR_STATUS                     0x2d
+#define SYS_CPU4_PWR_STATUS                     0x2e
+#define SYS_CPU5_PWR_STATUS                     0x2f
+#define SYS_CPU6_PWR_STATUS                     0x30
+#define SYS_CPU7_PWR_STATUS                     0x31
+#define SYS_STATUS                              0x32
+#define SYS_INT_POL                             0x33
+#define SYS_INT_TYPE                            0x34
+#define SYS_INT_STATUS                          0x35
+#define SYS_INT_MASK0                           0x36
+#define SYS_INT_MASK1                           0x37
+#define SYS_UCO_S_ECC                           0x38
+#define SYS_UCO_M_ECC                           0x39
+#define SYS_UCO_ADDR                            0x3a
+#define SYS_UCO_INSTR                           0x3b
+#define SYS_MEM_BIST0                           0x3c
+#define SYS_MEM_BIST1                           0x3d
+#define SYS_MEM_BIST2                           0x3e
+#define SYS_MEM_BIST3                           0x3f
+#define SYS_MEM_BIST4                           0x40
+#define SYS_MEM_BIST5                           0x41
+#define SYS_MEM_BIST6                           0x42
+#define SYS_MEM_BIST7                           0x43
+#define SYS_MEM_BIST8                           0x44
+#define SYS_MEM_BIST9                           0x45
+#define SYS_MEM_BIST10                          0x46
+#define SYS_MEM_BIST11                          0x47
+#define SYS_MEM_BIST12                          0x48
+#define SYS_SCRTCH0                             0x49
+#define SYS_SCRTCH1                             0x4a
+#define SYS_SCRTCH2                             0x4b
+#define SYS_SCRTCH3                             0x4c
+
+/* PLL registers XLP2XX */
+#define SYS_CPU_PLL_CTRL0(core)                 (0x1c0 + (core * 4))
+#define SYS_CPU_PLL_CTRL1(core)                 (0x1c1 + (core * 4))
+#define SYS_CPU_PLL_CTRL2(core)                 (0x1c2 + (core * 4))
+#define SYS_CPU_PLL_CTRL3(core)                 (0x1c3 + (core * 4))
+#define SYS_PLL_CTRL0                           0x240
+#define SYS_PLL_CTRL1                           0x241
+#define SYS_PLL_CTRL2                           0x242
+#define SYS_PLL_CTRL3                           0x243
+#define SYS_DMC_PLL_CTRL0                       0x244
+#define SYS_DMC_PLL_CTRL1                       0x245
+#define SYS_DMC_PLL_CTRL2                       0x246
+#define SYS_DMC_PLL_CTRL3                       0x247
+
+#define SYS_PLL_CTRL0_DEVX(x)                   (0x248 + (x) * 4)
+#define SYS_PLL_CTRL1_DEVX(x)                   (0x249 + (x) * 4)
+#define SYS_PLL_CTRL2_DEVX(x)                   (0x24a + (x) * 4)
+#define SYS_PLL_CTRL3_DEVX(x)                   (0x24b + (x) * 4)
+
+#define SYS_CPU_PLL_CHG_CTRL                    0x288
+#define SYS_PLL_CHG_CTRL                        0x289
+#define SYS_CLK_DEV_DIS                         0x28a
+#define SYS_CLK_DEV_SEL                         0x28b
+#define SYS_CLK_DEV_DIV                         0x28c
+#define SYS_CLK_DEV_CHG                         0x28d
+#define SYS_CLK_DEV_SEL_REG                     0x28e
+#define SYS_CLK_DEV_DIV_REG                     0x28f
+#define SYS_CPU_PLL_LOCK                        0x29f
+#define SYS_SYS_PLL_LOCK                        0x2a0
+#define SYS_PLL_MEM_CMD                         0x2a1
+#define SYS_CPU_PLL_MEM_REQ                     0x2a2
+#define SYS_SYS_PLL_MEM_REQ                     0x2a3
+#define SYS_PLL_MEM_STAT                        0x2a4
+
+/* PLL registers XLP9XX */
+#define SYS_9XX_CPU_PLL_CTRL0(core)             (0xc0 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL1(core)             (0xc1 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL2(core)             (0xc2 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL3(core)             (0xc3 + (core * 4))
+#define SYS_9XX_DMC_PLL_CTRL0                   0x140
+#define SYS_9XX_DMC_PLL_CTRL1                   0x141
+#define SYS_9XX_DMC_PLL_CTRL2                   0x142
+#define SYS_9XX_DMC_PLL_CTRL3                   0x143
+#define SYS_9XX_PLL_CTRL0                       0x144
+#define SYS_9XX_PLL_CTRL1                       0x145
+#define SYS_9XX_PLL_CTRL2                       0x146
+#define SYS_9XX_PLL_CTRL3                       0x147
+
+#define SYS_9XX_PLL_CTRL0_DEVX(x)               (0x148 + (x) * 4)
+#define SYS_9XX_PLL_CTRL1_DEVX(x)               (0x149 + (x) * 4)
+#define SYS_9XX_PLL_CTRL2_DEVX(x)               (0x14a + (x) * 4)
+#define SYS_9XX_PLL_CTRL3_DEVX(x)               (0x14b + (x) * 4)
+
+#define SYS_9XX_CPU_PLL_CHG_CTRL                0x188
+#define SYS_9XX_PLL_CHG_CTRL                    0x189
+#define SYS_9XX_CLK_DEV_DIS                     0x18a
+#define SYS_9XX_CLK_DEV_SEL                     0x18b
+#define SYS_9XX_CLK_DEV_DIV                     0x18d
+#define SYS_9XX_CLK_DEV_CHG                     0x18f
+
+#define SYS_9XX_CLK_DEV_SEL_REG                 0x1a4
+#define SYS_9XX_CLK_DEV_DIV_REG                 0x1a6
+
+/* Registers changed on 9XX */
+#define SYS_9XX_POWER_ON_RESET_CFG              0x00
+#define SYS_9XX_CHIP_RESET                      0x01
+#define SYS_9XX_CPU_RESET                       0x02
+#define SYS_9XX_CPU_NONCOHERENT_MODE            0x03
+
+/* XLP 9XX fuse block registers */
+#define FUSE_9XX_DEVCFG6                        0xc6
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
+#define nlm_get_sys_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+/* XLP9XX fuse block */
+#define nlm_get_fuse_pcibase(node)      \
+                        nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
+#define nlm_get_fuse_regbase(node)      \
+                        (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#define nlm_get_clock_pcibase(node)     \
+                        nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
+#define nlm_get_clock_regbase(node)     \
+                        (nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+unsigned int nlm_get_pic_frequency(int node);
+#endif
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 000000000..a6c54424d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLP_HAL_UART_H__
+#define __XLP_HAL_UART_H__
+
+/* UART Specific registers */
+#define UART_RX_DATA            0x00
+#define UART_TX_DATA            0x00
+
+#define UART_INT_EN             0x01
+#define UART_INT_ID             0x02
+#define UART_FIFO_CTL           0x02
+#define UART_LINE_CTL           0x03
+#define UART_MODEM_CTL          0x04
+#define UART_LINE_STS           0x05
+#define UART_MODEM_STS          0x06
+
+#define UART_DIVISOR0           0x00
+#define UART_DIVISOR1           0x01
+
+#define BASE_BAUD               (XLP_IO_CLK/16)
+#define BAUD_DIVISOR(baud)      (BASE_BAUD / baud)
+
+/* LCR mask values */
+#define LCR_5BITS               0x00
+#define LCR_6BITS               0x01
+#define LCR_7BITS               0x02
+#define LCR_8BITS               0x03
+#define LCR_STOPB               0x04
+#define LCR_PENAB               0x08
+#define LCR_PODD                0x00
+#define LCR_PEVEN               0x10
+#define LCR_PONE                0x20
+#define LCR_PZERO               0x30
+#define LCR_SBREAK              0x40
+#define LCR_EFR_ENABLE          0xbf
+#define LCR_DLAB                0x80
+
+/* MCR mask values */
+#define MCR_DTR                 0x01
+#define MCR_RTS                 0x02
+#define MCR_DRS                 0x04
+#define MCR_IE                  0x08
+#define MCR_LOOPBACK            0x10
+
+/* FCR mask values */
+#define FCR_RCV_RST             0x02
+#define FCR_XMT_RST             0x04
+#define FCR_RX_LOW              0x00
+#define FCR_RX_MEDL             0x40
+#define FCR_RX_MEDH             0x80
+#define FCR_RX_HIGH             0xc0
+
+/* IER mask values */
+#define IER_ERXRDY              0x1
+#define IER_ETXRDY              0x2
+#define IER_ERLS                0x4
+#define IER_EMSC                0x8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_uart_pcibase(node, inst)        \
+        nlm_pcicfg_base(cpu_is_xlp9xx() ?  XLP9XX_IO_UART_OFFSET(node) : \
+                                                XLP_IO_UART_OFFSET(node, inst))
+#define nlm_get_uart_regbase(node, inst)        \
+                        (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+static inline void
+nlm_uart_set_baudrate(uint64_t base, int baud)
+{
+        uint32_t lcr;
+
+        lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
+
+        /* enable divisor register, and write baud values */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
+        nlm_write_uart_reg(base, UART_DIVISOR0,
+                        (BAUD_DIVISOR(baud) & 0xff));
+        nlm_write_uart_reg(base, UART_DIVISOR1,
+                        ((BAUD_DIVISOR(baud) >> 8) & 0xff));
+
+        /* restore default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+}
+
+static inline void
+nlm_uart_outbyte(uint64_t base, char c)
+{
+        uint32_t lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x20)
+                        break;
+        }
+
+        nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
+}
+
+static inline char
+nlm_uart_inbyte(uint64_t base)
+{
+        int data, lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
+                        data = 0;
+                        break;
+                }
+                if (lsr & 0x01) {       /* Rx data */
+                        data = nlm_read_uart_reg(base, UART_RX_DATA);
+                        break;
+                }
+        }
+
+        return (char)data;
+}
+
+static inline int
+nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
+        int parity, int int_en, int loopback)
+{
+        uint32_t lcr;
+
+        lcr = 0;
+        if (databits >= 8)
+                lcr |= LCR_8BITS;
+        else if (databits == 7)
+                lcr |= LCR_7BITS;
+        else if (databits == 6)
+                lcr |= LCR_6BITS;
+        else
+                lcr |= LCR_5BITS;
+
+        if (stopbits > 1)
+                lcr |= LCR_STOPB;
+
+        lcr |= parity << 3;
+
+        /* setup default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+
+        /* Reset the FIFOs */
+        nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
+
+        nlm_uart_set_baudrate(base, baud);
+
+        if (loopback)
+                nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
+
+        if (int_en)
+                nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
+
+        return 0;
+}
+#endif /* !LOCORE && !__ASSEMBLY__ */
+#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
new file mode 100644
index 000000000..feb6ed807
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NLM_HAL_XLP_H
+#define _NLM_HAL_XLP_H
+
+#define PIC_UART_0_IRQ                  17
+#define PIC_UART_1_IRQ                  18
+
+#define PIC_PCIE_LINK_LEGACY_IRQ_BASE   19
+#define PIC_PCIE_LINK_LEGACY_IRQ(i)     (19 + (i))
+
+#define PIC_EHCI_0_IRQ                  23
+#define PIC_EHCI_1_IRQ                  24
+#define PIC_OHCI_0_IRQ                  25
+#define PIC_OHCI_1_IRQ                  26
+#define PIC_OHCI_2_IRQ                  27
+#define PIC_OHCI_3_IRQ                  28
+#define PIC_2XX_XHCI_0_IRQ              23
+#define PIC_2XX_XHCI_1_IRQ              24
+#define PIC_2XX_XHCI_2_IRQ              25
+#define PIC_9XX_XHCI_0_IRQ              23
+#define PIC_9XX_XHCI_1_IRQ              24
+#define PIC_9XX_XHCI_2_IRQ              25
+
+#define PIC_MMC_IRQ                     29
+#define PIC_I2C_0_IRQ                   30
+#define PIC_I2C_1_IRQ                   31
+#define PIC_I2C_2_IRQ                   32
+#define PIC_I2C_3_IRQ                   33
+#define PIC_SPI_IRQ                     34
+#define PIC_NAND_IRQ                    37
+#define PIC_SATA_IRQ                    38
+#define PIC_GPIO_IRQ                    39
+
+#define PIC_PCIE_LINK_MSI_IRQ_BASE      44      /* 44 - 47 MSI IRQ */
+#define PIC_PCIE_LINK_MSI_IRQ(i)        (44 + (i))
+
+/* MSI-X with second link-level dispatch */
+#define PIC_PCIE_MSIX_IRQ_BASE          48      /* 48 - 51 MSI-X IRQ */
+#define PIC_PCIE_MSIX_IRQ(i)            (48 + (i))
+
+/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
+#define NLM_MSIX_VEC_BASE               96      /* 96 - 223 - MSIX mapped */
+#define NLM_MSI_VEC_BASE                224     /* 224 -351 - MSI mapped */
+
+#define NLM_PIC_INDIRECT_VEC_BASE       512
+#define NLM_GPIO_VEC_BASE               768
+
+#define PIC_IRQ_BASE                    8
+#define PIC_IRT_FIRST_IRQ               PIC_IRQ_BASE
+#define PIC_IRT_LAST_IRQ                63
+
+#ifndef __ASSEMBLY__
+
+/* SMP support functions */
+void xlp_boot_core0_siblings(void);
+void xlp_wakeup_secondary_cpus(void);
+
+void xlp_mmu_init(void);
+void nlm_hal_init(void);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
+
+struct pci_dev;
+int xlp_socdev_to_node(const struct pci_dev *dev);
+
+/* Device tree related */
+void xlp_early_init_devtree(void);
+void *xlp_dt_init(void *fdtp);
+
+static inline int cpu_is_xlpii(void)
+{
+        int chip = read_c0_prid() & PRID_IMP_MASK;
+
+        return chip == PRID_IMP_NETLOGIC_XLP2XX ||
+                chip == PRID_IMP_NETLOGIC_XLP9XX ||
+                chip == PRID_IMP_NETLOGIC_XLP5XX;
+}
+
+static inline int cpu_is_xlp9xx(void)
+{
+        int chip = read_c0_prid() & PRID_IMP_MASK;
+
+        return chip == PRID_IMP_NETLOGIC_XLP9XX ||
+                chip == PRID_IMP_NETLOGIC_XLP5XX;
+}
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
new file mode 100644
index 000000000..2d02428c4
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/bridge.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_BRIDGE_H_
+#define _ASM_NLM_BRIDGE_H_
+
+#define BRIDGE_DRAM_0_BAR               0
+#define BRIDGE_DRAM_1_BAR               1
+#define BRIDGE_DRAM_2_BAR               2
+#define BRIDGE_DRAM_3_BAR               3
+#define BRIDGE_DRAM_4_BAR               4
+#define BRIDGE_DRAM_5_BAR               5
+#define BRIDGE_DRAM_6_BAR               6
+#define BRIDGE_DRAM_7_BAR               7
+#define BRIDGE_DRAM_CHN_0_MTR_0_BAR     8
+#define BRIDGE_DRAM_CHN_0_MTR_1_BAR     9
+#define BRIDGE_DRAM_CHN_0_MTR_2_BAR     10
+#define BRIDGE_DRAM_CHN_0_MTR_3_BAR     11
+#define BRIDGE_DRAM_CHN_0_MTR_4_BAR     12
+#define BRIDGE_DRAM_CHN_0_MTR_5_BAR     13
+#define BRIDGE_DRAM_CHN_0_MTR_6_BAR     14
+#define BRIDGE_DRAM_CHN_0_MTR_7_BAR     15
+#define BRIDGE_DRAM_CHN_1_MTR_0_BAR     16
+#define BRIDGE_DRAM_CHN_1_MTR_1_BAR     17
+#define BRIDGE_DRAM_CHN_1_MTR_2_BAR     18
+#define BRIDGE_DRAM_CHN_1_MTR_3_BAR     19
+#define BRIDGE_DRAM_CHN_1_MTR_4_BAR     20
+#define BRIDGE_DRAM_CHN_1_MTR_5_BAR     21
+#define BRIDGE_DRAM_CHN_1_MTR_6_BAR     22
+#define BRIDGE_DRAM_CHN_1_MTR_7_BAR     23
+#define BRIDGE_CFG_BAR                  24
+#define BRIDGE_PHNX_IO_BAR              25
+#define BRIDGE_FLASH_BAR                26
+#define BRIDGE_SRAM_BAR                 27
+#define BRIDGE_HTMEM_BAR                28
+#define BRIDGE_HTINT_BAR                29
+#define BRIDGE_HTPIC_BAR                30
+#define BRIDGE_HTSM_BAR                 31
+#define BRIDGE_HTIO_BAR                 32
+#define BRIDGE_HTCFG_BAR                33
+#define BRIDGE_PCIXCFG_BAR              34
+#define BRIDGE_PCIXMEM_BAR              35
+#define BRIDGE_PCIXIO_BAR               36
+#define BRIDGE_DEVICE_MASK              37
+#define BRIDGE_AERR_INTR_LOG1           38
+#define BRIDGE_AERR_INTR_LOG2           39
+#define BRIDGE_AERR_INTR_LOG3           40
+#define BRIDGE_AERR_DEV_STAT            41
+#define BRIDGE_AERR1_LOG1               42
+#define BRIDGE_AERR1_LOG2               43
+#define BRIDGE_AERR1_LOG3               44
+#define BRIDGE_AERR1_DEV_STAT           45
+#define BRIDGE_AERR_INTR_EN             46
+#define BRIDGE_AERR_UPG                 47
+#define BRIDGE_AERR_CLEAR               48
+#define BRIDGE_AERR1_CLEAR              49
+#define BRIDGE_SBE_COUNTS               50
+#define BRIDGE_DBE_COUNTS               51
+#define BRIDGE_BITERR_INT_EN            52
+
+#define BRIDGE_SYS2IO_CREDITS           53
+#define BRIDGE_EVNT_CNT_CTRL1           54
+#define BRIDGE_EVNT_COUNTER1            55
+#define BRIDGE_EVNT_CNT_CTRL2           56
+#define BRIDGE_EVNT_COUNTER2            57
+#define BRIDGE_RESERVED1                58
+
+#define BRIDGE_DEFEATURE                59
+#define BRIDGE_SCRATCH0                 60
+#define BRIDGE_SCRATCH1                 61
+#define BRIDGE_SCRATCH2                 62
+#define BRIDGE_SCRATCH3                 63
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
new file mode 100644
index 000000000..f8aca5472
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/flash.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_FLASH_H_
+#define _ASM_NLM_FLASH_H_
+
+#define FLASH_CSBASE_ADDR(cs)           (cs)
+#define FLASH_CSADDR_MASK(cs)           (0x10 + (cs))
+#define FLASH_CSDEV_PARM(cs)            (0x20 + (cs))
+#define FLASH_CSTIME_PARMA(cs)          (0x30 + (cs))
+#define FLASH_CSTIME_PARMB(cs)          (0x40 + (cs))
+
+#define FLASH_INT_MASK                  0x50
+#define FLASH_INT_STATUS                0x60
+#define FLASH_ERROR_STATUS              0x70
+#define FLASH_ERROR_ADDR                0x80
+
+#define FLASH_NAND_CLE(cs)              (0x90 + (cs))
+#define FLASH_NAND_ALE(cs)              (0xa0 + (cs))
+
+#define FLASH_NAND_CSDEV_PARAM          0x000041e6
+#define FLASH_NAND_CSTIME_PARAMA        0x4f400e22
+#define FLASH_NAND_CSTIME_PARAMB        0x000083cf
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
new file mode 100644
index 000000000..d79c68fa7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NLM_FMN_H_
+#define _NLM_FMN_H_
+
+#include <asm/netlogic/mips-extns.h> /* for COP2 access */
+
+/* Station IDs */
+#define FMN_STNID_CPU0                  0x00
+#define FMN_STNID_CPU1                  0x08
+#define FMN_STNID_CPU2                  0x10
+#define FMN_STNID_CPU3                  0x18
+#define FMN_STNID_CPU4                  0x20
+#define FMN_STNID_CPU5                  0x28
+#define FMN_STNID_CPU6                  0x30
+#define FMN_STNID_CPU7                  0x38
+
+#define FMN_STNID_XGS0_TX               64
+#define FMN_STNID_XMAC0_00_TX           64
+#define FMN_STNID_XMAC0_01_TX           65
+#define FMN_STNID_XMAC0_02_TX           66
+#define FMN_STNID_XMAC0_03_TX           67
+#define FMN_STNID_XMAC0_04_TX           68
+#define FMN_STNID_XMAC0_05_TX           69
+#define FMN_STNID_XMAC0_06_TX           70
+#define FMN_STNID_XMAC0_07_TX           71
+#define FMN_STNID_XMAC0_08_TX           72
+#define FMN_STNID_XMAC0_09_TX           73
+#define FMN_STNID_XMAC0_10_TX           74
+#define FMN_STNID_XMAC0_11_TX           75
+#define FMN_STNID_XMAC0_12_TX           76
+#define FMN_STNID_XMAC0_13_TX           77
+#define FMN_STNID_XMAC0_14_TX           78
+#define FMN_STNID_XMAC0_15_TX           79
+
+#define FMN_STNID_XGS1_TX               80
+#define FMN_STNID_XMAC1_00_TX           80
+#define FMN_STNID_XMAC1_01_TX           81
+#define FMN_STNID_XMAC1_02_TX           82
+#define FMN_STNID_XMAC1_03_TX           83
+#define FMN_STNID_XMAC1_04_TX           84
+#define FMN_STNID_XMAC1_05_TX           85
+#define FMN_STNID_XMAC1_06_TX           86
+#define FMN_STNID_XMAC1_07_TX           87
+#define FMN_STNID_XMAC1_08_TX           88
+#define FMN_STNID_XMAC1_09_TX           89
+#define FMN_STNID_XMAC1_10_TX           90
+#define FMN_STNID_XMAC1_11_TX           91
+#define FMN_STNID_XMAC1_12_TX           92
+#define FMN_STNID_XMAC1_13_TX           93
+#define FMN_STNID_XMAC1_14_TX           94
+#define FMN_STNID_XMAC1_15_TX           95
+
+#define FMN_STNID_GMAC                  96
+#define FMN_STNID_GMACJFR_0             96
+#define FMN_STNID_GMACRFR_0             97
+#define FMN_STNID_GMACTX0               98
+#define FMN_STNID_GMACTX1               99
+#define FMN_STNID_GMACTX2               100
+#define FMN_STNID_GMACTX3               101
+#define FMN_STNID_GMACJFR_1             102
+#define FMN_STNID_GMACRFR_1             103
+
+#define FMN_STNID_DMA                   104
+#define FMN_STNID_DMA_0                 104
+#define FMN_STNID_DMA_1                 105
+#define FMN_STNID_DMA_2                 106
+#define FMN_STNID_DMA_3                 107
+
+#define FMN_STNID_XGS0FR                112
+#define FMN_STNID_XMAC0JFR              112
+#define FMN_STNID_XMAC0RFR              113
+
+#define FMN_STNID_XGS1FR                114
+#define FMN_STNID_XMAC1JFR              114
+#define FMN_STNID_XMAC1RFR              115
+#define FMN_STNID_SEC                   120
+#define FMN_STNID_SEC0                  120
+#define FMN_STNID_SEC1                  121
+#define FMN_STNID_SEC2                  122
+#define FMN_STNID_SEC3                  123
+#define FMN_STNID_PK0                   124
+#define FMN_STNID_SEC_RSA               124
+#define FMN_STNID_SEC_RSVD0             125
+#define FMN_STNID_SEC_RSVD1             126
+#define FMN_STNID_SEC_RSVD2             127
+
+#define FMN_STNID_GMAC1                 80
+#define FMN_STNID_GMAC1_FR_0            81
+#define FMN_STNID_GMAC1_TX0             82
+#define FMN_STNID_GMAC1_TX1             83
+#define FMN_STNID_GMAC1_TX2             84
+#define FMN_STNID_GMAC1_TX3             85
+#define FMN_STNID_GMAC1_FR_1            87
+#define FMN_STNID_GMAC0                 96
+#define FMN_STNID_GMAC0_FR_0            97
+#define FMN_STNID_GMAC0_TX0             98
+#define FMN_STNID_GMAC0_TX1             99
+#define FMN_STNID_GMAC0_TX2             100
+#define FMN_STNID_GMAC0_TX3             101
+#define FMN_STNID_GMAC0_FR_1            103
+#define FMN_STNID_CMP_0                 108
+#define FMN_STNID_CMP_1                 109
+#define FMN_STNID_CMP_2                 110
+#define FMN_STNID_CMP_3                 111
+#define FMN_STNID_PCIE_0                116
+#define FMN_STNID_PCIE_1                117
+#define FMN_STNID_PCIE_2                118
+#define FMN_STNID_PCIE_3                119
+#define FMN_STNID_XLS_PK0               121
+
+#define nlm_read_c2_cc0(s)              __read_32bit_c2_register($16, s)
+#define nlm_read_c2_cc1(s)              __read_32bit_c2_register($17, s)
+#define nlm_read_c2_cc2(s)              __read_32bit_c2_register($18, s)
+#define nlm_read_c2_cc3(s)              __read_32bit_c2_register($19, s)
+#define nlm_read_c2_cc4(s)              __read_32bit_c2_register($20, s)
+#define nlm_read_c2_cc5(s)              __read_32bit_c2_register($21, s)
+#define nlm_read_c2_cc6(s)              __read_32bit_c2_register($22, s)
+#define nlm_read_c2_cc7(s)              __read_32bit_c2_register($23, s)
+#define nlm_read_c2_cc8(s)              __read_32bit_c2_register($24, s)
+#define nlm_read_c2_cc9(s)              __read_32bit_c2_register($25, s)
+#define nlm_read_c2_cc10(s)             __read_32bit_c2_register($26, s)
+#define nlm_read_c2_cc11(s)             __read_32bit_c2_register($27, s)
+#define nlm_read_c2_cc12(s)             __read_32bit_c2_register($28, s)
+#define nlm_read_c2_cc13(s)             __read_32bit_c2_register($29, s)
+#define nlm_read_c2_cc14(s)             __read_32bit_c2_register($30, s)
+#define nlm_read_c2_cc15(s)             __read_32bit_c2_register($31, s)
+
+#define nlm_write_c2_cc0(s, v)          __write_32bit_c2_register($16, s, v)
+#define nlm_write_c2_cc1(s, v)          __write_32bit_c2_register($17, s, v)
+#define nlm_write_c2_cc2(s, v)          __write_32bit_c2_register($18, s, v)
+#define nlm_write_c2_cc3(s, v)          __write_32bit_c2_register($19, s, v)
+#define nlm_write_c2_cc4(s, v)          __write_32bit_c2_register($20, s, v)
+#define nlm_write_c2_cc5(s, v)          __write_32bit_c2_register($21, s, v)
+#define nlm_write_c2_cc6(s, v)          __write_32bit_c2_register($22, s, v)
+#define nlm_write_c2_cc7(s, v)          __write_32bit_c2_register($23, s, v)
+#define nlm_write_c2_cc8(s, v)          __write_32bit_c2_register($24, s, v)
+#define nlm_write_c2_cc9(s, v)          __write_32bit_c2_register($25, s, v)
+#define nlm_write_c2_cc10(s, v)         __write_32bit_c2_register($26, s, v)
+#define nlm_write_c2_cc11(s, v)         __write_32bit_c2_register($27, s, v)
+#define nlm_write_c2_cc12(s, v)         __write_32bit_c2_register($28, s, v)
+#define nlm_write_c2_cc13(s, v)         __write_32bit_c2_register($29, s, v)
+#define nlm_write_c2_cc14(s, v)         __write_32bit_c2_register($30, s, v)
+#define nlm_write_c2_cc15(s, v)         __write_32bit_c2_register($31, s, v)
+
+#define nlm_read_c2_status0()           __read_32bit_c2_register($2, 0)
+#define nlm_write_c2_status0(v)         __write_32bit_c2_register($2, 0, v)
+#define nlm_read_c2_status1()           __read_32bit_c2_register($2, 1)
+#define nlm_write_c2_status1(v)         __write_32bit_c2_register($2, 1, v)
+#define nlm_read_c2_status(sel)         __read_32bit_c2_register($2, 0)
+#define nlm_read_c2_config()            __read_32bit_c2_register($3, 0)
+#define nlm_write_c2_config(v)          __write_32bit_c2_register($3, 0, v)
+#define nlm_read_c2_bucksize(b)         __read_32bit_c2_register($4, b)
+#define nlm_write_c2_bucksize(b, v)     __write_32bit_c2_register($4, b, v)
+
+#define nlm_read_c2_rx_msg0()           __read_64bit_c2_register($1, 0)
+#define nlm_read_c2_rx_msg1()           __read_64bit_c2_register($1, 1)
+#define nlm_read_c2_rx_msg2()           __read_64bit_c2_register($1, 2)
+#define nlm_read_c2_rx_msg3()           __read_64bit_c2_register($1, 3)
+
+#define nlm_write_c2_tx_msg0(v)         __write_64bit_c2_register($0, 0, v)
+#define nlm_write_c2_tx_msg1(v)         __write_64bit_c2_register($0, 1, v)
+#define nlm_write_c2_tx_msg2(v)         __write_64bit_c2_register($0, 2, v)
+#define nlm_write_c2_tx_msg3(v)         __write_64bit_c2_register($0, 3, v)
+
+#define FMN_STN_RX_QSIZE                256
+#define FMN_NSTATIONS                   128
+#define FMN_CORE_NBUCKETS               8
+
+static inline void nlm_msgsnd(unsigned int stid)
+{
+        __asm__ volatile (
+            ".set       push\n"
+            ".set       noreorder\n"
+            ".set       noat\n"
+            "move       $1, %0\n"
+            "c2         0x10001\n"      /* msgsnd $1 */
+            ".set       pop\n"
+            : : "r" (stid) : "$1"
+        );
+}
+
+static inline void nlm_msgld(unsigned int pri)
+{
+        __asm__ volatile (
+            ".set       push\n"
+            ".set       noreorder\n"
+            ".set       noat\n"
+            "move       $1, %0\n"
+            "c2         0x10002\n"    /* msgld $1 */
+            ".set       pop\n"
+            : : "r" (pri) : "$1"
+        );
+}
+
+static inline void nlm_msgwait(unsigned int mask)
+{
+        __asm__ volatile (
+            ".set       push\n"
+            ".set       noreorder\n"
+            ".set       noat\n"
+            "move       $8, %0\n"
+            "c2         0x10003\n"    /* msgwait $1 */
+            ".set       pop\n"
+            : : "r" (mask) : "$1"
+        );
+}
+
+/*
+ * Disable interrupts and enable COP2 access
+ */
+static inline uint32_t nlm_cop2_enable_irqsave(void)
+{
+        uint32_t sr = read_c0_status();
+
+        write_c0_status((sr & ~ST0_IE) | ST0_CU2);
+        return sr;
+}
+
+static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
+{
+        write_c0_status(sr);
+}
+
+static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
+{
+        uint32_t config;
+
+        config = (1 << 24)      /* interrupt water mark - 1 msg */
+                | (irq << 16)   /* irq */
+                | (tmask << 8)  /* thread mask */
+                | 0x2;          /* enable watermark intr, disable empty intr */
+        nlm_write_c2_config(config);
+}
+
+struct nlm_fmn_msg {
+        uint64_t msg0;
+        uint64_t msg1;
+        uint64_t msg2;
+        uint64_t msg3;
+};
+
+static inline int nlm_fmn_send(unsigned int size, unsigned int code,
+                unsigned int stid, struct nlm_fmn_msg *msg)
+{
+        unsigned int dest;
+        uint32_t status;
+        int i;
+
+        /*
+         * Make sure that all the writes pending at the cpu are flushed.
+         * Any writes pending on CPU will not be see by devices. L1/L2
+         * caches are coherent with IO, so no cache flush needed.
+         */
+        __asm __volatile("sync");
+
+        /* Load TX message buffers */
+        nlm_write_c2_tx_msg0(msg->msg0);
+        nlm_write_c2_tx_msg1(msg->msg1);
+        nlm_write_c2_tx_msg2(msg->msg2);
+        nlm_write_c2_tx_msg3(msg->msg3);
+        dest = ((size - 1) << 16) | (code << 8) | stid;
+
+        /*
+         * Retry a few times on credit fail, this should be a
+         * transient condition, unless there is a configuration
+         * failure, or the receiver is stuck.
+         */
+        for (i = 0; i < 8; i++) {
+                nlm_msgsnd(dest);
+                status = nlm_read_c2_status0();
+                if ((status & 0x4) == 0)
+                        return 0;
+        }
+
+        /* If there is a credit failure, return error */
+        return status & 0x06;
+}
+
+static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
+                struct nlm_fmn_msg *msg)
+{
+        uint32_t status, tmp;
+
+        nlm_msgld(bucket);
+
+        /* wait for load pending to clear */
+        do {
+                status = nlm_read_c2_status0();
+        } while ((status & 0x08) != 0);
+
+        /* receive error bits */
+        tmp = status & 0x30;
+        if (tmp != 0)
+                return tmp;
+
+        *size = ((status & 0xc0) >> 6) + 1;
+        *code = (status & 0xff00) >> 8;
+        *stid = (status & 0x7f0000) >> 16;
+        msg->msg0 = nlm_read_c2_rx_msg0();
+        msg->msg1 = nlm_read_c2_rx_msg1();
+        msg->msg2 = nlm_read_c2_rx_msg2();
+        msg->msg3 = nlm_read_c2_rx_msg3();
+
+        return 0;
+}
+
+struct xlr_fmn_info {
+        int num_buckets;
+        int start_stn_id;
+        int end_stn_id;
+        int credit_config[128];
+};
+
+struct xlr_board_fmn_config {
+        int bucket_size[128];           /* size of buckets for all stations */
+        struct xlr_fmn_info cpu[8];
+        struct xlr_fmn_info gmac[2];
+        struct xlr_fmn_info dma;
+        struct xlr_fmn_info cmp;
+        struct xlr_fmn_info sae;
+        struct xlr_fmn_info xgmac[2];
+};
+
+extern int nlm_register_fmn_handler(int start, int end,
+        void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
+        void *arg);
+extern void xlr_percpu_fmn_init(void);
+extern void nlm_setup_fmn_irq(void);
+extern void xlr_board_info_setup(void);
+
+extern struct xlr_board_fmn_config xlr_board_fmn_config;
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
new file mode 100644
index 000000000..8492e835b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_GPIO_H
+#define _ASM_NLM_GPIO_H
+
+#define GPIO_INT_EN_REG                 0
+#define GPIO_INPUT_INVERSION_REG        1
+#define GPIO_IO_DIR_REG                 2
+#define GPIO_IO_DATA_WR_REG             3
+#define GPIO_IO_DATA_RD_REG             4
+
+#define GPIO_SWRESET_REG                8
+#define GPIO_DRAM1_CNTRL_REG            9
+#define GPIO_DRAM1_RATIO_REG            10
+#define GPIO_DRAM1_RESET_REG            11
+#define GPIO_DRAM1_STATUS_REG           12
+#define GPIO_DRAM2_CNTRL_REG            13
+#define GPIO_DRAM2_RATIO_REG            14
+#define GPIO_DRAM2_RESET_REG            15
+#define GPIO_DRAM2_STATUS_REG           16
+
+#define GPIO_PWRON_RESET_CFG_REG        21
+#define GPIO_BIST_ALL_GO_STATUS_REG     24
+#define GPIO_BIST_CPU_GO_STATUS_REG     25
+#define GPIO_BIST_DEV_GO_STATUS_REG     26
+
+#define GPIO_FUSE_BANK_REG              35
+#define GPIO_CPU_RESET_REG              40
+#define GPIO_RNG_REG                    43
+
+#define PWRON_RESET_PCMCIA_BOOT         17
+
+#define GPIO_LED_BITMAP                 0x1700000
+#define GPIO_LED_0_SHIFT                20
+#define GPIO_LED_1_SHIFT                24
+
+#define GPIO_LED_OUTPUT_CODE_RESET      0x01
+#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
+#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
+#define GPIO_LED_OUTPUT_CODE_MAIN       0x04
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
new file mode 100644
index 000000000..ff4533d6e
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_IOMAP_H
+#define _ASM_NLM_IOMAP_H
+
+#define DEFAULT_NETLOGIC_IO_BASE           CKSEG1ADDR(0x1ef00000)
+#define NETLOGIC_IO_DDR2_CHN0_OFFSET       0x01000
+#define NETLOGIC_IO_DDR2_CHN1_OFFSET       0x02000
+#define NETLOGIC_IO_DDR2_CHN2_OFFSET       0x03000
+#define NETLOGIC_IO_DDR2_CHN3_OFFSET       0x04000
+#define NETLOGIC_IO_PIC_OFFSET             0x08000
+#define NETLOGIC_IO_UART_0_OFFSET          0x14000
+#define NETLOGIC_IO_UART_1_OFFSET          0x15100
+
+#define NETLOGIC_IO_SIZE                   0x1000
+
+#define NETLOGIC_IO_BRIDGE_OFFSET          0x00000
+
+#define NETLOGIC_IO_RLD2_CHN0_OFFSET       0x05000
+#define NETLOGIC_IO_RLD2_CHN1_OFFSET       0x06000
+
+#define NETLOGIC_IO_SRAM_OFFSET            0x07000
+
+#define NETLOGIC_IO_PCIX_OFFSET            0x09000
+#define NETLOGIC_IO_HT_OFFSET              0x0A000
+
+#define NETLOGIC_IO_SECURITY_OFFSET        0x0B000
+
+#define NETLOGIC_IO_GMAC_0_OFFSET          0x0C000
+#define NETLOGIC_IO_GMAC_1_OFFSET          0x0D000
+#define NETLOGIC_IO_GMAC_2_OFFSET          0x0E000
+#define NETLOGIC_IO_GMAC_3_OFFSET          0x0F000
+
+/* XLS devices */
+#define NETLOGIC_IO_GMAC_4_OFFSET          0x20000
+#define NETLOGIC_IO_GMAC_5_OFFSET          0x21000
+#define NETLOGIC_IO_GMAC_6_OFFSET          0x22000
+#define NETLOGIC_IO_GMAC_7_OFFSET          0x23000
+
+#define NETLOGIC_IO_PCIE_0_OFFSET          0x1E000
+#define NETLOGIC_IO_PCIE_1_OFFSET          0x1F000
+#define NETLOGIC_IO_SRIO_0_OFFSET          0x1E000
+#define NETLOGIC_IO_SRIO_1_OFFSET          0x1F000
+
+#define NETLOGIC_IO_USB_0_OFFSET           0x24000
+#define NETLOGIC_IO_USB_1_OFFSET           0x25000
+
+#define NETLOGIC_IO_COMP_OFFSET            0x1D000
+/* end XLS devices */
+
+/* XLR devices */
+#define NETLOGIC_IO_SPI4_0_OFFSET          0x10000
+#define NETLOGIC_IO_XGMAC_0_OFFSET         0x11000
+#define NETLOGIC_IO_SPI4_1_OFFSET          0x12000
+#define NETLOGIC_IO_XGMAC_1_OFFSET         0x13000
+/* end XLR devices */
+
+#define NETLOGIC_IO_I2C_0_OFFSET           0x16000
+#define NETLOGIC_IO_I2C_1_OFFSET           0x17000
+
+#define NETLOGIC_IO_GPIO_OFFSET            0x18000
+#define NETLOGIC_IO_FLASH_OFFSET           0x19000
+#define NETLOGIC_IO_TB_OFFSET              0x1C000
+
+#define NETLOGIC_CPLD_OFFSET               KSEG1ADDR(0x1d840000)
+
+/*
+ * Base Address (Virtual) of the PCI Config address space
+ * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
+ * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
+ * ie 1<<24 = 16M
+ */
+#define DEFAULT_PCI_CONFIG_BASE         0x18000000
+#define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
+#define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 000000000..c95d18edf
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ASM_RMI_MSIDEF_H
+#define ASM_RMI_MSIDEF_H
+
+/*
+ * Constants for Intel APIC based MSI messages.
+ * Adapted for the RMI XLR using identical defines
+ */
+
+/*
+ * Shifts for MSI data
+ */
+
+#define MSI_DATA_VECTOR_SHIFT           0
+#define  MSI_DATA_VECTOR_MASK           0x000000ff
+#define  MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
+                                                MSI_DATA_VECTOR_MASK)
+
+#define MSI_DATA_DELIVERY_MODE_SHIFT    8
+#define  MSI_DATA_DELIVERY_FIXED        (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
+#define  MSI_DATA_DELIVERY_LOWPRI       (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
+
+#define MSI_DATA_LEVEL_SHIFT            14
+#define  MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
+#define  MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
+
+#define MSI_DATA_TRIGGER_SHIFT          15
+#define  MSI_DATA_TRIGGER_EDGE          (0 << MSI_DATA_TRIGGER_SHIFT)
+#define  MSI_DATA_TRIGGER_LEVEL         (1 << MSI_DATA_TRIGGER_SHIFT)
+
+/*
+ * Shift/mask fields for msi address
+ */
+
+#define MSI_ADDR_BASE_HI                0
+#define MSI_ADDR_BASE_LO                0xfee00000
+
+#define MSI_ADDR_DEST_MODE_SHIFT        2
+#define  MSI_ADDR_DEST_MODE_PHYSICAL    (0 << MSI_ADDR_DEST_MODE_SHIFT)
+#define  MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
+
+#define MSI_ADDR_REDIRECTION_SHIFT      3
+#define  MSI_ADDR_REDIRECTION_CPU       (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define  MSI_ADDR_REDIRECTION_LOWPRI    (1 << MSI_ADDR_REDIRECTION_SHIFT)
+
+#define MSI_ADDR_DEST_ID_SHIFT          12
+#define  MSI_ADDR_DEST_ID_MASK          0x00ffff0
+#define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
+                                                 MSI_ADDR_DEST_ID_MASK)
+
+#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
new file mode 100644
index 000000000..3c80a7523
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_XLR_PIC_H
+#define _ASM_NLM_XLR_PIC_H
+
+#define PIC_CLK_HZ                      66666666
+#define pic_timer_freq()                PIC_CLK_HZ
+
+/* PIC hardware interrupt numbers */
+#define PIC_IRT_WD_INDEX                0
+#define PIC_IRT_TIMER_0_INDEX           1
+#define PIC_IRT_TIMER_INDEX(i)          ((i) + PIC_IRT_TIMER_0_INDEX)
+#define PIC_IRT_TIMER_1_INDEX           2
+#define PIC_IRT_TIMER_2_INDEX           3
+#define PIC_IRT_TIMER_3_INDEX           4
+#define PIC_IRT_TIMER_4_INDEX           5
+#define PIC_IRT_TIMER_5_INDEX           6
+#define PIC_IRT_TIMER_6_INDEX           7
+#define PIC_IRT_TIMER_7_INDEX           8
+#define PIC_IRT_CLOCK_INDEX             PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_UART_0_INDEX            9
+#define PIC_IRT_UART_1_INDEX            10
+#define PIC_IRT_I2C_0_INDEX             11
+#define PIC_IRT_I2C_1_INDEX             12
+#define PIC_IRT_PCMCIA_INDEX            13
+#define PIC_IRT_GPIO_INDEX              14
+#define PIC_IRT_HYPER_INDEX             15
+#define PIC_IRT_PCIX_INDEX              16
+/* XLS */
+#define PIC_IRT_CDE_INDEX               15
+#define PIC_IRT_BRIDGE_TB_XLS_INDEX     16
+/* XLS */
+#define PIC_IRT_GMAC0_INDEX             17
+#define PIC_IRT_GMAC1_INDEX             18
+#define PIC_IRT_GMAC2_INDEX             19
+#define PIC_IRT_GMAC3_INDEX             20
+#define PIC_IRT_XGS0_INDEX              21
+#define PIC_IRT_XGS1_INDEX              22
+#define PIC_IRT_HYPER_FATAL_INDEX       23
+#define PIC_IRT_PCIX_FATAL_INDEX        24
+#define PIC_IRT_BRIDGE_AERR_INDEX       25
+#define PIC_IRT_BRIDGE_BERR_INDEX       26
+#define PIC_IRT_BRIDGE_TB_XLR_INDEX     27
+#define PIC_IRT_BRIDGE_AERR_NMI_INDEX   28
+/* XLS */
+#define PIC_IRT_GMAC4_INDEX             21
+#define PIC_IRT_GMAC5_INDEX             22
+#define PIC_IRT_GMAC6_INDEX             23
+#define PIC_IRT_GMAC7_INDEX             24
+#define PIC_IRT_BRIDGE_ERR_INDEX        25
+#define PIC_IRT_PCIE_LINK0_INDEX        26
+#define PIC_IRT_PCIE_LINK1_INDEX        27
+#define PIC_IRT_PCIE_LINK2_INDEX        23
+#define PIC_IRT_PCIE_LINK3_INDEX        24
+#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX  28
+#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX  29
+#define PIC_IRT_SRIO_LINK0_INDEX        26
+#define PIC_IRT_SRIO_LINK1_INDEX        27
+#define PIC_IRT_SRIO_LINK2_INDEX        28
+#define PIC_IRT_SRIO_LINK3_INDEX        29
+#define PIC_IRT_PCIE_INT_INDEX          28
+#define PIC_IRT_PCIE_FATAL_INDEX        29
+#define PIC_IRT_GPIO_B_INDEX            30
+#define PIC_IRT_USB_INDEX               31
+/* XLS */
+#define PIC_NUM_IRTS                    32
+
+
+#define PIC_CLOCK_TIMER                 7
+
+/* PIC Registers */
+#define PIC_CTRL                        0x00
+#define PIC_CTRL_STE                    8       /* timer enable start bit */
+#define PIC_IPI                         0x04
+#define PIC_INT_ACK                     0x06
+
+#define WD_MAX_VAL_0                    0x08
+#define WD_MAX_VAL_1                    0x09
+#define WD_MASK_0                       0x0a
+#define WD_MASK_1                       0x0b
+#define WD_HEARBEAT_0                   0x0c
+#define WD_HEARBEAT_1                   0x0d
+
+#define PIC_IRT_0_BASE                  0x40
+#define PIC_IRT_1_BASE                  0x80
+#define PIC_TIMER_MAXVAL_0_BASE         0x100
+#define PIC_TIMER_MAXVAL_1_BASE         0x110
+#define PIC_TIMER_COUNT_0_BASE          0x120
+#define PIC_TIMER_COUNT_1_BASE          0x130
+
+#define PIC_IRT_0(picintr)      (PIC_IRT_0_BASE + (picintr))
+#define PIC_IRT_1(picintr)      (PIC_IRT_1_BASE + (picintr))
+
+#define PIC_TIMER_MAXVAL_0(i)   (PIC_TIMER_MAXVAL_0_BASE + (i))
+#define PIC_TIMER_MAXVAL_1(i)   (PIC_TIMER_MAXVAL_1_BASE + (i))
+#define PIC_TIMER_COUNT_0(i)    (PIC_TIMER_COUNT_0_BASE + (i))
+#define PIC_TIMER_COUNT_1(i)    (PIC_TIMER_COUNT_0_BASE + (i))
+
+/*
+ * Mapping between hardware interrupt numbers and IRQs on CPU
+ * we use a simple scheme to map PIC interrupts 0-31 to IRQs
+ * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
+ * count/compare and FMN
+ */
+#define PIC_IRQ_BASE            8
+#define PIC_INTR_TO_IRQ(i)      (PIC_IRQ_BASE + (i))
+#define PIC_IRQ_TO_INTR(i)      ((i) - PIC_IRQ_BASE)
+
+#define PIC_IRT_FIRST_IRQ       PIC_IRQ_BASE
+#define PIC_WD_IRQ              PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
+#define PIC_TIMER_0_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
+#define PIC_TIMER_1_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
+#define PIC_TIMER_2_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
+#define PIC_TIMER_3_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
+#define PIC_TIMER_4_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
+#define PIC_TIMER_5_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
+#define PIC_TIMER_6_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
+#define PIC_TIMER_7_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
+#define PIC_CLOCK_IRQ           (PIC_TIMER_7_IRQ)
+#define PIC_UART_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
+#define PIC_UART_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
+#define PIC_I2C_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
+#define PIC_I2C_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
+#define PIC_PCMCIA_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
+#define PIC_GPIO_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
+#define PIC_HYPER_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
+#define PIC_PCIX_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
+/* XLS */
+#define PIC_CDE_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
+#define PIC_BRIDGE_TB_XLS_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
+/* end XLS */
+#define PIC_GMAC_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
+#define PIC_GMAC_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
+#define PIC_GMAC_2_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
+#define PIC_GMAC_3_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
+#define PIC_XGS_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
+#define PIC_XGS_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
+#define PIC_HYPER_FATAL_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
+#define PIC_PCIX_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
+#define PIC_BRIDGE_AERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
+#define PIC_BRIDGE_BERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
+#define PIC_BRIDGE_TB_XLR_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
+#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
+/* XLS defines */
+#define PIC_GMAC_4_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
+#define PIC_GMAC_5_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
+#define PIC_GMAC_6_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
+#define PIC_GMAC_7_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
+#define PIC_BRIDGE_ERR_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
+#define PIC_PCIE_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
+#define PIC_PCIE_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
+#define PIC_PCIE_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
+#define PIC_PCIE_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
+#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
+#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
+#define PIC_SRIO_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
+#define PIC_SRIO_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
+#define PIC_SRIO_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
+#define PIC_SRIO_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
+#define PIC_PCIE_INT_IRQ        PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
+#define PIC_PCIE_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
+#define PIC_GPIO_B_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
+#define PIC_USB_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
+#define PIC_IRT_LAST_IRQ        PIC_USB_IRQ
+/* end XLS */
+
+#ifndef __ASSEMBLY__
+
+#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
+                                        ((irq) <= PIC_TIMER_7_IRQ))
+#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
+                                        ((irq) <= PIC_IRT_LAST_IRQ))
+
+static inline int
+nlm_irq_to_irt(int irq)
+{
+        if (PIC_IRQ_IS_IRT(irq) == 0)
+                return -1;
+
+        return PIC_IRQ_TO_INTR(irq);
+}
+
+static inline int
+nlm_irt_to_irq(int irt)
+{
+
+        return PIC_INTR_TO_IRQ(irt);
+}
+
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
+{
+        uint32_t reg;
+
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
+}
+
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
+{
+        uint32_t reg;
+
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
+}
+
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        unsigned int tid, pid;
+
+        tid = hwt & 0x3;
+        pid = (hwt >> 2) & 0x07;
+        nlm_write_reg(base, PIC_IPI,
+                (pid << 20) | (tid << 16) | (nmi << 8) | irq);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt)
+{
+        nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
+}
+
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
+{
+        nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
+        /* local scheduling, invalid, level by default */
+        nlm_write_reg(base, PIC_IRT_1(irt),
+                (en << 30) | (1 << 6) | irq);
+}
+
+static inline uint64_t
+nlm_pic_read_timer(uint64_t base, int timer)
+{
+        uint32_t up1, up2, low;
+
+        up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
+        low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
+        up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
+
+        if (up1 != up2) /* wrapped, get the new low */
+                low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
+        return ((uint64_t)up2 << 32) | low;
+
+}
+
+static inline uint32_t
+nlm_pic_read_timer32(uint64_t base, int timer)
+{
+        return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
+}
+
+static inline void
+nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
+{
+        uint32_t up, low;
+        uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
+        int en;
+
+        en = (irq > 0);
+        up = value >> 32;
+        low = value & 0xFFFFFFFF;
+        nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
+        nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
+        nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
+
+        /* enable the timer */
+        pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
+        nlm_write_reg(base, PIC_CTRL, pic_ctrl);
+}
+#endif
+#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
new file mode 100644
index 000000000..ceb991ca8
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_XLR_H
+#define _ASM_NLM_XLR_H
+
+/* SMP helpers */
+void xlr_wakeup_secondary_cpus(void);
+
+/* XLS B silicon "Rook" */
+static inline unsigned int nlm_chip_is_xls_b(void)
+{
+        uint32_t prid = read_c0_prid();
+
+        return ((prid & 0xf000) == 0x4000);
+}
+
+/*  XLR chip types */
+/* The XLS product line has chip versions 0x[48c]? */
+static inline unsigned int nlm_chip_is_xls(void)
+{
+        uint32_t prid = read_c0_prid();
+
+        return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
+                (prid & 0xf000) == 0xc000);
+}
+
+#endif /* _ASM_NLM_XLR_H */
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
new file mode 100644
index 000000000..e4444f8c4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -0,0 +1,341 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2009 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * Typedefs and defines for working with Octeon physical addresses.
+ *
+ */
+#ifndef __CVMX_ADDRESS_H__
+#define __CVMX_ADDRESS_H__
+
+#if 0
+typedef enum {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+} cvmx_mips_space_t;
+#endif
+
+typedef enum {
+        CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
+        CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
+        CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
+        CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
+} cvmx_mips_xkseg_space_t;
+
+/* decodes <14:13> of a kseg3 window address */
+typedef enum {
+        CVMX_ADD_WIN_SCR = 0L,
+        /* see cvmx_add_win_dma_dec_t for further decode */
+        CVMX_ADD_WIN_DMA = 1L,
+        CVMX_ADD_WIN_UNUSED = 2L,
+        CVMX_ADD_WIN_UNUSED2 = 3L
+} cvmx_add_win_dec_t;
+
+/* decode within DMA space */
+typedef enum {
+        /*
+         * Add store data to the write buffer entry, allocating it if
+         * necessary.
+         */
+        CVMX_ADD_WIN_DMA_ADD = 0L,
+        /* send out the write buffer entry to DRAM */
+        CVMX_ADD_WIN_DMA_SENDMEM = 1L,
+        /* store data must be normal DRAM memory space address in this case */
+        /* send out the write buffer entry as an IOBDMA command */
+        CVMX_ADD_WIN_DMA_SENDDMA = 2L,
+        /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
+        /* send out the write buffer entry as an IO write */
+        CVMX_ADD_WIN_DMA_SENDIO = 3L,
+        /* store data must be normal IO space address in this case */
+        /* send out a single-tick command on the NCB bus */
+        CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
+        /* no write buffer data needed/used */
+} cvmx_add_win_dma_dec_t;
+
+/*
+ *   Physical Address Decode
+ *
+ * Octeon-I HW never interprets this X (<39:36> reserved
+ * for future expansion), software should set to 0.
+ *
+ *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
+ *  - 0x0 XXX0 0FFF FFFF
+ *
+ *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
+ *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
+ *
+ *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
+ *  - 0x0 XXXF FFFF FFFF
+ *
+ *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
+ *  - 0x1 00XF FFFF FFFF
+ *
+ *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
+ *  - 0x1 FFXF FFFF FFFF         devices
+ *
+ * Decode of all Octeon addresses
+ */
+typedef union {
+
+        uint64_t u64;
+#ifdef __BIG_ENDIAN_BITFIELD
+        /* mapped or unmapped virtual address */
+        struct {
+                uint64_t R:2;
+                uint64_t offset:62;
+        } sva;
+
+        /* mapped USEG virtual addresses (typically) */
+        struct {
+                uint64_t zeroes:33;
+                uint64_t offset:31;
+        } suseg;
+
+        /* mapped or unmapped virtual address */
+        struct {
+                uint64_t ones:33;
+                uint64_t sp:2;
+                uint64_t offset:29;
+        } sxkseg;
+
+        /*
+         * physical address accessed through xkphys unmapped virtual
+         * address.
+         */
+        struct {
+                uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */
+                uint64_t cca:3; /* ignored by octeon */
+                uint64_t mbz:10;
+                uint64_t pa:49; /* physical address */
+        } sxkphys;
+
+        /* physical address */
+        struct {
+                uint64_t mbz:15;
+                /* if set, the address is uncached and resides on MCB bus */
+                uint64_t is_io:1;
+                /*
+                 * the hardware ignores this field when is_io==0, else
+                 * device ID.
+                 */
+                uint64_t did:8;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } sphys;
+
+        /* physical mem address */
+        struct {
+                /* techically, <47:40> are dont-cares */
+                uint64_t zeroes:24;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } smem;
+
+        /* physical IO address */
+        struct {
+                uint64_t mem_region:2;
+                uint64_t mbz:13;
+                /* 1 in this case */
+                uint64_t is_io:1;
+                /*
+                 * The hardware ignores this field when is_io==0, else
+                 * device ID.
+                 */
+                uint64_t did:8;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } sio;
+
+        /*
+         * Scratchpad virtual address - accessed through a window at
+         * the end of kseg3
+         */
+        struct {
+                uint64_t ones:49;
+                /* CVMX_ADD_WIN_SCR (0) in this case */
+                cvmx_add_win_dec_t csrdec:2;
+                uint64_t addr:13;
+        } sscr;
+
+        /* there should only be stores to IOBDMA space, no loads */
+        /*
+         * IOBDMA virtual address - accessed through a window at the
+         * end of kseg3
+         */
+        struct {
+                uint64_t ones:49;
+                uint64_t csrdec:2;      /* CVMX_ADD_WIN_DMA (1) in this case */
+                uint64_t unused2:3;
+                uint64_t type:3;
+                uint64_t addr:7;
+        } sdma;
+
+        struct {
+                uint64_t didspace:24;
+                uint64_t unused:40;
+        } sfilldidspace;
+#else
+        struct {
+                uint64_t offset:62;
+                uint64_t R:2;
+        } sva;
+
+        struct {
+                uint64_t offset:31;
+                uint64_t zeroes:33;
+        } suseg;
+
+        struct {
+                uint64_t offset:29;
+                uint64_t sp:2;
+                uint64_t ones:33;
+        } sxkseg;
+
+        struct {
+                uint64_t pa:49;
+                uint64_t mbz:10;
+                uint64_t cca:3;
+                uint64_t R:2;
+        } sxkphys;
+
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t mbz:15;
+        } sphys;
+
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t zeroes:24;
+        } smem;
+
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t mbz:13;
+                uint64_t mem_region:2;
+        } sio;
+
+        struct {
+                uint64_t addr:13;
+                cvmx_add_win_dec_t csrdec:2;
+                uint64_t ones:49;
+        } sscr;
+
+        struct {
+                uint64_t addr:7;
+                uint64_t type:3;
+                uint64_t unused2:3;
+                uint64_t csrdec:2;
+                uint64_t ones:49;
+        } sdma;
+
+        struct {
+                uint64_t unused:40;
+                uint64_t didspace:24;
+        } sfilldidspace;
+#endif
+
+} cvmx_addr_t;
+
+/* These macros for used by 32 bit applications */
+
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+/*
+ * Currently all IOs are performed using XKPHYS addressing. Linux uses
+ * the CvmMemCtl register to enable XKPHYS addressing to IO space from
+ * user mode.  Future OSes may need to change the upper bits of IO
+ * addresses. The following define controls the upper two bits for all
+ * IO addresses generated by the simple executive library.
+ */
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
+#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
+#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
+
+  /* from include/ncb_rsl_id.v */
+#define CVMX_OCT_DID_MIS 0ULL   /* misc stuff */
+#define CVMX_OCT_DID_GMX0 1ULL
+#define CVMX_OCT_DID_GMX1 2ULL
+#define CVMX_OCT_DID_PCI 3ULL
+#define CVMX_OCT_DID_KEY 4ULL
+#define CVMX_OCT_DID_FPA 5ULL
+#define CVMX_OCT_DID_DFA 6ULL
+#define CVMX_OCT_DID_ZIP 7ULL
+#define CVMX_OCT_DID_RNG 8ULL
+#define CVMX_OCT_DID_IPD 9ULL
+#define CVMX_OCT_DID_PKT 10ULL
+#define CVMX_OCT_DID_TIM 11ULL
+#define CVMX_OCT_DID_TAG 12ULL
+  /* the rest are not on the IO bus */
+#define CVMX_OCT_DID_L2C 16ULL
+#define CVMX_OCT_DID_LMC 17ULL
+#define CVMX_OCT_DID_SPX0 18ULL
+#define CVMX_OCT_DID_SPX1 19ULL
+#define CVMX_OCT_DID_PIP 20ULL
+#define CVMX_OCT_DID_ASX0 22ULL
+#define CVMX_OCT_DID_ASX1 23ULL
+#define CVMX_OCT_DID_IOB 30ULL
+
+#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
+#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
+#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
+#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
+#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
+#define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
+#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
+#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
+#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
+#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
+#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
+#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
+#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
+#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
+#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
+#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
+#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
+
+#endif /* __CVMX_ADDRESS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000..3635ab384
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1759 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
+
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
+
+union cvmx_agl_gmx_bad_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_24_25:2;
+                uint64_t loststat:2;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t out_ovr:2;
+                uint64_t reserved_4_21:18;
+                uint64_t loststat:2;
+                uint64_t reserved_24_25:2;
+                uint64_t statovr:1;
+                uint64_t reserved_27_31:5;
+                uint64_t ovrflw:1;
+                uint64_t txpop:1;
+                uint64_t txpsh:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpop1:1;
+                uint64_t txpsh1:1;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+        struct cvmx_agl_gmx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t out_ovr:2;
+                uint64_t reserved_4_21:18;
+                uint64_t loststat:1;
+                uint64_t reserved_23_25:3;
+                uint64_t statovr:1;
+                uint64_t reserved_27_31:5;
+                uint64_t ovrflw:1;
+                uint64_t txpop:1;
+                uint64_t txpsh:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpop1:1;
+                uint64_t txpsh1:1;
+                uint64_t reserved_38_63:26;
+#endif
+        } cn52xx;
+        struct cvmx_agl_gmx_bad_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
+                uint64_t reserved_23_25:3;
+                uint64_t loststat:1;
+                uint64_t reserved_3_21:19;
+                uint64_t out_ovr:1;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t out_ovr:1;
+                uint64_t reserved_3_21:19;
+                uint64_t loststat:1;
+                uint64_t reserved_23_25:3;
+                uint64_t statovr:1;
+                uint64_t reserved_27_31:5;
+                uint64_t ovrflw:1;
+                uint64_t txpop:1;
+                uint64_t txpsh:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_bist {
+        uint64_t u64;
+        struct cvmx_agl_gmx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t status:25;
+#else
+                uint64_t status:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+        struct cvmx_agl_gmx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t status:10;
+#else
+                uint64_t status:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_drv_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t byp_en1:1;
+                uint64_t reserved_45_47:3;
+                uint64_t pctl1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t nctl1:5;
+                uint64_t reserved_17_31:15;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t byp_en:1;
+                uint64_t reserved_17_31:15;
+                uint64_t nctl1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t pctl1:5;
+                uint64_t reserved_45_47:3;
+                uint64_t byp_en1:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+        struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t byp_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t byp_en:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_inf_mode {
+        uint64_t u64;
+        struct cvmx_agl_gmx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t en:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t en:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_7_7:1;
+                uint64_t burst:1;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t speed:1;
+                uint64_t duplex:1;
+                uint64_t slottime:1;
+                uint64_t rx_en:1;
+                uint64_t tx_en:1;
+                uint64_t burst:1;
+                uint64_t reserved_7_7:1;
+                uint64_t speed_msb:1;
+                uint64_t reserved_9_11:3;
+                uint64_t rx_idle:1;
+                uint64_t tx_idle:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t speed:1;
+                uint64_t duplex:1;
+                uint64_t slottime:1;
+                uint64_t rx_en:1;
+                uint64_t tx_en:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t adr:64;
+#else
+                uint64_t adr:64;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_cam_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_adr_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t cam_mode:1;
+                uint64_t mcst:2;
+                uint64_t bcst:1;
+#else
+                uint64_t bcst:1;
+                uint64_t mcst:2;
+                uint64_t cam_mode:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_decision {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t cnt:5;
+#else
+                uint64_t cnt:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_frm_chk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_rxx_frm_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_11_11:1;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t pre_align:1;
+                uint64_t null_dis:1;
+                uint64_t reserved_11_11:1;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t pre_align:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_rxx_frm_max {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+#else
+                uint64_t len:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_frm_min {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+#else
+                uint64_t len:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t ifg:4;
+#else
+                uint64_t ifg:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_rxx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t reserved_1_1:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn52xx;
+};
+
+union cvmx_agl_gmx_rxx_jabber {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+#else
+                uint64_t cnt:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_pause_drop_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t status:16;
+#else
+                uint64_t status:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_rx_inbnd {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t duplex:1;
+                uint64_t speed:2;
+                uint64_t status:1;
+#else
+                uint64_t status:1;
+                uint64_t speed:2;
+                uint64_t duplex:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+#else
+                uint64_t rd_clr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+#else
+                uint64_t cnt:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+#else
+                uint64_t cnt:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+#else
+                uint64_t cnt:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_octs_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+#else
+                uint64_t cnt:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_bad {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_stats_pkts_drp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rxx_udd_skp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t fcssel:1;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+#else
+                uint64_t len:7;
+                uint64_t reserved_7_7:1;
+                uint64_t fcssel:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rx_bp_dropx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+#else
+                uint64_t mark:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rx_bp_offx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+#else
+                uint64_t mark:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rx_bp_onx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t mark:9;
+#else
+                uint64_t mark:9;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_rx_prt_info {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t drop:2;
+                uint64_t reserved_2_15:14;
+                uint64_t commit:2;
+#else
+                uint64_t commit:2;
+                uint64_t reserved_2_15:14;
+                uint64_t drop:2;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t drop:1;
+                uint64_t reserved_1_15:15;
+                uint64_t commit:1;
+#else
+                uint64_t commit:1;
+                uint64_t reserved_1_15:15;
+                uint64_t drop:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_rx_tx_status {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t tx:2;
+                uint64_t reserved_2_3:2;
+                uint64_t rx:2;
+#else
+                uint64_t rx:2;
+                uint64_t reserved_2_3:2;
+                uint64_t tx:2;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+        struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t tx:1;
+                uint64_t reserved_1_3:3;
+                uint64_t rx:1;
+#else
+                uint64_t rx:1;
+                uint64_t reserved_1_3:3;
+                uint64_t tx:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_smacx {
+        uint64_t u64;
+        struct cvmx_agl_gmx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t smac:48;
+#else
+                uint64_t smac:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_stat_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t bp:1;
+                uint64_t cnt:16;
+#else
+                uint64_t cnt:16;
+                uint64_t bp:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_append {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t force_fcs:1;
+                uint64_t fcs:1;
+                uint64_t pad:1;
+                uint64_t preamble:1;
+#else
+                uint64_t preamble:1;
+                uint64_t pad:1;
+                uint64_t fcs:1;
+                uint64_t force_fcs:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_clk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t clk_cnt:6;
+#else
+                uint64_t clk_cnt:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t xsdef_en:1;
+                uint64_t xscol_en:1;
+#else
+                uint64_t xscol_en:1;
+                uint64_t xsdef_en:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_min_pkt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t min_size:8;
+#else
+                uint64_t min_size:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_interval {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t interval:16;
+#else
+                uint64_t interval:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_pause_pkt_time {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+#else
+                uint64_t time:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_pause_togo {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+#else
+                uint64_t time:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_pause_zero {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t send:1;
+#else
+                uint64_t send:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_soft_pause {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+#else
+                uint64_t time:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat0 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t xsdef:32;
+                uint64_t xscol:32;
+#else
+                uint64_t xscol:32;
+                uint64_t xsdef:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat1 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t scol:32;
+                uint64_t mcol:32;
+#else
+                uint64_t mcol:32;
+                uint64_t scol:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat2 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat3 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+#else
+                uint64_t pkts:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat4 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t hist1:32;
+                uint64_t hist0:32;
+#else
+                uint64_t hist0:32;
+                uint64_t hist1:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat5 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t hist3:32;
+                uint64_t hist2:32;
+#else
+                uint64_t hist2:32;
+                uint64_t hist3:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat6 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t hist5:32;
+                uint64_t hist4:32;
+#else
+                uint64_t hist4:32;
+                uint64_t hist5:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat7 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t hist7:32;
+                uint64_t hist6:32;
+#else
+                uint64_t hist6:32;
+                uint64_t hist7:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat8 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+#else
+                uint64_t bcst:32;
+                uint64_t mcst:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stat9 {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t undflw:32;
+                uint64_t ctl:32;
+#else
+                uint64_t ctl:32;
+                uint64_t undflw:32;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+#else
+                uint64_t rd_clr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_txx_thresh {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t cnt:6;
+#else
+                uint64_t cnt:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t bp:2;
+#else
+                uint64_t bp:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+        struct cvmx_agl_gmx_tx_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t bp:1;
+#else
+                uint64_t bp:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_tx_col_attempt {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t limit:5;
+#else
+                uint64_t limit:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_ifg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ifg2:4;
+                uint64_t ifg1:4;
+#else
+                uint64_t ifg1:4;
+                uint64_t ifg2:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_int_en {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_19:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_agl_gmx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_en_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:1;
+                uint64_t reserved_3_7:5;
+                uint64_t xscol:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_13_15:3;
+                uint64_t late_col:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_tx_int_reg {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_19:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t late_col:1;
+                uint64_t reserved_13_15:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xscol:1;
+                uint64_t reserved_3_7:5;
+                uint64_t undflw:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:1;
+                uint64_t reserved_3_7:5;
+                uint64_t xscol:1;
+                uint64_t reserved_9_11:3;
+                uint64_t xsdef:1;
+                uint64_t reserved_13_15:3;
+                uint64_t late_col:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_tx_jam {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t jam:8;
+#else
+                uint64_t jam:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_lfsr {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t lfsr:16;
+#else
+                uint64_t lfsr:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_ovr_bp {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t en:2;
+                uint64_t reserved_6_7:2;
+                uint64_t bp:2;
+                uint64_t reserved_2_3:2;
+                uint64_t ign_full:2;
+#else
+                uint64_t ign_full:2;
+                uint64_t reserved_2_3:2;
+                uint64_t bp:2;
+                uint64_t reserved_6_7:2;
+                uint64_t en:2;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t en:1;
+                uint64_t reserved_5_7:3;
+                uint64_t bp:1;
+                uint64_t reserved_1_3:3;
+                uint64_t ign_full:1;
+#else
+                uint64_t ign_full:1;
+                uint64_t reserved_1_3:3;
+                uint64_t bp:1;
+                uint64_t reserved_5_7:3;
+                uint64_t en:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn56xx;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_dmac {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t dmac:48;
+#else
+                uint64_t dmac:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_agl_gmx_tx_pause_pkt_type {
+        uint64_t u64;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t type:16;
+#else
+                uint64_t type:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_agl_prtx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_prtx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t drv_byp:1;
+                uint64_t reserved_62_62:1;
+                uint64_t cmp_pctl:6;
+                uint64_t reserved_54_55:2;
+                uint64_t cmp_nctl:6;
+                uint64_t reserved_46_47:2;
+                uint64_t drv_pctl:6;
+                uint64_t reserved_38_39:2;
+                uint64_t drv_nctl:6;
+                uint64_t reserved_29_31:3;
+                uint64_t clk_set:5;
+                uint64_t clkrx_byp:1;
+                uint64_t reserved_21_22:2;
+                uint64_t clkrx_set:5;
+                uint64_t clktx_byp:1;
+                uint64_t reserved_13_14:2;
+                uint64_t clktx_set:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dllrst:1;
+                uint64_t comp:1;
+                uint64_t enable:1;
+                uint64_t clkrst:1;
+                uint64_t mode:1;
+#else
+                uint64_t mode:1;
+                uint64_t clkrst:1;
+                uint64_t enable:1;
+                uint64_t comp:1;
+                uint64_t dllrst:1;
+                uint64_t reserved_5_7:3;
+                uint64_t clktx_set:5;
+                uint64_t reserved_13_14:2;
+                uint64_t clktx_byp:1;
+                uint64_t clkrx_set:5;
+                uint64_t reserved_21_22:2;
+                uint64_t clkrx_byp:1;
+                uint64_t clk_set:5;
+                uint64_t reserved_29_31:3;
+                uint64_t drv_nctl:6;
+                uint64_t reserved_38_39:2;
+                uint64_t drv_pctl:6;
+                uint64_t reserved_46_47:2;
+                uint64_t cmp_nctl:6;
+                uint64_t reserved_54_55:2;
+                uint64_t cmp_pctl:6;
+                uint64_t reserved_62_62:1;
+                uint64_t drv_byp:1;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
new file mode 100644
index 000000000..31eacc24b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * This is file defines ASM primitives for the executive.
+ */
+#ifndef __CVMX_ASM_H__
+#define __CVMX_ASM_H__
+
+#include <asm/octeon/octeon-model.h>
+
+/* other useful stuff */
+#define CVMX_SYNC asm volatile ("sync" : : : "memory")
+/* String version of SYNCW macro for using in inline asm constructs */
+#define CVMX_SYNCW_STR "syncw\nsyncw\n"
+#ifdef __OCTEON__
+
+/* Deprecated, will be removed in future release */
+#define CVMX_SYNCIO asm volatile ("nop")
+
+#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
+
+/* Deprecated, will be removed in future release */
+#define CVMX_SYNCIOALL asm volatile ("nop")
+
+/*
+ * We actually use two syncw instructions in a row when we need a write
+ * memory barrier. This is because the CN3XXX series of Octeons have
+ * errata Core-401. This can cause a single syncw to not enforce
+ * ordering under very rare conditions. Even if it is rare, better safe
+ * than sorry.
+ */
+#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
+
+/*
+ * Define new sync instructions to be normal SYNC instructions for
+ * operating systems that use threads.
+ */
+#define CVMX_SYNCWS CVMX_SYNCW
+#define CVMX_SYNCS  CVMX_SYNC
+#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#else
+/*
+ * Not using a Cavium compiler, always use the slower sync so the
+ * assembler stays happy.
+ */
+/* Deprecated, will be removed in future release */
+#define CVMX_SYNCIO asm volatile ("nop")
+
+#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
+
+/* Deprecated, will be removed in future release */
+#define CVMX_SYNCIOALL asm volatile ("nop")
+
+#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
+#define CVMX_SYNCWS CVMX_SYNCW
+#define CVMX_SYNCS  CVMX_SYNC
+#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#endif
+
+/*
+ * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
+ * (actually old value or zero) until that byte is stored to (by this or
+ * another processor. Note that the value of each byte is not only
+ * unpredictable, but may also change again - up until the point when one
+ * of the cores stores to the byte.
+ */
+#define CVMX_PREPARE_FOR_STORE(address, offset) \
+        asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
+        [rbase] "d" (address))
+/*
+ * This is a command headed to the L2 controller to tell it to clear
+ * its dirty bit for a block. Basically, SW is telling HW that the
+ * current version of the block will not be used.
+ */
+#define CVMX_DONT_WRITE_BACK(address, offset) \
+        asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
+        [rbase] "d" (address))
+
+/* flush stores, invalidate entire icache */
+#define CVMX_ICACHE_INVALIDATE \
+        { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
+
+/* flush stores, invalidate entire icache */
+#define CVMX_ICACHE_INVALIDATE2 \
+        { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
+
+/* complete prefetches, invalidate entire dcache */
+#define CVMX_DCACHE_INVALIDATE \
+        { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
+
+#define CVMX_CACHE(op, address, offset)                                 \
+        asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
+                : : [rbase] "d" (address) )
+/* fetch and lock the state. */
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
+/* unlock the state. */
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
+/* invalidate the cache block and clear the USED bits for the block */
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
+/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
+
+#define CVMX_POP(result, input) \
+        asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DPOP(result, input) \
+        asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+
+/* some new cop0-like stuff */
+#define CVMX_RDHWR(result, regstr) \
+        asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#define CVMX_RDHWRNV(result, regstr) \
+        asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
new file mode 100644
index 000000000..70f4a5729
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
@@ -0,0 +1,566 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
+
+#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
+#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
+#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
+#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
+#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
+
+void __cvmx_interrupt_asxx_enable(int block);
+
+union cvmx_asxx_gmii_rx_clk_set {
+        uint64_t u64;
+        struct cvmx_asxx_gmii_rx_clk_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_gmii_rx_dat_set {
+        uint64_t u64;
+        struct cvmx_asxx_gmii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_int_en {
+        uint64_t u64;
+        struct cvmx_asxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t txpsh:4;
+                uint64_t txpop:4;
+                uint64_t ovrflw:4;
+#else
+                uint64_t ovrflw:4;
+                uint64_t txpop:4;
+                uint64_t txpsh:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_asxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t txpsh:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ovrflw:3;
+#else
+                uint64_t ovrflw:3;
+                uint64_t reserved_3_3:1;
+                uint64_t txpop:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpsh:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn30xx;
+};
+
+union cvmx_asxx_int_reg {
+        uint64_t u64;
+        struct cvmx_asxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t txpsh:4;
+                uint64_t txpop:4;
+                uint64_t ovrflw:4;
+#else
+                uint64_t ovrflw:4;
+                uint64_t txpop:4;
+                uint64_t txpsh:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_asxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t txpsh:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ovrflw:3;
+#else
+                uint64_t ovrflw:3;
+                uint64_t reserved_3_3:1;
+                uint64_t txpop:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpsh:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn30xx;
+};
+
+union cvmx_asxx_mii_rx_dat_set {
+        uint64_t u64;
+        struct cvmx_asxx_mii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_prt_loop {
+        uint64_t u64;
+        struct cvmx_asxx_prt_loop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ext_loop:4;
+                uint64_t int_loop:4;
+#else
+                uint64_t int_loop:4;
+                uint64_t ext_loop:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_asxx_prt_loop_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t ext_loop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t int_loop:3;
+#else
+                uint64_t int_loop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ext_loop:3;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn30xx;
+};
+
+union cvmx_asxx_rld_bypass {
+        uint64_t u64;
+        struct cvmx_asxx_rld_bypass_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t bypass:1;
+#else
+                uint64_t bypass:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_bypass_setting {
+        uint64_t u64;
+        struct cvmx_asxx_rld_bypass_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_comp {
+        uint64_t u64;
+        struct cvmx_asxx_rld_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t pctl:5;
+                uint64_t nctl:4;
+#else
+                uint64_t nctl:4;
+                uint64_t pctl:5;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+        struct cvmx_asxx_rld_comp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+#else
+                uint64_t nctl:4;
+                uint64_t pctl:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn38xx;
+};
+
+union cvmx_asxx_rld_data_drv {
+        uint64_t u64;
+        struct cvmx_asxx_rld_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+#else
+                uint64_t nctl:4;
+                uint64_t pctl:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_fcram_mode {
+        uint64_t u64;
+        struct cvmx_asxx_rld_fcram_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t mode:1;
+#else
+                uint64_t mode:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_nctl_strong {
+        uint64_t u64;
+        struct cvmx_asxx_rld_nctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_nctl_weak {
+        uint64_t u64;
+        struct cvmx_asxx_rld_nctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_pctl_strong {
+        uint64_t u64;
+        struct cvmx_asxx_rld_pctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t pctl:5;
+#else
+                uint64_t pctl:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_pctl_weak {
+        uint64_t u64;
+        struct cvmx_asxx_rld_pctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t pctl:5;
+#else
+                uint64_t pctl:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rld_setting {
+        uint64_t u64;
+        struct cvmx_asxx_rld_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t dfaset:5;
+                uint64_t dfalag:1;
+                uint64_t dfalead:1;
+                uint64_t dfalock:1;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t dfalock:1;
+                uint64_t dfalead:1;
+                uint64_t dfalag:1;
+                uint64_t dfaset:5;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_asxx_rld_setting_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn38xx;
+};
+
+union cvmx_asxx_rx_clk_setx {
+        uint64_t u64;
+        struct cvmx_asxx_rx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rx_prt_en {
+        uint64_t u64;
+        struct cvmx_asxx_rx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t prt_en:4;
+#else
+                uint64_t prt_en:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_asxx_rx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t prt_en:3;
+#else
+                uint64_t prt_en:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+};
+
+union cvmx_asxx_rx_wol {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t status:1;
+                uint64_t enable:1;
+#else
+                uint64_t enable:1;
+                uint64_t status:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rx_wol_msk {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t msk:64;
+#else
+                uint64_t msk:64;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rx_wol_powok {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_powok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t powerok:1;
+#else
+                uint64_t powerok:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_asxx_rx_wol_sig {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_sig_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t sig:32;
+#else
+                uint64_t sig:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_asxx_tx_clk_setx {
+        uint64_t u64;
+        struct cvmx_asxx_tx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+#else
+                uint64_t setting:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_asxx_tx_comp_byp {
+        uint64_t u64;
+        struct cvmx_asxx_tx_comp_byp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_asxx_tx_comp_byp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t bypass:1;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+#else
+                uint64_t nctl:4;
+                uint64_t pctl:4;
+                uint64_t bypass:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn30xx;
+        struct cvmx_asxx_tx_comp_byp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+#else
+                uint64_t nctl:4;
+                uint64_t pctl:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn38xx;
+        struct cvmx_asxx_tx_comp_byp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t bypass:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t bypass:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn50xx;
+        struct cvmx_asxx_tx_comp_byp_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn58xx;
+};
+
+union cvmx_asxx_tx_hi_waterx {
+        uint64_t u64;
+        struct cvmx_asxx_tx_hi_waterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t mark:4;
+#else
+                uint64_t mark:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t mark:3;
+#else
+                uint64_t mark:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+};
+
+union cvmx_asxx_tx_prt_en {
+        uint64_t u64;
+        struct cvmx_asxx_tx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t prt_en:4;
+#else
+                uint64_t prt_en:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_asxx_tx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t prt_en:3;
+#else
+                uint64_t prt_en:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-boot-vector.h b/arch/mips/include/asm/octeon/cvmx-boot-vector.h
new file mode 100644
index 000000000..8db08241d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-boot-vector.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2017 Cavium, Inc.
+ */
+
+#ifndef __CVMX_BOOT_VECTOR_H__
+#define __CVMX_BOOT_VECTOR_H__
+
+#include <asm/octeon/octeon.h>
+
+/*
+ * The boot vector table is made up of an array of 1024 elements of
+ * struct cvmx_boot_vector_element.  There is one entry for each
+ * possible MIPS CPUNum, indexed by the CPUNum.
+ *
+ * Once cvmx_boot_vector_get() returns a non-NULL value (indicating
+ * success), NMI to a core will cause execution to transfer to the
+ * target_ptr location for that core's entry in the vector table.
+ *
+ * The struct cvmx_boot_vector_element fields app0, app1, and app2 can
+ * be used by the application that has set the target_ptr in any
+ * application specific manner, they are not touched by the vectoring
+ * code.
+ *
+ * The boot vector code clobbers the CP0_DESAVE register, and on
+ * OCTEON II and later CPUs also clobbers CP0_KScratch2.  All GP
+ * registers are preserved, except on pre-OCTEON II CPUs, where k1 is
+ * clobbered.
+ *
+ */
+
+
+/*
+ * Applications install the boot bus code in cvmx-boot-vector.c, which
+ * uses this magic:
+ */
+#define OCTEON_BOOT_MOVEABLE_MAGIC1 0xdb00110ad358eacdull
+
+struct cvmx_boot_vector_element {
+        /* kseg0 or xkphys address of target code. */
+        uint64_t target_ptr;
+        /* Three application specific arguments. */
+        uint64_t app0;
+        uint64_t app1;
+        uint64_t app2;
+};
+
+struct cvmx_boot_vector_element *cvmx_boot_vector_get(void);
+
+#endif /* __CVMX_BOOT_VECTOR_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
new file mode 100644
index 000000000..e77e8b7c0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -0,0 +1,424 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Header file containing the ABI with the bootloader.
+ */
+
+#ifndef __CVMX_BOOTINFO_H__
+#define __CVMX_BOOTINFO_H__
+
+#include "cvmx-coremask.h"
+
+/*
+ * Current major and minor versions of the CVMX bootinfo block that is
+ * passed from the bootloader to the application.  This is versioned
+ * so that applications can properly handle multiple bootloader
+ * versions.
+ */
+#define CVMX_BOOTINFO_MAJ_VER 1
+#define CVMX_BOOTINFO_MIN_VER 4
+
+#if (CVMX_BOOTINFO_MAJ_VER == 1)
+#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
+/*
+ * This structure is populated by the bootloader.  For binary
+ * compatibility the only changes that should be made are
+ * adding members to the end of the structure, and the minor
+ * version should be incremented at that time.
+ * If an incompatible change is made, the major version
+ * must be incremented, and the minor version should be reset
+ * to 0.
+ */
+struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint32_t major_version;
+        uint32_t minor_version;
+
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        uint64_t desc_vaddr;
+
+        uint32_t exception_base_addr;
+        uint32_t stack_size;
+        uint32_t flags;
+        uint32_t core_mask;
+        /* DRAM size in megabytes */
+        uint32_t dram_size;
+        /* physical address of free memory descriptor block*/
+        uint32_t phy_mem_desc_addr;
+        /* used to pass flags from app to debugger */
+        uint32_t debugger_flags_base_addr;
+
+        /* CPU clock speed, in hz */
+        uint32_t eclock_hz;
+
+        /* DRAM clock speed, in hz */
+        uint32_t dclock_hz;
+
+        uint32_t reserved0;
+        uint16_t board_type;
+        uint8_t board_rev_major;
+        uint8_t board_rev_minor;
+        uint16_t reserved1;
+        uint8_t reserved2;
+        uint8_t reserved3;
+        char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+        /*
+         * Several boards support compact flash on the Octeon boot
+         * bus.  The CF memory spaces may be mapped to different
+         * addresses on different boards.  These are the physical
+         * addresses, so care must be taken to use the correct
+         * XKPHYS/KSEG0 addressing depending on the application's
+         * ABI.  These values will be 0 if CF is not present.
+         */
+        uint64_t compact_flash_common_base_addr;
+        uint64_t compact_flash_attribute_base_addr;
+        /*
+         * Base address of the LED display (as on EBT3000 board)
+         * This will be 0 if LED display not present.
+         */
+        uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+        /* DFA reference clock in hz (if applicable)*/
+        uint32_t dfa_ref_clock_hz;
+
+        /*
+         * flags indicating various configuration options.  These
+         * flags supercede the 'flags' variable and should be used
+         * instead if available.
+         */
+        uint32_t config_flags;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+        /*
+         * Address of the OF Flattened Device Tree structure
+         * describing the board.
+         */
+        uint64_t fdt_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 4)
+        /*
+         * Coremask used for processors with more than 32 cores
+         * or with OCI.  This replaces core_mask.
+         */
+        struct cvmx_coremask ext_core_mask;
+#endif
+#else                           /* __BIG_ENDIAN */
+        /*
+         * Little-Endian: When the CPU mode is switched to
+         * little-endian, the view of the structure has some of the
+         * fields swapped.
+         */
+        uint32_t minor_version;
+        uint32_t major_version;
+
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        uint64_t desc_vaddr;
+
+        uint32_t stack_size;
+        uint32_t exception_base_addr;
+
+        uint32_t core_mask;
+        uint32_t flags;
+
+        uint32_t phy_mem_desc_addr;
+        uint32_t dram_size;
+
+        uint32_t eclock_hz;
+        uint32_t debugger_flags_base_addr;
+
+        uint32_t reserved0;
+        uint32_t dclock_hz;
+
+        uint8_t reserved3;
+        uint8_t reserved2;
+        uint16_t reserved1;
+        uint8_t board_rev_minor;
+        uint8_t board_rev_major;
+        uint16_t board_type;
+
+        char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+        uint8_t pad[5];
+
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+        uint64_t compact_flash_common_base_addr;
+        uint64_t compact_flash_attribute_base_addr;
+        uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+        uint32_t config_flags;
+        uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+        uint64_t fdt_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 4)
+        struct cvmx_coremask ext_core_mask;
+#endif
+#endif
+};
+
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST                 (1ull << 0)
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET               (1ull << 1)
+#define CVMX_BOOTINFO_CFG_FLAG_DEBUG                    (1ull << 2)
+#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC                 (1ull << 3)
+/* This flag is set if the TLB mappings are not contained in the
+ * 0x10000000 - 0x20000000 boot bus region. */
+#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING     (1ull << 4)
+#define CVMX_BOOTINFO_CFG_FLAG_BREAK                    (1ull << 5)
+
+#endif /*   (CVMX_BOOTINFO_MAJ_VER == 1) */
+
+/* Type defines for board and chip types */
+enum cvmx_board_types_enum {
+        CVMX_BOARD_TYPE_NULL = 0,
+        CVMX_BOARD_TYPE_SIM = 1,
+        CVMX_BOARD_TYPE_EBT3000 = 2,
+        CVMX_BOARD_TYPE_KODAMA = 3,
+        CVMX_BOARD_TYPE_NIAGARA = 4,
+        CVMX_BOARD_TYPE_NAC38 = 5,      /* formerly NAO38 */
+        CVMX_BOARD_TYPE_THUNDER = 6,
+        CVMX_BOARD_TYPE_TRANTOR = 7,
+        CVMX_BOARD_TYPE_EBH3000 = 8,
+        CVMX_BOARD_TYPE_EBH3100 = 9,
+        CVMX_BOARD_TYPE_HIKARI = 10,
+        CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
+        CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
+        CVMX_BOARD_TYPE_KBP = 13,
+        /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
+        CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
+        CVMX_BOARD_TYPE_EBT5800 = 15,
+        CVMX_BOARD_TYPE_NICPRO2 = 16,
+        CVMX_BOARD_TYPE_EBH5600 = 17,
+        CVMX_BOARD_TYPE_EBH5601 = 18,
+        CVMX_BOARD_TYPE_EBH5200 = 19,
+        CVMX_BOARD_TYPE_BBGW_REF = 20,
+        CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
+        CVMX_BOARD_TYPE_EBT5600 = 22,
+        CVMX_BOARD_TYPE_EBH5201 = 23,
+        CVMX_BOARD_TYPE_EBT5200 = 24,
+        CVMX_BOARD_TYPE_CB5600  = 25,
+        CVMX_BOARD_TYPE_CB5601  = 26,
+        CVMX_BOARD_TYPE_CB5200  = 27,
+        /* Special 'generic' board type, supports many boards */
+        CVMX_BOARD_TYPE_GENERIC = 28,
+        CVMX_BOARD_TYPE_EBH5610 = 29,
+        CVMX_BOARD_TYPE_LANAI2_A = 30,
+        CVMX_BOARD_TYPE_LANAI2_U = 31,
+        CVMX_BOARD_TYPE_EBB5600 = 32,
+        CVMX_BOARD_TYPE_EBB6300 = 33,
+        CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
+        CVMX_BOARD_TYPE_LANAI2_G = 35,
+        CVMX_BOARD_TYPE_EBT5810 = 36,
+        CVMX_BOARD_TYPE_NIC10E = 37,
+        CVMX_BOARD_TYPE_EP6300C = 38,
+        CVMX_BOARD_TYPE_EBB6800 = 39,
+        CVMX_BOARD_TYPE_NIC4E = 40,
+        CVMX_BOARD_TYPE_NIC2E = 41,
+        CVMX_BOARD_TYPE_EBB6600 = 42,
+        CVMX_BOARD_TYPE_REDWING = 43,
+        CVMX_BOARD_TYPE_NIC68_4 = 44,
+        CVMX_BOARD_TYPE_NIC10E_66 = 45,
+        CVMX_BOARD_TYPE_MAX,
+
+        /*
+         * The range from CVMX_BOARD_TYPE_MAX to
+         * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
+         * SDK use.
+         */
+
+        /*
+         * Set aside a range for customer boards.  These numbers are managed
+         * by Cavium.
+         */
+        CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
+        CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
+        CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
+        CVMX_BOARD_TYPE_CUST_NB5 = 10003,
+        CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
+        CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
+        CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
+        CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
+        CVMX_BOARD_TYPE_CUST_GST104 = 10008,
+        CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
+        CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
+        CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
+        CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
+        CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
+        CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
+        CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
+        CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
+
+        /*
+         * Set aside a range for customer private use.  The SDK won't
+         * use any numbers in this range.
+         */
+        CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
+        CVMX_BOARD_TYPE_UBNT_E100 = 20002,
+        CVMX_BOARD_TYPE_UBNT_E200 = 20003,
+        CVMX_BOARD_TYPE_UBNT_E220 = 20005,
+        CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
+        CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
+        CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
+
+        /* The remaining range is reserved for future use. */
+};
+
+enum cvmx_chip_types_enum {
+        CVMX_CHIP_TYPE_NULL = 0,
+        CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
+        CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
+        CVMX_CHIP_TYPE_MAX,
+};
+
+/* Compatibility alias for NAC38 name change, planned to be removed
+ * from SDK 1.7 */
+#define CVMX_BOARD_TYPE_NAO38   CVMX_BOARD_TYPE_NAC38
+
+/* Functions to return string based on type */
+#define ENUM_BRD_TYPE_CASE(x) \
+        case x: return (&#x[16]);       /* Skip CVMX_BOARD_TYPE_ */
+static inline const char *cvmx_board_type_to_string(enum
+                                                    cvmx_board_types_enum type)
+{
+        switch (type) {
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
+
+                        /* Customer boards listed here */
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
+
+                    /* Customer private range */
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
+        }
+        return NULL;
+}
+
+#define ENUM_CHIP_TYPE_CASE(x) \
+        case x: return (&#x[15]);       /* Skip CVMX_CHIP_TYPE */
+static inline const char *cvmx_chip_type_to_string(enum
+                                                   cvmx_chip_types_enum type)
+{
+        switch (type) {
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+        }
+        return "Unsupported Chip";
+}
+
+#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
new file mode 100644
index 000000000..689a82cac
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -0,0 +1,341 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Simple allocate only memory allocator.  Used to allocate memory at
+ * application start time.
+ */
+
+#ifndef __CVMX_BOOTMEM_H__
+#define __CVMX_BOOTMEM_H__
+/* Must be multiple of 8, changing breaks ABI */
+#define CVMX_BOOTMEM_NAME_LEN 128
+
+/* Can change without breaking ABI */
+#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
+
+/* minimum alignment of bootmem alloced blocks */
+#define CVMX_BOOTMEM_ALIGNMENT_SIZE     (16ull)
+
+/* Flags for cvmx_bootmem_phy_mem* functions */
+/* Allocate from end of block instead of beginning */
+#define CVMX_BOOTMEM_FLAG_END_ALLOC    (1 << 0)
+
+/* Don't do any locking. */
+#define CVMX_BOOTMEM_FLAG_NO_LOCKING   (1 << 1)
+
+/* First bytes of each free physical block of memory contain this structure,
+ * which is used to maintain the free memory list.  Since the bootloader is
+ * only 32 bits, there is a union providing 64 and 32 bit versions.  The
+ * application init code converts addresses to 64 bit addresses before the
+ * application starts.
+ */
+struct cvmx_bootmem_block_header {
+        /*
+         * Note: these are referenced from assembly routines in the
+         * bootloader, so this structure should not be changed
+         * without changing those routines as well.
+         */
+        uint64_t next_block_addr;
+        uint64_t size;
+
+};
+
+/*
+ * Structure for named memory blocks.  Number of descriptors available
+ * can be changed without affecting compatibility, but name length
+ * changes require a bump in the bootmem descriptor version Note: This
+ * structure must be naturally 64 bit aligned, as a single memory
+ * image will be used by both 32 and 64 bit programs.
+ */
+struct cvmx_bootmem_named_block_desc {
+        /* Base address of named block */
+        uint64_t base_addr;
+        /*
+         * Size actually allocated for named block (may differ from
+         * requested).
+         */
+        uint64_t size;
+        /* name of named block */
+        char name[CVMX_BOOTMEM_NAME_LEN];
+};
+
+/* Current descriptor versions */
+/* CVMX bootmem descriptor major version */
+#define CVMX_BOOTMEM_DESC_MAJ_VER   3
+
+/* CVMX bootmem descriptor minor version */
+#define CVMX_BOOTMEM_DESC_MIN_VER   0
+
+/* First three members of cvmx_bootmem_desc_t are left in original
+ * positions for backwards compatibility.
+ */
+struct cvmx_bootmem_desc {
+#if defined(__BIG_ENDIAN_BITFIELD) || defined(CVMX_BUILD_FOR_LINUX_HOST)
+        /* spinlock to control access to list */
+        uint32_t lock;
+        /* flags for indicating various conditions */
+        uint32_t flags;
+        uint64_t head_addr;
+
+        /* Incremented when incompatible changes made */
+        uint32_t major_version;
+
+        /*
+         * Incremented changed when compatible changes made, reset to
+         * zero when major incremented.
+         */
+        uint32_t minor_version;
+
+        uint64_t app_data_addr;
+        uint64_t app_data_size;
+
+        /* number of elements in named blocks array */
+        uint32_t named_block_num_blocks;
+
+        /* length of name array in bootmem blocks */
+        uint32_t named_block_name_len;
+        /* address of named memory block descriptors */
+        uint64_t named_block_array_addr;
+#else                           /* __LITTLE_ENDIAN */
+        uint32_t flags;
+        uint32_t lock;
+        uint64_t head_addr;
+
+        uint32_t minor_version;
+        uint32_t major_version;
+        uint64_t app_data_addr;
+        uint64_t app_data_size;
+
+        uint32_t named_block_name_len;
+        uint32_t named_block_num_blocks;
+        uint64_t named_block_array_addr;
+#endif
+};
+
+/**
+ * Initialize the boot alloc memory structures. This is
+ * normally called inside of cvmx_user_app_init()
+ *
+ * @mem_desc_ptr:       Address of the free memory list
+ */
+extern int cvmx_bootmem_init(void *mem_desc_ptr);
+
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader at a specific
+ * address. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated at the specified address.
+ *
+ * @size:      Size in bytes of block to allocate
+ * @address:   Physical address to allocate memory at.  If this memory is not
+ *                  available, the allocation fails.
+ * @alignment: Alignment required - must be power of 2
+ * Returns pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
+                                        uint64_t alignment);
+
+/**
+ * Frees a previously allocated named bootmem block.
+ *
+ * @name:   name of block to free
+ *
+ * Returns 0 on failure,
+ *         !0 on success
+ */
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @size:      Size in bytes of block to allocate
+ * @alignment: Alignment required - must be power of 2
+ * @name:      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+                                      char *name);
+
+/**
+ * Allocate a block of memory from a specific range of the free list
+ * that was passed to the application by the bootloader, and assign it
+ * a name in the global named block table.  (part of the
+ * cvmx_bootmem_descriptor_t structure) Named blocks can later be
+ * freed.  If request cannot be satisfied within the address range
+ * specified, NULL is returned
+ *
+ * @size:      Size in bytes of block to allocate
+ * @min_addr:  minimum address of range
+ * @max_addr:  maximum address of range
+ * @align:     Alignment of memory to be allocated. (must be a power of 2)
+ * @name:      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                            uint64_t max_addr, uint64_t align,
+                                            char *name);
+
+/**
+ * Allocate if needed a block of memory from a specific range of the
+ * free list that was passed to the application by the bootloader, and
+ * assign it a name in the global named block table.  (part of the
+ * cvmx_bootmem_descriptor_t structure) Named blocks can later be
+ * freed.  If the requested name block is already allocated, return
+ * the pointer to block of memory.  If request cannot be satisfied
+ * within the address range specified, NULL is returned
+ *
+ * @param size   Size in bytes of block to allocate
+ * @param min_addr  minimum address of range
+ * @param max_addr  maximum address of range
+ * @param align  Alignment of memory to be allocated. (must be a power of 2)
+ * @param name   name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param init   Initialization function
+ *
+ * The initialization function is optional, if omitted the named block
+ * is initialized to all zeros when it is created, i.e. once.
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size,
+                                          uint64_t min_addr,
+                                          uint64_t max_addr,
+                                          uint64_t align,
+                                          char *name,
+                                          void (*init) (void *));
+
+extern int cvmx_bootmem_free_named(char *name);
+
+/**
+ * Finds a named bootmem block by name.
+ *
+ * @name:   name of block to free
+ *
+ * Returns pointer to named block descriptor on success
+ *         0 on failure
+ */
+struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
+
+/**
+ * Allocates a block of physical memory from the free list, at
+ * (optional) requested address and alignment.
+ *
+ * @req_size: size of region to allocate.  All requests are rounded up
+ *            to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ *
+ * @address_min: Minimum address that block can occupy.
+ *
+ * @address_max: Specifies the maximum address_min (inclusive) that
+ *               the allocation can use.
+ *
+ * @alignment: Requested alignment of the block.  If this alignment
+ *             cannot be met, the allocation fails.  This must be a
+ *             power of 2.  (Note: Alignment of
+ *             CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ *             internally enforced.  Requested alignments of less than
+ *             CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ *             CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ *
+ * @flags:     Flags to control options for the allocation.
+ *
+ * Returns physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
+                               uint64_t address_max, uint64_t alignment,
+                               uint32_t flags);
+
+/**
+ * Allocates a named block of physical memory from the free list, at
+ * (optional) requested address and alignment.
+ *
+ * @param size      size of region to allocate.  All requests are rounded
+ *                  up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
+ *                  bytes size
+ * @param min_addr Minimum address that block can occupy.
+ * @param max_addr  Specifies the maximum address_min (inclusive) that
+ *                  the allocation can use.
+ * @param alignment Requested alignment of the block.  If this
+ *                  alignment cannot be met, the allocation fails.
+ *                  This must be a power of 2.  (Note: Alignment of
+ *                  CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ *                  internally enforced.  Requested alignments of less
+ *                  than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ *                  CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name      name to assign to named block
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+                                           uint64_t max_addr,
+                                           uint64_t alignment,
+                                           char *name, uint32_t flags);
+
+/**
+ * Frees a block to the bootmem allocator list.  This must
+ * be used with care, as the size provided must match the size
+ * of the block that was allocated, or the list will become
+ * corrupted.
+ *
+ * IMPORTANT:  This is only intended to be used as part of named block
+ * frees and initial population of the free memory list.
+ *                                                      *
+ *
+ * @phy_addr: physical address of block
+ * @size:     size of block in bytes.
+ * @flags:    flags for passing options
+ *
+ * Returns 1 on success,
+ *         0 on failure
+ */
+int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
+
+/**
+ * Locks the bootmem allocator.  This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_lock(void);
+
+/**
+ * Unlocks the bootmem allocator.  This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_unlock(void);
+
+extern struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void);
+
+#endif /*   __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
new file mode 100644
index 000000000..1d18be8cd
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Octeon CIU definitions
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ */
+
+#ifndef __CVMX_CIU_DEFS_H__
+#define __CVMX_CIU_DEFS_H__
+
+#include <asm/bitfield.h>
+
+#define CVMX_CIU_ADDR(addr, coreid, coremask, offset)                          \
+        (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) +                  \
+        (((coreid) & (coremask)) * offset))
+
+#define CVMX_CIU_EN2_PPX_IP4(c)         CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
+#define CVMX_CIU_EN2_PPX_IP4_W1C(c)     CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
+#define CVMX_CIU_EN2_PPX_IP4_W1S(c)     CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
+#define CVMX_CIU_FUSE                   CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
+#define CVMX_CIU_INT_SUM1               CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
+#define CVMX_CIU_INTX_EN0(c)            CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
+#define CVMX_CIU_INTX_EN0_W1C(c)        CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
+#define CVMX_CIU_INTX_EN0_W1S(c)        CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
+#define CVMX_CIU_INTX_EN1(c)            CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
+#define CVMX_CIU_INTX_EN1_W1C(c)        CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
+#define CVMX_CIU_INTX_EN1_W1S(c)        CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
+#define CVMX_CIU_INTX_SUM0(c)           CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
+#define CVMX_CIU_NMI                    CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
+#define CVMX_CIU_PCI_INTA               CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
+#define CVMX_CIU_PP_BIST_STAT           CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
+#define CVMX_CIU_PP_DBG                 CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
+#define CVMX_CIU_PP_RST                 CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
+#define CVMX_CIU_QLM0                   CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
+#define CVMX_CIU_QLM1                   CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
+#define CVMX_CIU_QLM_JTGC               CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
+#define CVMX_CIU_QLM_JTGD               CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
+#define CVMX_CIU_SOFT_BIST              CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
+#define CVMX_CIU_SOFT_PRST1             CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
+#define CVMX_CIU_SOFT_PRST              CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
+#define CVMX_CIU_SOFT_RST               CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
+#define CVMX_CIU_SUM2_PPX_IP4(c)        CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
+#define CVMX_CIU_TIM_MULTI_CAST         CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
+#define CVMX_CIU_TIMX(c)                CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
+
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned int coreid)
+{
+        if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
+                return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8);
+        else
+                return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8);
+}
+
+static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned int coreid)
+{
+        if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
+                return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8);
+        else
+                return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8);
+}
+
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned int coreid)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8);
+        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+                return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) -
+                        0x60000000000ull;
+        default:
+                return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8);
+        }
+}
+
+static inline uint64_t CVMX_CIU_WDOGX(unsigned int coreid)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8);
+        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+                return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) -
+                        0x60000000000ull;
+        default:
+                return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8);
+        }
+}
+
+
+union cvmx_ciu_qlm {
+        uint64_t u64;
+        struct cvmx_ciu_qlm_s {
+                __BITFIELD_FIELD(uint64_t g2bypass:1,
+                __BITFIELD_FIELD(uint64_t reserved_53_62:10,
+                __BITFIELD_FIELD(uint64_t g2deemph:5,
+                __BITFIELD_FIELD(uint64_t reserved_45_47:3,
+                __BITFIELD_FIELD(uint64_t g2margin:5,
+                __BITFIELD_FIELD(uint64_t reserved_32_39:8,
+                __BITFIELD_FIELD(uint64_t txbypass:1,
+                __BITFIELD_FIELD(uint64_t reserved_21_30:10,
+                __BITFIELD_FIELD(uint64_t txdeemph:5,
+                __BITFIELD_FIELD(uint64_t reserved_13_15:3,
+                __BITFIELD_FIELD(uint64_t txmargin:5,
+                __BITFIELD_FIELD(uint64_t reserved_4_7:4,
+                __BITFIELD_FIELD(uint64_t lane_en:4,
+                ;)))))))))))))
+        } s;
+};
+
+union cvmx_ciu_qlm_jtgc {
+        uint64_t u64;
+        struct cvmx_ciu_qlm_jtgc_s {
+                __BITFIELD_FIELD(uint64_t reserved_17_63:47,
+                __BITFIELD_FIELD(uint64_t bypass_ext:1,
+                __BITFIELD_FIELD(uint64_t reserved_11_15:5,
+                __BITFIELD_FIELD(uint64_t clk_div:3,
+                __BITFIELD_FIELD(uint64_t reserved_7_7:1,
+                __BITFIELD_FIELD(uint64_t mux_sel:3,
+                __BITFIELD_FIELD(uint64_t bypass:4,
+                ;)))))))
+        } s;
+};
+
+union cvmx_ciu_qlm_jtgd {
+        uint64_t u64;
+        struct cvmx_ciu_qlm_jtgd_s {
+                __BITFIELD_FIELD(uint64_t capture:1,
+                __BITFIELD_FIELD(uint64_t shift:1,
+                __BITFIELD_FIELD(uint64_t update:1,
+                __BITFIELD_FIELD(uint64_t reserved_45_60:16,
+                __BITFIELD_FIELD(uint64_t select:5,
+                __BITFIELD_FIELD(uint64_t reserved_37_39:3,
+                __BITFIELD_FIELD(uint64_t shft_cnt:5,
+                __BITFIELD_FIELD(uint64_t shft_reg:32,
+                ;))))))))
+        } s;
+};
+
+union cvmx_ciu_soft_prst {
+        uint64_t u64;
+        struct cvmx_ciu_soft_prst_s {
+                __BITFIELD_FIELD(uint64_t reserved_3_63:61,
+                __BITFIELD_FIELD(uint64_t host64:1,
+                __BITFIELD_FIELD(uint64_t npi:1,
+                __BITFIELD_FIELD(uint64_t soft_prst:1,
+                ;))))
+        } s;
+};
+
+union cvmx_ciu_timx {
+        uint64_t u64;
+        struct cvmx_ciu_timx_s {
+                __BITFIELD_FIELD(uint64_t reserved_37_63:27,
+                __BITFIELD_FIELD(uint64_t one_shot:1,
+                __BITFIELD_FIELD(uint64_t len:36,
+                ;)))
+        } s;
+};
+
+union cvmx_ciu_wdogx {
+        uint64_t u64;
+        struct cvmx_ciu_wdogx_s {
+                __BITFIELD_FIELD(uint64_t reserved_46_63:18,
+                __BITFIELD_FIELD(uint64_t gstopen:1,
+                __BITFIELD_FIELD(uint64_t dstop:1,
+                __BITFIELD_FIELD(uint64_t cnt:24,
+                __BITFIELD_FIELD(uint64_t len:16,
+                __BITFIELD_FIELD(uint64_t state:2,
+                __BITFIELD_FIELD(uint64_t mode:2,
+                ;)))))))
+        } s;
+};
+
+#endif /* __CVMX_CIU_DEFS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
new file mode 100644
index 000000000..5babd88d4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
@@ -0,0 +1,48 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_CIU2_DEFS_H__
+#define __CVMX_CIU2_DEFS_H__
+
+#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
+#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
+#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
+#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu3-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
new file mode 100644
index 000000000..547f778f5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2003-2016 Cavium Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ */
+
+#ifndef __CVMX_CIU3_DEFS_H__
+#define __CVMX_CIU3_DEFS_H__
+
+#define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull)
+#define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull)
+#define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull)
+#define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull)
+#define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8)
+#define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8)
+#define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull)
+#define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8)
+#define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8)
+#define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull)
+#define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull)
+#define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull)
+#define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull)
+#define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull)
+#define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8)
+#define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8)
+#define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8)
+#define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull)
+#define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8)
+#define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8)
+
+union cvmx_ciu3_bist {
+        uint64_t u64;
+        struct cvmx_ciu3_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_9_63                : 55;
+        uint64_t bist                         : 9;
+#else
+        uint64_t bist                         : 9;
+        uint64_t reserved_9_63                : 55;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_const {
+        uint64_t u64;
+        struct cvmx_ciu3_const_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t dests_io                     : 16;
+        uint64_t pintsn                       : 16;
+        uint64_t dests_pp                     : 16;
+        uint64_t idt                          : 16;
+#else
+        uint64_t idt                          : 16;
+        uint64_t dests_pp                     : 16;
+        uint64_t pintsn                       : 16;
+        uint64_t dests_io                     : 16;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_ctl {
+        uint64_t u64;
+        struct cvmx_ciu3_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_5_63                : 59;
+        uint64_t mcd_sel                      : 2;
+        uint64_t iscmem_le                    : 1;
+        uint64_t seq_dis                      : 1;
+        uint64_t cclk_dis                     : 1;
+#else
+        uint64_t cclk_dis                     : 1;
+        uint64_t seq_dis                      : 1;
+        uint64_t iscmem_le                    : 1;
+        uint64_t mcd_sel                      : 2;
+        uint64_t reserved_5_63                : 59;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_destx_io_int {
+        uint64_t u64;
+        struct cvmx_ciu3_destx_io_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_52_63               : 12;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_10_31               : 22;
+        uint64_t intidt                       : 8;
+        uint64_t newint                       : 1;
+        uint64_t intr                         : 1;
+#else
+        uint64_t intr                         : 1;
+        uint64_t newint                       : 1;
+        uint64_t intidt                       : 8;
+        uint64_t reserved_10_31               : 22;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_52_63               : 12;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_destx_pp_int {
+        uint64_t u64;
+        struct cvmx_ciu3_destx_pp_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_52_63               : 12;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_10_31               : 22;
+        uint64_t intidt                       : 8;
+        uint64_t newint                       : 1;
+        uint64_t intr                         : 1;
+#else
+        uint64_t intr                         : 1;
+        uint64_t newint                       : 1;
+        uint64_t intidt                       : 8;
+        uint64_t reserved_10_31               : 22;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_52_63               : 12;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_gstop {
+        uint64_t u64;
+        struct cvmx_ciu3_gstop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_1_63                : 63;
+        uint64_t gstop                        : 1;
+#else
+        uint64_t gstop                        : 1;
+        uint64_t reserved_1_63                : 63;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_idtx_ctl {
+        uint64_t u64;
+        struct cvmx_ciu3_idtx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_52_63               : 12;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_4_31                : 28;
+        uint64_t intr                         : 1;
+        uint64_t newint                       : 1;
+        uint64_t ip_num                       : 2;
+#else
+        uint64_t ip_num                       : 2;
+        uint64_t newint                       : 1;
+        uint64_t intr                         : 1;
+        uint64_t reserved_4_31                : 28;
+        uint64_t intsn                        : 20;
+        uint64_t reserved_52_63               : 12;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_idtx_io {
+        uint64_t u64;
+        struct cvmx_ciu3_idtx_io_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_5_63                : 59;
+        uint64_t io                           : 5;
+#else
+        uint64_t io                           : 5;
+        uint64_t reserved_5_63                : 59;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_idtx_ppx {
+        uint64_t u64;
+        struct cvmx_ciu3_idtx_ppx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_48_63               : 16;
+        uint64_t pp                           : 48;
+#else
+        uint64_t pp                           : 48;
+        uint64_t reserved_48_63               : 16;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_intr_ram_ecc_ctl {
+        uint64_t u64;
+        struct cvmx_ciu3_intr_ram_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_3_63                : 61;
+        uint64_t flip_synd                    : 2;
+        uint64_t ecc_ena                      : 1;
+#else
+        uint64_t ecc_ena                      : 1;
+        uint64_t flip_synd                    : 2;
+        uint64_t reserved_3_63                : 61;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_intr_ram_ecc_st {
+        uint64_t u64;
+        struct cvmx_ciu3_intr_ram_ecc_st_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_52_63               : 12;
+        uint64_t addr                         : 20;
+        uint64_t reserved_6_31                : 26;
+        uint64_t sisc_dbe                     : 1;
+        uint64_t sisc_sbe                     : 1;
+        uint64_t idt_dbe                      : 1;
+        uint64_t idt_sbe                      : 1;
+        uint64_t isc_dbe                      : 1;
+        uint64_t isc_sbe                      : 1;
+#else
+        uint64_t isc_sbe                      : 1;
+        uint64_t isc_dbe                      : 1;
+        uint64_t idt_sbe                      : 1;
+        uint64_t idt_dbe                      : 1;
+        uint64_t sisc_sbe                     : 1;
+        uint64_t sisc_dbe                     : 1;
+        uint64_t reserved_6_31                : 26;
+        uint64_t addr                         : 20;
+        uint64_t reserved_52_63               : 12;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_intr_ready {
+        uint64_t u64;
+        struct cvmx_ciu3_intr_ready_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_46_63               : 18;
+        uint64_t index                        : 14;
+        uint64_t reserved_1_31                : 31;
+        uint64_t ready                        : 1;
+#else
+        uint64_t ready                        : 1;
+        uint64_t reserved_1_31                : 31;
+        uint64_t index                        : 14;
+        uint64_t reserved_46_63               : 18;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_intr_slowdown {
+        uint64_t u64;
+        struct cvmx_ciu3_intr_slowdown_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_3_63                : 61;
+        uint64_t ctl                          : 3;
+#else
+        uint64_t ctl                          : 3;
+        uint64_t reserved_3_63                : 61;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_iscx_ctl {
+        uint64_t u64;
+        struct cvmx_ciu3_iscx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_24_63               : 40;
+        uint64_t idt                          : 8;
+        uint64_t imp                          : 1;
+        uint64_t reserved_2_14                : 13;
+        uint64_t en                           : 1;
+        uint64_t raw                          : 1;
+#else
+        uint64_t raw                          : 1;
+        uint64_t en                           : 1;
+        uint64_t reserved_2_14                : 13;
+        uint64_t imp                          : 1;
+        uint64_t idt                          : 8;
+        uint64_t reserved_24_63               : 40;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_iscx_w1c {
+        uint64_t u64;
+        struct cvmx_ciu3_iscx_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_2_63                : 62;
+        uint64_t en                           : 1;
+        uint64_t raw                          : 1;
+#else
+        uint64_t raw                          : 1;
+        uint64_t en                           : 1;
+        uint64_t reserved_2_63                : 62;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_iscx_w1s {
+        uint64_t u64;
+        struct cvmx_ciu3_iscx_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_2_63                : 62;
+        uint64_t en                           : 1;
+        uint64_t raw                          : 1;
+#else
+        uint64_t raw                          : 1;
+        uint64_t en                           : 1;
+        uint64_t reserved_2_63                : 62;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_nmi {
+        uint64_t u64;
+        struct cvmx_ciu3_nmi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_48_63               : 16;
+        uint64_t nmi                          : 48;
+#else
+        uint64_t nmi                          : 48;
+        uint64_t reserved_48_63               : 16;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_siscx {
+        uint64_t u64;
+        struct cvmx_ciu3_siscx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t en                           : 64;
+#else
+        uint64_t en                           : 64;
+#endif
+        } s;
+};
+
+union cvmx_ciu3_timx {
+        uint64_t u64;
+        struct cvmx_ciu3_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+        uint64_t reserved_37_63               : 27;
+        uint64_t one_shot                     : 1;
+        uint64_t len                          : 36;
+#else
+        uint64_t len                          : 36;
+        uint64_t one_shot                     : 1;
+        uint64_t reserved_37_63               : 27;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
new file mode 100644
index 000000000..a07a36f7d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -0,0 +1,619 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Support functions for managing command queues used for
+ * various hardware blocks.
+ *
+ * The common command queue infrastructure abstracts out the
+ * software necessary for adding to Octeon's chained queue
+ * structures. These structures are used for commands to the
+ * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
+ * hardware unit takes commands and CSRs of different types,
+ * they all use basic linked command buffers to store the
+ * pending request. In general, users of the CVMX API don't
+ * call cvmx-cmd-queue functions directly. Instead the hardware
+ * unit specific wrapper should be used. The wrappers perform
+ * unit specific validation and CSR writes to submit the
+ * commands.
+ *
+ * Even though most software will never directly interact with
+ * cvmx-cmd-queue, knowledge of its internal working can help
+ * in diagnosing performance problems and help with debugging.
+ *
+ * Command queue pointers are stored in a global named block
+ * called "cvmx_cmd_queues". Except for the PKO queues, each
+ * hardware queue is stored in its own cache line to reduce SMP
+ * contention on spin locks. The PKO queues are stored such that
+ * every 16th queue is next to each other in memory. This scheme
+ * allows for queues being in separate cache lines when there
+ * are low number of queues per port. With 16 queues per port,
+ * the first queue for each port is in the same cache area. The
+ * second queues for each port are in another area, etc. This
+ * allows software to implement very efficient lockless PKO with
+ * 16 queues per port using a minimum of cache lines per core.
+ * All queues for a given core will be isolated in the same
+ * cache area.
+ *
+ * In addition to the memory pointer layout, cvmx-cmd-queue
+ * provides an optimized fair ll/sc locking mechanism for the
+ * queues. The lock uses a "ticket / now serving" model to
+ * maintain fair order on contended locks. In addition, it uses
+ * predicted locking time to limit cache contention. When a core
+ * know it must wait in line for a lock, it spins on the
+ * internal cycle counter to completely eliminate any causes of
+ * bus traffic.
+ *
+ */
+
+#ifndef __CVMX_CMD_QUEUE_H__
+#define __CVMX_CMD_QUEUE_H__
+
+#include <linux/prefetch.h>
+
+#include <asm/compiler.h>
+
+#include <asm/octeon/cvmx-fpa.h>
+/**
+ * By default we disable the max depth support. Most programs
+ * don't use it and it slows down the command queue processing
+ * significantly.
+ */
+#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
+#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
+#endif
+
+/**
+ * Enumeration representing all hardware blocks that use command
+ * queues. Each hardware block has up to 65536 sub identifiers for
+ * multiple command queues. Not all chips support all hardware
+ * units.
+ */
+typedef enum {
+        CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
+
+#define CVMX_CMD_QUEUE_PKO(queue) \
+        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
+
+        CVMX_CMD_QUEUE_ZIP = 0x10000,
+        CVMX_CMD_QUEUE_DFA = 0x20000,
+        CVMX_CMD_QUEUE_RAID = 0x30000,
+        CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
+
+#define CVMX_CMD_QUEUE_DMA(queue) \
+        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
+
+        CVMX_CMD_QUEUE_END = 0x50000,
+} cvmx_cmd_queue_id_t;
+
+/**
+ * Command write operations can fail if the command queue needs
+ * a new buffer and the associated FPA pool is empty. It can also
+ * fail if the number of queued command words reaches the maximum
+ * set at initialization.
+ */
+typedef enum {
+        CVMX_CMD_QUEUE_SUCCESS = 0,
+        CVMX_CMD_QUEUE_NO_MEMORY = -1,
+        CVMX_CMD_QUEUE_FULL = -2,
+        CVMX_CMD_QUEUE_INVALID_PARAM = -3,
+        CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
+} cvmx_cmd_queue_result_t;
+
+typedef struct {
+        /* You have lock when this is your ticket */
+        uint8_t now_serving;
+        uint64_t unused1:24;
+        /* Maximum outstanding command words */
+        uint32_t max_depth;
+        /* FPA pool buffers come from */
+        uint64_t fpa_pool:3;
+        /* Top of command buffer pointer shifted 7 */
+        uint64_t base_ptr_div128:29;
+        uint64_t unused2:6;
+        /* FPA buffer size in 64bit words minus 1 */
+        uint64_t pool_size_m1:13;
+        /* Number of commands already used in buffer */
+        uint64_t index:13;
+} __cvmx_cmd_queue_state_t;
+
+/**
+ * This structure contains the global state of all command queues.
+ * It is stored in a bootmem named block and shared by all
+ * applications running on Octeon. Tickets are stored in a differnet
+ * cache line that queue information to reduce the contention on the
+ * ll/sc used to get a ticket. If this is not the case, the update
+ * of queue state causes the ll/sc to fail quite often.
+ */
+typedef struct {
+        uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256];
+        __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
+} __cvmx_cmd_queue_all_state_t;
+
+/**
+ * Initialize a command queue for use. The initial FPA buffer is
+ * allocated and the hardware unit is configured to point to the
+ * new command queue.
+ *
+ * @queue_id:  Hardware command queue to initialize.
+ * @max_depth: Maximum outstanding commands that can be queued.
+ * @fpa_pool:  FPA pool the command queues should come from.
+ * @pool_size: Size of each buffer in the FPA pool (bytes)
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
+                                                  int max_depth, int fpa_pool,
+                                                  int pool_size);
+
+/**
+ * Shutdown a queue a free it's command buffers to the FPA. The
+ * hardware connected to the queue must be stopped before this
+ * function is called.
+ *
+ * @queue_id: Queue to shutdown
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the number of command words pending in the queue. This
+ * function may be relatively slow for some hardware units.
+ *
+ * @queue_id: Hardware command queue to query
+ *
+ * Returns Number of outstanding commands
+ */
+int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the command buffer to be written to. The purpose of this
+ * function is to allow CVMX routine access t othe low level buffer
+ * for initial hardware setup. User applications should not call this
+ * function directly.
+ *
+ * @queue_id: Command queue to query
+ *
+ * Returns Command buffer or NULL on failure
+ */
+void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Get the index into the state arrays for the supplied queue id.
+ *
+ * @queue_id: Queue ID to get an index for
+ *
+ * Returns Index into the state arrays
+ */
+static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
+{
+        /*
+         * Warning: This code currently only works with devices that
+         * have 256 queues or less. Devices with more than 16 queues
+         * are laid out in memory to allow cores quick access to
+         * every 16th queue. This reduces cache thrashing when you are
+         * running 16 queues per port to support lockless operation.
+         */
+        int unit = queue_id >> 16;
+        int q = (queue_id >> 4) & 0xf;
+        int core = queue_id & 0xf;
+        return unit * 256 + core * 16 + q;
+}
+
+/**
+ * Lock the supplied queue so nobody else is updating it at the same
+ * time as us.
+ *
+ * @queue_id: Queue ID to lock
+ * @qptr:     Pointer to the queue's global state
+ */
+static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
+                                         __cvmx_cmd_queue_state_t *qptr)
+{
+        extern __cvmx_cmd_queue_all_state_t
+            *__cvmx_cmd_queue_state_ptr;
+        int tmp;
+        int my_ticket;
+        prefetch(qptr);
+        asm volatile (
+                ".set push\n"
+                ".set noreorder\n"
+                "1:\n"
+                /* Atomic add one to ticket_ptr */
+                "ll     %[my_ticket], %[ticket_ptr]\n"
+                /* and store the original value */
+                "li     %[ticket], 1\n"
+                /* in my_ticket */
+                "baddu  %[ticket], %[my_ticket]\n"
+                "sc     %[ticket], %[ticket_ptr]\n"
+                "beqz   %[ticket], 1b\n"
+                " nop\n"
+                /* Load the current now_serving ticket */
+                "lbu    %[ticket], %[now_serving]\n"
+                "2:\n"
+                /* Jump out if now_serving == my_ticket */
+                "beq    %[ticket], %[my_ticket], 4f\n"
+                /* Find out how many tickets are in front of me */
+                " subu   %[ticket], %[my_ticket], %[ticket]\n"
+                /* Use tickets in front of me minus one to delay */
+                "subu  %[ticket], 1\n"
+                /* Delay will be ((tickets in front)-1)*32 loops */
+                "cins   %[ticket], %[ticket], 5, 7\n"
+                "3:\n"
+                /* Loop here until our ticket might be up */
+                "bnez   %[ticket], 3b\n"
+                " subu  %[ticket], 1\n"
+                /* Jump back up to check out ticket again */
+                "b      2b\n"
+                /* Load the current now_serving ticket */
+                " lbu   %[ticket], %[now_serving]\n"
+                "4:\n"
+                ".set pop\n" :
+                [ticket_ptr] "=" GCC_OFF_SMALL_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
+                [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
+                [my_ticket] "=r"(my_ticket)
+            );
+}
+
+/**
+ * Unlock the queue, flushing all writes.
+ *
+ * @qptr:   Queue to unlock
+ */
+static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
+{
+        qptr->now_serving++;
+        CVMX_SYNCWS;
+}
+
+/**
+ * Get the queue state structure for the given queue id
+ *
+ * @queue_id: Queue id to get
+ *
+ * Returns Queue structure or NULL on failure
+ */
+static inline __cvmx_cmd_queue_state_t
+    *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
+{
+        extern __cvmx_cmd_queue_all_state_t
+            *__cvmx_cmd_queue_state_ptr;
+        return &__cvmx_cmd_queue_state_ptr->
+            state[__cvmx_cmd_queue_get_index(queue_id)];
+}
+
+/**
+ * Write an arbitrary number of command words to a command queue.
+ * This is a generic function; the fixed number of command word
+ * functions yield higher performance.
+ *
+ * @queue_id:  Hardware command queue to write to
+ * @use_locking:
+ *                  Use internal locking to ensure exclusive access for queue
+ *                  updates. If you don't use this locking you must ensure
+ *                  exclusivity some other way. Locking is strongly recommended.
+ * @cmd_count: Number of command words to write
+ * @cmds:      Array of commands to write
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
+                                                           queue_id,
+                                                           int use_locking,
+                                                           int cmd_count,
+                                                           uint64_t *cmds)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += cmd_count;
+                while (cmd_count--)
+                        *ptr++ = *cmds++;
+        } else {
+                uint64_t *ptr;
+                int count;
+                /*
+                 * We need a new command buffer. Fail if there isn't
+                 * one available.
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer.
+                 */
+                count = qptr->pool_size_m1 - qptr->index;
+                ptr += qptr->index;
+                cmd_count -= count;
+                while (count--)
+                        *ptr++ = *cmds++;
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = cmd_count;
+                ptr = new_buffer;
+                while (cmd_count--)
+                        *ptr++ = *cmds++;
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Simple function to write two command words to a command
+ * queue.
+ *
+ * @queue_id: Hardware command queue to write to
+ * @use_locking:
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @cmd1:     Command
+ * @cmd2:     Command
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
+                                                            queue_id,
+                                                            int use_locking,
+                                                            uint64_t cmd1,
+                                                            uint64_t cmd2)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + 2 < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += 2;
+                ptr[0] = cmd1;
+                ptr[1] = cmd2;
+        } else {
+                uint64_t *ptr;
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer.
+                 */
+                int count = qptr->pool_size_m1 - qptr->index;
+                /*
+                 * We need a new command buffer. Fail if there isn't
+                 * one available.
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                count--;
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                *ptr++ = cmd1;
+                if (likely(count))
+                        *ptr++ = cmd2;
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = 0;
+                if (unlikely(count == 0)) {
+                        qptr->index = 1;
+                        new_buffer[0] = cmd2;
+                }
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Simple function to write three command words to a command
+ * queue.
+ *
+ * @queue_id: Hardware command queue to write to
+ * @use_locking:
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @cmd1:     Command
+ * @cmd2:     Command
+ * @cmd3:     Command
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
+                                                            queue_id,
+                                                            int use_locking,
+                                                            uint64_t cmd1,
+                                                            uint64_t cmd2,
+                                                            uint64_t cmd3)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + 3 < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += 3;
+                ptr[0] = cmd1;
+                ptr[1] = cmd2;
+                ptr[2] = cmd3;
+        } else {
+                uint64_t *ptr;
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer
+                 */
+                int count = qptr->pool_size_m1 - qptr->index;
+                /*
+                 * We need a new command buffer. Fail if there isn't
+                 * one available
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                count--;
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                *ptr++ = cmd1;
+                if (count) {
+                        *ptr++ = cmd2;
+                        if (count > 1)
+                                *ptr++ = cmd3;
+                }
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = 0;
+                ptr = new_buffer;
+                if (count == 0) {
+                        *ptr++ = cmd2;
+                        qptr->index++;
+                }
+                if (count < 2) {
+                        *ptr++ = cmd3;
+                        qptr->index++;
+                }
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
new file mode 100644
index 000000000..a8c358c02
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CVMX_CONFIG_H__
+#define __CVMX_CONFIG_H__
+
+/************************* Config Specific Defines ************************/
+#define CVMX_LLM_NUM_PORTS 1
+#define CVMX_NULL_POINTER_PROTECT 1
+#define CVMX_ENABLE_DEBUG_PRINTS 1
+/* PKO queues per port for interface 0 (ports 0-15) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
+/* PKO queues per port for interface 1 (ports 16-31) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
+/* Limit on the number of PKO ports enabled for interface 0 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+/* Limit on the number of PKO ports enabled for interface 1 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+/* PKO queues per port for PCI (ports 32-35) */
+#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
+/* PKO queues per port for Loop devices (ports 36-39) */
+#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
+
+/************************* FPA allocation *********************************/
+/* Pool sizes in bytes, must be multiple of a cache line */
+#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+
+/* Pools in use */
+/* Packet buffers */
+#define CVMX_FPA_PACKET_POOL                (0)
+#define CVMX_FPA_PACKET_POOL_SIZE           CVMX_FPA_POOL_0_SIZE
+/* Work queue entries */
+#define CVMX_FPA_WQE_POOL                   (1)
+#define CVMX_FPA_WQE_POOL_SIZE              CVMX_FPA_POOL_1_SIZE
+/* PKO queue command buffers */
+#define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
+#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
+
+/*************************  FAU allocation ********************************/
+/* The fetch and add registers are allocated here.  They are arranged
+ * in order of descending size so that all alignment constraints are
+ * automatically met.  The enums are linked so that the following enum
+ * continues allocating where the previous one left off, so the
+ * numbering within each enum always starts with zero.  The macros
+ * take care of the address increment size, so the values entered
+ * always increase by 1.  FAU registers are accessed with byte
+ * addresses.
+ */
+
+#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
+typedef enum {
+        CVMX_FAU_REG_64_START   = 0,
+        CVMX_FAU_REG_64_END     = CVMX_FAU_REG_64_ADDR(0),
+} cvmx_fau_reg_64_t;
+
+#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
+typedef enum {
+        CVMX_FAU_REG_32_START   = CVMX_FAU_REG_64_END,
+        CVMX_FAU_REG_32_END     = CVMX_FAU_REG_32_ADDR(0),
+} cvmx_fau_reg_32_t;
+
+#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
+typedef enum {
+        CVMX_FAU_REG_16_START   = CVMX_FAU_REG_32_END,
+        CVMX_FAU_REG_16_END     = CVMX_FAU_REG_16_ADDR(0),
+} cvmx_fau_reg_16_t;
+
+#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
+typedef enum {
+        CVMX_FAU_REG_8_START    = CVMX_FAU_REG_16_END,
+        CVMX_FAU_REG_8_END      = CVMX_FAU_REG_8_ADDR(0),
+} cvmx_fau_reg_8_t;
+
+/*
+ * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
+ * available FAU address that is not allocated in cvmx-config.h. This
+ * is 64 bit aligned.
+ */
+#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
+#define CVMX_FAU_REG_END (2048)
+
+/********************** scratch memory allocation *************************/
+/* Scratchpad memory allocation.  Note that these are byte memory
+ * addresses.  Some uses of scratchpad (IOBDMA for example) require
+ * the use of 8-byte aligned addresses, so proper alignment needs to
+ * be taken into account.
+ */
+/* Generic scratch iobdma area */
+#define CVMX_SCR_SCRATCH               (0)
+/* First location available after cvmx-config.h allocated region. */
+#define CVMX_SCR_REG_AVAIL_BASE        (8)
+
+/*
+ * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
+ * before the beginning of the packet. If necessary, override the
+ * default here.  See the IPD section of the hardware manual for MBUFF
+ * SKIP details.
+ */
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+
+/*
+ * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
+ * in each chained packet element. If necessary, override the default
+ * here.
+ */
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+
+/*
+ * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
+ * enabled for all input ports. This controls if IPD sends
+ * backpressure to all ports if Octeon's FPA pools don't have enough
+ * packet or work queue entries. Even when this is off, it is still
+ * possible to get backpressure from individual hardware ports. When
+ * configuring backpressure, also check
+ * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
+ * the default here.
+ */
+#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
+
+/*
+ * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+ * function. Once it is enabled the hardware starts accepting
+ * packets. You might want to skip the IPD enable if configuration
+ * changes are need from the default helper setup. If necessary,
+ * override the default here.
+ */
+#define CVMX_HELPER_ENABLE_IPD 0
+
+/*
+ * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
+ * to incoming packets.
+ */
+#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+
+#define CVMX_ENABLE_PARAMETER_CHECKING 0
+
+/*
+ * The following select which fields are used by the PIP to generate
+ * the tag on INPUT
+ * 0: don't include
+ * 1: include
+ */
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER  0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL     0
+#define CVMX_HELPER_INPUT_TAG_INPUT_PORT        1
+
+/* Select skip mode for input ports */
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE        CVMX_PIP_PORT_CFG_MODE_SKIPL2
+
+/*
+ * Force backpressure to be disabled.  This overrides all other
+ * backpressure configuration.
+ */
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
+
+#endif /* __CVMX_CONFIG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-coremask.h b/arch/mips/include/asm/octeon/cvmx-coremask.h
new file mode 100644
index 000000000..097dc096d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-coremask.h
@@ -0,0 +1,89 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2016  Cavium Inc. (support@cavium.com).
+ *
+ */
+
+/*
+ * Module to support operations on bitmap of cores. Coremask can be used to
+ * select a specific core, a group of cores, or all available cores, for
+ * initialization and differentiation of roles within a single shared binary
+ * executable image.
+ *
+ * The core numbers used in this file are the same value as what is found in
+ * the COP0_EBASE register and the rdhwr 0 instruction.
+ *
+ * For the CN78XX and other multi-node environments the core numbers are not
+ * contiguous.  The core numbers for the CN78XX are as follows:
+ *
+ * Node 0:      Cores 0 - 47
+ * Node 1:      Cores 128 - 175
+ * Node 2:      Cores 256 - 303
+ * Node 3:      Cores 384 - 431
+ *
+ */
+
+#ifndef __CVMX_COREMASK_H__
+#define __CVMX_COREMASK_H__
+
+#define CVMX_MIPS_MAX_CORES 1024
+/* bits per holder */
+#define CVMX_COREMASK_ELTSZ 64
+
+/* cvmx_coremask_t's size in u64 */
+#define CVMX_COREMASK_BMPSZ (CVMX_MIPS_MAX_CORES / CVMX_COREMASK_ELTSZ)
+
+
+/* cvmx_coremask_t */
+struct cvmx_coremask {
+        u64 coremask_bitmap[CVMX_COREMASK_BMPSZ];
+};
+
+/*
+ * Is ``core'' set in the coremask?
+ */
+static inline bool cvmx_coremask_is_core_set(const struct cvmx_coremask *pcm,
+                                            int core)
+{
+        int n, i;
+
+        n = core % CVMX_COREMASK_ELTSZ;
+        i = core / CVMX_COREMASK_ELTSZ;
+
+        return (pcm->coremask_bitmap[i] & ((u64)1 << n)) != 0;
+}
+
+/*
+ * Make a copy of a coremask
+ */
+static inline void cvmx_coremask_copy(struct cvmx_coremask *dest,
+                                      const struct cvmx_coremask *src)
+{
+        memcpy(dest, src, sizeof(*dest));
+}
+
+/*
+ * Set the lower 64-bit of the coremask.
+ */
+static inline void cvmx_coremask_set64(struct cvmx_coremask *pcm,
+                                       uint64_t coremask_64)
+{
+        pcm->coremask_bitmap[0] = coremask_64;
+}
+
+/*
+ * Clear ``core'' from the coremask.
+ */
+static inline void cvmx_coremask_clear_core(struct cvmx_coremask *pcm, int core)
+{
+        int n, i;
+
+        n = core % CVMX_COREMASK_ELTSZ;
+        i = core / CVMX_COREMASK_ELTSZ;
+        pcm->coremask_bitmap[i] &= ~(1ull << n);
+}
+
+#endif /* __CVMX_COREMASK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
new file mode 100644
index 000000000..828d07d87
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
@@ -0,0 +1,101 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DBG_DEFS_H__
+#define __CVMX_DBG_DEFS_H__
+
+#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
+
+union cvmx_dbg_data {
+        uint64_t u64;
+        struct cvmx_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_dbg_data_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t pll_mul:3;
+                uint64_t reserved_23_27:5;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t reserved_23_27:5;
+                uint64_t pll_mul:3;
+                uint64_t reserved_31_63:33;
+#endif
+        } cn30xx;
+        struct cvmx_dbg_data_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t d_mul:4;
+                uint64_t dclk_mul2:1;
+                uint64_t cclk_div2:1;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t cclk_div2:1;
+                uint64_t dclk_mul2:1;
+                uint64_t d_mul:4;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn38xx;
+        struct cvmx_dbg_data_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t rem:6;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t rem:6;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn58xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 000000000..e8613e1f6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,874 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
+
+#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
+#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
+#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
+#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
+#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
+#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
+#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
+#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
+#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
+#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
+#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
+#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
+#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
+#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
+#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
+#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
+static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
+                        return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
+
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
+                        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
+        }
+        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+}
+
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
+
+union cvmx_dpi_bist_status {
+        uint64_t u64;
+        struct cvmx_dpi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t bist:47;
+#else
+                uint64_t bist:47;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_dpi_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t bist:45;
+#else
+                uint64_t bist:45;
+                uint64_t reserved_45_63:19;
+#endif
+        } cn63xx;
+        struct cvmx_dpi_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t bist:37;
+#else
+                uint64_t bist:37;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_dpi_ctl {
+        uint64_t u64;
+        struct cvmx_dpi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t clk:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t clk:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+        struct cvmx_dpi_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } cn61xx;
+};
+
+union cvmx_dpi_dmax_counts {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t fcnt:7;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dmax_dbell {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+#else
+                uint64_t dbell:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dmax_err_rsp_status {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_err_rsp_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t status:6;
+#else
+                uint64_t status:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dmax_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t saddr:33;
+                uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:33;
+                uint64_t idle:1;
+                uint64_t reserved_41_47:7;
+                uint64_t csize:14;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t reserved_36_39:4;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:29;
+                uint64_t reserved_36_39:4;
+                uint64_t idle:1;
+                uint64_t reserved_41_47:7;
+                uint64_t csize:14;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn61xx;
+};
+
+union cvmx_dpi_dmax_iflight {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_iflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t cnt:3;
+#else
+                uint64_t cnt:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dmax_naddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+        struct cvmx_dpi_dmax_naddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn61xx;
+};
+
+union cvmx_dpi_dmax_reqbnk0 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:64;
+#else
+                uint64_t state:64;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dmax_reqbnk1 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:64;
+#else
+                uint64_t state:64;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dma_control {
+        uint64_t u64;
+        struct cvmx_dpi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t dici_mode:1;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t ffp_dis:1;
+                uint64_t pkt_en1:1;
+                uint64_t dici_mode:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+        struct cvmx_dpi_dma_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t ffp_dis:1;
+                uint64_t pkt_en1:1;
+                uint64_t reserved_61_63:3;
+#endif
+        } cn63xx;
+        struct cvmx_dpi_dma_control_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_dpi_dma_engx_en {
+        uint64_t u64;
+        struct cvmx_dpi_dma_engx_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+#else
+                uint64_t qen:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_dma_ppx_cnt {
+        uint64_t u64;
+        struct cvmx_dpi_dma_ppx_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+#else
+                uint64_t cnt:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_dpi_engx_buf {
+        uint64_t u64;
+        struct cvmx_dpi_engx_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t compblks:5;
+                uint64_t reserved_9_31:23;
+                uint64_t base:5;
+                uint64_t blks:4;
+#else
+                uint64_t blks:4;
+                uint64_t base:5;
+                uint64_t reserved_9_31:23;
+                uint64_t compblks:5;
+                uint64_t reserved_37_63:27;
+#endif
+        } s;
+        struct cvmx_dpi_engx_buf_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t base:4;
+                uint64_t blks:4;
+#else
+                uint64_t blks:4;
+                uint64_t base:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn63xx;
+};
+
+union cvmx_dpi_info_reg {
+        uint64_t u64;
+        struct cvmx_dpi_info_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ffp:4;
+                uint64_t reserved_2_3:2;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+#else
+                uint64_t rsl:1;
+                uint64_t ncb:1;
+                uint64_t reserved_2_3:2;
+                uint64_t ffp:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_dpi_info_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+#else
+                uint64_t rsl:1;
+                uint64_t ncb:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_dpi_int_en {
+        uint64_t u64;
+        struct cvmx_dpi_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt3_rst:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+        struct cvmx_dpi_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t reserved_26_63:38;
+#endif
+        } cn63xx;
+};
+
+union cvmx_dpi_int_reg {
+        uint64_t u64;
+        struct cvmx_dpi_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt3_rst:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+        struct cvmx_dpi_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t reserved_26_63:38;
+#endif
+        } cn63xx;
+};
+
+union cvmx_dpi_ncbx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_ncbx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t molr:6;
+#else
+                uint64_t molr:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_dpi_pint_info {
+        uint64_t u64;
+        struct cvmx_dpi_pint_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t iinfo:6;
+                uint64_t reserved_6_7:2;
+                uint64_t sinfo:6;
+#else
+                uint64_t sinfo:6;
+                uint64_t reserved_6_7:2;
+                uint64_t iinfo:6;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_dpi_pkt_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_pkt_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t pkterr:1;
+#else
+                uint64_t pkterr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+#else
+                uint64_t qerr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_err_rsp_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_err_rst {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+#else
+                uint64_t qerr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_err_rst_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_err_skip_comp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_skip_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t en_rst:8;
+                uint64_t reserved_8_15:8;
+                uint64_t en_rsp:8;
+#else
+                uint64_t en_rsp:8;
+                uint64_t reserved_8_15:8;
+                uint64_t en_rst:8;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_dpi_req_gbl_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_gbl_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+#else
+                uint64_t qen:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_dpi_sli_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t qlm_cfg:4;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+#else
+                uint64_t mrrs:2;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs_lim:1;
+                uint64_t mps:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps_lim:1;
+                uint64_t molr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t rd_mode:1;
+                uint64_t reserved_17_19:3;
+                uint64_t qlm_cfg:4;
+                uint64_t halt:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t reserved_21_23:3;
+                uint64_t qlm_cfg:1;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+#else
+                uint64_t mrrs:2;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs_lim:1;
+                uint64_t mps:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps_lim:1;
+                uint64_t molr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t rd_mode:1;
+                uint64_t reserved_17_19:3;
+                uint64_t qlm_cfg:1;
+                uint64_t reserved_21_23:3;
+                uint64_t halt:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } cn63xx;
+};
+
+union cvmx_dpi_sli_prtx_err {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t addr:61;
+#endif
+        } s;
+};
+
+union cvmx_dpi_sli_prtx_err_info {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t lock:1;
+                uint64_t reserved_5_7:3;
+                uint64_t type:1;
+                uint64_t reserved_3_3:1;
+                uint64_t reqq:3;
+#else
+                uint64_t reqq:3;
+                uint64_t reserved_3_3:1;
+                uint64_t type:1;
+                uint64_t reserved_5_7:3;
+                uint64_t lock:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
new file mode 100644
index 000000000..dafeae300
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -0,0 +1,619 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Interface to the hardware Fetch and Add Unit.
+ */
+
+#ifndef __CVMX_FAU_H__
+#define __CVMX_FAU_H__
+
+/*
+ * Octeon Fetch and Add Unit (FAU)
+ */
+
+#define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
+#define CVMX_FAU_BITS_SCRADDR       63, 56
+#define CVMX_FAU_BITS_LEN           55, 48
+#define CVMX_FAU_BITS_INEVAL        35, 14
+#define CVMX_FAU_BITS_TAGWAIT       13, 13
+#define CVMX_FAU_BITS_NOADD         13, 13
+#define CVMX_FAU_BITS_SIZE          12, 11
+#define CVMX_FAU_BITS_REGISTER      10, 0
+
+typedef enum {
+        CVMX_FAU_OP_SIZE_8 = 0,
+        CVMX_FAU_OP_SIZE_16 = 1,
+        CVMX_FAU_OP_SIZE_32 = 2,
+        CVMX_FAU_OP_SIZE_64 = 3
+} cvmx_fau_op_size_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int64_t value:63;
+} cvmx_fau_tagwait64_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int32_t value:31;
+} cvmx_fau_tagwait32_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int16_t value:15;
+} cvmx_fau_tagwait16_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int8_t value:7;
+} cvmx_fau_tagwait8_t;
+
+/**
+ * Asynchronous tagwait return definition. If a timeout occurs,
+ * the error bit will be set. Otherwise the value of the
+ * register before the update will be returned.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                uint64_t invalid:1;
+                uint64_t data:63;       /* unpredictable if invalid is set */
+        } s;
+} cvmx_fau_async_tagwait_result_t;
+
+#ifdef __BIG_ENDIAN_BITFIELD
+#define SWIZZLE_8  0
+#define SWIZZLE_16 0
+#define SWIZZLE_32 0
+#else
+#define SWIZZLE_8  0x7
+#define SWIZZLE_16 0x6
+#define SWIZZLE_32 0x4
+#endif
+
+/**
+ * Builds a store I/O address for writing to the FAU
+ *
+ * @noadd:  0 = Store value is atomically added to the current value
+ *               1 = Store value is atomically written over the current value
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ *               - Step by 4 for 32 bit access.
+ *               - Step by 8 for 64 bit access.
+ * Returns Address to store for atomic update
+ */
+static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
+{
+        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+               cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Builds a I/O address for accessing the FAU
+ *
+ * @tagwait: Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * Returns Address to read from for atomic update
+ */
+static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
+                                                 int64_t value)
+{
+        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Value of the register before the update
+ */
+static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
+                                               int64_t value)
+{
+        return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Value of the register before the update
+ */
+static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
+                                               int32_t value)
+{
+        reg ^= SWIZZLE_32;
+        return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ * Returns Value of the register before the update
+ */
+static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
+                                               int16_t value)
+{
+        reg ^= SWIZZLE_16;
+        return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ * Returns Value of the register before the update
+ */
+static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        reg ^= SWIZZLE_8;
+        return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 64 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 8 for 64 bit access.
+ * @value:  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait64_t
+cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        union {
+                uint64_t i64;
+                cvmx_fau_tagwait64_t t;
+        } result;
+        result.i64 =
+            cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 32 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 4 for 32 bit access.
+ * @value:  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait32_t
+cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        union {
+                uint64_t i32;
+                cvmx_fau_tagwait32_t t;
+        } result;
+        reg ^= SWIZZLE_32;
+        result.i32 =
+            cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 16 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ * @value:  Signed value to add.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait16_t
+cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        union {
+                uint64_t i16;
+                cvmx_fau_tagwait16_t t;
+        } result;
+        reg ^= SWIZZLE_16;
+        result.i16 =
+            cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 8 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ * @value:  Signed value to add.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait8_t
+cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        union {
+                uint64_t i8;
+                cvmx_fau_tagwait8_t t;
+        } result;
+        reg ^= SWIZZLE_8;
+        result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Builds I/O data for async operations
+ *
+ * @scraddr: Scratch pad byte address to write to.  Must be 8 byte aligned
+ * @value:   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * @tagwait: Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @size:    The size of the operation:
+ *                - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
+ *                - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
+ *                - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
+ *                - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * Returns Data to write using cvmx_send_single
+ */
+static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
+                                              uint64_t tagwait,
+                                              cvmx_fau_op_size_t size,
+                                              uint64_t reg)
+{
+        return CVMX_FAU_LOAD_IO_ADDRESS |
+               cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
+               cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
+               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+               cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Perform an async atomic 64 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
+                                                  cvmx_fau_reg_64_t reg,
+                                                  int64_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+/**
+ * Perform an async atomic 32 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
+                                                  cvmx_fau_reg_32_t reg,
+                                                  int32_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+/**
+ * Perform an async atomic 16 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
+                                                  cvmx_fau_reg_16_t reg,
+                                                  int16_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+/**
+ * Perform an async atomic 8 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
+                                                 cvmx_fau_reg_8_t reg,
+                                                 int8_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+/**
+ * Perform an async atomic 64 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
+                                                          cvmx_fau_reg_64_t reg,
+                                                          int64_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+/**
+ * Perform an async atomic 32 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
+                                                          cvmx_fau_reg_32_t reg,
+                                                          int32_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+/**
+ * Perform an async atomic 16 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ *
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
+                                                          cvmx_fau_reg_16_t reg,
+                                                          int16_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+/**
+ * Perform an async atomic 8 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ *
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
+                                                         cvmx_fau_reg_8_t reg,
+                                                         int8_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        reg ^= SWIZZLE_32;
+        cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        reg ^= SWIZZLE_16;
+        cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        reg ^= SWIZZLE_8;
+        cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 64 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 32 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        reg ^= SWIZZLE_32;
+        cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 16 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        reg ^= SWIZZLE_16;
+        cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 8 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        reg ^= SWIZZLE_8;
+        cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
+}
+
+#endif /* __CVMX_FAU_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
new file mode 100644
index 000000000..322943f7c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
@@ -0,0 +1,1252 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_FPA_DEFS_H__
+#define __CVMX_FPA_DEFS_H__
+
+#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
+#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
+#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
+#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
+#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
+#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
+#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
+#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
+#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
+#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
+#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
+#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
+#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
+#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
+#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
+#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
+#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
+#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
+#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
+#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
+#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
+#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
+#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
+#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
+#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
+#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
+#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
+#define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull))
+
+union cvmx_fpa_addr_range_error {
+        uint64_t u64;
+        struct cvmx_fpa_addr_range_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t pool:5;
+                uint64_t addr:33;
+#else
+                uint64_t addr:33;
+                uint64_t pool:5;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+};
+
+union cvmx_fpa_bist_status {
+        uint64_t u64;
+        struct cvmx_fpa_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t frd:1;
+                uint64_t fpf0:1;
+                uint64_t fpf1:1;
+                uint64_t ffr:1;
+                uint64_t fdr:1;
+#else
+                uint64_t fdr:1;
+                uint64_t ffr:1;
+                uint64_t fpf1:1;
+                uint64_t fpf0:1;
+                uint64_t frd:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_fpa_ctl_status {
+        uint64_t u64;
+        struct cvmx_fpa_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t free_en:1;
+                uint64_t ret_off:1;
+                uint64_t req_off:1;
+                uint64_t reset:1;
+                uint64_t use_ldt:1;
+                uint64_t use_stt:1;
+                uint64_t enb:1;
+                uint64_t mem1_err:7;
+                uint64_t mem0_err:7;
+#else
+                uint64_t mem0_err:7;
+                uint64_t mem1_err:7;
+                uint64_t enb:1;
+                uint64_t use_stt:1;
+                uint64_t use_ldt:1;
+                uint64_t reset:1;
+                uint64_t req_off:1;
+                uint64_t ret_off:1;
+                uint64_t free_en:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+        struct cvmx_fpa_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t reset:1;
+                uint64_t use_ldt:1;
+                uint64_t use_stt:1;
+                uint64_t enb:1;
+                uint64_t mem1_err:7;
+                uint64_t mem0_err:7;
+#else
+                uint64_t mem0_err:7;
+                uint64_t mem1_err:7;
+                uint64_t enb:1;
+                uint64_t use_stt:1;
+                uint64_t use_ldt:1;
+                uint64_t reset:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn30xx;
+};
+
+union cvmx_fpa_fpfx_marks {
+        uint64_t u64;
+        struct cvmx_fpa_fpfx_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t fpf_wr:11;
+                uint64_t fpf_rd:11;
+#else
+                uint64_t fpf_rd:11;
+                uint64_t fpf_wr:11;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+};
+
+union cvmx_fpa_fpfx_size {
+        uint64_t u64;
+        struct cvmx_fpa_fpfx_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t fpf_siz:11;
+#else
+                uint64_t fpf_siz:11;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+};
+
+union cvmx_fpa_fpf0_marks {
+        uint64_t u64;
+        struct cvmx_fpa_fpf0_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t fpf_wr:12;
+                uint64_t fpf_rd:12;
+#else
+                uint64_t fpf_rd:12;
+                uint64_t fpf_wr:12;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_fpa_fpf0_size {
+        uint64_t u64;
+        struct cvmx_fpa_fpf0_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t fpf_siz:12;
+#else
+                uint64_t fpf_siz:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_fpa_fpf8_marks {
+        uint64_t u64;
+        struct cvmx_fpa_fpf8_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t fpf_wr:11;
+                uint64_t fpf_rd:11;
+#else
+                uint64_t fpf_rd:11;
+                uint64_t fpf_wr:11;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+};
+
+union cvmx_fpa_fpf8_size {
+        uint64_t u64;
+        struct cvmx_fpa_fpf8_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t fpf_siz:12;
+#else
+                uint64_t fpf_siz:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_fpa_int_enb {
+        uint64_t u64;
+        struct cvmx_fpa_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_50_63:14;
+                uint64_t paddr_e:1;
+                uint64_t reserved_44_48:5;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t reserved_44_48:5;
+                uint64_t paddr_e:1;
+                uint64_t reserved_50_63:14;
+#endif
+        } s;
+        struct cvmx_fpa_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn30xx;
+        struct cvmx_fpa_int_enb_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_50_63:14;
+                uint64_t paddr_e:1;
+                uint64_t res_44:5;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t res_44:5;
+                uint64_t paddr_e:1;
+                uint64_t reserved_50_63:14;
+#endif
+        } cn61xx;
+        struct cvmx_fpa_int_enb_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn63xx;
+        struct cvmx_fpa_int_enb_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_50_63:14;
+                uint64_t paddr_e:1;
+                uint64_t pool8th:1;
+                uint64_t q8_perr:1;
+                uint64_t q8_coff:1;
+                uint64_t q8_und:1;
+                uint64_t free8:1;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t free8:1;
+                uint64_t q8_und:1;
+                uint64_t q8_coff:1;
+                uint64_t q8_perr:1;
+                uint64_t pool8th:1;
+                uint64_t paddr_e:1;
+                uint64_t reserved_50_63:14;
+#endif
+        } cn68xx;
+};
+
+union cvmx_fpa_int_sum {
+        uint64_t u64;
+        struct cvmx_fpa_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_50_63:14;
+                uint64_t paddr_e:1;
+                uint64_t pool8th:1;
+                uint64_t q8_perr:1;
+                uint64_t q8_coff:1;
+                uint64_t q8_und:1;
+                uint64_t free8:1;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t free8:1;
+                uint64_t q8_und:1;
+                uint64_t q8_coff:1;
+                uint64_t q8_perr:1;
+                uint64_t pool8th:1;
+                uint64_t paddr_e:1;
+                uint64_t reserved_50_63:14;
+#endif
+        } s;
+        struct cvmx_fpa_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn30xx;
+        struct cvmx_fpa_int_sum_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_50_63:14;
+                uint64_t paddr_e:1;
+                uint64_t reserved_44_48:5;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t reserved_44_48:5;
+                uint64_t paddr_e:1;
+                uint64_t reserved_50_63:14;
+#endif
+        } cn61xx;
+        struct cvmx_fpa_int_sum_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t free7:1;
+                uint64_t free6:1;
+                uint64_t free5:1;
+                uint64_t free4:1;
+                uint64_t free3:1;
+                uint64_t free2:1;
+                uint64_t free1:1;
+                uint64_t free0:1;
+                uint64_t pool7th:1;
+                uint64_t pool6th:1;
+                uint64_t pool5th:1;
+                uint64_t pool4th:1;
+                uint64_t pool3th:1;
+                uint64_t pool2th:1;
+                uint64_t pool1th:1;
+                uint64_t pool0th:1;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+#else
+                uint64_t fed0_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed1_dbe:1;
+                uint64_t q0_und:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_perr:1;
+                uint64_t q1_und:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_perr:1;
+                uint64_t q2_und:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_perr:1;
+                uint64_t q3_und:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_perr:1;
+                uint64_t q4_und:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_perr:1;
+                uint64_t q5_und:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_perr:1;
+                uint64_t q6_und:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_perr:1;
+                uint64_t q7_und:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_perr:1;
+                uint64_t pool0th:1;
+                uint64_t pool1th:1;
+                uint64_t pool2th:1;
+                uint64_t pool3th:1;
+                uint64_t pool4th:1;
+                uint64_t pool5th:1;
+                uint64_t pool6th:1;
+                uint64_t pool7th:1;
+                uint64_t free0:1;
+                uint64_t free1:1;
+                uint64_t free2:1;
+                uint64_t free3:1;
+                uint64_t free4:1;
+                uint64_t free5:1;
+                uint64_t free6:1;
+                uint64_t free7:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn63xx;
+};
+
+union cvmx_fpa_packet_threshold {
+        uint64_t u64;
+        struct cvmx_fpa_packet_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t thresh:32;
+#else
+                uint64_t thresh:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_fpa_poolx_end_addr {
+        uint64_t u64;
+        struct cvmx_fpa_poolx_end_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t addr:33;
+#else
+                uint64_t addr:33;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_fpa_poolx_start_addr {
+        uint64_t u64;
+        struct cvmx_fpa_poolx_start_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t addr:33;
+#else
+                uint64_t addr:33;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_fpa_poolx_threshold {
+        uint64_t u64;
+        struct cvmx_fpa_poolx_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t thresh:32;
+#else
+                uint64_t thresh:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_fpa_poolx_threshold_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t thresh:29;
+#else
+                uint64_t thresh:29;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn61xx;
+};
+
+union cvmx_fpa_quex_available {
+        uint64_t u64;
+        struct cvmx_fpa_quex_available_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t que_siz:32;
+#else
+                uint64_t que_siz:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_fpa_quex_available_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t que_siz:29;
+#else
+                uint64_t que_siz:29;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn30xx;
+};
+
+union cvmx_fpa_quex_page_index {
+        uint64_t u64;
+        struct cvmx_fpa_quex_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t pg_num:25;
+#else
+                uint64_t pg_num:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_fpa_que8_page_index {
+        uint64_t u64;
+        struct cvmx_fpa_que8_page_index_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t pg_num:25;
+#else
+                uint64_t pg_num:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_fpa_que_act {
+        uint64_t u64;
+        struct cvmx_fpa_que_act_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t act_que:3;
+                uint64_t act_indx:26;
+#else
+                uint64_t act_indx:26;
+                uint64_t act_que:3;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+union cvmx_fpa_que_exp {
+        uint64_t u64;
+        struct cvmx_fpa_que_exp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t exp_que:3;
+                uint64_t exp_indx:26;
+#else
+                uint64_t exp_indx:26;
+                uint64_t exp_que:3;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+union cvmx_fpa_wart_ctl {
+        uint64_t u64;
+        struct cvmx_fpa_wart_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t ctl:16;
+#else
+                uint64_t ctl:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_fpa_wart_status {
+        uint64_t u64;
+        struct cvmx_fpa_wart_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t status:32;
+#else
+                uint64_t status:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_fpa_wqe_threshold {
+        uint64_t u64;
+        struct cvmx_fpa_wqe_threshold_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t thresh:32;
+#else
+                uint64_t thresh:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
new file mode 100644
index 000000000..29ae63606
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -0,0 +1,308 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to the hardware Free Pool Allocator.
+ *
+ *
+ */
+
+#ifndef __CVMX_FPA_H__
+#define __CVMX_FPA_H__
+
+#include <linux/delay.h>
+
+#include <asm/octeon/cvmx-address.h>
+#include <asm/octeon/cvmx-fpa-defs.h>
+
+#define CVMX_FPA_NUM_POOLS      8
+#define CVMX_FPA_MIN_BLOCK_SIZE 128
+#define CVMX_FPA_ALIGNMENT      128
+
+/**
+ * Structure describing the data format used for stores to the FPA.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * the (64-bit word) location in scratchpad to write
+                 * to (if len != 0)
+                 */
+                uint64_t scraddr:8;
+                /* the number of words in the response (0 => no response) */
+                uint64_t len:8;
+                /* the ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                /*
+                 * the address that will appear in the first tick on
+                 * the NCB bus.
+                 */
+                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t did:8;
+                uint64_t len:8;
+                uint64_t scraddr:8;
+#endif
+        } s;
+} cvmx_fpa_iobdma_data_t;
+
+/**
+ * Structure describing the current state of a FPA pool.
+ */
+typedef struct {
+        /* Name it was created under */
+        const char *name;
+        /* Size of each block */
+        uint64_t size;
+        /* The base memory address of whole block */
+        void *base;
+        /* The number of elements in the pool at creation */
+        uint64_t starting_element_count;
+} cvmx_fpa_pool_info_t;
+
+/**
+ * Current state of all the pools. Use access functions
+ * instead of using it directly.
+ */
+extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Return the name of the pool
+ *
+ * @pool:   Pool to get the name of
+ * Returns The name
+ */
+static inline const char *cvmx_fpa_get_name(uint64_t pool)
+{
+        return cvmx_fpa_pool_info[pool].name;
+}
+
+/**
+ * Return the base of the pool
+ *
+ * @pool:   Pool to get the base of
+ * Returns The base
+ */
+static inline void *cvmx_fpa_get_base(uint64_t pool)
+{
+        return cvmx_fpa_pool_info[pool].base;
+}
+
+/**
+ * Check if a pointer belongs to an FPA pool. Return non-zero
+ * if the supplied pointer is inside the memory controlled by
+ * an FPA pool.
+ *
+ * @pool:   Pool to check
+ * @ptr:    Pointer to check
+ * Returns Non-zero if pointer is in the pool. Zero if not
+ */
+static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
+{
+        return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
+                ((char *)ptr <
+                 ((char *)(cvmx_fpa_pool_info[pool].base)) +
+                 cvmx_fpa_pool_info[pool].size *
+                 cvmx_fpa_pool_info[pool].starting_element_count));
+}
+
+/**
+ * Enable the FPA for use. Must be performed after any CSR
+ * configuration but before any other FPA functions.
+ */
+static inline void cvmx_fpa_enable(void)
+{
+        union cvmx_fpa_ctl_status status;
+
+        status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
+        if (status.s.enb) {
+                cvmx_dprintf
+                    ("Warning: Enabling FPA when FPA already enabled.\n");
+        }
+
+        /*
+         * Do runtime check as we allow pass1 compiled code to run on
+         * pass2 chips.
+         */
+        if (cvmx_octeon_is_pass1()) {
+                union cvmx_fpa_fpfx_marks marks;
+                int i;
+                for (i = 1; i < 8; i++) {
+                        marks.u64 =
+                            cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
+                        marks.s.fpf_wr = 0xe0;
+                        cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
+                                       marks.u64);
+                }
+
+                /* Enforce a 10 cycle delay between config and enable */
+                __delay(10);
+        }
+
+        /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
+        status.u64 = 0;
+        status.s.enb = 1;
+        cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
+}
+
+/**
+ * Get a new block from the FPA
+ *
+ * @pool:   Pool to get the block from
+ * Returns Pointer to the block or NULL on failure
+ */
+static inline void *cvmx_fpa_alloc(uint64_t pool)
+{
+        uint64_t address =
+            cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
+        if (address)
+                return cvmx_phys_to_ptr(address);
+        else
+                return NULL;
+}
+
+/**
+ * Asynchronously get a new block from the FPA
+ *
+ * @scr_addr: Local scratch address to put response in.  This is a byte address,
+ *                  but must be 8 byte aligned.
+ * @pool:      Pool to get the block from
+ */
+static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
+{
+        cvmx_fpa_iobdma_data_t data;
+
+        /*
+         * Hardware only uses 64 bit aligned locations, so convert
+         * from byte address to 64-bit index
+         */
+        data.s.scraddr = scr_addr >> 3;
+        data.s.len = 1;
+        data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
+        data.s.addr = 0;
+        cvmx_send_single(data.u64);
+}
+
+/**
+ * Free a block allocated with a FPA pool.  Does NOT provide memory
+ * ordering in cases where the memory block was modified by the core.
+ *
+ * @ptr:    Block to free
+ * @pool:   Pool to put it in
+ * @num_cache_lines:
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
+                                        uint64_t num_cache_lines)
+{
+        cvmx_addr_t newptr;
+        newptr.u64 = cvmx_ptr_to_phys(ptr);
+        newptr.sfilldidspace.didspace =
+            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
+        /* Prevent GCC from reordering around free */
+        barrier();
+        /* value written is number of cache lines not written back */
+        cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+/**
+ * Free a block allocated with a FPA pool.  Provides required memory
+ * ordering in cases where memory block was modified by core.
+ *
+ * @ptr:    Block to free
+ * @pool:   Pool to put it in
+ * @num_cache_lines:
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
+                                 uint64_t num_cache_lines)
+{
+        cvmx_addr_t newptr;
+        newptr.u64 = cvmx_ptr_to_phys(ptr);
+        newptr.sfilldidspace.didspace =
+            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
+        /*
+         * Make sure that any previous writes to memory go out before
+         * we free this buffer.  This also serves as a barrier to
+         * prevent GCC from reordering operations to after the
+         * free.
+         */
+        CVMX_SYNCWS;
+        /* value written is number of cache lines not written back */
+        cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+/**
+ * Setup a FPA pool to control a new block of memory.
+ * This can only be called once per pool. Make sure proper
+ * locking enforces this.
+ *
+ * @pool:       Pool to initialize
+ *                   0 <= pool < 8
+ * @name:       Constant character string to name this pool.
+ *                   String is not copied.
+ * @buffer:     Pointer to the block of memory to use. This must be
+ *                   accessible by all processors and external hardware.
+ * @block_size: Size for each block controlled by the FPA
+ * @num_blocks: Number of blocks
+ *
+ * Returns 0 on Success,
+ *         -1 on failure
+ */
+extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
+                               uint64_t block_size, uint64_t num_blocks);
+
+/**
+ * Shutdown a Memory pool and validate that it had all of
+ * the buffers originally placed in it. This should only be
+ * called by one processor after all hardware has finished
+ * using the pool.
+ *
+ * @pool:   Pool to shutdown
+ * Returns Zero on success
+ *         - Positive is count of missing buffers
+ *         - Negative is too many buffers or corrupted pointers
+ */
+extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
+
+/**
+ * Get the size of blocks controlled by the pool
+ * This is resolved to a constant at compile time.
+ *
+ * @pool:   Pool to access
+ * Returns Size of the block in bytes
+ */
+uint64_t cvmx_fpa_get_block_size(uint64_t pool);
+
+#endif /*  __CVM_FPA_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
new file mode 100644
index 000000000..bdba676f1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
@@ -0,0 +1,2259 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_GMXX_DEFS_H__
+#define __CVMX_GMXX_DEFS_H__
+
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+
+static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+
+static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
+}
+
+#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
+static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
+}
+
+void __cvmx_interrupt_gmxx_enable(int interface);
+
+union cvmx_gmxx_hg2_control {
+        uint64_t u64;
+        struct cvmx_gmxx_hg2_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t hg2tx_en:1;
+                uint64_t hg2rx_en:1;
+                uint64_t phys_en:1;
+                uint64_t logl_en:16;
+#else
+                uint64_t logl_en:16;
+                uint64_t phys_en:1;
+                uint64_t hg2rx_en:1;
+                uint64_t hg2tx_en:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_inf_mode {
+        uint64_t u64;
+        struct cvmx_gmxx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t rate:4;
+                uint64_t reserved_12_15:4;
+                uint64_t speed:4;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:3;
+                uint64_t reserved_3_3:1;
+                uint64_t p0mii:1;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t p0mii:1;
+                uint64_t reserved_3_3:1;
+                uint64_t mode:3;
+                uint64_t reserved_7_7:1;
+                uint64_t speed:4;
+                uint64_t reserved_12_15:4;
+                uint64_t rate:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_gmxx_inf_mode_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t p0mii:1;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t p0mii:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_inf_mode_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn31xx;
+        struct cvmx_gmxx_inf_mode_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t speed:2;
+                uint64_t reserved_6_7:2;
+                uint64_t mode:2;
+                uint64_t reserved_2_3:2;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t reserved_2_3:2;
+                uint64_t mode:2;
+                uint64_t reserved_6_7:2;
+                uint64_t speed:2;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn52xx;
+        struct cvmx_gmxx_inf_mode_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t speed:4;
+                uint64_t reserved_5_7:3;
+                uint64_t mode:1;
+                uint64_t reserved_2_3:2;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t reserved_2_3:2;
+                uint64_t mode:1;
+                uint64_t reserved_5_7:3;
+                uint64_t speed:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn61xx;
+        struct cvmx_gmxx_inf_mode_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t rate:4;
+                uint64_t reserved_12_15:4;
+                uint64_t speed:4;
+                uint64_t reserved_5_7:3;
+                uint64_t mode:1;
+                uint64_t reserved_2_3:2;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t reserved_2_3:2;
+                uint64_t mode:1;
+                uint64_t reserved_5_7:3;
+                uint64_t speed:4;
+                uint64_t reserved_12_15:4;
+                uint64_t rate:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn66xx;
+        struct cvmx_gmxx_inf_mode_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t speed:4;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:3;
+                uint64_t reserved_2_3:2;
+                uint64_t en:1;
+                uint64_t type:1;
+#else
+                uint64_t type:1;
+                uint64_t en:1;
+                uint64_t reserved_2_3:2;
+                uint64_t mode:3;
+                uint64_t reserved_7_7:1;
+                uint64_t speed:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn68xx;
+};
+
+union cvmx_gmxx_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_gmxx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t pknd:6;
+                uint64_t reserved_14_15:2;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_4_7:4;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t speed:1;
+                uint64_t duplex:1;
+                uint64_t slottime:1;
+                uint64_t reserved_4_7:4;
+                uint64_t speed_msb:1;
+                uint64_t reserved_9_11:3;
+                uint64_t rx_idle:1;
+                uint64_t tx_idle:1;
+                uint64_t reserved_14_15:2;
+                uint64_t pknd:6;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_gmxx_prtx_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t speed:1;
+                uint64_t duplex:1;
+                uint64_t slottime:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_4_7:4;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t speed:1;
+                uint64_t duplex:1;
+                uint64_t slottime:1;
+                uint64_t reserved_4_7:4;
+                uint64_t speed_msb:1;
+                uint64_t reserved_9_11:3;
+                uint64_t rx_idle:1;
+                uint64_t tx_idle:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn52xx;
+};
+
+union cvmx_gmxx_rxx_adr_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t cam_mode:1;
+                uint64_t mcst:2;
+                uint64_t bcst:1;
+#else
+                uint64_t bcst:1;
+                uint64_t mcst:2;
+                uint64_t cam_mode:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rxx_frm_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_11_11:1;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t pre_align:1;
+                uint64_t null_dis:1;
+                uint64_t reserved_11_11:1;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn31xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_align:1;
+                uint64_t null_dis:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn50xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_align:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t pre_align:1;
+                uint64_t null_dis:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn58xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_11_11:1;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+#else
+                uint64_t pre_chk:1;
+                uint64_t pre_strp:1;
+                uint64_t ctl_drp:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_smac:1;
+                uint64_t pre_free:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_align:1;
+                uint64_t null_dis:1;
+                uint64_t reserved_11_11:1;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gmxx_rxx_frm_max {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+#else
+                uint64_t len:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rxx_frm_min {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+#else
+                uint64_t len:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rxx_int_en {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+        struct cvmx_gmxx_rxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_rxx_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn50xx;
+        struct cvmx_gmxx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn52xx;
+        struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn58xx;
+        struct cvmx_gmxx_rxx_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gmxx_rxx_int_reg {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+        struct cvmx_gmxx_rxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_rxx_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn50xx;
+        struct cvmx_gmxx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn52xx;
+        struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_int_reg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t maxerr:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t alnerr:1;
+                uint64_t lenerr:1;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t niberr:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t phy_link:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_dupx:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn58xx;
+        struct cvmx_gmxx_rxx_int_reg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+#else
+                uint64_t minerr:1;
+                uint64_t carext:1;
+                uint64_t reserved_2_2:1;
+                uint64_t jabber:1;
+                uint64_t fcserr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t rcverr:1;
+                uint64_t skperr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t ovrerr:1;
+                uint64_t pcterr:1;
+                uint64_t rsverr:1;
+                uint64_t falerr:1;
+                uint64_t coldet:1;
+                uint64_t ifgerr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t pause_drp:1;
+                uint64_t loc_fault:1;
+                uint64_t rem_fault:1;
+                uint64_t bad_seq:1;
+                uint64_t bad_term:1;
+                uint64_t unsop:1;
+                uint64_t uneop:1;
+                uint64_t undat:1;
+                uint64_t hg2fld:1;
+                uint64_t hg2cc:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gmxx_rxx_jabber {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+#else
+                uint64_t cnt:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rxx_rx_inbnd {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t duplex:1;
+                uint64_t speed:2;
+                uint64_t status:1;
+#else
+                uint64_t status:1;
+                uint64_t speed:2;
+                uint64_t duplex:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rx_prts {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t prts:3;
+#else
+                uint64_t prts:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_rx_xaui_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t status:2;
+#else
+                uint64_t status:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_txx_thresh {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t cnt:10;
+#else
+                uint64_t cnt:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_gmxx_txx_thresh_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t cnt:7;
+#else
+                uint64_t cnt:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_txx_thresh_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t cnt:9;
+#else
+                uint64_t cnt:9;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn38xx;
+};
+
+union cvmx_gmxx_tx_int_en {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+        struct cvmx_gmxx_tx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t late_col:3;
+                uint64_t reserved_15_15:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:3;
+                uint64_t reserved_5_7:3;
+                uint64_t xscol:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_15_15:1;
+                uint64_t late_col:3;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_tx_int_en_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:3;
+                uint64_t reserved_5_7:3;
+                uint64_t xscol:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn31xx;
+        struct cvmx_gmxx_tx_int_en_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t ncb_nxa:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn38xx;
+        struct cvmx_gmxx_tx_int_en_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t ncb_nxa:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xxp2;
+        struct cvmx_gmxx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn52xx;
+        struct cvmx_gmxx_tx_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn63xx;
+        struct cvmx_gmxx_tx_int_en_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t pko_nxp:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t pko_nxp:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } cn68xx;
+        struct cvmx_gmxx_tx_int_en_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t reserved_22_23:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_19:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_22_23:2;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } cnf71xx;
+};
+
+union cvmx_gmxx_tx_int_reg {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+        struct cvmx_gmxx_tx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t late_col:3;
+                uint64_t reserved_15_15:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:3;
+                uint64_t reserved_5_7:3;
+                uint64_t xscol:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_15_15:1;
+                uint64_t late_col:3;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_tx_int_reg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:3;
+                uint64_t reserved_5_7:3;
+                uint64_t xscol:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn31xx;
+        struct cvmx_gmxx_tx_int_reg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t ncb_nxa:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn38xx;
+        struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t ncb_nxa:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xxp2;
+        struct cvmx_gmxx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn52xx;
+        struct cvmx_gmxx_tx_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn63xx;
+        struct cvmx_gmxx_tx_int_reg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t ptp_lost:4;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t pko_nxp:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t pko_nxp:1;
+                uint64_t undflw:4;
+                uint64_t reserved_6_7:2;
+                uint64_t xscol:4;
+                uint64_t xsdef:4;
+                uint64_t late_col:4;
+                uint64_t ptp_lost:4;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } cn68xx;
+        struct cvmx_gmxx_tx_int_reg_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t xchange:1;
+                uint64_t reserved_22_23:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+#else
+                uint64_t pko_nxa:1;
+                uint64_t reserved_1_1:1;
+                uint64_t undflw:2;
+                uint64_t reserved_4_7:4;
+                uint64_t xscol:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_14_15:2;
+                uint64_t late_col:2;
+                uint64_t reserved_18_19:2;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_22_23:2;
+                uint64_t xchange:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } cnf71xx;
+};
+
+union cvmx_gmxx_tx_ovr_bp {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t tx_prt_bp:16;
+                uint64_t reserved_12_31:20;
+                uint64_t en:4;
+                uint64_t bp:4;
+                uint64_t ign_full:4;
+#else
+                uint64_t ign_full:4;
+                uint64_t bp:4;
+                uint64_t en:4;
+                uint64_t reserved_12_31:20;
+                uint64_t tx_prt_bp:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_gmxx_tx_ovr_bp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t en:3;
+                uint64_t reserved_7_7:1;
+                uint64_t bp:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ign_full:3;
+#else
+                uint64_t ign_full:3;
+                uint64_t reserved_3_3:1;
+                uint64_t bp:3;
+                uint64_t reserved_7_7:1;
+                uint64_t en:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn30xx;
+        struct cvmx_gmxx_tx_ovr_bp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t en:4;
+                uint64_t bp:4;
+                uint64_t ign_full:4;
+#else
+                uint64_t ign_full:4;
+                uint64_t bp:4;
+                uint64_t en:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn38xx;
+        struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t tx_prt_bp:16;
+                uint64_t reserved_10_31:22;
+                uint64_t en:2;
+                uint64_t reserved_6_7:2;
+                uint64_t bp:2;
+                uint64_t reserved_2_3:2;
+                uint64_t ign_full:2;
+#else
+                uint64_t ign_full:2;
+                uint64_t reserved_2_3:2;
+                uint64_t bp:2;
+                uint64_t reserved_6_7:2;
+                uint64_t en:2;
+                uint64_t reserved_10_31:22;
+                uint64_t tx_prt_bp:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } cnf71xx;
+};
+
+union cvmx_gmxx_tx_prts {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t prts:5;
+#else
+                uint64_t prts:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_tx_spi_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t tpa_clr:1;
+                uint64_t cont_pkt:1;
+#else
+                uint64_t cont_pkt:1;
+                uint64_t tpa_clr:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_tx_spi_max {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t slice:7;
+                uint64_t max2:8;
+                uint64_t max1:8;
+#else
+                uint64_t max1:8;
+                uint64_t max2:8;
+                uint64_t slice:7;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_gmxx_tx_spi_max_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t max2:8;
+                uint64_t max1:8;
+#else
+                uint64_t max1:8;
+                uint64_t max2:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xx;
+};
+
+union cvmx_gmxx_tx_spi_thresh {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t thresh:6;
+#else
+                uint64_t thresh:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_gmxx_tx_xaui_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t hg_pause_hgi:2;
+                uint64_t hg_en:1;
+                uint64_t reserved_7_7:1;
+                uint64_t ls_byp:1;
+                uint64_t ls:2;
+                uint64_t reserved_2_3:2;
+                uint64_t uni_en:1;
+                uint64_t dic_en:1;
+#else
+                uint64_t dic_en:1;
+                uint64_t uni_en:1;
+                uint64_t reserved_2_3:2;
+                uint64_t ls:2;
+                uint64_t ls_byp:1;
+                uint64_t reserved_7_7:1;
+                uint64_t hg_en:1;
+                uint64_t hg_pause_hgi:2;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
new file mode 100644
index 000000000..5420fa667
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -0,0 +1,399 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_GPIO_DEFS_H__
+#define __CVMX_GPIO_DEFS_H__
+
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
+#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
+
+union cvmx_gpio_bit_cfgx {
+        uint64_t u64;
+        struct cvmx_gpio_bit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:42;
+                uint64_t output_sel:5;
+                uint64_t synce_sel:2;
+                uint64_t clk_gen:1;
+                uint64_t clk_sel:2;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+#else
+                uint64_t tx_oe:1;
+                uint64_t rx_xor:1;
+                uint64_t int_en:1;
+                uint64_t int_type:1;
+                uint64_t fil_cnt:4;
+                uint64_t fil_sel:4;
+                uint64_t clk_sel:2;
+                uint64_t clk_gen:1;
+                uint64_t synce_sel:2;
+                uint64_t output_sel:5;
+                uint64_t reserved_21_63:42;
+#endif
+        } s;
+        struct cvmx_gpio_bit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+#else
+                uint64_t tx_oe:1;
+                uint64_t rx_xor:1;
+                uint64_t int_en:1;
+                uint64_t int_type:1;
+                uint64_t fil_cnt:4;
+                uint64_t fil_sel:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn30xx;
+        struct cvmx_gpio_bit_cfgx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t clk_gen:1;
+                uint64_t clk_sel:2;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+#else
+                uint64_t tx_oe:1;
+                uint64_t rx_xor:1;
+                uint64_t int_en:1;
+                uint64_t int_type:1;
+                uint64_t fil_cnt:4;
+                uint64_t fil_sel:4;
+                uint64_t clk_sel:2;
+                uint64_t clk_gen:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn52xx;
+};
+
+union cvmx_gpio_boot_ena {
+        uint64_t u64;
+        struct cvmx_gpio_boot_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t boot_ena:4;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t boot_ena:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_gpio_clk_genx {
+        uint64_t u64;
+        struct cvmx_gpio_clk_genx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t n:32;
+#else
+                uint64_t n:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_gpio_clk_qlmx {
+        uint64_t u64;
+        struct cvmx_gpio_clk_qlmx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t qlm_sel:3;
+                uint64_t reserved_3_7:5;
+                uint64_t div:1;
+                uint64_t lane_sel:2;
+#else
+                uint64_t lane_sel:2;
+                uint64_t div:1;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_sel:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+        struct cvmx_gpio_clk_qlmx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t qlm_sel:2;
+                uint64_t reserved_3_7:5;
+                uint64_t div:1;
+                uint64_t lane_sel:2;
+#else
+                uint64_t lane_sel:2;
+                uint64_t div:1;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_sel:2;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn61xx;
+        struct cvmx_gpio_clk_qlmx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t div:1;
+                uint64_t lane_sel:2;
+#else
+                uint64_t lane_sel:2;
+                uint64_t div:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn63xx;
+};
+
+union cvmx_gpio_dbg_ena {
+        uint64_t u64;
+        struct cvmx_gpio_dbg_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t dbg_ena:21;
+#else
+                uint64_t dbg_ena:21;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+};
+
+union cvmx_gpio_int_clr {
+        uint64_t u64;
+        struct cvmx_gpio_int_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t type:16;
+#else
+                uint64_t type:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_gpio_multi_cast {
+        uint64_t u64;
+        struct cvmx_gpio_multi_cast_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_gpio_pin_ena {
+        uint64_t u64;
+        struct cvmx_gpio_pin_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t ena19:1;
+                uint64_t ena18:1;
+                uint64_t reserved_0_17:18;
+#else
+                uint64_t reserved_0_17:18;
+                uint64_t ena18:1;
+                uint64_t ena19:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_gpio_rx_dat {
+        uint64_t u64;
+        struct cvmx_gpio_rx_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t dat:24;
+#else
+                uint64_t dat:24;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_gpio_rx_dat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dat:16;
+#else
+                uint64_t dat:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xx;
+        struct cvmx_gpio_rx_dat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t dat:20;
+#else
+                uint64_t dat:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gpio_tim_ctl {
+        uint64_t u64;
+        struct cvmx_gpio_tim_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t sel:4;
+#else
+                uint64_t sel:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_gpio_tx_clr {
+        uint64_t u64;
+        struct cvmx_gpio_tx_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t clr:24;
+#else
+                uint64_t clr:24;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_gpio_tx_clr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t clr:16;
+#else
+                uint64_t clr:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xx;
+        struct cvmx_gpio_tx_clr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t clr:20;
+#else
+                uint64_t clr:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gpio_tx_set {
+        uint64_t u64;
+        struct cvmx_gpio_tx_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t set:24;
+#else
+                uint64_t set:24;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_gpio_tx_set_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t set:16;
+#else
+                uint64_t set:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xx;
+        struct cvmx_gpio_tx_set_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t set:20;
+#else
+                uint64_t set:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn61xx;
+};
+
+union cvmx_gpio_xbit_cfgx {
+        uint64_t u64;
+        struct cvmx_gpio_xbit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t synce_sel:2;
+                uint64_t clk_gen:1;
+                uint64_t clk_sel:2;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+#else
+                uint64_t tx_oe:1;
+                uint64_t rx_xor:1;
+                uint64_t int_en:1;
+                uint64_t int_type:1;
+                uint64_t fil_cnt:4;
+                uint64_t fil_sel:4;
+                uint64_t clk_sel:2;
+                uint64_t clk_gen:1;
+                uint64_t synce_sel:2;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+        struct cvmx_gpio_xbit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t reserved_2_3:2;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+#else
+                uint64_t tx_oe:1;
+                uint64_t rx_xor:1;
+                uint64_t reserved_2_3:2;
+                uint64_t fil_cnt:4;
+                uint64_t fil_sel:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn30xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
new file mode 100644
index 000000000..ce52aafe7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -0,0 +1,124 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ *
+ */
+#ifndef __CVMX_HELPER_BOARD_H__
+#define __CVMX_HELPER_BOARD_H__
+
+#include <asm/octeon/cvmx-helper.h>
+
+enum cvmx_helper_board_usb_clock_types {
+        USB_CLOCK_TYPE_REF_12,
+        USB_CLOCK_TYPE_REF_24,
+        USB_CLOCK_TYPE_REF_48,
+        USB_CLOCK_TYPE_CRYSTAL_12,
+};
+
+typedef enum {
+        set_phy_link_flags_autoneg = 0x1,
+        set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
+        set_phy_link_flags_flow_control_enable = 0x1 << 1,
+        set_phy_link_flags_flow_control_disable = 0x2 << 1,
+        set_phy_link_flags_flow_control_mask = 0x3 << 1,        /* Mask for 2 bit wide flow control field */
+} cvmx_helper_board_set_phy_link_flags_types_t;
+
+/*
+ * Fake IPD port, the RGMII/MII interface may use different PHY, use
+ * this macro to return appropriate MIX address to read the PHY.
+ */
+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. A result of -1 means there isn't a MII capable PHY
+ * connected to this port. On chips supporting multiple MII
+ * busses the bus number is encoded in bits <15:8>.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: Octeon IPD port to get the MII address for.
+ *
+ * Returns MII PHY address and bus number or -1.
+ */
+extern int cvmx_helper_board_get_mii_address(int ipd_port);
+
+/**
+ * This function is the board specific method of determining an
+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs
+ * and are handled by the fall through case. This function must be
+ * updated for boards that don't have the normal Marvell PHYs.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * Returns The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+extern union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port);
+
+/**
+ * This function is called by cvmx_helper_interface_probe() after it
+ * determines the number of ports Octeon can support on a specific
+ * interface. This function is the per board location to override
+ * this value. It is called with the number of ports Octeon might
+ * support and should return the number of actual ports on the
+ * board.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @interface: Interface to probe
+ * @supported_ports:
+ *                  Number of ports Octeon supports.
+ *
+ * Returns Number of ports the actual board supports. Many times this will
+ *         simple be "support_ports".
+ */
+extern int __cvmx_helper_board_interface_probe(int interface,
+                                               int supported_ports);
+
+enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void);
+
+#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
new file mode 100644
index 000000000..5fc99189f
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
@@ -0,0 +1,33 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_HELPER_ERRATA_H__
+#define __CVMX_HELPER_ERRATA_H__
+
+extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-jtag.h b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
new file mode 100644
index 000000000..29f016ddb
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
@@ -0,0 +1,43 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ *  Helper utilities for qlm_jtag.
+ *
+ */
+
+#ifndef __CVMX_HELPER_JTAG_H__
+#define __CVMX_HELPER_JTAG_H__
+
+extern void cvmx_helper_qlm_jtag_init(void);
+extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
+extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
+extern void cvmx_helper_qlm_jtag_update(int qlm);
+
+#endif /* __CVMX_HELPER_JTAG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
new file mode 100644
index 000000000..077f0e9d3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
@@ -0,0 +1,60 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_LOOP_H__
+#define __CVMX_HELPER_LOOP_H__
+
+/**
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_loop_probe(int interface);
+static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
+
+/**
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_loop_enable(int interface);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
new file mode 100644
index 000000000..8df4c7faf
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -0,0 +1,61 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_NPI_H__
+#define __CVMX_HELPER_NPI_H__
+
+/**
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_npi_probe(int interface);
+#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
+
+/**
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_npi_enable(int interface);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
new file mode 100644
index 000000000..3e79a7f89
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -0,0 +1,93 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_RGMII_H__
+#define __CVMX_HELPER_RGMII_H__
+
+/**
+ * Probe RGMII ports and determine the number present
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of RGMII/GMII/MII ports (0-4).
+ */
+extern int __cvmx_helper_rgmii_probe(int interface);
+#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
+
+/**
+ * Put an RGMII interface in loopback mode. Internal packets sent
+ * out will be received back again on the same port. Externally
+ * received packets will echo back out.
+ *
+ * @port:   IPD port number to loop.
+ */
+extern void cvmx_helper_rgmii_internal_loopback(int port);
+
+/**
+ * Configure all of the ASX, GMX, and PKO registers required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @interface: PKO Interface to configure (0 or 1)
+ *
+ * Returns Zero on success
+ */
+extern int __cvmx_helper_rgmii_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern union cvmx_helper_link_info __cvmx_helper_rgmii_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get().
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_rgmii_link_set(int ipd_port,
+                                        union cvmx_helper_link_info link_info);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
new file mode 100644
index 000000000..8aac90f18
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -0,0 +1,87 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_SGMII_H__
+#define __CVMX_HELPER_SGMII_H__
+
+/**
+ * Probe a SGMII interface and determine the number of ports
+ * connected to it. The SGMII interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_sgmii_probe(int interface);
+extern int __cvmx_helper_sgmii_enumerate(int interface);
+
+/**
+ * Bringup and enable a SGMII interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get().
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_link_set(int ipd_port,
+                                        union cvmx_helper_link_info link_info);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
new file mode 100644
index 000000000..bc8cab936
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -0,0 +1,84 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for SPI initialization, configuration,
+ * and monitoring.
+ */
+#ifndef __CVMX_HELPER_SPI_H__
+#define __CVMX_HELPER_SPI_H__
+
+/**
+ * Probe a SPI interface and determine the number of ports
+ * connected to it. The SPI interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_spi_probe(int interface);
+extern int __cvmx_helper_spi_enumerate(int interface);
+
+/**
+ * Bringup and enable a SPI interface. After this call packet I/O
+ * should be fully functional. This is called with IPD enabled but
+ * PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern union cvmx_helper_link_info __cvmx_helper_spi_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get().
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_link_set(int ipd_port,
+                                      union cvmx_helper_link_info link_info);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
new file mode 100644
index 000000000..97b27a07c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -0,0 +1,192 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Small helper utilities.
+ *
+ */
+
+#ifndef __CVMX_HELPER_UTIL_H__
+#define __CVMX_HELPER_UTIL_H__
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @mode:   Mode to convert
+ *
+ * Returns String
+ */
+extern const char
+    *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
+
+/**
+ * Setup Random Early Drop to automatically begin dropping packets.
+ *
+ * @pass_thresh:
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @drop_thresh:
+ *               All incoming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * Returns Zero on success. Negative on failure
+ */
+extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
+
+/**
+ * Get the version of the CVMX libraries.
+ *
+ * Returns Version string. Note this buffer is allocated statically
+ *         and will be shared by all callers.
+ */
+extern const char *cvmx_helper_get_version(void);
+
+/**
+ * Setup the common GMX settings that determine the number of
+ * ports. These setting apply to almost all configurations of all
+ * chips.
+ *
+ * @interface: Interface to configure
+ * @num_ports: Number of ports on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
+
+/**
+ * Returns the IPD/PKO port number for a port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ * @port:      Port on the interface
+ *
+ * Returns IPD/PKO port number
+ */
+extern int cvmx_helper_get_ipd_port(int interface, int port);
+
+/**
+ * Returns the IPD/PKO port number for the first port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ *
+ * Returns IPD/PKO port number
+ */
+static inline int cvmx_helper_get_first_ipd_port(int interface)
+{
+        return cvmx_helper_get_ipd_port(interface, 0);
+}
+
+/**
+ * Returns the IPD/PKO port number for the last port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ *
+ * Returns IPD/PKO port number
+ */
+static inline int cvmx_helper_get_last_ipd_port(int interface)
+{
+        extern int cvmx_helper_ports_on_interface(int interface);
+
+        return cvmx_helper_get_first_ipd_port(interface) +
+               cvmx_helper_ports_on_interface(interface) - 1;
+}
+
+/**
+ * Free the packet buffers contained in a work queue entry.
+ * The work queue entry is not freed.
+ *
+ * @work:   Work queue entry with packet to free
+ */
+static inline void cvmx_helper_free_packet_data(struct cvmx_wqe *work)
+{
+        uint64_t number_buffers;
+        union cvmx_buf_ptr buffer_ptr;
+        union cvmx_buf_ptr next_buffer_ptr;
+        uint64_t start_of_buffer;
+
+        number_buffers = work->word2.s.bufs;
+        if (number_buffers == 0)
+                return;
+        buffer_ptr = work->packet_ptr;
+
+        /*
+         * Since the number of buffers is not zero, we know this is
+         * not a dynamic short packet. We need to check if it is a
+         * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
+         * true, we need to free all buffers except for the first
+         * one. The caller doesn't expect their WQE pointer to be
+         * freed
+         */
+        start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+        if (cvmx_ptr_to_phys(work) == start_of_buffer) {
+                next_buffer_ptr =
+                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+                buffer_ptr = next_buffer_ptr;
+                number_buffers--;
+        }
+
+        while (number_buffers--) {
+                /*
+                 * Remember the back pointer is in cache lines, not
+                 * 64bit words
+                 */
+                start_of_buffer =
+                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+                /*
+                 * Read pointer to next buffer before we free the
+                 * current buffer.
+                 */
+                next_buffer_ptr =
+                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+                cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
+                              buffer_ptr.s.pool, 0);
+                buffer_ptr = next_buffer_ptr;
+        }
+}
+
+/**
+ * Returns the interface number for an IPD/PKO port number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface number
+ */
+extern int cvmx_helper_get_interface_num(int ipd_port);
+
+/**
+ * Returns the interface index number for an IPD/PKO port
+ * number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface index number
+ */
+extern int cvmx_helper_get_interface_index_num(int ipd_port);
+
+#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
new file mode 100644
index 000000000..c18da2eba
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -0,0 +1,87 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_XAUI_H__
+#define __CVMX_HELPER_XAUI_H__
+
+/**
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_xaui_probe(int interface);
+extern int __cvmx_helper_xaui_enumerate(int interface);
+
+/**
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern union cvmx_helper_link_info __cvmx_helper_xaui_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get().
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_link_set(int ipd_port,
+                                       union cvmx_helper_link_info link_info);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
new file mode 100644
index 000000000..c6c99e28e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -0,0 +1,178 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Helper functions for common, but complicated tasks.
+ *
+ */
+
+#ifndef __CVMX_HELPER_H__
+#define __CVMX_HELPER_H__
+
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-wqe.h>
+
+typedef enum {
+        CVMX_HELPER_INTERFACE_MODE_DISABLED,
+        CVMX_HELPER_INTERFACE_MODE_RGMII,
+        CVMX_HELPER_INTERFACE_MODE_GMII,
+        CVMX_HELPER_INTERFACE_MODE_SPI,
+        CVMX_HELPER_INTERFACE_MODE_PCIE,
+        CVMX_HELPER_INTERFACE_MODE_XAUI,
+        CVMX_HELPER_INTERFACE_MODE_SGMII,
+        CVMX_HELPER_INTERFACE_MODE_PICMG,
+        CVMX_HELPER_INTERFACE_MODE_NPI,
+        CVMX_HELPER_INTERFACE_MODE_LOOP,
+} cvmx_helper_interface_mode_t;
+
+union cvmx_helper_link_info {
+        uint64_t u64;
+        struct {
+                uint64_t reserved_20_63:44;
+                uint64_t link_up:1;         /**< Is the physical link up? */
+                uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
+                uint64_t speed:18;          /**< Speed of the link in Mbps */
+        } s;
+};
+
+#include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-helper-loop.h>
+#include <asm/octeon/cvmx-helper-npi.h>
+#include <asm/octeon/cvmx-helper-rgmii.h>
+#include <asm/octeon/cvmx-helper-sgmii.h>
+#include <asm/octeon/cvmx-helper-spi.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-xaui.h>
+
+/**
+ * This function enables the IPD and also enables the packet interfaces.
+ * The packet interfaces (RGMII and SPI) must be enabled after the
+ * IPD.  This should be called by the user program after any additional
+ * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
+ * is not set in the executive-config.h file.
+ *
+ * Returns 0 on success
+ *         -1 on failure
+ */
+extern int cvmx_helper_ipd_and_packet_input_enable(void);
+
+/**
+ * Initialize the PIP, IPD, and PKO hardware to support
+ * simple priority based queues for the ethernet ports. Each
+ * port is configured with a number of priority queues based
+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
+ * priority than the previous.
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_global(void);
+
+/**
+ * Does core local initialization for packet io
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_local(void);
+
+/**
+ * Returns the number of ports on the given interface.
+ * The interface must be initialized before the port count
+ * can be returned.
+ *
+ * @interface: Which interface to return port count for.
+ *
+ * Returns Port count for interface
+ *         -1 for uninitialized interface
+ */
+extern int cvmx_helper_ports_on_interface(int interface);
+
+/**
+ * Return the number of interfaces the chip has. Each interface
+ * may have multiple ports. Most chips support two interfaces,
+ * but the CNX0XX and CNX1XX are exceptions. These only support
+ * one interface.
+ *
+ * Returns Number of interfaces on chip
+ */
+extern int cvmx_helper_get_number_of_interfaces(void);
+
+/**
+ * Get the operating mode of an interface. Depending on the Octeon
+ * chip and configuration, this function returns an enumeration
+ * of the type of packet I/O supported by an interface.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Mode of the interface. Unknown or unsupported interfaces return
+ *         DISABLED.
+ */
+extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
+                                                                   interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get().
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_helper_link_set(int ipd_port,
+                                union cvmx_helper_link_info link_info);
+
+/**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_helper_interface_probe(int interface);
+extern int cvmx_helper_interface_enumerate(int interface);
+
+#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
new file mode 100644
index 000000000..989b67bba
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -0,0 +1,903 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_IOB_DEFS_H__
+#define __CVMX_IOB_DEFS_H__
+
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
+#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
+#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
+#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
+#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
+#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
+#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
+#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
+#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
+#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
+#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
+#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
+
+union cvmx_iob_bist_status {
+        uint64_t u64;
+        struct cvmx_iob_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+#else
+                uint64_t icd:1;
+                uint64_t ibd:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+        struct cvmx_iob_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t icnrcb:1;
+                uint64_t icr0:1;
+                uint64_t icr1:1;
+                uint64_t icnr1:1;
+                uint64_t icnr0:1;
+                uint64_t ibdr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibr1:1;
+                uint64_t icnrt:1;
+                uint64_t ibrq0:1;
+                uint64_t ibrq1:1;
+                uint64_t icrn0:1;
+                uint64_t icrn1:1;
+                uint64_t icrp0:1;
+                uint64_t icrp1:1;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+#else
+                uint64_t icd:1;
+                uint64_t ibd:1;
+                uint64_t icrp1:1;
+                uint64_t icrp0:1;
+                uint64_t icrn1:1;
+                uint64_t icrn0:1;
+                uint64_t ibrq1:1;
+                uint64_t ibrq0:1;
+                uint64_t icnrt:1;
+                uint64_t ibr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibdr0:1;
+                uint64_t icnr0:1;
+                uint64_t icnr1:1;
+                uint64_t icr1:1;
+                uint64_t icr0:1;
+                uint64_t icnrcb:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn30xx;
+        struct cvmx_iob_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t xmdfif:1;
+                uint64_t xmcfif:1;
+                uint64_t iorfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iocfif:1;
+                uint64_t icnrcb:1;
+                uint64_t icr0:1;
+                uint64_t icr1:1;
+                uint64_t icnr1:1;
+                uint64_t icnr0:1;
+                uint64_t ibdr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibr1:1;
+                uint64_t icnrt:1;
+                uint64_t ibrq0:1;
+                uint64_t ibrq1:1;
+                uint64_t icrn0:1;
+                uint64_t icrn1:1;
+                uint64_t icrp0:1;
+                uint64_t icrp1:1;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+#else
+                uint64_t icd:1;
+                uint64_t ibd:1;
+                uint64_t icrp1:1;
+                uint64_t icrp0:1;
+                uint64_t icrn1:1;
+                uint64_t icrn0:1;
+                uint64_t ibrq1:1;
+                uint64_t ibrq0:1;
+                uint64_t icnrt:1;
+                uint64_t ibr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibdr0:1;
+                uint64_t icnr0:1;
+                uint64_t icnr1:1;
+                uint64_t icr1:1;
+                uint64_t icr0:1;
+                uint64_t icnrcb:1;
+                uint64_t iocfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iorfif:1;
+                uint64_t xmcfif:1;
+                uint64_t xmdfif:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } cn61xx;
+        struct cvmx_iob_bist_status_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t xmdfif:1;
+                uint64_t xmcfif:1;
+                uint64_t iorfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iocfif:1;
+                uint64_t icnrcb:1;
+                uint64_t icr0:1;
+                uint64_t icr1:1;
+                uint64_t icnr0:1;
+                uint64_t ibr0:1;
+                uint64_t ibr1:1;
+                uint64_t icnrt:1;
+                uint64_t ibrq0:1;
+                uint64_t ibrq1:1;
+                uint64_t icrn0:1;
+                uint64_t icrn1:1;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+#else
+                uint64_t icd:1;
+                uint64_t ibd:1;
+                uint64_t icrn1:1;
+                uint64_t icrn0:1;
+                uint64_t ibrq1:1;
+                uint64_t ibrq0:1;
+                uint64_t icnrt:1;
+                uint64_t ibr1:1;
+                uint64_t ibr0:1;
+                uint64_t icnr0:1;
+                uint64_t icr1:1;
+                uint64_t icr0:1;
+                uint64_t icnrcb:1;
+                uint64_t iocfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iorfif:1;
+                uint64_t xmcfif:1;
+                uint64_t xmdfif:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn68xx;
+};
+
+union cvmx_iob_ctl_status {
+        uint64_t u64;
+        struct cvmx_iob_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t fif_dly:1;
+                uint64_t xmc_per:4;
+                uint64_t reserved_5_5:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t reserved_5_5:1;
+                uint64_t xmc_per:4;
+                uint64_t fif_dly:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+        struct cvmx_iob_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn30xx;
+        struct cvmx_iob_ctl_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t rr_mode:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t rr_mode:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn52xx;
+        struct cvmx_iob_ctl_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t fif_dly:1;
+                uint64_t xmc_per:4;
+                uint64_t rr_mode:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t rr_mode:1;
+                uint64_t xmc_per:4;
+                uint64_t fif_dly:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn61xx;
+        struct cvmx_iob_ctl_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t xmc_per:4;
+                uint64_t rr_mode:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t rr_mode:1;
+                uint64_t xmc_per:4;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn63xx;
+        struct cvmx_iob_ctl_status_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t fif_dly:1;
+                uint64_t xmc_per:4;
+                uint64_t rsvr5:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+#else
+                uint64_t fau_end:1;
+                uint64_t dwb_enb:1;
+                uint64_t pko_enb:1;
+                uint64_t inb_mat:1;
+                uint64_t outb_mat:1;
+                uint64_t rsvr5:1;
+                uint64_t xmc_per:4;
+                uint64_t fif_dly:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn68xx;
+};
+
+union cvmx_iob_dwb_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_dwb_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_fau_timeout {
+        uint64_t u64;
+        struct cvmx_iob_fau_timeout_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t tout_enb:1;
+                uint64_t tout_val:12;
+#else
+                uint64_t tout_val:12;
+                uint64_t tout_enb:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+};
+
+union cvmx_iob_i2c_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_i2c_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_inb_control_match {
+        uint64_t u64;
+        struct cvmx_iob_inb_control_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t mask:8;
+                uint64_t opc:4;
+                uint64_t dst:9;
+                uint64_t src:8;
+#else
+                uint64_t src:8;
+                uint64_t dst:9;
+                uint64_t opc:4;
+                uint64_t mask:8;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+union cvmx_iob_inb_control_match_enb {
+        uint64_t u64;
+        struct cvmx_iob_inb_control_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t mask:8;
+                uint64_t opc:4;
+                uint64_t dst:9;
+                uint64_t src:8;
+#else
+                uint64_t src:8;
+                uint64_t dst:9;
+                uint64_t opc:4;
+                uint64_t mask:8;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+union cvmx_iob_inb_data_match {
+        uint64_t u64;
+        struct cvmx_iob_inb_data_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_iob_inb_data_match_enb {
+        uint64_t u64;
+        struct cvmx_iob_inb_data_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_iob_int_enb {
+        uint64_t u64;
+        struct cvmx_iob_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t p_dat:1;
+                uint64_t np_dat:1;
+                uint64_t p_eop:1;
+                uint64_t p_sop:1;
+                uint64_t np_eop:1;
+                uint64_t np_sop:1;
+#else
+                uint64_t np_sop:1;
+                uint64_t np_eop:1;
+                uint64_t p_sop:1;
+                uint64_t p_eop:1;
+                uint64_t np_dat:1;
+                uint64_t p_dat:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+        struct cvmx_iob_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t p_eop:1;
+                uint64_t p_sop:1;
+                uint64_t np_eop:1;
+                uint64_t np_sop:1;
+#else
+                uint64_t np_sop:1;
+                uint64_t np_eop:1;
+                uint64_t p_sop:1;
+                uint64_t p_eop:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_iob_int_enb_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } cn68xx;
+};
+
+union cvmx_iob_int_sum {
+        uint64_t u64;
+        struct cvmx_iob_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t p_dat:1;
+                uint64_t np_dat:1;
+                uint64_t p_eop:1;
+                uint64_t p_sop:1;
+                uint64_t np_eop:1;
+                uint64_t np_sop:1;
+#else
+                uint64_t np_sop:1;
+                uint64_t np_eop:1;
+                uint64_t p_sop:1;
+                uint64_t p_eop:1;
+                uint64_t np_dat:1;
+                uint64_t p_dat:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+        struct cvmx_iob_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t p_eop:1;
+                uint64_t p_sop:1;
+                uint64_t np_eop:1;
+                uint64_t np_sop:1;
+#else
+                uint64_t np_sop:1;
+                uint64_t np_eop:1;
+                uint64_t p_sop:1;
+                uint64_t p_eop:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_iob_int_sum_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } cn68xx;
+};
+
+union cvmx_iob_n2c_l2c_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_n2c_l2c_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_n2c_rsp_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_n2c_rsp_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_com_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_outb_com_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_control_match {
+        uint64_t u64;
+        struct cvmx_iob_outb_control_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t mask:8;
+                uint64_t eot:1;
+                uint64_t dst:8;
+                uint64_t src:9;
+#else
+                uint64_t src:9;
+                uint64_t dst:8;
+                uint64_t eot:1;
+                uint64_t mask:8;
+                uint64_t reserved_26_63:38;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_control_match_enb {
+        uint64_t u64;
+        struct cvmx_iob_outb_control_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t mask:8;
+                uint64_t eot:1;
+                uint64_t dst:8;
+                uint64_t src:9;
+#else
+                uint64_t src:9;
+                uint64_t dst:8;
+                uint64_t eot:1;
+                uint64_t mask:8;
+                uint64_t reserved_26_63:38;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_data_match {
+        uint64_t u64;
+        struct cvmx_iob_outb_data_match_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_data_match_enb {
+        uint64_t u64;
+        struct cvmx_iob_outb_data_match_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_fpa_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_outb_fpa_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_outb_req_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_outb_req_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_p2c_req_pri_cnt {
+        uint64_t u64;
+        struct cvmx_iob_p2c_req_pri_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t cnt_enb:1;
+                uint64_t cnt_val:15;
+#else
+                uint64_t cnt_val:15;
+                uint64_t cnt_enb:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_iob_pkt_err {
+        uint64_t u64;
+        struct cvmx_iob_pkt_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t vport:6;
+                uint64_t port:6;
+#else
+                uint64_t port:6;
+                uint64_t vport:6;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_iob_pkt_err_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t port:6;
+#else
+                uint64_t port:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn30xx;
+};
+
+union cvmx_iob_to_cmb_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_cmb_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t ncb_rd:3;
+                uint64_t ncb_wr:3;
+#else
+                uint64_t ncb_wr:3;
+                uint64_t ncb_rd:3;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+        struct cvmx_iob_to_cmb_credits_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t pko_rd:3;
+                uint64_t ncb_rd:3;
+                uint64_t ncb_wr:3;
+#else
+                uint64_t ncb_wr:3;
+                uint64_t ncb_rd:3;
+                uint64_t pko_rd:3;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn52xx;
+        struct cvmx_iob_to_cmb_credits_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t dwb:3;
+                uint64_t ncb_rd:3;
+                uint64_t ncb_wr:3;
+#else
+                uint64_t ncb_wr:3;
+                uint64_t ncb_rd:3;
+                uint64_t dwb:3;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn68xx;
+};
+
+union cvmx_iob_to_ncb_did_00_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_00_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_111_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_111_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_223_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_223_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_24_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_24_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_32_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_32_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_40_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_40_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_55_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_55_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_64_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_64_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_79_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_79_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_96_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_96_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_iob_to_ncb_did_98_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_ncb_did_98_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t crd:7;
+#else
+                uint64_t crd:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
new file mode 100644
index 000000000..c0a4ac7b4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -0,0 +1,1472 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_IPD_DEFS_H__
+#define __CVMX_IPD_DEFS_H__
+
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
+#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
+#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
+#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
+#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
+#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
+
+union cvmx_ipd_1st_mbuff_skip {
+        uint64_t u64;
+        struct cvmx_ipd_1st_mbuff_skip_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t skip_sz:6;
+#else
+                uint64_t skip_sz:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_ipd_1st_next_ptr_back {
+        uint64_t u64;
+        struct cvmx_ipd_1st_next_ptr_back_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t back:4;
+#else
+                uint64_t back:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_ipd_2nd_next_ptr_back {
+        uint64_t u64;
+        struct cvmx_ipd_2nd_next_ptr_back_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t back:4;
+#else
+                uint64_t back:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_ipd_bist_status {
+        uint64_t u64;
+        struct cvmx_ipd_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t iiwo1:1;
+                uint64_t iiwo0:1;
+                uint64_t iio1:1;
+                uint64_t iio0:1;
+                uint64_t pbm4:1;
+                uint64_t csr_mem:1;
+                uint64_t csr_ncmd:1;
+                uint64_t pwq_wqed:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_pow:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t pbm3:1;
+                uint64_t pbm2:1;
+                uint64_t pbm1:1;
+                uint64_t pbm0:1;
+                uint64_t pbm_word:1;
+                uint64_t pwq1:1;
+                uint64_t pwq0:1;
+                uint64_t prc_off:1;
+                uint64_t ipd_old:1;
+                uint64_t ipd_new:1;
+                uint64_t pwp:1;
+#else
+                uint64_t pwp:1;
+                uint64_t ipd_new:1;
+                uint64_t ipd_old:1;
+                uint64_t prc_off:1;
+                uint64_t pwq0:1;
+                uint64_t pwq1:1;
+                uint64_t pbm_word:1;
+                uint64_t pbm0:1;
+                uint64_t pbm1:1;
+                uint64_t pbm2:1;
+                uint64_t pbm3:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t pwq_pow:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_wqed:1;
+                uint64_t csr_ncmd:1;
+                uint64_t csr_mem:1;
+                uint64_t pbm4:1;
+                uint64_t iio0:1;
+                uint64_t iio1:1;
+                uint64_t iiwo0:1;
+                uint64_t iiwo1:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_ipd_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t pwq_wqed:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_pow:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t pbm3:1;
+                uint64_t pbm2:1;
+                uint64_t pbm1:1;
+                uint64_t pbm0:1;
+                uint64_t pbm_word:1;
+                uint64_t pwq1:1;
+                uint64_t pwq0:1;
+                uint64_t prc_off:1;
+                uint64_t ipd_old:1;
+                uint64_t ipd_new:1;
+                uint64_t pwp:1;
+#else
+                uint64_t pwp:1;
+                uint64_t ipd_new:1;
+                uint64_t ipd_old:1;
+                uint64_t prc_off:1;
+                uint64_t pwq0:1;
+                uint64_t pwq1:1;
+                uint64_t pbm_word:1;
+                uint64_t pbm0:1;
+                uint64_t pbm1:1;
+                uint64_t pbm2:1;
+                uint64_t pbm3:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t pwq_pow:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_wqed:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_bist_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t csr_mem:1;
+                uint64_t csr_ncmd:1;
+                uint64_t pwq_wqed:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_pow:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t pbm3:1;
+                uint64_t pbm2:1;
+                uint64_t pbm1:1;
+                uint64_t pbm0:1;
+                uint64_t pbm_word:1;
+                uint64_t pwq1:1;
+                uint64_t pwq0:1;
+                uint64_t prc_off:1;
+                uint64_t ipd_old:1;
+                uint64_t ipd_new:1;
+                uint64_t pwp:1;
+#else
+                uint64_t pwp:1;
+                uint64_t ipd_new:1;
+                uint64_t ipd_old:1;
+                uint64_t prc_off:1;
+                uint64_t pwq0:1;
+                uint64_t pwq1:1;
+                uint64_t pbm_word:1;
+                uint64_t pbm0:1;
+                uint64_t pbm1:1;
+                uint64_t pbm2:1;
+                uint64_t pbm3:1;
+                uint64_t ipq_pbe0:1;
+                uint64_t ipq_pbe1:1;
+                uint64_t pwq_pow:1;
+                uint64_t pwq_wp1:1;
+                uint64_t pwq_wqed:1;
+                uint64_t csr_ncmd:1;
+                uint64_t csr_mem:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn52xx;
+};
+
+union cvmx_ipd_bp_prt_red_end {
+        uint64_t u64;
+        struct cvmx_ipd_bp_prt_red_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t prt_enb:48;
+#else
+                uint64_t prt_enb:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_ipd_bp_prt_red_end_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t prt_enb:36;
+#else
+                uint64_t prt_enb:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t prt_enb:40;
+#else
+                uint64_t prt_enb:40;
+                uint64_t reserved_40_63:24;
+#endif
+        } cn52xx;
+        struct cvmx_ipd_bp_prt_red_end_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t prt_enb:44;
+#else
+                uint64_t prt_enb:44;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn63xx;
+};
+
+union cvmx_ipd_bpidx_mbuf_th {
+        uint64_t u64;
+        struct cvmx_ipd_bpidx_mbuf_th_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+#else
+                uint64_t page_cnt:17;
+                uint64_t bp_enb:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_ipd_bpid_bp_counterx {
+        uint64_t u64;
+        struct cvmx_ipd_bpid_bp_counterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+#else
+                uint64_t cnt_val:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_ipd_clk_count {
+        uint64_t u64;
+        struct cvmx_ipd_clk_count_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t clk_cnt:64;
+#else
+                uint64_t clk_cnt:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_credits {
+        uint64_t u64;
+        struct cvmx_ipd_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t iob_wrc:8;
+                uint64_t iob_wr:8;
+#else
+                uint64_t iob_wr:8;
+                uint64_t iob_wrc:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_ipd_ctl_status {
+        uint64_t u64;
+        struct cvmx_ipd_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t use_sop:1;
+                uint64_t rst_done:1;
+                uint64_t clken:1;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t len_m8:1;
+                uint64_t pkt_off:1;
+                uint64_t ipd_full:1;
+                uint64_t pq_nabuf:1;
+                uint64_t pq_apkt:1;
+                uint64_t no_wptr:1;
+                uint64_t clken:1;
+                uint64_t rst_done:1;
+                uint64_t use_sop:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+        struct cvmx_ipd_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t len_m8:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_ctl_status_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn38xxp2;
+        struct cvmx_ipd_ctl_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t len_m8:1;
+                uint64_t pkt_off:1;
+                uint64_t ipd_full:1;
+                uint64_t pq_nabuf:1;
+                uint64_t pq_apkt:1;
+                uint64_t no_wptr:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn50xx;
+        struct cvmx_ipd_ctl_status_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t len_m8:1;
+                uint64_t pkt_off:1;
+                uint64_t ipd_full:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn58xx;
+        struct cvmx_ipd_ctl_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t clken:1;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+#else
+                uint64_t ipd_en:1;
+                uint64_t opc_mode:2;
+                uint64_t pbp_en:1;
+                uint64_t wqe_lend:1;
+                uint64_t pkt_lend:1;
+                uint64_t naddbuf:1;
+                uint64_t addpkt:1;
+                uint64_t reset:1;
+                uint64_t len_m8:1;
+                uint64_t pkt_off:1;
+                uint64_t ipd_full:1;
+                uint64_t pq_nabuf:1;
+                uint64_t pq_apkt:1;
+                uint64_t no_wptr:1;
+                uint64_t clken:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_ipd_ecc_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t pm3_syn:2;
+                uint64_t pm2_syn:2;
+                uint64_t pm1_syn:2;
+                uint64_t pm0_syn:2;
+#else
+                uint64_t pm0_syn:2;
+                uint64_t pm1_syn:2;
+                uint64_t pm2_syn:2;
+                uint64_t pm3_syn:2;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_ipd_free_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_free_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t max_cnts:7;
+                uint64_t wraddr:8;
+                uint64_t praddr:8;
+                uint64_t cena:1;
+                uint64_t raddr:8;
+#else
+                uint64_t raddr:8;
+                uint64_t cena:1;
+                uint64_t praddr:8;
+                uint64_t wraddr:8;
+                uint64_t max_cnts:7;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_ipd_free_ptr_value {
+        uint64_t u64;
+        struct cvmx_ipd_free_ptr_value_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t ptr:33;
+#else
+                uint64_t ptr:33;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_ipd_hold_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_hold_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_43_63:21;
+                uint64_t ptr:33;
+                uint64_t max_pkt:3;
+                uint64_t praddr:3;
+                uint64_t cena:1;
+                uint64_t raddr:3;
+#else
+                uint64_t raddr:3;
+                uint64_t cena:1;
+                uint64_t praddr:3;
+                uint64_t max_pkt:3;
+                uint64_t ptr:33;
+                uint64_t reserved_43_63:21;
+#endif
+        } s;
+};
+
+union cvmx_ipd_int_enb {
+        uint64_t u64;
+        struct cvmx_ipd_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t pw3_dbe:1;
+                uint64_t pw3_sbe:1;
+                uint64_t pw2_dbe:1;
+                uint64_t pw2_sbe:1;
+                uint64_t pw1_dbe:1;
+                uint64_t pw1_sbe:1;
+                uint64_t pw0_dbe:1;
+                uint64_t pw0_sbe:1;
+                uint64_t dat:1;
+                uint64_t eop:1;
+                uint64_t sop:1;
+                uint64_t pq_sub:1;
+                uint64_t pq_add:1;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t pq_add:1;
+                uint64_t pq_sub:1;
+                uint64_t sop:1;
+                uint64_t eop:1;
+                uint64_t dat:1;
+                uint64_t pw0_sbe:1;
+                uint64_t pw0_dbe:1;
+                uint64_t pw1_sbe:1;
+                uint64_t pw1_dbe:1;
+                uint64_t pw2_sbe:1;
+                uint64_t pw2_dbe:1;
+                uint64_t pw3_sbe:1;
+                uint64_t pw3_dbe:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_ipd_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_int_enb_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn38xx;
+        struct cvmx_ipd_int_enb_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t pq_sub:1;
+                uint64_t pq_add:1;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t pq_add:1;
+                uint64_t pq_sub:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn52xx;
+};
+
+union cvmx_ipd_int_sum {
+        uint64_t u64;
+        struct cvmx_ipd_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t pw3_dbe:1;
+                uint64_t pw3_sbe:1;
+                uint64_t pw2_dbe:1;
+                uint64_t pw2_sbe:1;
+                uint64_t pw1_dbe:1;
+                uint64_t pw1_sbe:1;
+                uint64_t pw0_dbe:1;
+                uint64_t pw0_sbe:1;
+                uint64_t dat:1;
+                uint64_t eop:1;
+                uint64_t sop:1;
+                uint64_t pq_sub:1;
+                uint64_t pq_add:1;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t pq_add:1;
+                uint64_t pq_sub:1;
+                uint64_t sop:1;
+                uint64_t eop:1;
+                uint64_t dat:1;
+                uint64_t pw0_sbe:1;
+                uint64_t pw0_dbe:1;
+                uint64_t pw1_sbe:1;
+                uint64_t pw1_dbe:1;
+                uint64_t pw2_sbe:1;
+                uint64_t pw2_dbe:1;
+                uint64_t pw3_sbe:1;
+                uint64_t pw3_dbe:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_ipd_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_int_sum_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn38xx;
+        struct cvmx_ipd_int_sum_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t pq_sub:1;
+                uint64_t pq_add:1;
+                uint64_t bc_ovr:1;
+                uint64_t d_coll:1;
+                uint64_t c_coll:1;
+                uint64_t cc_ovr:1;
+                uint64_t dc_ovr:1;
+                uint64_t bp_sub:1;
+                uint64_t prc_par3:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par0:1;
+#else
+                uint64_t prc_par0:1;
+                uint64_t prc_par1:1;
+                uint64_t prc_par2:1;
+                uint64_t prc_par3:1;
+                uint64_t bp_sub:1;
+                uint64_t dc_ovr:1;
+                uint64_t cc_ovr:1;
+                uint64_t c_coll:1;
+                uint64_t d_coll:1;
+                uint64_t bc_ovr:1;
+                uint64_t pq_add:1;
+                uint64_t pq_sub:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn52xx;
+};
+
+union cvmx_ipd_next_pkt_ptr {
+        uint64_t u64;
+        struct cvmx_ipd_next_pkt_ptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t ptr:33;
+#else
+                uint64_t ptr:33;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_ipd_next_wqe_ptr {
+        uint64_t u64;
+        struct cvmx_ipd_next_wqe_ptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t ptr:33;
+#else
+                uint64_t ptr:33;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_ipd_not_1st_mbuff_skip {
+        uint64_t u64;
+        struct cvmx_ipd_not_1st_mbuff_skip_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t skip_sz:6;
+#else
+                uint64_t skip_sz:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_ipd_on_bp_drop_pktx {
+        uint64_t u64;
+        struct cvmx_ipd_on_bp_drop_pktx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t prt_enb:64;
+#else
+                uint64_t prt_enb:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_packet_mbuff_size {
+        uint64_t u64;
+        struct cvmx_ipd_packet_mbuff_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t mb_size:12;
+#else
+                uint64_t mb_size:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_ipd_pkt_err {
+        uint64_t u64;
+        struct cvmx_ipd_pkt_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t reasm:6;
+#else
+                uint64_t reasm:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_ipd_pkt_ptr_valid {
+        uint64_t u64;
+        struct cvmx_ipd_pkt_ptr_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t ptr:29;
+#else
+                uint64_t ptr:29;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+union cvmx_ipd_portx_bp_page_cnt {
+        uint64_t u64;
+        struct cvmx_ipd_portx_bp_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+#else
+                uint64_t page_cnt:17;
+                uint64_t bp_enb:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_ipd_portx_bp_page_cnt2 {
+        uint64_t u64;
+        struct cvmx_ipd_portx_bp_page_cnt2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+#else
+                uint64_t page_cnt:17;
+                uint64_t bp_enb:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_ipd_portx_bp_page_cnt3 {
+        uint64_t u64;
+        struct cvmx_ipd_portx_bp_page_cnt3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+#else
+                uint64_t page_cnt:17;
+                uint64_t bp_enb:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_bp_counters2_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters2_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+#else
+                uint64_t cnt_val:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_bp_counters3_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters3_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+#else
+                uint64_t cnt_val:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_bp_counters4_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters4_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+#else
+                uint64_t cnt_val:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_bp_counters_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters_pairx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+#else
+                uint64_t cnt_val:25;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_port_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t ptr:33;
+                uint64_t max_pkt:7;
+                uint64_t cena:1;
+                uint64_t raddr:7;
+#else
+                uint64_t raddr:7;
+                uint64_t cena:1;
+                uint64_t max_pkt:7;
+                uint64_t ptr:33;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_qos_x_cnt {
+        uint64_t u64;
+        struct cvmx_ipd_port_qos_x_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wmark:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t wmark:32;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_qos_intx {
+        uint64_t u64;
+        struct cvmx_ipd_port_qos_intx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t intr:64;
+#else
+                uint64_t intr:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_qos_int_enbx {
+        uint64_t u64;
+        struct cvmx_ipd_port_qos_int_enbx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t enb:64;
+#else
+                uint64_t enb:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_port_sopx {
+        uint64_t u64;
+        struct cvmx_ipd_port_sopx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t sop:64;
+#else
+                uint64_t sop:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_prc_hold_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t max_pkt:3;
+                uint64_t praddr:3;
+                uint64_t ptr:29;
+                uint64_t cena:1;
+                uint64_t raddr:3;
+#else
+                uint64_t raddr:3;
+                uint64_t cena:1;
+                uint64_t ptr:29;
+                uint64_t praddr:3;
+                uint64_t max_pkt:3;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+};
+
+union cvmx_ipd_prc_port_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t max_pkt:7;
+                uint64_t ptr:29;
+                uint64_t cena:1;
+                uint64_t raddr:7;
+#else
+                uint64_t raddr:7;
+                uint64_t cena:1;
+                uint64_t ptr:29;
+                uint64_t max_pkt:7;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_ipd_ptr_count {
+        uint64_t u64;
+        struct cvmx_ipd_ptr_count_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t pktv_cnt:1;
+                uint64_t wqev_cnt:1;
+                uint64_t pfif_cnt:3;
+                uint64_t pkt_pcnt:7;
+                uint64_t wqe_pcnt:7;
+#else
+                uint64_t wqe_pcnt:7;
+                uint64_t pkt_pcnt:7;
+                uint64_t pfif_cnt:3;
+                uint64_t wqev_cnt:1;
+                uint64_t pktv_cnt:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } s;
+};
+
+union cvmx_ipd_pwp_ptr_fifo_ctl {
+        uint64_t u64;
+        struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t max_cnts:7;
+                uint64_t wraddr:8;
+                uint64_t praddr:8;
+                uint64_t ptr:29;
+                uint64_t cena:1;
+                uint64_t raddr:8;
+#else
+                uint64_t raddr:8;
+                uint64_t cena:1;
+                uint64_t ptr:29;
+                uint64_t praddr:8;
+                uint64_t wraddr:8;
+                uint64_t max_cnts:7;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+};
+
+union cvmx_ipd_qosx_red_marks {
+        uint64_t u64;
+        struct cvmx_ipd_qosx_red_marks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t drop:32;
+                uint64_t pass:32;
+#else
+                uint64_t pass:32;
+                uint64_t drop:32;
+#endif
+        } s;
+};
+
+union cvmx_ipd_que0_free_page_cnt {
+        uint64_t u64;
+        struct cvmx_ipd_que0_free_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t q0_pcnt:32;
+#else
+                uint64_t q0_pcnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_ipd_red_bpid_enablex {
+        uint64_t u64;
+        struct cvmx_ipd_red_bpid_enablex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t prt_enb:64;
+#else
+                uint64_t prt_enb:64;
+#endif
+        } s;
+};
+
+union cvmx_ipd_red_delay {
+        uint64_t u64;
+        struct cvmx_ipd_red_delay_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t prb_dly:14;
+                uint64_t avg_dly:14;
+#else
+                uint64_t avg_dly:14;
+                uint64_t prb_dly:14;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+};
+
+union cvmx_ipd_red_port_enable {
+        uint64_t u64;
+        struct cvmx_ipd_red_port_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t prb_dly:14;
+                uint64_t avg_dly:14;
+                uint64_t prt_enb:36;
+#else
+                uint64_t prt_enb:36;
+                uint64_t avg_dly:14;
+                uint64_t prb_dly:14;
+#endif
+        } s;
+};
+
+union cvmx_ipd_red_port_enable2 {
+        uint64_t u64;
+        struct cvmx_ipd_red_port_enable2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t prt_enb:12;
+#else
+                uint64_t prt_enb:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_ipd_red_port_enable2_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t prt_enb:4;
+#else
+                uint64_t prt_enb:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn52xx;
+        struct cvmx_ipd_red_port_enable2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t prt_enb:8;
+#else
+                uint64_t prt_enb:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn63xx;
+};
+
+union cvmx_ipd_red_quex_param {
+        uint64_t u64;
+        struct cvmx_ipd_red_quex_param_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t use_pcnt:1;
+                uint64_t new_con:8;
+                uint64_t avg_con:8;
+                uint64_t prb_con:32;
+#else
+                uint64_t prb_con:32;
+                uint64_t avg_con:8;
+                uint64_t new_con:8;
+                uint64_t use_pcnt:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+};
+
+union cvmx_ipd_req_wgt {
+        uint64_t u64;
+        struct cvmx_ipd_req_wgt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wgt7:8;
+                uint64_t wgt6:8;
+                uint64_t wgt5:8;
+                uint64_t wgt4:8;
+                uint64_t wgt3:8;
+                uint64_t wgt2:8;
+                uint64_t wgt1:8;
+                uint64_t wgt0:8;
+#else
+                uint64_t wgt0:8;
+                uint64_t wgt1:8;
+                uint64_t wgt2:8;
+                uint64_t wgt3:8;
+                uint64_t wgt4:8;
+                uint64_t wgt5:8;
+                uint64_t wgt6:8;
+                uint64_t wgt7:8;
+#endif
+        } s;
+};
+
+union cvmx_ipd_sub_port_bp_page_cnt {
+        uint64_t u64;
+        struct cvmx_ipd_sub_port_bp_page_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t port:6;
+                uint64_t page_cnt:25;
+#else
+                uint64_t page_cnt:25;
+                uint64_t port:6;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_ipd_sub_port_fcs {
+        uint64_t u64;
+        struct cvmx_ipd_sub_port_fcs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t port_bit2:4;
+                uint64_t reserved_32_35:4;
+                uint64_t port_bit:32;
+#else
+                uint64_t port_bit:32;
+                uint64_t reserved_32_35:4;
+                uint64_t port_bit2:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+        struct cvmx_ipd_sub_port_fcs_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t port_bit:3;
+#else
+                uint64_t port_bit:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+        struct cvmx_ipd_sub_port_fcs_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t port_bit:32;
+#else
+                uint64_t port_bit:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+};
+
+union cvmx_ipd_sub_port_qos_cnt {
+        uint64_t u64;
+        struct cvmx_ipd_sub_port_qos_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_41_63:23;
+                uint64_t port_qos:9;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t port_qos:9;
+                uint64_t reserved_41_63:23;
+#endif
+        } s;
+};
+
+union cvmx_ipd_wqe_fpa_queue {
+        uint64_t u64;
+        struct cvmx_ipd_wqe_fpa_queue_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t wqe_pool:3;
+#else
+                uint64_t wqe_pool:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_ipd_wqe_ptr_valid {
+        uint64_t u64;
+        struct cvmx_ipd_wqe_ptr_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t ptr:29;
+#else
+                uint64_t ptr:29;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
new file mode 100644
index 000000000..adab7b54c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -0,0 +1,339 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Interface to the hardware Input Packet Data unit.
+ */
+
+#ifndef __CVMX_IPD_H__
+#define __CVMX_IPD_H__
+
+#include <asm/octeon/octeon-feature.h>
+
+#include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+
+enum cvmx_ipd_mode {
+   CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
+   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All blocks into  L2 */
+   CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
+   CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
+};
+
+#ifndef CVMX_ENABLE_LEN_M8_FIX
+#define CVMX_ENABLE_LEN_M8_FIX 0
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
+typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
+
+typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
+typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
+
+/**
+ * Configure IPD
+ *
+ * @mbuff_size: Packets buffer size in 8 byte words
+ * @first_mbuff_skip:
+ *                   Number of 8 byte words to skip in the first buffer
+ * @not_first_mbuff_skip:
+ *                   Number of 8 byte words to skip in each following buffer
+ * @first_back: Must be same as first_mbuff_skip / 128
+ * @second_back:
+ *                   Must be same as not_first_mbuff_skip / 128
+ * @wqe_fpa_pool:
+ *                   FPA pool to get work entries from
+ * @cache_mode:
+ * @back_pres_enable_flag:
+ *                   Enable or disable port back pressure
+ */
+static inline void cvmx_ipd_config(uint64_t mbuff_size,
+                                   uint64_t first_mbuff_skip,
+                                   uint64_t not_first_mbuff_skip,
+                                   uint64_t first_back,
+                                   uint64_t second_back,
+                                   uint64_t wqe_fpa_pool,
+                                   enum cvmx_ipd_mode cache_mode,
+                                   uint64_t back_pres_enable_flag)
+{
+        cvmx_ipd_mbuff_first_skip_t first_skip;
+        cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
+        union cvmx_ipd_packet_mbuff_size size;
+        cvmx_ipd_first_next_ptr_back_t first_back_struct;
+        cvmx_ipd_second_next_ptr_back_t second_back_struct;
+        union cvmx_ipd_wqe_fpa_queue wqe_pool;
+        union cvmx_ipd_ctl_status ipd_ctl_reg;
+
+        first_skip.u64 = 0;
+        first_skip.s.skip_sz = first_mbuff_skip;
+        cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
+
+        not_first_skip.u64 = 0;
+        not_first_skip.s.skip_sz = not_first_mbuff_skip;
+        cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
+
+        size.u64 = 0;
+        size.s.mb_size = mbuff_size;
+        cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
+
+        first_back_struct.u64 = 0;
+        first_back_struct.s.back = first_back;
+        cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
+
+        second_back_struct.u64 = 0;
+        second_back_struct.s.back = second_back;
+        cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
+
+        wqe_pool.u64 = 0;
+        wqe_pool.s.wqe_pool = wqe_fpa_pool;
+        cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
+
+        ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        ipd_ctl_reg.s.opc_mode = cache_mode;
+        ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
+
+        /* Note: the example RED code that used to be here has been moved to
+           cvmx_helper_setup_red */
+}
+
+/**
+ * Enable IPD
+ */
+static inline void cvmx_ipd_enable(void)
+{
+        union cvmx_ipd_ctl_status ipd_reg;
+        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        if (ipd_reg.s.ipd_en) {
+                cvmx_dprintf
+                    ("Warning: Enabling IPD when IPD already enabled.\n");
+        }
+        ipd_reg.s.ipd_en = 1;
+#if  CVMX_ENABLE_LEN_M8_FIX
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+                ipd_reg.s.len_m8 = TRUE;
+#endif
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+/**
+ * Disable IPD
+ */
+static inline void cvmx_ipd_disable(void)
+{
+        union cvmx_ipd_ctl_status ipd_reg;
+        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        ipd_reg.s.ipd_en = 0;
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+/**
+ * Supportive function for cvmx_fpa_shutdown_pool.
+ */
+static inline void cvmx_ipd_free_ptr(void)
+{
+        /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
+            && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+                int no_wptr = 0;
+                union cvmx_ipd_ptr_count ipd_ptr_count;
+                ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+
+                /* Handle Work Queue Entry in cn56xx and cn52xx */
+                if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
+                        union cvmx_ipd_ctl_status ipd_ctl_status;
+                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+                        if (ipd_ctl_status.s.no_wptr)
+                                no_wptr = 1;
+                }
+
+                /* Free the prefetched WQE */
+                if (ipd_ptr_count.s.wqev_cnt) {
+                        union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
+                        ipd_wqe_ptr_valid.u64 =
+                            cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
+                        if (no_wptr)
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_wqe_ptr_valid.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        else
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_wqe_ptr_valid.s.
+                                               ptr << 7), CVMX_FPA_WQE_POOL, 0);
+                }
+
+                /* Free all WQE in the fifo */
+                if (ipd_ptr_count.s.wqe_pcnt) {
+                        int i;
+                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
+                        ipd_pwp_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                        for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
+                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+                                ipd_pwp_ptr_fifo_ctl.s.raddr =
+                                    ipd_pwp_ptr_fifo_ctl.s.max_cnts +
+                                    (ipd_pwp_ptr_fifo_ctl.s.wraddr +
+                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                               ipd_pwp_ptr_fifo_ctl.u64);
+                                ipd_pwp_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                                if (no_wptr)
+                                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                                      ((uint64_t)
+                                                       ipd_pwp_ptr_fifo_ctl.s.
+                                                       ptr << 7),
+                                                      CVMX_FPA_PACKET_POOL, 0);
+                                else
+                                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                                      ((uint64_t)
+                                                       ipd_pwp_ptr_fifo_ctl.s.
+                                                       ptr << 7),
+                                                      CVMX_FPA_WQE_POOL, 0);
+                        }
+                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                       ipd_pwp_ptr_fifo_ctl.u64);
+                }
+
+                /* Free the prefetched packet */
+                if (ipd_ptr_count.s.pktv_cnt) {
+                        union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
+                        ipd_pkt_ptr_valid.u64 =
+                            cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
+                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                      (ipd_pkt_ptr_valid.s.ptr << 7),
+                                      CVMX_FPA_PACKET_POOL, 0);
+                }
+
+                /* Free the per port prefetched packets */
+                if (1) {
+                        int i;
+                        union cvmx_ipd_prc_port_ptr_fifo_ctl
+                            ipd_prc_port_ptr_fifo_ctl;
+                        ipd_prc_port_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+                             i++) {
+                                ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
+                                ipd_prc_port_ptr_fifo_ctl.s.raddr =
+                                    i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+                                cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
+                                               ipd_prc_port_ptr_fifo_ctl.u64);
+                                ipd_prc_port_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr
+                                    (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t)
+                                               ipd_prc_port_ptr_fifo_ctl.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        }
+                        ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
+                                       ipd_prc_port_ptr_fifo_ctl.u64);
+                }
+
+                /* Free all packets in the holding fifo */
+                if (ipd_ptr_count.s.pfif_cnt) {
+                        int i;
+                        union cvmx_ipd_prc_hold_ptr_fifo_ctl
+                            ipd_prc_hold_ptr_fifo_ctl;
+
+                        ipd_prc_hold_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
+                                ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
+                                ipd_prc_hold_ptr_fifo_ctl.s.raddr =
+                                    (ipd_prc_hold_ptr_fifo_ctl.s.praddr +
+                                     i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
+                                cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
+                                               ipd_prc_hold_ptr_fifo_ctl.u64);
+                                ipd_prc_hold_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr
+                                    (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t)
+                                               ipd_prc_hold_ptr_fifo_ctl.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        }
+                        ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
+                                       ipd_prc_hold_ptr_fifo_ctl.u64);
+                }
+
+                /* Free all packets in the fifo */
+                if (ipd_ptr_count.s.pkt_pcnt) {
+                        int i;
+                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
+                        ipd_pwp_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
+                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+                                ipd_pwp_ptr_fifo_ctl.s.raddr =
+                                    (ipd_pwp_ptr_fifo_ctl.s.praddr +
+                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                               ipd_pwp_ptr_fifo_ctl.u64);
+                                ipd_pwp_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_pwp_ptr_fifo_ctl.
+                                               s.ptr << 7),
+                                              CVMX_FPA_PACKET_POOL, 0);
+                        }
+                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                       ipd_pwp_ptr_fifo_ctl.u64);
+                }
+
+                /* Reset the IPD to get all buffers out of it */
+                {
+                        union cvmx_ipd_ctl_status ipd_ctl_status;
+                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+                        ipd_ctl_status.s.reset = 1;
+                        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+                }
+
+                /* Reset the PIP */
+                {
+                        union cvmx_pip_sft_rst pip_sft_rst;
+                        pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
+                        pip_sft_rst.s.rst = 1;
+                        cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
+                }
+        }
+}
+
+#endif /*  __CVMX_IPD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
new file mode 100644
index 000000000..3ea84acf1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -0,0 +1,239 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_L2C_DEFS_H__
+#define __CVMX_L2C_DEFS_H__
+
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#define CVMX_L2C_ERR_TDTX(block_id)                                            \
+        (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_ERR_TTGX(block_id)                                            \
+        (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) +        \
+                ((offset) & 3) * 8)
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#define CVMX_L2C_TADX_PFCX(offset, block_id)                                   \
+                (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + (((offset) & 3) +    \
+                ((block_id) & 7) * 0x8000ull) * 8)
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \
+                ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \
+                ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + \
+                ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + \
+                ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_TADX_PRF(offset) (CVMX_ADD_IO_SEG(0x0001180080A00008ull)    + \
+                ((offset) & 7) * 0x40000ull)
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull)  + \
+                ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull)   + \
+                ((offset) & 1) * 8)
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull)    + \
+                ((offset) & 31) * 8)
+
+
+union cvmx_l2c_err_tdtx {
+        uint64_t u64;
+        struct cvmx_l2c_err_tdtx_s {
+                __BITFIELD_FIELD(uint64_t dbe:1,
+                __BITFIELD_FIELD(uint64_t sbe:1,
+                __BITFIELD_FIELD(uint64_t vdbe:1,
+                __BITFIELD_FIELD(uint64_t vsbe:1,
+                __BITFIELD_FIELD(uint64_t syn:10,
+                __BITFIELD_FIELD(uint64_t reserved_22_49:28,
+                __BITFIELD_FIELD(uint64_t wayidx:18,
+                __BITFIELD_FIELD(uint64_t reserved_2_3:2,
+                __BITFIELD_FIELD(uint64_t type:2,
+                ;)))))))))
+        } s;
+};
+
+union cvmx_l2c_err_ttgx {
+        uint64_t u64;
+        struct cvmx_l2c_err_ttgx_s {
+                __BITFIELD_FIELD(uint64_t dbe:1,
+                __BITFIELD_FIELD(uint64_t sbe:1,
+                __BITFIELD_FIELD(uint64_t noway:1,
+                __BITFIELD_FIELD(uint64_t reserved_56_60:5,
+                __BITFIELD_FIELD(uint64_t syn:6,
+                __BITFIELD_FIELD(uint64_t reserved_22_49:28,
+                __BITFIELD_FIELD(uint64_t wayidx:15,
+                __BITFIELD_FIELD(uint64_t reserved_2_6:5,
+                __BITFIELD_FIELD(uint64_t type:2,
+                ;)))))))))
+        } s;
+};
+
+union cvmx_l2c_cfg {
+        uint64_t u64;
+        struct cvmx_l2c_cfg_s {
+                __BITFIELD_FIELD(uint64_t reserved_20_63:44,
+                __BITFIELD_FIELD(uint64_t bstrun:1,
+                __BITFIELD_FIELD(uint64_t lbist:1,
+                __BITFIELD_FIELD(uint64_t xor_bank:1,
+                __BITFIELD_FIELD(uint64_t dpres1:1,
+                __BITFIELD_FIELD(uint64_t dpres0:1,
+                __BITFIELD_FIELD(uint64_t dfill_dis:1,
+                __BITFIELD_FIELD(uint64_t fpexp:4,
+                __BITFIELD_FIELD(uint64_t fpempty:1,
+                __BITFIELD_FIELD(uint64_t fpen:1,
+                __BITFIELD_FIELD(uint64_t idxalias:1,
+                __BITFIELD_FIELD(uint64_t mwf_crd:4,
+                __BITFIELD_FIELD(uint64_t rsp_arb_mode:1,
+                __BITFIELD_FIELD(uint64_t rfb_arb_mode:1,
+                __BITFIELD_FIELD(uint64_t lrf_arb_mode:1,
+                ;)))))))))))))))
+        } s;
+};
+
+union cvmx_l2c_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_ctl_s {
+                __BITFIELD_FIELD(uint64_t reserved_30_63:34,
+                __BITFIELD_FIELD(uint64_t sepcmt:1,
+                __BITFIELD_FIELD(uint64_t rdf_fast:1,
+                __BITFIELD_FIELD(uint64_t disstgl2i:1,
+                __BITFIELD_FIELD(uint64_t l2dfsbe:1,
+                __BITFIELD_FIELD(uint64_t l2dfdbe:1,
+                __BITFIELD_FIELD(uint64_t discclk:1,
+                __BITFIELD_FIELD(uint64_t maxvab:4,
+                __BITFIELD_FIELD(uint64_t maxlfb:4,
+                __BITFIELD_FIELD(uint64_t rsp_arb_mode:1,
+                __BITFIELD_FIELD(uint64_t xmc_arb_mode:1,
+                __BITFIELD_FIELD(uint64_t ef_ena:1,
+                __BITFIELD_FIELD(uint64_t ef_cnt:7,
+                __BITFIELD_FIELD(uint64_t vab_thresh:4,
+                __BITFIELD_FIELD(uint64_t disecc:1,
+                __BITFIELD_FIELD(uint64_t disidxalias:1,
+                ;))))))))))))))))
+        } s;
+};
+
+union cvmx_l2c_dbg {
+        uint64_t u64;
+        struct cvmx_l2c_dbg_s {
+                __BITFIELD_FIELD(uint64_t reserved_15_63:49,
+                __BITFIELD_FIELD(uint64_t lfb_enum:4,
+                __BITFIELD_FIELD(uint64_t lfb_dmp:1,
+                __BITFIELD_FIELD(uint64_t ppnum:4,
+                __BITFIELD_FIELD(uint64_t set:3,
+                __BITFIELD_FIELD(uint64_t finv:1,
+                __BITFIELD_FIELD(uint64_t l2d:1,
+                __BITFIELD_FIELD(uint64_t l2t:1,
+                ;))))))))
+        } s;
+};
+
+union cvmx_l2c_pfctl {
+        uint64_t u64;
+        struct cvmx_l2c_pfctl_s {
+                __BITFIELD_FIELD(uint64_t reserved_36_63:28,
+                __BITFIELD_FIELD(uint64_t cnt3rdclr:1,
+                __BITFIELD_FIELD(uint64_t cnt2rdclr:1,
+                __BITFIELD_FIELD(uint64_t cnt1rdclr:1,
+                __BITFIELD_FIELD(uint64_t cnt0rdclr:1,
+                __BITFIELD_FIELD(uint64_t cnt3ena:1,
+                __BITFIELD_FIELD(uint64_t cnt3clr:1,
+                __BITFIELD_FIELD(uint64_t cnt3sel:6,
+                __BITFIELD_FIELD(uint64_t cnt2ena:1,
+                __BITFIELD_FIELD(uint64_t cnt2clr:1,
+                __BITFIELD_FIELD(uint64_t cnt2sel:6,
+                __BITFIELD_FIELD(uint64_t cnt1ena:1,
+                __BITFIELD_FIELD(uint64_t cnt1clr:1,
+                __BITFIELD_FIELD(uint64_t cnt1sel:6,
+                __BITFIELD_FIELD(uint64_t cnt0ena:1,
+                __BITFIELD_FIELD(uint64_t cnt0clr:1,
+                __BITFIELD_FIELD(uint64_t cnt0sel:6,
+                ;)))))))))))))))))
+        } s;
+};
+
+union cvmx_l2c_tadx_prf {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_prf_s {
+                __BITFIELD_FIELD(uint64_t reserved_32_63:32,
+                __BITFIELD_FIELD(uint64_t cnt3sel:8,
+                __BITFIELD_FIELD(uint64_t cnt2sel:8,
+                __BITFIELD_FIELD(uint64_t cnt1sel:8,
+                __BITFIELD_FIELD(uint64_t cnt0sel:8,
+                ;)))))
+        } s;
+};
+
+union cvmx_l2c_tadx_tag {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_tag_s {
+                __BITFIELD_FIELD(uint64_t reserved_46_63:18,
+                __BITFIELD_FIELD(uint64_t ecc:6,
+                __BITFIELD_FIELD(uint64_t reserved_36_39:4,
+                __BITFIELD_FIELD(uint64_t tag:19,
+                __BITFIELD_FIELD(uint64_t reserved_4_16:13,
+                __BITFIELD_FIELD(uint64_t use:1,
+                __BITFIELD_FIELD(uint64_t valid:1,
+                __BITFIELD_FIELD(uint64_t dirty:1,
+                __BITFIELD_FIELD(uint64_t lock:1,
+                ;)))))))))
+        } s;
+};
+
+union cvmx_l2c_lckbase {
+        uint64_t u64;
+        struct cvmx_l2c_lckbase_s {
+                __BITFIELD_FIELD(uint64_t reserved_31_63:33,
+                __BITFIELD_FIELD(uint64_t lck_base:27,
+                __BITFIELD_FIELD(uint64_t reserved_1_3:3,
+                __BITFIELD_FIELD(uint64_t lck_ena:1,
+                ;))))
+        } s;
+};
+
+union cvmx_l2c_lckoff {
+        uint64_t u64;
+        struct cvmx_l2c_lckoff_s {
+                __BITFIELD_FIELD(uint64_t reserved_10_63:54,
+                __BITFIELD_FIELD(uint64_t lck_offset:10,
+                ;))
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
new file mode 100644
index 000000000..4459a3200
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -0,0 +1,364 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
+ * facilities.
+ */
+
+#ifndef __CVMX_L2C_H__
+#define __CVMX_L2C_H__
+
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_L2_ASSOC    cvmx_l2c_get_num_assoc()       /* Deprecated macro */
+#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()        /* Deprecated macro */
+#define CVMX_L2_SETS     cvmx_l2c_get_num_sets()        /* Deprecated macro */
+
+/* Based on 128 byte cache line size */
+#define CVMX_L2C_IDX_ADDR_SHIFT 7
+#define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
+
+/* Defines for index aliasing computations */
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT +               \
+                cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
+
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS  1
+
+union cvmx_l2c_tag {
+        uint64_t u64;
+        struct {
+                __BITFIELD_FIELD(uint64_t reserved:28,
+                __BITFIELD_FIELD(uint64_t V:1,
+                __BITFIELD_FIELD(uint64_t D:1,
+                __BITFIELD_FIELD(uint64_t L:1,
+                __BITFIELD_FIELD(uint64_t U:1,
+                __BITFIELD_FIELD(uint64_t addr:32,
+                ;))))))
+        } s;
+};
+
+/* L2C Performance Counter events. */
+enum cvmx_l2c_event {
+        CVMX_L2C_EVENT_CYCLES           =  0,
+        CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
+        CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
+        CVMX_L2C_EVENT_DATA_MISS        =  3,
+        CVMX_L2C_EVENT_DATA_HIT         =  4,
+        CVMX_L2C_EVENT_MISS             =  5,
+        CVMX_L2C_EVENT_HIT              =  6,
+        CVMX_L2C_EVENT_VICTIM_HIT       =  7,
+        CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
+        CVMX_L2C_EVENT_TAG_PROBE        =  9,
+        CVMX_L2C_EVENT_TAG_UPDATE       = 10,
+        CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
+        CVMX_L2C_EVENT_TAG_DIRTY        = 12,
+        CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
+        CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
+        CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
+        CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
+        CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
+        CVMX_L2C_EVENT_READ_REQUEST     = 18,
+        CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
+        CVMX_L2C_EVENT_XMC_NOP          = 20,
+        CVMX_L2C_EVENT_XMC_LDT          = 21,
+        CVMX_L2C_EVENT_XMC_LDI          = 22,
+        CVMX_L2C_EVENT_XMC_LDD          = 23,
+        CVMX_L2C_EVENT_XMC_STF          = 24,
+        CVMX_L2C_EVENT_XMC_STT          = 25,
+        CVMX_L2C_EVENT_XMC_STP          = 26,
+        CVMX_L2C_EVENT_XMC_STC          = 27,
+        CVMX_L2C_EVENT_XMC_DWB          = 28,
+        CVMX_L2C_EVENT_XMC_PL2          = 29,
+        CVMX_L2C_EVENT_XMC_PSL1         = 30,
+        CVMX_L2C_EVENT_XMC_IOBLD        = 31,
+        CVMX_L2C_EVENT_XMC_IOBST        = 32,
+        CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
+        CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
+        CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
+        CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
+        CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
+        CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
+        CVMX_L2C_EVENT_RSC_NOP          = 39,
+        CVMX_L2C_EVENT_RSC_STDN         = 40,
+        CVMX_L2C_EVENT_RSC_FILL         = 41,
+        CVMX_L2C_EVENT_RSC_REFL         = 42,
+        CVMX_L2C_EVENT_RSC_STIN         = 43,
+        CVMX_L2C_EVENT_RSC_SCIN         = 44,
+        CVMX_L2C_EVENT_RSC_SCFL         = 45,
+        CVMX_L2C_EVENT_RSC_SCDN         = 46,
+        CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
+        CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
+        CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
+        CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
+        CVMX_L2C_EVENT_LRF_REQ          = 51,
+        CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
+        CVMX_L2C_EVENT_DT_WR_INVAL      = 53,
+        CVMX_L2C_EVENT_MAX
+};
+
+/* L2C Performance Counter events for Octeon2. */
+enum cvmx_l2c_tad_event {
+        CVMX_L2C_TAD_EVENT_NONE          = 0,
+        CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,
+        CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,
+        CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
+        CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
+        CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,
+        CVMX_L2C_TAD_EVENT_SC_PASS       = 6,
+        CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
+        CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
+        CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
+        CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
+        CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
+        CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
+        CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
+        CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
+        CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
+        CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
+        CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
+        CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
+        CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
+        CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
+        CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
+        CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
+        CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,
+        CVMX_L2C_TAD_EVENT_MAX
+};
+
+/**
+ * Configure one of the four L2 Cache performance counters to capture event
+ * occurrences.
+ *
+ * @counter:        The counter to configure. Range 0..3.
+ * @event:          The type of L2 Cache event occurrence to count.
+ * @clear_on_read:  When asserted, any read of the performance counter
+ *                       clears the counter.
+ *
+ * @note The routine does not clear the counter.
+ */
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
+                          uint32_t clear_on_read);
+
+/**
+ * Read the given L2 Cache performance counter. The counter must be configured
+ * before reading, but this routine does not enforce this requirement.
+ *
+ * @counter:  The counter to configure. Range 0..3.
+ *
+ * Returns The current counter value.
+ */
+uint64_t cvmx_l2c_read_perf(uint32_t counter);
+
+/**
+ * Return the L2 Cache way partitioning for a given core.
+ *
+ * @core:  The core processor of interest.
+ *
+ * Returns    The mask specifying the partitioning. 0 bits in mask indicates
+ *              the cache 'ways' that a core can evict from.
+ *            -1 on error
+ */
+int cvmx_l2c_get_core_way_partition(uint32_t core);
+
+/**
+ * Partitions the L2 cache for a core
+ *
+ * @core: The core that the partitioning applies to.
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
+ *
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
+
+/**
+ * Return the L2 Cache way partitioning for the hw blocks.
+ *
+ * Returns    The mask specifying the reserved way. 0 bits in mask indicates
+ *              the cache 'ways' that a core can evict from.
+ *            -1 on error
+ */
+int cvmx_l2c_get_hw_way_partition(void);
+
+/**
+ * Partitions the L2 cache for the hardware blocks.
+ *
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
+ *
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_hw_way_partition(uint32_t mask);
+
+
+/**
+ * Locks a line in the L2 cache at the specified physical address
+ *
+ * @addr:   physical address of line to lock
+ *
+ * Returns 0 on success,
+ *         1 if line not locked.
+ */
+int cvmx_l2c_lock_line(uint64_t addr);
+
+/**
+ * Locks a specified memory region in the L2 cache.
+ *
+ * Note that if not all lines can be locked, that means that all
+ * but one of the ways (associations) available to the locking
+ * core are locked.  Having only 1 association available for
+ * normal caching may have a significant adverse affect on performance.
+ * Care should be taken to ensure that enough of the L2 cache is left
+ * unlocked to allow for normal caching of DRAM.
+ *
+ * @start:  Physical address of the start of the region to lock
+ * @len:    Length (in bytes) of region to lock
+ *
+ * Returns Number of requested lines that where not locked.
+ *         0 on success (all locked)
+ */
+int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
+
+/**
+ * Unlock and flush a cache line from the L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ * Note that this function will flush a matching but unlocked cache line.
+ * (If address is not in L2, no lines are flushed.)
+ *
+ * @address: Physical address to unlock
+ *
+ * Returns 0: line not unlocked
+ *         1: line unlocked
+ */
+int cvmx_l2c_unlock_line(uint64_t address);
+
+/**
+ * Unlocks a region of memory that is locked in the L2 cache
+ *
+ * @start:  start physical address
+ * @len:    length (in bytes) to unlock
+ *
+ * Returns Number of locked lines that the call unlocked
+ */
+int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
+
+/**
+ * Read the L2 controller tag for a given location in L2
+ *
+ * @association:
+ *               Which association to read line from
+ * @index:  Which way to read from.
+ *
+ * Returns l2c tag structure for line requested.
+ */
+union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
+
+/* Wrapper providing a deprecated old function name */
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
+                                                  uint32_t index)
+                                                  __attribute__((deprecated));
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
+                                                  uint32_t index)
+{
+        return cvmx_l2c_get_tag(association, index);
+}
+
+
+/**
+ * Returns the cache index for a given physical address
+ *
+ * @addr:   physical address
+ *
+ * Returns L2 cache index
+ */
+uint32_t cvmx_l2c_address_to_index(uint64_t addr);
+
+/**
+ * Flushes (and unlocks) the entire L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ */
+void cvmx_l2c_flush(void);
+
+/**
+ *
+ * Returns the size of the L2 cache in bytes,
+ * -1 on error (unrecognized model)
+ */
+int cvmx_l2c_get_cache_size_bytes(void);
+
+/**
+ * Return the number of sets in the L2 Cache
+ *
+ * Returns
+ */
+int cvmx_l2c_get_num_sets(void);
+
+/**
+ * Return log base 2 of the number of sets in the L2 cache
+ * Returns
+ */
+int cvmx_l2c_get_set_bits(void);
+/**
+ * Return the number of associations in the L2 Cache
+ *
+ * Returns
+ */
+int cvmx_l2c_get_num_assoc(void);
+
+/**
+ * Flush a line from the L2 cache
+ * This should only be called from one core at a time, as this routine
+ * sets the core to the 'debug' core in order to flush the line.
+ *
+ * @assoc:  Association (or way) to flush
+ * @index:  Index to flush
+ */
+void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
+
+#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
new file mode 100644
index 000000000..a951ad5d6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -0,0 +1,60 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_L2D_DEFS_H__
+#define __CVMX_L2D_DEFS_H__
+
+#define CVMX_L2D_ERR    (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#define CVMX_L2D_FUS3   (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
+
+
+union cvmx_l2d_err {
+        uint64_t u64;
+        struct cvmx_l2d_err_s {
+                __BITFIELD_FIELD(uint64_t reserved_6_63:58,
+                __BITFIELD_FIELD(uint64_t bmhclsel:1,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;)))))))
+        } s;
+};
+
+union cvmx_l2d_fus3 {
+        uint64_t u64;
+        struct cvmx_l2d_fus3_s {
+                __BITFIELD_FIELD(uint64_t reserved_40_63:24,
+                __BITFIELD_FIELD(uint64_t ema_ctl:3,
+                __BITFIELD_FIELD(uint64_t reserved_34_36:3,
+                __BITFIELD_FIELD(uint64_t q3fus:34,
+                ;))))
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
new file mode 100644
index 000000000..06ea13251
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -0,0 +1,143 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_L2T_DEFS_H__
+#define __CVMX_L2T_DEFS_H__
+
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_L2T_ERR    (CVMX_ADD_IO_SEG(0x0001180080000008ull))
+
+
+union cvmx_l2t_err {
+        uint64_t u64;
+        struct cvmx_l2t_err_s {
+                __BITFIELD_FIELD(uint64_t reserved_29_63:35,
+                __BITFIELD_FIELD(uint64_t fadru:1,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t fset:3,
+                __BITFIELD_FIELD(uint64_t fadr:10,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;))))))))))))))
+        } s;
+        struct cvmx_l2t_err_cn30xx {
+                __BITFIELD_FIELD(uint64_t reserved_28_63:36,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t reserved_23_23:1,
+                __BITFIELD_FIELD(uint64_t fset:2,
+                __BITFIELD_FIELD(uint64_t reserved_19_20:2,
+                __BITFIELD_FIELD(uint64_t fadr:8,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;)))))))))))))))
+        } cn30xx;
+        struct cvmx_l2t_err_cn31xx {
+                __BITFIELD_FIELD(uint64_t reserved_28_63:36,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t reserved_23_23:1,
+                __BITFIELD_FIELD(uint64_t fset:2,
+                __BITFIELD_FIELD(uint64_t reserved_20_20:1,
+                __BITFIELD_FIELD(uint64_t fadr:9,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;)))))))))))))))
+        } cn31xx;
+        struct cvmx_l2t_err_cn38xx {
+                __BITFIELD_FIELD(uint64_t reserved_28_63:36,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t fset:3,
+                __BITFIELD_FIELD(uint64_t fadr:10,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;)))))))))))))
+        } cn38xx;
+        struct cvmx_l2t_err_cn50xx {
+                __BITFIELD_FIELD(uint64_t reserved_28_63:36,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t fset:3,
+                __BITFIELD_FIELD(uint64_t reserved_18_20:3,
+                __BITFIELD_FIELD(uint64_t fadr:7,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;))))))))))))))
+        } cn50xx;
+        struct cvmx_l2t_err_cn52xx {
+                __BITFIELD_FIELD(uint64_t reserved_28_63:36,
+                __BITFIELD_FIELD(uint64_t lck_intena2:1,
+                __BITFIELD_FIELD(uint64_t lckerr2:1,
+                __BITFIELD_FIELD(uint64_t lck_intena:1,
+                __BITFIELD_FIELD(uint64_t lckerr:1,
+                __BITFIELD_FIELD(uint64_t fset:3,
+                __BITFIELD_FIELD(uint64_t reserved_20_20:1,
+                __BITFIELD_FIELD(uint64_t fadr:9,
+                __BITFIELD_FIELD(uint64_t fsyn:6,
+                __BITFIELD_FIELD(uint64_t ded_err:1,
+                __BITFIELD_FIELD(uint64_t sec_err:1,
+                __BITFIELD_FIELD(uint64_t ded_intena:1,
+                __BITFIELD_FIELD(uint64_t sec_intena:1,
+                __BITFIELD_FIELD(uint64_t ecc_ena:1,
+                ;))))))))))))))
+        } cn52xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
new file mode 100644
index 000000000..023790752
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -0,0 +1,214 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_LED_DEFS_H__
+#define __CVMX_LED_DEFS_H__
+
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
+
+union cvmx_led_blink {
+        uint64_t u64;
+        struct cvmx_led_blink_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rate:8;
+#else
+                uint64_t rate:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_led_clk_phase {
+        uint64_t u64;
+        struct cvmx_led_clk_phase_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t phase:7;
+#else
+                uint64_t phase:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_led_cylon {
+        uint64_t u64;
+        struct cvmx_led_cylon_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t rate:16;
+#else
+                uint64_t rate:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_led_dbg {
+        uint64_t u64;
+        struct cvmx_led_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t dbg_en:1;
+#else
+                uint64_t dbg_en:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_led_en {
+        uint64_t u64;
+        struct cvmx_led_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_led_polarity {
+        uint64_t u64;
+        struct cvmx_led_polarity_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t polarity:1;
+#else
+                uint64_t polarity:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_led_prt {
+        uint64_t u64;
+        struct cvmx_led_prt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t prt_en:8;
+#else
+                uint64_t prt_en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_led_prt_fmt {
+        uint64_t u64;
+        struct cvmx_led_prt_fmt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t format:4;
+#else
+                uint64_t format:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_led_prt_statusx {
+        uint64_t u64;
+        struct cvmx_led_prt_statusx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t status:6;
+#else
+                uint64_t status:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_led_udd_cntx {
+        uint64_t u64;
+        struct cvmx_led_udd_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t cnt:6;
+#else
+                uint64_t cnt:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_led_udd_datx {
+        uint64_t u64;
+        struct cvmx_led_udd_datx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dat:32;
+#else
+                uint64_t dat:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_led_udd_dat_clrx {
+        uint64_t u64;
+        struct cvmx_led_udd_dat_clrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t clr:32;
+#else
+                uint64_t clr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_led_udd_dat_setx {
+        uint64_t u64;
+        struct cvmx_led_udd_dat_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t set:32;
+#else
+                uint64_t set:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
new file mode 100644
index 000000000..4167a4c7a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
@@ -0,0 +1,2943 @@
+/***********************license start***************
+ * Author: Cavium Inc.
+ *
+ * Contact: support@cavium.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Inc. for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_LMCX_DEFS_H__
+#define __CVMX_LMCX_DEFS_H__
+
+#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
+static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
+}
+
+#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
+static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
+}
+
+#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
+#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
+#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
+#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
+#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
+#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
+#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_lmcx_bist_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_bist_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t start:1;
+#else
+                uint64_t start:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_bist_result {
+        uint64_t u64;
+        struct cvmx_lmcx_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t csrd2e:1;
+                uint64_t csre2d:1;
+                uint64_t mwf:1;
+                uint64_t mwd:3;
+                uint64_t mwc:1;
+                uint64_t mrf:1;
+                uint64_t mrd:3;
+#else
+                uint64_t mrd:3;
+                uint64_t mrf:1;
+                uint64_t mwc:1;
+                uint64_t mwd:3;
+                uint64_t mwf:1;
+                uint64_t csre2d:1;
+                uint64_t csrd2e:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+        struct cvmx_lmcx_bist_result_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t mwf:1;
+                uint64_t mwd:3;
+                uint64_t mwc:1;
+                uint64_t mrf:1;
+                uint64_t mrd:3;
+#else
+                uint64_t mrd:3;
+                uint64_t mrf:1;
+                uint64_t mwc:1;
+                uint64_t mwd:3;
+                uint64_t mwf:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn50xx;
+};
+
+union cvmx_lmcx_char_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_char_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t dr:1;
+                uint64_t skew_on:1;
+                uint64_t en:1;
+                uint64_t sel:1;
+                uint64_t prog:8;
+                uint64_t prbs:32;
+#else
+                uint64_t prbs:32;
+                uint64_t prog:8;
+                uint64_t sel:1;
+                uint64_t en:1;
+                uint64_t skew_on:1;
+                uint64_t dr:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+        struct cvmx_lmcx_char_ctl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t en:1;
+                uint64_t sel:1;
+                uint64_t prog:8;
+                uint64_t prbs:32;
+#else
+                uint64_t prbs:32;
+                uint64_t prog:8;
+                uint64_t sel:1;
+                uint64_t en:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn63xx;
+};
+
+union cvmx_lmcx_char_mask0 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mask:64;
+#else
+                uint64_t mask:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_char_mask1 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t mask:8;
+#else
+                uint64_t mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_char_mask2 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mask:64;
+#else
+                uint64_t mask:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_char_mask3 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t mask:8;
+#else
+                uint64_t mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_char_mask4 {
+        uint64_t u64;
+        struct cvmx_lmcx_char_mask4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t reset_n_mask:1;
+                uint64_t a_mask:16;
+                uint64_t ba_mask:3;
+                uint64_t we_n_mask:1;
+                uint64_t cas_n_mask:1;
+                uint64_t ras_n_mask:1;
+                uint64_t odt1_mask:2;
+                uint64_t odt0_mask:2;
+                uint64_t cs1_n_mask:2;
+                uint64_t cs0_n_mask:2;
+                uint64_t cke_mask:2;
+#else
+                uint64_t cke_mask:2;
+                uint64_t cs0_n_mask:2;
+                uint64_t cs1_n_mask:2;
+                uint64_t odt0_mask:2;
+                uint64_t odt1_mask:2;
+                uint64_t ras_n_mask:1;
+                uint64_t cas_n_mask:1;
+                uint64_t we_n_mask:1;
+                uint64_t ba_mask:3;
+                uint64_t a_mask:16;
+                uint64_t reset_n_mask:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_comp_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t pctl_clk:4;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_comp_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_cmd:4;
+                uint64_t pctl_dat:4;
+#else
+                uint64_t pctl_dat:4;
+                uint64_t pctl_cmd:4;
+                uint64_t pctl_clk:4;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t nctl_cmd:4;
+                uint64_t nctl_clk:4;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_comp_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t reserved_5_11:7;
+                uint64_t pctl_dat:5;
+#else
+                uint64_t pctl_dat:5;
+                uint64_t reserved_5_11:7;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_comp_ctl_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_dat:4;
+                uint64_t pctl_csr:4;
+                uint64_t reserved_4_11:8;
+                uint64_t pctl_dat:4;
+#else
+                uint64_t pctl_dat:4;
+                uint64_t reserved_4_11:8;
+                uint64_t pctl_csr:4;
+                uint64_t nctl_dat:4;
+                uint64_t reserved_20_27:8;
+                uint64_t nctl_csr:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn58xxp1;
+};
+
+union cvmx_lmcx_comp_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_comp_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ddr__ptune:4;
+                uint64_t ddr__ntune:4;
+                uint64_t m180:1;
+                uint64_t byp:1;
+                uint64_t ptune:4;
+                uint64_t ntune:4;
+                uint64_t rodt_ctl:4;
+                uint64_t cmd_ctl:4;
+                uint64_t ck_ctl:4;
+                uint64_t dqx_ctl:4;
+#else
+                uint64_t dqx_ctl:4;
+                uint64_t ck_ctl:4;
+                uint64_t cmd_ctl:4;
+                uint64_t rodt_ctl:4;
+                uint64_t ntune:4;
+                uint64_t ptune:4;
+                uint64_t byp:1;
+                uint64_t m180:1;
+                uint64_t ddr__ntune:4;
+                uint64_t ddr__ptune:4;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_config {
+        uint64_t u64;
+        struct cvmx_lmcx_config_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t mode32b:1;
+                uint64_t scrz:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t scrz:1;
+                uint64_t mode32b:1;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+        struct cvmx_lmcx_config_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_config_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t reserved_55_63:9;
+#endif
+        } cn63xxp1;
+        struct cvmx_lmcx_config_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t scrz:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t init_status:4;
+                uint64_t mirrmask:4;
+                uint64_t rankmask:4;
+                uint64_t rank_ena:1;
+                uint64_t sref_with_dll:1;
+                uint64_t early_dqx:1;
+                uint64_t sequence:3;
+                uint64_t ref_zqcs_int:19;
+                uint64_t reset:1;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reset:1;
+                uint64_t ref_zqcs_int:19;
+                uint64_t sequence:3;
+                uint64_t early_dqx:1;
+                uint64_t sref_with_dll:1;
+                uint64_t rank_ena:1;
+                uint64_t rankmask:4;
+                uint64_t mirrmask:4;
+                uint64_t init_status:4;
+                uint64_t early_unload_d0_r0:1;
+                uint64_t early_unload_d0_r1:1;
+                uint64_t early_unload_d1_r0:1;
+                uint64_t early_unload_d1_r1:1;
+                uint64_t scrz:1;
+                uint64_t reserved_60_63:4;
+#endif
+        } cn66xx;
+};
+
+union cvmx_lmcx_control {
+        uint64_t u64;
+        struct cvmx_lmcx_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t scramble_ena:1;
+                uint64_t thrcnt:12;
+                uint64_t persub:8;
+                uint64_t thrmax:4;
+                uint64_t crm_cnt:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_max:5;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t crm_max:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_cnt:5;
+                uint64_t thrmax:4;
+                uint64_t persub:8;
+                uint64_t thrcnt:12;
+                uint64_t scramble_ena:1;
+#endif
+        } s;
+        struct cvmx_lmcx_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn63xx;
+        struct cvmx_lmcx_control_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t scramble_ena:1;
+                uint64_t reserved_24_62:39;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t reserved_24_62:39;
+                uint64_t scramble_ena:1;
+#endif
+        } cn66xx;
+        struct cvmx_lmcx_control_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t thrcnt:12;
+                uint64_t persub:8;
+                uint64_t thrmax:4;
+                uint64_t crm_cnt:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_max:5;
+                uint64_t rodt_bprch:1;
+                uint64_t wodt_bprch:1;
+                uint64_t bprch:2;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t nxm_write_en:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t inorder_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t throttle_rd:1;
+                uint64_t fprch2:2;
+                uint64_t pocas:1;
+                uint64_t ddr2t:1;
+                uint64_t bwcnt:1;
+                uint64_t rdimm_ena:1;
+#else
+                uint64_t rdimm_ena:1;
+                uint64_t bwcnt:1;
+                uint64_t ddr2t:1;
+                uint64_t pocas:1;
+                uint64_t fprch2:2;
+                uint64_t throttle_rd:1;
+                uint64_t throttle_wr:1;
+                uint64_t inorder_rd:1;
+                uint64_t inorder_wr:1;
+                uint64_t elev_prio_dis:1;
+                uint64_t nxm_write_en:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t auto_dclkdis:1;
+                uint64_t int_zqcs_dis:1;
+                uint64_t ext_zqcs_dis:1;
+                uint64_t bprch:2;
+                uint64_t wodt_bprch:1;
+                uint64_t rodt_bprch:1;
+                uint64_t crm_max:5;
+                uint64_t crm_thr:5;
+                uint64_t crm_cnt:5;
+                uint64_t thrmax:4;
+                uint64_t persub:8;
+                uint64_t thrcnt:12;
+                uint64_t reserved_63_63:1;
+#endif
+        } cn68xx;
+};
+
+union cvmx_lmcx_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t pll_div2:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t reserved_10_11:2;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t reserved_10_11:2;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t pll_div2:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t pll_div2:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t pll_div2:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_ctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t set_zero:1;
+                uint64_t mode128b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode128b:1;
+                uint64_t set_zero:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_lmcx_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_17_17:1;
+                uint64_t pll_bypass:1;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t pll_bypass:1;
+                uint64_t reserved_17_17:1;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode32b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode32b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn52xx;
+        struct cvmx_lmcx_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:4;
+                uint64_t ddr__pctl:4;
+                uint64_t slow_scf:1;
+                uint64_t xor_bank:1;
+                uint64_t max_write_batch:4;
+                uint64_t reserved_16_17:2;
+                uint64_t rdimm_ena:1;
+                uint64_t r2r_slot:1;
+                uint64_t inorder_mwf:1;
+                uint64_t inorder_mrf:1;
+                uint64_t dreset:1;
+                uint64_t mode128b:1;
+                uint64_t fprch2:1;
+                uint64_t bprch:1;
+                uint64_t sil_lat:2;
+                uint64_t tskw:2;
+                uint64_t qs_dic:2;
+                uint64_t dic:2;
+#else
+                uint64_t dic:2;
+                uint64_t qs_dic:2;
+                uint64_t tskw:2;
+                uint64_t sil_lat:2;
+                uint64_t bprch:1;
+                uint64_t fprch2:1;
+                uint64_t mode128b:1;
+                uint64_t dreset:1;
+                uint64_t inorder_mrf:1;
+                uint64_t inorder_mwf:1;
+                uint64_t r2r_slot:1;
+                uint64_t rdimm_ena:1;
+                uint64_t reserved_16_17:2;
+                uint64_t max_write_batch:4;
+                uint64_t xor_bank:1;
+                uint64_t slow_scf:1;
+                uint64_t ddr__pctl:4;
+                uint64_t ddr__nctl:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn58xx;
+};
+
+union cvmx_lmcx_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t sequence:3;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_2_7:6;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_7:6;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t sequence:3;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+        struct cvmx_lmcx_ctl1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_ctl1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_2_7:6;
+                uint64_t data_layout:2;
+#else
+                uint64_t data_layout:2;
+                uint64_t reserved_2_7:6;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_ctl1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t ecc_adr:1;
+                uint64_t forcewrite:4;
+                uint64_t idlepower:3;
+                uint64_t sequence:3;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t sequence:3;
+                uint64_t idlepower:3;
+                uint64_t forcewrite:4;
+                uint64_t ecc_adr:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } cn52xx;
+        struct cvmx_lmcx_ctl1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sil_mode:1;
+                uint64_t dcc_enable:1;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t dcc_enable:1;
+                uint64_t sil_mode:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn58xx;
+};
+
+union cvmx_lmcx_dclk_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dclkcnt:64;
+#else
+                uint64_t dclkcnt:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dclk_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dclkcnt_hi:32;
+#else
+                uint64_t dclkcnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dclk_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dclkcnt_lo:32;
+#else
+                uint64_t dclkcnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dclk_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dclk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t off90_ena:1;
+                uint64_t dclk90_byp:1;
+                uint64_t dclk90_ld:1;
+                uint64_t dclk90_vlu:5;
+#else
+                uint64_t dclk90_vlu:5;
+                uint64_t dclk90_ld:1;
+                uint64_t dclk90_byp:1;
+                uint64_t off90_ena:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_ddr2_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ddr2_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bank8:1;
+                uint64_t burst8:1;
+                uint64_t addlat:3;
+                uint64_t pocas:1;
+                uint64_t bwcnt:1;
+                uint64_t twr:3;
+                uint64_t silo_hc:1;
+                uint64_t ddr_eof:4;
+                uint64_t tfaw:5;
+                uint64_t crip_mode:1;
+                uint64_t ddr2t:1;
+                uint64_t odt_ena:1;
+                uint64_t qdll_ena:1;
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_byp:1;
+                uint64_t rdqs:1;
+                uint64_t ddr2:1;
+#else
+                uint64_t ddr2:1;
+                uint64_t rdqs:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_vlu:5;
+                uint64_t qdll_ena:1;
+                uint64_t odt_ena:1;
+                uint64_t ddr2t:1;
+                uint64_t crip_mode:1;
+                uint64_t tfaw:5;
+                uint64_t ddr_eof:4;
+                uint64_t silo_hc:1;
+                uint64_t twr:3;
+                uint64_t bwcnt:1;
+                uint64_t pocas:1;
+                uint64_t addlat:3;
+                uint64_t burst8:1;
+                uint64_t bank8:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_ddr2_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bank8:1;
+                uint64_t burst8:1;
+                uint64_t addlat:3;
+                uint64_t pocas:1;
+                uint64_t bwcnt:1;
+                uint64_t twr:3;
+                uint64_t silo_hc:1;
+                uint64_t ddr_eof:4;
+                uint64_t tfaw:5;
+                uint64_t crip_mode:1;
+                uint64_t ddr2t:1;
+                uint64_t odt_ena:1;
+                uint64_t qdll_ena:1;
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_byp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t ddr2:1;
+#else
+                uint64_t ddr2:1;
+                uint64_t reserved_1_1:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_vlu:5;
+                uint64_t qdll_ena:1;
+                uint64_t odt_ena:1;
+                uint64_t ddr2t:1;
+                uint64_t crip_mode:1;
+                uint64_t tfaw:5;
+                uint64_t ddr_eof:4;
+                uint64_t silo_hc:1;
+                uint64_t twr:3;
+                uint64_t bwcnt:1;
+                uint64_t pocas:1;
+                uint64_t addlat:3;
+                uint64_t burst8:1;
+                uint64_t bank8:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+};
+
+union cvmx_lmcx_ddr_pll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_ddr_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t jtg_test_mode:1;
+                uint64_t dfm_div_reset:1;
+                uint64_t dfm_ps_en:3;
+                uint64_t ddr_div_reset:1;
+                uint64_t ddr_ps_en:3;
+                uint64_t diffamp:4;
+                uint64_t cps:3;
+                uint64_t cpb:3;
+                uint64_t reset_n:1;
+                uint64_t clkf:7;
+#else
+                uint64_t clkf:7;
+                uint64_t reset_n:1;
+                uint64_t cpb:3;
+                uint64_t cps:3;
+                uint64_t diffamp:4;
+                uint64_t ddr_ps_en:3;
+                uint64_t ddr_div_reset:1;
+                uint64_t dfm_ps_en:3;
+                uint64_t dfm_div_reset:1;
+                uint64_t jtg_test_mode:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_delay_cfg {
+        uint64_t u64;
+        struct cvmx_lmcx_delay_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t dq:5;
+                uint64_t cmd:5;
+                uint64_t clk:5;
+#else
+                uint64_t clk:5;
+                uint64_t cmd:5;
+                uint64_t dq:5;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+        struct cvmx_lmcx_delay_cfg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t dq:4;
+                uint64_t reserved_9_9:1;
+                uint64_t cmd:4;
+                uint64_t reserved_4_4:1;
+                uint64_t clk:4;
+#else
+                uint64_t clk:4;
+                uint64_t reserved_4_4:1;
+                uint64_t cmd:4;
+                uint64_t reserved_9_9:1;
+                uint64_t dq:4;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn38xx;
+};
+
+union cvmx_lmcx_dimmx_params {
+        uint64_t u64;
+        struct cvmx_lmcx_dimmx_params_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rc15:4;
+                uint64_t rc14:4;
+                uint64_t rc13:4;
+                uint64_t rc12:4;
+                uint64_t rc11:4;
+                uint64_t rc10:4;
+                uint64_t rc9:4;
+                uint64_t rc8:4;
+                uint64_t rc7:4;
+                uint64_t rc6:4;
+                uint64_t rc5:4;
+                uint64_t rc4:4;
+                uint64_t rc3:4;
+                uint64_t rc2:4;
+                uint64_t rc1:4;
+                uint64_t rc0:4;
+#else
+                uint64_t rc0:4;
+                uint64_t rc1:4;
+                uint64_t rc2:4;
+                uint64_t rc3:4;
+                uint64_t rc4:4;
+                uint64_t rc5:4;
+                uint64_t rc6:4;
+                uint64_t rc7:4;
+                uint64_t rc8:4;
+                uint64_t rc9:4;
+                uint64_t rc10:4;
+                uint64_t rc11:4;
+                uint64_t rc12:4;
+                uint64_t rc13:4;
+                uint64_t rc14:4;
+                uint64_t rc15:4;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dimm_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dimm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t parity:1;
+                uint64_t tcws:13;
+                uint64_t dimm1_wmask:16;
+                uint64_t dimm0_wmask:16;
+#else
+                uint64_t dimm0_wmask:16;
+                uint64_t dimm1_wmask:16;
+                uint64_t tcws:13;
+                uint64_t parity:1;
+                uint64_t reserved_46_63:18;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dreset:1;
+                uint64_t dll90_byp:1;
+                uint64_t dll90_ena:1;
+                uint64_t dll90_vlu:5;
+#else
+                uint64_t dll90_vlu:5;
+                uint64_t dll90_ena:1;
+                uint64_t dll90_byp:1;
+                uint64_t dreset:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_dll_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t intf_en:1;
+                uint64_t dll_bringup:1;
+                uint64_t dreset:1;
+                uint64_t quad_dll_ena:1;
+                uint64_t byp_sel:4;
+                uint64_t byp_setting:8;
+#else
+                uint64_t byp_setting:8;
+                uint64_t byp_sel:4;
+                uint64_t quad_dll_ena:1;
+                uint64_t dreset:1;
+                uint64_t dll_bringup:1;
+                uint64_t intf_en:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+        struct cvmx_lmcx_dll_ctl2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t dll_bringup:1;
+                uint64_t dreset:1;
+                uint64_t quad_dll_ena:1;
+                uint64_t byp_sel:4;
+                uint64_t byp_setting:8;
+#else
+                uint64_t byp_setting:8;
+                uint64_t byp_sel:4;
+                uint64_t quad_dll_ena:1;
+                uint64_t dreset:1;
+                uint64_t dll_bringup:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn63xx;
+};
+
+union cvmx_lmcx_dll_ctl3 {
+        uint64_t u64;
+        struct cvmx_lmcx_dll_ctl3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_41_63:23;
+                uint64_t dclk90_fwd:1;
+                uint64_t ddr_90_dly_byp:1;
+                uint64_t dclk90_recal_dis:1;
+                uint64_t dclk90_byp_sel:1;
+                uint64_t dclk90_byp_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t dll90_setting:8;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll_mode:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t offset_ena:1;
+                uint64_t load_offset:1;
+                uint64_t mode_sel:2;
+                uint64_t byte_sel:4;
+                uint64_t offset:6;
+#else
+                uint64_t offset:6;
+                uint64_t byte_sel:4;
+                uint64_t mode_sel:2;
+                uint64_t load_offset:1;
+                uint64_t offset_ena:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t dll_mode:1;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll90_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t dclk90_byp_setting:8;
+                uint64_t dclk90_byp_sel:1;
+                uint64_t dclk90_recal_dis:1;
+                uint64_t ddr_90_dly_byp:1;
+                uint64_t dclk90_fwd:1;
+                uint64_t reserved_41_63:23;
+#endif
+        } s;
+        struct cvmx_lmcx_dll_ctl3_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t dll_fast:1;
+                uint64_t dll90_setting:8;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll_mode:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t offset_ena:1;
+                uint64_t load_offset:1;
+                uint64_t mode_sel:2;
+                uint64_t byte_sel:4;
+                uint64_t offset:6;
+#else
+                uint64_t offset:6;
+                uint64_t byte_sel:4;
+                uint64_t mode_sel:2;
+                uint64_t load_offset:1;
+                uint64_t offset_ena:1;
+                uint64_t dll90_byte_sel:4;
+                uint64_t dll_mode:1;
+                uint64_t fine_tune_mode:1;
+                uint64_t dll90_setting:8;
+                uint64_t dll_fast:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn63xx;
+};
+
+union cvmx_lmcx_dual_memcfg {
+        uint64_t u64;
+        struct cvmx_lmcx_dual_memcfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t bank8:1;
+                uint64_t row_lsb:3;
+                uint64_t reserved_8_15:8;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_15:8;
+                uint64_t row_lsb:3;
+                uint64_t bank8:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_lmcx_dual_memcfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t row_lsb:3;
+                uint64_t reserved_8_15:8;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_15:8;
+                uint64_t row_lsb:3;
+                uint64_t reserved_19_63:45;
+#endif
+        } cn61xx;
+};
+
+union cvmx_lmcx_ecc_synd {
+        uint64_t u64;
+        struct cvmx_lmcx_ecc_synd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t mrdsyn3:8;
+                uint64_t mrdsyn2:8;
+                uint64_t mrdsyn1:8;
+                uint64_t mrdsyn0:8;
+#else
+                uint64_t mrdsyn0:8;
+                uint64_t mrdsyn1:8;
+                uint64_t mrdsyn2:8;
+                uint64_t mrdsyn3:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_fadr {
+        uint64_t u64;
+        struct cvmx_lmcx_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_lmcx_fadr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:14;
+                uint64_t fcol:12;
+#else
+                uint64_t fcol:12;
+                uint64_t frow:14;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_fadr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:16;
+                uint64_t fcol:14;
+#else
+                uint64_t fcol:14;
+                uint64_t frow:16;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn61xx;
+};
+
+union cvmx_lmcx_ifb_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ifbcnt:64;
+#else
+                uint64_t ifbcnt:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_ifb_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ifbcnt_hi:32;
+#else
+                uint64_t ifbcnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_ifb_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_ifb_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ifbcnt_lo:32;
+#else
+                uint64_t ifbcnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_int {
+        uint64_t u64;
+        struct cvmx_lmcx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t ded_err:4;
+                uint64_t sec_err:4;
+                uint64_t nxm_wr_err:1;
+#else
+                uint64_t nxm_wr_err:1;
+                uint64_t sec_err:4;
+                uint64_t ded_err:4;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_int_en {
+        uint64_t u64;
+        struct cvmx_lmcx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t intr_ded_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_nxm_wr_ena:1;
+#else
+                uint64_t intr_nxm_wr_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_ded_ena:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_mem_cfg0 {
+        uint64_t u64;
+        struct cvmx_lmcx_mem_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t reset:1;
+                uint64_t silo_qc:1;
+                uint64_t bunk_ena:1;
+                uint64_t ded_err:4;
+                uint64_t sec_err:4;
+                uint64_t intr_ded_ena:1;
+                uint64_t intr_sec_ena:1;
+                uint64_t tcl:4;
+                uint64_t ref_int:6;
+                uint64_t pbank_lsb:4;
+                uint64_t row_lsb:3;
+                uint64_t ecc_ena:1;
+                uint64_t init_start:1;
+#else
+                uint64_t init_start:1;
+                uint64_t ecc_ena:1;
+                uint64_t row_lsb:3;
+                uint64_t pbank_lsb:4;
+                uint64_t ref_int:6;
+                uint64_t tcl:4;
+                uint64_t intr_sec_ena:1;
+                uint64_t intr_ded_ena:1;
+                uint64_t sec_err:4;
+                uint64_t ded_err:4;
+                uint64_t bunk_ena:1;
+                uint64_t silo_qc:1;
+                uint64_t reset:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_mem_cfg1 {
+        uint64_t u64;
+        struct cvmx_lmcx_mem_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t comp_bypass:1;
+                uint64_t trrd:3;
+                uint64_t caslat:3;
+                uint64_t tmrd:3;
+                uint64_t trfc:5;
+                uint64_t trp:4;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+#else
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trp:4;
+                uint64_t trfc:5;
+                uint64_t tmrd:3;
+                uint64_t caslat:3;
+                uint64_t trrd:3;
+                uint64_t comp_bypass:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_mem_cfg1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t trrd:3;
+                uint64_t caslat:3;
+                uint64_t tmrd:3;
+                uint64_t trfc:5;
+                uint64_t trp:4;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+#else
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trp:4;
+                uint64_t trfc:5;
+                uint64_t tmrd:3;
+                uint64_t caslat:3;
+                uint64_t trrd:3;
+                uint64_t reserved_31_63:33;
+#endif
+        } cn38xx;
+};
+
+union cvmx_lmcx_modereg_params0 {
+        uint64_t u64;
+        struct cvmx_lmcx_modereg_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t ppd:1;
+                uint64_t wrp:3;
+                uint64_t dllr:1;
+                uint64_t tm:1;
+                uint64_t rbt:1;
+                uint64_t cl:4;
+                uint64_t bl:2;
+                uint64_t qoff:1;
+                uint64_t tdqs:1;
+                uint64_t wlev:1;
+                uint64_t al:2;
+                uint64_t dll:1;
+                uint64_t mpr:1;
+                uint64_t mprloc:2;
+                uint64_t cwl:3;
+#else
+                uint64_t cwl:3;
+                uint64_t mprloc:2;
+                uint64_t mpr:1;
+                uint64_t dll:1;
+                uint64_t al:2;
+                uint64_t wlev:1;
+                uint64_t tdqs:1;
+                uint64_t qoff:1;
+                uint64_t bl:2;
+                uint64_t cl:4;
+                uint64_t rbt:1;
+                uint64_t tm:1;
+                uint64_t dllr:1;
+                uint64_t wrp:3;
+                uint64_t ppd:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_modereg_params1 {
+        uint64_t u64;
+        struct cvmx_lmcx_modereg_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t rtt_nom_11:3;
+                uint64_t dic_11:2;
+                uint64_t rtt_wr_11:2;
+                uint64_t srt_11:1;
+                uint64_t asr_11:1;
+                uint64_t pasr_11:3;
+                uint64_t rtt_nom_10:3;
+                uint64_t dic_10:2;
+                uint64_t rtt_wr_10:2;
+                uint64_t srt_10:1;
+                uint64_t asr_10:1;
+                uint64_t pasr_10:3;
+                uint64_t rtt_nom_01:3;
+                uint64_t dic_01:2;
+                uint64_t rtt_wr_01:2;
+                uint64_t srt_01:1;
+                uint64_t asr_01:1;
+                uint64_t pasr_01:3;
+                uint64_t rtt_nom_00:3;
+                uint64_t dic_00:2;
+                uint64_t rtt_wr_00:2;
+                uint64_t srt_00:1;
+                uint64_t asr_00:1;
+                uint64_t pasr_00:3;
+#else
+                uint64_t pasr_00:3;
+                uint64_t asr_00:1;
+                uint64_t srt_00:1;
+                uint64_t rtt_wr_00:2;
+                uint64_t dic_00:2;
+                uint64_t rtt_nom_00:3;
+                uint64_t pasr_01:3;
+                uint64_t asr_01:1;
+                uint64_t srt_01:1;
+                uint64_t rtt_wr_01:2;
+                uint64_t dic_01:2;
+                uint64_t rtt_nom_01:3;
+                uint64_t pasr_10:3;
+                uint64_t asr_10:1;
+                uint64_t srt_10:1;
+                uint64_t rtt_wr_10:2;
+                uint64_t dic_10:2;
+                uint64_t rtt_nom_10:3;
+                uint64_t pasr_11:3;
+                uint64_t asr_11:1;
+                uint64_t srt_11:1;
+                uint64_t rtt_wr_11:2;
+                uint64_t dic_11:2;
+                uint64_t rtt_nom_11:3;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_nxm {
+        uint64_t u64;
+        struct cvmx_lmcx_nxm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t mem_msb_d3_r1:4;
+                uint64_t mem_msb_d3_r0:4;
+                uint64_t mem_msb_d2_r1:4;
+                uint64_t mem_msb_d2_r0:4;
+                uint64_t mem_msb_d1_r1:4;
+                uint64_t mem_msb_d1_r0:4;
+                uint64_t mem_msb_d0_r1:4;
+                uint64_t mem_msb_d0_r0:4;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t mem_msb_d0_r0:4;
+                uint64_t mem_msb_d0_r1:4;
+                uint64_t mem_msb_d1_r0:4;
+                uint64_t mem_msb_d1_r1:4;
+                uint64_t mem_msb_d2_r0:4;
+                uint64_t mem_msb_d2_r1:4;
+                uint64_t mem_msb_d3_r0:4;
+                uint64_t mem_msb_d3_r1:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+        struct cvmx_lmcx_nxm_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t cs_mask:8;
+#else
+                uint64_t cs_mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn52xx;
+};
+
+union cvmx_lmcx_ops_cnt {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t opscnt:64;
+#else
+                uint64_t opscnt:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_ops_cnt_hi {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t opscnt_hi:32;
+#else
+                uint64_t opscnt_hi:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_ops_cnt_lo {
+        uint64_t u64;
+        struct cvmx_lmcx_ops_cnt_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t opscnt_lo:32;
+#else
+                uint64_t opscnt_lo:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_phy_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_phy_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t rx_always_on:1;
+                uint64_t lv_mode:1;
+                uint64_t ck_tune1:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t loopback:1;
+                uint64_t loopback_pos:1;
+                uint64_t ts_stagger:1;
+#else
+                uint64_t ts_stagger:1;
+                uint64_t loopback_pos:1;
+                uint64_t loopback:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune1:1;
+                uint64_t lv_mode:1;
+                uint64_t rx_always_on:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+        struct cvmx_lmcx_phy_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t lv_mode:1;
+                uint64_t ck_tune1:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t loopback:1;
+                uint64_t loopback_pos:1;
+                uint64_t ts_stagger:1;
+#else
+                uint64_t ts_stagger:1;
+                uint64_t loopback_pos:1;
+                uint64_t loopback:1;
+                uint64_t ck_dlyout0:4;
+                uint64_t ck_tune0:1;
+                uint64_t ck_dlyout1:4;
+                uint64_t ck_tune1:1;
+                uint64_t lv_mode:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_lmcx_pll_bwctl {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_bwctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t bwupd:1;
+                uint64_t bwctl:4;
+#else
+                uint64_t bwctl:4;
+                uint64_t bwupd:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_pll_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_30_63:34;
+                uint64_t bypass:1;
+                uint64_t fasten_n:1;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t fasten_n:1;
+                uint64_t bypass:1;
+                uint64_t reserved_30_63:34;
+#endif
+        } s;
+        struct cvmx_lmcx_pll_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t fasten_n:1;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t fasten_n:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn50xx;
+        struct cvmx_lmcx_pll_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t div_reset:1;
+                uint64_t reset_n:1;
+                uint64_t clkf:12;
+                uint64_t clkr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t en16:1;
+                uint64_t en12:1;
+                uint64_t en8:1;
+                uint64_t en6:1;
+                uint64_t en4:1;
+                uint64_t en2:1;
+#else
+                uint64_t en2:1;
+                uint64_t en4:1;
+                uint64_t en6:1;
+                uint64_t en8:1;
+                uint64_t en12:1;
+                uint64_t en16:1;
+                uint64_t reserved_6_7:2;
+                uint64_t clkr:6;
+                uint64_t clkf:12;
+                uint64_t reset_n:1;
+                uint64_t div_reset:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_lmcx_pll_status {
+        uint64_t u64;
+        struct cvmx_lmcx_pll_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ddr__nctl:5;
+                uint64_t ddr__pctl:5;
+                uint64_t reserved_2_21:20;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t reserved_2_21:20;
+                uint64_t ddr__pctl:5;
+                uint64_t ddr__nctl:5;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_lmcx_pll_status_cn58xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn58xxp1;
+};
+
+union cvmx_lmcx_read_level_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t rankmask:4;
+                uint64_t pattern:8;
+                uint64_t row:16;
+                uint64_t col:12;
+                uint64_t reserved_3_3:1;
+                uint64_t bnk:3;
+#else
+                uint64_t bnk:3;
+                uint64_t reserved_3_3:1;
+                uint64_t col:12;
+                uint64_t row:16;
+                uint64_t pattern:8;
+                uint64_t rankmask:4;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_read_level_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bitmask:16;
+                uint64_t reserved_4_15:12;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t reserved_4_15:12;
+                uint64_t bitmask:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_read_level_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_read_level_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t status:2;
+                uint64_t byte8:4;
+                uint64_t byte7:4;
+                uint64_t byte6:4;
+                uint64_t byte5:4;
+                uint64_t byte4:4;
+                uint64_t byte3:4;
+                uint64_t byte2:4;
+                uint64_t byte1:4;
+                uint64_t byte0:4;
+#else
+                uint64_t byte0:4;
+                uint64_t byte1:4;
+                uint64_t byte2:4;
+                uint64_t byte3:4;
+                uint64_t byte4:4;
+                uint64_t byte5:4;
+                uint64_t byte6:4;
+                uint64_t byte7:4;
+                uint64_t byte8:4;
+                uint64_t status:2;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_reset_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_reset_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t ddr3psv:1;
+                uint64_t ddr3psoft:1;
+                uint64_t ddr3pwarm:1;
+                uint64_t ddr3rst:1;
+#else
+                uint64_t ddr3rst:1;
+                uint64_t ddr3pwarm:1;
+                uint64_t ddr3psoft:1;
+                uint64_t ddr3psv:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_rlevel_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t delay_unload_3:1;
+                uint64_t delay_unload_2:1;
+                uint64_t delay_unload_1:1;
+                uint64_t delay_unload_0:1;
+                uint64_t bitmask:8;
+                uint64_t or_dis:1;
+                uint64_t offset_en:1;
+                uint64_t offset:4;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t offset:4;
+                uint64_t offset_en:1;
+                uint64_t or_dis:1;
+                uint64_t bitmask:8;
+                uint64_t delay_unload_0:1;
+                uint64_t delay_unload_1:1;
+                uint64_t delay_unload_2:1;
+                uint64_t delay_unload_3:1;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t offset_en:1;
+                uint64_t offset:4;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t offset:4;
+                uint64_t offset_en:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_lmcx_rlevel_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bitmask:64;
+#else
+                uint64_t bitmask:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_rlevel_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_rlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t status:2;
+                uint64_t byte8:6;
+                uint64_t byte7:6;
+                uint64_t byte6:6;
+                uint64_t byte5:6;
+                uint64_t byte4:6;
+                uint64_t byte3:6;
+                uint64_t byte2:6;
+                uint64_t byte1:6;
+                uint64_t byte0:6;
+#else
+                uint64_t byte0:6;
+                uint64_t byte1:6;
+                uint64_t byte2:6;
+                uint64_t byte3:6;
+                uint64_t byte4:6;
+                uint64_t byte5:6;
+                uint64_t byte6:6;
+                uint64_t byte7:6;
+                uint64_t byte8:6;
+                uint64_t status:2;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_rodt_comp_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t enable:1;
+                uint64_t reserved_12_15:4;
+                uint64_t nctl:4;
+                uint64_t reserved_5_7:3;
+                uint64_t pctl:5;
+#else
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:4;
+                uint64_t reserved_12_15:4;
+                uint64_t enable:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_rodt_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rodt_hi3:4;
+                uint64_t rodt_hi2:4;
+                uint64_t rodt_hi1:4;
+                uint64_t rodt_hi0:4;
+                uint64_t rodt_lo3:4;
+                uint64_t rodt_lo2:4;
+                uint64_t rodt_lo1:4;
+                uint64_t rodt_lo0:4;
+#else
+                uint64_t rodt_lo0:4;
+                uint64_t rodt_lo1:4;
+                uint64_t rodt_lo2:4;
+                uint64_t rodt_lo3:4;
+                uint64_t rodt_hi0:4;
+                uint64_t rodt_hi1:4;
+                uint64_t rodt_hi2:4;
+                uint64_t rodt_hi3:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_rodt_mask {
+        uint64_t u64;
+        struct cvmx_lmcx_rodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rodt_d3_r1:8;
+                uint64_t rodt_d3_r0:8;
+                uint64_t rodt_d2_r1:8;
+                uint64_t rodt_d2_r0:8;
+                uint64_t rodt_d1_r1:8;
+                uint64_t rodt_d1_r0:8;
+                uint64_t rodt_d0_r1:8;
+                uint64_t rodt_d0_r0:8;
+#else
+                uint64_t rodt_d0_r0:8;
+                uint64_t rodt_d0_r1:8;
+                uint64_t rodt_d1_r0:8;
+                uint64_t rodt_d1_r1:8;
+                uint64_t rodt_d2_r0:8;
+                uint64_t rodt_d2_r1:8;
+                uint64_t rodt_d3_r0:8;
+                uint64_t rodt_d3_r1:8;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_scramble_cfg0 {
+        uint64_t u64;
+        struct cvmx_lmcx_scramble_cfg0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t key:64;
+#else
+                uint64_t key:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_scramble_cfg1 {
+        uint64_t u64;
+        struct cvmx_lmcx_scramble_cfg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t key:64;
+#else
+                uint64_t key:64;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_scrambled_fadr {
+        uint64_t u64;
+        struct cvmx_lmcx_scrambled_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t fdimm:2;
+                uint64_t fbunk:1;
+                uint64_t fbank:3;
+                uint64_t frow:16;
+                uint64_t fcol:14;
+#else
+                uint64_t fcol:14;
+                uint64_t frow:16;
+                uint64_t fbank:3;
+                uint64_t fbunk:1;
+                uint64_t fdimm:2;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_slot_ctl0 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_init:6;
+                uint64_t w2r_init:6;
+                uint64_t r2w_init:6;
+                uint64_t r2r_init:6;
+#else
+                uint64_t r2r_init:6;
+                uint64_t r2w_init:6;
+                uint64_t w2r_init:6;
+                uint64_t w2w_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_slot_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_xrank_init:6;
+                uint64_t w2r_xrank_init:6;
+                uint64_t r2w_xrank_init:6;
+                uint64_t r2r_xrank_init:6;
+#else
+                uint64_t r2r_xrank_init:6;
+                uint64_t r2w_xrank_init:6;
+                uint64_t w2r_xrank_init:6;
+                uint64_t w2w_xrank_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_slot_ctl2 {
+        uint64_t u64;
+        struct cvmx_lmcx_slot_ctl2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t w2w_xdimm_init:6;
+                uint64_t w2r_xdimm_init:6;
+                uint64_t r2w_xdimm_init:6;
+                uint64_t r2r_xdimm_init:6;
+#else
+                uint64_t r2r_xdimm_init:6;
+                uint64_t r2w_xdimm_init:6;
+                uint64_t w2r_xdimm_init:6;
+                uint64_t w2w_xdimm_init:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_timing_params0 {
+        uint64_t u64;
+        struct cvmx_lmcx_timing_params0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t trp_ext:1;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t tckeon:10;
+#else
+                uint64_t tckeon:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t trp_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_lmcx_timing_params0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t trp_ext:1;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t reserved_0_9:10;
+#else
+                uint64_t reserved_0_9:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t trp_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } cn61xx;
+        struct cvmx_lmcx_timing_params0_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t tcksre:4;
+                uint64_t trp:4;
+                uint64_t tzqinit:4;
+                uint64_t tdllk:4;
+                uint64_t tmod:4;
+                uint64_t tmrd:4;
+                uint64_t txpr:4;
+                uint64_t tcke:4;
+                uint64_t tzqcs:4;
+                uint64_t tckeon:10;
+#else
+                uint64_t tckeon:10;
+                uint64_t tzqcs:4;
+                uint64_t tcke:4;
+                uint64_t txpr:4;
+                uint64_t tmrd:4;
+                uint64_t tmod:4;
+                uint64_t tdllk:4;
+                uint64_t tzqinit:4;
+                uint64_t trp:4;
+                uint64_t tcksre:4;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_lmcx_timing_params1 {
+        uint64_t u64;
+        struct cvmx_lmcx_timing_params1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t tras_ext:1;
+                uint64_t txpdll:5;
+                uint64_t tfaw:5;
+                uint64_t twldqsen:4;
+                uint64_t twlmrd:4;
+                uint64_t txp:3;
+                uint64_t trrd:3;
+                uint64_t trfc:5;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+                uint64_t tmprr:4;
+#else
+                uint64_t tmprr:4;
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trfc:5;
+                uint64_t trrd:3;
+                uint64_t txp:3;
+                uint64_t twlmrd:4;
+                uint64_t twldqsen:4;
+                uint64_t tfaw:5;
+                uint64_t txpdll:5;
+                uint64_t tras_ext:1;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+        struct cvmx_lmcx_timing_params1_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t txpdll:5;
+                uint64_t tfaw:5;
+                uint64_t twldqsen:4;
+                uint64_t twlmrd:4;
+                uint64_t txp:3;
+                uint64_t trrd:3;
+                uint64_t trfc:5;
+                uint64_t twtr:4;
+                uint64_t trcd:4;
+                uint64_t tras:5;
+                uint64_t tmprr:4;
+#else
+                uint64_t tmprr:4;
+                uint64_t tras:5;
+                uint64_t trcd:4;
+                uint64_t twtr:4;
+                uint64_t trfc:5;
+                uint64_t trrd:3;
+                uint64_t txp:3;
+                uint64_t twlmrd:4;
+                uint64_t twldqsen:4;
+                uint64_t tfaw:5;
+                uint64_t txpdll:5;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_lmcx_tro_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_tro_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t rclk_cnt:32;
+                uint64_t treset:1;
+#else
+                uint64_t treset:1;
+                uint64_t rclk_cnt:32;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_tro_stat {
+        uint64_t u64;
+        struct cvmx_lmcx_tro_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ring_cnt:32;
+#else
+                uint64_t ring_cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_wlevel_ctl {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t rtt_nom:3;
+                uint64_t bitmask:8;
+                uint64_t or_dis:1;
+                uint64_t sset:1;
+                uint64_t lanemask:9;
+#else
+                uint64_t lanemask:9;
+                uint64_t sset:1;
+                uint64_t or_dis:1;
+                uint64_t bitmask:8;
+                uint64_t rtt_nom:3;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t sset:1;
+                uint64_t lanemask:9;
+#else
+                uint64_t lanemask:9;
+                uint64_t sset:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_lmcx_wlevel_dbg {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t bitmask:8;
+                uint64_t byte:4;
+#else
+                uint64_t byte:4;
+                uint64_t bitmask:8;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_wlevel_rankx {
+        uint64_t u64;
+        struct cvmx_lmcx_wlevel_rankx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t status:2;
+                uint64_t byte8:5;
+                uint64_t byte7:5;
+                uint64_t byte6:5;
+                uint64_t byte5:5;
+                uint64_t byte4:5;
+                uint64_t byte3:5;
+                uint64_t byte2:5;
+                uint64_t byte1:5;
+                uint64_t byte0:5;
+#else
+                uint64_t byte0:5;
+                uint64_t byte1:5;
+                uint64_t byte2:5;
+                uint64_t byte3:5;
+                uint64_t byte4:5;
+                uint64_t byte5:5;
+                uint64_t byte6:5;
+                uint64_t byte7:5;
+                uint64_t byte8:5;
+                uint64_t status:2;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_wodt_ctl0 {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_ctl0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_lmcx_wodt_ctl0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d0_r0:8;
+#else
+                uint64_t wodt_d0_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_lmcx_wodt_ctl0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_hi3:4;
+                uint64_t wodt_hi2:4;
+                uint64_t wodt_hi1:4;
+                uint64_t wodt_hi0:4;
+                uint64_t wodt_lo3:4;
+                uint64_t wodt_lo2:4;
+                uint64_t wodt_lo1:4;
+                uint64_t wodt_lo0:4;
+#else
+                uint64_t wodt_lo0:4;
+                uint64_t wodt_lo1:4;
+                uint64_t wodt_lo2:4;
+                uint64_t wodt_lo3:4;
+                uint64_t wodt_hi0:4;
+                uint64_t wodt_hi1:4;
+                uint64_t wodt_hi2:4;
+                uint64_t wodt_hi3:4;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+};
+
+union cvmx_lmcx_wodt_ctl1 {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_ctl1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wodt_d3_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d2_r0:8;
+#else
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d3_r1:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_lmcx_wodt_mask {
+        uint64_t u64;
+        struct cvmx_lmcx_wodt_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wodt_d3_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d0_r0:8;
+#else
+                uint64_t wodt_d0_r0:8;
+                uint64_t wodt_d0_r1:8;
+                uint64_t wodt_d1_r0:8;
+                uint64_t wodt_d1_r1:8;
+                uint64_t wodt_d2_r0:8;
+                uint64_t wodt_d2_r1:8;
+                uint64_t wodt_d3_r0:8;
+                uint64_t wodt_d3_r1:8;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
new file mode 100644
index 000000000..4ad95d040
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -0,0 +1,4396 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_MIO_DEFS_H__
+#define __CVMX_MIO_DEFS_H__
+
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
+#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
+#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
+#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
+#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
+#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
+#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
+#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
+#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
+#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
+#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
+#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
+#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
+#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
+#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
+#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
+#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
+#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
+#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
+#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
+#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
+
+union cvmx_mio_boot_bist_stat {
+        uint64_t u64;
+        struct cvmx_mio_boot_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_mio_boot_bist_stat_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t ncbo_1:1;
+                uint64_t ncbo_0:1;
+                uint64_t loc:1;
+                uint64_t ncbi:1;
+#else
+                uint64_t ncbi:1;
+                uint64_t loc:1;
+                uint64_t ncbo_0:1;
+                uint64_t ncbo_1:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_mio_boot_bist_stat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t ncbo_0:1;
+                uint64_t loc:1;
+                uint64_t ncbi:1;
+#else
+                uint64_t ncbi:1;
+                uint64_t loc:1;
+                uint64_t ncbo_0:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn38xx;
+        struct cvmx_mio_boot_bist_stat_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t pcm_1:1;
+                uint64_t pcm_0:1;
+                uint64_t ncbo_1:1;
+                uint64_t ncbo_0:1;
+                uint64_t loc:1;
+                uint64_t ncbi:1;
+#else
+                uint64_t ncbi:1;
+                uint64_t loc:1;
+                uint64_t ncbo_0:1;
+                uint64_t ncbo_1:1;
+                uint64_t pcm_0:1;
+                uint64_t pcm_1:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn50xx;
+        struct cvmx_mio_boot_bist_stat_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t ndf:2;
+                uint64_t ncbo_0:1;
+                uint64_t dma:1;
+                uint64_t loc:1;
+                uint64_t ncbi:1;
+#else
+                uint64_t ncbi:1;
+                uint64_t loc:1;
+                uint64_t dma:1;
+                uint64_t ncbo_0:1;
+                uint64_t ndf:2;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn52xx;
+        struct cvmx_mio_boot_bist_stat_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t ncbo_0:1;
+                uint64_t dma:1;
+                uint64_t loc:1;
+                uint64_t ncbi:1;
+#else
+                uint64_t ncbi:1;
+                uint64_t loc:1;
+                uint64_t dma:1;
+                uint64_t ncbo_0:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn52xxp1;
+        struct cvmx_mio_boot_bist_stat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t stat:12;
+#else
+                uint64_t stat:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn61xx;
+        struct cvmx_mio_boot_bist_stat_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t stat:9;
+#else
+                uint64_t stat:9;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn63xx;
+        struct cvmx_mio_boot_bist_stat_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t stat:10;
+#else
+                uint64_t stat:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn66xx;
+};
+
+union cvmx_mio_boot_comp {
+        uint64_t u64;
+        struct cvmx_mio_boot_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_mio_boot_comp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pctl:5;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t pctl:5;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn50xx;
+        struct cvmx_mio_boot_comp_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+#else
+                uint64_t nctl:6;
+                uint64_t pctl:6;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_boot_dma_cfgx {
+        uint64_t u64;
+        struct cvmx_mio_boot_dma_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t en:1;
+                uint64_t rw:1;
+                uint64_t clr:1;
+                uint64_t reserved_60_60:1;
+                uint64_t swap32:1;
+                uint64_t swap16:1;
+                uint64_t swap8:1;
+                uint64_t endian:1;
+                uint64_t size:20;
+                uint64_t adr:36;
+#else
+                uint64_t adr:36;
+                uint64_t size:20;
+                uint64_t endian:1;
+                uint64_t swap8:1;
+                uint64_t swap16:1;
+                uint64_t swap32:1;
+                uint64_t reserved_60_60:1;
+                uint64_t clr:1;
+                uint64_t rw:1;
+                uint64_t en:1;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_dma_intx {
+        uint64_t u64;
+        struct cvmx_mio_boot_dma_intx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t dmarq:1;
+                uint64_t done:1;
+#else
+                uint64_t done:1;
+                uint64_t dmarq:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_dma_int_enx {
+        uint64_t u64;
+        struct cvmx_mio_boot_dma_int_enx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t dmarq:1;
+                uint64_t done:1;
+#else
+                uint64_t done:1;
+                uint64_t dmarq:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_dma_timx {
+        uint64_t u64;
+        struct cvmx_mio_boot_dma_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dmack_pi:1;
+                uint64_t dmarq_pi:1;
+                uint64_t tim_mult:2;
+                uint64_t rd_dly:3;
+                uint64_t ddr:1;
+                uint64_t width:1;
+                uint64_t reserved_48_54:7;
+                uint64_t pause:6;
+                uint64_t dmack_h:6;
+                uint64_t we_n:6;
+                uint64_t we_a:6;
+                uint64_t oe_n:6;
+                uint64_t oe_a:6;
+                uint64_t dmack_s:6;
+                uint64_t dmarq:6;
+#else
+                uint64_t dmarq:6;
+                uint64_t dmack_s:6;
+                uint64_t oe_a:6;
+                uint64_t oe_n:6;
+                uint64_t we_a:6;
+                uint64_t we_n:6;
+                uint64_t dmack_h:6;
+                uint64_t pause:6;
+                uint64_t reserved_48_54:7;
+                uint64_t width:1;
+                uint64_t ddr:1;
+                uint64_t rd_dly:3;
+                uint64_t tim_mult:2;
+                uint64_t dmarq_pi:1;
+                uint64_t dmack_pi:1;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_err {
+        uint64_t u64;
+        struct cvmx_mio_boot_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t wait_err:1;
+                uint64_t adr_err:1;
+#else
+                uint64_t adr_err:1;
+                uint64_t wait_err:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_int {
+        uint64_t u64;
+        struct cvmx_mio_boot_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t wait_int:1;
+                uint64_t adr_int:1;
+#else
+                uint64_t adr_int:1;
+                uint64_t wait_int:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_loc_adr {
+        uint64_t u64;
+        struct cvmx_mio_boot_loc_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t adr:5;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t adr:5;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_loc_cfgx {
+        uint64_t u64;
+        struct cvmx_mio_boot_loc_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t en:1;
+                uint64_t reserved_28_30:3;
+                uint64_t base:25;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t base:25;
+                uint64_t reserved_28_30:3;
+                uint64_t en:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_loc_dat {
+        uint64_t u64;
+        struct cvmx_mio_boot_loc_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_boot_pin_defs {
+        uint64_t u64;
+        struct cvmx_mio_boot_pin_defs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t dmack_p2:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t nand:1;
+                uint64_t user0:8;
+#else
+                uint64_t user0:8;
+                uint64_t nand:1;
+                uint64_t term:2;
+                uint64_t dmack_p0:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p2:1;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t user1:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_mio_boot_pin_defs_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t nand:1;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t nand:1;
+                uint64_t term:2;
+                uint64_t dmack_p0:1;
+                uint64_t dmack_p1:1;
+                uint64_t reserved_13_13:1;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn52xx;
+        struct cvmx_mio_boot_pin_defs_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t dmack_p2:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t reserved_0_8:9;
+#else
+                uint64_t reserved_0_8:9;
+                uint64_t term:2;
+                uint64_t dmack_p0:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p2:1;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn56xx;
+        struct cvmx_mio_boot_pin_defs_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t nand:1;
+                uint64_t user0:8;
+#else
+                uint64_t user0:8;
+                uint64_t nand:1;
+                uint64_t term:2;
+                uint64_t dmack_p0:1;
+                uint64_t dmack_p1:1;
+                uint64_t reserved_13_13:1;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t user1:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_boot_reg_cfgx {
+        uint64_t u64;
+        struct cvmx_mio_boot_reg_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t dmack:2;
+                uint64_t tim_mult:2;
+                uint64_t rd_dly:3;
+                uint64_t sam:1;
+                uint64_t we_ext:2;
+                uint64_t oe_ext:2;
+                uint64_t en:1;
+                uint64_t orbit:1;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t size:12;
+                uint64_t base:16;
+#else
+                uint64_t base:16;
+                uint64_t size:12;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t orbit:1;
+                uint64_t en:1;
+                uint64_t oe_ext:2;
+                uint64_t we_ext:2;
+                uint64_t sam:1;
+                uint64_t rd_dly:3;
+                uint64_t tim_mult:2;
+                uint64_t dmack:2;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+        struct cvmx_mio_boot_reg_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t sam:1;
+                uint64_t we_ext:2;
+                uint64_t oe_ext:2;
+                uint64_t en:1;
+                uint64_t orbit:1;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t size:12;
+                uint64_t base:16;
+#else
+                uint64_t base:16;
+                uint64_t size:12;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t orbit:1;
+                uint64_t en:1;
+                uint64_t oe_ext:2;
+                uint64_t we_ext:2;
+                uint64_t sam:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn30xx;
+        struct cvmx_mio_boot_reg_cfgx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t en:1;
+                uint64_t orbit:1;
+                uint64_t reserved_28_29:2;
+                uint64_t size:12;
+                uint64_t base:16;
+#else
+                uint64_t base:16;
+                uint64_t size:12;
+                uint64_t reserved_28_29:2;
+                uint64_t orbit:1;
+                uint64_t en:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_mio_boot_reg_cfgx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t tim_mult:2;
+                uint64_t rd_dly:3;
+                uint64_t sam:1;
+                uint64_t we_ext:2;
+                uint64_t oe_ext:2;
+                uint64_t en:1;
+                uint64_t orbit:1;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t size:12;
+                uint64_t base:16;
+#else
+                uint64_t base:16;
+                uint64_t size:12;
+                uint64_t width:1;
+                uint64_t ale:1;
+                uint64_t orbit:1;
+                uint64_t en:1;
+                uint64_t oe_ext:2;
+                uint64_t we_ext:2;
+                uint64_t sam:1;
+                uint64_t rd_dly:3;
+                uint64_t tim_mult:2;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn50xx;
+};
+
+union cvmx_mio_boot_reg_timx {
+        uint64_t u64;
+        struct cvmx_mio_boot_reg_timx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pagem:1;
+                uint64_t waitm:1;
+                uint64_t pages:2;
+                uint64_t ale:6;
+                uint64_t page:6;
+                uint64_t wait:6;
+                uint64_t pause:6;
+                uint64_t wr_hld:6;
+                uint64_t rd_hld:6;
+                uint64_t we:6;
+                uint64_t oe:6;
+                uint64_t ce:6;
+                uint64_t adr:6;
+#else
+                uint64_t adr:6;
+                uint64_t ce:6;
+                uint64_t oe:6;
+                uint64_t we:6;
+                uint64_t rd_hld:6;
+                uint64_t wr_hld:6;
+                uint64_t pause:6;
+                uint64_t wait:6;
+                uint64_t page:6;
+                uint64_t ale:6;
+                uint64_t pages:2;
+                uint64_t waitm:1;
+                uint64_t pagem:1;
+#endif
+        } s;
+        struct cvmx_mio_boot_reg_timx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pagem:1;
+                uint64_t waitm:1;
+                uint64_t pages:2;
+                uint64_t reserved_54_59:6;
+                uint64_t page:6;
+                uint64_t wait:6;
+                uint64_t pause:6;
+                uint64_t wr_hld:6;
+                uint64_t rd_hld:6;
+                uint64_t we:6;
+                uint64_t oe:6;
+                uint64_t ce:6;
+                uint64_t adr:6;
+#else
+                uint64_t adr:6;
+                uint64_t ce:6;
+                uint64_t oe:6;
+                uint64_t we:6;
+                uint64_t rd_hld:6;
+                uint64_t wr_hld:6;
+                uint64_t pause:6;
+                uint64_t wait:6;
+                uint64_t page:6;
+                uint64_t reserved_54_59:6;
+                uint64_t pages:2;
+                uint64_t waitm:1;
+                uint64_t pagem:1;
+#endif
+        } cn38xx;
+};
+
+union cvmx_mio_boot_thr {
+        uint64_t u64;
+        struct cvmx_mio_boot_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t dma_thr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t fif_cnt:6;
+                uint64_t reserved_6_7:2;
+                uint64_t fif_thr:6;
+#else
+                uint64_t fif_thr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t fif_cnt:6;
+                uint64_t reserved_14_15:2;
+                uint64_t dma_thr:6;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_mio_boot_thr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t fif_cnt:6;
+                uint64_t reserved_6_7:2;
+                uint64_t fif_thr:6;
+#else
+                uint64_t fif_thr:6;
+                uint64_t reserved_6_7:2;
+                uint64_t fif_cnt:6;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn30xx;
+};
+
+union cvmx_mio_emm_buf_dat {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_buf_idx {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t inc:1;
+                uint64_t reserved_7_15:9;
+                uint64_t buf_num:1;
+                uint64_t offset:6;
+#else
+                uint64_t offset:6;
+                uint64_t buf_num:1;
+                uint64_t reserved_7_15:9;
+                uint64_t inc:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_cfg {
+        uint64_t u64;
+        struct cvmx_mio_emm_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t boot_fail:1;
+                uint64_t reserved_4_15:12;
+                uint64_t bus_ena:4;
+#else
+                uint64_t bus_ena:4;
+                uint64_t reserved_4_15:12;
+                uint64_t boot_fail:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_cmd {
+        uint64_t u64;
+        struct cvmx_mio_emm_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t reserved_56_58:3;
+                uint64_t dbuf:1;
+                uint64_t offset:6;
+                uint64_t reserved_43_48:6;
+                uint64_t ctype_xor:2;
+                uint64_t rtype_xor:3;
+                uint64_t cmd_idx:6;
+                uint64_t arg:32;
+#else
+                uint64_t arg:32;
+                uint64_t cmd_idx:6;
+                uint64_t rtype_xor:3;
+                uint64_t ctype_xor:2;
+                uint64_t reserved_43_48:6;
+                uint64_t offset:6;
+                uint64_t dbuf:1;
+                uint64_t reserved_56_58:3;
+                uint64_t cmd_val:1;
+                uint64_t bus_id:2;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_dma {
+        uint64_t u64;
+        struct cvmx_mio_emm_dma_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t dma_val:1;
+                uint64_t sector:1;
+                uint64_t dat_null:1;
+                uint64_t thres:6;
+                uint64_t rel_wr:1;
+                uint64_t rw:1;
+                uint64_t multi:1;
+                uint64_t block_cnt:16;
+                uint64_t card_addr:32;
+#else
+                uint64_t card_addr:32;
+                uint64_t block_cnt:16;
+                uint64_t multi:1;
+                uint64_t rw:1;
+                uint64_t rel_wr:1;
+                uint64_t thres:6;
+                uint64_t dat_null:1;
+                uint64_t sector:1;
+                uint64_t dma_val:1;
+                uint64_t bus_id:2;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_int {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+#else
+                uint64_t buf_done:1;
+                uint64_t cmd_done:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_err:1;
+                uint64_t switch_done:1;
+                uint64_t switch_err:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_int_en {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+#else
+                uint64_t buf_done:1;
+                uint64_t cmd_done:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_err:1;
+                uint64_t switch_done:1;
+                uint64_t switch_err:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_modex {
+        uint64_t u64;
+        struct cvmx_mio_emm_modex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+#else
+                uint64_t clk_lo:16;
+                uint64_t clk_hi:16;
+                uint64_t power_class:4;
+                uint64_t reserved_36_39:4;
+                uint64_t bus_width:3;
+                uint64_t reserved_43_47:5;
+                uint64_t hs_timing:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_rca {
+        uint64_t u64;
+        struct cvmx_mio_emm_rca_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t card_rca:16;
+#else
+                uint64_t card_rca:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_rsp_hi {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_rsp_lo {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_rsp_sts {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_sts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t switch_val:1;
+                uint64_t dma_val:1;
+                uint64_t dma_pend:1;
+                uint64_t reserved_29_55:27;
+                uint64_t dbuf_err:1;
+                uint64_t reserved_24_27:4;
+                uint64_t dbuf:1;
+                uint64_t blk_timeout:1;
+                uint64_t blk_crc_err:1;
+                uint64_t rsp_busybit:1;
+                uint64_t stp_timeout:1;
+                uint64_t stp_crc_err:1;
+                uint64_t stp_bad_sts:1;
+                uint64_t stp_val:1;
+                uint64_t rsp_timeout:1;
+                uint64_t rsp_crc_err:1;
+                uint64_t rsp_bad_sts:1;
+                uint64_t rsp_val:1;
+                uint64_t rsp_type:3;
+                uint64_t cmd_type:2;
+                uint64_t cmd_idx:6;
+                uint64_t cmd_done:1;
+#else
+                uint64_t cmd_done:1;
+                uint64_t cmd_idx:6;
+                uint64_t cmd_type:2;
+                uint64_t rsp_type:3;
+                uint64_t rsp_val:1;
+                uint64_t rsp_bad_sts:1;
+                uint64_t rsp_crc_err:1;
+                uint64_t rsp_timeout:1;
+                uint64_t stp_val:1;
+                uint64_t stp_bad_sts:1;
+                uint64_t stp_crc_err:1;
+                uint64_t stp_timeout:1;
+                uint64_t rsp_busybit:1;
+                uint64_t blk_crc_err:1;
+                uint64_t blk_timeout:1;
+                uint64_t dbuf:1;
+                uint64_t reserved_24_27:4;
+                uint64_t dbuf_err:1;
+                uint64_t reserved_29_55:27;
+                uint64_t dma_pend:1;
+                uint64_t dma_val:1;
+                uint64_t switch_val:1;
+                uint64_t cmd_val:1;
+                uint64_t bus_id:2;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_sample {
+        uint64_t u64;
+        struct cvmx_mio_emm_sample_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t cmd_cnt:10;
+                uint64_t reserved_10_15:6;
+                uint64_t dat_cnt:10;
+#else
+                uint64_t dat_cnt:10;
+                uint64_t reserved_10_15:6;
+                uint64_t cmd_cnt:10;
+                uint64_t reserved_26_63:38;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_sts_mask {
+        uint64_t u64;
+        struct cvmx_mio_emm_sts_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t sts_msk:32;
+#else
+                uint64_t sts_msk:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_switch {
+        uint64_t u64;
+        struct cvmx_mio_emm_switch_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t switch_exe:1;
+                uint64_t switch_err0:1;
+                uint64_t switch_err1:1;
+                uint64_t switch_err2:1;
+                uint64_t reserved_49_55:7;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+#else
+                uint64_t clk_lo:16;
+                uint64_t clk_hi:16;
+                uint64_t power_class:4;
+                uint64_t reserved_36_39:4;
+                uint64_t bus_width:3;
+                uint64_t reserved_43_47:5;
+                uint64_t hs_timing:1;
+                uint64_t reserved_49_55:7;
+                uint64_t switch_err2:1;
+                uint64_t switch_err1:1;
+                uint64_t switch_err0:1;
+                uint64_t switch_exe:1;
+                uint64_t bus_id:2;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+};
+
+union cvmx_mio_emm_wdog {
+        uint64_t u64;
+        struct cvmx_mio_emm_wdog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t clk_cnt:26;
+#else
+                uint64_t clk_cnt:26;
+                uint64_t reserved_26_63:38;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_bnk_datx {
+        uint64_t u64;
+        struct cvmx_mio_fus_bnk_datx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_dat0 {
+        uint64_t u64;
+        struct cvmx_mio_fus_dat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t man_info:32;
+#else
+                uint64_t man_info:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_dat1 {
+        uint64_t u64;
+        struct cvmx_mio_fus_dat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t man_info:32;
+#else
+                uint64_t man_info:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_dat2 {
+        uint64_t u64;
+        struct cvmx_mio_fus_dat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t run_platform:3;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_30_31:2;
+                uint64_t nokasu:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nokasu:1;
+                uint64_t reserved_30_31:2;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t run_platform:3;
+                uint64_t reserved_59_63:5;
+#endif
+        } s;
+        struct cvmx_mio_fus_dat2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t pll_off:4;
+                uint64_t reserved_1_11:11;
+                uint64_t pp_dis:1;
+#else
+                uint64_t pp_dis:1;
+                uint64_t reserved_1_11:11;
+                uint64_t pll_off:4;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn30xx;
+        struct cvmx_mio_fus_dat2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t pll_off:4;
+                uint64_t reserved_2_11:10;
+                uint64_t pp_dis:2;
+#else
+                uint64_t pp_dis:2;
+                uint64_t reserved_2_11:10;
+                uint64_t pll_off:4;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn31xx;
+        struct cvmx_mio_fus_dat2_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t pp_dis:16;
+#else
+                uint64_t pp_dis:16;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn38xx;
+        struct cvmx_mio_fus_dat2_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_30_31:2;
+                uint64_t nokasu:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t reserved_2_15:14;
+                uint64_t pp_dis:2;
+#else
+                uint64_t pp_dis:2;
+                uint64_t reserved_2_15:14;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nokasu:1;
+                uint64_t reserved_30_31:2;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn50xx;
+        struct cvmx_mio_fus_dat2_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_30_31:2;
+                uint64_t nokasu:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t reserved_4_15:12;
+                uint64_t pp_dis:4;
+#else
+                uint64_t pp_dis:4;
+                uint64_t reserved_4_15:12;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nokasu:1;
+                uint64_t reserved_30_31:2;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn52xx;
+        struct cvmx_mio_fus_dat2_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_30_31:2;
+                uint64_t nokasu:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t reserved_12_15:4;
+                uint64_t pp_dis:12;
+#else
+                uint64_t pp_dis:12;
+                uint64_t reserved_12_15:4;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nokasu:1;
+                uint64_t reserved_30_31:2;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn56xx;
+        struct cvmx_mio_fus_dat2_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_30_63:34;
+                uint64_t nokasu:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t rst_sht:1;
+                uint64_t bist_dis:1;
+                uint64_t chip_id:8;
+                uint64_t pp_dis:16;
+#else
+                uint64_t pp_dis:16;
+                uint64_t chip_id:8;
+                uint64_t bist_dis:1;
+                uint64_t rst_sht:1;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t nokasu:1;
+                uint64_t reserved_30_63:34;
+#endif
+        } cn58xx;
+        struct cvmx_mio_fus_dat2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_4_15:12;
+                uint64_t pp_dis:4;
+#else
+                uint64_t pp_dis:4;
+                uint64_t reserved_4_15:12;
+                uint64_t chip_id:8;
+                uint64_t reserved_24_25:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_31:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn61xx;
+        struct cvmx_mio_fus_dat2_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_6_15:10;
+                uint64_t pp_dis:6;
+#else
+                uint64_t pp_dis:6;
+                uint64_t reserved_6_15:10;
+                uint64_t chip_id:8;
+                uint64_t reserved_24_25:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_31:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } cn63xx;
+        struct cvmx_mio_fus_dat2_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_10_15:6;
+                uint64_t pp_dis:10;
+#else
+                uint64_t pp_dis:10;
+                uint64_t reserved_10_15:6;
+                uint64_t chip_id:8;
+                uint64_t reserved_24_25:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_31:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn66xx;
+        struct cvmx_mio_fus_dat2_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t chip_id:8;
+                uint64_t reserved_24_25:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_29_31:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn68xx;
+        struct cvmx_mio_fus_dat2_cn70xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_31_29:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_25_24:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_15_0:16;
+#else
+                uint64_t reserved_15_0:16;
+                uint64_t chip_id:8;
+                uint64_t reserved_25_24:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_31_29:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn70xx;
+        struct cvmx_mio_fus_dat2_cn73xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t run_platform:3;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_31_29:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_25_24:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_15_0:16;
+#else
+                uint64_t reserved_15_0:16;
+                uint64_t chip_id:8;
+                uint64_t reserved_25_24:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_31_29:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t run_platform:3;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn73xx;
+        struct cvmx_mio_fus_dat2_cn78xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t run_platform:3;
+                uint64_t reserved_48_55:8;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_31_29:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_25_24:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t chip_id:8;
+                uint64_t reserved_25_24:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_31_29:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t reserved_48_55:8;
+                uint64_t run_platform:3;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn78xx;
+        struct cvmx_mio_fus_dat2_cn78xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t run_platform:3;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_31_29:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_25_24:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t chip_id:8;
+                uint64_t reserved_25_24:2;
+                uint64_t nocrypto:1;
+                uint64_t nomul:1;
+                uint64_t nodfa_cp2:1;
+                uint64_t reserved_31_29:3;
+                uint64_t raid_en:1;
+                uint64_t fus318:1;
+                uint64_t dorm_crypto:1;
+                uint64_t power_limit:2;
+                uint64_t rom_info:10;
+                uint64_t fus118:1;
+                uint64_t gbl_pwr_throttle:8;
+                uint64_t run_platform:3;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn78xxp2;
+};
+
+union cvmx_mio_fus_dat3 {
+        uint64_t u64;
+        struct cvmx_mio_fus_dat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t pll_alt_matrix:1;
+                uint64_t reserved_38_39:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_28_31:4;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t reserved_0_23:24;
+#else
+                uint64_t reserved_0_23:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t reserved_28_31:4;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t reserved_38_39:2;
+                uint64_t pll_alt_matrix:1;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } s;
+        struct cvmx_mio_fus_dat3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pll_div4:1;
+                uint64_t reserved_29_30:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+#else
+                uint64_t icache:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_en:1;
+                uint64_t reserved_29_30:2;
+                uint64_t pll_div4:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_mio_fus_dat3_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pll_div4:1;
+                uint64_t zip_crip:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+#else
+                uint64_t icache:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_en:1;
+                uint64_t zip_crip:2;
+                uint64_t pll_div4:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn31xx;
+        struct cvmx_mio_fus_dat3_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t zip_crip:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+#else
+                uint64_t icache:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_en:1;
+                uint64_t zip_crip:2;
+                uint64_t reserved_31_63:33;
+#endif
+        } cn38xx;
+        struct cvmx_mio_fus_dat3_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+#else
+                uint64_t icache:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn38xxp2;
+        struct cvmx_mio_fus_dat3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_58_63:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_40_40:1;
+                uint64_t ema:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_31_31:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t reserved_0_23:24;
+#else
+                uint64_t reserved_0_23:24;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_en:1;
+                uint64_t zip_info:2;
+                uint64_t reserved_31_31:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t ema:2;
+                uint64_t reserved_40_40:1;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t reserved_58_63:6;
+#endif
+        } cn61xx;
+        struct cvmx_mio_fus_dat3_cn70xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t pll_alt_matrix:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t use_int_refclk:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_sz_conf:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t ema1:6;
+                uint64_t reserved_0_17:18;
+#else
+                uint64_t reserved_0_17:18;
+                uint64_t ema1:6;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_sz_conf:1;
+                uint64_t zip_info:2;
+                uint64_t use_int_refclk:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t pll_alt_matrix:1;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } cn70xx;
+        struct cvmx_mio_fus_dat3_cn70xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_38_40:3;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_31_31:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_sz_conf:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t ema1:6;
+                uint64_t reserved_0_17:18;
+#else
+                uint64_t reserved_0_17:18;
+                uint64_t ema1:6;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_sz_conf:1;
+                uint64_t zip_info:2;
+                uint64_t reserved_31_31:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t reserved_38_40:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } cn70xxp1;
+        struct cvmx_mio_fus_dat3_cn73xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t pll_alt_matrix:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t use_int_refclk:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_sz_conf:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t ema1:6;
+                uint64_t nohna_dte:1;
+                uint64_t hna_info_dte:3;
+                uint64_t hna_info_clm:4;
+                uint64_t reserved_9_9:1;
+                uint64_t core_pll_mul:5;
+                uint64_t pnr_pll_mul:4;
+#else
+                uint64_t pnr_pll_mul:4;
+                uint64_t core_pll_mul:5;
+                uint64_t reserved_9_9:1;
+                uint64_t hna_info_clm:4;
+                uint64_t hna_info_dte:3;
+                uint64_t nohna_dte:1;
+                uint64_t ema1:6;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_sz_conf:1;
+                uint64_t zip_info:2;
+                uint64_t use_int_refclk:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t pll_alt_matrix:1;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } cn73xx;
+        struct cvmx_mio_fus_dat3_cn78xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_38_40:3;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_31_31:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_sz_conf:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t ema1:6;
+                uint64_t nohna_dte:1;
+                uint64_t hna_info_dte:3;
+                uint64_t hna_info_clm:4;
+                uint64_t reserved_0_9:10;
+#else
+                uint64_t reserved_0_9:10;
+                uint64_t hna_info_clm:4;
+                uint64_t hna_info_dte:3;
+                uint64_t nohna_dte:1;
+                uint64_t ema1:6;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_sz_conf:1;
+                uint64_t zip_info:2;
+                uint64_t reserved_31_31:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t reserved_38_40:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } cn78xx;
+        struct cvmx_mio_fus_dat3_cnf75xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ema0:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t pll_alt_matrix:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t use_int_refclk:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_sz_conf:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t ema1:6;
+                uint64_t reserved_9_17:9;
+                uint64_t core_pll_mul:5;
+                uint64_t pnr_pll_mul:4;
+#else
+                uint64_t pnr_pll_mul:4;
+                uint64_t core_pll_mul:5;
+                uint64_t reserved_9_17:9;
+                uint64_t ema1:6;
+                uint64_t nodfa_dte:1;
+                uint64_t nozip:1;
+                uint64_t efus_ign:1;
+                uint64_t efus_lck:1;
+                uint64_t bar2_sz_conf:1;
+                uint64_t zip_info:2;
+                uint64_t use_int_refclk:1;
+                uint64_t l2c_crip:3;
+                uint64_t pll_half_dis:1;
+                uint64_t efus_lck_man:1;
+                uint64_t efus_lck_rsv:1;
+                uint64_t pll_bwadj_denom:2;
+                uint64_t pll_alt_matrix:1;
+                uint64_t dfa_info_clm:4;
+                uint64_t dfa_info_dte:3;
+                uint64_t pll_ctl:10;
+                uint64_t ema0:6;
+#endif
+        } cnf75xx;
+};
+
+union cvmx_mio_fus_ema {
+        uint64_t u64;
+        struct cvmx_mio_fus_ema_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t eff_ema:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ema:3;
+#else
+                uint64_t ema:3;
+                uint64_t reserved_3_3:1;
+                uint64_t eff_ema:3;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+        struct cvmx_mio_fus_ema_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t ema:2;
+#else
+                uint64_t ema:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn58xx;
+};
+
+union cvmx_mio_fus_pdf {
+        uint64_t u64;
+        struct cvmx_mio_fus_pdf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pdf:64;
+#else
+                uint64_t pdf:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_pll {
+        uint64_t u64;
+        struct cvmx_mio_fus_pll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t rclk_align_r:8;
+                uint64_t rclk_align_l:8;
+                uint64_t reserved_8_31:24;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t c_cout_rst:1;
+                uint64_t reserved_8_31:24;
+                uint64_t rclk_align_l:8;
+                uint64_t rclk_align_r:8;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_mio_fus_pll_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn50xx;
+        struct cvmx_mio_fus_pll_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+#else
+                uint64_t fbslip:1;
+                uint64_t rfslip:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t c_cout_rst:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_fus_prog {
+        uint64_t u64;
+        struct cvmx_mio_fus_prog_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t soft:1;
+                uint64_t prog:1;
+#else
+                uint64_t prog:1;
+                uint64_t soft:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+        struct cvmx_mio_fus_prog_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t prog:1;
+#else
+                uint64_t prog:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } cn30xx;
+};
+
+union cvmx_mio_fus_prog_times {
+        uint64_t u64;
+        struct cvmx_mio_fus_prog_times_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t reserved_6_31:26;
+                uint64_t setup:6;
+#else
+                uint64_t setup:6;
+                uint64_t reserved_6_31:26;
+                uint64_t prog_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t vgate_pin:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } s;
+        struct cvmx_mio_fus_prog_times_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t prog_pin:1;
+                uint64_t out:8;
+                uint64_t sclk_lo:4;
+                uint64_t sclk_hi:12;
+                uint64_t setup:8;
+#else
+                uint64_t setup:8;
+                uint64_t sclk_hi:12;
+                uint64_t sclk_lo:4;
+                uint64_t out:8;
+                uint64_t prog_pin:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } cn50xx;
+        struct cvmx_mio_fus_prog_times_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t out:7;
+                uint64_t sclk_lo:4;
+                uint64_t sclk_hi:15;
+                uint64_t setup:6;
+#else
+                uint64_t setup:6;
+                uint64_t sclk_hi:15;
+                uint64_t sclk_lo:4;
+                uint64_t out:7;
+                uint64_t prog_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t vgate_pin:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_fus_rcmd {
+        uint64_t u64;
+        struct cvmx_mio_fus_rcmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t dat:8;
+                uint64_t reserved_13_15:3;
+                uint64_t pend:1;
+                uint64_t reserved_9_11:3;
+                uint64_t efuse:1;
+                uint64_t addr:8;
+#else
+                uint64_t addr:8;
+                uint64_t efuse:1;
+                uint64_t reserved_9_11:3;
+                uint64_t pend:1;
+                uint64_t reserved_13_15:3;
+                uint64_t dat:8;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+        struct cvmx_mio_fus_rcmd_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t dat:8;
+                uint64_t reserved_13_15:3;
+                uint64_t pend:1;
+                uint64_t reserved_9_11:3;
+                uint64_t efuse:1;
+                uint64_t reserved_7_7:1;
+                uint64_t addr:7;
+#else
+                uint64_t addr:7;
+                uint64_t reserved_7_7:1;
+                uint64_t efuse:1;
+                uint64_t reserved_9_11:3;
+                uint64_t pend:1;
+                uint64_t reserved_13_15:3;
+                uint64_t dat:8;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn30xx;
+};
+
+union cvmx_mio_fus_read_times {
+        uint64_t u64;
+        struct cvmx_mio_fus_read_times_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t sch:4;
+                uint64_t fsh:4;
+                uint64_t prh:4;
+                uint64_t sdh:4;
+                uint64_t setup:10;
+#else
+                uint64_t setup:10;
+                uint64_t sdh:4;
+                uint64_t prh:4;
+                uint64_t fsh:4;
+                uint64_t sch:4;
+                uint64_t reserved_26_63:38;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_repair_res0 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t too_many:1;
+                uint64_t repair2:18;
+                uint64_t repair1:18;
+                uint64_t repair0:18;
+#else
+                uint64_t repair0:18;
+                uint64_t repair1:18;
+                uint64_t repair2:18;
+                uint64_t too_many:1;
+                uint64_t reserved_55_63:9;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_repair_res1 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t repair5:18;
+                uint64_t repair4:18;
+                uint64_t repair3:18;
+#else
+                uint64_t repair3:18;
+                uint64_t repair4:18;
+                uint64_t repair5:18;
+                uint64_t reserved_54_63:10;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_repair_res2 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t repair6:18;
+#else
+                uint64_t repair6:18;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_spr_repair_res {
+        uint64_t u64;
+        struct cvmx_mio_fus_spr_repair_res_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t repair2:14;
+                uint64_t repair1:14;
+                uint64_t repair0:14;
+#else
+                uint64_t repair0:14;
+                uint64_t repair1:14;
+                uint64_t repair2:14;
+                uint64_t reserved_42_63:22;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_spr_repair_sum {
+        uint64_t u64;
+        struct cvmx_mio_fus_spr_repair_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t too_many:1;
+#else
+                uint64_t too_many:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_tgg {
+        uint64_t u64;
+        struct cvmx_mio_fus_tgg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t val:1;
+                uint64_t dat:63;
+#else
+                uint64_t dat:63;
+                uint64_t val:1;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_unlock {
+        uint64_t u64;
+        struct cvmx_mio_fus_unlock_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t key:24;
+#else
+                uint64_t key:24;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_mio_fus_wadr {
+        uint64_t u64;
+        struct cvmx_mio_fus_wadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t addr:10;
+#else
+                uint64_t addr:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_mio_fus_wadr_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t addr:2;
+#else
+                uint64_t addr:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn50xx;
+        struct cvmx_mio_fus_wadr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t addr:3;
+#else
+                uint64_t addr:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn52xx;
+        struct cvmx_mio_fus_wadr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t addr:4;
+#else
+                uint64_t addr:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_gpio_comp {
+        uint64_t u64;
+        struct cvmx_mio_gpio_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+#else
+                uint64_t nctl:6;
+                uint64_t pctl:6;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_mio_ndf_dma_cfg {
+        uint64_t u64;
+        struct cvmx_mio_ndf_dma_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t en:1;
+                uint64_t rw:1;
+                uint64_t clr:1;
+                uint64_t reserved_60_60:1;
+                uint64_t swap32:1;
+                uint64_t swap16:1;
+                uint64_t swap8:1;
+                uint64_t endian:1;
+                uint64_t size:20;
+                uint64_t adr:36;
+#else
+                uint64_t adr:36;
+                uint64_t size:20;
+                uint64_t endian:1;
+                uint64_t swap8:1;
+                uint64_t swap16:1;
+                uint64_t swap32:1;
+                uint64_t reserved_60_60:1;
+                uint64_t clr:1;
+                uint64_t rw:1;
+                uint64_t en:1;
+#endif
+        } s;
+};
+
+union cvmx_mio_ndf_dma_int {
+        uint64_t u64;
+        struct cvmx_mio_ndf_dma_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t done:1;
+#else
+                uint64_t done:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_ndf_dma_int_en {
+        uint64_t u64;
+        struct cvmx_mio_ndf_dma_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t done:1;
+#else
+                uint64_t done:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_pll_ctl {
+        uint64_t u64;
+        struct cvmx_mio_pll_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t bw_ctl:5;
+#else
+                uint64_t bw_ctl:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_mio_pll_setting {
+        uint64_t u64;
+        struct cvmx_mio_pll_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t setting:17;
+#else
+                uint64_t setting:17;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_ckout_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_hi_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t nanosec:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_ckout_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_lo_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t nanosec:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_ckout_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:64;
+#else
+                uint64_t nanosec:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_ckout_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_clock_cfg {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t pps:1;
+                uint64_t ckout:1;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+#else
+                uint64_t ptp_en:1;
+                uint64_t ext_clk_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t tstmp_en:1;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_in:6;
+                uint64_t evcnt_en:1;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_in:6;
+                uint64_t ckout_en:1;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_out:4;
+                uint64_t pps_en:1;
+                uint64_t pps_inv:1;
+                uint64_t pps_out:5;
+                uint64_t ckout_out4:1;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout:1;
+                uint64_t pps:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } s;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+#else
+                uint64_t ptp_en:1;
+                uint64_t ext_clk_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t tstmp_en:1;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_in:6;
+                uint64_t evcnt_en:1;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_in:6;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+#else
+                uint64_t ptp_en:1;
+                uint64_t ext_clk_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t tstmp_en:1;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_in:6;
+                uint64_t evcnt_en:1;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_in:6;
+                uint64_t ckout_en:1;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_out:4;
+                uint64_t pps_en:1;
+                uint64_t pps_inv:1;
+                uint64_t pps_out:5;
+                uint64_t ckout_out4:1;
+                uint64_t ext_clk_edge:2;
+                uint64_t reserved_40_63:24;
+#endif
+        } cn66xx;
+};
+
+union cvmx_mio_ptp_clock_comp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t nanosec:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_clock_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:64;
+#else
+                uint64_t nanosec:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_clock_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_evt_cnt {
+        uint64_t u64;
+        struct cvmx_mio_ptp_evt_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t cntr:64;
+#else
+                uint64_t cntr:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_phy_1pps_in {
+        uint64_t u64;
+        struct cvmx_mio_ptp_phy_1pps_in_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t sel:5;
+#else
+                uint64_t sel:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_pps_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_hi_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t nanosec:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_pps_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_lo_incr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t nanosec:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_pps_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:64;
+#else
+                uint64_t nanosec:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_pps_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+#else
+                uint64_t frnanosec:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_ptp_timestamp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_timestamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t nanosec:64;
+#else
+                uint64_t nanosec:64;
+#endif
+        } s;
+};
+
+union cvmx_mio_qlmx_cfg {
+        uint64_t u64;
+        struct cvmx_mio_qlmx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t prtmode:1;
+                uint64_t reserved_12_13:2;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_cfg:4;
+#else
+                uint64_t qlm_cfg:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_12_13:2;
+                uint64_t prtmode:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+        struct cvmx_mio_qlmx_cfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t prtmode:1;
+                uint64_t reserved_12_13:2;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_2_7:6;
+                uint64_t qlm_cfg:2;
+#else
+                uint64_t qlm_cfg:2;
+                uint64_t reserved_2_7:6;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_12_13:2;
+                uint64_t prtmode:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn61xx;
+        struct cvmx_mio_qlmx_cfg_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_cfg:4;
+#else
+                uint64_t qlm_cfg:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn66xx;
+        struct cvmx_mio_qlmx_cfg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_cfg:3;
+#else
+                uint64_t qlm_cfg:3;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn68xx;
+};
+
+union cvmx_mio_rst_boot {
+        uint64_t u64;
+        struct cvmx_mio_rst_boot_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_44_47:4;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t qlm3_spd:4;
+                uint64_t qlm4_spd:4;
+                uint64_t reserved_44_47:4;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_50_57:8;
+                uint64_t jt_tstmode:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t romen:1;
+                uint64_t ejtagdis:1;
+                uint64_t jtcsrdis:1;
+                uint64_t chipkill:1;
+#endif
+        } s;
+        struct cvmx_mio_rst_boot_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t reserved_36_47:12;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_50_57:8;
+                uint64_t jt_tstmode:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t romen:1;
+                uint64_t ejtagdis:1;
+                uint64_t jtcsrdis:1;
+                uint64_t chipkill:1;
+#endif
+        } cn61xx;
+        struct cvmx_mio_rst_boot_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn63xx;
+        struct cvmx_mio_rst_boot_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t reserved_50_58:9;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t reserved_36_47:12;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_50_58:9;
+                uint64_t ckill_ppdis:1;
+                uint64_t romen:1;
+                uint64_t ejtagdis:1;
+                uint64_t jtcsrdis:1;
+                uint64_t chipkill:1;
+#endif
+        } cn66xx;
+        struct cvmx_mio_rst_boot_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_44_57:14;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t qlm3_spd:4;
+                uint64_t qlm4_spd:4;
+                uint64_t reserved_44_57:14;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn68xx;
+        struct cvmx_mio_rst_boot_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t qlm0_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm2_spd:4;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:6;
+                uint64_t qlm3_spd:4;
+                uint64_t qlm4_spd:4;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn68xxp1;
+};
+
+union cvmx_mio_rst_cfg {
+        uint64_t u64;
+        struct cvmx_mio_rst_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+#else
+                uint64_t soft_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t cntl_clr_bist:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+        struct cvmx_mio_rst_cfg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bist_delay:58;
+                uint64_t reserved_3_5:3;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+#else
+                uint64_t soft_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t cntl_clr_bist:1;
+                uint64_t reserved_3_5:3;
+                uint64_t bist_delay:58;
+#endif
+        } cn61xx;
+        struct cvmx_mio_rst_cfg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bist_delay:58;
+                uint64_t reserved_2_5:4;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+#else
+                uint64_t soft_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t reserved_2_5:4;
+                uint64_t bist_delay:58;
+#endif
+        } cn63xxp1;
+        struct cvmx_mio_rst_cfg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bist_delay:56;
+                uint64_t reserved_3_7:5;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+#else
+                uint64_t soft_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t cntl_clr_bist:1;
+                uint64_t reserved_3_7:5;
+                uint64_t bist_delay:56;
+#endif
+        } cn68xx;
+};
+
+union cvmx_mio_rst_ckill {
+        uint64_t u64;
+        struct cvmx_mio_rst_ckill_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t timer:47;
+#else
+                uint64_t timer:47;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+};
+
+union cvmx_mio_rst_cntlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_cntlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t prtmode:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t prst_link:1;
+                uint64_t gen1_only:1;
+                uint64_t rev_lanes:1;
+                uint64_t in_rev_ln:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_mio_rst_cntlx_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t prtmode:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t prst_link:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn66xx;
+};
+
+union cvmx_mio_rst_ctlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t prtmode:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t prst_link:1;
+                uint64_t gen1_only:1;
+                uint64_t rev_lanes:1;
+                uint64_t in_rev_ln:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_mio_rst_ctlx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t prtmode:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t prst_link:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn63xx;
+        struct cvmx_mio_rst_ctlx_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t prtmode:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_mio_rst_delay {
+        uint64_t u64;
+        struct cvmx_mio_rst_delay_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t warm_rst_dly:16;
+                uint64_t soft_rst_dly:16;
+#else
+                uint64_t soft_rst_dly:16;
+                uint64_t warm_rst_dly:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_mio_rst_int {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+#else
+                uint64_t rst_link0:1;
+                uint64_t rst_link1:1;
+                uint64_t rst_link2:1;
+                uint64_t rst_link3:1;
+                uint64_t reserved_4_7:4;
+                uint64_t perst0:1;
+                uint64_t perst1:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_mio_rst_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+#else
+                uint64_t rst_link0:1;
+                uint64_t rst_link1:1;
+                uint64_t reserved_2_7:6;
+                uint64_t perst0:1;
+                uint64_t perst1:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_rst_int_en {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+#else
+                uint64_t rst_link0:1;
+                uint64_t rst_link1:1;
+                uint64_t rst_link2:1;
+                uint64_t rst_link3:1;
+                uint64_t reserved_4_7:4;
+                uint64_t perst0:1;
+                uint64_t perst1:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_mio_rst_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+#else
+                uint64_t rst_link0:1;
+                uint64_t rst_link1:1;
+                uint64_t reserved_2_7:6;
+                uint64_t perst0:1;
+                uint64_t perst1:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn61xx;
+};
+
+union cvmx_mio_twsx_int {
+        uint64_t u64;
+        struct cvmx_mio_twsx_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t scl:1;
+                uint64_t sda:1;
+                uint64_t scl_ovr:1;
+                uint64_t sda_ovr:1;
+                uint64_t reserved_7_7:1;
+                uint64_t core_en:1;
+                uint64_t ts_en:1;
+                uint64_t st_en:1;
+                uint64_t reserved_3_3:1;
+                uint64_t core_int:1;
+                uint64_t ts_int:1;
+                uint64_t st_int:1;
+#else
+                uint64_t st_int:1;
+                uint64_t ts_int:1;
+                uint64_t core_int:1;
+                uint64_t reserved_3_3:1;
+                uint64_t st_en:1;
+                uint64_t ts_en:1;
+                uint64_t core_en:1;
+                uint64_t reserved_7_7:1;
+                uint64_t sda_ovr:1;
+                uint64_t scl_ovr:1;
+                uint64_t sda:1;
+                uint64_t scl:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_mio_twsx_int_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t core_en:1;
+                uint64_t ts_en:1;
+                uint64_t st_en:1;
+                uint64_t reserved_3_3:1;
+                uint64_t core_int:1;
+                uint64_t ts_int:1;
+                uint64_t st_int:1;
+#else
+                uint64_t st_int:1;
+                uint64_t ts_int:1;
+                uint64_t core_int:1;
+                uint64_t reserved_3_3:1;
+                uint64_t st_en:1;
+                uint64_t ts_en:1;
+                uint64_t core_en:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn38xxp2;
+};
+
+union cvmx_mio_twsx_sw_twsi {
+        uint64_t u64;
+        struct cvmx_mio_twsx_sw_twsi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t v:1;
+                uint64_t slonly:1;
+                uint64_t eia:1;
+                uint64_t op:4;
+                uint64_t r:1;
+                uint64_t sovr:1;
+                uint64_t size:3;
+                uint64_t scr:2;
+                uint64_t a:10;
+                uint64_t ia:5;
+                uint64_t eop_ia:3;
+                uint64_t d:32;
+#else
+                uint64_t d:32;
+                uint64_t eop_ia:3;
+                uint64_t ia:5;
+                uint64_t a:10;
+                uint64_t scr:2;
+                uint64_t size:3;
+                uint64_t sovr:1;
+                uint64_t r:1;
+                uint64_t op:4;
+                uint64_t eia:1;
+                uint64_t slonly:1;
+                uint64_t v:1;
+#endif
+        } s;
+};
+
+union cvmx_mio_twsx_sw_twsi_ext {
+        uint64_t u64;
+        struct cvmx_mio_twsx_sw_twsi_ext_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t ia:8;
+                uint64_t d:32;
+#else
+                uint64_t d:32;
+                uint64_t ia:8;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_mio_twsx_twsi_sw {
+        uint64_t u64;
+        struct cvmx_mio_twsx_twsi_sw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t v:2;
+                uint64_t reserved_32_61:30;
+                uint64_t d:32;
+#else
+                uint64_t d:32;
+                uint64_t reserved_32_61:30;
+                uint64_t v:2;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_dlh {
+        uint64_t u64;
+        struct cvmx_mio_uartx_dlh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dlh:8;
+#else
+                uint64_t dlh:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_dll {
+        uint64_t u64;
+        struct cvmx_mio_uartx_dll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dll:8;
+#else
+                uint64_t dll:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_far {
+        uint64_t u64;
+        struct cvmx_mio_uartx_far_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t far:1;
+#else
+                uint64_t far:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_fcr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_fcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rxtrig:2;
+                uint64_t txtrig:2;
+                uint64_t reserved_3_3:1;
+                uint64_t txfr:1;
+                uint64_t rxfr:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t rxfr:1;
+                uint64_t txfr:1;
+                uint64_t reserved_3_3:1;
+                uint64_t txtrig:2;
+                uint64_t rxtrig:2;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_htx {
+        uint64_t u64;
+        struct cvmx_mio_uartx_htx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t htx:1;
+#else
+                uint64_t htx:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_ier {
+        uint64_t u64;
+        struct cvmx_mio_uartx_ier_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ptime:1;
+                uint64_t reserved_4_6:3;
+                uint64_t edssi:1;
+                uint64_t elsi:1;
+                uint64_t etbei:1;
+                uint64_t erbfi:1;
+#else
+                uint64_t erbfi:1;
+                uint64_t etbei:1;
+                uint64_t elsi:1;
+                uint64_t edssi:1;
+                uint64_t reserved_4_6:3;
+                uint64_t ptime:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_iir {
+        uint64_t u64;
+        struct cvmx_mio_uartx_iir_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t fen:2;
+                uint64_t reserved_4_5:2;
+                uint64_t iid:4;
+#else
+                uint64_t iid:4;
+                uint64_t reserved_4_5:2;
+                uint64_t fen:2;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_lcr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_lcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dlab:1;
+                uint64_t brk:1;
+                uint64_t reserved_5_5:1;
+                uint64_t eps:1;
+                uint64_t pen:1;
+                uint64_t stop:1;
+                uint64_t cls:2;
+#else
+                uint64_t cls:2;
+                uint64_t stop:1;
+                uint64_t pen:1;
+                uint64_t eps:1;
+                uint64_t reserved_5_5:1;
+                uint64_t brk:1;
+                uint64_t dlab:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_lsr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_lsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ferr:1;
+                uint64_t temt:1;
+                uint64_t thre:1;
+                uint64_t bi:1;
+                uint64_t fe:1;
+                uint64_t pe:1;
+                uint64_t oe:1;
+                uint64_t dr:1;
+#else
+                uint64_t dr:1;
+                uint64_t oe:1;
+                uint64_t pe:1;
+                uint64_t fe:1;
+                uint64_t bi:1;
+                uint64_t thre:1;
+                uint64_t temt:1;
+                uint64_t ferr:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_mcr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_mcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t afce:1;
+                uint64_t loop:1;
+                uint64_t out2:1;
+                uint64_t out1:1;
+                uint64_t rts:1;
+                uint64_t dtr:1;
+#else
+                uint64_t dtr:1;
+                uint64_t rts:1;
+                uint64_t out1:1;
+                uint64_t out2:1;
+                uint64_t loop:1;
+                uint64_t afce:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_msr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_msr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dcd:1;
+                uint64_t ri:1;
+                uint64_t dsr:1;
+                uint64_t cts:1;
+                uint64_t ddcd:1;
+                uint64_t teri:1;
+                uint64_t ddsr:1;
+                uint64_t dcts:1;
+#else
+                uint64_t dcts:1;
+                uint64_t ddsr:1;
+                uint64_t teri:1;
+                uint64_t ddcd:1;
+                uint64_t cts:1;
+                uint64_t dsr:1;
+                uint64_t ri:1;
+                uint64_t dcd:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_rbr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_rbr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rbr:8;
+#else
+                uint64_t rbr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_rfl {
+        uint64_t u64;
+        struct cvmx_mio_uartx_rfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t rfl:7;
+#else
+                uint64_t rfl:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_rfw {
+        uint64_t u64;
+        struct cvmx_mio_uartx_rfw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t rffe:1;
+                uint64_t rfpe:1;
+                uint64_t rfwd:8;
+#else
+                uint64_t rfwd:8;
+                uint64_t rfpe:1;
+                uint64_t rffe:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_sbcr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_sbcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t sbcr:1;
+#else
+                uint64_t sbcr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_scr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_scr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t scr:8;
+#else
+                uint64_t scr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_sfe {
+        uint64_t u64;
+        struct cvmx_mio_uartx_sfe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t sfe:1;
+#else
+                uint64_t sfe:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_srr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_srr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t stfr:1;
+                uint64_t srfr:1;
+                uint64_t usr:1;
+#else
+                uint64_t usr:1;
+                uint64_t srfr:1;
+                uint64_t stfr:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_srt {
+        uint64_t u64;
+        struct cvmx_mio_uartx_srt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t srt:2;
+#else
+                uint64_t srt:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_srts {
+        uint64_t u64;
+        struct cvmx_mio_uartx_srts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t srts:1;
+#else
+                uint64_t srts:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_stt {
+        uint64_t u64;
+        struct cvmx_mio_uartx_stt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t stt:2;
+#else
+                uint64_t stt:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_tfl {
+        uint64_t u64;
+        struct cvmx_mio_uartx_tfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t tfl:7;
+#else
+                uint64_t tfl:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_tfr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_tfr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t tfr:8;
+#else
+                uint64_t tfr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_thr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t thr:8;
+#else
+                uint64_t thr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uartx_usr {
+        uint64_t u64;
+        struct cvmx_mio_uartx_usr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t rff:1;
+                uint64_t rfne:1;
+                uint64_t tfe:1;
+                uint64_t tfnf:1;
+                uint64_t busy:1;
+#else
+                uint64_t busy:1;
+                uint64_t tfnf:1;
+                uint64_t tfe:1;
+                uint64_t rfne:1;
+                uint64_t rff:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_dlh {
+        uint64_t u64;
+        struct cvmx_mio_uart2_dlh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dlh:8;
+#else
+                uint64_t dlh:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_dll {
+        uint64_t u64;
+        struct cvmx_mio_uart2_dll_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dll:8;
+#else
+                uint64_t dll:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_far {
+        uint64_t u64;
+        struct cvmx_mio_uart2_far_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t far:1;
+#else
+                uint64_t far:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_fcr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_fcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rxtrig:2;
+                uint64_t txtrig:2;
+                uint64_t reserved_3_3:1;
+                uint64_t txfr:1;
+                uint64_t rxfr:1;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t rxfr:1;
+                uint64_t txfr:1;
+                uint64_t reserved_3_3:1;
+                uint64_t txtrig:2;
+                uint64_t rxtrig:2;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_htx {
+        uint64_t u64;
+        struct cvmx_mio_uart2_htx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t htx:1;
+#else
+                uint64_t htx:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_ier {
+        uint64_t u64;
+        struct cvmx_mio_uart2_ier_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ptime:1;
+                uint64_t reserved_4_6:3;
+                uint64_t edssi:1;
+                uint64_t elsi:1;
+                uint64_t etbei:1;
+                uint64_t erbfi:1;
+#else
+                uint64_t erbfi:1;
+                uint64_t etbei:1;
+                uint64_t elsi:1;
+                uint64_t edssi:1;
+                uint64_t reserved_4_6:3;
+                uint64_t ptime:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_iir {
+        uint64_t u64;
+        struct cvmx_mio_uart2_iir_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t fen:2;
+                uint64_t reserved_4_5:2;
+                uint64_t iid:4;
+#else
+                uint64_t iid:4;
+                uint64_t reserved_4_5:2;
+                uint64_t fen:2;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_lcr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_lcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dlab:1;
+                uint64_t brk:1;
+                uint64_t reserved_5_5:1;
+                uint64_t eps:1;
+                uint64_t pen:1;
+                uint64_t stop:1;
+                uint64_t cls:2;
+#else
+                uint64_t cls:2;
+                uint64_t stop:1;
+                uint64_t pen:1;
+                uint64_t eps:1;
+                uint64_t reserved_5_5:1;
+                uint64_t brk:1;
+                uint64_t dlab:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_lsr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_lsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ferr:1;
+                uint64_t temt:1;
+                uint64_t thre:1;
+                uint64_t bi:1;
+                uint64_t fe:1;
+                uint64_t pe:1;
+                uint64_t oe:1;
+                uint64_t dr:1;
+#else
+                uint64_t dr:1;
+                uint64_t oe:1;
+                uint64_t pe:1;
+                uint64_t fe:1;
+                uint64_t bi:1;
+                uint64_t thre:1;
+                uint64_t temt:1;
+                uint64_t ferr:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_mcr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_mcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t afce:1;
+                uint64_t loop:1;
+                uint64_t out2:1;
+                uint64_t out1:1;
+                uint64_t rts:1;
+                uint64_t dtr:1;
+#else
+                uint64_t dtr:1;
+                uint64_t rts:1;
+                uint64_t out1:1;
+                uint64_t out2:1;
+                uint64_t loop:1;
+                uint64_t afce:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_msr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_msr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t dcd:1;
+                uint64_t ri:1;
+                uint64_t dsr:1;
+                uint64_t cts:1;
+                uint64_t ddcd:1;
+                uint64_t teri:1;
+                uint64_t ddsr:1;
+                uint64_t dcts:1;
+#else
+                uint64_t dcts:1;
+                uint64_t ddsr:1;
+                uint64_t teri:1;
+                uint64_t ddcd:1;
+                uint64_t cts:1;
+                uint64_t dsr:1;
+                uint64_t ri:1;
+                uint64_t dcd:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_rbr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_rbr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rbr:8;
+#else
+                uint64_t rbr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_rfl {
+        uint64_t u64;
+        struct cvmx_mio_uart2_rfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t rfl:7;
+#else
+                uint64_t rfl:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_rfw {
+        uint64_t u64;
+        struct cvmx_mio_uart2_rfw_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t rffe:1;
+                uint64_t rfpe:1;
+                uint64_t rfwd:8;
+#else
+                uint64_t rfwd:8;
+                uint64_t rfpe:1;
+                uint64_t rffe:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_sbcr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_sbcr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t sbcr:1;
+#else
+                uint64_t sbcr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_scr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_scr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t scr:8;
+#else
+                uint64_t scr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_sfe {
+        uint64_t u64;
+        struct cvmx_mio_uart2_sfe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t sfe:1;
+#else
+                uint64_t sfe:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_srr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_srr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t stfr:1;
+                uint64_t srfr:1;
+                uint64_t usr:1;
+#else
+                uint64_t usr:1;
+                uint64_t srfr:1;
+                uint64_t stfr:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_srt {
+        uint64_t u64;
+        struct cvmx_mio_uart2_srt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t srt:2;
+#else
+                uint64_t srt:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_srts {
+        uint64_t u64;
+        struct cvmx_mio_uart2_srts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t srts:1;
+#else
+                uint64_t srts:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_stt {
+        uint64_t u64;
+        struct cvmx_mio_uart2_stt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t stt:2;
+#else
+                uint64_t stt:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_tfl {
+        uint64_t u64;
+        struct cvmx_mio_uart2_tfl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t tfl:7;
+#else
+                uint64_t tfl:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_tfr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_tfr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t tfr:8;
+#else
+                uint64_t tfr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_thr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t thr:8;
+#else
+                uint64_t thr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_mio_uart2_usr {
+        uint64_t u64;
+        struct cvmx_mio_uart2_usr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t rff:1;
+                uint64_t rfne:1;
+                uint64_t tfe:1;
+                uint64_t tfnf:1;
+                uint64_t busy:1;
+#else
+                uint64_t busy:1;
+                uint64_t tfnf:1;
+                uint64_t tfe:1;
+                uint64_t rfne:1;
+                uint64_t rff:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000..cd60d43e8
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,430 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_MIXX_DEFS_H__
+#define __CVMX_MIXX_DEFS_H__
+
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
+
+union cvmx_mixx_bist {
+        uint64_t u64;
+        struct cvmx_mixx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t opfdat:1;
+                uint64_t mrgdat:1;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+#else
+                uint64_t orfdat:1;
+                uint64_t irfdat:1;
+                uint64_t ipfdat:1;
+                uint64_t mrqdat:1;
+                uint64_t mrgdat:1;
+                uint64_t opfdat:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+        struct cvmx_mixx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+#else
+                uint64_t orfdat:1;
+                uint64_t irfdat:1;
+                uint64_t ipfdat:1;
+                uint64_t mrqdat:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_ctl {
+        uint64_t u64;
+        struct cvmx_mixx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t ts_thresh:4;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+#else
+                uint64_t mrq_hwm:2;
+                uint64_t nbtarb:1;
+                uint64_t lendian:1;
+                uint64_t reset:1;
+                uint64_t en:1;
+                uint64_t busy:1;
+                uint64_t crc_strip:1;
+                uint64_t ts_thresh:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_mixx_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+#else
+                uint64_t mrq_hwm:2;
+                uint64_t nbtarb:1;
+                uint64_t lendian:1;
+                uint64_t reset:1;
+                uint64_t en:1;
+                uint64_t busy:1;
+                uint64_t crc_strip:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_intena {
+        uint64_t u64;
+        struct cvmx_mixx_intena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t tsena:1;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+#else
+                uint64_t ovfena:1;
+                uint64_t ivfena:1;
+                uint64_t othena:1;
+                uint64_t ithena:1;
+                uint64_t data_drpena:1;
+                uint64_t irunena:1;
+                uint64_t orunena:1;
+                uint64_t tsena:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_mixx_intena_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+#else
+                uint64_t ovfena:1;
+                uint64_t ivfena:1;
+                uint64_t othena:1;
+                uint64_t ithena:1;
+                uint64_t data_drpena:1;
+                uint64_t irunena:1;
+                uint64_t orunena:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_ircnt {
+        uint64_t u64;
+        struct cvmx_mixx_ircnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t ircnt:20;
+#else
+                uint64_t ircnt:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_mixx_irhwm {
+        uint64_t u64;
+        struct cvmx_mixx_irhwm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t ibplwm:20;
+                uint64_t irhwm:20;
+#else
+                uint64_t irhwm:20;
+                uint64_t ibplwm:20;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_mixx_iring1 {
+        uint64_t u64;
+        struct cvmx_mixx_iring1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
+                uint64_t ibase:37;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t ibase:37;
+                uint64_t isize:20;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+        struct cvmx_mixx_iring1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t ibase:33;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t ibase:33;
+                uint64_t reserved_36_39:4;
+                uint64_t isize:20;
+                uint64_t reserved_60_63:4;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_iring2 {
+        uint64_t u64;
+        struct cvmx_mixx_iring2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                uint64_t itlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t idbell:20;
+#else
+                uint64_t idbell:20;
+                uint64_t reserved_20_31:12;
+                uint64_t itlptr:20;
+                uint64_t reserved_52_63:12;
+#endif
+        } s;
+};
+
+union cvmx_mixx_isr {
+        uint64_t u64;
+        struct cvmx_mixx_isr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ts:1;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+#else
+                uint64_t odblovf:1;
+                uint64_t idblovf:1;
+                uint64_t orthresh:1;
+                uint64_t irthresh:1;
+                uint64_t data_drp:1;
+                uint64_t irun:1;
+                uint64_t orun:1;
+                uint64_t ts:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+        struct cvmx_mixx_isr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+#else
+                uint64_t odblovf:1;
+                uint64_t idblovf:1;
+                uint64_t orthresh:1;
+                uint64_t irthresh:1;
+                uint64_t data_drp:1;
+                uint64_t irun:1;
+                uint64_t orun:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_orcnt {
+        uint64_t u64;
+        struct cvmx_mixx_orcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t orcnt:20;
+#else
+                uint64_t orcnt:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_mixx_orhwm {
+        uint64_t u64;
+        struct cvmx_mixx_orhwm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t orhwm:20;
+#else
+                uint64_t orhwm:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_mixx_oring1 {
+        uint64_t u64;
+        struct cvmx_mixx_oring1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
+                uint64_t obase:37;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t obase:37;
+                uint64_t osize:20;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+        struct cvmx_mixx_oring1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
+                uint64_t reserved_36_39:4;
+                uint64_t obase:33;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t obase:33;
+                uint64_t reserved_36_39:4;
+                uint64_t osize:20;
+                uint64_t reserved_60_63:4;
+#endif
+        } cn52xx;
+};
+
+union cvmx_mixx_oring2 {
+        uint64_t u64;
+        struct cvmx_mixx_oring2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                uint64_t otlptr:20;
+                uint64_t reserved_20_31:12;
+                uint64_t odbell:20;
+#else
+                uint64_t odbell:20;
+                uint64_t reserved_20_31:12;
+                uint64_t otlptr:20;
+                uint64_t reserved_52_63:12;
+#endif
+        } s;
+};
+
+union cvmx_mixx_remcnt {
+        uint64_t u64;
+        struct cvmx_mixx_remcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                uint64_t iremcnt:20;
+                uint64_t reserved_20_31:12;
+                uint64_t oremcnt:20;
+#else
+                uint64_t oremcnt:20;
+                uint64_t reserved_20_31:12;
+                uint64_t iremcnt:20;
+                uint64_t reserved_52_63:12;
+#endif
+        } s;
+};
+
+union cvmx_mixx_tsctl {
+        uint64_t u64;
+        struct cvmx_mixx_tsctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t tsavl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t tstot:5;
+                uint64_t reserved_5_7:3;
+                uint64_t tscnt:5;
+#else
+                uint64_t tscnt:5;
+                uint64_t reserved_5_7:3;
+                uint64_t tstot:5;
+                uint64_t reserved_13_15:3;
+                uint64_t tsavl:5;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+};
+
+union cvmx_mixx_tstamp {
+        uint64_t u64;
+        struct cvmx_mixx_tstamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t tstamp:64;
+#else
+                uint64_t tstamp:64;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
new file mode 100644
index 000000000..6a51b1ef8
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -0,0 +1,3925 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_NPEI_DEFS_H__
+#define __CVMX_NPEI_DEFS_H__
+
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
+
+union cvmx_npei_bar1_indexx {
+        uint32_t u32;
+        struct cvmx_npei_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_18_31:14;
+                uint32_t addr_idx:14;
+                uint32_t ca:1;
+                uint32_t end_swp:2;
+                uint32_t addr_v:1;
+#else
+                uint32_t addr_v:1;
+                uint32_t end_swp:2;
+                uint32_t ca:1;
+                uint32_t addr_idx:14;
+                uint32_t reserved_18_31:14;
+#endif
+        } s;
+};
+
+union cvmx_npei_bist_status {
+        uint64_t u64;
+        struct cvmx_npei_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pkt_rdf:1;
+                uint64_t reserved_60_62:3;
+                uint64_t pcr_gim:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t reserved_50_52:3;
+                uint64_t pkt_ind:1;
+                uint64_t pkt_slm:1;
+                uint64_t reserved_36_47:12;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t reserved_31_31:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t reserved_2_2:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+#else
+                uint64_t ncb_cmd:1;
+                uint64_t msi:1;
+                uint64_t reserved_2_2:1;
+                uint64_t dif3:1;
+                uint64_t dif2:1;
+                uint64_t dif1:1;
+                uint64_t dif0:1;
+                uint64_t csm1:1;
+                uint64_t csm0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_po:1;
+                uint64_t cpl_p1:1;
+                uint64_t cpl_p0:1;
+                uint64_t n2p1_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p0_c:1;
+                uint64_t reserved_31_31:1;
+                uint64_t d3_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d0_pst:1;
+                uint64_t reserved_36_47:12;
+                uint64_t pkt_slm:1;
+                uint64_t pkt_ind:1;
+                uint64_t reserved_50_52:3;
+                uint64_t pcsr_sl:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_int:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcr_gim:1;
+                uint64_t reserved_60_62:3;
+                uint64_t pkt_rdf:1;
+#endif
+        } s;
+        struct cvmx_npei_bist_status_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pkt_rdf:1;
+                uint64_t reserved_60_62:3;
+                uint64_t pcr_gim:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_pfm:1;
+                uint64_t pkt_pof:1;
+                uint64_t reserved_48_49:2;
+                uint64_t pkt_pop0:1;
+                uint64_t pkt_pop1:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t ds_mem:1;
+                uint64_t reserved_36_39:4;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d4_pst:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dif4:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+#else
+                uint64_t ncb_cmd:1;
+                uint64_t msi:1;
+                uint64_t dif4:1;
+                uint64_t dif3:1;
+                uint64_t dif2:1;
+                uint64_t dif1:1;
+                uint64_t dif0:1;
+                uint64_t csm1:1;
+                uint64_t csm0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_po:1;
+                uint64_t cpl_p1:1;
+                uint64_t cpl_p0:1;
+                uint64_t n2p1_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p0_c:1;
+                uint64_t d4_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d0_pst:1;
+                uint64_t reserved_36_39:4;
+                uint64_t ds_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d0_mem:1;
+                uint64_t pkt_pop1:1;
+                uint64_t pkt_pop0:1;
+                uint64_t reserved_48_49:2;
+                uint64_t pkt_pof:1;
+                uint64_t pkt_pfm:1;
+                uint64_t pkt_imem:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_int:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcr_gim:1;
+                uint64_t reserved_60_62:3;
+                uint64_t pkt_rdf:1;
+#endif
+        } cn52xx;
+        struct cvmx_npei_bist_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t d0_mem0:1;
+                uint64_t d1_mem1:1;
+                uint64_t d2_mem2:1;
+                uint64_t d3_mem3:1;
+                uint64_t dr0_mem:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t dr1_mem:1;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t dr2_mem:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dr3_mem:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+#else
+                uint64_t ncb_cmd:1;
+                uint64_t msi:1;
+                uint64_t dr3_mem:1;
+                uint64_t dif3:1;
+                uint64_t dif2:1;
+                uint64_t dif1:1;
+                uint64_t dif0:1;
+                uint64_t csm1:1;
+                uint64_t csm0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_po:1;
+                uint64_t cpl_p1:1;
+                uint64_t cpl_p0:1;
+                uint64_t n2p1_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p0_c:1;
+                uint64_t dr2_mem:1;
+                uint64_t d3_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d0_pst:1;
+                uint64_t dr1_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d0_mem:1;
+                uint64_t dr0_mem:1;
+                uint64_t d3_mem3:1;
+                uint64_t d2_mem2:1;
+                uint64_t d1_mem1:1;
+                uint64_t d0_mem0:1;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_bist_status_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_58_63:6;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pkt_pout:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_cntm:1;
+                uint64_t pkt_ind:1;
+                uint64_t pkt_slm:1;
+                uint64_t pkt_odf:1;
+                uint64_t pkt_oif:1;
+                uint64_t pkt_out:1;
+                uint64_t pkt_i0:1;
+                uint64_t pkt_i1:1;
+                uint64_t pkt_s0:1;
+                uint64_t pkt_s1:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d4_pst:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dif4:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+#else
+                uint64_t ncb_cmd:1;
+                uint64_t msi:1;
+                uint64_t dif4:1;
+                uint64_t dif3:1;
+                uint64_t dif2:1;
+                uint64_t dif1:1;
+                uint64_t dif0:1;
+                uint64_t csm1:1;
+                uint64_t csm0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_po:1;
+                uint64_t cpl_p1:1;
+                uint64_t cpl_p0:1;
+                uint64_t n2p1_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p0_c:1;
+                uint64_t d4_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d0_pst:1;
+                uint64_t d4_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d0_mem:1;
+                uint64_t pkt_s1:1;
+                uint64_t pkt_s0:1;
+                uint64_t pkt_i1:1;
+                uint64_t pkt_i0:1;
+                uint64_t pkt_out:1;
+                uint64_t pkt_oif:1;
+                uint64_t pkt_odf:1;
+                uint64_t pkt_slm:1;
+                uint64_t pkt_ind:1;
+                uint64_t pkt_cntm:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_pout:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_int:1;
+                uint64_t reserved_58_63:6;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_bist_status2 {
+        uint64_t u64;
+        struct cvmx_npei_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t prd_tag:1;
+                uint64_t prd_st0:1;
+                uint64_t prd_st1:1;
+                uint64_t prd_err:1;
+                uint64_t nrd_st:1;
+                uint64_t nwe_st:1;
+                uint64_t nwe_wr0:1;
+                uint64_t nwe_wr1:1;
+                uint64_t pkt_rd:1;
+                uint64_t psc_p0:1;
+                uint64_t psc_p1:1;
+                uint64_t pkt_gd:1;
+                uint64_t pkt_gl:1;
+                uint64_t pkt_blk:1;
+#else
+                uint64_t pkt_blk:1;
+                uint64_t pkt_gl:1;
+                uint64_t pkt_gd:1;
+                uint64_t psc_p1:1;
+                uint64_t psc_p0:1;
+                uint64_t pkt_rd:1;
+                uint64_t nwe_wr1:1;
+                uint64_t nwe_wr0:1;
+                uint64_t nwe_st:1;
+                uint64_t nrd_st:1;
+                uint64_t prd_err:1;
+                uint64_t prd_st1:1;
+                uint64_t prd_st0:1;
+                uint64_t prd_tag:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_npei_ctl_port0 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_port0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t waitl_com:1;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+                uint64_t wait_com:1;
+#else
+                uint64_t wait_com:1;
+                uint64_t bar2_cax:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_enb:1;
+                uint64_t ptlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ctlp_ro:1;
+                uint64_t inta_map:2;
+                uint64_t intb_map:2;
+                uint64_t intc_map:2;
+                uint64_t intd_map:2;
+                uint64_t inta:1;
+                uint64_t intb:1;
+                uint64_t intc:1;
+                uint64_t intd:1;
+                uint64_t waitl_com:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+};
+
+union cvmx_npei_ctl_port1 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_port1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t waitl_com:1;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+                uint64_t wait_com:1;
+#else
+                uint64_t wait_com:1;
+                uint64_t bar2_cax:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_enb:1;
+                uint64_t ptlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ctlp_ro:1;
+                uint64_t inta_map:2;
+                uint64_t intb_map:2;
+                uint64_t intc_map:2;
+                uint64_t intd_map:2;
+                uint64_t inta:1;
+                uint64_t intb:1;
+                uint64_t intc:1;
+                uint64_t intd:1;
+                uint64_t waitl_com:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } s;
+};
+
+union cvmx_npei_ctl_status {
+        uint64_t u64;
+        struct cvmx_npei_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t cfg_rtry:16;
+                uint64_t ring_en:1;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t pkt_bp:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+#else
+                uint64_t chip_rev:8;
+                uint64_t host_mode:1;
+                uint64_t pkt_bp:4;
+                uint64_t arb:1;
+                uint64_t lnk_rst:1;
+                uint64_t ring_en:1;
+                uint64_t cfg_rtry:16;
+                uint64_t p0_ntags:6;
+                uint64_t p1_ntags:6;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+        struct cvmx_npei_ctl_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_15_15:1;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t reserved_9_12:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+#else
+                uint64_t chip_rev:8;
+                uint64_t host_mode:1;
+                uint64_t reserved_9_12:4;
+                uint64_t arb:1;
+                uint64_t lnk_rst:1;
+                uint64_t reserved_15_15:1;
+                uint64_t cfg_rtry:16;
+                uint64_t p0_ntags:6;
+                uint64_t p1_ntags:6;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_ctl_status_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t pkt_bp:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+#else
+                uint64_t chip_rev:8;
+                uint64_t host_mode:1;
+                uint64_t pkt_bp:4;
+                uint64_t arb:1;
+                uint64_t lnk_rst:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_ctl_status2 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t mps:1;
+                uint64_t mrrs:3;
+                uint64_t c1_w_flt:1;
+                uint64_t c0_w_flt:1;
+                uint64_t c1_b1_s:3;
+                uint64_t c0_b1_s:3;
+                uint64_t c1_wi_d:1;
+                uint64_t c1_b0_d:1;
+                uint64_t c0_wi_d:1;
+                uint64_t c0_b0_d:1;
+#else
+                uint64_t c0_b0_d:1;
+                uint64_t c0_wi_d:1;
+                uint64_t c1_b0_d:1;
+                uint64_t c1_wi_d:1;
+                uint64_t c0_b1_s:3;
+                uint64_t c1_b1_s:3;
+                uint64_t c0_w_flt:1;
+                uint64_t c1_w_flt:1;
+                uint64_t mrrs:3;
+                uint64_t mps:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npei_data_out_cnt {
+        uint64_t u64;
+        struct cvmx_npei_data_out_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ucnt:16;
+                uint64_t p1_fcnt:6;
+                uint64_t p0_ucnt:16;
+                uint64_t p0_fcnt:6;
+#else
+                uint64_t p0_fcnt:6;
+                uint64_t p0_ucnt:16;
+                uint64_t p1_fcnt:6;
+                uint64_t p1_ucnt:16;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npei_dbg_data {
+        uint64_t u64;
+        struct cvmx_npei_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t reserved_25_26:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t qlm1_spd:2;
+                uint64_t reserved_25_26:2;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+        struct cvmx_npei_dbg_data_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t qlm0_link_width:1;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm1_mode:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t qlm1_spd:2;
+                uint64_t qlm1_mode:2;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm0_link_width:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn52xx;
+        struct cvmx_npei_dbg_data_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t qlm2_rev_lanes:1;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm3_spd:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+#else
+                uint64_t data:17;
+                uint64_t dsel_ext:1;
+                uint64_t c_mul:5;
+                uint64_t qlm1_spd:2;
+                uint64_t qlm3_spd:2;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm2_rev_lanes:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn56xx;
+};
+
+union cvmx_npei_dbg_select {
+        uint64_t u64;
+        struct cvmx_npei_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dbg_sel:16;
+#else
+                uint64_t dbg_sel:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npei_dmax_counts {
+        uint64_t u64;
+        struct cvmx_npei_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t fcnt:7;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+};
+
+union cvmx_npei_dmax_dbell {
+        uint32_t u32;
+        struct cvmx_npei_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_16_31:16;
+                uint32_t dbell:16;
+#else
+                uint32_t dbell:16;
+                uint32_t reserved_16_31:16;
+#endif
+        } s;
+};
+
+union cvmx_npei_dmax_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npei_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t idle:1;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:29;
+                uint64_t idle:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } s;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:29;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_dmax_naddr {
+        uint64_t u64;
+        struct cvmx_npei_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma0_int_level {
+        uint64_t u64;
+        struct cvmx_npei_dma0_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t time:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t time:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma1_int_level {
+        uint64_t u64;
+        struct cvmx_npei_dma1_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t time:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t time:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_cnts {
+        uint64_t u64;
+        struct cvmx_npei_dma_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dma1:32;
+                uint64_t dma0:32;
+#else
+                uint64_t dma0:32;
+                uint64_t dma1:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_control {
+        uint64_t u64;
+        struct cvmx_npei_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t p_32b_m:1;
+                uint64_t dma4_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+#else
+                uint64_t csize:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t dma0_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma4_enb:1;
+                uint64_t p_32b_m:1;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+        struct cvmx_npei_dma_control_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+#else
+                uint64_t csize:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t dma0_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t reserved_38_63:26;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_dma_control_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t dma4_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+#else
+                uint64_t csize:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t dma0_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma4_enb:1;
+                uint64_t reserved_39_63:25;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_dma_pcie_req_num {
+        uint64_t u64;
+        struct cvmx_npei_dma_pcie_req_num_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dma_arb:1;
+                uint64_t reserved_53_62:10;
+                uint64_t pkt_cnt:5;
+                uint64_t reserved_45_47:3;
+                uint64_t dma4_cnt:5;
+                uint64_t reserved_37_39:3;
+                uint64_t dma3_cnt:5;
+                uint64_t reserved_29_31:3;
+                uint64_t dma2_cnt:5;
+                uint64_t reserved_21_23:3;
+                uint64_t dma1_cnt:5;
+                uint64_t reserved_13_15:3;
+                uint64_t dma0_cnt:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dma_cnt:5;
+#else
+                uint64_t dma_cnt:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dma0_cnt:5;
+                uint64_t reserved_13_15:3;
+                uint64_t dma1_cnt:5;
+                uint64_t reserved_21_23:3;
+                uint64_t dma2_cnt:5;
+                uint64_t reserved_29_31:3;
+                uint64_t dma3_cnt:5;
+                uint64_t reserved_37_39:3;
+                uint64_t dma4_cnt:5;
+                uint64_t reserved_45_47:3;
+                uint64_t pkt_cnt:5;
+                uint64_t reserved_53_62:10;
+                uint64_t dma_arb:1;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_state1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t d4_dwe:8;
+                uint64_t d3_dwe:8;
+                uint64_t d2_dwe:8;
+                uint64_t d1_dwe:8;
+                uint64_t d0_dwe:8;
+#else
+                uint64_t d0_dwe:8;
+                uint64_t d1_dwe:8;
+                uint64_t d2_dwe:8;
+                uint64_t d3_dwe:8;
+                uint64_t d4_dwe:8;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_state1_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t d4_difst:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t d4_reqst:5;
+#else
+                uint64_t d4_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d0_reqst:5;
+                uint64_t d4_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d0_difst:7;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+        struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t reserved_25_31:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t reserved_0_4:5;
+#else
+                uint64_t reserved_0_4:5;
+                uint64_t d3_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d0_reqst:5;
+                uint64_t reserved_25_31:7;
+                uint64_t d3_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d0_difst:7;
+                uint64_t reserved_60_63:4;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_dma_state2 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t ndwe:4;
+                uint64_t reserved_21_23:3;
+                uint64_t ndre:5;
+                uint64_t reserved_10_15:6;
+                uint64_t prd:10;
+#else
+                uint64_t prd:10;
+                uint64_t reserved_10_15:6;
+                uint64_t ndre:5;
+                uint64_t reserved_21_23:3;
+                uint64_t ndwe:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_state2_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t d4_dffst:9;
+#else
+                uint64_t d4_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d0_dffst:9;
+                uint64_t reserved_45_63:19;
+#endif
+        } s;
+        struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t reserved_0_8:9;
+#else
+                uint64_t reserved_0_8:9;
+                uint64_t d3_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d0_dffst:9;
+                uint64_t reserved_45_63:19;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_dma_state3_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state3_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t d0_drest:15;
+                uint64_t d1_drest:15;
+                uint64_t d2_drest:15;
+                uint64_t d3_drest:15;
+#else
+                uint64_t d3_drest:15;
+                uint64_t d2_drest:15;
+                uint64_t d1_drest:15;
+                uint64_t d0_drest:15;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_state4_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state4_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                uint64_t d0_dwest:13;
+                uint64_t d1_dwest:13;
+                uint64_t d2_dwest:13;
+                uint64_t d3_dwest:13;
+#else
+                uint64_t d3_dwest:13;
+                uint64_t d2_dwest:13;
+                uint64_t d1_dwest:13;
+                uint64_t d0_dwest:13;
+                uint64_t reserved_52_63:12;
+#endif
+        } s;
+};
+
+union cvmx_npei_dma_state5_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state5_p1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t d4_drest:15;
+                uint64_t d4_dwest:13;
+#else
+                uint64_t d4_dwest:13;
+                uint64_t d4_drest:15;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+};
+
+union cvmx_npei_int_a_enb {
+        uint64_t u64;
+        struct cvmx_npei_int_a_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t p0_rdlk:1;
+                uint64_t p1_rdlk:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_npei_int_a_enb_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_int_a_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_int_a_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t p0_rdlk:1;
+                uint64_t p1_rdlk:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_npei_int_a_enb2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_int_a_sum {
+        uint64_t u64;
+        struct cvmx_npei_int_a_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t p0_rdlk:1;
+                uint64_t p1_rdlk:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_npei_int_a_sum_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+#else
+                uint64_t dma0_cpl:1;
+                uint64_t dma1_cpl:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_npei_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_62:1;
+                uint64_t mio_inta:1;
+#endif
+        } s;
+        struct cvmx_npei_int_enb_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_62:1;
+                uint64_t mio_inta:1;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_int_enb_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_61_62:2;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t reserved_61_62:2;
+                uint64_t mio_inta:1;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_int_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+        struct cvmx_npei_int_enb2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_int_enb2_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t reserved_61_63:3;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_info {
+        uint64_t u64;
+        struct cvmx_npei_int_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t pidbof:6;
+                uint64_t psldbof:6;
+#else
+                uint64_t psldbof:6;
+                uint64_t pidbof:6;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_npei_int_sum {
+        uint64_t u64;
+        struct cvmx_npei_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t pcnt:1;
+                uint64_t ptime:1;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_62:1;
+                uint64_t mio_inta:1;
+#endif
+        } s;
+        struct cvmx_npei_int_sum_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_15_18:4;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t reserved_15_18:4;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_62:1;
+                uint64_t mio_inta:1;
+#endif
+        } cn52xxp1;
+        struct cvmx_npei_int_sum_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_61_62:2;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_15_18:4;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t reserved_15_18:4;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t reserved_61_62:2;
+                uint64_t mio_inta:1;
+#endif
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_sum2 {
+        uint64_t u64;
+        struct cvmx_npei_int_sum2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_15_18:4;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t bar0_to:1;
+                uint64_t iob2big:1;
+                uint64_t dma0dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma0fi:1;
+                uint64_t dma1fi:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t reserved_15_18:4;
+                uint64_t c0_aeri:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_wake:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_hpint:1;
+                uint64_t c1_aeri:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_wake:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_hpint:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_ldwn:1;
+                uint64_t int_a:1;
+                uint64_t reserved_62_62:1;
+                uint64_t mio_inta:1;
+#endif
+        } s;
+};
+
+union cvmx_npei_last_win_rdata0 {
+        uint64_t u64;
+        struct cvmx_npei_last_win_rdata0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_last_win_rdata1 {
+        uint64_t u64;
+        struct cvmx_npei_last_win_rdata1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_mem_access_ctl {
+        uint64_t u64;
+        struct cvmx_npei_mem_access_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t max_word:4;
+                uint64_t timer:10;
+#else
+                uint64_t timer:10;
+                uint64_t max_word:4;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_npei_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_npei_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t zero:1;
+                uint64_t port:2;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:30;
+#else
+                uint64_t ba:30;
+                uint64_t row:1;
+                uint64_t ror:1;
+                uint64_t nsw:1;
+                uint64_t nsr:1;
+                uint64_t esw:2;
+                uint64_t esr:2;
+                uint64_t nmerge:1;
+                uint64_t port:2;
+                uint64_t zero:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t enb:64;
+#else
+                uint64_t enb:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t enb:64;
+#else
+                uint64_t enb:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t enb:64;
+#else
+                uint64_t enb:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t enb:64;
+#else
+                uint64_t enb:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_rcv0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t intr:64;
+#else
+                uint64_t intr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_rcv1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t intr:64;
+#else
+                uint64_t intr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_rcv2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t intr:64;
+#else
+                uint64_t intr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_rcv3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t intr:64;
+#else
+                uint64_t intr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_rd_map {
+        uint64_t u64;
+        struct cvmx_npei_msi_rd_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t rd_int:8;
+                uint64_t msi_int:8;
+#else
+                uint64_t msi_int:8;
+                uint64_t rd_int:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1c_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t clr:64;
+#else
+                uint64_t clr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1c_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t clr:64;
+#else
+                uint64_t clr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1c_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t clr:64;
+#else
+                uint64_t clr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1c_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t clr:64;
+#else
+                uint64_t clr:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1s_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t set:64;
+#else
+                uint64_t set:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1s_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t set:64;
+#else
+                uint64_t set:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1s_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t set:64;
+#else
+                uint64_t set:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_w1s_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t set:64;
+#else
+                uint64_t set:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_msi_wr_map {
+        uint64_t u64;
+        struct cvmx_npei_msi_wr_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t ciu_int:8;
+                uint64_t msi_int:8;
+#else
+                uint64_t msi_int:8;
+                uint64_t ciu_int:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npei_pcie_credit_cnt {
+        uint64_t u64;
+        struct cvmx_npei_pcie_credit_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+#else
+                uint64_t p0_pcnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_ccnt:8;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_npei_pcie_msi_rcv {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t intr:8;
+#else
+                uint64_t intr:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_npei_pcie_msi_rcv_b1 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t intr:8;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t intr:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npei_pcie_msi_rcv_b2 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t intr:8;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t intr:8;
+                uint64_t reserved_24_63:40;
+#endif
+        } s;
+};
+
+union cvmx_npei_pcie_msi_rcv_b3 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t intr:8;
+                uint64_t reserved_0_23:24;
+#else
+                uint64_t reserved_0_23:24;
+                uint64_t intr:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_cnts {
+        uint64_t u64;
+        struct cvmx_npei_pktx_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t timer:22;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t timer:22;
+                uint64_t reserved_54_63:10;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_in_bp {
+        uint64_t u64;
+        struct cvmx_npei_pktx_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wmark:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t wmark:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_instr_baddr {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t addr:61;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_instr_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t aoff:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_instr_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t max:9;
+                uint64_t rrp:9;
+                uint64_t wrp:9;
+                uint64_t fcnt:5;
+                uint64_t rsize:32;
+#else
+                uint64_t rsize:32;
+                uint64_t fcnt:5;
+                uint64_t wrp:9;
+                uint64_t rrp:9;
+                uint64_t max:9;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_instr_header {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_header_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t reserved_38_42:5;
+                uint64_t rparmode:2;
+                uint64_t reserved_35_35:1;
+                uint64_t rskp_len:7;
+                uint64_t reserved_22_27:6;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_16_20:5;
+                uint64_t par_mode:2;
+                uint64_t reserved_13_13:1;
+                uint64_t skp_len:7;
+                uint64_t reserved_0_5:6;
+#else
+                uint64_t reserved_0_5:6;
+                uint64_t skp_len:7;
+                uint64_t reserved_13_13:1;
+                uint64_t par_mode:2;
+                uint64_t reserved_16_20:5;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_22_27:6;
+                uint64_t rskp_len:7;
+                uint64_t reserved_35_35:1;
+                uint64_t rparmode:2;
+                uint64_t reserved_38_42:5;
+                uint64_t pbp:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_slist_baddr {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:60;
+                uint64_t reserved_0_3:4;
+#else
+                uint64_t reserved_0_3:4;
+                uint64_t addr:60;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_slist_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t aoff:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pktx_slist_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rsize:32;
+#else
+                uint64_t rsize:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_cnt_int {
+        uint64_t u64;
+        struct cvmx_npei_pkt_cnt_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+#else
+                uint64_t port:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_cnt_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_cnt_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+#else
+                uint64_t port:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_data_out_es {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t es:64;
+#else
+                uint64_t es:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_data_out_ns {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+#else
+                uint64_t nsr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_data_out_ror {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+#else
+                uint64_t ror:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_dpaddr {
+        uint64_t u64;
+        struct cvmx_npei_pkt_dpaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dptr:32;
+#else
+                uint64_t dptr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_in_bp {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bp:32;
+#else
+                uint64_t bp:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_in_donex_cnts {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_donex_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_in_instr_counts {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_instr_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wr_cnt:32;
+                uint64_t rd_cnt:32;
+#else
+                uint64_t rd_cnt:32;
+                uint64_t wr_cnt:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_in_pcie_port {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pp:64;
+#else
+                uint64_t pp:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_input_control {
+        uint64_t u64;
+        struct cvmx_npei_pkt_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+#else
+                uint64_t ror:1;
+                uint64_t esr:2;
+                uint64_t nsr:1;
+                uint64_t use_csr:1;
+                uint64_t d_ror:1;
+                uint64_t d_esr:2;
+                uint64_t d_nsr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_instr_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+#else
+                uint64_t enb:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_instr_rd_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_rd_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rdsize:64;
+#else
+                uint64_t rdsize:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_instr_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t is_64b:32;
+#else
+                uint64_t is_64b:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_int_levels {
+        uint64_t u64;
+        struct cvmx_npei_pkt_int_levels_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t time:22;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t time:22;
+                uint64_t reserved_54_63:10;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_iptr {
+        uint64_t u64;
+        struct cvmx_npei_pkt_iptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iptr:32;
+#else
+                uint64_t iptr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_out_bmode {
+        uint64_t u64;
+        struct cvmx_npei_pkt_out_bmode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bmode:32;
+#else
+                uint64_t bmode:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_out_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_out_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+#else
+                uint64_t enb:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_output_wmark {
+        uint64_t u64;
+        struct cvmx_npei_pkt_output_wmark_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wmark:32;
+#else
+                uint64_t wmark:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_pcie_port {
+        uint64_t u64;
+        struct cvmx_npei_pkt_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pp:64;
+#else
+                uint64_t pp:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_port_in_rst {
+        uint64_t u64;
+        struct cvmx_npei_pkt_port_in_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t in_rst:32;
+                uint64_t out_rst:32;
+#else
+                uint64_t out_rst:32;
+                uint64_t in_rst:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_slist_es {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t es:64;
+#else
+                uint64_t es:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_slist_id_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_id_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+#else
+                uint64_t bsize:16;
+                uint64_t isize:7;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_slist_ns {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+#else
+                uint64_t nsr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_slist_ror {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+#else
+                uint64_t ror:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_time_int {
+        uint64_t u64;
+        struct cvmx_npei_pkt_time_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+#else
+                uint64_t port:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_pkt_time_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_time_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+#else
+                uint64_t port:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npei_rsl_int_blocks {
+        uint64_t u64;
+        struct cvmx_npei_rsl_int_blocks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t iob:1;
+                uint64_t lmc1:1;
+                uint64_t agl:1;
+                uint64_t reserved_24_27:4;
+                uint64_t asxpcs1:1;
+                uint64_t asxpcs0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc0:1;
+                uint64_t l2c:1;
+                uint64_t usb1:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npei:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+#else
+                uint64_t mio:1;
+                uint64_t gmx0:1;
+                uint64_t gmx1:1;
+                uint64_t npei:1;
+                uint64_t key:1;
+                uint64_t fpa:1;
+                uint64_t dfa:1;
+                uint64_t zip:1;
+                uint64_t reserved_8_8:1;
+                uint64_t ipd:1;
+                uint64_t pko:1;
+                uint64_t tim:1;
+                uint64_t pow:1;
+                uint64_t usb:1;
+                uint64_t rad:1;
+                uint64_t usb1:1;
+                uint64_t l2c:1;
+                uint64_t lmc0:1;
+                uint64_t spx0:1;
+                uint64_t spx1:1;
+                uint64_t pip:1;
+                uint64_t reserved_21_21:1;
+                uint64_t asxpcs0:1;
+                uint64_t asxpcs1:1;
+                uint64_t reserved_24_27:4;
+                uint64_t agl:1;
+                uint64_t lmc1:1;
+                uint64_t iob:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_npei_scratch_1 {
+        uint64_t u64;
+        struct cvmx_npei_scratch_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_state1 {
+        uint64_t u64;
+        struct cvmx_npei_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t cpl1:12;
+                uint64_t cpl0:12;
+                uint64_t arb:1;
+                uint64_t csr:39;
+#else
+                uint64_t csr:39;
+                uint64_t arb:1;
+                uint64_t cpl0:12;
+                uint64_t cpl1:12;
+#endif
+        } s;
+};
+
+union cvmx_npei_state2 {
+        uint64_t u64;
+        struct cvmx_npei_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t npei:1;
+                uint64_t rac:1;
+                uint64_t csm1:15;
+                uint64_t csm0:15;
+                uint64_t nnp0:8;
+                uint64_t nnd:8;
+#else
+                uint64_t nnd:8;
+                uint64_t nnp0:8;
+                uint64_t csm0:15;
+                uint64_t csm1:15;
+                uint64_t rac:1;
+                uint64_t npei:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_npei_state3 {
+        uint64_t u64;
+        struct cvmx_npei_state3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t psm1:15;
+                uint64_t psm0:15;
+                uint64_t nsm1:13;
+                uint64_t nsm0:13;
+#else
+                uint64_t nsm0:13;
+                uint64_t nsm1:13;
+                uint64_t psm0:15;
+                uint64_t psm1:15;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+};
+
+union cvmx_npei_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_npei_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                uint64_t ld_cmd:2;
+                uint64_t iobit:1;
+                uint64_t rd_addr:48;
+#else
+                uint64_t rd_addr:48;
+                uint64_t iobit:1;
+                uint64_t ld_cmd:2;
+                uint64_t reserved_51_63:13;
+#endif
+        } s;
+};
+
+union cvmx_npei_win_rd_data {
+        uint64_t u64;
+        struct cvmx_npei_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rd_data:64;
+#else
+                uint64_t rd_data:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:46;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t wr_addr:46;
+                uint64_t iobit:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+};
+
+union cvmx_npei_win_wr_data {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wr_data:64;
+#else
+                uint64_t wr_data:64;
+#endif
+        } s;
+};
+
+union cvmx_npei_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+#else
+                uint64_t wr_mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_npei_window_ctl {
+        uint64_t u64;
+        struct cvmx_npei_window_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+#else
+                uint64_t time:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
new file mode 100644
index 000000000..ba4967fda
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -0,0 +1,2514 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_NPI_DEFS_H__
+#define __CVMX_NPI_DEFS_H__
+
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
+
+union cvmx_npi_base_addr_inputx {
+        uint64_t u64;
+        struct cvmx_npi_base_addr_inputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t baddr:61;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t baddr:61;
+#endif
+        } s;
+};
+
+union cvmx_npi_base_addr_outputx {
+        uint64_t u64;
+        struct cvmx_npi_base_addr_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t baddr:61;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t baddr:61;
+#endif
+        } s;
+};
+
+union cvmx_npi_bist_status {
+        uint64_t u64;
+        struct cvmx_npi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pof1_bs:1;
+                uint64_t pof2_bs:1;
+                uint64_t pof3_bs:1;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+#else
+                uint64_t dpi_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t pos_bs:1;
+                uint64_t pof3_bs:1;
+                uint64_t pof2_bs:1;
+                uint64_t pof1_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t csr_bs:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_npi_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t reserved_5_7:3;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+#else
+                uint64_t dpi_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t pos_bs:1;
+                uint64_t reserved_5_7:3;
+                uint64_t pof0_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t csr_bs:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn30xx;
+        struct cvmx_npi_bist_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pof1_bs:1;
+                uint64_t reserved_5_6:2;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+#else
+                uint64_t dpi_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t pos_bs:1;
+                uint64_t reserved_5_6:2;
+                uint64_t pof1_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t csr_bs:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn50xx;
+};
+
+union cvmx_npi_buff_size_outputx {
+        uint64_t u64;
+        struct cvmx_npi_buff_size_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+#else
+                uint64_t bsize:16;
+                uint64_t isize:7;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+};
+
+union cvmx_npi_comp_ctl {
+        uint64_t u64;
+        struct cvmx_npi_comp_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t pctl:5;
+                uint64_t nctl:5;
+#else
+                uint64_t nctl:5;
+                uint64_t pctl:5;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_npi_ctl_status {
+        uint64_t u64;
+        struct cvmx_npi_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t out3_enb:1;
+                uint64_t out2_enb:1;
+                uint64_t out1_enb:1;
+                uint64_t out0_enb:1;
+                uint64_t ins3_enb:1;
+                uint64_t ins2_enb:1;
+                uint64_t ins1_enb:1;
+                uint64_t ins0_enb:1;
+                uint64_t ins3_64b:1;
+                uint64_t ins2_64b:1;
+                uint64_t ins1_64b:1;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+#else
+                uint64_t timer:10;
+                uint64_t reserved_10_31:22;
+                uint64_t max_word:5;
+                uint64_t reserved_37_39:3;
+                uint64_t wait_com:1;
+                uint64_t pci_wdis:1;
+                uint64_t ins0_64b:1;
+                uint64_t ins1_64b:1;
+                uint64_t ins2_64b:1;
+                uint64_t ins3_64b:1;
+                uint64_t ins0_enb:1;
+                uint64_t ins1_enb:1;
+                uint64_t ins2_enb:1;
+                uint64_t ins3_enb:1;
+                uint64_t out0_enb:1;
+                uint64_t out1_enb:1;
+                uint64_t out2_enb:1;
+                uint64_t out3_enb:1;
+                uint64_t dis_pniw:1;
+                uint64_t chip_rev:8;
+                uint64_t reserved_63_63:1;
+#endif
+        } s;
+        struct cvmx_npi_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t reserved_51_53:3;
+                uint64_t out0_enb:1;
+                uint64_t reserved_47_49:3;
+                uint64_t ins0_enb:1;
+                uint64_t reserved_43_45:3;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+#else
+                uint64_t timer:10;
+                uint64_t reserved_10_31:22;
+                uint64_t max_word:5;
+                uint64_t reserved_37_39:3;
+                uint64_t wait_com:1;
+                uint64_t pci_wdis:1;
+                uint64_t ins0_64b:1;
+                uint64_t reserved_43_45:3;
+                uint64_t ins0_enb:1;
+                uint64_t reserved_47_49:3;
+                uint64_t out0_enb:1;
+                uint64_t reserved_51_53:3;
+                uint64_t dis_pniw:1;
+                uint64_t chip_rev:8;
+                uint64_t reserved_63_63:1;
+#endif
+        } cn30xx;
+        struct cvmx_npi_ctl_status_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t reserved_52_53:2;
+                uint64_t out1_enb:1;
+                uint64_t out0_enb:1;
+                uint64_t reserved_48_49:2;
+                uint64_t ins1_enb:1;
+                uint64_t ins0_enb:1;
+                uint64_t reserved_44_45:2;
+                uint64_t ins1_64b:1;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+#else
+                uint64_t timer:10;
+                uint64_t reserved_10_31:22;
+                uint64_t max_word:5;
+                uint64_t reserved_37_39:3;
+                uint64_t wait_com:1;
+                uint64_t pci_wdis:1;
+                uint64_t ins0_64b:1;
+                uint64_t ins1_64b:1;
+                uint64_t reserved_44_45:2;
+                uint64_t ins0_enb:1;
+                uint64_t ins1_enb:1;
+                uint64_t reserved_48_49:2;
+                uint64_t out0_enb:1;
+                uint64_t out1_enb:1;
+                uint64_t reserved_52_53:2;
+                uint64_t dis_pniw:1;
+                uint64_t chip_rev:8;
+                uint64_t reserved_63_63:1;
+#endif
+        } cn31xx;
+};
+
+union cvmx_npi_dbg_select {
+        uint64_t u64;
+        struct cvmx_npi_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dbg_sel:16;
+#else
+                uint64_t dbg_sel:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npi_dma_control {
+        uint64_t u64;
+        struct cvmx_npi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t hp_enb:1;
+                uint64_t lp_enb:1;
+                uint64_t csize:14;
+#else
+                uint64_t csize:14;
+                uint64_t lp_enb:1;
+                uint64_t hp_enb:1;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_npi_dma_highp_counts {
+        uint64_t u64;
+        struct cvmx_npi_dma_highp_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t fcnt:7;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+};
+
+union cvmx_npi_dma_highp_naddr {
+        uint64_t u64;
+        struct cvmx_npi_dma_highp_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t state:4;
+                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t state:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_npi_dma_lowp_counts {
+        uint64_t u64;
+        struct cvmx_npi_dma_lowp_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t fcnt:7;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+};
+
+union cvmx_npi_dma_lowp_naddr {
+        uint64_t u64;
+        struct cvmx_npi_dma_lowp_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t state:4;
+                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t state:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_npi_highp_dbell {
+        uint64_t u64;
+        struct cvmx_npi_highp_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+#else
+                uint64_t dbell:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npi_highp_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npi_highp_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:36;
+#else
+                uint64_t saddr:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_npi_input_control {
+        uint64_t u64;
+        struct cvmx_npi_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+#else
+                uint64_t ror:1;
+                uint64_t esr:2;
+                uint64_t nsr:1;
+                uint64_t use_csr:1;
+                uint64_t d_ror:1;
+                uint64_t d_esr:2;
+                uint64_t d_nsr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+        struct cvmx_npi_input_control_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+#else
+                uint64_t ror:1;
+                uint64_t esr:2;
+                uint64_t nsr:1;
+                uint64_t use_csr:1;
+                uint64_t d_ror:1;
+                uint64_t d_esr:2;
+                uint64_t d_nsr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t reserved_22_63:42;
+#endif
+        } cn30xx;
+};
+
+union cvmx_npi_int_enb {
+        uint64_t u64;
+        struct cvmx_npi_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po3_2sml:1;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i3_rtout:1;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i3_overf:1;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p3_rtout:1;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p3_perr:1;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g3_rtout:1;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p3_pperr:1;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p3_ptout:1;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i3_pperr:1;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+        struct cvmx_npi_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_36_38:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_32_34:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_24_26:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_20_22:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_12_14:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_4_6:3;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t reserved_4_6:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_12_14:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_20_22:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_24_26:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_32_34:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_36_38:3;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn30xx;
+        struct cvmx_npi_int_enb_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_37_38:2;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_33_34:2;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_25_26:2;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_21_22:2;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_13_14:2;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_5_6:2;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t reserved_5_6:2;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t reserved_13_14:2;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t reserved_21_22:2;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t reserved_25_26:2;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t reserved_33_34:2;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t reserved_37_38:2;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn31xx;
+        struct cvmx_npi_int_enb_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po3_2sml:1;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i3_rtout:1;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i3_overf:1;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p3_rtout:1;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p3_perr:1;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g3_rtout:1;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p3_pperr:1;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p3_ptout:1;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i3_pperr:1;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn38xxp2;
+};
+
+union cvmx_npi_int_sum {
+        uint64_t u64;
+        struct cvmx_npi_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po3_2sml:1;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i3_rtout:1;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i3_overf:1;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p3_rtout:1;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p3_perr:1;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g3_rtout:1;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p3_pperr:1;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p3_ptout:1;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i3_pperr:1;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+        struct cvmx_npi_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_36_38:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_32_34:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_24_26:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_20_22:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_12_14:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_4_6:3;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t reserved_4_6:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_12_14:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_20_22:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_24_26:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_32_34:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_36_38:3;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn30xx;
+        struct cvmx_npi_int_sum_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_37_38:2;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_33_34:2;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_25_26:2;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_21_22:2;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_13_14:2;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_5_6:2;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t reserved_5_6:2;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t reserved_13_14:2;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t reserved_21_22:2;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t reserved_25_26:2;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t reserved_33_34:2;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t reserved_37_38:2;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t fcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t rwx_s_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t pcf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t q1_a_f:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } cn31xx;
+        struct cvmx_npi_int_sum_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+#else
+                uint64_t rml_rto:1;
+                uint64_t rml_wto:1;
+                uint64_t pci_rsl:1;
+                uint64_t po0_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po3_2sml:1;
+                uint64_t i0_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i3_rtout:1;
+                uint64_t i0_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i3_overf:1;
+                uint64_t p0_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p3_rtout:1;
+                uint64_t p0_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p3_perr:1;
+                uint64_t g0_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g3_rtout:1;
+                uint64_t p0_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p3_pperr:1;
+                uint64_t p0_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p3_ptout:1;
+                uint64_t i0_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i3_pperr:1;
+                uint64_t win_rto:1;
+                uint64_t p_dperr:1;
+                uint64_t iobdma:1;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn38xxp2;
+};
+
+union cvmx_npi_lowp_dbell {
+        uint64_t u64;
+        struct cvmx_npi_lowp_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+#else
+                uint64_t dbell:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_npi_lowp_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npi_lowp_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:36;
+#else
+                uint64_t saddr:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_npi_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_npi_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t shortl:1;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:28;
+#else
+                uint64_t ba:28;
+                uint64_t row:1;
+                uint64_t ror:1;
+                uint64_t nsw:1;
+                uint64_t nsr:1;
+                uint64_t esw:2;
+                uint64_t esr:2;
+                uint64_t nmerge:1;
+                uint64_t shortl:1;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+        struct cvmx_npi_mem_access_subidx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:28;
+#else
+                uint64_t ba:28;
+                uint64_t row:1;
+                uint64_t ror:1;
+                uint64_t nsw:1;
+                uint64_t nsr:1;
+                uint64_t esw:2;
+                uint64_t esr:2;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn31xx;
+};
+
+union cvmx_npi_msi_rcv {
+        uint64_t u64;
+        struct cvmx_npi_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t int_vec:64;
+#else
+                uint64_t int_vec:64;
+#endif
+        } s;
+};
+
+union cvmx_npi_num_desc_outputx {
+        uint64_t u64;
+        struct cvmx_npi_num_desc_outputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t size:32;
+#else
+                uint64_t size:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npi_output_control {
+        uint64_t u64;
+        struct cvmx_npi_output_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t pkt_rr:1;
+                uint64_t p3_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t o3_es:2;
+                uint64_t o3_ns:1;
+                uint64_t o3_ro:1;
+                uint64_t o2_es:2;
+                uint64_t o2_ns:1;
+                uint64_t o2_ro:1;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t o3_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_20_23:4;
+                uint64_t iptr_o3:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t esr_sl3:2;
+                uint64_t nsr_sl3:1;
+                uint64_t ror_sl3:1;
+                uint64_t esr_sl2:2;
+                uint64_t nsr_sl2:1;
+                uint64_t ror_sl2:1;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+#else
+                uint64_t ror_sl0:1;
+                uint64_t nsr_sl0:1;
+                uint64_t esr_sl0:2;
+                uint64_t ror_sl1:1;
+                uint64_t nsr_sl1:1;
+                uint64_t esr_sl1:2;
+                uint64_t ror_sl2:1;
+                uint64_t nsr_sl2:1;
+                uint64_t esr_sl2:2;
+                uint64_t ror_sl3:1;
+                uint64_t nsr_sl3:1;
+                uint64_t esr_sl3:2;
+                uint64_t iptr_o0:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o3:1;
+                uint64_t reserved_20_23:4;
+                uint64_t o0_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o3_csrm:1;
+                uint64_t o0_ro:1;
+                uint64_t o0_ns:1;
+                uint64_t o0_es:2;
+                uint64_t o1_ro:1;
+                uint64_t o1_ns:1;
+                uint64_t o1_es:2;
+                uint64_t o2_ro:1;
+                uint64_t o2_ns:1;
+                uint64_t o2_es:2;
+                uint64_t o3_ro:1;
+                uint64_t o3_ns:1;
+                uint64_t o3_es:2;
+                uint64_t p0_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p3_bmode:1;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+        struct cvmx_npi_output_control_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_32_43:12;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_25_27:3;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_17_23:7;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_4_15:12;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+#else
+                uint64_t ror_sl0:1;
+                uint64_t nsr_sl0:1;
+                uint64_t esr_sl0:2;
+                uint64_t reserved_4_15:12;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_17_23:7;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_25_27:3;
+                uint64_t o0_ro:1;
+                uint64_t o0_ns:1;
+                uint64_t o0_es:2;
+                uint64_t reserved_32_43:12;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_45_63:19;
+#endif
+        } cn30xx;
+        struct cvmx_npi_output_control_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_36_43:8;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_18_23:6;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+#else
+                uint64_t ror_sl0:1;
+                uint64_t nsr_sl0:1;
+                uint64_t esr_sl0:2;
+                uint64_t ror_sl1:1;
+                uint64_t nsr_sl1:1;
+                uint64_t esr_sl1:2;
+                uint64_t reserved_8_15:8;
+                uint64_t iptr_o0:1;
+                uint64_t iptr_o1:1;
+                uint64_t reserved_18_23:6;
+                uint64_t o0_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o0_ro:1;
+                uint64_t o0_ns:1;
+                uint64_t o0_es:2;
+                uint64_t o1_ro:1;
+                uint64_t o1_ns:1;
+                uint64_t o1_es:2;
+                uint64_t reserved_36_43:8;
+                uint64_t p0_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t reserved_46_63:18;
+#endif
+        } cn31xx;
+        struct cvmx_npi_output_control_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t p3_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t o3_es:2;
+                uint64_t o3_ns:1;
+                uint64_t o3_ro:1;
+                uint64_t o2_es:2;
+                uint64_t o2_ns:1;
+                uint64_t o2_ro:1;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t o3_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_20_23:4;
+                uint64_t iptr_o3:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t esr_sl3:2;
+                uint64_t nsr_sl3:1;
+                uint64_t ror_sl3:1;
+                uint64_t esr_sl2:2;
+                uint64_t nsr_sl2:1;
+                uint64_t ror_sl2:1;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+#else
+                uint64_t ror_sl0:1;
+                uint64_t nsr_sl0:1;
+                uint64_t esr_sl0:2;
+                uint64_t ror_sl1:1;
+                uint64_t nsr_sl1:1;
+                uint64_t esr_sl1:2;
+                uint64_t ror_sl2:1;
+                uint64_t nsr_sl2:1;
+                uint64_t esr_sl2:2;
+                uint64_t ror_sl3:1;
+                uint64_t nsr_sl3:1;
+                uint64_t esr_sl3:2;
+                uint64_t iptr_o0:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o3:1;
+                uint64_t reserved_20_23:4;
+                uint64_t o0_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o3_csrm:1;
+                uint64_t o0_ro:1;
+                uint64_t o0_ns:1;
+                uint64_t o0_es:2;
+                uint64_t o1_ro:1;
+                uint64_t o1_ns:1;
+                uint64_t o1_es:2;
+                uint64_t o2_ro:1;
+                uint64_t o2_ns:1;
+                uint64_t o2_es:2;
+                uint64_t o3_ro:1;
+                uint64_t o3_ns:1;
+                uint64_t o3_es:2;
+                uint64_t p0_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p3_bmode:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn38xxp2;
+        struct cvmx_npi_output_control_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_46_47:2;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_36_43:8;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_18_23:6;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+#else
+                uint64_t ror_sl0:1;
+                uint64_t nsr_sl0:1;
+                uint64_t esr_sl0:2;
+                uint64_t ror_sl1:1;
+                uint64_t nsr_sl1:1;
+                uint64_t esr_sl1:2;
+                uint64_t reserved_8_15:8;
+                uint64_t iptr_o0:1;
+                uint64_t iptr_o1:1;
+                uint64_t reserved_18_23:6;
+                uint64_t o0_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o0_ro:1;
+                uint64_t o0_ns:1;
+                uint64_t o0_es:2;
+                uint64_t o1_ro:1;
+                uint64_t o1_ns:1;
+                uint64_t o1_es:2;
+                uint64_t reserved_36_43:8;
+                uint64_t p0_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t reserved_46_47:2;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } cn50xx;
+};
+
+union cvmx_npi_px_dbpair_addr {
+        uint64_t u64;
+        struct cvmx_npi_px_dbpair_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t state:2;
+                uint64_t naddr:61;
+#else
+                uint64_t naddr:61;
+                uint64_t state:2;
+                uint64_t reserved_63_63:1;
+#endif
+        } s;
+};
+
+union cvmx_npi_px_instr_addr {
+        uint64_t u64;
+        struct cvmx_npi_px_instr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:3;
+                uint64_t naddr:61;
+#else
+                uint64_t naddr:61;
+                uint64_t state:3;
+#endif
+        } s;
+};
+
+union cvmx_npi_px_instr_cnts {
+        uint64_t u64;
+        struct cvmx_npi_px_instr_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t fcnt:6;
+                uint64_t avail:32;
+#else
+                uint64_t avail:32;
+                uint64_t fcnt:6;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+};
+
+union cvmx_npi_px_pair_cnts {
+        uint64_t u64;
+        struct cvmx_npi_px_pair_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t fcnt:5;
+                uint64_t avail:32;
+#else
+                uint64_t avail:32;
+                uint64_t fcnt:5;
+                uint64_t reserved_37_63:27;
+#endif
+        } s;
+};
+
+union cvmx_npi_pci_burst_size {
+        uint64_t u64;
+        struct cvmx_npi_pci_burst_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t wr_brst:7;
+                uint64_t rd_brst:7;
+#else
+                uint64_t rd_brst:7;
+                uint64_t wr_brst:7;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_npi_pci_int_arb_cfg {
+        uint64_t u64;
+        struct cvmx_npi_pci_int_arb_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t hostmode:1;
+                uint64_t pci_ovr:4;
+                uint64_t reserved_5_7:3;
+                uint64_t en:1;
+                uint64_t park_mod:1;
+                uint64_t park_dev:3;
+#else
+                uint64_t park_dev:3;
+                uint64_t park_mod:1;
+                uint64_t en:1;
+                uint64_t reserved_5_7:3;
+                uint64_t pci_ovr:4;
+                uint64_t hostmode:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_npi_pci_int_arb_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t en:1;
+                uint64_t park_mod:1;
+                uint64_t park_dev:3;
+#else
+                uint64_t park_dev:3;
+                uint64_t park_mod:1;
+                uint64_t en:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } cn30xx;
+};
+
+union cvmx_npi_pci_read_cmd {
+        uint64_t u64;
+        struct cvmx_npi_pci_read_cmd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t cmd_size:11;
+#else
+                uint64_t cmd_size:11;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+};
+
+union cvmx_npi_port32_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port32_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+#else
+                uint64_t rsv_a:6;
+                uint64_t skp_len:7;
+                uint64_t rsv_b:1;
+                uint64_t par_mode:2;
+                uint64_t rsv_c:5;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_d:6;
+                uint64_t rskp_len:7;
+                uint64_t rsv_e:1;
+                uint64_t rparmode:2;
+                uint64_t rsv_f:5;
+                uint64_t pbp:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npi_port33_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port33_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+#else
+                uint64_t rsv_a:6;
+                uint64_t skp_len:7;
+                uint64_t rsv_b:1;
+                uint64_t par_mode:2;
+                uint64_t rsv_c:5;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_d:6;
+                uint64_t rskp_len:7;
+                uint64_t rsv_e:1;
+                uint64_t rparmode:2;
+                uint64_t rsv_f:5;
+                uint64_t pbp:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npi_port34_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port34_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+#else
+                uint64_t rsv_a:6;
+                uint64_t skp_len:7;
+                uint64_t rsv_b:1;
+                uint64_t par_mode:2;
+                uint64_t rsv_c:5;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_d:6;
+                uint64_t rskp_len:7;
+                uint64_t rsv_e:1;
+                uint64_t rparmode:2;
+                uint64_t rsv_f:5;
+                uint64_t pbp:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npi_port35_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port35_instr_hdr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+#else
+                uint64_t rsv_a:6;
+                uint64_t skp_len:7;
+                uint64_t rsv_b:1;
+                uint64_t par_mode:2;
+                uint64_t rsv_c:5;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_d:6;
+                uint64_t rskp_len:7;
+                uint64_t rsv_e:1;
+                uint64_t rparmode:2;
+                uint64_t rsv_f:5;
+                uint64_t pbp:1;
+                uint64_t reserved_44_63:20;
+#endif
+        } s;
+};
+
+union cvmx_npi_port_bp_control {
+        uint64_t u64;
+        struct cvmx_npi_port_bp_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t bp_on:4;
+                uint64_t enb:4;
+#else
+                uint64_t enb:4;
+                uint64_t bp_on:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_npi_rsl_int_blocks {
+        uint64_t u64;
+        struct cvmx_npi_rsl_int_blocks_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t reserved_28_29:2;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t reserved_13_14:2;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+#else
+                uint64_t mio:1;
+                uint64_t gmx0:1;
+                uint64_t gmx1:1;
+                uint64_t npi:1;
+                uint64_t key:1;
+                uint64_t fpa:1;
+                uint64_t dfa:1;
+                uint64_t zip:1;
+                uint64_t rint_8:1;
+                uint64_t ipd:1;
+                uint64_t pko:1;
+                uint64_t tim:1;
+                uint64_t pow:1;
+                uint64_t reserved_13_14:2;
+                uint64_t rint_15:1;
+                uint64_t l2c:1;
+                uint64_t lmc:1;
+                uint64_t spx0:1;
+                uint64_t spx1:1;
+                uint64_t pip:1;
+                uint64_t rint_21:1;
+                uint64_t asx0:1;
+                uint64_t asx1:1;
+                uint64_t rint_24:1;
+                uint64_t rint_25:1;
+                uint64_t rint_26:1;
+                uint64_t rint_27:1;
+                uint64_t reserved_28_29:2;
+                uint64_t iob:1;
+                uint64_t rint_31:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_npi_rsl_int_blocks_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t rint_29:1;
+                uint64_t rint_28:1;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t rint_14:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+#else
+                uint64_t mio:1;
+                uint64_t gmx0:1;
+                uint64_t gmx1:1;
+                uint64_t npi:1;
+                uint64_t key:1;
+                uint64_t fpa:1;
+                uint64_t dfa:1;
+                uint64_t zip:1;
+                uint64_t rint_8:1;
+                uint64_t ipd:1;
+                uint64_t pko:1;
+                uint64_t tim:1;
+                uint64_t pow:1;
+                uint64_t usb:1;
+                uint64_t rint_14:1;
+                uint64_t rint_15:1;
+                uint64_t l2c:1;
+                uint64_t lmc:1;
+                uint64_t spx0:1;
+                uint64_t spx1:1;
+                uint64_t pip:1;
+                uint64_t rint_21:1;
+                uint64_t asx0:1;
+                uint64_t asx1:1;
+                uint64_t rint_24:1;
+                uint64_t rint_25:1;
+                uint64_t rint_26:1;
+                uint64_t rint_27:1;
+                uint64_t rint_28:1;
+                uint64_t rint_29:1;
+                uint64_t iob:1;
+                uint64_t rint_31:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn30xx;
+        struct cvmx_npi_rsl_int_blocks_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t rint_29:1;
+                uint64_t rint_28:1;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t rint_14:1;
+                uint64_t rint_13:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+#else
+                uint64_t mio:1;
+                uint64_t gmx0:1;
+                uint64_t gmx1:1;
+                uint64_t npi:1;
+                uint64_t key:1;
+                uint64_t fpa:1;
+                uint64_t dfa:1;
+                uint64_t zip:1;
+                uint64_t rint_8:1;
+                uint64_t ipd:1;
+                uint64_t pko:1;
+                uint64_t tim:1;
+                uint64_t pow:1;
+                uint64_t rint_13:1;
+                uint64_t rint_14:1;
+                uint64_t rint_15:1;
+                uint64_t l2c:1;
+                uint64_t lmc:1;
+                uint64_t spx0:1;
+                uint64_t spx1:1;
+                uint64_t pip:1;
+                uint64_t rint_21:1;
+                uint64_t asx0:1;
+                uint64_t asx1:1;
+                uint64_t rint_24:1;
+                uint64_t rint_25:1;
+                uint64_t rint_26:1;
+                uint64_t rint_27:1;
+                uint64_t rint_28:1;
+                uint64_t rint_29:1;
+                uint64_t iob:1;
+                uint64_t rint_31:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_npi_rsl_int_blocks_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t iob:1;
+                uint64_t lmc1:1;
+                uint64_t agl:1;
+                uint64_t reserved_24_27:4;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t reserved_15_15:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+#else
+                uint64_t mio:1;
+                uint64_t gmx0:1;
+                uint64_t gmx1:1;
+                uint64_t npi:1;
+                uint64_t key:1;
+                uint64_t fpa:1;
+                uint64_t dfa:1;
+                uint64_t zip:1;
+                uint64_t reserved_8_8:1;
+                uint64_t ipd:1;
+                uint64_t pko:1;
+                uint64_t tim:1;
+                uint64_t pow:1;
+                uint64_t usb:1;
+                uint64_t rad:1;
+                uint64_t reserved_15_15:1;
+                uint64_t l2c:1;
+                uint64_t lmc:1;
+                uint64_t spx0:1;
+                uint64_t spx1:1;
+                uint64_t pip:1;
+                uint64_t reserved_21_21:1;
+                uint64_t asx0:1;
+                uint64_t asx1:1;
+                uint64_t reserved_24_27:4;
+                uint64_t agl:1;
+                uint64_t lmc1:1;
+                uint64_t iob:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } cn50xx;
+};
+
+union cvmx_npi_size_inputx {
+        uint64_t u64;
+        struct cvmx_npi_size_inputx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t size:32;
+#else
+                uint64_t size:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_npi_win_read_to {
+        uint64_t u64;
+        struct cvmx_npi_win_read_to_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+#else
+                uint64_t time:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
new file mode 100644
index 000000000..895e93d68
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -0,0 +1,69 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Packet buffer defines.
+ */
+
+#ifndef __CVMX_PACKET_H__
+#define __CVMX_PACKET_H__
+
+/**
+ * This structure defines a buffer pointer on Octeon
+ */
+union cvmx_buf_ptr {
+        void *ptr;
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* if set, invert the "free" pick of the overall
+                 * packet. HW always sets this bit to 0 on inbound
+                 * packet */
+                uint64_t i:1;
+
+                /* Indicates the amount to back up to get to the
+                 * buffer start in cache lines. In most cases this is
+                 * less than one complete cache line, so the value is
+                 * zero */
+                uint64_t back:4;
+                /* The pool that the buffer came from / goes to */
+                uint64_t pool:3;
+                /* The size of the segment pointed to by addr (in bytes) */
+                uint64_t size:16;
+                /* Pointer to the first byte of the data, NOT buffer */
+                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } s;
+};
+
+#endif /*  __CVMX_PACKET_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
new file mode 100644
index 000000000..be56b693b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -0,0 +1,2037 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCI_DEFS_H__
+#define __CVMX_PCI_DEFS_H__
+
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
+
+union cvmx_pci_bar1_indexx {
+        uint32_t u32;
+        struct cvmx_pci_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_18_31:14;
+                uint32_t addr_idx:14;
+                uint32_t ca:1;
+                uint32_t end_swp:2;
+                uint32_t addr_v:1;
+#else
+                uint32_t addr_v:1;
+                uint32_t end_swp:2;
+                uint32_t ca:1;
+                uint32_t addr_idx:14;
+                uint32_t reserved_18_31:14;
+#endif
+        } s;
+};
+
+union cvmx_pci_bist_reg {
+        uint64_t u64;
+        struct cvmx_pci_bist_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t rsp_bs:1;
+                uint64_t dma0_bs:1;
+                uint64_t cmd0_bs:1;
+                uint64_t cmd_bs:1;
+                uint64_t csr2p_bs:1;
+                uint64_t csrr_bs:1;
+                uint64_t rsp2p_bs:1;
+                uint64_t csr2n_bs:1;
+                uint64_t dat2n_bs:1;
+                uint64_t dbg2n_bs:1;
+#else
+                uint64_t dbg2n_bs:1;
+                uint64_t dat2n_bs:1;
+                uint64_t csr2n_bs:1;
+                uint64_t rsp2p_bs:1;
+                uint64_t csrr_bs:1;
+                uint64_t csr2p_bs:1;
+                uint64_t cmd_bs:1;
+                uint64_t cmd0_bs:1;
+                uint64_t dma0_bs:1;
+                uint64_t rsp_bs:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg00 {
+        uint32_t u32;
+        struct cvmx_pci_cfg00_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t devid:16;
+                uint32_t vendid:16;
+#else
+                uint32_t vendid:16;
+                uint32_t devid:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg01 {
+        uint32_t u32;
+        struct cvmx_pci_cfg01_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t cle:1;
+                uint32_t i_stat:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_dis:1;
+                uint32_t fbbe:1;
+                uint32_t see:1;
+                uint32_t ads:1;
+                uint32_t pee:1;
+                uint32_t vps:1;
+                uint32_t mwice:1;
+                uint32_t scse:1;
+                uint32_t me:1;
+                uint32_t msae:1;
+                uint32_t isae:1;
+#else
+                uint32_t isae:1;
+                uint32_t msae:1;
+                uint32_t me:1;
+                uint32_t scse:1;
+                uint32_t mwice:1;
+                uint32_t vps:1;
+                uint32_t pee:1;
+                uint32_t ads:1;
+                uint32_t see:1;
+                uint32_t fbbe:1;
+                uint32_t i_dis:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_stat:1;
+                uint32_t cle:1;
+                uint32_t m66:1;
+                uint32_t reserved_22_22:1;
+                uint32_t fbb:1;
+                uint32_t mdpe:1;
+                uint32_t devt:2;
+                uint32_t sta:1;
+                uint32_t rta:1;
+                uint32_t rma:1;
+                uint32_t sse:1;
+                uint32_t dpe:1;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg02 {
+        uint32_t u32;
+        struct cvmx_pci_cfg02_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t cc:24;
+                uint32_t rid:8;
+#else
+                uint32_t rid:8;
+                uint32_t cc:24;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg03 {
+        uint32_t u32;
+        struct cvmx_pci_cfg03_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t bcap:1;
+                uint32_t brb:1;
+                uint32_t reserved_28_29:2;
+                uint32_t bcod:4;
+                uint32_t ht:8;
+                uint32_t lt:8;
+                uint32_t cls:8;
+#else
+                uint32_t cls:8;
+                uint32_t lt:8;
+                uint32_t ht:8;
+                uint32_t bcod:4;
+                uint32_t reserved_28_29:2;
+                uint32_t brb:1;
+                uint32_t bcap:1;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg04 {
+        uint32_t u32;
+        struct cvmx_pci_cfg04_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t lbase:20;
+                uint32_t lbasez:8;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+#else
+                uint32_t mspc:1;
+                uint32_t typ:2;
+                uint32_t pf:1;
+                uint32_t lbasez:8;
+                uint32_t lbase:20;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg05 {
+        uint32_t u32;
+        struct cvmx_pci_cfg05_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t hbase:32;
+#else
+                uint32_t hbase:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg06 {
+        uint32_t u32;
+        struct cvmx_pci_cfg06_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t lbase:5;
+                uint32_t lbasez:23;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+#else
+                uint32_t mspc:1;
+                uint32_t typ:2;
+                uint32_t pf:1;
+                uint32_t lbasez:23;
+                uint32_t lbase:5;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg07 {
+        uint32_t u32;
+        struct cvmx_pci_cfg07_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t hbase:32;
+#else
+                uint32_t hbase:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg08 {
+        uint32_t u32;
+        struct cvmx_pci_cfg08_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t lbasez:28;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+#else
+                uint32_t mspc:1;
+                uint32_t typ:2;
+                uint32_t pf:1;
+                uint32_t lbasez:28;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg09 {
+        uint32_t u32;
+        struct cvmx_pci_cfg09_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t hbase:25;
+                uint32_t hbasez:7;
+#else
+                uint32_t hbasez:7;
+                uint32_t hbase:25;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg10 {
+        uint32_t u32;
+        struct cvmx_pci_cfg10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t cisp:32;
+#else
+                uint32_t cisp:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg11 {
+        uint32_t u32;
+        struct cvmx_pci_cfg11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t ssid:16;
+                uint32_t ssvid:16;
+#else
+                uint32_t ssvid:16;
+                uint32_t ssid:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg12 {
+        uint32_t u32;
+        struct cvmx_pci_cfg12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t erbar:16;
+                uint32_t erbarz:5;
+                uint32_t reserved_1_10:10;
+                uint32_t erbar_en:1;
+#else
+                uint32_t erbar_en:1;
+                uint32_t reserved_1_10:10;
+                uint32_t erbarz:5;
+                uint32_t erbar:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg13 {
+        uint32_t u32;
+        struct cvmx_pci_cfg13_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_8_31:24;
+                uint32_t cp:8;
+#else
+                uint32_t cp:8;
+                uint32_t reserved_8_31:24;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg15 {
+        uint32_t u32;
+        struct cvmx_pci_cfg15_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t ml:8;
+                uint32_t mg:8;
+                uint32_t inta:8;
+                uint32_t il:8;
+#else
+                uint32_t il:8;
+                uint32_t inta:8;
+                uint32_t mg:8;
+                uint32_t ml:8;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg16 {
+        uint32_t u32;
+        struct cvmx_pci_cfg16_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t trdnpr:1;
+                uint32_t trdard:1;
+                uint32_t rdsati:1;
+                uint32_t trdrs:1;
+                uint32_t trtae:1;
+                uint32_t twsei:1;
+                uint32_t twsen:1;
+                uint32_t twtae:1;
+                uint32_t tmae:1;
+                uint32_t tslte:3;
+                uint32_t tilt:4;
+                uint32_t pbe:12;
+                uint32_t dppmr:1;
+                uint32_t reserved_2_2:1;
+                uint32_t tswc:1;
+                uint32_t mltd:1;
+#else
+                uint32_t mltd:1;
+                uint32_t tswc:1;
+                uint32_t reserved_2_2:1;
+                uint32_t dppmr:1;
+                uint32_t pbe:12;
+                uint32_t tilt:4;
+                uint32_t tslte:3;
+                uint32_t tmae:1;
+                uint32_t twtae:1;
+                uint32_t twsen:1;
+                uint32_t twsei:1;
+                uint32_t trtae:1;
+                uint32_t trdrs:1;
+                uint32_t rdsati:1;
+                uint32_t trdard:1;
+                uint32_t trdnpr:1;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg17 {
+        uint32_t u32;
+        struct cvmx_pci_cfg17_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t tscme:32;
+#else
+                uint32_t tscme:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg18 {
+        uint32_t u32;
+        struct cvmx_pci_cfg18_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t tdsrps:32;
+#else
+                uint32_t tdsrps:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg19 {
+        uint32_t u32;
+        struct cvmx_pci_cfg19_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t mrbcm:1;
+                uint32_t mrbci:1;
+                uint32_t mdwe:1;
+                uint32_t mdre:1;
+                uint32_t mdrimc:1;
+                uint32_t mdrrmc:3;
+                uint32_t tmes:8;
+                uint32_t teci:1;
+                uint32_t tmei:1;
+                uint32_t tmse:1;
+                uint32_t tmdpes:1;
+                uint32_t tmapes:1;
+                uint32_t reserved_9_10:2;
+                uint32_t tibcd:1;
+                uint32_t tibde:1;
+                uint32_t reserved_6_6:1;
+                uint32_t tidomc:1;
+                uint32_t tdomc:5;
+#else
+                uint32_t tdomc:5;
+                uint32_t tidomc:1;
+                uint32_t reserved_6_6:1;
+                uint32_t tibde:1;
+                uint32_t tibcd:1;
+                uint32_t reserved_9_10:2;
+                uint32_t tmapes:1;
+                uint32_t tmdpes:1;
+                uint32_t tmse:1;
+                uint32_t tmei:1;
+                uint32_t teci:1;
+                uint32_t tmes:8;
+                uint32_t mdrrmc:3;
+                uint32_t mdrimc:1;
+                uint32_t mdre:1;
+                uint32_t mdwe:1;
+                uint32_t mrbci:1;
+                uint32_t mrbcm:1;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg20 {
+        uint32_t u32;
+        struct cvmx_pci_cfg20_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t mdsp:32;
+#else
+                uint32_t mdsp:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg21 {
+        uint32_t u32;
+        struct cvmx_pci_cfg21_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t scmre:32;
+#else
+                uint32_t scmre:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg22 {
+        uint32_t u32;
+        struct cvmx_pci_cfg22_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t mac:7;
+                uint32_t reserved_19_24:6;
+                uint32_t flush:1;
+                uint32_t mra:1;
+                uint32_t mtta:1;
+                uint32_t mrv:8;
+                uint32_t mttv:8;
+#else
+                uint32_t mttv:8;
+                uint32_t mrv:8;
+                uint32_t mtta:1;
+                uint32_t mra:1;
+                uint32_t flush:1;
+                uint32_t reserved_19_24:6;
+                uint32_t mac:7;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg56 {
+        uint32_t u32;
+        struct cvmx_pci_cfg56_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_23_31:9;
+                uint32_t most:3;
+                uint32_t mmbc:2;
+                uint32_t roe:1;
+                uint32_t dpere:1;
+                uint32_t ncp:8;
+                uint32_t pxcid:8;
+#else
+                uint32_t pxcid:8;
+                uint32_t ncp:8;
+                uint32_t dpere:1;
+                uint32_t roe:1;
+                uint32_t mmbc:2;
+                uint32_t most:3;
+                uint32_t reserved_23_31:9;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg57 {
+        uint32_t u32;
+        struct cvmx_pci_cfg57_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_30_31:2;
+                uint32_t scemr:1;
+                uint32_t mcrsd:3;
+                uint32_t mostd:3;
+                uint32_t mmrbcd:2;
+                uint32_t dc:1;
+                uint32_t usc:1;
+                uint32_t scd:1;
+                uint32_t m133:1;
+                uint32_t w64:1;
+                uint32_t bn:8;
+                uint32_t dn:5;
+                uint32_t fn:3;
+#else
+                uint32_t fn:3;
+                uint32_t dn:5;
+                uint32_t bn:8;
+                uint32_t w64:1;
+                uint32_t m133:1;
+                uint32_t scd:1;
+                uint32_t usc:1;
+                uint32_t dc:1;
+                uint32_t mmrbcd:2;
+                uint32_t mostd:3;
+                uint32_t mcrsd:3;
+                uint32_t scemr:1;
+                uint32_t reserved_30_31:2;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg58 {
+        uint32_t u32;
+        struct cvmx_pci_cfg58_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pmes:5;
+                uint32_t d2s:1;
+                uint32_t d1s:1;
+                uint32_t auxc:3;
+                uint32_t dsi:1;
+                uint32_t reserved_20_20:1;
+                uint32_t pmec:1;
+                uint32_t pcimiv:3;
+                uint32_t ncp:8;
+                uint32_t pmcid:8;
+#else
+                uint32_t pmcid:8;
+                uint32_t ncp:8;
+                uint32_t pcimiv:3;
+                uint32_t pmec:1;
+                uint32_t reserved_20_20:1;
+                uint32_t dsi:1;
+                uint32_t auxc:3;
+                uint32_t d1s:1;
+                uint32_t d2s:1;
+                uint32_t pmes:5;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg59 {
+        uint32_t u32;
+        struct cvmx_pci_cfg59_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pmdia:8;
+                uint32_t bpccen:1;
+                uint32_t bd3h:1;
+                uint32_t reserved_16_21:6;
+                uint32_t pmess:1;
+                uint32_t pmedsia:2;
+                uint32_t pmds:4;
+                uint32_t pmeens:1;
+                uint32_t reserved_2_7:6;
+                uint32_t ps:2;
+#else
+                uint32_t ps:2;
+                uint32_t reserved_2_7:6;
+                uint32_t pmeens:1;
+                uint32_t pmds:4;
+                uint32_t pmedsia:2;
+                uint32_t pmess:1;
+                uint32_t reserved_16_21:6;
+                uint32_t bd3h:1;
+                uint32_t bpccen:1;
+                uint32_t pmdia:8;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg60 {
+        uint32_t u32;
+        struct cvmx_pci_cfg60_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+#else
+                uint32_t msicid:8;
+                uint32_t ncp:8;
+                uint32_t msien:1;
+                uint32_t mmc:3;
+                uint32_t mme:3;
+                uint32_t m64:1;
+                uint32_t reserved_24_31:8;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg61 {
+        uint32_t u32;
+        struct cvmx_pci_cfg61_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t msi31t2:30;
+                uint32_t reserved_0_1:2;
+#else
+                uint32_t reserved_0_1:2;
+                uint32_t msi31t2:30;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg62 {
+        uint32_t u32;
+        struct cvmx_pci_cfg62_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t msi:32;
+#else
+                uint32_t msi:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_cfg63 {
+        uint32_t u32;
+        struct cvmx_pci_cfg63_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_16_31:16;
+                uint32_t msimd:16;
+#else
+                uint32_t msimd:16;
+                uint32_t reserved_16_31:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_cnt_reg {
+        uint64_t u64;
+        struct cvmx_pci_cnt_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t hm_pcix:1;
+                uint64_t hm_speed:2;
+                uint64_t ap_pcix:1;
+                uint64_t ap_speed:2;
+                uint64_t pcicnt:32;
+#else
+                uint64_t pcicnt:32;
+                uint64_t ap_speed:2;
+                uint64_t ap_pcix:1;
+                uint64_t hm_speed:2;
+                uint64_t hm_pcix:1;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+};
+
+union cvmx_pci_ctl_status_2 {
+        uint32_t u32;
+        struct cvmx_pci_ctl_status_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_29_31:3;
+                uint32_t bb1_hole:3;
+                uint32_t bb1_siz:1;
+                uint32_t bb_ca:1;
+                uint32_t bb_es:2;
+                uint32_t bb1:1;
+                uint32_t bb0:1;
+                uint32_t erst_n:1;
+                uint32_t bar2pres:1;
+                uint32_t scmtyp:1;
+                uint32_t scm:1;
+                uint32_t en_wfilt:1;
+                uint32_t reserved_14_14:1;
+                uint32_t ap_pcix:1;
+                uint32_t ap_64ad:1;
+                uint32_t b12_bist:1;
+                uint32_t pmo_amod:1;
+                uint32_t pmo_fpc:3;
+                uint32_t tsr_hwm:3;
+                uint32_t bar2_enb:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_cax:1;
+#else
+                uint32_t bar2_cax:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_enb:1;
+                uint32_t tsr_hwm:3;
+                uint32_t pmo_fpc:3;
+                uint32_t pmo_amod:1;
+                uint32_t b12_bist:1;
+                uint32_t ap_64ad:1;
+                uint32_t ap_pcix:1;
+                uint32_t reserved_14_14:1;
+                uint32_t en_wfilt:1;
+                uint32_t scm:1;
+                uint32_t scmtyp:1;
+                uint32_t bar2pres:1;
+                uint32_t erst_n:1;
+                uint32_t bb0:1;
+                uint32_t bb1:1;
+                uint32_t bb_es:2;
+                uint32_t bb_ca:1;
+                uint32_t bb1_siz:1;
+                uint32_t bb1_hole:3;
+                uint32_t reserved_29_31:3;
+#endif
+        } s;
+        struct cvmx_pci_ctl_status_2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_20_31:12;
+                uint32_t erst_n:1;
+                uint32_t bar2pres:1;
+                uint32_t scmtyp:1;
+                uint32_t scm:1;
+                uint32_t en_wfilt:1;
+                uint32_t reserved_14_14:1;
+                uint32_t ap_pcix:1;
+                uint32_t ap_64ad:1;
+                uint32_t b12_bist:1;
+                uint32_t pmo_amod:1;
+                uint32_t pmo_fpc:3;
+                uint32_t tsr_hwm:3;
+                uint32_t bar2_enb:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_cax:1;
+#else
+                uint32_t bar2_cax:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_enb:1;
+                uint32_t tsr_hwm:3;
+                uint32_t pmo_fpc:3;
+                uint32_t pmo_amod:1;
+                uint32_t b12_bist:1;
+                uint32_t ap_64ad:1;
+                uint32_t ap_pcix:1;
+                uint32_t reserved_14_14:1;
+                uint32_t en_wfilt:1;
+                uint32_t scm:1;
+                uint32_t scmtyp:1;
+                uint32_t bar2pres:1;
+                uint32_t erst_n:1;
+                uint32_t reserved_20_31:12;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pci_dbellx {
+        uint32_t u32;
+        struct cvmx_pci_dbellx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_16_31:16;
+                uint32_t inc_val:16;
+#else
+                uint32_t inc_val:16;
+                uint32_t reserved_16_31:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_dma_cntx {
+        uint32_t u32;
+        struct cvmx_pci_dma_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t dma_cnt:32;
+#else
+                uint32_t dma_cnt:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_dma_int_levx {
+        uint32_t u32;
+        struct cvmx_pci_dma_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pkt_cnt:32;
+#else
+                uint32_t pkt_cnt:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_dma_timex {
+        uint32_t u32;
+        struct cvmx_pci_dma_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t dma_time:32;
+#else
+                uint32_t dma_time:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_instr_countx {
+        uint32_t u32;
+        struct cvmx_pci_instr_countx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t icnt:32;
+#else
+                uint32_t icnt:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_int_enb {
+        uint64_t u64;
+        struct cvmx_pci_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t iptime3:1;
+                uint64_t iptime2:1;
+                uint64_t iptime1:1;
+                uint64_t iptime0:1;
+                uint64_t ipcnt3:1;
+                uint64_t ipcnt2:1;
+                uint64_t ipcnt1:1;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+#else
+                uint64_t itr_wabt:1;
+                uint64_t imr_wabt:1;
+                uint64_t imr_wtto:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_abt:1;
+                uint64_t imr_tto:1;
+                uint64_t imsi_per:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsc_msg:1;
+                uint64_t itsr_abt:1;
+                uint64_t iserr:1;
+                uint64_t iaperr:1;
+                uint64_t idperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t irsl_int:1;
+                uint64_t ipcnt0:1;
+                uint64_t ipcnt1:1;
+                uint64_t ipcnt2:1;
+                uint64_t ipcnt3:1;
+                uint64_t iptime0:1;
+                uint64_t iptime1:1;
+                uint64_t iptime2:1;
+                uint64_t iptime3:1;
+                uint64_t idcnt0:1;
+                uint64_t idcnt1:1;
+                uint64_t idtime0:1;
+                uint64_t idtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+        struct cvmx_pci_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t iptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+#else
+                uint64_t itr_wabt:1;
+                uint64_t imr_wabt:1;
+                uint64_t imr_wtto:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_abt:1;
+                uint64_t imr_tto:1;
+                uint64_t imsi_per:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsc_msg:1;
+                uint64_t itsr_abt:1;
+                uint64_t iserr:1;
+                uint64_t iaperr:1;
+                uint64_t idperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t irsl_int:1;
+                uint64_t ipcnt0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t iptime0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t idcnt0:1;
+                uint64_t idcnt1:1;
+                uint64_t idtime0:1;
+                uint64_t idtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn30xx;
+        struct cvmx_pci_int_enb_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t iptime1:1;
+                uint64_t iptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t ipcnt1:1;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+#else
+                uint64_t itr_wabt:1;
+                uint64_t imr_wabt:1;
+                uint64_t imr_wtto:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_abt:1;
+                uint64_t imr_tto:1;
+                uint64_t imsi_per:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsc_msg:1;
+                uint64_t itsr_abt:1;
+                uint64_t iserr:1;
+                uint64_t iaperr:1;
+                uint64_t idperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t irsl_int:1;
+                uint64_t ipcnt0:1;
+                uint64_t ipcnt1:1;
+                uint64_t reserved_19_20:2;
+                uint64_t iptime0:1;
+                uint64_t iptime1:1;
+                uint64_t reserved_23_24:2;
+                uint64_t idcnt0:1;
+                uint64_t idcnt1:1;
+                uint64_t idtime0:1;
+                uint64_t idtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pci_int_enb2 {
+        uint64_t u64;
+        struct cvmx_pci_int_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t rptime3:1;
+                uint64_t rptime2:1;
+                uint64_t rptime1:1;
+                uint64_t rptime0:1;
+                uint64_t rpcnt3:1;
+                uint64_t rpcnt2:1;
+                uint64_t rpcnt1:1;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+#else
+                uint64_t rtr_wabt:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_abt:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rserr:1;
+                uint64_t raperr:1;
+                uint64_t rdperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rrsl_int:1;
+                uint64_t rpcnt0:1;
+                uint64_t rpcnt1:1;
+                uint64_t rpcnt2:1;
+                uint64_t rpcnt3:1;
+                uint64_t rptime0:1;
+                uint64_t rptime1:1;
+                uint64_t rptime2:1;
+                uint64_t rptime3:1;
+                uint64_t rdcnt0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+        struct cvmx_pci_int_enb2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t rptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+#else
+                uint64_t rtr_wabt:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_abt:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rserr:1;
+                uint64_t raperr:1;
+                uint64_t rdperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rrsl_int:1;
+                uint64_t rpcnt0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t rptime0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t rdcnt0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn30xx;
+        struct cvmx_pci_int_enb2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t rptime1:1;
+                uint64_t rptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t rpcnt1:1;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+#else
+                uint64_t rtr_wabt:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_abt:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rserr:1;
+                uint64_t raperr:1;
+                uint64_t rdperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rrsl_int:1;
+                uint64_t rpcnt0:1;
+                uint64_t rpcnt1:1;
+                uint64_t reserved_19_20:2;
+                uint64_t rptime0:1;
+                uint64_t rptime1:1;
+                uint64_t reserved_23_24:2;
+                uint64_t rdcnt0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pci_int_sum {
+        uint64_t u64;
+        struct cvmx_pci_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t ptime3:1;
+                uint64_t ptime2:1;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t pcnt3:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt3:1;
+                uint64_t ptime0:1;
+                uint64_t ptime1:1;
+                uint64_t ptime2:1;
+                uint64_t ptime3:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+        struct cvmx_pci_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn30xx;
+        struct cvmx_pci_int_sum_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t pcnt1:1;
+                uint64_t reserved_19_20:2;
+                uint64_t ptime0:1;
+                uint64_t ptime1:1;
+                uint64_t reserved_23_24:2;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pci_int_sum2 {
+        uint64_t u64;
+        struct cvmx_pci_int_sum2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t ptime3:1;
+                uint64_t ptime2:1;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t pcnt3:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt3:1;
+                uint64_t ptime0:1;
+                uint64_t ptime1:1;
+                uint64_t ptime2:1;
+                uint64_t ptime3:1;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } s;
+        struct cvmx_pci_int_sum2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn30xx;
+        struct cvmx_pci_int_sum2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+#else
+                uint64_t tr_wabt:1;
+                uint64_t mr_wabt:1;
+                uint64_t mr_wtto:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_abt:1;
+                uint64_t mr_tto:1;
+                uint64_t msi_per:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_mabt:1;
+                uint64_t msc_msg:1;
+                uint64_t tsr_abt:1;
+                uint64_t serr:1;
+                uint64_t aperr:1;
+                uint64_t dperr:1;
+                uint64_t ill_rwr:1;
+                uint64_t ill_rrd:1;
+                uint64_t rsl_int:1;
+                uint64_t pcnt0:1;
+                uint64_t pcnt1:1;
+                uint64_t reserved_19_20:2;
+                uint64_t ptime0:1;
+                uint64_t ptime1:1;
+                uint64_t reserved_23_24:2;
+                uint64_t dcnt0:1;
+                uint64_t dcnt1:1;
+                uint64_t dtime0:1;
+                uint64_t dtime1:1;
+                uint64_t dma0_fi:1;
+                uint64_t dma1_fi:1;
+                uint64_t win_wr:1;
+                uint64_t ill_wr:1;
+                uint64_t ill_rd:1;
+                uint64_t reserved_34_63:30;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pci_msi_rcv {
+        uint32_t u32;
+        struct cvmx_pci_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_6_31:26;
+                uint32_t intr:6;
+#else
+                uint32_t intr:6;
+                uint32_t reserved_6_31:26;
+#endif
+        } s;
+};
+
+union cvmx_pci_pkt_creditsx {
+        uint32_t u32;
+        struct cvmx_pci_pkt_creditsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pkt_cnt:16;
+                uint32_t ptr_cnt:16;
+#else
+                uint32_t ptr_cnt:16;
+                uint32_t pkt_cnt:16;
+#endif
+        } s;
+};
+
+union cvmx_pci_pkts_sentx {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sentx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pkt_cnt:32;
+#else
+                uint32_t pkt_cnt:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_pkts_sent_int_levx {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sent_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pkt_cnt:32;
+#else
+                uint32_t pkt_cnt:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_pkts_sent_timex {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sent_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t pkt_time:32;
+#else
+                uint32_t pkt_time:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_read_cmd_6 {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+#else
+                uint32_t prefetch:3;
+                uint32_t min_data:6;
+                uint32_t reserved_9_31:23;
+#endif
+        } s;
+};
+
+union cvmx_pci_read_cmd_c {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+#else
+                uint32_t prefetch:3;
+                uint32_t min_data:6;
+                uint32_t reserved_9_31:23;
+#endif
+        } s;
+};
+
+union cvmx_pci_read_cmd_e {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_e_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+#else
+                uint32_t prefetch:3;
+                uint32_t min_data:6;
+                uint32_t reserved_9_31:23;
+#endif
+        } s;
+};
+
+union cvmx_pci_read_timeout {
+        uint64_t u64;
+        struct cvmx_pci_read_timeout_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enb:1;
+                uint64_t cnt:31;
+#else
+                uint64_t cnt:31;
+                uint64_t enb:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_scm_reg {
+        uint64_t u64;
+        struct cvmx_pci_scm_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t scm:32;
+#else
+                uint64_t scm:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pci_tsr_reg {
+        uint64_t u64;
+        struct cvmx_pci_tsr_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t tsr:36;
+#else
+                uint64_t tsr:36;
+                uint64_t reserved_36_63:28;
+#endif
+        } s;
+};
+
+union cvmx_pci_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_pci_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t reserved_0_47:48;
+#else
+                uint64_t reserved_0_47:48;
+                uint64_t iobit:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+        struct cvmx_pci_win_rd_addr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t rd_addr:46;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t rd_addr:46;
+                uint64_t iobit:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } cn30xx;
+        struct cvmx_pci_win_rd_addr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t rd_addr:45;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t rd_addr:45;
+                uint64_t iobit:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } cn38xx;
+};
+
+union cvmx_pci_win_rd_data {
+        uint64_t u64;
+        struct cvmx_pci_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rd_data:64;
+#else
+                uint64_t rd_data:64;
+#endif
+        } s;
+};
+
+union cvmx_pci_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:45;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t wr_addr:45;
+                uint64_t iobit:1;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+};
+
+union cvmx_pci_win_wr_data {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wr_data:64;
+#else
+                uint64_t wr_data:64;
+#endif
+        } s;
+};
+
+union cvmx_pci_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+#else
+                uint64_t wr_mask:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
new file mode 100644
index 000000000..e2dce1acf
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -0,0 +1,368 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCIERCX_DEFS_H__
+#define __CVMX_PCIERCX_DEFS_H__
+
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+
+union cvmx_pciercx_cfg001 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg001_s {
+                __BITFIELD_FIELD(uint32_t dpe:1,
+                __BITFIELD_FIELD(uint32_t sse:1,
+                __BITFIELD_FIELD(uint32_t rma:1,
+                __BITFIELD_FIELD(uint32_t rta:1,
+                __BITFIELD_FIELD(uint32_t sta:1,
+                __BITFIELD_FIELD(uint32_t devt:2,
+                __BITFIELD_FIELD(uint32_t mdpe:1,
+                __BITFIELD_FIELD(uint32_t fbb:1,
+                __BITFIELD_FIELD(uint32_t reserved_22_22:1,
+                __BITFIELD_FIELD(uint32_t m66:1,
+                __BITFIELD_FIELD(uint32_t cl:1,
+                __BITFIELD_FIELD(uint32_t i_stat:1,
+                __BITFIELD_FIELD(uint32_t reserved_11_18:8,
+                __BITFIELD_FIELD(uint32_t i_dis:1,
+                __BITFIELD_FIELD(uint32_t fbbe:1,
+                __BITFIELD_FIELD(uint32_t see:1,
+                __BITFIELD_FIELD(uint32_t ids_wcc:1,
+                __BITFIELD_FIELD(uint32_t per:1,
+                __BITFIELD_FIELD(uint32_t vps:1,
+                __BITFIELD_FIELD(uint32_t mwice:1,
+                __BITFIELD_FIELD(uint32_t scse:1,
+                __BITFIELD_FIELD(uint32_t me:1,
+                __BITFIELD_FIELD(uint32_t msae:1,
+                __BITFIELD_FIELD(uint32_t isae:1,
+                ;))))))))))))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg006 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg006_s {
+                __BITFIELD_FIELD(uint32_t slt:8,
+                __BITFIELD_FIELD(uint32_t subbnum:8,
+                __BITFIELD_FIELD(uint32_t sbnum:8,
+                __BITFIELD_FIELD(uint32_t pbnum:8,
+                ;))))
+        } s;
+};
+
+union cvmx_pciercx_cfg008 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg008_s {
+                __BITFIELD_FIELD(uint32_t ml_addr:12,
+                __BITFIELD_FIELD(uint32_t reserved_16_19:4,
+                __BITFIELD_FIELD(uint32_t mb_addr:12,
+                __BITFIELD_FIELD(uint32_t reserved_0_3:4,
+                ;))))
+        } s;
+};
+
+union cvmx_pciercx_cfg009 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg009_s {
+                __BITFIELD_FIELD(uint32_t lmem_limit:12,
+                __BITFIELD_FIELD(uint32_t reserved_17_19:3,
+                __BITFIELD_FIELD(uint32_t mem64b:1,
+                __BITFIELD_FIELD(uint32_t lmem_base:12,
+                __BITFIELD_FIELD(uint32_t reserved_1_3:3,
+                __BITFIELD_FIELD(uint32_t mem64a:1,
+                ;))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg010 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg010_s {
+                uint32_t umem_base;
+        } s;
+};
+
+union cvmx_pciercx_cfg011 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg011_s {
+                uint32_t umem_limit;
+        } s;
+};
+
+union cvmx_pciercx_cfg030 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg030_s {
+                __BITFIELD_FIELD(uint32_t reserved_22_31:10,
+                __BITFIELD_FIELD(uint32_t tp:1,
+                __BITFIELD_FIELD(uint32_t ap_d:1,
+                __BITFIELD_FIELD(uint32_t ur_d:1,
+                __BITFIELD_FIELD(uint32_t fe_d:1,
+                __BITFIELD_FIELD(uint32_t nfe_d:1,
+                __BITFIELD_FIELD(uint32_t ce_d:1,
+                __BITFIELD_FIELD(uint32_t reserved_15_15:1,
+                __BITFIELD_FIELD(uint32_t mrrs:3,
+                __BITFIELD_FIELD(uint32_t ns_en:1,
+                __BITFIELD_FIELD(uint32_t ap_en:1,
+                __BITFIELD_FIELD(uint32_t pf_en:1,
+                __BITFIELD_FIELD(uint32_t etf_en:1,
+                __BITFIELD_FIELD(uint32_t mps:3,
+                __BITFIELD_FIELD(uint32_t ro_en:1,
+                __BITFIELD_FIELD(uint32_t ur_en:1,
+                __BITFIELD_FIELD(uint32_t fe_en:1,
+                __BITFIELD_FIELD(uint32_t nfe_en:1,
+                __BITFIELD_FIELD(uint32_t ce_en:1,
+                ;)))))))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg031 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg031_s {
+                __BITFIELD_FIELD(uint32_t pnum:8,
+                __BITFIELD_FIELD(uint32_t reserved_23_23:1,
+                __BITFIELD_FIELD(uint32_t aspm:1,
+                __BITFIELD_FIELD(uint32_t lbnc:1,
+                __BITFIELD_FIELD(uint32_t dllarc:1,
+                __BITFIELD_FIELD(uint32_t sderc:1,
+                __BITFIELD_FIELD(uint32_t cpm:1,
+                __BITFIELD_FIELD(uint32_t l1el:3,
+                __BITFIELD_FIELD(uint32_t l0el:3,
+                __BITFIELD_FIELD(uint32_t aslpms:2,
+                __BITFIELD_FIELD(uint32_t mlw:6,
+                __BITFIELD_FIELD(uint32_t mls:4,
+                ;))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg032 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg032_s {
+                __BITFIELD_FIELD(uint32_t lab:1,
+                __BITFIELD_FIELD(uint32_t lbm:1,
+                __BITFIELD_FIELD(uint32_t dlla:1,
+                __BITFIELD_FIELD(uint32_t scc:1,
+                __BITFIELD_FIELD(uint32_t lt:1,
+                __BITFIELD_FIELD(uint32_t reserved_26_26:1,
+                __BITFIELD_FIELD(uint32_t nlw:6,
+                __BITFIELD_FIELD(uint32_t ls:4,
+                __BITFIELD_FIELD(uint32_t reserved_12_15:4,
+                __BITFIELD_FIELD(uint32_t lab_int_enb:1,
+                __BITFIELD_FIELD(uint32_t lbm_int_enb:1,
+                __BITFIELD_FIELD(uint32_t hawd:1,
+                __BITFIELD_FIELD(uint32_t ecpm:1,
+                __BITFIELD_FIELD(uint32_t es:1,
+                __BITFIELD_FIELD(uint32_t ccc:1,
+                __BITFIELD_FIELD(uint32_t rl:1,
+                __BITFIELD_FIELD(uint32_t ld:1,
+                __BITFIELD_FIELD(uint32_t rcb:1,
+                __BITFIELD_FIELD(uint32_t reserved_2_2:1,
+                __BITFIELD_FIELD(uint32_t aslpc:2,
+                ;))))))))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg034 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg034_s {
+                __BITFIELD_FIELD(uint32_t reserved_25_31:7,
+                __BITFIELD_FIELD(uint32_t dlls_c:1,
+                __BITFIELD_FIELD(uint32_t emis:1,
+                __BITFIELD_FIELD(uint32_t pds:1,
+                __BITFIELD_FIELD(uint32_t mrlss:1,
+                __BITFIELD_FIELD(uint32_t ccint_d:1,
+                __BITFIELD_FIELD(uint32_t pd_c:1,
+                __BITFIELD_FIELD(uint32_t mrls_c:1,
+                __BITFIELD_FIELD(uint32_t pf_d:1,
+                __BITFIELD_FIELD(uint32_t abp_d:1,
+                __BITFIELD_FIELD(uint32_t reserved_13_15:3,
+                __BITFIELD_FIELD(uint32_t dlls_en:1,
+                __BITFIELD_FIELD(uint32_t emic:1,
+                __BITFIELD_FIELD(uint32_t pcc:1,
+                __BITFIELD_FIELD(uint32_t pic:1,
+                __BITFIELD_FIELD(uint32_t aic:1,
+                __BITFIELD_FIELD(uint32_t hpint_en:1,
+                __BITFIELD_FIELD(uint32_t ccint_en:1,
+                __BITFIELD_FIELD(uint32_t pd_en:1,
+                __BITFIELD_FIELD(uint32_t mrls_en:1,
+                __BITFIELD_FIELD(uint32_t pf_en:1,
+                __BITFIELD_FIELD(uint32_t abp_en:1,
+                ;))))))))))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg035 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg035_s {
+                __BITFIELD_FIELD(uint32_t reserved_17_31:15,
+                __BITFIELD_FIELD(uint32_t crssv:1,
+                __BITFIELD_FIELD(uint32_t reserved_5_15:11,
+                __BITFIELD_FIELD(uint32_t crssve:1,
+                __BITFIELD_FIELD(uint32_t pmeie:1,
+                __BITFIELD_FIELD(uint32_t sefee:1,
+                __BITFIELD_FIELD(uint32_t senfee:1,
+                __BITFIELD_FIELD(uint32_t secee:1,
+                ;))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg040 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg040_s {
+                __BITFIELD_FIELD(uint32_t reserved_22_31:10,
+                __BITFIELD_FIELD(uint32_t ler:1,
+                __BITFIELD_FIELD(uint32_t ep3s:1,
+                __BITFIELD_FIELD(uint32_t ep2s:1,
+                __BITFIELD_FIELD(uint32_t ep1s:1,
+                __BITFIELD_FIELD(uint32_t eqc:1,
+                __BITFIELD_FIELD(uint32_t cdl:1,
+                __BITFIELD_FIELD(uint32_t cde:4,
+                __BITFIELD_FIELD(uint32_t csos:1,
+                __BITFIELD_FIELD(uint32_t emc:1,
+                __BITFIELD_FIELD(uint32_t tm:3,
+                __BITFIELD_FIELD(uint32_t sde:1,
+                __BITFIELD_FIELD(uint32_t hasd:1,
+                __BITFIELD_FIELD(uint32_t ec:1,
+                __BITFIELD_FIELD(uint32_t tls:4,
+                ;)))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg070 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg070_s {
+                __BITFIELD_FIELD(uint32_t reserved_12_31:20,
+                __BITFIELD_FIELD(uint32_t tplp:1,
+                __BITFIELD_FIELD(uint32_t reserved_9_10:2,
+                __BITFIELD_FIELD(uint32_t ce:1,
+                __BITFIELD_FIELD(uint32_t cc:1,
+                __BITFIELD_FIELD(uint32_t ge:1,
+                __BITFIELD_FIELD(uint32_t gc:1,
+                __BITFIELD_FIELD(uint32_t fep:5,
+                ;))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg075 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg075_s {
+                __BITFIELD_FIELD(uint32_t reserved_3_31:29,
+                __BITFIELD_FIELD(uint32_t fere:1,
+                __BITFIELD_FIELD(uint32_t nfere:1,
+                __BITFIELD_FIELD(uint32_t cere:1,
+                ;))))
+        } s;
+};
+
+union cvmx_pciercx_cfg448 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg448_s {
+                __BITFIELD_FIELD(uint32_t rtl:16,
+                __BITFIELD_FIELD(uint32_t rtltl:16,
+                ;))
+        } s;
+};
+
+union cvmx_pciercx_cfg452 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg452_s {
+                __BITFIELD_FIELD(uint32_t reserved_26_31:6,
+                __BITFIELD_FIELD(uint32_t eccrc:1,
+                __BITFIELD_FIELD(uint32_t reserved_22_24:3,
+                __BITFIELD_FIELD(uint32_t lme:6,
+                __BITFIELD_FIELD(uint32_t reserved_12_15:4,
+                __BITFIELD_FIELD(uint32_t link_rate:4,
+                __BITFIELD_FIELD(uint32_t flm:1,
+                __BITFIELD_FIELD(uint32_t reserved_6_6:1,
+                __BITFIELD_FIELD(uint32_t dllle:1,
+                __BITFIELD_FIELD(uint32_t reserved_4_4:1,
+                __BITFIELD_FIELD(uint32_t ra:1,
+                __BITFIELD_FIELD(uint32_t le:1,
+                __BITFIELD_FIELD(uint32_t sd:1,
+                __BITFIELD_FIELD(uint32_t omr:1,
+                ;))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg455 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg455_s {
+                __BITFIELD_FIELD(uint32_t m_cfg0_filt:1,
+                __BITFIELD_FIELD(uint32_t m_io_filt:1,
+                __BITFIELD_FIELD(uint32_t msg_ctrl:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_ecrc_filt:1,
+                __BITFIELD_FIELD(uint32_t m_ecrc_filt:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_len_err:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_attr_err:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_tc_err:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_fun_err:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_rid_err:1,
+                __BITFIELD_FIELD(uint32_t m_cpl_tag_err:1,
+                __BITFIELD_FIELD(uint32_t m_lk_filt:1,
+                __BITFIELD_FIELD(uint32_t m_cfg1_filt:1,
+                __BITFIELD_FIELD(uint32_t m_bar_match:1,
+                __BITFIELD_FIELD(uint32_t m_pois_filt:1,
+                __BITFIELD_FIELD(uint32_t m_fun:1,
+                __BITFIELD_FIELD(uint32_t dfcwt:1,
+                __BITFIELD_FIELD(uint32_t reserved_11_14:4,
+                __BITFIELD_FIELD(uint32_t skpiv:11,
+                ;)))))))))))))))))))
+        } s;
+};
+
+union cvmx_pciercx_cfg515 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg515_s {
+                __BITFIELD_FIELD(uint32_t reserved_21_31:11,
+                __BITFIELD_FIELD(uint32_t s_d_e:1,
+                __BITFIELD_FIELD(uint32_t ctcrb:1,
+                __BITFIELD_FIELD(uint32_t cpyts:1,
+                __BITFIELD_FIELD(uint32_t dsc:1,
+                __BITFIELD_FIELD(uint32_t le:9,
+                __BITFIELD_FIELD(uint32_t n_fts:8,
+                ;)))))))
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
new file mode 100644
index 000000000..5f013269a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
@@ -0,0 +1,826 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCSX_DEFS_H__
+#define __CVMX_PCSX_DEFS_H__
+
+static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
+}
+
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
+
+union cvmx_pcsx_anx_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t np:1;
+                uint64_t reserved_14_14:1;
+                uint64_t rem_flt:2;
+                uint64_t reserved_9_11:3;
+                uint64_t pause:2;
+                uint64_t hfd:1;
+                uint64_t fd:1;
+                uint64_t reserved_0_4:5;
+#else
+                uint64_t reserved_0_4:5;
+                uint64_t fd:1;
+                uint64_t hfd:1;
+                uint64_t pause:2;
+                uint64_t reserved_9_11:3;
+                uint64_t rem_flt:2;
+                uint64_t reserved_14_14:1;
+                uint64_t np:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_anx_ext_st_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_ext_st_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t thou_xfd:1;
+                uint64_t thou_xhd:1;
+                uint64_t thou_tfd:1;
+                uint64_t thou_thd:1;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t thou_thd:1;
+                uint64_t thou_tfd:1;
+                uint64_t thou_xhd:1;
+                uint64_t thou_xfd:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_anx_lp_abil_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_lp_abil_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t np:1;
+                uint64_t ack:1;
+                uint64_t rem_flt:2;
+                uint64_t reserved_9_11:3;
+                uint64_t pause:2;
+                uint64_t hfd:1;
+                uint64_t fd:1;
+                uint64_t reserved_0_4:5;
+#else
+                uint64_t reserved_0_4:5;
+                uint64_t fd:1;
+                uint64_t hfd:1;
+                uint64_t pause:2;
+                uint64_t reserved_9_11:3;
+                uint64_t rem_flt:2;
+                uint64_t ack:1;
+                uint64_t np:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_anx_results_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_results_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t pause:2;
+                uint64_t spd:2;
+                uint64_t an_cpt:1;
+                uint64_t dup:1;
+                uint64_t link_ok:1;
+#else
+                uint64_t link_ok:1;
+                uint64_t dup:1;
+                uint64_t an_cpt:1;
+                uint64_t spd:2;
+                uint64_t pause:2;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_intx_en_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_intx_en_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t dbg_sync_en:1;
+                uint64_t dup:1;
+                uint64_t sync_bad_en:1;
+                uint64_t an_bad_en:1;
+                uint64_t rxlock_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxerr_en:1;
+                uint64_t txbad_en:1;
+                uint64_t txfifo_en:1;
+                uint64_t txfifu_en:1;
+                uint64_t an_err_en:1;
+                uint64_t xmit_en:1;
+                uint64_t lnkspd_en:1;
+#else
+                uint64_t lnkspd_en:1;
+                uint64_t xmit_en:1;
+                uint64_t an_err_en:1;
+                uint64_t txfifu_en:1;
+                uint64_t txfifo_en:1;
+                uint64_t txbad_en:1;
+                uint64_t rxerr_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxlock_en:1;
+                uint64_t an_bad_en:1;
+                uint64_t sync_bad_en:1;
+                uint64_t dup:1;
+                uint64_t dbg_sync_en:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_pcsx_intx_en_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t dup:1;
+                uint64_t sync_bad_en:1;
+                uint64_t an_bad_en:1;
+                uint64_t rxlock_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxerr_en:1;
+                uint64_t txbad_en:1;
+                uint64_t txfifo_en:1;
+                uint64_t txfifu_en:1;
+                uint64_t an_err_en:1;
+                uint64_t xmit_en:1;
+                uint64_t lnkspd_en:1;
+#else
+                uint64_t lnkspd_en:1;
+                uint64_t xmit_en:1;
+                uint64_t an_err_en:1;
+                uint64_t txfifu_en:1;
+                uint64_t txfifo_en:1;
+                uint64_t txbad_en:1;
+                uint64_t rxerr_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxlock_en:1;
+                uint64_t an_bad_en:1;
+                uint64_t sync_bad_en:1;
+                uint64_t dup:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pcsx_intx_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_intx_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t dbg_sync:1;
+                uint64_t dup:1;
+                uint64_t sync_bad:1;
+                uint64_t an_bad:1;
+                uint64_t rxlock:1;
+                uint64_t rxbad:1;
+                uint64_t rxerr:1;
+                uint64_t txbad:1;
+                uint64_t txfifo:1;
+                uint64_t txfifu:1;
+                uint64_t an_err:1;
+                uint64_t xmit:1;
+                uint64_t lnkspd:1;
+#else
+                uint64_t lnkspd:1;
+                uint64_t xmit:1;
+                uint64_t an_err:1;
+                uint64_t txfifu:1;
+                uint64_t txfifo:1;
+                uint64_t txbad:1;
+                uint64_t rxerr:1;
+                uint64_t rxbad:1;
+                uint64_t rxlock:1;
+                uint64_t an_bad:1;
+                uint64_t sync_bad:1;
+                uint64_t dup:1;
+                uint64_t dbg_sync:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_pcsx_intx_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t dup:1;
+                uint64_t sync_bad:1;
+                uint64_t an_bad:1;
+                uint64_t rxlock:1;
+                uint64_t rxbad:1;
+                uint64_t rxerr:1;
+                uint64_t txbad:1;
+                uint64_t txfifo:1;
+                uint64_t txfifu:1;
+                uint64_t an_err:1;
+                uint64_t xmit:1;
+                uint64_t lnkspd:1;
+#else
+                uint64_t lnkspd:1;
+                uint64_t xmit:1;
+                uint64_t an_err:1;
+                uint64_t txfifu:1;
+                uint64_t txfifo:1;
+                uint64_t txbad:1;
+                uint64_t rxerr:1;
+                uint64_t rxbad:1;
+                uint64_t rxlock:1;
+                uint64_t an_bad:1;
+                uint64_t sync_bad:1;
+                uint64_t dup:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pcsx_linkx_timer_count_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_linkx_timer_count_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t count:16;
+#else
+                uint64_t count:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_log_anlx_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_log_anlx_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t lafifovfl:1;
+                uint64_t la_en:1;
+                uint64_t pkt_sz:2;
+#else
+                uint64_t pkt_sz:2;
+                uint64_t la_en:1;
+                uint64_t lafifovfl:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_miscx_ctl_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_miscx_ctl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t sgmii:1;
+                uint64_t gmxeno:1;
+                uint64_t loopbck2:1;
+                uint64_t mac_phy:1;
+                uint64_t mode:1;
+                uint64_t an_ovrd:1;
+                uint64_t samp_pt:7;
+#else
+                uint64_t samp_pt:7;
+                uint64_t an_ovrd:1;
+                uint64_t mode:1;
+                uint64_t mac_phy:1;
+                uint64_t loopbck2:1;
+                uint64_t gmxeno:1;
+                uint64_t sgmii:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_mrx_control_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_mrx_control_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t reset:1;
+                uint64_t loopbck1:1;
+                uint64_t spdlsb:1;
+                uint64_t an_en:1;
+                uint64_t pwr_dn:1;
+                uint64_t reserved_10_10:1;
+                uint64_t rst_an:1;
+                uint64_t dup:1;
+                uint64_t coltst:1;
+                uint64_t spdmsb:1;
+                uint64_t uni:1;
+                uint64_t reserved_0_4:5;
+#else
+                uint64_t reserved_0_4:5;
+                uint64_t uni:1;
+                uint64_t spdmsb:1;
+                uint64_t coltst:1;
+                uint64_t dup:1;
+                uint64_t rst_an:1;
+                uint64_t reserved_10_10:1;
+                uint64_t pwr_dn:1;
+                uint64_t an_en:1;
+                uint64_t spdlsb:1;
+                uint64_t loopbck1:1;
+                uint64_t reset:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_mrx_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_mrx_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t hun_t4:1;
+                uint64_t hun_xfd:1;
+                uint64_t hun_xhd:1;
+                uint64_t ten_fd:1;
+                uint64_t ten_hd:1;
+                uint64_t hun_t2fd:1;
+                uint64_t hun_t2hd:1;
+                uint64_t ext_st:1;
+                uint64_t reserved_7_7:1;
+                uint64_t prb_sup:1;
+                uint64_t an_cpt:1;
+                uint64_t rm_flt:1;
+                uint64_t an_abil:1;
+                uint64_t lnk_st:1;
+                uint64_t reserved_1_1:1;
+                uint64_t extnd:1;
+#else
+                uint64_t extnd:1;
+                uint64_t reserved_1_1:1;
+                uint64_t lnk_st:1;
+                uint64_t an_abil:1;
+                uint64_t rm_flt:1;
+                uint64_t an_cpt:1;
+                uint64_t prb_sup:1;
+                uint64_t reserved_7_7:1;
+                uint64_t ext_st:1;
+                uint64_t hun_t2hd:1;
+                uint64_t hun_t2fd:1;
+                uint64_t ten_hd:1;
+                uint64_t ten_fd:1;
+                uint64_t hun_xhd:1;
+                uint64_t hun_xfd:1;
+                uint64_t hun_t4:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_rxx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_rxx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t rx_bad:1;
+                uint64_t rx_st:5;
+                uint64_t sync_bad:1;
+                uint64_t sync:4;
+                uint64_t an_bad:1;
+                uint64_t an_st:4;
+#else
+                uint64_t an_st:4;
+                uint64_t an_bad:1;
+                uint64_t sync:4;
+                uint64_t sync_bad:1;
+                uint64_t rx_st:5;
+                uint64_t rx_bad:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_rxx_sync_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_rxx_sync_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t sync:1;
+                uint64_t bit_lock:1;
+#else
+                uint64_t bit_lock:1;
+                uint64_t sync:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_sgmx_an_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t link:1;
+                uint64_t ack:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dup:1;
+                uint64_t speed:2;
+                uint64_t reserved_1_9:9;
+                uint64_t one:1;
+#else
+                uint64_t one:1;
+                uint64_t reserved_1_9:9;
+                uint64_t speed:2;
+                uint64_t dup:1;
+                uint64_t reserved_13_13:1;
+                uint64_t ack:1;
+                uint64_t link:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_sgmx_lp_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t link:1;
+                uint64_t reserved_13_14:2;
+                uint64_t dup:1;
+                uint64_t speed:2;
+                uint64_t reserved_1_9:9;
+                uint64_t one:1;
+#else
+                uint64_t one:1;
+                uint64_t reserved_1_9:9;
+                uint64_t speed:2;
+                uint64_t dup:1;
+                uint64_t reserved_13_14:2;
+                uint64_t link:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_txx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_txx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t xmit:2;
+                uint64_t tx_bad:1;
+                uint64_t ord_st:4;
+#else
+                uint64_t ord_st:4;
+                uint64_t tx_bad:1;
+                uint64_t xmit:2;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_pcsx_tx_rxx_polarity_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t rxovrd:1;
+                uint64_t autorxpl:1;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+#else
+                uint64_t txplrt:1;
+                uint64_t rxplrt:1;
+                uint64_t autorxpl:1;
+                uint64_t rxovrd:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
new file mode 100644
index 000000000..b353775ee
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
@@ -0,0 +1,664 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCSXX_DEFS_H__
+#define __CVMX_PCSXX_DEFS_H__
+
+static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
+        }
+        return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
+}
+
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+
+union cvmx_pcsxx_10gbx_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_10gbx_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t alignd:1;
+                uint64_t pattst:1;
+                uint64_t reserved_4_10:7;
+                uint64_t l3sync:1;
+                uint64_t l2sync:1;
+                uint64_t l1sync:1;
+                uint64_t l0sync:1;
+#else
+                uint64_t l0sync:1;
+                uint64_t l1sync:1;
+                uint64_t l2sync:1;
+                uint64_t l3sync:1;
+                uint64_t reserved_4_10:7;
+                uint64_t pattst:1;
+                uint64_t alignd:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_bist_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_bist_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t bist_status:1;
+#else
+                uint64_t bist_status:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_bit_lock_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_bit_lock_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t bitlck3:1;
+                uint64_t bitlck2:1;
+                uint64_t bitlck1:1;
+                uint64_t bitlck0:1;
+#else
+                uint64_t bitlck0:1;
+                uint64_t bitlck1:1;
+                uint64_t bitlck2:1;
+                uint64_t bitlck3:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_control1_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_control1_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t reset:1;
+                uint64_t loopbck1:1;
+                uint64_t spdsel1:1;
+                uint64_t reserved_12_12:1;
+                uint64_t lo_pwr:1;
+                uint64_t reserved_7_10:4;
+                uint64_t spdsel0:1;
+                uint64_t spd:4;
+                uint64_t reserved_0_1:2;
+#else
+                uint64_t reserved_0_1:2;
+                uint64_t spd:4;
+                uint64_t spdsel0:1;
+                uint64_t reserved_7_10:4;
+                uint64_t lo_pwr:1;
+                uint64_t reserved_12_12:1;
+                uint64_t spdsel1:1;
+                uint64_t loopbck1:1;
+                uint64_t reset:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_control2_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_control2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t type:2;
+#else
+                uint64_t type:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_int_en_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_int_en_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t dbg_sync_en:1;
+                uint64_t algnlos_en:1;
+                uint64_t synlos_en:1;
+                uint64_t bitlckls_en:1;
+                uint64_t rxsynbad_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t txflt_en:1;
+#else
+                uint64_t txflt_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxsynbad_en:1;
+                uint64_t bitlckls_en:1;
+                uint64_t synlos_en:1;
+                uint64_t algnlos_en:1;
+                uint64_t dbg_sync_en:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+        struct cvmx_pcsxx_int_en_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t algnlos_en:1;
+                uint64_t synlos_en:1;
+                uint64_t bitlckls_en:1;
+                uint64_t rxsynbad_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t txflt_en:1;
+#else
+                uint64_t txflt_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxsynbad_en:1;
+                uint64_t bitlckls_en:1;
+                uint64_t synlos_en:1;
+                uint64_t algnlos_en:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pcsxx_int_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t dbg_sync:1;
+                uint64_t algnlos:1;
+                uint64_t synlos:1;
+                uint64_t bitlckls:1;
+                uint64_t rxsynbad:1;
+                uint64_t rxbad:1;
+                uint64_t txflt:1;
+#else
+                uint64_t txflt:1;
+                uint64_t rxbad:1;
+                uint64_t rxsynbad:1;
+                uint64_t bitlckls:1;
+                uint64_t synlos:1;
+                uint64_t algnlos:1;
+                uint64_t dbg_sync:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+        struct cvmx_pcsxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t algnlos:1;
+                uint64_t synlos:1;
+                uint64_t bitlckls:1;
+                uint64_t rxsynbad:1;
+                uint64_t rxbad:1;
+                uint64_t txflt:1;
+#else
+                uint64_t txflt:1;
+                uint64_t rxbad:1;
+                uint64_t rxsynbad:1;
+                uint64_t bitlckls:1;
+                uint64_t synlos:1;
+                uint64_t algnlos:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pcsxx_log_anl_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_log_anl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t enc_mode:1;
+                uint64_t drop_ln:2;
+                uint64_t lafifovfl:1;
+                uint64_t la_en:1;
+                uint64_t pkt_sz:2;
+#else
+                uint64_t pkt_sz:2;
+                uint64_t la_en:1;
+                uint64_t lafifovfl:1;
+                uint64_t drop_ln:2;
+                uint64_t enc_mode:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_misc_ctl_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_misc_ctl_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t tx_swap:1;
+                uint64_t rx_swap:1;
+                uint64_t xaui:1;
+                uint64_t gmxeno:1;
+#else
+                uint64_t gmxeno:1;
+                uint64_t xaui:1;
+                uint64_t rx_swap:1;
+                uint64_t tx_swap:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_rx_sync_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_rx_sync_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t sync3st:4;
+                uint64_t sync2st:4;
+                uint64_t sync1st:4;
+                uint64_t sync0st:4;
+#else
+                uint64_t sync0st:4;
+                uint64_t sync1st:4;
+                uint64_t sync2st:4;
+                uint64_t sync3st:4;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_spd_abil_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_spd_abil_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t tenpasst:1;
+                uint64_t tengb:1;
+#else
+                uint64_t tengb:1;
+                uint64_t tenpasst:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_status1_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_status1_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t flt:1;
+                uint64_t reserved_3_6:4;
+                uint64_t rcv_lnk:1;
+                uint64_t lpable:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t lpable:1;
+                uint64_t rcv_lnk:1;
+                uint64_t reserved_3_6:4;
+                uint64_t flt:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_status2_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_status2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t dev:2;
+                uint64_t reserved_12_13:2;
+                uint64_t xmtflt:1;
+                uint64_t rcvflt:1;
+                uint64_t reserved_3_9:7;
+                uint64_t tengb_w:1;
+                uint64_t tengb_x:1;
+                uint64_t tengb_r:1;
+#else
+                uint64_t tengb_r:1;
+                uint64_t tengb_x:1;
+                uint64_t tengb_w:1;
+                uint64_t reserved_3_9:7;
+                uint64_t rcvflt:1;
+                uint64_t xmtflt:1;
+                uint64_t reserved_12_13:2;
+                uint64_t dev:2;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pcsxx_tx_rx_polarity_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t xor_rxplrt:4;
+                uint64_t xor_txplrt:4;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+#else
+                uint64_t txplrt:1;
+                uint64_t rxplrt:1;
+                uint64_t xor_txplrt:4;
+                uint64_t xor_rxplrt:4;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+#else
+                uint64_t txplrt:1;
+                uint64_t rxplrt:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_pcsxx_tx_rx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_tx_rx_states_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t term_err:1;
+                uint64_t syn3bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn0bad:1;
+                uint64_t rxbad:1;
+                uint64_t algn_st:3;
+                uint64_t rx_st:2;
+                uint64_t tx_st:3;
+#else
+                uint64_t tx_st:3;
+                uint64_t rx_st:2;
+                uint64_t algn_st:3;
+                uint64_t rxbad:1;
+                uint64_t syn0bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn3bad:1;
+                uint64_t term_err:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+        struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t syn3bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn0bad:1;
+                uint64_t rxbad:1;
+                uint64_t algn_st:3;
+                uint64_t rx_st:2;
+                uint64_t tx_st:3;
+#else
+                uint64_t tx_st:3;
+                uint64_t rx_st:2;
+                uint64_t algn_st:3;
+                uint64_t rxbad:1;
+                uint64_t syn0bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn3bad:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn52xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 000000000..d2d6dba93
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,651 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
+
+#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
+
+union cvmx_pemx_bar1_indexx {
+        uint64_t u64;
+        struct cvmx_pemx_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t addr_idx:16;
+                uint64_t ca:1;
+                uint64_t end_swp:2;
+                uint64_t addr_v:1;
+#else
+                uint64_t addr_v:1;
+                uint64_t end_swp:2;
+                uint64_t ca:1;
+                uint64_t addr_idx:16;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_pemx_bar2_mask {
+        uint64_t u64;
+        struct cvmx_pemx_bar2_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t mask:35;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t mask:35;
+                uint64_t reserved_38_63:26;
+#endif
+        } s;
+};
+
+union cvmx_pemx_bar_ctl {
+        uint64_t u64;
+        struct cvmx_pemx_bar_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t bar1_siz:3;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+#else
+                uint64_t bar2_cax:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_enb:1;
+                uint64_t bar1_siz:3;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+};
+
+union cvmx_pemx_bist_status {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+#else
+                uint64_t sot:1;
+                uint64_t rqhdr0:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata0:1;
+                uint64_t retry:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pemx_bist_status2 {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t e2p_cpl:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_p:1;
+                uint64_t peai_p2e:1;
+                uint64_t pef_tpf1:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tc0:1;
+                uint64_t ppf:1;
+#else
+                uint64_t ppf:1;
+                uint64_t pef_tc0:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tpf1:1;
+                uint64_t peai_p2e:1;
+                uint64_t e2p_p:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_cpl:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_pemx_cfg_rd {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_rd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:32;
+                uint64_t addr:32;
+#else
+                uint64_t addr:32;
+                uint64_t data:32;
+#endif
+        } s;
+};
+
+union cvmx_pemx_cfg_wr {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_wr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:32;
+                uint64_t addr:32;
+#else
+                uint64_t addr:32;
+                uint64_t data:32;
+#endif
+        } s;
+};
+
+union cvmx_pemx_cpl_lut_valid {
+        uint64_t u64;
+        struct cvmx_pemx_cpl_lut_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pemx_ctl_status {
+        uint64_t u64;
+        struct cvmx_pemx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t auto_sd:1;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t reserved_32_33:2;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_12_15:4;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t fast_lm:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+#else
+                uint64_t inv_lcrc:1;
+                uint64_t inv_ecrc:1;
+                uint64_t fast_lm:1;
+                uint64_t ro_ctlp:1;
+                uint64_t lnk_enb:1;
+                uint64_t dly_one:1;
+                uint64_t nf_ecrc:1;
+                uint64_t reserved_7_8:2;
+                uint64_t ob_p_cmd:1;
+                uint64_t pm_xpme:1;
+                uint64_t pm_xtoff:1;
+                uint64_t reserved_12_15:4;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_32_33:2;
+                uint64_t pbus:8;
+                uint64_t dnum:5;
+                uint64_t auto_sd:1;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pemx_dbg_info {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+#else
+                uint64_t spoison:1;
+                uint64_t rtlpmal:1;
+                uint64_t rtlplle:1;
+                uint64_t recrce:1;
+                uint64_t rpoison:1;
+                uint64_t rcemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rfemrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rptamrc:1;
+                uint64_t rumep:1;
+                uint64_t rvdm:1;
+                uint64_t acto:1;
+                uint64_t rte:1;
+                uint64_t mre:1;
+                uint64_t rdwdle:1;
+                uint64_t rtwdle:1;
+                uint64_t dpeoosd:1;
+                uint64_t fcpvwt:1;
+                uint64_t rpe:1;
+                uint64_t fcuv:1;
+                uint64_t rqo:1;
+                uint64_t rauc:1;
+                uint64_t racur:1;
+                uint64_t racca:1;
+                uint64_t caar:1;
+                uint64_t rarwdns:1;
+                uint64_t ramtlp:1;
+                uint64_t racpp:1;
+                uint64_t rawwpp:1;
+                uint64_t ecrc_e:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_pemx_dbg_info_en {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+#else
+                uint64_t spoison:1;
+                uint64_t rtlpmal:1;
+                uint64_t rtlplle:1;
+                uint64_t recrce:1;
+                uint64_t rpoison:1;
+                uint64_t rcemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rfemrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rptamrc:1;
+                uint64_t rumep:1;
+                uint64_t rvdm:1;
+                uint64_t acto:1;
+                uint64_t rte:1;
+                uint64_t mre:1;
+                uint64_t rdwdle:1;
+                uint64_t rtwdle:1;
+                uint64_t dpeoosd:1;
+                uint64_t fcpvwt:1;
+                uint64_t rpe:1;
+                uint64_t fcuv:1;
+                uint64_t rqo:1;
+                uint64_t rauc:1;
+                uint64_t racur:1;
+                uint64_t racca:1;
+                uint64_t caar:1;
+                uint64_t rarwdns:1;
+                uint64_t ramtlp:1;
+                uint64_t racpp:1;
+                uint64_t rawwpp:1;
+                uint64_t ecrc_e:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_pemx_diag_status {
+        uint64_t u64;
+        struct cvmx_pemx_diag_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t pm_dst:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_en:1;
+                uint64_t aux_en:1;
+#else
+                uint64_t aux_en:1;
+                uint64_t pm_en:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_dst:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_pemx_inb_read_credits {
+        uint64_t u64;
+        struct cvmx_pemx_inb_read_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t num:6;
+#else
+                uint64_t num:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_pemx_int_enb {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+#else
+                uint64_t aeri:1;
+                uint64_t se:1;
+                uint64_t pmei:1;
+                uint64_t pmem:1;
+                uint64_t up_b1:1;
+                uint64_t up_b2:1;
+                uint64_t up_bx:1;
+                uint64_t un_b1:1;
+                uint64_t un_b2:1;
+                uint64_t un_bx:1;
+                uint64_t exc:1;
+                uint64_t rdlk:1;
+                uint64_t crs_er:1;
+                uint64_t crs_dr:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_pemx_int_enb_int {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+#else
+                uint64_t aeri:1;
+                uint64_t se:1;
+                uint64_t pmei:1;
+                uint64_t pmem:1;
+                uint64_t up_b1:1;
+                uint64_t up_b2:1;
+                uint64_t up_bx:1;
+                uint64_t un_b1:1;
+                uint64_t un_b2:1;
+                uint64_t un_bx:1;
+                uint64_t exc:1;
+                uint64_t rdlk:1;
+                uint64_t crs_er:1;
+                uint64_t crs_dr:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_pemx_int_sum {
+        uint64_t u64;
+        struct cvmx_pemx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+#else
+                uint64_t aeri:1;
+                uint64_t se:1;
+                uint64_t pmei:1;
+                uint64_t pmem:1;
+                uint64_t up_b1:1;
+                uint64_t up_b2:1;
+                uint64_t up_bx:1;
+                uint64_t un_b1:1;
+                uint64_t un_b2:1;
+                uint64_t un_bx:1;
+                uint64_t exc:1;
+                uint64_t rdlk:1;
+                uint64_t crs_er:1;
+                uint64_t crs_dr:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_pemx_p2n_bar0_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar0_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:50;
+                uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t addr:50;
+#endif
+        } s;
+};
+
+union cvmx_pemx_p2n_bar1_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar1_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:38;
+                uint64_t reserved_0_25:26;
+#else
+                uint64_t reserved_0_25:26;
+                uint64_t addr:38;
+#endif
+        } s;
+};
+
+union cvmx_pemx_p2n_bar2_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:23;
+                uint64_t reserved_0_40:41;
+#else
+                uint64_t reserved_0_40:41;
+                uint64_t addr:23;
+#endif
+        } s;
+};
+
+union cvmx_pemx_p2p_barx_end {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t addr:52;
+#endif
+        } s;
+};
+
+union cvmx_pemx_p2p_barx_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t addr:52;
+#endif
+        } s;
+};
+
+union cvmx_pemx_tlp_credits {
+        uint64_t u64;
+        struct cvmx_pemx_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t pem_cpl:8;
+                uint64_t pem_np:8;
+                uint64_t pem_p:8;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+#else
+                uint64_t sli_p:8;
+                uint64_t sli_np:8;
+                uint64_t sli_cpl:8;
+                uint64_t pem_p:8;
+                uint64_t pem_np:8;
+                uint64_t pem_cpl:8;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+        struct cvmx_pemx_tlp_credits_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_24_47:24;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+#else
+                uint64_t sli_p:8;
+                uint64_t sli_np:8;
+                uint64_t sli_cpl:8;
+                uint64_t reserved_24_47:24;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_56_63:8;
+#endif
+        } cn61xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
new file mode 100644
index 000000000..665610825
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -0,0 +1,579 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PESCX_DEFS_H__
+#define __CVMX_PESCX_DEFS_H__
+
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
+
+union cvmx_pescx_bist_status {
+        uint64_t u64;
+        struct cvmx_pescx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t rqdata5:1;
+                uint64_t ctlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ptlp_or:1;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata4:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+#else
+                uint64_t sot:1;
+                uint64_t rqhdr0:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqdata4:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata0:1;
+                uint64_t retry:1;
+                uint64_t ptlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ctlp_or:1;
+                uint64_t rqdata5:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_pescx_bist_status_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t ctlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ptlp_or:1;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata4:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+#else
+                uint64_t sot:1;
+                uint64_t rqhdr0:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqdata4:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata0:1;
+                uint64_t retry:1;
+                uint64_t ptlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ctlp_or:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_pescx_bist_status2 {
+        uint64_t u64;
+        struct cvmx_pescx_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t cto_p2e:1;
+                uint64_t e2p_cpl:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_p:1;
+                uint64_t e2p_rsl:1;
+                uint64_t dbg_p2e:1;
+                uint64_t peai_p2e:1;
+                uint64_t rsl_p2e:1;
+                uint64_t pef_tpf1:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tc0:1;
+                uint64_t ppf:1;
+#else
+                uint64_t ppf:1;
+                uint64_t pef_tc0:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tpf1:1;
+                uint64_t rsl_p2e:1;
+                uint64_t peai_p2e:1;
+                uint64_t dbg_p2e:1;
+                uint64_t e2p_rsl:1;
+                uint64_t e2p_p:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_cpl:1;
+                uint64_t cto_p2e:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_pescx_cfg_rd {
+        uint64_t u64;
+        struct cvmx_pescx_cfg_rd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:32;
+                uint64_t addr:32;
+#else
+                uint64_t addr:32;
+                uint64_t data:32;
+#endif
+        } s;
+};
+
+union cvmx_pescx_cfg_wr {
+        uint64_t u64;
+        struct cvmx_pescx_cfg_wr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:32;
+                uint64_t addr:32;
+#else
+                uint64_t addr:32;
+                uint64_t data:32;
+#endif
+        } s;
+};
+
+union cvmx_pescx_cpl_lut_valid {
+        uint64_t u64;
+        struct cvmx_pescx_cpl_lut_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pescx_ctl_status {
+        uint64_t u64;
+        struct cvmx_pescx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t qlm_cfg:2;
+                uint64_t lane_swp:1;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t reserved_2_2:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+#else
+                uint64_t inv_lcrc:1;
+                uint64_t inv_ecrc:1;
+                uint64_t reserved_2_2:1;
+                uint64_t ro_ctlp:1;
+                uint64_t lnk_enb:1;
+                uint64_t dly_one:1;
+                uint64_t nf_ecrc:1;
+                uint64_t reserved_7_8:2;
+                uint64_t ob_p_cmd:1;
+                uint64_t pm_xpme:1;
+                uint64_t pm_xtoff:1;
+                uint64_t lane_swp:1;
+                uint64_t qlm_cfg:2;
+                uint64_t pbus:8;
+                uint64_t dnum:5;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+        struct cvmx_pescx_ctl_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t qlm_cfg:2;
+                uint64_t reserved_12_12:1;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t reserved_2_2:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+#else
+                uint64_t inv_lcrc:1;
+                uint64_t inv_ecrc:1;
+                uint64_t reserved_2_2:1;
+                uint64_t ro_ctlp:1;
+                uint64_t lnk_enb:1;
+                uint64_t dly_one:1;
+                uint64_t nf_ecrc:1;
+                uint64_t reserved_7_8:2;
+                uint64_t ob_p_cmd:1;
+                uint64_t pm_xpme:1;
+                uint64_t pm_xtoff:1;
+                uint64_t reserved_12_12:1;
+                uint64_t qlm_cfg:2;
+                uint64_t pbus:8;
+                uint64_t dnum:5;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn56xx;
+};
+
+union cvmx_pescx_ctl_status2 {
+        uint64_t u64;
+        struct cvmx_pescx_ctl_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t pclk_run:1;
+                uint64_t pcierst:1;
+#else
+                uint64_t pcierst:1;
+                uint64_t pclk_run:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+        struct cvmx_pescx_ctl_status2_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t pcierst:1;
+#else
+                uint64_t pcierst:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } cn52xxp1;
+};
+
+union cvmx_pescx_dbg_info {
+        uint64_t u64;
+        struct cvmx_pescx_dbg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+#else
+                uint64_t spoison:1;
+                uint64_t rtlpmal:1;
+                uint64_t rtlplle:1;
+                uint64_t recrce:1;
+                uint64_t rpoison:1;
+                uint64_t rcemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rfemrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rptamrc:1;
+                uint64_t rumep:1;
+                uint64_t rvdm:1;
+                uint64_t acto:1;
+                uint64_t rte:1;
+                uint64_t mre:1;
+                uint64_t rdwdle:1;
+                uint64_t rtwdle:1;
+                uint64_t dpeoosd:1;
+                uint64_t fcpvwt:1;
+                uint64_t rpe:1;
+                uint64_t fcuv:1;
+                uint64_t rqo:1;
+                uint64_t rauc:1;
+                uint64_t racur:1;
+                uint64_t racca:1;
+                uint64_t caar:1;
+                uint64_t rarwdns:1;
+                uint64_t ramtlp:1;
+                uint64_t racpp:1;
+                uint64_t rawwpp:1;
+                uint64_t ecrc_e:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_pescx_dbg_info_en {
+        uint64_t u64;
+        struct cvmx_pescx_dbg_info_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+#else
+                uint64_t spoison:1;
+                uint64_t rtlpmal:1;
+                uint64_t rtlplle:1;
+                uint64_t recrce:1;
+                uint64_t rpoison:1;
+                uint64_t rcemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rfemrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rptamrc:1;
+                uint64_t rumep:1;
+                uint64_t rvdm:1;
+                uint64_t acto:1;
+                uint64_t rte:1;
+                uint64_t mre:1;
+                uint64_t rdwdle:1;
+                uint64_t rtwdle:1;
+                uint64_t dpeoosd:1;
+                uint64_t fcpvwt:1;
+                uint64_t rpe:1;
+                uint64_t fcuv:1;
+                uint64_t rqo:1;
+                uint64_t rauc:1;
+                uint64_t racur:1;
+                uint64_t racca:1;
+                uint64_t caar:1;
+                uint64_t rarwdns:1;
+                uint64_t ramtlp:1;
+                uint64_t racpp:1;
+                uint64_t rawwpp:1;
+                uint64_t ecrc_e:1;
+                uint64_t reserved_31_63:33;
+#endif
+        } s;
+};
+
+union cvmx_pescx_diag_status {
+        uint64_t u64;
+        struct cvmx_pescx_diag_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t pm_dst:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_en:1;
+                uint64_t aux_en:1;
+#else
+                uint64_t aux_en:1;
+                uint64_t pm_en:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_dst:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_pescx_p2n_bar0_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar0_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:50;
+                uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t addr:50;
+#endif
+        } s;
+};
+
+union cvmx_pescx_p2n_bar1_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar1_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:38;
+                uint64_t reserved_0_25:26;
+#else
+                uint64_t reserved_0_25:26;
+                uint64_t addr:38;
+#endif
+        } s;
+};
+
+union cvmx_pescx_p2n_bar2_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:25;
+                uint64_t reserved_0_38:39;
+#else
+                uint64_t reserved_0_38:39;
+                uint64_t addr:25;
+#endif
+        } s;
+};
+
+union cvmx_pescx_p2p_barx_end {
+        uint64_t u64;
+        struct cvmx_pescx_p2p_barx_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t addr:52;
+#endif
+        } s;
+};
+
+union cvmx_pescx_p2p_barx_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2p_barx_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t addr:52;
+#endif
+        } s;
+};
+
+union cvmx_pescx_tlp_credits {
+        uint64_t u64;
+        struct cvmx_pescx_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pescx_tlp_credits_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t pesc_cpl:8;
+                uint64_t pesc_np:8;
+                uint64_t pesc_p:8;
+                uint64_t npei_cpl:8;
+                uint64_t npei_np:8;
+                uint64_t npei_p:8;
+#else
+                uint64_t npei_p:8;
+                uint64_t npei_np:8;
+                uint64_t npei_cpl:8;
+                uint64_t pesc_p:8;
+                uint64_t pesc_np:8;
+                uint64_t pesc_cpl:8;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_56_63:8;
+#endif
+        } cn52xx;
+        struct cvmx_pescx_tlp_credits_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_38_63:26;
+                uint64_t peai_ppf:8;
+                uint64_t pesc_cpl:5;
+                uint64_t pesc_np:5;
+                uint64_t pesc_p:5;
+                uint64_t npei_cpl:5;
+                uint64_t npei_np:5;
+                uint64_t npei_p:5;
+#else
+                uint64_t npei_p:5;
+                uint64_t npei_np:5;
+                uint64_t npei_cpl:5;
+                uint64_t pesc_p:5;
+                uint64_t pesc_np:5;
+                uint64_t pesc_cpl:5;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_38_63:26;
+#endif
+        } cn52xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
new file mode 100644
index 000000000..eb673f351
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -0,0 +1,224 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PEXP_DEFS_H__
+#define __CVMX_PEXP_DEFS_H__
+
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
new file mode 100644
index 000000000..e42f411bd
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
@@ -0,0 +1,2734 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PIP_DEFS_H__
+#define __CVMX_PIP_DEFS_H__
+
+/*
+ * Enumeration representing the amount of packet processing
+ * and validation performed by the input hardware.
+ */
+enum cvmx_pip_port_parse_mode {
+        /*
+         * Packet input doesn't perform any processing of the input
+         * packet.
+         */
+        CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
+        /*
+         * Full packet processing is performed with pointer starting
+         * at the L2 (ethernet MAC) header.
+         */
+        CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
+        /*
+         * Input packets are assumed to be IP.  Results from non IP
+         * packets is undefined. Pointers reference the beginning of
+         * the IP header.
+         */
+        CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
+};
+
+#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
+#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
+#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
+#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
+#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
+#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
+#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
+#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
+#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
+#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
+#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
+#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
+#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
+#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
+#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
+#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
+#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
+#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
+#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
+#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
+#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
+#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
+#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
+#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
+#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
+#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
+#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
+#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
+#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
+#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
+#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
+#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
+#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
+#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
+#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
+#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
+#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
+#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
+#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
+#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
+#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
+#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
+#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
+#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
+
+union cvmx_pip_alt_skip_cfgx {
+        uint64_t u64;
+        struct cvmx_pip_alt_skip_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_57_63:7;
+                uint64_t len:1;
+                uint64_t reserved_46_55:10;
+                uint64_t bit1:6;
+                uint64_t reserved_38_39:2;
+                uint64_t bit0:6;
+                uint64_t reserved_23_31:9;
+                uint64_t skip3:7;
+                uint64_t reserved_15_15:1;
+                uint64_t skip2:7;
+                uint64_t reserved_7_7:1;
+                uint64_t skip1:7;
+#else
+                uint64_t skip1:7;
+                uint64_t reserved_7_7:1;
+                uint64_t skip2:7;
+                uint64_t reserved_15_15:1;
+                uint64_t skip3:7;
+                uint64_t reserved_23_31:9;
+                uint64_t bit0:6;
+                uint64_t reserved_38_39:2;
+                uint64_t bit1:6;
+                uint64_t reserved_46_55:10;
+                uint64_t len:1;
+                uint64_t reserved_57_63:7;
+#endif
+        } s;
+};
+
+union cvmx_pip_bck_prs {
+        uint64_t u64;
+        struct cvmx_pip_bck_prs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bckprs:1;
+                uint64_t reserved_13_62:50;
+                uint64_t hiwater:5;
+                uint64_t reserved_5_7:3;
+                uint64_t lowater:5;
+#else
+                uint64_t lowater:5;
+                uint64_t reserved_5_7:3;
+                uint64_t hiwater:5;
+                uint64_t reserved_13_62:50;
+                uint64_t bckprs:1;
+#endif
+        } s;
+};
+
+union cvmx_pip_bist_status {
+        uint64_t u64;
+        struct cvmx_pip_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t bist:22;
+#else
+                uint64_t bist:22;
+                uint64_t reserved_22_63:42;
+#endif
+        } s;
+        struct cvmx_pip_bist_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t bist:18;
+#else
+                uint64_t bist:18;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn30xx;
+        struct cvmx_pip_bist_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t bist:17;
+#else
+                uint64_t bist:17;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn50xx;
+        struct cvmx_pip_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t bist:20;
+#else
+                uint64_t bist:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn61xx;
+};
+
+union cvmx_pip_bsel_ext_cfgx {
+        uint64_t u64;
+        struct cvmx_pip_bsel_ext_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t upper_tag:16;
+                uint64_t tag:8;
+                uint64_t reserved_25_31:7;
+                uint64_t offset:9;
+                uint64_t reserved_7_15:9;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_15:9;
+                uint64_t offset:9;
+                uint64_t reserved_25_31:7;
+                uint64_t tag:8;
+                uint64_t upper_tag:16;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+};
+
+union cvmx_pip_bsel_ext_posx {
+        uint64_t u64;
+        struct cvmx_pip_bsel_ext_posx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pos7_val:1;
+                uint64_t pos7:7;
+                uint64_t pos6_val:1;
+                uint64_t pos6:7;
+                uint64_t pos5_val:1;
+                uint64_t pos5:7;
+                uint64_t pos4_val:1;
+                uint64_t pos4:7;
+                uint64_t pos3_val:1;
+                uint64_t pos3:7;
+                uint64_t pos2_val:1;
+                uint64_t pos2:7;
+                uint64_t pos1_val:1;
+                uint64_t pos1:7;
+                uint64_t pos0_val:1;
+                uint64_t pos0:7;
+#else
+                uint64_t pos0:7;
+                uint64_t pos0_val:1;
+                uint64_t pos1:7;
+                uint64_t pos1_val:1;
+                uint64_t pos2:7;
+                uint64_t pos2_val:1;
+                uint64_t pos3:7;
+                uint64_t pos3_val:1;
+                uint64_t pos4:7;
+                uint64_t pos4_val:1;
+                uint64_t pos5:7;
+                uint64_t pos5_val:1;
+                uint64_t pos6:7;
+                uint64_t pos6_val:1;
+                uint64_t pos7:7;
+                uint64_t pos7_val:1;
+#endif
+        } s;
+};
+
+union cvmx_pip_bsel_tbl_entx {
+        uint64_t u64;
+        struct cvmx_pip_bsel_tbl_entx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t tag_en:1;
+                uint64_t grp_en:1;
+                uint64_t tt_en:1;
+                uint64_t qos_en:1;
+                uint64_t reserved_40_59:20;
+                uint64_t tag:8;
+                uint64_t reserved_22_31:10;
+                uint64_t grp:6;
+                uint64_t reserved_10_15:6;
+                uint64_t tt:2;
+                uint64_t reserved_3_7:5;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t reserved_3_7:5;
+                uint64_t tt:2;
+                uint64_t reserved_10_15:6;
+                uint64_t grp:6;
+                uint64_t reserved_22_31:10;
+                uint64_t tag:8;
+                uint64_t reserved_40_59:20;
+                uint64_t qos_en:1;
+                uint64_t tt_en:1;
+                uint64_t grp_en:1;
+                uint64_t tag_en:1;
+#endif
+        } s;
+        struct cvmx_pip_bsel_tbl_entx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t tag_en:1;
+                uint64_t grp_en:1;
+                uint64_t tt_en:1;
+                uint64_t qos_en:1;
+                uint64_t reserved_40_59:20;
+                uint64_t tag:8;
+                uint64_t reserved_20_31:12;
+                uint64_t grp:4;
+                uint64_t reserved_10_15:6;
+                uint64_t tt:2;
+                uint64_t reserved_3_7:5;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t reserved_3_7:5;
+                uint64_t tt:2;
+                uint64_t reserved_10_15:6;
+                uint64_t grp:4;
+                uint64_t reserved_20_31:12;
+                uint64_t tag:8;
+                uint64_t reserved_40_59:20;
+                uint64_t qos_en:1;
+                uint64_t tt_en:1;
+                uint64_t grp_en:1;
+                uint64_t tag_en:1;
+#endif
+        } cn61xx;
+};
+
+union cvmx_pip_clken {
+        uint64_t u64;
+        struct cvmx_pip_clken_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t clken:1;
+#else
+                uint64_t clken:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_pip_crc_ctlx {
+        uint64_t u64;
+        struct cvmx_pip_crc_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t invres:1;
+                uint64_t reflect:1;
+#else
+                uint64_t reflect:1;
+                uint64_t invres:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pip_crc_ivx {
+        uint64_t u64;
+        struct cvmx_pip_crc_ivx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iv:32;
+#else
+                uint64_t iv:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_dec_ipsecx {
+        uint64_t u64;
+        struct cvmx_pip_dec_ipsecx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t tcp:1;
+                uint64_t udp:1;
+                uint64_t dprt:16;
+#else
+                uint64_t dprt:16;
+                uint64_t udp:1;
+                uint64_t tcp:1;
+                uint64_t reserved_18_63:46;
+#endif
+        } s;
+};
+
+union cvmx_pip_dsa_src_grp {
+        uint64_t u64;
+        struct cvmx_pip_dsa_src_grp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t map15:4;
+                uint64_t map14:4;
+                uint64_t map13:4;
+                uint64_t map12:4;
+                uint64_t map11:4;
+                uint64_t map10:4;
+                uint64_t map9:4;
+                uint64_t map8:4;
+                uint64_t map7:4;
+                uint64_t map6:4;
+                uint64_t map5:4;
+                uint64_t map4:4;
+                uint64_t map3:4;
+                uint64_t map2:4;
+                uint64_t map1:4;
+                uint64_t map0:4;
+#else
+                uint64_t map0:4;
+                uint64_t map1:4;
+                uint64_t map2:4;
+                uint64_t map3:4;
+                uint64_t map4:4;
+                uint64_t map5:4;
+                uint64_t map6:4;
+                uint64_t map7:4;
+                uint64_t map8:4;
+                uint64_t map9:4;
+                uint64_t map10:4;
+                uint64_t map11:4;
+                uint64_t map12:4;
+                uint64_t map13:4;
+                uint64_t map14:4;
+                uint64_t map15:4;
+#endif
+        } s;
+};
+
+union cvmx_pip_dsa_vid_grp {
+        uint64_t u64;
+        struct cvmx_pip_dsa_vid_grp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t map15:4;
+                uint64_t map14:4;
+                uint64_t map13:4;
+                uint64_t map12:4;
+                uint64_t map11:4;
+                uint64_t map10:4;
+                uint64_t map9:4;
+                uint64_t map8:4;
+                uint64_t map7:4;
+                uint64_t map6:4;
+                uint64_t map5:4;
+                uint64_t map4:4;
+                uint64_t map3:4;
+                uint64_t map2:4;
+                uint64_t map1:4;
+                uint64_t map0:4;
+#else
+                uint64_t map0:4;
+                uint64_t map1:4;
+                uint64_t map2:4;
+                uint64_t map3:4;
+                uint64_t map4:4;
+                uint64_t map5:4;
+                uint64_t map6:4;
+                uint64_t map7:4;
+                uint64_t map8:4;
+                uint64_t map9:4;
+                uint64_t map10:4;
+                uint64_t map11:4;
+                uint64_t map12:4;
+                uint64_t map13:4;
+                uint64_t map14:4;
+                uint64_t map15:4;
+#endif
+        } s;
+};
+
+union cvmx_pip_frm_len_chkx {
+        uint64_t u64;
+        struct cvmx_pip_frm_len_chkx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t maxlen:16;
+                uint64_t minlen:16;
+#else
+                uint64_t minlen:16;
+                uint64_t maxlen:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_gbl_cfg {
+        uint64_t u64;
+        struct cvmx_pip_gbl_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t tag_syn:1;
+                uint64_t ip6_udp:1;
+                uint64_t max_l2:1;
+                uint64_t reserved_11_15:5;
+                uint64_t raw_shf:3;
+                uint64_t reserved_3_7:5;
+                uint64_t nip_shf:3;
+#else
+                uint64_t nip_shf:3;
+                uint64_t reserved_3_7:5;
+                uint64_t raw_shf:3;
+                uint64_t reserved_11_15:5;
+                uint64_t max_l2:1;
+                uint64_t ip6_udp:1;
+                uint64_t tag_syn:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } s;
+};
+
+union cvmx_pip_gbl_ctl {
+        uint64_t u64;
+        struct cvmx_pip_gbl_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t egrp_dis:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_21_23:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_21_23:3;
+                uint64_t dsa_grp_sid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t egrp_dis:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+        struct cvmx_pip_gbl_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn30xx;
+        struct cvmx_pip_gbl_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_21_23:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_21_23:3;
+                uint64_t dsa_grp_sid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } cn52xx;
+        struct cvmx_pip_gbl_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_21_63:43;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_21_63:43;
+#endif
+        } cn56xxp1;
+        struct cvmx_pip_gbl_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t ihmsk_dis:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_21_23:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_21_23:3;
+                uint64_t dsa_grp_sid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn61xx;
+        struct cvmx_pip_gbl_ctl_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t egrp_dis:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_17_23:7;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_23:7;
+                uint64_t dsa_grp_sid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t egrp_dis:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn68xx;
+        struct cvmx_pip_gbl_ctl_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t ihmsk_dis:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_17_23:7;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+#else
+                uint64_t ip_chk:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_hop:1;
+                uint64_t ip4_opts:1;
+                uint64_t ip6_eext:2;
+                uint64_t reserved_6_7:2;
+                uint64_t l4_mal:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_len:1;
+                uint64_t tcp_flag:1;
+                uint64_t l2_mal:1;
+                uint64_t vs_qos:1;
+                uint64_t vs_wqe:1;
+                uint64_t ignrs:1;
+                uint64_t reserved_17_23:7;
+                uint64_t dsa_grp_sid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t ihmsk_dis:1;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn68xxp1;
+};
+
+union cvmx_pip_hg_pri_qos {
+        uint64_t u64;
+        struct cvmx_pip_hg_pri_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t up_qos:1;
+                uint64_t reserved_11_11:1;
+                uint64_t qos:3;
+                uint64_t reserved_6_7:2;
+                uint64_t pri:6;
+#else
+                uint64_t pri:6;
+                uint64_t reserved_6_7:2;
+                uint64_t qos:3;
+                uint64_t reserved_11_11:1;
+                uint64_t up_qos:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+};
+
+union cvmx_pip_int_en {
+        uint64_t u64;
+        struct cvmx_pip_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_pip_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn30xx;
+        struct cvmx_pip_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn50xx;
+        struct cvmx_pip_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn52xx;
+        struct cvmx_pip_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn56xxp1;
+        struct cvmx_pip_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn58xx;
+};
+
+union cvmx_pip_int_reg {
+        uint64_t u64;
+        struct cvmx_pip_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+        struct cvmx_pip_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn30xx;
+        struct cvmx_pip_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn50xx;
+        struct cvmx_pip_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t reserved_1_1:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn52xx;
+        struct cvmx_pip_int_reg_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t minerr:1;
+                uint64_t maxerr:1;
+                uint64_t lenerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn56xxp1;
+        struct cvmx_pip_int_reg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+#else
+                uint64_t pktdrp:1;
+                uint64_t crcerr:1;
+                uint64_t bckprs:1;
+                uint64_t prtnxa:1;
+                uint64_t badtag:1;
+                uint64_t skprunt:1;
+                uint64_t todoovr:1;
+                uint64_t feperr:1;
+                uint64_t beperr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t punyerr:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } cn58xx;
+};
+
+union cvmx_pip_ip_offset {
+        uint64_t u64;
+        struct cvmx_pip_ip_offset_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t offset:3;
+#else
+                uint64_t offset:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_pip_pri_tblx {
+        uint64_t u64;
+        struct cvmx_pip_pri_tblx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t diff2_padd:8;
+                uint64_t hg2_padd:8;
+                uint64_t vlan2_padd:8;
+                uint64_t reserved_38_39:2;
+                uint64_t diff2_bpid:6;
+                uint64_t reserved_30_31:2;
+                uint64_t hg2_bpid:6;
+                uint64_t reserved_22_23:2;
+                uint64_t vlan2_bpid:6;
+                uint64_t reserved_11_15:5;
+                uint64_t diff2_qos:3;
+                uint64_t reserved_7_7:1;
+                uint64_t hg2_qos:3;
+                uint64_t reserved_3_3:1;
+                uint64_t vlan2_qos:3;
+#else
+                uint64_t vlan2_qos:3;
+                uint64_t reserved_3_3:1;
+                uint64_t hg2_qos:3;
+                uint64_t reserved_7_7:1;
+                uint64_t diff2_qos:3;
+                uint64_t reserved_11_15:5;
+                uint64_t vlan2_bpid:6;
+                uint64_t reserved_22_23:2;
+                uint64_t hg2_bpid:6;
+                uint64_t reserved_30_31:2;
+                uint64_t diff2_bpid:6;
+                uint64_t reserved_38_39:2;
+                uint64_t vlan2_padd:8;
+                uint64_t hg2_padd:8;
+                uint64_t diff2_padd:8;
+#endif
+        } s;
+};
+
+union cvmx_pip_prt_cfgx {
+        uint64_t u64;
+        struct cvmx_pip_prt_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t ih_pri:1;
+                uint64_t len_chk_sel:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t hg_qos:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t qos_vsel:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t higig_en:1;
+                uint64_t dsa_en:1;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t dsa_en:1;
+                uint64_t higig_en:1;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_vsel:1;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t hg_qos:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_39:3;
+                uint64_t qos_wat_47:4;
+                uint64_t grp_wat_47:4;
+                uint64_t minerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t lenerr_en:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t len_chk_sel:1;
+                uint64_t ih_pri:1;
+                uint64_t reserved_55_63:9;
+#endif
+        } s;
+        struct cvmx_pip_prt_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_10_15:6;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t reserved_10_15:6;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t reserved_27_27:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn30xx;
+        struct cvmx_pip_prt_cfgx_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t reserved_10_11:2;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t reserved_27_27:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn38xx;
+        struct cvmx_pip_prt_cfgx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_53_63:11;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t reserved_10_11:2;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vod:1;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t reserved_27_27:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_39:3;
+                uint64_t qos_wat_47:4;
+                uint64_t grp_wat_47:4;
+                uint64_t minerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t lenerr_en:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t reserved_53_63:11;
+#endif
+        } cn50xx;
+        struct cvmx_pip_prt_cfgx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_53_63:11;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t hg_qos:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t qos_vsel:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t higig_en:1;
+                uint64_t dsa_en:1;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t dsa_en:1;
+                uint64_t higig_en:1;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_vsel:1;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t hg_qos:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_39:3;
+                uint64_t qos_wat_47:4;
+                uint64_t grp_wat_47:4;
+                uint64_t minerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t lenerr_en:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t reserved_53_63:11;
+#endif
+        } cn52xx;
+        struct cvmx_pip_prt_cfgx_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t reserved_10_11:2;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vod:1;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t reserved_27_27:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn58xx;
+        struct cvmx_pip_prt_cfgx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t ih_pri:1;
+                uint64_t len_chk_sel:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t hg_qos:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t higig_en:1;
+                uint64_t dsa_en:1;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+#else
+                uint64_t skip:7;
+                uint64_t reserved_7_7:1;
+                uint64_t mode:2;
+                uint64_t dsa_en:1;
+                uint64_t higig_en:1;
+                uint64_t crc_en:1;
+                uint64_t reserved_13_15:3;
+                uint64_t qos_vlan:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vod:1;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_wat:4;
+                uint64_t qos:3;
+                uint64_t hg_qos:1;
+                uint64_t grp_wat:4;
+                uint64_t inst_hdr:1;
+                uint64_t dyn_rs:1;
+                uint64_t tag_inc:2;
+                uint64_t rawdrp:1;
+                uint64_t reserved_37_39:3;
+                uint64_t qos_wat_47:4;
+                uint64_t grp_wat_47:4;
+                uint64_t minerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t lenerr_en:1;
+                uint64_t vlan_len:1;
+                uint64_t pad_len:1;
+                uint64_t len_chk_sel:1;
+                uint64_t ih_pri:1;
+                uint64_t reserved_55_63:9;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pip_prt_cfgbx {
+        uint64_t u64;
+        struct cvmx_pip_prt_cfgbx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t alt_skp_sel:2;
+                uint64_t alt_skp_en:1;
+                uint64_t reserved_35_35:1;
+                uint64_t bsel_num:2;
+                uint64_t bsel_en:1;
+                uint64_t reserved_24_31:8;
+                uint64_t base:8;
+                uint64_t reserved_6_15:10;
+                uint64_t bpid:6;
+#else
+                uint64_t bpid:6;
+                uint64_t reserved_6_15:10;
+                uint64_t base:8;
+                uint64_t reserved_24_31:8;
+                uint64_t bsel_en:1;
+                uint64_t bsel_num:2;
+                uint64_t reserved_35_35:1;
+                uint64_t alt_skp_en:1;
+                uint64_t alt_skp_sel:2;
+                uint64_t reserved_39_63:25;
+#endif
+        } s;
+        struct cvmx_pip_prt_cfgbx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t alt_skp_sel:2;
+                uint64_t alt_skp_en:1;
+                uint64_t reserved_35_35:1;
+                uint64_t bsel_num:2;
+                uint64_t bsel_en:1;
+                uint64_t reserved_0_31:32;
+#else
+                uint64_t reserved_0_31:32;
+                uint64_t bsel_en:1;
+                uint64_t bsel_num:2;
+                uint64_t reserved_35_35:1;
+                uint64_t alt_skp_en:1;
+                uint64_t alt_skp_sel:2;
+                uint64_t reserved_39_63:25;
+#endif
+        } cn61xx;
+        struct cvmx_pip_prt_cfgbx_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                uint64_t alt_skp_sel:2;
+                uint64_t alt_skp_en:1;
+                uint64_t reserved_0_35:36;
+#else
+                uint64_t reserved_0_35:36;
+                uint64_t alt_skp_en:1;
+                uint64_t alt_skp_sel:2;
+                uint64_t reserved_39_63:25;
+#endif
+        } cn66xx;
+        struct cvmx_pip_prt_cfgbx_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t base:8;
+                uint64_t reserved_6_15:10;
+                uint64_t bpid:6;
+#else
+                uint64_t bpid:6;
+                uint64_t reserved_6_15:10;
+                uint64_t base:8;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn68xxp1;
+};
+
+union cvmx_pip_prt_tagx {
+        uint64_t u64;
+        struct cvmx_pip_prt_tagx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t portadd_en:1;
+                uint64_t inc_hwchk:1;
+                uint64_t reserved_50_51:2;
+                uint64_t grptagbase_msb:2;
+                uint64_t reserved_46_47:2;
+                uint64_t grptagmask_msb:2;
+                uint64_t reserved_42_43:2;
+                uint64_t grp_msb:2;
+                uint64_t grptagbase:4;
+                uint64_t grptagmask:4;
+                uint64_t grptag:1;
+                uint64_t grptag_mskip:1;
+                uint64_t tag_mode:2;
+                uint64_t inc_vs:2;
+                uint64_t inc_vlan:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_src_flag:1;
+                uint64_t tcp6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t non_tag_type:2;
+                uint64_t grp:4;
+#else
+                uint64_t grp:4;
+                uint64_t non_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t tcp6_tag_type:2;
+                uint64_t ip4_src_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t inc_vlan:1;
+                uint64_t inc_vs:2;
+                uint64_t tag_mode:2;
+                uint64_t grptag_mskip:1;
+                uint64_t grptag:1;
+                uint64_t grptagmask:4;
+                uint64_t grptagbase:4;
+                uint64_t grp_msb:2;
+                uint64_t reserved_42_43:2;
+                uint64_t grptagmask_msb:2;
+                uint64_t reserved_46_47:2;
+                uint64_t grptagbase_msb:2;
+                uint64_t reserved_50_51:2;
+                uint64_t inc_hwchk:1;
+                uint64_t portadd_en:1;
+                uint64_t reserved_54_63:10;
+#endif
+        } s;
+        struct cvmx_pip_prt_tagx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t grptagbase:4;
+                uint64_t grptagmask:4;
+                uint64_t grptag:1;
+                uint64_t reserved_30_30:1;
+                uint64_t tag_mode:2;
+                uint64_t inc_vs:2;
+                uint64_t inc_vlan:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_src_flag:1;
+                uint64_t tcp6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t non_tag_type:2;
+                uint64_t grp:4;
+#else
+                uint64_t grp:4;
+                uint64_t non_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t tcp6_tag_type:2;
+                uint64_t ip4_src_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t inc_vlan:1;
+                uint64_t inc_vs:2;
+                uint64_t tag_mode:2;
+                uint64_t reserved_30_30:1;
+                uint64_t grptag:1;
+                uint64_t grptagmask:4;
+                uint64_t grptagbase:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } cn30xx;
+        struct cvmx_pip_prt_tagx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t grptagbase:4;
+                uint64_t grptagmask:4;
+                uint64_t grptag:1;
+                uint64_t grptag_mskip:1;
+                uint64_t tag_mode:2;
+                uint64_t inc_vs:2;
+                uint64_t inc_vlan:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_src_flag:1;
+                uint64_t tcp6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t non_tag_type:2;
+                uint64_t grp:4;
+#else
+                uint64_t grp:4;
+                uint64_t non_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t tcp6_tag_type:2;
+                uint64_t ip4_src_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t inc_vlan:1;
+                uint64_t inc_vs:2;
+                uint64_t tag_mode:2;
+                uint64_t grptag_mskip:1;
+                uint64_t grptag:1;
+                uint64_t grptagmask:4;
+                uint64_t grptagbase:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pip_qos_diffx {
+        uint64_t u64;
+        struct cvmx_pip_qos_diffx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_pip_qos_vlanx {
+        uint64_t u64;
+        struct cvmx_pip_qos_vlanx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t qos1:3;
+                uint64_t reserved_3_3:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t reserved_3_3:1;
+                uint64_t qos1:3;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+        struct cvmx_pip_qos_vlanx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn30xx;
+};
+
+union cvmx_pip_qos_watchx {
+        uint64_t u64;
+        struct cvmx_pip_qos_watchx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t mask:16;
+                uint64_t reserved_30_31:2;
+                uint64_t grp:6;
+                uint64_t reserved_23_23:1;
+                uint64_t qos:3;
+                uint64_t reserved_19_19:1;
+                uint64_t match_type:3;
+                uint64_t match_value:16;
+#else
+                uint64_t match_value:16;
+                uint64_t match_type:3;
+                uint64_t reserved_19_19:1;
+                uint64_t qos:3;
+                uint64_t reserved_23_23:1;
+                uint64_t grp:6;
+                uint64_t reserved_30_31:2;
+                uint64_t mask:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_pip_qos_watchx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t mask:16;
+                uint64_t reserved_28_31:4;
+                uint64_t grp:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos:3;
+                uint64_t reserved_18_19:2;
+                uint64_t match_type:2;
+                uint64_t match_value:16;
+#else
+                uint64_t match_value:16;
+                uint64_t match_type:2;
+                uint64_t reserved_18_19:2;
+                uint64_t qos:3;
+                uint64_t reserved_23_23:1;
+                uint64_t grp:4;
+                uint64_t reserved_28_31:4;
+                uint64_t mask:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn30xx;
+        struct cvmx_pip_qos_watchx_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t mask:16;
+                uint64_t reserved_28_31:4;
+                uint64_t grp:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos:3;
+                uint64_t reserved_19_19:1;
+                uint64_t match_type:3;
+                uint64_t match_value:16;
+#else
+                uint64_t match_value:16;
+                uint64_t match_type:3;
+                uint64_t reserved_19_19:1;
+                uint64_t qos:3;
+                uint64_t reserved_23_23:1;
+                uint64_t grp:4;
+                uint64_t reserved_28_31:4;
+                uint64_t mask:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pip_raw_word {
+        uint64_t u64;
+        struct cvmx_pip_raw_word_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t word:56;
+#else
+                uint64_t word:56;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+};
+
+union cvmx_pip_sft_rst {
+        uint64_t u64;
+        struct cvmx_pip_sft_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t rst:1;
+#else
+                uint64_t rst:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat0_x {
+        uint64_t u64;
+        struct cvmx_pip_stat0_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t drp_pkts:32;
+                uint64_t drp_octs:32;
+#else
+                uint64_t drp_octs:32;
+                uint64_t drp_pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat0_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat0_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t drp_pkts:32;
+                uint64_t drp_octs:32;
+#else
+                uint64_t drp_octs:32;
+                uint64_t drp_pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat10_x {
+        uint64_t u64;
+        struct cvmx_pip_stat10_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat10_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat10_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat11_x {
+        uint64_t u64;
+        struct cvmx_pip_stat11_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat11_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat11_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat1_x {
+        uint64_t u64;
+        struct cvmx_pip_stat1_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat1_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat1_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat2_x {
+        uint64_t u64;
+        struct cvmx_pip_stat2_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pkts:32;
+                uint64_t raw:32;
+#else
+                uint64_t raw:32;
+                uint64_t pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat2_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat2_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pkts:32;
+                uint64_t raw:32;
+#else
+                uint64_t raw:32;
+                uint64_t pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat3_x {
+        uint64_t u64;
+        struct cvmx_pip_stat3_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcst:32;
+                uint64_t mcst:32;
+#else
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat3_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat3_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcst:32;
+                uint64_t mcst:32;
+#else
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat4_x {
+        uint64_t u64;
+        struct cvmx_pip_stat4_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h65to127:32;
+                uint64_t h64:32;
+#else
+                uint64_t h64:32;
+                uint64_t h65to127:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat4_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat4_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h65to127:32;
+                uint64_t h64:32;
+#else
+                uint64_t h64:32;
+                uint64_t h65to127:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat5_x {
+        uint64_t u64;
+        struct cvmx_pip_stat5_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h256to511:32;
+                uint64_t h128to255:32;
+#else
+                uint64_t h128to255:32;
+                uint64_t h256to511:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat5_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat5_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h256to511:32;
+                uint64_t h128to255:32;
+#else
+                uint64_t h128to255:32;
+                uint64_t h256to511:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat6_x {
+        uint64_t u64;
+        struct cvmx_pip_stat6_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h1024to1518:32;
+                uint64_t h512to1023:32;
+#else
+                uint64_t h512to1023:32;
+                uint64_t h1024to1518:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat6_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat6_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h1024to1518:32;
+                uint64_t h512to1023:32;
+#else
+                uint64_t h512to1023:32;
+                uint64_t h1024to1518:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat7_x {
+        uint64_t u64;
+        struct cvmx_pip_stat7_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fcs:32;
+                uint64_t h1519:32;
+#else
+                uint64_t h1519:32;
+                uint64_t fcs:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat7_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat7_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fcs:32;
+                uint64_t h1519:32;
+#else
+                uint64_t h1519:32;
+                uint64_t fcs:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat8_x {
+        uint64_t u64;
+        struct cvmx_pip_stat8_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t frag:32;
+                uint64_t undersz:32;
+#else
+                uint64_t undersz:32;
+                uint64_t frag:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat8_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat8_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t frag:32;
+                uint64_t undersz:32;
+#else
+                uint64_t undersz:32;
+                uint64_t frag:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat9_x {
+        uint64_t u64;
+        struct cvmx_pip_stat9_x_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t jabber:32;
+                uint64_t oversz:32;
+#else
+                uint64_t oversz:32;
+                uint64_t jabber:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat9_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat9_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t jabber:32;
+                uint64_t oversz:32;
+#else
+                uint64_t oversz:32;
+                uint64_t jabber:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_ctl {
+        uint64_t u64;
+        struct cvmx_pip_stat_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t mode:1;
+                uint64_t reserved_1_7:7;
+                uint64_t rdclr:1;
+#else
+                uint64_t rdclr:1;
+                uint64_t reserved_1_7:7;
+                uint64_t mode:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+        struct cvmx_pip_stat_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t rdclr:1;
+#else
+                uint64_t rdclr:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } cn30xx;
+};
+
+union cvmx_pip_stat_inb_errsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_errsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t errs:16;
+#else
+                uint64_t errs:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_inb_errs_pkndx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_errs_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t errs:16;
+#else
+                uint64_t errs:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_inb_octsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_octsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_inb_octs_pkndx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_octs_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_inb_pktsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_pktsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+#else
+                uint64_t pkts:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_stat_inb_pkts_pkndx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_pkts_pkndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+#else
+                uint64_t pkts:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_sub_pkind_fcsx {
+        uint64_t u64;
+        struct cvmx_pip_sub_pkind_fcsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t port_bit:64;
+#else
+                uint64_t port_bit:64;
+#endif
+        } s;
+};
+
+union cvmx_pip_tag_incx {
+        uint64_t u64;
+        struct cvmx_pip_tag_incx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pip_tag_mask {
+        uint64_t u64;
+        struct cvmx_pip_tag_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+#else
+                uint64_t mask:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pip_tag_secret {
+        uint64_t u64;
+        struct cvmx_pip_tag_secret_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t dst:16;
+                uint64_t src:16;
+#else
+                uint64_t src:16;
+                uint64_t dst:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_todo_entry {
+        uint64_t u64;
+        struct cvmx_pip_todo_entry_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t val:1;
+                uint64_t reserved_62_62:1;
+                uint64_t entry:62;
+#else
+                uint64_t entry:62;
+                uint64_t reserved_62_62:1;
+                uint64_t val:1;
+#endif
+        } s;
+};
+
+union cvmx_pip_vlan_etypesx {
+        uint64_t u64;
+        struct cvmx_pip_vlan_etypesx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t type3:16;
+                uint64_t type2:16;
+                uint64_t type1:16;
+                uint64_t type0:16;
+#else
+                uint64_t type0:16;
+                uint64_t type1:16;
+                uint64_t type2:16;
+                uint64_t type3:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat0_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat0_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t drp_pkts:32;
+                uint64_t drp_octs:32;
+#else
+                uint64_t drp_octs:32;
+                uint64_t drp_pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat10_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat10_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat11_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat11_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcast:32;
+                uint64_t mcast:32;
+#else
+                uint64_t mcast:32;
+                uint64_t bcast:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat1_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat1_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+#else
+                uint64_t octs:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat2_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat2_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t pkts:32;
+                uint64_t raw:32;
+#else
+                uint64_t raw:32;
+                uint64_t pkts:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat3_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat3_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bcst:32;
+                uint64_t mcst:32;
+#else
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat4_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat4_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h65to127:32;
+                uint64_t h64:32;
+#else
+                uint64_t h64:32;
+                uint64_t h65to127:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat5_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat5_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h256to511:32;
+                uint64_t h128to255:32;
+#else
+                uint64_t h128to255:32;
+                uint64_t h256to511:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat6_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat6_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t h1024to1518:32;
+                uint64_t h512to1023:32;
+#else
+                uint64_t h512to1023:32;
+                uint64_t h1024to1518:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat7_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat7_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fcs:32;
+                uint64_t h1519:32;
+#else
+                uint64_t h1519:32;
+                uint64_t fcs:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat8_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat8_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t frag:32;
+                uint64_t undersz:32;
+#else
+                uint64_t undersz:32;
+                uint64_t frag:32;
+#endif
+        } s;
+};
+
+union cvmx_pip_xstat9_prtx {
+        uint64_t u64;
+        struct cvmx_pip_xstat9_prtx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t jabber:32;
+                uint64_t oversz:32;
+#else
+                uint64_t oversz:32;
+                uint64_t jabber:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
new file mode 100644
index 000000000..01ca7267a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
@@ -0,0 +1,524 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Interface to the hardware Packet Input Processing unit.
+ *
+ */
+
+#ifndef __CVMX_PIP_H__
+#define __CVMX_PIP_H__
+
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip-defs.h>
+
+#define CVMX_PIP_NUM_INPUT_PORTS                48
+#define CVMX_PIP_NUM_WATCHERS                   4
+
+/*
+ * Encodes the different error and exception codes
+ */
+typedef enum {
+        CVMX_PIP_L4_NO_ERR = 0ull,
+        /*
+         * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
+         * header
+         */
+        CVMX_PIP_L4_MAL_ERR = 1ull,
+        /* 2  = TCP/UDP checksum failure */
+        CVMX_PIP_CHK_ERR = 2ull,
+        /*
+         * 3 = TCP/UDP length check (TCP/UDP length does not match IP
+         * length).
+         */
+        CVMX_PIP_L4_LENGTH_ERR = 3ull,
+        /* 4  = illegal TCP/UDP port (either source or dest port is zero) */
+        CVMX_PIP_BAD_PRT_ERR = 4ull,
+        /* 8  = TCP flags = FIN only */
+        CVMX_PIP_TCP_FLG8_ERR = 8ull,
+        /* 9  = TCP flags = 0 */
+        CVMX_PIP_TCP_FLG9_ERR = 9ull,
+        /* 10 = TCP flags = FIN+RST+* */
+        CVMX_PIP_TCP_FLG10_ERR = 10ull,
+        /* 11 = TCP flags = SYN+URG+* */
+        CVMX_PIP_TCP_FLG11_ERR = 11ull,
+        /* 12 = TCP flags = SYN+RST+* */
+        CVMX_PIP_TCP_FLG12_ERR = 12ull,
+        /* 13 = TCP flags = SYN+FIN+* */
+        CVMX_PIP_TCP_FLG13_ERR = 13ull
+} cvmx_pip_l4_err_t;
+
+typedef enum {
+
+        CVMX_PIP_IP_NO_ERR = 0ull,
+        /* 1 = not IPv4 or IPv6 */
+        CVMX_PIP_NOT_IP = 1ull,
+        /* 2 = IPv4 header checksum violation */
+        CVMX_PIP_IPV4_HDR_CHK = 2ull,
+        /* 3 = malformed (packet not long enough to cover IP hdr) */
+        CVMX_PIP_IP_MAL_HDR = 3ull,
+        /* 4 = malformed (packet not long enough to cover len in IP hdr) */
+        CVMX_PIP_IP_MAL_PKT = 4ull,
+        /* 5 = TTL / hop count equal zero */
+        CVMX_PIP_TTL_HOP = 5ull,
+        /* 6 = IPv4 options / IPv6 early extension headers */
+        CVMX_PIP_OPTS = 6ull
+} cvmx_pip_ip_exc_t;
+
+/**
+ * NOTES
+ *       late collision (data received before collision)
+ *            late collisions cannot be detected by the receiver
+ *            they would appear as JAM bits which would appear as bad FCS
+ *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+ */
+typedef enum {
+        /* No error */
+        CVMX_PIP_RX_NO_ERR = 0ull,
+        /* RGM+SPI 1 = partially received packet (buffering/bandwidth
+         * not adequate) */
+        CVMX_PIP_PARTIAL_ERR = 1ull,
+        /* RGM+SPI 2 = receive packet too large and truncated */
+        CVMX_PIP_JABBER_ERR = 2ull,
+        /*
+         * RGM 3 = max frame error (pkt len > max frame len) (with FCS
+         * error)
+         */
+        CVMX_PIP_OVER_FCS_ERR = 3ull,
+        /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
+        CVMX_PIP_OVER_ERR = 4ull,
+        /*
+         * RGM 5 = nibble error (data not byte multiple - 100M and 10M
+         * only)
+         */
+        CVMX_PIP_ALIGN_ERR = 5ull,
+        /*
+         * RGM 6 = min frame error (pkt len < min frame len) (with FCS
+         * error)
+         */
+        CVMX_PIP_UNDER_FCS_ERR = 6ull,
+        /* RGM     7 = FCS error */
+        CVMX_PIP_GMX_FCS_ERR = 7ull,
+        /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
+        CVMX_PIP_UNDER_ERR = 8ull,
+        /* RGM     9 = Frame carrier extend error */
+        CVMX_PIP_EXTEND_ERR = 9ull,
+        /*
+         * RGM 10 = length mismatch (len did not match len in L2
+         * length/type)
+         */
+        CVMX_PIP_LENGTH_ERR = 10ull,
+        /* RGM 11 = Frame error (some or all data bits marked err) */
+        CVMX_PIP_DAT_ERR = 11ull,
+        /*     SPI 11 = DIP4 error */
+        CVMX_PIP_DIP_ERR = 11ull,
+        /*
+         * RGM 12 = packet was not large enough to pass the skipper -
+         * no inspection could occur.
+         */
+        CVMX_PIP_SKIP_ERR = 12ull,
+        /*
+         * RGM 13 = studder error (data not repeated - 100M and 10M
+         * only)
+         */
+        CVMX_PIP_NIBBLE_ERR = 13ull,
+        /* RGM+SPI 16 = FCS error */
+        CVMX_PIP_PIP_FCS = 16L,
+        /*
+         * RGM+SPI+PCI 17 = packet was not large enough to pass the
+         * skipper - no inspection could occur.
+         */
+        CVMX_PIP_PIP_SKIP_ERR = 17L,
+        /*
+         * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
+         * cover L2 hdr).
+         */
+        CVMX_PIP_PIP_L2_MAL_HDR = 18L
+        /*
+         * NOTES: xx = late collision (data received before collision)
+         *       late collisions cannot be detected by the receiver
+         *       they would appear as JAM bits which would appear as
+         *       bad FCS or carrier extend error which is
+         *       CVMX_PIP_EXTEND_ERR
+         */
+} cvmx_pip_rcv_err_t;
+
+/**
+ * This defines the err_code field errors in the work Q entry
+ */
+typedef union {
+        cvmx_pip_l4_err_t l4_err;
+        cvmx_pip_ip_exc_t ip_exc;
+        cvmx_pip_rcv_err_t rcv_err;
+} cvmx_pip_err_t;
+
+/**
+ * Status statistics for a port
+ */
+typedef struct {
+        /* Inbound octets marked to be dropped by the IPD */
+        uint32_t dropped_octets;
+        /* Inbound packets marked to be dropped by the IPD */
+        uint32_t dropped_packets;
+        /* RAW PCI Packets received by PIP per port */
+        uint32_t pci_raw_packets;
+        /* Number of octets processed by PIP */
+        uint32_t octets;
+        /* Number of packets processed by PIP */
+        uint32_t packets;
+        /*
+         * Number of identified L2 multicast packets.   Does not
+         * include broadcast packets.  Only includes packets whose
+         * parse mode is SKIP_TO_L2
+         */
+        uint32_t multicast_packets;
+        /*
+         * Number of identified L2 broadcast packets.   Does not
+         * include multicast packets.  Only includes packets whose
+         * parse mode is SKIP_TO_L2
+         */
+        uint32_t broadcast_packets;
+        /* Number of 64B packets */
+        uint32_t len_64_packets;
+        /* Number of 65-127B packets */
+        uint32_t len_65_127_packets;
+        /* Number of 128-255B packets */
+        uint32_t len_128_255_packets;
+        /* Number of 256-511B packets */
+        uint32_t len_256_511_packets;
+        /* Number of 512-1023B packets */
+        uint32_t len_512_1023_packets;
+        /* Number of 1024-1518B packets */
+        uint32_t len_1024_1518_packets;
+        /* Number of 1519-max packets */
+        uint32_t len_1519_max_packets;
+        /* Number of packets with FCS or Align opcode errors */
+        uint32_t fcs_align_err_packets;
+        /* Number of packets with length < min */
+        uint32_t runt_packets;
+        /* Number of packets with length < min and FCS error */
+        uint32_t runt_crc_packets;
+        /* Number of packets with length > max */
+        uint32_t oversize_packets;
+        /* Number of packets with length > max and FCS error */
+        uint32_t oversize_crc_packets;
+        /* Number of packets without GMX/SPX/PCI errors received by PIP */
+        uint32_t inb_packets;
+        /*
+         * Total number of octets from all packets received by PIP,
+         * including CRC
+         */
+        uint64_t inb_octets;
+        /* Number of packets with GMX/SPX/PCI errors received by PIP */
+        uint16_t inb_errors;
+} cvmx_pip_port_status_t;
+
+/**
+ * Definition of the PIP custom header that can be prepended
+ * to a packet by external hardware.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /*
+                 * Documented as R - Set if the Packet is RAWFULL. If
+                 * set, this header must be the full 8 bytes.
+                 */
+                uint64_t rawfull:1;
+                /* Must be zero */
+                uint64_t reserved0:5;
+                /* PIP parse mode for this packet */
+                uint64_t parse_mode:2;
+                /* Must be zero */
+                uint64_t reserved1:1;
+                /*
+                 * Skip amount, including this header, to the
+                 * beginning of the packet
+                 */
+                uint64_t skip_len:7;
+                /* Must be zero */
+                uint64_t reserved2:6;
+                /* POW input queue for this packet */
+                uint64_t qos:3;
+                /* POW input group for this packet */
+                uint64_t grp:4;
+                /*
+                 * Flag to store this packet in the work queue entry,
+                 * if possible
+                 */
+                uint64_t rs:1;
+                /* POW input tag type */
+                uint64_t tag_type:2;
+                /* POW input tag */
+                uint64_t tag:32;
+        } s;
+} cvmx_pip_pkt_inst_hdr_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Configure an ethernet input port
+ *
+ * @port_num: Port number to configure
+ * @port_cfg: Port hardware configuration
+ * @port_tag_cfg:
+ *                 Port POW tagging configuration
+ */
+static inline void cvmx_pip_config_port(uint64_t port_num,
+                                        union cvmx_pip_prt_cfgx port_cfg,
+                                        union cvmx_pip_prt_tagx port_tag_cfg)
+{
+        cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
+        cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
+}
+#if 0
+/**
+ * @deprecated      This function is a thin wrapper around the Pass1 version
+ *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
+ *                  setting the group that is incompatible with this function,
+ *                  the preferred upgrade path is to use the CSR directly.
+ *
+ * Configure the global QoS packet watchers. Each watcher is
+ * capable of matching a field in a packet to determine the
+ * QoS queue for scheduling.
+ *
+ * @watcher:    Watcher number to configure (0 - 3).
+ * @match_type: Watcher match type
+ * @match_value:
+ *                   Value the watcher will match against
+ * @qos:        QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_watcher(uint64_t watcher,
+                                           cvmx_pip_qos_watch_types match_type,
+                                           uint64_t match_value, uint64_t qos)
+{
+        cvmx_pip_port_watcher_cfg_t watcher_config;
+
+        watcher_config.u64 = 0;
+        watcher_config.s.match_type = match_type;
+        watcher_config.s.match_value = match_value;
+        watcher_config.s.qos = qos;
+
+        cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
+}
+#endif
+/**
+ * Configure the VLAN priority to QoS queue mapping.
+ *
+ * @vlan_priority:
+ *               VLAN priority (0-7)
+ * @qos:    QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
+                                            uint64_t qos)
+{
+        union cvmx_pip_qos_vlanx pip_qos_vlanx;
+        pip_qos_vlanx.u64 = 0;
+        pip_qos_vlanx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
+}
+
+/**
+ * Configure the Diffserv to QoS queue mapping.
+ *
+ * @diffserv: Diffserv field value (0-63)
+ * @qos:      QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
+{
+        union cvmx_pip_qos_diffx pip_qos_diffx;
+        pip_qos_diffx.u64 = 0;
+        pip_qos_diffx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
+}
+
+/**
+ * Get the status counters for a port.
+ *
+ * @port_num: Port number to get statistics for.
+ * @clear:    Set to 1 to clear the counters after they are read
+ * @status:   Where to put the results.
+ */
+static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
+                                            cvmx_pip_port_status_t *status)
+{
+        union cvmx_pip_stat_ctl pip_stat_ctl;
+        union cvmx_pip_stat0_prtx stat0;
+        union cvmx_pip_stat1_prtx stat1;
+        union cvmx_pip_stat2_prtx stat2;
+        union cvmx_pip_stat3_prtx stat3;
+        union cvmx_pip_stat4_prtx stat4;
+        union cvmx_pip_stat5_prtx stat5;
+        union cvmx_pip_stat6_prtx stat6;
+        union cvmx_pip_stat7_prtx stat7;
+        union cvmx_pip_stat8_prtx stat8;
+        union cvmx_pip_stat9_prtx stat9;
+        union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
+        union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
+        union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
+
+        pip_stat_ctl.u64 = 0;
+        pip_stat_ctl.s.rdclr = clear;
+        cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
+
+        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
+        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
+        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
+        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
+        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
+        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
+        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
+        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
+        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
+        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+        pip_stat_inb_pktsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
+        pip_stat_inb_octsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
+        pip_stat_inb_errsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
+
+        status->dropped_octets = stat0.s.drp_octs;
+        status->dropped_packets = stat0.s.drp_pkts;
+        status->octets = stat1.s.octs;
+        status->pci_raw_packets = stat2.s.raw;
+        status->packets = stat2.s.pkts;
+        status->multicast_packets = stat3.s.mcst;
+        status->broadcast_packets = stat3.s.bcst;
+        status->len_64_packets = stat4.s.h64;
+        status->len_65_127_packets = stat4.s.h65to127;
+        status->len_128_255_packets = stat5.s.h128to255;
+        status->len_256_511_packets = stat5.s.h256to511;
+        status->len_512_1023_packets = stat6.s.h512to1023;
+        status->len_1024_1518_packets = stat6.s.h1024to1518;
+        status->len_1519_max_packets = stat7.s.h1519;
+        status->fcs_align_err_packets = stat7.s.fcs;
+        status->runt_packets = stat8.s.undersz;
+        status->runt_crc_packets = stat8.s.frag;
+        status->oversize_packets = stat9.s.oversz;
+        status->oversize_crc_packets = stat9.s.jabber;
+        status->inb_packets = pip_stat_inb_pktsx.s.pkts;
+        status->inb_octets = pip_stat_inb_octsx.s.octs;
+        status->inb_errors = pip_stat_inb_errsx.s.errs;
+
+        if (cvmx_octeon_is_pass1()) {
+                /*
+                 * Kludge to fix Octeon Pass 1 errata - Drop counts
+                 * don't work.
+                 */
+                if (status->inb_packets > status->packets)
+                        status->dropped_packets =
+                            status->inb_packets - status->packets;
+                else
+                        status->dropped_packets = 0;
+                if (status->inb_octets - status->inb_packets * 4 >
+                    status->octets)
+                        status->dropped_octets =
+                            status->inb_octets - status->inb_packets * 4 -
+                            status->octets;
+                else
+                        status->dropped_octets = 0;
+        }
+}
+
+/**
+ * Configure the hardware CRC engine
+ *
+ * @interface: Interface to configure (0 or 1)
+ * @invert_result:
+ *                 Invert the result of the CRC
+ * @reflect:  Reflect
+ * @initialization_vector:
+ *                 CRC initialization vector
+ */
+static inline void cvmx_pip_config_crc(uint64_t interface,
+                                       uint64_t invert_result, uint64_t reflect,
+                                       uint32_t initialization_vector)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                union cvmx_pip_crc_ctlx config;
+                union cvmx_pip_crc_ivx pip_crc_ivx;
+
+                config.u64 = 0;
+                config.s.invres = invert_result;
+                config.s.reflect = reflect;
+                cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
+
+                pip_crc_ivx.u64 = 0;
+                pip_crc_ivx.s.iv = initialization_vector;
+                cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
+        }
+}
+
+/**
+ * Clear all bits in a tag mask. This should be called on
+ * startup before any calls to cvmx_pip_tag_mask_set. Each bit
+ * set in the final mask represent a byte used in the packet for
+ * tag generation.
+ *
+ * @mask_index: Which tag mask to clear (0..3)
+ */
+static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
+{
+        uint64_t index;
+        union cvmx_pip_tag_incx pip_tag_incx;
+        pip_tag_incx.u64 = 0;
+        pip_tag_incx.s.en = 0;
+        for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
+                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+}
+
+/**
+ * Sets a range of bits in the tag mask. The tag mask is used
+ * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
+ * There are four separate masks that can be configured.
+ *
+ * @mask_index: Which tag mask to modify (0..3)
+ * @offset: Offset into the bitmask to set bits at. Use the GCC macro
+ *          offsetof() to determine the offsets into packet headers.
+ *          For example, offsetof(ethhdr, protocol) returns the offset
+ *          of the ethernet protocol field.  The bitmask selects which
+ *          bytes to include the tag, with bit offset X selecting
+ *          byte at offset X from the beginning of the packet data.
+ * @len:    Number of bytes to include. Usually this is the sizeof()
+ *          the field.
+ */
+static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
+                                         uint64_t len)
+{
+        while (len--) {
+                union cvmx_pip_tag_incx pip_tag_incx;
+                uint64_t index = mask_index * 16 + offset / 8;
+                pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
+                pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
+                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+                offset++;
+        }
+}
+
+#endif /*  __CVMX_PIP_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
new file mode 100644
index 000000000..7e14c0d32
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
@@ -0,0 +1,2205 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PKO_DEFS_H__
+#define __CVMX_PKO_DEFS_H__
+
+#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
+#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
+#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
+#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
+#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
+#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
+#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
+#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
+#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
+#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
+#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
+#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
+#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
+#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
+#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
+#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
+#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
+#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
+#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
+#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
+#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
+#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
+#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
+#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
+#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
+#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
+#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
+#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
+#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
+#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
+#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
+#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
+#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
+#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
+#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
+#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
+#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
+#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
+#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
+#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
+#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
+#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
+#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
+#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
+#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
+#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
+#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
+#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
+#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
+#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
+#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
+#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
+#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
+#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
+#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
+#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
+#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
+
+union cvmx_pko_mem_count0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_count0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t count:32;
+#else
+                uint64_t count:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_count1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_count1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t count:48;
+#else
+                uint64_t count:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_debug0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+#else
+                uint64_t size:16;
+                uint64_t segs:6;
+                uint64_t cmd:14;
+                uint64_t fau:28;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_debug1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+#else
+                uint64_t ptr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_debug10 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug10_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+#else
+                uint64_t size:16;
+                uint64_t segs:6;
+                uint64_t cmd:14;
+                uint64_t fau:28;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug10_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs1:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs2:17;
+#else
+                uint64_t ptrs2:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs1:17;
+                uint64_t reserved_49_63:15;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_mem_debug11 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t reserved_0_39:40;
+#else
+                uint64_t reserved_0_39:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug11_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+#else
+                uint64_t ptr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug11_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t maj:1;
+                uint64_t uid:3;
+                uint64_t sop:1;
+                uint64_t len:1;
+                uint64_t chk:1;
+                uint64_t cnt:13;
+                uint64_t mod:3;
+#else
+                uint64_t mod:3;
+                uint64_t cnt:13;
+                uint64_t chk:1;
+                uint64_t len:1;
+                uint64_t sop:1;
+                uint64_t uid:3;
+                uint64_t maj:1;
+                uint64_t reserved_23_63:41;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_mem_debug12 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug12_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug12_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+#else
+                uint64_t size:16;
+                uint64_t segs:6;
+                uint64_t cmd:14;
+                uint64_t fau:28;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug12_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:64;
+#else
+                uint64_t state:64;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pko_mem_debug13 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug13_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug13_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                uint64_t widx:17;
+                uint64_t ridx2:17;
+                uint64_t widx2:17;
+#else
+                uint64_t widx2:17;
+                uint64_t ridx2:17;
+                uint64_t widx:17;
+                uint64_t reserved_51_63:13;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug13_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+#else
+                uint64_t ptr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug13_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:64;
+#else
+                uint64_t state:64;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pko_mem_debug14 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug14_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug14_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t ridx:17;
+#else
+                uint64_t ridx:17;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug14_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pko_mem_debug2 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+#else
+                uint64_t ptr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_debug3 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+#else
+                uint64_t ptr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug3_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_mem_debug4 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug4_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t data:64;
+#else
+                uint64_t data:64;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug4_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t cmnd_segs:3;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_off:6;
+                uint64_t uid:3;
+                uint64_t dread_sop:1;
+                uint64_t init_dwrite:1;
+                uint64_t chk_once:1;
+                uint64_t chk_mode:1;
+                uint64_t active:1;
+                uint64_t static_p:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_off_max:4;
+                uint64_t qid_off:4;
+                uint64_t qid_base:8;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:3;
+#else
+                uint64_t major:3;
+                uint64_t minor:2;
+                uint64_t wait:1;
+                uint64_t qid_base:8;
+                uint64_t qid_off:4;
+                uint64_t qid_off_max:4;
+                uint64_t qcb_ridx:5;
+                uint64_t qos:3;
+                uint64_t static_p:1;
+                uint64_t active:1;
+                uint64_t chk_mode:1;
+                uint64_t chk_once:1;
+                uint64_t init_dwrite:1;
+                uint64_t dread_sop:1;
+                uint64_t uid:3;
+                uint64_t cmnd_off:6;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_segs:3;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug4_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t curr_siz:8;
+                uint64_t curr_off:16;
+                uint64_t cmnd_segs:6;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_off:6;
+                uint64_t uid:2;
+                uint64_t dread_sop:1;
+                uint64_t init_dwrite:1;
+                uint64_t chk_once:1;
+                uint64_t chk_mode:1;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:3;
+#else
+                uint64_t major:3;
+                uint64_t minor:2;
+                uint64_t wait:1;
+                uint64_t chk_mode:1;
+                uint64_t chk_once:1;
+                uint64_t init_dwrite:1;
+                uint64_t dread_sop:1;
+                uint64_t uid:2;
+                uint64_t cmnd_off:6;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_segs:6;
+                uint64_t curr_off:16;
+                uint64_t curr_siz:8;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pko_mem_debug5 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug5_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dwri_mod:1;
+                uint64_t dwri_sop:1;
+                uint64_t dwri_len:1;
+                uint64_t dwri_cnt:13;
+                uint64_t cmnd_siz:16;
+                uint64_t uid:1;
+                uint64_t xfer_wor:1;
+                uint64_t xfer_dwr:1;
+                uint64_t cbuf_fre:1;
+                uint64_t reserved_27_27:1;
+                uint64_t chk_mode:1;
+                uint64_t active:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_off:3;
+                uint64_t qid_base:7;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:4;
+#else
+                uint64_t major:4;
+                uint64_t minor:2;
+                uint64_t wait:1;
+                uint64_t qid_base:7;
+                uint64_t qid_off:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qos:3;
+                uint64_t active:1;
+                uint64_t chk_mode:1;
+                uint64_t reserved_27_27:1;
+                uint64_t cbuf_fre:1;
+                uint64_t xfer_dwr:1;
+                uint64_t xfer_wor:1;
+                uint64_t uid:1;
+                uint64_t cmnd_siz:16;
+                uint64_t dwri_cnt:13;
+                uint64_t dwri_len:1;
+                uint64_t dwri_sop:1;
+                uint64_t dwri_mod:1;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug5_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t curr_ptr:29;
+                uint64_t curr_siz:16;
+                uint64_t curr_off:16;
+                uint64_t cmnd_segs:3;
+#else
+                uint64_t cmnd_segs:3;
+                uint64_t curr_off:16;
+                uint64_t curr_siz:16;
+                uint64_t curr_ptr:29;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug5_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t nxt_inflt:6;
+                uint64_t curr_ptr:40;
+                uint64_t curr_siz:8;
+#else
+                uint64_t curr_siz:8;
+                uint64_t curr_ptr:40;
+                uint64_t nxt_inflt:6;
+                uint64_t reserved_54_63:10;
+#endif
+        } cn52xx;
+        struct cvmx_pko_mem_debug5_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t ptp:1;
+                uint64_t major_3:1;
+                uint64_t nxt_inflt:6;
+                uint64_t curr_ptr:40;
+                uint64_t curr_siz:8;
+#else
+                uint64_t curr_siz:8;
+                uint64_t curr_ptr:40;
+                uint64_t nxt_inflt:6;
+                uint64_t major_3:1;
+                uint64_t ptp:1;
+                uint64_t reserved_56_63:8;
+#endif
+        } cn61xx;
+        struct cvmx_pko_mem_debug5_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_57_63:7;
+                uint64_t uid_2:1;
+                uint64_t ptp:1;
+                uint64_t major_3:1;
+                uint64_t nxt_inflt:6;
+                uint64_t curr_ptr:40;
+                uint64_t curr_siz:8;
+#else
+                uint64_t curr_siz:8;
+                uint64_t curr_ptr:40;
+                uint64_t nxt_inflt:6;
+                uint64_t major_3:1;
+                uint64_t ptp:1;
+                uint64_t uid_2:1;
+                uint64_t reserved_57_63:7;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pko_mem_debug6 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t qid_offres:4;
+                uint64_t qid_offths:4;
+                uint64_t preempter:1;
+                uint64_t preemptee:1;
+                uint64_t preempted:1;
+                uint64_t active:1;
+                uint64_t statc:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_offmax:4;
+                uint64_t reserved_0_11:12;
+#else
+                uint64_t reserved_0_11:12;
+                uint64_t qid_offmax:4;
+                uint64_t qcb_ridx:5;
+                uint64_t qos:3;
+                uint64_t statc:1;
+                uint64_t active:1;
+                uint64_t preempted:1;
+                uint64_t preemptee:1;
+                uint64_t preempter:1;
+                uint64_t qid_offths:4;
+                uint64_t qid_offres:4;
+                uint64_t reserved_37_63:27;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug6_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t qid_offm:3;
+                uint64_t static_p:1;
+                uint64_t work_min:3;
+                uint64_t dwri_chk:1;
+                uint64_t dwri_uid:1;
+                uint64_t dwri_mod:2;
+#else
+                uint64_t dwri_mod:2;
+                uint64_t dwri_uid:1;
+                uint64_t dwri_chk:1;
+                uint64_t work_min:3;
+                uint64_t static_p:1;
+                uint64_t qid_offm:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug6_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t curr_ptr:11;
+#else
+                uint64_t curr_ptr:11;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug6_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t qid_offres:4;
+                uint64_t qid_offths:4;
+                uint64_t preempter:1;
+                uint64_t preemptee:1;
+                uint64_t preempted:1;
+                uint64_t active:1;
+                uint64_t statc:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_offmax:4;
+                uint64_t qid_off:4;
+                uint64_t qid_base:8;
+#else
+                uint64_t qid_base:8;
+                uint64_t qid_off:4;
+                uint64_t qid_offmax:4;
+                uint64_t qcb_ridx:5;
+                uint64_t qos:3;
+                uint64_t statc:1;
+                uint64_t active:1;
+                uint64_t preempted:1;
+                uint64_t preemptee:1;
+                uint64_t preempter:1;
+                uint64_t qid_offths:4;
+                uint64_t qid_offres:4;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pko_mem_debug7 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug7_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_58_63:6;
+                uint64_t dwb:9;
+                uint64_t start:33;
+                uint64_t size:16;
+#else
+                uint64_t size:16;
+                uint64_t start:33;
+                uint64_t dwb:9;
+                uint64_t reserved_58_63:6;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug7_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t qos:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t buf_ptr:33;
+                uint64_t qcb_widx:6;
+                uint64_t qcb_ridx:6;
+#else
+                uint64_t qcb_ridx:6;
+                uint64_t qcb_widx:6;
+                uint64_t buf_ptr:33;
+                uint64_t buf_siz:13;
+                uint64_t tail:1;
+                uint64_t qos:5;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug7_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t qos:3;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t buf_ptr:33;
+                uint64_t qcb_widx:7;
+                uint64_t qcb_ridx:7;
+#else
+                uint64_t qcb_ridx:7;
+                uint64_t qcb_widx:7;
+                uint64_t buf_ptr:33;
+                uint64_t buf_siz:13;
+                uint64_t tail:1;
+                uint64_t qos:3;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pko_mem_debug8 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t reserved_0_44:45;
+#else
+                uint64_t reserved_0_44:45;
+                uint64_t buf_siz:13;
+                uint64_t tail:1;
+                uint64_t reserved_59_63:5;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug8_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t qos:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t buf_ptr:33;
+                uint64_t qcb_widx:6;
+                uint64_t qcb_ridx:6;
+#else
+                uint64_t qcb_ridx:6;
+                uint64_t qcb_widx:6;
+                uint64_t buf_ptr:33;
+                uint64_t buf_siz:13;
+                uint64_t tail:1;
+                uint64_t qos:5;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug8_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_6_7:2;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t reserved_6_7:2;
+                uint64_t doorbell:20;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn50xx;
+        struct cvmx_pko_mem_debug8_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t preempter:1;
+                uint64_t doorbell:20;
+                uint64_t reserved_7_7:1;
+                uint64_t preemptee:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t preemptee:1;
+                uint64_t reserved_7_7:1;
+                uint64_t doorbell:20;
+                uint64_t preempter:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn52xx;
+        struct cvmx_pko_mem_debug8_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_42_63:22;
+                uint64_t qid_qqos:8;
+                uint64_t reserved_33_33:1;
+                uint64_t qid_idx:4;
+                uint64_t preempter:1;
+                uint64_t doorbell:20;
+                uint64_t reserved_7_7:1;
+                uint64_t preemptee:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t preemptee:1;
+                uint64_t reserved_7_7:1;
+                uint64_t doorbell:20;
+                uint64_t preempter:1;
+                uint64_t qid_idx:4;
+                uint64_t reserved_33_33:1;
+                uint64_t qid_qqos:8;
+                uint64_t reserved_42_63:22;
+#endif
+        } cn61xx;
+        struct cvmx_pko_mem_debug8_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_37_63:27;
+                uint64_t preempter:1;
+                uint64_t doorbell:20;
+                uint64_t reserved_9_15:7;
+                uint64_t preemptee:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:5;
+#else
+                uint64_t qos:5;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t preemptee:1;
+                uint64_t reserved_9_15:7;
+                uint64_t doorbell:20;
+                uint64_t preempter:1;
+                uint64_t reserved_37_63:27;
+#endif
+        } cn68xx;
+};
+
+union cvmx_pko_mem_debug9 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs0:17;
+                uint64_t reserved_0_31:32;
+#else
+                uint64_t reserved_0_31:32;
+                uint64_t ptrs0:17;
+                uint64_t reserved_49_63:15;
+#endif
+        } s;
+        struct cvmx_pko_mem_debug9_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_5_7:3;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t reserved_5_7:3;
+                uint64_t doorbell:20;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn30xx;
+        struct cvmx_pko_mem_debug9_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_6_7:2;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+#else
+                uint64_t qos:3;
+                uint64_t static_q:1;
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t reserved_6_7:2;
+                uint64_t doorbell:20;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn38xx;
+        struct cvmx_pko_mem_debug9_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs0:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs3:17;
+#else
+                uint64_t ptrs3:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs0:17;
+                uint64_t reserved_49_63:15;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_mem_iport_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_iport_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t crc:1;
+                uint64_t static_p:1;
+                uint64_t qos_mask:8;
+                uint64_t min_pkt:3;
+                uint64_t reserved_31_49:19;
+                uint64_t pipe:7;
+                uint64_t reserved_21_23:3;
+                uint64_t intr:5;
+                uint64_t reserved_13_15:3;
+                uint64_t eid:5;
+                uint64_t reserved_7_7:1;
+                uint64_t ipid:7;
+#else
+                uint64_t ipid:7;
+                uint64_t reserved_7_7:1;
+                uint64_t eid:5;
+                uint64_t reserved_13_15:3;
+                uint64_t intr:5;
+                uint64_t reserved_21_23:3;
+                uint64_t pipe:7;
+                uint64_t reserved_31_49:19;
+                uint64_t min_pkt:3;
+                uint64_t qos_mask:8;
+                uint64_t static_p:1;
+                uint64_t crc:1;
+                uint64_t reserved_63_63:1;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_iport_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_iport_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_13_52:40;
+                uint64_t eid:5;
+                uint64_t reserved_7_7:1;
+                uint64_t ipid:7;
+#else
+                uint64_t ipid:7;
+                uint64_t reserved_7_7:1;
+                uint64_t eid:5;
+                uint64_t reserved_13_52:40;
+                uint64_t qos_mask:8;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_iqueue_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_iqueue_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t static_q:1;
+                uint64_t qos_mask:8;
+                uint64_t buf_ptr:31;
+                uint64_t tail:1;
+                uint64_t index:5;
+                uint64_t reserved_15_15:1;
+                uint64_t ipid:7;
+                uint64_t qid:8;
+#else
+                uint64_t qid:8;
+                uint64_t ipid:7;
+                uint64_t reserved_15_15:1;
+                uint64_t index:5;
+                uint64_t tail:1;
+                uint64_t buf_ptr:31;
+                uint64_t qos_mask:8;
+                uint64_t static_q:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_iqueue_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_iqueue_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_15_52:38;
+                uint64_t ipid:7;
+                uint64_t qid:8;
+#else
+                uint64_t qid:8;
+                uint64_t ipid:7;
+                uint64_t reserved_15_52:38;
+                uint64_t qos_mask:8;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_port_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                uint64_t static_p:1;
+                uint64_t qos_mask:8;
+                uint64_t reserved_16_52:37;
+                uint64_t bp_port:6;
+                uint64_t eid:4;
+                uint64_t pid:6;
+#else
+                uint64_t pid:6;
+                uint64_t eid:4;
+                uint64_t bp_port:6;
+                uint64_t reserved_16_52:37;
+                uint64_t qos_mask:8;
+                uint64_t static_p:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_port_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_10_52:43;
+                uint64_t eid:4;
+                uint64_t pid:6;
+#else
+                uint64_t pid:6;
+                uint64_t eid:4;
+                uint64_t reserved_10_52:43;
+                uint64_t qos_mask:8;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_port_rate0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_rate0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                uint64_t rate_word:19;
+                uint64_t rate_pkt:24;
+                uint64_t reserved_7_7:1;
+                uint64_t pid:7;
+#else
+                uint64_t pid:7;
+                uint64_t reserved_7_7:1;
+                uint64_t rate_pkt:24;
+                uint64_t rate_word:19;
+                uint64_t reserved_51_63:13;
+#endif
+        } s;
+        struct cvmx_pko_mem_port_rate0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                uint64_t rate_word:19;
+                uint64_t rate_pkt:24;
+                uint64_t reserved_6_7:2;
+                uint64_t pid:6;
+#else
+                uint64_t pid:6;
+                uint64_t reserved_6_7:2;
+                uint64_t rate_pkt:24;
+                uint64_t rate_word:19;
+                uint64_t reserved_51_63:13;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pko_mem_port_rate1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_rate1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rate_lim:24;
+                uint64_t reserved_7_7:1;
+                uint64_t pid:7;
+#else
+                uint64_t pid:7;
+                uint64_t reserved_7_7:1;
+                uint64_t rate_lim:24;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_pko_mem_port_rate1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rate_lim:24;
+                uint64_t reserved_6_7:2;
+                uint64_t pid:6;
+#else
+                uint64_t pid:6;
+                uint64_t reserved_6_7:2;
+                uint64_t rate_lim:24;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn52xx;
+};
+
+union cvmx_pko_mem_queue_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_queue_ptrs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t static_q:1;
+                uint64_t qos_mask:8;
+                uint64_t buf_ptr:36;
+                uint64_t tail:1;
+                uint64_t index:3;
+                uint64_t port:6;
+                uint64_t queue:7;
+#else
+                uint64_t queue:7;
+                uint64_t port:6;
+                uint64_t index:3;
+                uint64_t tail:1;
+                uint64_t buf_ptr:36;
+                uint64_t qos_mask:8;
+                uint64_t static_q:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_queue_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_queue_qos_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_13_52:40;
+                uint64_t pid:6;
+                uint64_t qid:7;
+#else
+                uint64_t qid:7;
+                uint64_t pid:6;
+                uint64_t reserved_13_52:40;
+                uint64_t qos_mask:8;
+                uint64_t reserved_61_63:3;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_throttle_int {
+        uint64_t u64;
+        struct cvmx_pko_mem_throttle_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t word:15;
+                uint64_t reserved_14_31:18;
+                uint64_t packet:6;
+                uint64_t reserved_5_7:3;
+                uint64_t intr:5;
+#else
+                uint64_t intr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t packet:6;
+                uint64_t reserved_14_31:18;
+                uint64_t word:15;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+};
+
+union cvmx_pko_mem_throttle_pipe {
+        uint64_t u64;
+        struct cvmx_pko_mem_throttle_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t word:15;
+                uint64_t reserved_14_31:18;
+                uint64_t packet:6;
+                uint64_t reserved_7_7:1;
+                uint64_t pipe:7;
+#else
+                uint64_t pipe:7;
+                uint64_t reserved_7_7:1;
+                uint64_t packet:6;
+                uint64_t reserved_14_31:18;
+                uint64_t word:15;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_bist_result {
+        uint64_t u64;
+        struct cvmx_pko_reg_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_pko_reg_bist_result_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t psb2:5;
+                uint64_t count:1;
+                uint64_t rif:1;
+                uint64_t wif:1;
+                uint64_t ncb:1;
+                uint64_t out:1;
+                uint64_t crc:1;
+                uint64_t chk:1;
+                uint64_t qsb:2;
+                uint64_t qcb:2;
+                uint64_t pdb:4;
+                uint64_t psb:7;
+#else
+                uint64_t psb:7;
+                uint64_t pdb:4;
+                uint64_t qcb:2;
+                uint64_t qsb:2;
+                uint64_t chk:1;
+                uint64_t crc:1;
+                uint64_t out:1;
+                uint64_t ncb:1;
+                uint64_t wif:1;
+                uint64_t rif:1;
+                uint64_t count:1;
+                uint64_t psb2:5;
+                uint64_t reserved_27_63:37;
+#endif
+        } cn30xx;
+        struct cvmx_pko_reg_bist_result_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_crc:1;
+                uint64_t out_ctl:3;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb:6;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t dat_dat:4;
+                uint64_t dat_ptr:4;
+#else
+                uint64_t dat_ptr:4;
+                uint64_t dat_dat:4;
+                uint64_t prt_qsb:3;
+                uint64_t prt_qcb:2;
+                uint64_t ncb_inb:2;
+                uint64_t prt_psb:6;
+                uint64_t prt_nxt:1;
+                uint64_t prt_chk:3;
+                uint64_t out_wif:1;
+                uint64_t out_sta:1;
+                uint64_t out_ctl:3;
+                uint64_t out_crc:1;
+                uint64_t iob:1;
+                uint64_t csr:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } cn50xx;
+        struct cvmx_pko_reg_bist_result_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_dat:1;
+                uint64_t out_ctl:3;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb:8;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_ctl:2;
+                uint64_t dat_dat:2;
+                uint64_t dat_ptr:4;
+#else
+                uint64_t dat_ptr:4;
+                uint64_t dat_dat:2;
+                uint64_t prt_ctl:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_qcb:2;
+                uint64_t ncb_inb:2;
+                uint64_t prt_psb:8;
+                uint64_t prt_nxt:1;
+                uint64_t prt_chk:3;
+                uint64_t out_wif:1;
+                uint64_t out_sta:1;
+                uint64_t out_ctl:3;
+                uint64_t out_dat:1;
+                uint64_t iob:1;
+                uint64_t csr:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } cn52xx;
+        struct cvmx_pko_reg_bist_result_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_36_63:28;
+                uint64_t crc:1;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_dat:1;
+                uint64_t reserved_31_31:1;
+                uint64_t out_ctl:2;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb7:1;
+                uint64_t reserved_21_21:1;
+                uint64_t prt_psb:6;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_ctl:2;
+                uint64_t dat_dat:2;
+                uint64_t dat_ptr:4;
+#else
+                uint64_t dat_ptr:4;
+                uint64_t dat_dat:2;
+                uint64_t prt_ctl:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_qcb:2;
+                uint64_t ncb_inb:2;
+                uint64_t prt_psb:6;
+                uint64_t reserved_21_21:1;
+                uint64_t prt_psb7:1;
+                uint64_t prt_nxt:1;
+                uint64_t prt_chk:3;
+                uint64_t out_wif:1;
+                uint64_t out_sta:1;
+                uint64_t out_ctl:2;
+                uint64_t reserved_31_31:1;
+                uint64_t out_dat:1;
+                uint64_t iob:1;
+                uint64_t csr:1;
+                uint64_t crc:1;
+                uint64_t reserved_36_63:28;
+#endif
+        } cn68xx;
+        struct cvmx_pko_reg_bist_result_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_35_63:29;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_dat:1;
+                uint64_t reserved_31_31:1;
+                uint64_t out_ctl:2;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb7:1;
+                uint64_t reserved_21_21:1;
+                uint64_t prt_psb:6;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_ctl:2;
+                uint64_t dat_dat:2;
+                uint64_t dat_ptr:4;
+#else
+                uint64_t dat_ptr:4;
+                uint64_t dat_dat:2;
+                uint64_t prt_ctl:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_qcb:2;
+                uint64_t ncb_inb:2;
+                uint64_t prt_psb:6;
+                uint64_t reserved_21_21:1;
+                uint64_t prt_psb7:1;
+                uint64_t prt_nxt:1;
+                uint64_t prt_chk:3;
+                uint64_t out_wif:1;
+                uint64_t out_sta:1;
+                uint64_t out_ctl:2;
+                uint64_t reserved_31_31:1;
+                uint64_t out_dat:1;
+                uint64_t iob:1;
+                uint64_t csr:1;
+                uint64_t reserved_35_63:29;
+#endif
+        } cn68xxp1;
+};
+
+union cvmx_pko_reg_cmd_buf {
+        uint64_t u64;
+        struct cvmx_pko_reg_cmd_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_23_63:41;
+                uint64_t pool:3;
+                uint64_t reserved_13_19:7;
+                uint64_t size:13;
+#else
+                uint64_t size:13;
+                uint64_t reserved_13_19:7;
+                uint64_t pool:3;
+                uint64_t reserved_23_63:41;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_crc_ctlx {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t invres:1;
+                uint64_t refin:1;
+#else
+                uint64_t refin:1;
+                uint64_t invres:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_crc_enable {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enable:32;
+#else
+                uint64_t enable:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_crc_ivx {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_ivx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iv:32;
+#else
+                uint64_t iv:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_debug0 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t asserts:64;
+#else
+                uint64_t asserts:64;
+#endif
+        } s;
+        struct cvmx_pko_reg_debug0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t asserts:17;
+#else
+                uint64_t asserts:17;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn30xx;
+};
+
+union cvmx_pko_reg_debug1 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t asserts:64;
+#else
+                uint64_t asserts:64;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_debug2 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t asserts:64;
+#else
+                uint64_t asserts:64;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_debug3 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t asserts:64;
+#else
+                uint64_t asserts:64;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_debug4 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t asserts:64;
+#else
+                uint64_t asserts:64;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_engine_inflight {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_inflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t engine15:4;
+                uint64_t engine14:4;
+                uint64_t engine13:4;
+                uint64_t engine12:4;
+                uint64_t engine11:4;
+                uint64_t engine10:4;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+#else
+                uint64_t engine0:4;
+                uint64_t engine1:4;
+                uint64_t engine2:4;
+                uint64_t engine3:4;
+                uint64_t engine4:4;
+                uint64_t engine5:4;
+                uint64_t engine6:4;
+                uint64_t engine7:4;
+                uint64_t engine8:4;
+                uint64_t engine9:4;
+                uint64_t engine10:4;
+                uint64_t engine11:4;
+                uint64_t engine12:4;
+                uint64_t engine13:4;
+                uint64_t engine14:4;
+                uint64_t engine15:4;
+#endif
+        } s;
+        struct cvmx_pko_reg_engine_inflight_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+#else
+                uint64_t engine0:4;
+                uint64_t engine1:4;
+                uint64_t engine2:4;
+                uint64_t engine3:4;
+                uint64_t engine4:4;
+                uint64_t engine5:4;
+                uint64_t engine6:4;
+                uint64_t engine7:4;
+                uint64_t engine8:4;
+                uint64_t engine9:4;
+                uint64_t reserved_40_63:24;
+#endif
+        } cn52xx;
+        struct cvmx_pko_reg_engine_inflight_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t engine13:4;
+                uint64_t engine12:4;
+                uint64_t engine11:4;
+                uint64_t engine10:4;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+#else
+                uint64_t engine0:4;
+                uint64_t engine1:4;
+                uint64_t engine2:4;
+                uint64_t engine3:4;
+                uint64_t engine4:4;
+                uint64_t engine5:4;
+                uint64_t engine6:4;
+                uint64_t engine7:4;
+                uint64_t engine8:4;
+                uint64_t engine9:4;
+                uint64_t engine10:4;
+                uint64_t engine11:4;
+                uint64_t engine12:4;
+                uint64_t engine13:4;
+                uint64_t reserved_56_63:8;
+#endif
+        } cn61xx;
+        struct cvmx_pko_reg_engine_inflight_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t engine11:4;
+                uint64_t engine10:4;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+#else
+                uint64_t engine0:4;
+                uint64_t engine1:4;
+                uint64_t engine2:4;
+                uint64_t engine3:4;
+                uint64_t engine4:4;
+                uint64_t engine5:4;
+                uint64_t engine6:4;
+                uint64_t engine7:4;
+                uint64_t engine8:4;
+                uint64_t engine9:4;
+                uint64_t engine10:4;
+                uint64_t engine11:4;
+                uint64_t reserved_48_63:16;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pko_reg_engine_inflight1 {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_inflight1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t engine19:4;
+                uint64_t engine18:4;
+                uint64_t engine17:4;
+                uint64_t engine16:4;
+#else
+                uint64_t engine16:4;
+                uint64_t engine17:4;
+                uint64_t engine18:4;
+                uint64_t engine19:4;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_engine_storagex {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_storagex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t engine15:4;
+                uint64_t engine14:4;
+                uint64_t engine13:4;
+                uint64_t engine12:4;
+                uint64_t engine11:4;
+                uint64_t engine10:4;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+#else
+                uint64_t engine0:4;
+                uint64_t engine1:4;
+                uint64_t engine2:4;
+                uint64_t engine3:4;
+                uint64_t engine4:4;
+                uint64_t engine5:4;
+                uint64_t engine6:4;
+                uint64_t engine7:4;
+                uint64_t engine8:4;
+                uint64_t engine9:4;
+                uint64_t engine10:4;
+                uint64_t engine11:4;
+                uint64_t engine12:4;
+                uint64_t engine13:4;
+                uint64_t engine14:4;
+                uint64_t engine15:4;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_engine_thresh {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t mask:20;
+#else
+                uint64_t mask:20;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+        struct cvmx_pko_reg_engine_thresh_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t mask:10;
+#else
+                uint64_t mask:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn52xx;
+        struct cvmx_pko_reg_engine_thresh_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t mask:14;
+#else
+                uint64_t mask:14;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn61xx;
+        struct cvmx_pko_reg_engine_thresh_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t mask:12;
+#else
+                uint64_t mask:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pko_reg_error {
+        uint64_t u64;
+        struct cvmx_pko_reg_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t loopback:1;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t currzero:1;
+                uint64_t loopback:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_pko_reg_error_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn30xx;
+        struct cvmx_pko_reg_error_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t currzero:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_reg_flags {
+        uint64_t u64;
+        struct cvmx_pko_reg_flags_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t dis_perf3:1;
+                uint64_t dis_perf2:1;
+                uint64_t dis_perf1:1;
+                uint64_t dis_perf0:1;
+                uint64_t ena_throttle:1;
+                uint64_t reset:1;
+                uint64_t store_be:1;
+                uint64_t ena_dwb:1;
+                uint64_t ena_pko:1;
+#else
+                uint64_t ena_pko:1;
+                uint64_t ena_dwb:1;
+                uint64_t store_be:1;
+                uint64_t reset:1;
+                uint64_t ena_throttle:1;
+                uint64_t dis_perf0:1;
+                uint64_t dis_perf1:1;
+                uint64_t dis_perf2:1;
+                uint64_t dis_perf3:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+        struct cvmx_pko_reg_flags_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t reset:1;
+                uint64_t store_be:1;
+                uint64_t ena_dwb:1;
+                uint64_t ena_pko:1;
+#else
+                uint64_t ena_pko:1;
+                uint64_t ena_dwb:1;
+                uint64_t store_be:1;
+                uint64_t reset:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_pko_reg_flags_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t dis_perf3:1;
+                uint64_t dis_perf2:1;
+                uint64_t reserved_4_6:3;
+                uint64_t reset:1;
+                uint64_t store_be:1;
+                uint64_t ena_dwb:1;
+                uint64_t ena_pko:1;
+#else
+                uint64_t ena_pko:1;
+                uint64_t ena_dwb:1;
+                uint64_t store_be:1;
+                uint64_t reset:1;
+                uint64_t reserved_4_6:3;
+                uint64_t dis_perf2:1;
+                uint64_t dis_perf3:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn61xx;
+        struct cvmx_pko_reg_flags_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t dis_perf1:1;
+                uint64_t dis_perf0:1;
+                uint64_t ena_throttle:1;
+                uint64_t reset:1;
+                uint64_t store_be:1;
+                uint64_t ena_dwb:1;
+                uint64_t ena_pko:1;
+#else
+                uint64_t ena_pko:1;
+                uint64_t ena_dwb:1;
+                uint64_t store_be:1;
+                uint64_t reset:1;
+                uint64_t ena_throttle:1;
+                uint64_t dis_perf0:1;
+                uint64_t dis_perf1:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn68xxp1;
+};
+
+union cvmx_pko_reg_gmx_port_mode {
+        uint64_t u64;
+        struct cvmx_pko_reg_gmx_port_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t mode1:3;
+                uint64_t mode0:3;
+#else
+                uint64_t mode0:3;
+                uint64_t mode1:3;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_int_mask {
+        uint64_t u64;
+        struct cvmx_pko_reg_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t loopback:1;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t currzero:1;
+                uint64_t loopback:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+        struct cvmx_pko_reg_int_mask_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } cn30xx;
+        struct cvmx_pko_reg_int_mask_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+#else
+                uint64_t parity:1;
+                uint64_t doorbell:1;
+                uint64_t currzero:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn50xx;
+};
+
+union cvmx_pko_reg_loopback_bpid {
+        uint64_t u64;
+        struct cvmx_pko_reg_loopback_bpid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t bpid7:6;
+                uint64_t reserved_52_52:1;
+                uint64_t bpid6:6;
+                uint64_t reserved_45_45:1;
+                uint64_t bpid5:6;
+                uint64_t reserved_38_38:1;
+                uint64_t bpid4:6;
+                uint64_t reserved_31_31:1;
+                uint64_t bpid3:6;
+                uint64_t reserved_24_24:1;
+                uint64_t bpid2:6;
+                uint64_t reserved_17_17:1;
+                uint64_t bpid1:6;
+                uint64_t reserved_10_10:1;
+                uint64_t bpid0:6;
+                uint64_t reserved_0_3:4;
+#else
+                uint64_t reserved_0_3:4;
+                uint64_t bpid0:6;
+                uint64_t reserved_10_10:1;
+                uint64_t bpid1:6;
+                uint64_t reserved_17_17:1;
+                uint64_t bpid2:6;
+                uint64_t reserved_24_24:1;
+                uint64_t bpid3:6;
+                uint64_t reserved_31_31:1;
+                uint64_t bpid4:6;
+                uint64_t reserved_38_38:1;
+                uint64_t bpid5:6;
+                uint64_t reserved_45_45:1;
+                uint64_t bpid6:6;
+                uint64_t reserved_52_52:1;
+                uint64_t bpid7:6;
+                uint64_t reserved_59_63:5;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_loopback_pkind {
+        uint64_t u64;
+        struct cvmx_pko_reg_loopback_pkind_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t pkind7:6;
+                uint64_t reserved_52_52:1;
+                uint64_t pkind6:6;
+                uint64_t reserved_45_45:1;
+                uint64_t pkind5:6;
+                uint64_t reserved_38_38:1;
+                uint64_t pkind4:6;
+                uint64_t reserved_31_31:1;
+                uint64_t pkind3:6;
+                uint64_t reserved_24_24:1;
+                uint64_t pkind2:6;
+                uint64_t reserved_17_17:1;
+                uint64_t pkind1:6;
+                uint64_t reserved_10_10:1;
+                uint64_t pkind0:6;
+                uint64_t num_ports:4;
+#else
+                uint64_t num_ports:4;
+                uint64_t pkind0:6;
+                uint64_t reserved_10_10:1;
+                uint64_t pkind1:6;
+                uint64_t reserved_17_17:1;
+                uint64_t pkind2:6;
+                uint64_t reserved_24_24:1;
+                uint64_t pkind3:6;
+                uint64_t reserved_31_31:1;
+                uint64_t pkind4:6;
+                uint64_t reserved_38_38:1;
+                uint64_t pkind5:6;
+                uint64_t reserved_45_45:1;
+                uint64_t pkind6:6;
+                uint64_t reserved_52_52:1;
+                uint64_t pkind7:6;
+                uint64_t reserved_59_63:5;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_min_pkt {
+        uint64_t u64;
+        struct cvmx_pko_reg_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t size7:8;
+                uint64_t size6:8;
+                uint64_t size5:8;
+                uint64_t size4:8;
+                uint64_t size3:8;
+                uint64_t size2:8;
+                uint64_t size1:8;
+                uint64_t size0:8;
+#else
+                uint64_t size0:8;
+                uint64_t size1:8;
+                uint64_t size2:8;
+                uint64_t size3:8;
+                uint64_t size4:8;
+                uint64_t size5:8;
+                uint64_t size6:8;
+                uint64_t size7:8;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_preempt {
+        uint64_t u64;
+        struct cvmx_pko_reg_preempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t min_size:16;
+#else
+                uint64_t min_size:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_queue_mode {
+        uint64_t u64;
+        struct cvmx_pko_reg_queue_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t mode:2;
+#else
+                uint64_t mode:2;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_queue_preempt {
+        uint64_t u64;
+        struct cvmx_pko_reg_queue_preempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t preemptee:1;
+                uint64_t preempter:1;
+#else
+                uint64_t preempter:1;
+                uint64_t preemptee:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_queue_ptrs1 {
+        uint64_t u64;
+        struct cvmx_pko_reg_queue_ptrs1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t idx3:1;
+                uint64_t qid7:1;
+#else
+                uint64_t qid7:1;
+                uint64_t idx3:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_read_idx {
+        uint64_t u64;
+        struct cvmx_pko_reg_read_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t inc:8;
+                uint64_t index:8;
+#else
+                uint64_t index:8;
+                uint64_t inc:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_throttle {
+        uint64_t u64;
+        struct cvmx_pko_reg_throttle_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t int_mask:32;
+#else
+                uint64_t int_mask:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pko_reg_timestamp {
+        uint64_t u64;
+        struct cvmx_pko_reg_timestamp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t wqe_word:4;
+#else
+                uint64_t wqe_word:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
new file mode 100644
index 000000000..03fb64b13
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -0,0 +1,643 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Interface to the hardware Packet Output unit.
+ *
+ * Starting with SDK 1.7.0, the PKO output functions now support
+ * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
+ * function similarly to previous SDKs by using POW atomic tags
+ * to preserve ordering and exclusivity. As a new option, you
+ * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
+ * memory based locking instead. This locking has the advantage
+ * of not affecting the tag state but doesn't preserve packet
+ * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
+ * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
+ * with hand tuned fast path code.
+ *
+ * Some of other SDK differences visible to the command queuing:
+ * - PKO indexes are no longer stored in the FAU. A large
+ *   percentage of the FAU register block used to be tied up
+ *   maintaining PKO queue pointers. These are now stored in a
+ *   global named block.
+ * - The PKO <b>use_locking</b> parameter can now have a global
+ *   effect. Since all application use the same named block,
+ *   queue locking correctly applies across all operating
+ *   systems when using CVMX_PKO_LOCK_CMD_QUEUE.
+ * - PKO 3 word commands are now supported. Use
+ *   cvmx_pko_send_packet_finish3().
+ *
+ */
+
+#ifndef __CVMX_PKO_H__
+#define __CVMX_PKO_H__
+
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pow.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#include <asm/octeon/cvmx-pko-defs.h>
+
+/* Adjust the command buffer size by 1 word so that in the case of using only
+ * two word PKO commands no command words stradle buffers.  The useful values
+ * for this are 0 and 1. */
+#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
+
+#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
+#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
+        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
+        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
+                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
+                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
+#define CVMX_PKO_NUM_OUTPUT_PORTS       40
+/* use this for queues that are not used */
+#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
+#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
+#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
+#define CVMX_PKO_MAX_QUEUE_DEPTH 0
+
+typedef enum {
+        CVMX_PKO_SUCCESS,
+        CVMX_PKO_INVALID_PORT,
+        CVMX_PKO_INVALID_QUEUE,
+        CVMX_PKO_INVALID_PRIORITY,
+        CVMX_PKO_NO_MEMORY,
+        CVMX_PKO_PORT_ALREADY_SETUP,
+        CVMX_PKO_CMD_QUEUE_INIT_ERROR
+} cvmx_pko_status_t;
+
+/**
+ * This enumeration represents the differnet locking modes supported by PKO.
+ */
+typedef enum {
+        /*
+         * PKO doesn't do any locking. It is the responsibility of the
+         * application to make sure that no other core is accessing
+         * the same queue at the same time
+         */
+        CVMX_PKO_LOCK_NONE = 0,
+        /*
+         * PKO performs an atomic tagswitch to insure exclusive access
+         * to the output queue. This will maintain packet ordering on
+         * output.
+         */
+        CVMX_PKO_LOCK_ATOMIC_TAG = 1,
+        /*
+         * PKO uses the common command queue locks to insure exclusive
+         * access to the output queue. This is a memory based
+         * ll/sc. This is the most portable locking mechanism.
+         */
+        CVMX_PKO_LOCK_CMD_QUEUE = 2,
+} cvmx_pko_lock_t;
+
+typedef struct {
+        uint32_t packets;
+        uint64_t octets;
+        uint64_t doorbell;
+} cvmx_pko_port_status_t;
+
+/**
+ * This structure defines the address to use on a packet enqueue
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Must CVMX_IO_SEG */
+                uint64_t mem_space:2;
+                /* Must be zero */
+                uint64_t reserved:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* The ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved2:4;
+                /* Must be zero */
+                uint64_t reserved3:18;
+                /*
+                 * The hardware likes to have the output port in
+                 * addition to the output queue,
+                 */
+                uint64_t port:6;
+                /*
+                 * The output queue to send the packet to (0-127 are
+                 * legal)
+                 */
+                uint64_t queue:9;
+                /* Must be zero */
+                uint64_t reserved4:3;
+#else
+                uint64_t reserved4:3;
+                uint64_t queue:9;
+                uint64_t port:9;
+                uint64_t reserved3:15;
+                uint64_t reserved2:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved:13;
+                uint64_t mem_space:2;
+#endif
+        } s;
+} cvmx_pko_doorbell_address_t;
+
+/**
+ * Structure of the first packet output command word.
+ */
+union cvmx_pko_command_word0 {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * The size of the reg1 operation - could be 8, 16,
+                 * 32, or 64 bits.
+                 */
+                uint64_t size1:2;
+                /*
+                 * The size of the reg0 operation - could be 8, 16,
+                 * 32, or 64 bits.
+                 */
+                uint64_t size0:2;
+                /*
+                 * If set, subtract 1, if clear, subtract packet
+                 * size.
+                 */
+                uint64_t subone1:1;
+                /*
+                 * The register, subtract will be done if reg1 is
+                 * non-zero.
+                 */
+                uint64_t reg1:11;
+                /* If set, subtract 1, if clear, subtract packet size */
+                uint64_t subone0:1;
+                /* The register, subtract will be done if reg0 is non-zero */
+                uint64_t reg0:11;
+                /*
+                 * When set, interpret segment pointer and segment
+                 * bytes in little endian order.
+                 */
+                uint64_t le:1;
+                /*
+                 * When set, packet data not allocated in L2 cache by
+                 * PKO.
+                 */
+                uint64_t n2:1;
+                /*
+                 * If set and rsp is set, word3 contains a pointer to
+                 * a work queue entry.
+                 */
+                uint64_t wqp:1;
+                /* If set, the hardware will send a response when done */
+                uint64_t rsp:1;
+                /*
+                 * If set, the supplied pkt_ptr is really a pointer to
+                 * a list of pkt_ptr's.
+                 */
+                uint64_t gather:1;
+                /*
+                 * If ipoffp1 is non zero, (ipoffp1-1) is the number
+                 * of bytes to IP header, and the hardware will
+                 * calculate and insert the UDP/TCP checksum.
+                 */
+                uint64_t ipoffp1:7;
+                /*
+                 * If set, ignore the I bit (force to zero) from all
+                 * pointer structures.
+                 */
+                uint64_t ignore_i:1;
+                /*
+                 * If clear, the hardware will attempt to free the
+                 * buffers containing the packet.
+                 */
+                uint64_t dontfree:1;
+                /*
+                 * The total number of segs in the packet, if gather
+                 * set, also gather list length.
+                 */
+                uint64_t segs:6;
+                /* Including L2, but no trailing CRC */
+                uint64_t total_bytes:16;
+#else
+                uint64_t total_bytes:16;
+                uint64_t segs:6;
+                uint64_t dontfree:1;
+                uint64_t ignore_i:1;
+                uint64_t ipoffp1:7;
+                uint64_t gather:1;
+                uint64_t rsp:1;
+                uint64_t wqp:1;
+                uint64_t n2:1;
+                uint64_t le:1;
+                uint64_t reg0:11;
+                uint64_t subone0:1;
+                uint64_t reg1:11;
+                uint64_t subone1:1;
+                uint64_t size0:2;
+                uint64_t size1:2;
+#endif
+        } s;
+};
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Definition of internal state for Packet output processing
+ */
+typedef struct {
+        /* ptr to start of buffer, offset kept in FAU reg */
+        uint64_t *start_ptr;
+} cvmx_pko_state_elem_t;
+
+/**
+ * Call before any other calls to initialize the packet
+ * output system.
+ */
+extern void cvmx_pko_initialize_global(void);
+extern int cvmx_pko_initialize_local(void);
+
+/**
+ * Enables the packet output hardware. It must already be
+ * configured.
+ */
+extern void cvmx_pko_enable(void);
+
+/**
+ * Disables the packet output. Does not affect any configuration.
+ */
+extern void cvmx_pko_disable(void);
+
+/**
+ * Shutdown and free resources required by packet output.
+ */
+
+extern void cvmx_pko_shutdown(void);
+
+/**
+ * Configure a output port and the associated queues for use.
+ *
+ * @port:       Port to configure.
+ * @base_queue: First queue number to associate with this port.
+ * @num_queues: Number of queues t oassociate with this port
+ * @priority:   Array of priority levels for each queue. Values are
+ *                   allowed to be 1-8. A value of 8 get 8 times the traffic
+ *                   of a value of 1. There must be num_queues elements in the
+ *                   array.
+ */
+extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
+                                              uint64_t base_queue,
+                                              uint64_t num_queues,
+                                              const uint64_t priority[]);
+
+/**
+ * Ring the packet output doorbell. This tells the packet
+ * output hardware that "len" command words have been added
+ * to its pending list.  This command includes the required
+ * CVMX_SYNCWS before the doorbell ring.
+ *
+ * @port:   Port the packet is for
+ * @queue:  Queue the packet is for
+ * @len:    Length of the command in 64 bit words
+ */
+static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
+                                     uint64_t len)
+{
+        cvmx_pko_doorbell_address_t ptr;
+
+        ptr.u64 = 0;
+        ptr.s.mem_space = CVMX_IO_SEG;
+        ptr.s.did = CVMX_OCT_DID_PKT_SEND;
+        ptr.s.is_io = 1;
+        ptr.s.port = port;
+        ptr.s.queue = queue;
+        /*
+         * Need to make sure output queue data is in DRAM before
+         * doorbell write.
+         */
+        CVMX_SYNCWS;
+        cvmx_write_io(ptr.u64, len);
+}
+
+/**
+ * Prepare to send a packet.  This may initiate a tag switch to
+ * get exclusive access to the output queue structure, and
+ * performs other prep work for the packet send operation.
+ *
+ * cvmx_pko_send_packet_finish() MUST be called after this function is called,
+ * and must be called with the same port/queue/use_locking arguments.
+ *
+ * The use_locking parameter allows the caller to use three
+ * possible locking modes.
+ * - CVMX_PKO_LOCK_NONE
+ *      - PKO doesn't do any locking. It is the responsibility
+ *          of the application to make sure that no other core
+ *          is accessing the same queue at the same time.
+ * - CVMX_PKO_LOCK_ATOMIC_TAG
+ *      - PKO performs an atomic tagswitch to insure exclusive
+ *          access to the output queue. This will maintain
+ *          packet ordering on output.
+ * - CVMX_PKO_LOCK_CMD_QUEUE
+ *      - PKO uses the common command queue locks to insure
+ *          exclusive access to the output queue. This is a
+ *          memory based ll/sc. This is the most portable
+ *          locking mechanism.
+ *
+ * NOTE: If atomic locking is used, the POW entry CANNOT be
+ * descheduled, as it does not contain a valid WQE pointer.
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ */
+
+static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
+                                                cvmx_pko_lock_t use_locking)
+{
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
+                /*
+                 * Must do a full switch here to handle all cases.  We
+                 * use a fake WQE pointer, as the POW does not access
+                 * this memory.  The WQE pointer and group are only
+                 * used if this work is descheduled, which is not
+                 * supported by the
+                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
+                 * combination.  Note that this is a special case in
+                 * which these fake values can be used - this is not a
+                 * general technique.
+                 */
+                uint32_t tag =
+                    CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
+                    CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
+                    (CVMX_TAG_SUBGROUP_MASK & queue);
+                cvmx_pow_tag_sw_full((struct cvmx_wqe *) cvmx_phys_to_ptr(0x80), tag,
+                                     CVMX_POW_TAG_TYPE_ATOMIC, 0);
+        }
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be
+ * called exactly once before this, and the same parameters must be
+ * passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @pko_command:
+ *               PKO HW command word
+ * @packet: Packet to send
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * Returns: CVMX_PKO_SUCCESS on success, or error code on
+ * failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
+        uint64_t port,
+        uint64_t queue,
+        union cvmx_pko_command_word0 pko_command,
+        union cvmx_buf_ptr packet,
+        cvmx_pko_lock_t use_locking)
+{
+        cvmx_cmd_queue_result_t result;
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+                cvmx_pow_tag_sw_wait();
+        result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
+                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                       pko_command.u64, packet.u64);
+        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
+                cvmx_pko_doorbell(port, queue, 2);
+                return CVMX_PKO_SUCCESS;
+        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
+                   || (result == CVMX_CMD_QUEUE_FULL)) {
+                return CVMX_PKO_NO_MEMORY;
+        } else {
+                return CVMX_PKO_INVALID_QUEUE;
+        }
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be
+ * called exactly once before this, and the same parameters must be
+ * passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @pko_command:
+ *               PKO HW command word
+ * @packet: Packet to send
+ * @addr: Plysical address of a work queue entry or physical address
+ *        to zero on complete.
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * Returns: CVMX_PKO_SUCCESS on success, or error code on
+ * failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
+        uint64_t port,
+        uint64_t queue,
+        union cvmx_pko_command_word0 pko_command,
+        union cvmx_buf_ptr packet,
+        uint64_t addr,
+        cvmx_pko_lock_t use_locking)
+{
+        cvmx_cmd_queue_result_t result;
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+                cvmx_pow_tag_sw_wait();
+        result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
+                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                       pko_command.u64, packet.u64, addr);
+        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
+                cvmx_pko_doorbell(port, queue, 3);
+                return CVMX_PKO_SUCCESS;
+        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
+                   || (result == CVMX_CMD_QUEUE_FULL)) {
+                return CVMX_PKO_NO_MEMORY;
+        } else {
+                return CVMX_PKO_INVALID_QUEUE;
+        }
+}
+
+/**
+ * Return the pko output queue associated with a port and a specific core.
+ * In normal mode (PKO lockless operation is disabled), the value returned
+ * is the base queue.
+ *
+ * @port:   Port number
+ * @core:   Core to get queue for
+ *
+ * Returns Core-specific output queue
+ */
+static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
+{
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
+#endif
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
+#endif
+
+        if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
+                return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
+        else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
+                                                           16) *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
+        else if ((port >= 32) && (port < 36))
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
+                                                           32) *
+                    CVMX_PKO_QUEUES_PER_PORT_PCI;
+        else if ((port >= 36) && (port < 40))
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+                    4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
+                                                        36) *
+                    CVMX_PKO_QUEUES_PER_PORT_LOOP;
+        else
+                /* Given the limit on the number of ports we can map to
+                 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
+                 * divided among all cores), the remaining unmapped ports
+                 * are assigned an illegal queue number */
+                return CVMX_PKO_ILLEGAL_QUEUE;
+}
+
+/**
+ * For a given port number, return the base pko output queue
+ * for the port.
+ *
+ * @port:   Port number
+ * Returns Base output queue
+ */
+static inline int cvmx_pko_get_base_queue(int port)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                return port;
+
+        return cvmx_pko_get_base_queue_per_core(port, 0);
+}
+
+/**
+ * For a given port number, return the number of pko output queues.
+ *
+ * @port:   Port number
+ * Returns Number of output queues
+ */
+static inline int cvmx_pko_get_num_queues(int port)
+{
+        if (port < 16)
+                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+        else if (port < 32)
+                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+        else if (port < 36)
+                return CVMX_PKO_QUEUES_PER_PORT_PCI;
+        else if (port < 40)
+                return CVMX_PKO_QUEUES_PER_PORT_LOOP;
+        else
+                return 0;
+}
+
+/**
+ * Get the status counters for a port.
+ *
+ * @port_num: Port number to get statistics for.
+ * @clear:    Set to 1 to clear the counters after they are read
+ * @status:   Where to put the results.
+ */
+static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
+                                            cvmx_pko_port_status_t *status)
+{
+        union cvmx_pko_reg_read_idx pko_reg_read_idx;
+        union cvmx_pko_mem_count0 pko_mem_count0;
+        union cvmx_pko_mem_count1 pko_mem_count1;
+
+        pko_reg_read_idx.u64 = 0;
+        pko_reg_read_idx.s.index = port_num;
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+
+        pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
+        status->packets = pko_mem_count0.s.count;
+        if (clear) {
+                pko_mem_count0.s.count = port_num;
+                cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
+        }
+
+        pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
+        status->octets = pko_mem_count1.s.count;
+        if (clear) {
+                pko_mem_count1.s.count = port_num;
+                cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
+        }
+
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_pko_mem_debug9 debug9;
+                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+                debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
+                status->doorbell = debug9.cn38xx.doorbell;
+        } else {
+                union cvmx_pko_mem_debug8 debug8;
+                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+                debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
+                status->doorbell = debug8.cn50xx.doorbell;
+        }
+}
+
+/**
+ * Rate limit a PKO port to a max packets/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @port:      Port to rate limit
+ * @packets_s: Maximum packet/sec
+ * @burst:     Maximum number of packets to burst in a row before rate
+ *                  limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
+
+/**
+ * Rate limit a PKO port to a max bits/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @port:   Port to rate limit
+ * @bits_s: PKO rate limit in bits/sec
+ * @burst:  Maximum number of bits to burst before rate
+ *               limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
+
+#endif /* __CVMX_PKO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
new file mode 100644
index 000000000..474dd5443
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -0,0 +1,1001 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_POW_DEFS_H__
+#define __CVMX_POW_DEFS_H__
+
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
+
+#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
+#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
+#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
+#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
+#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
+
+union cvmx_pow_bist_stat {
+        uint64_t u64;
+        struct cvmx_pow_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pp:16;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t pp:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_pow_bist_stat_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t pp:1;
+                uint64_t reserved_9_15:7;
+                uint64_t cam:1;
+                uint64_t nbt1:1;
+                uint64_t nbt0:1;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t nbr1:1;
+                uint64_t nbr0:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t nbr0:1;
+                uint64_t nbr1:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt0:1;
+                uint64_t nbt1:1;
+                uint64_t cam:1;
+                uint64_t reserved_9_15:7;
+                uint64_t pp:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } cn30xx;
+        struct cvmx_pow_bist_stat_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_18_63:46;
+                uint64_t pp:2;
+                uint64_t reserved_9_15:7;
+                uint64_t cam:1;
+                uint64_t nbt1:1;
+                uint64_t nbt0:1;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t nbr1:1;
+                uint64_t nbr0:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t nbr0:1;
+                uint64_t nbr1:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt0:1;
+                uint64_t nbt1:1;
+                uint64_t cam:1;
+                uint64_t reserved_9_15:7;
+                uint64_t pp:2;
+                uint64_t reserved_18_63:46;
+#endif
+        } cn31xx;
+        struct cvmx_pow_bist_stat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t pp:16;
+                uint64_t reserved_10_15:6;
+                uint64_t cam:1;
+                uint64_t nbt:1;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t nbr1:1;
+                uint64_t nbr0:1;
+                uint64_t pend1:1;
+                uint64_t pend0:1;
+                uint64_t adr1:1;
+                uint64_t adr0:1;
+#else
+                uint64_t adr0:1;
+                uint64_t adr1:1;
+                uint64_t pend0:1;
+                uint64_t pend1:1;
+                uint64_t nbr0:1;
+                uint64_t nbr1:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt:1;
+                uint64_t cam:1;
+                uint64_t reserved_10_15:6;
+                uint64_t pp:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn38xx;
+        struct cvmx_pow_bist_stat_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pp:4;
+                uint64_t reserved_9_15:7;
+                uint64_t cam:1;
+                uint64_t nbt1:1;
+                uint64_t nbt0:1;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t nbr1:1;
+                uint64_t nbr0:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t nbr0:1;
+                uint64_t nbr1:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt0:1;
+                uint64_t nbt1:1;
+                uint64_t cam:1;
+                uint64_t reserved_9_15:7;
+                uint64_t pp:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn52xx;
+        struct cvmx_pow_bist_stat_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t pp:12;
+                uint64_t reserved_10_15:6;
+                uint64_t cam:1;
+                uint64_t nbt:1;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t nbr1:1;
+                uint64_t nbr0:1;
+                uint64_t pend1:1;
+                uint64_t pend0:1;
+                uint64_t adr1:1;
+                uint64_t adr0:1;
+#else
+                uint64_t adr0:1;
+                uint64_t adr1:1;
+                uint64_t pend0:1;
+                uint64_t pend1:1;
+                uint64_t nbr0:1;
+                uint64_t nbr1:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt:1;
+                uint64_t cam:1;
+                uint64_t reserved_10_15:6;
+                uint64_t pp:12;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn56xx;
+        struct cvmx_pow_bist_stat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t pp:4;
+                uint64_t reserved_12_15:4;
+                uint64_t cam:1;
+                uint64_t nbr:3;
+                uint64_t nbt:4;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt:4;
+                uint64_t nbr:3;
+                uint64_t cam:1;
+                uint64_t reserved_12_15:4;
+                uint64_t pp:4;
+                uint64_t reserved_20_63:44;
+#endif
+        } cn61xx;
+        struct cvmx_pow_bist_stat_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t pp:6;
+                uint64_t reserved_12_15:4;
+                uint64_t cam:1;
+                uint64_t nbr:3;
+                uint64_t nbt:4;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt:4;
+                uint64_t nbr:3;
+                uint64_t cam:1;
+                uint64_t reserved_12_15:4;
+                uint64_t pp:6;
+                uint64_t reserved_22_63:42;
+#endif
+        } cn63xx;
+        struct cvmx_pow_bist_stat_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_26_63:38;
+                uint64_t pp:10;
+                uint64_t reserved_12_15:4;
+                uint64_t cam:1;
+                uint64_t nbr:3;
+                uint64_t nbt:4;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+#else
+                uint64_t adr:1;
+                uint64_t pend:1;
+                uint64_t fidx:1;
+                uint64_t index:1;
+                uint64_t nbt:4;
+                uint64_t nbr:3;
+                uint64_t cam:1;
+                uint64_t reserved_12_15:4;
+                uint64_t pp:10;
+                uint64_t reserved_26_63:38;
+#endif
+        } cn66xx;
+};
+
+union cvmx_pow_ds_pc {
+        uint64_t u64;
+        struct cvmx_pow_ds_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ds_pc:32;
+#else
+                uint64_t ds_pc:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_ecc_err {
+        uint64_t u64;
+        struct cvmx_pow_ecc_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t iop_ie:13;
+                uint64_t reserved_29_31:3;
+                uint64_t iop:13;
+                uint64_t reserved_14_15:2;
+                uint64_t rpe_ie:1;
+                uint64_t rpe:1;
+                uint64_t reserved_9_11:3;
+                uint64_t syn:5;
+                uint64_t dbe_ie:1;
+                uint64_t sbe_ie:1;
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+#else
+                uint64_t sbe:1;
+                uint64_t dbe:1;
+                uint64_t sbe_ie:1;
+                uint64_t dbe_ie:1;
+                uint64_t syn:5;
+                uint64_t reserved_9_11:3;
+                uint64_t rpe:1;
+                uint64_t rpe_ie:1;
+                uint64_t reserved_14_15:2;
+                uint64_t iop:13;
+                uint64_t reserved_29_31:3;
+                uint64_t iop_ie:13;
+                uint64_t reserved_45_63:19;
+#endif
+        } s;
+        struct cvmx_pow_ecc_err_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t rpe_ie:1;
+                uint64_t rpe:1;
+                uint64_t reserved_9_11:3;
+                uint64_t syn:5;
+                uint64_t dbe_ie:1;
+                uint64_t sbe_ie:1;
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+#else
+                uint64_t sbe:1;
+                uint64_t dbe:1;
+                uint64_t sbe_ie:1;
+                uint64_t dbe_ie:1;
+                uint64_t syn:5;
+                uint64_t reserved_9_11:3;
+                uint64_t rpe:1;
+                uint64_t rpe_ie:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } cn31xx;
+};
+
+union cvmx_pow_int_ctl {
+        uint64_t u64;
+        struct cvmx_pow_int_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t pfr_dis:1;
+                uint64_t nbr_thr:5;
+#else
+                uint64_t nbr_thr:5;
+                uint64_t pfr_dis:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_pow_iq_cntx {
+        uint64_t u64;
+        struct cvmx_pow_iq_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iq_cnt:32;
+#else
+                uint64_t iq_cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_iq_com_cnt {
+        uint64_t u64;
+        struct cvmx_pow_iq_com_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iq_cnt:32;
+#else
+                uint64_t iq_cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_iq_int {
+        uint64_t u64;
+        struct cvmx_pow_iq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t iq_int:8;
+#else
+                uint64_t iq_int:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pow_iq_int_en {
+        uint64_t u64;
+        struct cvmx_pow_iq_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t int_en:8;
+#else
+                uint64_t int_en:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pow_iq_thrx {
+        uint64_t u64;
+        struct cvmx_pow_iq_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iq_thr:32;
+#else
+                uint64_t iq_thr:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_nos_cnt {
+        uint64_t u64;
+        struct cvmx_pow_nos_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t nos_cnt:12;
+#else
+                uint64_t nos_cnt:12;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_pow_nos_cnt_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t nos_cnt:7;
+#else
+                uint64_t nos_cnt:7;
+                uint64_t reserved_7_63:57;
+#endif
+        } cn30xx;
+        struct cvmx_pow_nos_cnt_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t nos_cnt:9;
+#else
+                uint64_t nos_cnt:9;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn31xx;
+        struct cvmx_pow_nos_cnt_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t nos_cnt:10;
+#else
+                uint64_t nos_cnt:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } cn52xx;
+        struct cvmx_pow_nos_cnt_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t nos_cnt:11;
+#else
+                uint64_t nos_cnt:11;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pow_nw_tim {
+        uint64_t u64;
+        struct cvmx_pow_nw_tim_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t nw_tim:10;
+#else
+                uint64_t nw_tim:10;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_pow_pf_rst_msk {
+        uint64_t u64;
+        struct cvmx_pow_pf_rst_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t rst_msk:8;
+#else
+                uint64_t rst_msk:8;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_pow_pp_grp_mskx {
+        uint64_t u64;
+        struct cvmx_pow_pp_grp_mskx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t qos7_pri:4;
+                uint64_t qos6_pri:4;
+                uint64_t qos5_pri:4;
+                uint64_t qos4_pri:4;
+                uint64_t qos3_pri:4;
+                uint64_t qos2_pri:4;
+                uint64_t qos1_pri:4;
+                uint64_t qos0_pri:4;
+                uint64_t grp_msk:16;
+#else
+                uint64_t grp_msk:16;
+                uint64_t qos0_pri:4;
+                uint64_t qos1_pri:4;
+                uint64_t qos2_pri:4;
+                uint64_t qos3_pri:4;
+                uint64_t qos4_pri:4;
+                uint64_t qos5_pri:4;
+                uint64_t qos6_pri:4;
+                uint64_t qos7_pri:4;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_pow_pp_grp_mskx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t grp_msk:16;
+#else
+                uint64_t grp_msk:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn30xx;
+};
+
+union cvmx_pow_qos_rndx {
+        uint64_t u64;
+        struct cvmx_pow_qos_rndx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t rnd_p3:8;
+                uint64_t rnd_p2:8;
+                uint64_t rnd_p1:8;
+                uint64_t rnd:8;
+#else
+                uint64_t rnd:8;
+                uint64_t rnd_p1:8;
+                uint64_t rnd_p2:8;
+                uint64_t rnd_p3:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_qos_thrx {
+        uint64_t u64;
+        struct cvmx_pow_qos_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t des_cnt:12;
+                uint64_t buf_cnt:12;
+                uint64_t free_cnt:12;
+                uint64_t reserved_23_23:1;
+                uint64_t max_thr:11;
+                uint64_t reserved_11_11:1;
+                uint64_t min_thr:11;
+#else
+                uint64_t min_thr:11;
+                uint64_t reserved_11_11:1;
+                uint64_t max_thr:11;
+                uint64_t reserved_23_23:1;
+                uint64_t free_cnt:12;
+                uint64_t buf_cnt:12;
+                uint64_t des_cnt:12;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+        struct cvmx_pow_qos_thrx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_55_63:9;
+                uint64_t des_cnt:7;
+                uint64_t reserved_43_47:5;
+                uint64_t buf_cnt:7;
+                uint64_t reserved_31_35:5;
+                uint64_t free_cnt:7;
+                uint64_t reserved_18_23:6;
+                uint64_t max_thr:6;
+                uint64_t reserved_6_11:6;
+                uint64_t min_thr:6;
+#else
+                uint64_t min_thr:6;
+                uint64_t reserved_6_11:6;
+                uint64_t max_thr:6;
+                uint64_t reserved_18_23:6;
+                uint64_t free_cnt:7;
+                uint64_t reserved_31_35:5;
+                uint64_t buf_cnt:7;
+                uint64_t reserved_43_47:5;
+                uint64_t des_cnt:7;
+                uint64_t reserved_55_63:9;
+#endif
+        } cn30xx;
+        struct cvmx_pow_qos_thrx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_57_63:7;
+                uint64_t des_cnt:9;
+                uint64_t reserved_45_47:3;
+                uint64_t buf_cnt:9;
+                uint64_t reserved_33_35:3;
+                uint64_t free_cnt:9;
+                uint64_t reserved_20_23:4;
+                uint64_t max_thr:8;
+                uint64_t reserved_8_11:4;
+                uint64_t min_thr:8;
+#else
+                uint64_t min_thr:8;
+                uint64_t reserved_8_11:4;
+                uint64_t max_thr:8;
+                uint64_t reserved_20_23:4;
+                uint64_t free_cnt:9;
+                uint64_t reserved_33_35:3;
+                uint64_t buf_cnt:9;
+                uint64_t reserved_45_47:3;
+                uint64_t des_cnt:9;
+                uint64_t reserved_57_63:7;
+#endif
+        } cn31xx;
+        struct cvmx_pow_qos_thrx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_58_63:6;
+                uint64_t des_cnt:10;
+                uint64_t reserved_46_47:2;
+                uint64_t buf_cnt:10;
+                uint64_t reserved_34_35:2;
+                uint64_t free_cnt:10;
+                uint64_t reserved_21_23:3;
+                uint64_t max_thr:9;
+                uint64_t reserved_9_11:3;
+                uint64_t min_thr:9;
+#else
+                uint64_t min_thr:9;
+                uint64_t reserved_9_11:3;
+                uint64_t max_thr:9;
+                uint64_t reserved_21_23:3;
+                uint64_t free_cnt:10;
+                uint64_t reserved_34_35:2;
+                uint64_t buf_cnt:10;
+                uint64_t reserved_46_47:2;
+                uint64_t des_cnt:10;
+                uint64_t reserved_58_63:6;
+#endif
+        } cn52xx;
+        struct cvmx_pow_qos_thrx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_59_63:5;
+                uint64_t des_cnt:11;
+                uint64_t reserved_47_47:1;
+                uint64_t buf_cnt:11;
+                uint64_t reserved_35_35:1;
+                uint64_t free_cnt:11;
+                uint64_t reserved_22_23:2;
+                uint64_t max_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t min_thr:10;
+#else
+                uint64_t min_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t max_thr:10;
+                uint64_t reserved_22_23:2;
+                uint64_t free_cnt:11;
+                uint64_t reserved_35_35:1;
+                uint64_t buf_cnt:11;
+                uint64_t reserved_47_47:1;
+                uint64_t des_cnt:11;
+                uint64_t reserved_59_63:5;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pow_ts_pc {
+        uint64_t u64;
+        struct cvmx_pow_ts_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ts_pc:32;
+#else
+                uint64_t ts_pc:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_wa_com_pc {
+        uint64_t u64;
+        struct cvmx_pow_wa_com_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wa_pc:32;
+#else
+                uint64_t wa_pc:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_wa_pcx {
+        uint64_t u64;
+        struct cvmx_pow_wa_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t wa_pc:32;
+#else
+                uint64_t wa_pc:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_wq_int {
+        uint64_t u64;
+        struct cvmx_pow_wq_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t iq_dis:16;
+                uint64_t wq_int:16;
+#else
+                uint64_t wq_int:16;
+                uint64_t iq_dis:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_pow_wq_int_cntx {
+        uint64_t u64;
+        struct cvmx_pow_wq_int_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t ds_cnt:12;
+                uint64_t iq_cnt:12;
+#else
+                uint64_t iq_cnt:12;
+                uint64_t ds_cnt:12;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+        struct cvmx_pow_wq_int_cntx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_19_23:5;
+                uint64_t ds_cnt:7;
+                uint64_t reserved_7_11:5;
+                uint64_t iq_cnt:7;
+#else
+                uint64_t iq_cnt:7;
+                uint64_t reserved_7_11:5;
+                uint64_t ds_cnt:7;
+                uint64_t reserved_19_23:5;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn30xx;
+        struct cvmx_pow_wq_int_cntx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_21_23:3;
+                uint64_t ds_cnt:9;
+                uint64_t reserved_9_11:3;
+                uint64_t iq_cnt:9;
+#else
+                uint64_t iq_cnt:9;
+                uint64_t reserved_9_11:3;
+                uint64_t ds_cnt:9;
+                uint64_t reserved_21_23:3;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn31xx;
+        struct cvmx_pow_wq_int_cntx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_22_23:2;
+                uint64_t ds_cnt:10;
+                uint64_t reserved_10_11:2;
+                uint64_t iq_cnt:10;
+#else
+                uint64_t iq_cnt:10;
+                uint64_t reserved_10_11:2;
+                uint64_t ds_cnt:10;
+                uint64_t reserved_22_23:2;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn52xx;
+        struct cvmx_pow_wq_int_cntx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_23_23:1;
+                uint64_t ds_cnt:11;
+                uint64_t reserved_11_11:1;
+                uint64_t iq_cnt:11;
+#else
+                uint64_t iq_cnt:11;
+                uint64_t reserved_11_11:1;
+                uint64_t ds_cnt:11;
+                uint64_t reserved_23_23:1;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pow_wq_int_pc {
+        uint64_t u64;
+        struct cvmx_pow_wq_int_pc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_60_63:4;
+                uint64_t pc:28;
+                uint64_t reserved_28_31:4;
+                uint64_t pc_thr:20;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t pc_thr:20;
+                uint64_t reserved_28_31:4;
+                uint64_t pc:28;
+                uint64_t reserved_60_63:4;
+#endif
+        } s;
+};
+
+union cvmx_pow_wq_int_thrx {
+        uint64_t u64;
+        struct cvmx_pow_wq_int_thrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_23_23:1;
+                uint64_t ds_thr:11;
+                uint64_t reserved_11_11:1;
+                uint64_t iq_thr:11;
+#else
+                uint64_t iq_thr:11;
+                uint64_t reserved_11_11:1;
+                uint64_t ds_thr:11;
+                uint64_t reserved_23_23:1;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } s;
+        struct cvmx_pow_wq_int_thrx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_18_23:6;
+                uint64_t ds_thr:6;
+                uint64_t reserved_6_11:6;
+                uint64_t iq_thr:6;
+#else
+                uint64_t iq_thr:6;
+                uint64_t reserved_6_11:6;
+                uint64_t ds_thr:6;
+                uint64_t reserved_18_23:6;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn30xx;
+        struct cvmx_pow_wq_int_thrx_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_20_23:4;
+                uint64_t ds_thr:8;
+                uint64_t reserved_8_11:4;
+                uint64_t iq_thr:8;
+#else
+                uint64_t iq_thr:8;
+                uint64_t reserved_8_11:4;
+                uint64_t ds_thr:8;
+                uint64_t reserved_20_23:4;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn31xx;
+        struct cvmx_pow_wq_int_thrx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_21_23:3;
+                uint64_t ds_thr:9;
+                uint64_t reserved_9_11:3;
+                uint64_t iq_thr:9;
+#else
+                uint64_t iq_thr:9;
+                uint64_t reserved_9_11:3;
+                uint64_t ds_thr:9;
+                uint64_t reserved_21_23:3;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn52xx;
+        struct cvmx_pow_wq_int_thrx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_22_23:2;
+                uint64_t ds_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t iq_thr:10;
+#else
+                uint64_t iq_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t ds_thr:10;
+                uint64_t reserved_22_23:2;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_29_63:35;
+#endif
+        } cn63xx;
+};
+
+union cvmx_pow_ws_pcx {
+        uint64_t u64;
+        struct cvmx_pow_ws_pcx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t ws_pc:32;
+#else
+                uint64_t ws_pc:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sso_wq_int_thrx {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_26_27:2;
+                uint64_t ds_thr:12;
+                uint64_t reserved_12_13:2;
+                uint64_t iq_thr:12;
+#else
+                uint64_t iq_thr:12;
+                uint64_t reserved_12_13:2;
+                uint64_t ds_thr:12;
+                uint64_t reserved_26_27:2;
+                uint64_t tc_thr:4;
+                uint64_t tc_en:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
new file mode 100644
index 000000000..a3b23811e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -0,0 +1,2215 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * Interface to the hardware Packet Order / Work unit.
+ *
+ * New, starting with SDK 1.7.0, cvmx-pow supports a number of
+ * extended consistency checks. The define
+ * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
+ * internal state checks to find common programming errors. If
+ * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
+ * enabled. For example, cvmx-pow will check for the following
+ * program errors or POW state inconsistency.
+ * - Requesting a POW operation with an active tag switch in
+ *   progress.
+ * - Waiting for a tag switch to complete for an excessively
+ *   long period. This is normally a sign of an error in locking
+ *   causing deadlock.
+ * - Illegal tag switches from NULL_NULL.
+ * - Illegal tag switches from NULL.
+ * - Illegal deschedule request.
+ * - WQE pointer not matching the one attached to the core by
+ *   the POW.
+ *
+ */
+
+#ifndef __CVMX_POW_H__
+#define __CVMX_POW_H__
+
+#include <asm/octeon/cvmx-pow-defs.h>
+
+#include <asm/octeon/cvmx-scratch.h>
+#include <asm/octeon/cvmx-wqe.h>
+
+/* Default to having all POW constancy checks turned on */
+#ifndef CVMX_ENABLE_POW_CHECKS
+#define CVMX_ENABLE_POW_CHECKS 1
+#endif
+
+enum cvmx_pow_tag_type {
+        /* Tag ordering is maintained */
+        CVMX_POW_TAG_TYPE_ORDERED   = 0L,
+        /* Tag ordering is maintained, and at most one PP has the tag */
+        CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
+        /*
+         * The work queue entry from the order - NEVER tag switch from
+         * NULL to NULL
+         */
+        CVMX_POW_TAG_TYPE_NULL      = 2L,
+        /* A tag switch to NULL, and there is no space reserved in POW
+         * - NEVER tag switch to NULL_NULL
+         * - NEVER tag switch from NULL_NULL
+         * - NULL_NULL is entered at the beginning of time and on a deschedule.
+         * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
+         * load can also switch the state to NULL
+         */
+        CVMX_POW_TAG_TYPE_NULL_NULL = 3L
+};
+
+/**
+ * Wait flag values for pow functions.
+ */
+typedef enum {
+        CVMX_POW_WAIT = 1,
+        CVMX_POW_NO_WAIT = 0,
+} cvmx_pow_wait_t;
+
+/**
+ *  POW tag operations.  These are used in the data stored to the POW.
+ */
+typedef enum {
+        /*
+         * switch the tag (only) for this PP
+         * - the previous tag should be non-NULL in this case
+         * - tag switch response required
+         * - fields used: op, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG = 0L,
+        /*
+         * switch the tag for this PP, with full information
+         * - this should be used when the previous tag is NULL
+         * - tag switch response required
+         * - fields used: address, op, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
+        /*
+         * switch the tag (and/or group) for this PP and de-schedule
+         * - OK to keep the tag the same and only change the group
+         * - fields used: op, no_sched, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
+        /*
+         * just de-schedule
+         * - fields used: op, no_sched
+         */
+        CVMX_POW_TAG_OP_DESCH = 3L,
+        /*
+         * create an entirely new work queue entry
+         * - fields used: address, op, qos, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_ADDWQ = 4L,
+        /*
+         * just update the work queue pointer and grp for this PP
+         * - fields used: address, op, grp
+         */
+        CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
+        /*
+         * set the no_sched bit on the de-schedule list
+         *
+         * - does nothing if the selected entry is not on the
+         *   de-schedule list
+         *
+         * - does nothing if the stored work queue pointer does not
+         *   match the address field
+         *
+         * - fields used: address, index, op
+         *
+         *  Before issuing a *_NSCHED operation, SW must guarantee
+         *  that all prior deschedules and set/clr NSCHED operations
+         *  are complete and all prior switches are complete. The
+         *  hardware provides the opsdone bit and swdone bit for SW
+         *  polling. After issuing a *_NSCHED operation, SW must
+         *  guarantee that the set/clr NSCHED is complete before any
+         *  subsequent operations.
+         */
+        CVMX_POW_TAG_OP_SET_NSCHED = 6L,
+        /*
+         * clears the no_sched bit on the de-schedule list
+         *
+         * - does nothing if the selected entry is not on the
+         *   de-schedule list
+         *
+         * - does nothing if the stored work queue pointer does not
+         *   match the address field
+         *
+         * - fields used: address, index, op
+         *
+         * Before issuing a *_NSCHED operation, SW must guarantee that
+         * all prior deschedules and set/clr NSCHED operations are
+         * complete and all prior switches are complete. The hardware
+         * provides the opsdone bit and swdone bit for SW
+         * polling. After issuing a *_NSCHED operation, SW must
+         * guarantee that the set/clr NSCHED is complete before any
+         * subsequent operations.
+         */
+        CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
+        /* do nothing */
+        CVMX_POW_TAG_OP_NOP = 15L
+} cvmx_pow_tag_op_t;
+
+/**
+ * This structure defines the store data on a store to POW
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * Don't reschedule this entry. no_sched is used for
+                 * CVMX_POW_TAG_OP_SWTAG_DESCH and
+                 * CVMX_POW_TAG_OP_DESCH
+                 */
+                uint64_t no_sched:1;
+                uint64_t unused:2;
+                /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
+                uint64_t index:13;
+                /* The operation to perform */
+                cvmx_pow_tag_op_t op:4;
+                uint64_t unused2:2;
+                /*
+                 * The QOS level for the packet. qos is only used for
+                 * CVMX_POW_TAG_OP_ADDWQ
+                 */
+                uint64_t qos:3;
+                /*
+                 * The group that the work queue entry will be
+                 * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
+                 * CVMX_POW_TAG_OP_SWTAG_FULL,
+                 * CVMX_POW_TAG_OP_SWTAG_DESCH, and
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP
+                 */
+                uint64_t grp:4;
+                /*
+                 * The type of the tag. type is used for everything
+                 * except CVMX_POW_TAG_OP_DESCH,
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
+                 * CVMX_POW_TAG_OP_*_NSCHED
+                 */
+                uint64_t type:3;
+                /*
+                 * The actual tag. tag is used for everything except
+                 * CVMX_POW_TAG_OP_DESCH,
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
+                 * CVMX_POW_TAG_OP_*_NSCHED
+                 */
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t type:3;
+                uint64_t grp:4;
+                uint64_t qos:3;
+                uint64_t unused2:2;
+                cvmx_pow_tag_op_t op:4;
+                uint64_t index:13;
+                uint64_t unused:2;
+                uint64_t no_sched:1;
+#endif
+        } s;
+} cvmx_pow_tag_req_t;
+
+/**
+ * This structure describes the address to load stuff from POW
+ */
+typedef union {
+        uint64_t u64;
+
+    /**
+     * Address for new work request loads (did<2:0> == 0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 0 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_4_39:36;
+                /*
+                 * If set, don't return load response until work is
+                 * available.
+                 */
+                uint64_t wait:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t wait:1;
+                uint64_t reserved_4_39:36;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
+        } swork;
+
+    /**
+     * Address for loads to get POW internal status
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 1 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_10_39:30;
+                /* The core id to get status for */
+                uint64_t coreid:4;
+                /*
+                 * If set and get_cur is set, return reverse tag-list
+                 * pointer rather than forward tag-list pointer.
+                 */
+                uint64_t get_rev:1;
+                /*
+                 * If set, return current status rather than pending
+                 * status.
+                 */
+                uint64_t get_cur:1;
+                /*
+                 * If set, get the work-queue pointer rather than
+                 * tag/type.
+                 */
+                uint64_t get_wqp:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_wqp:1;
+                uint64_t get_cur:1;
+                uint64_t get_rev:1;
+                uint64_t coreid:4;
+                uint64_t reserved_10_39:30;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
+        } sstatus;
+
+    /**
+     * Address for memory loads to get POW internal state
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 2 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_16_39:24;
+                /* POW memory index */
+                uint64_t index:11;
+                /*
+                 * If set, return deschedule information rather than
+                 * the standard response for work-queue index (invalid
+                 * if the work-queue entry is not on the deschedule
+                 * list).
+                 */
+                uint64_t get_des:1;
+                /*
+                 * If set, get the work-queue pointer rather than
+                 * tag/type (no effect when get_des set).
+                 */
+                uint64_t get_wqp:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_wqp:1;
+                uint64_t get_des:1;
+                uint64_t index:11;
+                uint64_t reserved_16_39:24;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
+        } smemload;
+
+    /**
+     * Address for index/pointer loads
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 3 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_9_39:31;
+                /*
+                 * when {get_rmt ==0 AND get_des_get_tail == 0}, this
+                 * field selects one of eight POW internal-input
+                 * queues (0-7), one per QOS level; values 8-15 are
+                 * illegal in this case; when {get_rmt ==0 AND
+                 * get_des_get_tail == 1}, this field selects one of
+                 * 16 deschedule lists (per group); when get_rmt ==1,
+                 * this field selects one of 16 memory-input queue
+                 * lists.  The two memory-input queue lists associated
+                 * with each QOS level are:
+                 *
+                 * - qosgrp = 0, qosgrp = 8:      QOS0
+                 * - qosgrp = 1, qosgrp = 9:      QOS1
+                 * - qosgrp = 2, qosgrp = 10:     QOS2
+                 * - qosgrp = 3, qosgrp = 11:     QOS3
+                 * - qosgrp = 4, qosgrp = 12:     QOS4
+                 * - qosgrp = 5, qosgrp = 13:     QOS5
+                 * - qosgrp = 6, qosgrp = 14:     QOS6
+                 * - qosgrp = 7, qosgrp = 15:     QOS7
+                 */
+                uint64_t qosgrp:4;
+                /*
+                 * If set and get_rmt is clear, return deschedule list
+                 * indexes rather than indexes for the specified qos
+                 * level; if set and get_rmt is set, return the tail
+                 * pointer rather than the head pointer for the
+                 * specified qos level.
+                 */
+                uint64_t get_des_get_tail:1;
+                /*
+                 * If set, return remote pointers rather than the
+                 * local indexes for the specified qos level.
+                 */
+                uint64_t get_rmt:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_rmt:1;
+                uint64_t get_des_get_tail:1;
+                uint64_t qosgrp:4;
+                uint64_t reserved_9_39:31;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
+        } sindexload;
+
+    /**
+     * address for NULL_RD request (did<2:0> == 4) when this is read,
+     * HW attempts to change the state to NULL if it is NULL_NULL (the
+     * hardware cannot switch from NULL_NULL to NULL if a POW entry is
+     * not available - software may need to recover by finishing
+     * another piece of work before a POW entry can ever become
+     * available.)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 4 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_0_39:40;
+#else
+                uint64_t reserved_0_39:40;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
+        } snull_rd;
+} cvmx_pow_load_addr_t;
+
+/**
+ * This structure defines the response to a load/SENDSINGLE to POW
+ * (except CSR reads)
+ */
+typedef union {
+        uint64_t u64;
+
+    /**
+     * Response to new work request loads
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * Set when no new work queue entry was returned.  *
+                 * If there was de-scheduled work, the HW will
+                 * definitely return it. When this bit is set, it
+                 * could mean either mean:
+                 *
+                 * - There was no work, or
+                 *
+                 * - There was no work that the HW could find. This
+                 *   case can happen, regardless of the wait bit value
+                 *   in the original request, when there is work in
+                 *   the IQ's that is too deep down the list.
+                 */
+                uint64_t no_work:1;
+                /* Must be zero */
+                uint64_t reserved_40_62:23;
+                /* 36 in O1 -- the work queue pointer */
+                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t reserved_40_62:23;
+                uint64_t no_work:1;
+#endif
+        } s_work;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /* Set when there is a pending non-NULL SWTAG or
+                 * SWTAG_FULL, and the POW entry has not left the list
+                 * for the original tag. */
+                uint64_t pend_switch:1;
+                /* Set when SWTAG_FULL and pend_switch is set. */
+                uint64_t pend_switch_full:1;
+                /*
+                 * Set when there is a pending NULL SWTAG, or an
+                 * implicit switch to NULL.
+                 */
+                uint64_t pend_switch_null:1;
+                /* Set when there is a pending DESCHED or SWTAG_DESCHED. */
+                uint64_t pend_desched:1;
+                /*
+                 * Set when there is a pending SWTAG_DESCHED and
+                 * pend_desched is set.
+                 */
+                uint64_t pend_desched_switch:1;
+                /* Set when nosched is desired and pend_desched is set. */
+                uint64_t pend_nosched:1;
+                /* Set when there is a pending GET_WORK. */
+                uint64_t pend_new_work:1;
+                /*
+                 * When pend_new_work is set, this bit indicates that
+                 * the wait bit was set.
+                 */
+                uint64_t pend_new_work_wait:1;
+                /* Set when there is a pending NULL_RD. */
+                uint64_t pend_null_rd:1;
+                /* Set when there is a pending CLR_NSCHED. */
+                uint64_t pend_nosched_clr:1;
+                uint64_t reserved_51:1;
+                /* This is the index when pend_nosched_clr is set. */
+                uint64_t pend_index:11;
+                /*
+                 * This is the new_grp when (pend_desched AND
+                 * pend_desched_switch) is set.
+                 */
+                uint64_t pend_grp:4;
+                uint64_t reserved_34_35:2;
+                /*
+                 * This is the tag type when pend_switch or
+                 * (pend_desched AND pend_desched_switch) are set.
+                 */
+                uint64_t pend_type:2;
+                /*
+                 * - this is the tag when pend_switch or (pend_desched
+                 *    AND pend_desched_switch) are set.
+                 */
+                uint64_t pend_tag:32;
+#else
+                uint64_t pend_tag:32;
+                uint64_t pend_type:2;
+                uint64_t reserved_34_35:2;
+                uint64_t pend_grp:4;
+                uint64_t pend_index:11;
+                uint64_t reserved_51:1;
+                uint64_t pend_nosched_clr:1;
+                uint64_t pend_null_rd:1;
+                uint64_t pend_new_work_wait:1;
+                uint64_t pend_new_work:1;
+                uint64_t pend_nosched:1;
+                uint64_t pend_desched_switch:1;
+                uint64_t pend_desched:1;
+                uint64_t pend_switch_null:1;
+                uint64_t pend_switch_full:1;
+                uint64_t pend_switch:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus0;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /*
+                 * Set when there is a pending non-NULL SWTAG or
+                 * SWTAG_FULL, and the POW entry has not left the list
+                 * for the original tag.
+                 */
+                uint64_t pend_switch:1;
+                /* Set when SWTAG_FULL and pend_switch is set. */
+                uint64_t pend_switch_full:1;
+                /*
+                 * Set when there is a pending NULL SWTAG, or an
+                 * implicit switch to NULL.
+                 */
+                uint64_t pend_switch_null:1;
+                /*
+                 * Set when there is a pending DESCHED or
+                 * SWTAG_DESCHED.
+                 */
+                uint64_t pend_desched:1;
+                /*
+                 * Set when there is a pending SWTAG_DESCHED and
+                 * pend_desched is set.
+                 */
+                uint64_t pend_desched_switch:1;
+                /* Set when nosched is desired and pend_desched is set. */
+                uint64_t pend_nosched:1;
+                /* Set when there is a pending GET_WORK. */
+                uint64_t pend_new_work:1;
+                /*
+                 * When pend_new_work is set, this bit indicates that
+                 * the wait bit was set.
+                 */
+                uint64_t pend_new_work_wait:1;
+                /* Set when there is a pending NULL_RD. */
+                uint64_t pend_null_rd:1;
+                /* Set when there is a pending CLR_NSCHED. */
+                uint64_t pend_nosched_clr:1;
+                uint64_t reserved_51:1;
+                /* This is the index when pend_nosched_clr is set. */
+                uint64_t pend_index:11;
+                /*
+                 * This is the new_grp when (pend_desched AND
+                 * pend_desched_switch) is set.
+                 */
+                uint64_t pend_grp:4;
+                /* This is the wqp when pend_nosched_clr is set. */
+                uint64_t pend_wqp:36;
+#else
+                uint64_t pend_wqp:36;
+                uint64_t pend_grp:4;
+                uint64_t pend_index:11;
+                uint64_t reserved_51:1;
+                uint64_t pend_nosched_clr:1;
+                uint64_t pend_null_rd:1;
+                uint64_t pend_new_work_wait:1;
+                uint64_t pend_new_work:1;
+                uint64_t pend_nosched:1;
+                uint64_t pend_desched_switch:1;
+                uint64_t pend_desched:1;
+                uint64_t pend_switch_null:1;
+                uint64_t pend_switch_full:1;
+                uint64_t pend_switch:1;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus1;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and
+     * get_rev==0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the next POW entry in the tag list when
+                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
+                 */
+                uint64_t link_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * Set when this POW entry is at the head of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t head:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /*
+                 * The tag type attached to the core (updated when new
+                 * tag list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag_type:2;
+                /*
+                 * The tag attached to the core (updated when new tag
+                 * list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t head:1;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t link_index:11;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus2;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the prior POW entry in the tag list when
+                 * head == 0 (and tag_type is not NULL or
+                 * NULL_NULL). This field is unpredictable when the
+                 * core's state is NULL or NULL_NULL.
+                 */
+                uint64_t revlink_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /* Set when this POW entry is at the head of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t head:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /*
+                 * The tag type attached to the core (updated when new
+                 * tag list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag_type:2;
+                /*
+                 * The tag attached to the core (updated when new tag
+                 * list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t head:1;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t revlink_index:11;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus3;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
+     * get_rev==0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the next POW entry in the tag list when
+                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
+                 */
+                uint64_t link_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * The wqp attached to the core (updated when new tag
+                 * list entered on SWTAG_FULL).
+                 */
+                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t link_index:11;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus4;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
+     * get_rev==1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the prior POW entry in the tag list when
+                 * head == 0 (and tag_type is not NULL or
+                 * NULL_NULL). This field is unpredictable when the
+                 * core's state is NULL or NULL_NULL.
+                 */
+                uint64_t revlink_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * The wqp attached to the core (updated when new tag
+                 * list entered on SWTAG_FULL).
+                 */
+                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t revlink_index:11;
+                uint64_t reserved_62_63:2;
+#endif
+        } s_sstatus5;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the input, free, descheduled_head
+                 * list (unpredictable if entry is the tail of the
+                 * list).
+                 */
+                uint64_t next_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                uint64_t reserved_35:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /* The tag type of the POW entry. */
+                uint64_t tag_type:2;
+                /* The tag of the POW entry. */
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t reserved_35:1;
+                uint64_t grp:4;
+                uint64_t next_index:11;
+                uint64_t reserved_51_63:13;
+#endif
+        } s_smemload0;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the input, free, descheduled_head
+                 * list (unpredictable if entry is the tail of the
+                 * list).
+                 */
+                uint64_t next_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                /* The WQP held in the POW entry. */
+                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t next_index:11;
+                uint64_t reserved_51_63:13;
+#endif
+        } s_smemload1;
+
+    /**
+     * Result For POW Memory Load (get_des == 1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the tag list connected to the
+                 * descheduled head.
+                 */
+                uint64_t fwd_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                /* The nosched bit for the POW entry. */
+                uint64_t nosched:1;
+                /* There is a pending tag switch */
+                uint64_t pend_switch:1;
+                /*
+                 * The next tag type for the new tag list when
+                 * pend_switch is set.
+                 */
+                uint64_t pend_type:2;
+                /*
+                 * The next tag for the new tag list when pend_switch
+                 * is set.
+                 */
+                uint64_t pend_tag:32;
+#else
+                uint64_t pend_tag:32;
+                uint64_t pend_type:2;
+                uint64_t pend_switch:1;
+                uint64_t nosched:1;
+                uint64_t grp:4;
+                uint64_t fwd_index:11;
+                uint64_t reserved_51_63:13;
+#endif
+        } s_smemload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                /*
+                 * set when there is one or more POW entries on the
+                 * free list.
+                 */
+                uint64_t free_val:1;
+                /*
+                 * set when there is exactly one POW entry on the free
+                 * list.
+                 */
+                uint64_t free_one:1;
+                uint64_t reserved_49:1;
+                /*
+                 * when free_val is set, indicates the first entry on
+                 * the free list.
+                 */
+                uint64_t free_head:11;
+                uint64_t reserved_37:1;
+                /*
+                 * when free_val is set, indicates the last entry on
+                 * the free list.
+                 */
+                uint64_t free_tail:11;
+                /*
+                 * set when there is one or more POW entries on the
+                 * input Q list selected by qosgrp.
+                 */
+                uint64_t loc_val:1;
+                /*
+                 * set when there is exactly one POW entry on the
+                 * input Q list selected by qosgrp.
+                 */
+                uint64_t loc_one:1;
+                uint64_t reserved_23:1;
+                /*
+                 * when loc_val is set, indicates the first entry on
+                 * the input Q list selected by qosgrp.
+                 */
+                uint64_t loc_head:11;
+                uint64_t reserved_11:1;
+                /*
+                 * when loc_val is set, indicates the last entry on
+                 * the input Q list selected by qosgrp.
+                 */
+                uint64_t loc_tail:11;
+#else
+                uint64_t loc_tail:11;
+                uint64_t reserved_11:1;
+                uint64_t loc_head:11;
+                uint64_t reserved_23:1;
+                uint64_t loc_one:1;
+                uint64_t loc_val:1;
+                uint64_t free_tail:11;
+                uint64_t reserved_37:1;
+                uint64_t free_head:11;
+                uint64_t reserved_49:1;
+                uint64_t free_one:1;
+                uint64_t free_val:1;
+                uint64_t reserved_52_63:12;
+#endif
+        } sindexload0;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_52_63:12;
+                /*
+                 * set when there is one or more POW entries on the
+                 * nosched list.
+                 */
+                uint64_t nosched_val:1;
+                /*
+                 * set when there is exactly one POW entry on the
+                 * nosched list.
+                 */
+                uint64_t nosched_one:1;
+                uint64_t reserved_49:1;
+                /*
+                 * when nosched_val is set, indicates the first entry
+                 * on the nosched list.
+                 */
+                uint64_t nosched_head:11;
+                uint64_t reserved_37:1;
+                /*
+                 * when nosched_val is set, indicates the last entry
+                 * on the nosched list.
+                 */
+                uint64_t nosched_tail:11;
+                /*
+                 * set when there is one or more descheduled heads on
+                 * the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_val:1;
+                /*
+                 * set when there is exactly one descheduled head on
+                 * the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_one:1;
+                uint64_t reserved_23:1;
+                /*
+                 * when des_val is set, indicates the first
+                 * descheduled head on the descheduled list selected
+                 * by qosgrp.
+                 */
+                uint64_t des_head:11;
+                uint64_t reserved_11:1;
+                /*
+                 * when des_val is set, indicates the last descheduled
+                 * head on the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_tail:11;
+#else
+                uint64_t des_tail:11;
+                uint64_t reserved_11:1;
+                uint64_t des_head:11;
+                uint64_t reserved_23:1;
+                uint64_t des_one:1;
+                uint64_t des_val:1;
+                uint64_t nosched_tail:11;
+                uint64_t reserved_37:1;
+                uint64_t nosched_head:11;
+                uint64_t reserved_49:1;
+                uint64_t nosched_one:1;
+                uint64_t nosched_val:1;
+                uint64_t reserved_52_63:12;
+#endif
+        } sindexload1;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                /*
+                 * Set when this DRAM list is the current head
+                 * (i.e. is the next to be reloaded when the POW
+                 * hardware reloads a POW entry from DRAM). The POW
+                 * hardware alternates between the two DRAM lists
+                 * associated with a QOS level when it reloads work
+                 * from DRAM into the POW unit.
+                 */
+                uint64_t rmt_is_head:1;
+                /*
+                 * Set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains one or more pieces of
+                 * work.
+                 */
+                uint64_t rmt_val:1;
+                /*
+                 * Set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains exactly one piece of
+                 * work.
+                 */
+                uint64_t rmt_one:1;
+                /*
+                 * When rmt_val is set, indicates the first piece of
+                 * work on the DRAM input Q list selected by
+                 * qosgrp.
+                 */
+                uint64_t rmt_head:36;
+#else
+                uint64_t rmt_head:36;
+                uint64_t rmt_one:1;
+                uint64_t rmt_val:1;
+                uint64_t rmt_is_head:1;
+                uint64_t reserved_39_63:25;
+#endif
+        } sindexload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt ==
+     * 1/get_des_get_tail == 1)
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_39_63:25;
+                /*
+                 * set when this DRAM list is the current head
+                 * (i.e. is the next to be reloaded when the POW
+                 * hardware reloads a POW entry from DRAM). The POW
+                 * hardware alternates between the two DRAM lists
+                 * associated with a QOS level when it reloads work
+                 * from DRAM into the POW unit.
+                 */
+                uint64_t rmt_is_head:1;
+                /*
+                 * set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains one or more pieces of
+                 * work.
+                 */
+                uint64_t rmt_val:1;
+                /*
+                 * set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains exactly one piece of
+                 * work.
+                 */
+                uint64_t rmt_one:1;
+                /*
+                 * when rmt_val is set, indicates the last piece of
+                 * work on the DRAM input Q list selected by
+                 * qosgrp.
+                 */
+                uint64_t rmt_tail:36;
+#else
+                uint64_t rmt_tail:36;
+                uint64_t rmt_one:1;
+                uint64_t rmt_val:1;
+                uint64_t rmt_is_head:1;
+                uint64_t reserved_39_63:25;
+#endif
+        } sindexload3;
+
+    /**
+     * Response to NULL_RD request loads
+     */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t unused:62;
+                /* of type cvmx_pow_tag_type_t. state is one of the
+                 * following:
+                 *
+                 * - CVMX_POW_TAG_TYPE_ORDERED
+                 * - CVMX_POW_TAG_TYPE_ATOMIC
+                 * - CVMX_POW_TAG_TYPE_NULL
+                 * - CVMX_POW_TAG_TYPE_NULL_NULL
+                 */
+                uint64_t state:2;
+#else
+                uint64_t state:2;
+                uint64_t unused:62;
+#endif
+        } s_null_rd;
+
+} cvmx_pow_tag_load_resp_t;
+
+/**
+ * This structure describes the address used for stores to the POW.
+ *  The store address is meaningful on stores to the POW.  The
+ *  hardware assumes that an aligned 64-bit store was used for all
+ *  these stores.  Note the assumption that the work queue entry is
+ *  aligned on an 8-byte boundary (since the low-order 3 address bits
+ *  must be zero).  Note that not all fields are used by all
+ *  operations.
+ *
+ *  NOTE: The following is the behavior of the pending switch bit at the PP
+ *       for POW stores (i.e. when did<7:3> == 0xc)
+ *     - did<2:0> == 0      => pending switch bit is set
+ *     - did<2:0> == 1      => no affect on the pending switch bit
+ *     - did<2:0> == 3      => pending switch bit is cleared
+ *     - did<2:0> == 7      => no affect on the pending switch bit
+ *     - did<2:0> == others => must not be used
+ *     - No other loads/stores have an affect on the pending switch bit
+ *     - The switch bus from POW can clear the pending switch bit
+ *
+ *  NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
+ *  ADDWQ command that only contains the pointer). SW must never use
+ *  did<2:0> == 2.
+ */
+typedef union {
+    /**
+     * Unsigned 64 bit integer representation of store address
+     */
+        uint64_t u64;
+
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* Memory region.  Should be CVMX_IO_SEG in most cases */
+                uint64_t mem_reg:2;
+                uint64_t reserved_49_61:13;     /* Must be zero */
+                uint64_t is_io:1;       /* Must be one */
+                /* Device ID of POW.  Note that different sub-dids are used. */
+                uint64_t did:8;
+                uint64_t reserved_36_39:4;      /* Must be zero */
+                /* Address field. addr<2:0> must be zero */
+                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t reserved_36_39:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_reg:2;
+#endif
+        } stag;
+} cvmx_pow_tag_store_addr_t;
+
+/**
+ * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
+ */
+typedef union {
+        uint64_t u64;
+
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * the (64-bit word) location in scratchpad to write
+                 * to (if len != 0)
+                 */
+                uint64_t scraddr:8;
+                /* the number of words in the response (0 => no response) */
+                uint64_t len:8;
+                /* the ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                uint64_t unused:36;
+                /* if set, don't return load response until work is available */
+                uint64_t wait:1;
+                uint64_t unused2:3;
+#else
+                uint64_t unused2:3;
+                uint64_t wait:1;
+                uint64_t unused:36;
+                uint64_t did:8;
+                uint64_t len:8;
+                uint64_t scraddr:8;
+#endif
+        } s;
+
+} cvmx_pow_iobdma_store_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Get the POW tag for this core. This returns the current
+ * tag type, tag, group, and POW entry index associated with
+ * this core. Index is only valid if the tag type isn't NULL_NULL.
+ * If a tag switch is pending this routine returns the tag before
+ * the tag switch, not after.
+ *
+ * Returns Current tag
+ */
+static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
+{
+        cvmx_pow_load_addr_t load_addr;
+        cvmx_pow_tag_load_resp_t load_resp;
+        cvmx_pow_tag_req_t result;
+
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        result.u64 = 0;
+        result.s.grp = load_resp.s_sstatus2.grp;
+        result.s.index = load_resp.s_sstatus2.index;
+        result.s.type = load_resp.s_sstatus2.tag_type;
+        result.s.tag = load_resp.s_sstatus2.tag;
+        return result;
+}
+
+/**
+ * Get the POW WQE for this core. This returns the work queue
+ * entry currently associated with this core.
+ *
+ * Returns WQE pointer
+ */
+static inline struct cvmx_wqe *cvmx_pow_get_current_wqp(void)
+{
+        cvmx_pow_load_addr_t load_addr;
+        cvmx_pow_tag_load_resp_t load_resp;
+
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_addr.sstatus.get_wqp = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        return (struct cvmx_wqe *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
+}
+
+#ifndef CVMX_MF_CHORD
+#define CVMX_MF_CHORD(dest)         CVMX_RDHWR(dest, 30)
+#endif
+
+/**
+ * Print a warning if a tag switch is pending for this core
+ *
+ * @function: Function name checking for a pending tag switch
+ */
+static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
+{
+        uint64_t switch_complete;
+        CVMX_MF_CHORD(switch_complete);
+        if (!switch_complete)
+                pr_warn("%s called with tag switch in progress\n", function);
+}
+
+/**
+ * Waits for a tag switch to complete by polling the completion bit.
+ * Note that switches to NULL complete immediately and do not need
+ * to be waited for.
+ */
+static inline void cvmx_pow_tag_sw_wait(void)
+{
+        const uint64_t MAX_CYCLES = 1ull << 31;
+        uint64_t switch_complete;
+        uint64_t start_cycle = cvmx_get_cycle();
+        while (1) {
+                CVMX_MF_CHORD(switch_complete);
+                if (unlikely(switch_complete))
+                        break;
+                if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
+                        pr_warn("Tag switch is taking a long time, possible deadlock\n");
+                        start_cycle = -MAX_CYCLES - 1;
+                }
+        }
+}
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that there is not a pending tag switch.
+ *
+ * @wait:   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * Returns: the WQE pointer from POW. Returns NULL if no work
+ * was available.
+ */
+static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
+                                                             wait)
+{
+        cvmx_pow_load_addr_t ptr;
+        cvmx_pow_tag_load_resp_t result;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        ptr.u64 = 0;
+        ptr.swork.mem_region = CVMX_IO_SEG;
+        ptr.swork.is_io = 1;
+        ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
+        ptr.swork.wait = wait;
+
+        result.u64 = cvmx_read_csr(ptr.u64);
+
+        if (result.s_work.no_work)
+                return NULL;
+        else
+                return (struct cvmx_wqe *) cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function waits for any previous tag switch to complete before
+ * requesting the new work.
+ *
+ * @wait:   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * Returns: the WQE pointer from POW. Returns NULL if no work
+ * was available.
+ */
+static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+        return cvmx_pow_work_request_sync_nocheck(wait);
+
+}
+
+/**
+ * Synchronous null_rd request.  Requests a switch out of NULL_NULL POW state.
+ * This function waits for any previous tag switch to complete before
+ * requesting the null_rd.
+ *
+ * Returns: the POW state of type cvmx_pow_tag_type_t.
+ */
+static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
+{
+        cvmx_pow_load_addr_t ptr;
+        cvmx_pow_tag_load_resp_t result;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+
+        ptr.u64 = 0;
+        ptr.snull_rd.mem_region = CVMX_IO_SEG;
+        ptr.snull_rd.is_io = 1;
+        ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
+
+        result.u64 = cvmx_read_csr(ptr.u64);
+
+        return (enum cvmx_pow_tag_type) result.s_null_rd.state;
+}
+
+/**
+ * Asynchronous work request.  Work is requested from the POW unit,
+ * and should later be checked with function
+ * cvmx_pow_work_response_async.  This function does NOT wait for
+ * previous tag switches to complete, so the caller must ensure that
+ * there is not a pending tag switch.
+ *
+ * @scr_addr: Scratch memory address that response will be returned
+ *            to, which is either a valid WQE, or a response with the
+ *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *
+ * @wait: 1 to cause response to wait for work to become available (or
+ *        timeout), 0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
+                                                       cvmx_pow_wait_t wait)
+{
+        cvmx_pow_iobdma_store_t data;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* scr_addr must be 8 byte aligned */
+        data.s.scraddr = scr_addr >> 3;
+        data.s.len = 1;
+        data.s.did = CVMX_OCT_DID_TAG_SWTAG;
+        data.s.wait = wait;
+        cvmx_send_single(data.u64);
+}
+
+/**
+ * Asynchronous work request.  Work is requested from the POW unit,
+ * and should later be checked with function
+ * cvmx_pow_work_response_async.  This function waits for any previous
+ * tag switch to complete before requesting the new work.
+ *
+ * @scr_addr: Scratch memory address that response will be returned
+ *            to, which is either a valid WQE, or a response with the
+ *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *
+ * @wait: 1 to cause response to wait for work to become available (or
+ *                  timeout), 0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async(int scr_addr,
+                                               cvmx_pow_wait_t wait)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_work_request_async_nocheck(scr_addr, wait);
+}
+
+/**
+ * Gets result of asynchronous work request.  Performs a IOBDMA sync
+ * to wait for the response.
+ *
+ * @scr_addr: Scratch memory address to get result from Byte address,
+ *            must be 8 byte aligned.
+ *
+ * Returns: the WQE from the scratch register, or NULL if no
+ * work was available.
+ */
+static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
+{
+        cvmx_pow_tag_load_resp_t result;
+
+        CVMX_SYNCIOBDMA;
+        result.u64 = cvmx_scratch_read64(scr_addr);
+
+        if (result.s_work.no_work)
+                return NULL;
+        else
+                return (struct cvmx_wqe *) cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+/**
+ * Checks if a work queue entry pointer returned by a work
+ * request is valid.  It may be invalid due to no work
+ * being available or due to a timeout.
+ *
+ * @wqe_ptr: pointer to a work queue entry returned by the POW
+ *
+ * Returns 0 if pointer is valid
+ *         1 if invalid (no work was returned)
+ */
+static inline uint64_t cvmx_pow_work_invalid(struct cvmx_wqe *wqe_ptr)
+{
+        return wqe_ptr == NULL;
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function does no checks, so the caller must ensure that any
+ * previous tag switch has completed.
+ *
+ * @tag:      new tag value
+ * @tag_type: new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
+                                           enum cvmx_pow_tag_type tag_type)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warn("%s called with NULL_NULL tag\n", __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called with NULL tag\n", __func__);
+                if ((current_tag.s.type == tag_type)
+                   && (current_tag.s.tag == tag))
+                        pr_warn("%s called to perform a tag switch to the same tag\n",
+                                __func__);
+                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n",
+                                __func__);
+        }
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+
+        /* once this store arrives at POW, it will attempt the switch
+           software must wait for the switch to complete separately */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function waits for any previous tag switch to complete, and also
+ * displays an error on tag switches to NULL.
+ *
+ * @tag:      new tag value
+ * @tag_type: new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw(uint32_t tag,
+                                   enum cvmx_pow_tag_type tag_type)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_nocheck(tag, tag_type);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function does no checks, so the caller must ensure that any
+ * previous tag switch has completed.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is
+ *            updated to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @group:    group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full_nocheck(struct cvmx_wqe *wqp, uint32_t tag,
+                                                enum cvmx_pow_tag_type tag_type,
+                                                uint64_t group)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warn("%s called with NULL_NULL tag\n", __func__);
+                if ((current_tag.s.type == tag_type)
+                   && (current_tag.s.tag == tag))
+                        pr_warn("%s called to perform a tag switch to the same tag\n",
+                                __func__);
+                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n",
+                                __func__);
+                if (wqp != cvmx_phys_to_ptr(0x80))
+                        if (wqp != cvmx_pow_get_current_wqp())
+                                pr_warn("%s passed WQE(%p) doesn't match the address in the POW(%p)\n",
+                                        __func__, wqp,
+                                        cvmx_pow_get_current_wqp());
+        }
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+        tag_req.s.grp = group;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+        ptr.sio.offset = CAST64(wqp);
+
+        /*
+         * once this store arrives at POW, it will attempt the switch
+         * software must wait for the switch to complete separately.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function waits for any pending tag switches to complete
+ * before requesting the tag switch.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is updated
+ *            to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @group:      group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full(struct cvmx_wqe *wqp, uint32_t tag,
+                                        enum cvmx_pow_tag_type tag_type,
+                                        uint64_t group)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
+}
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediately,
+ * so completion should not be waited for.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that any previous tag switches have completed.
+ */
+static inline void cvmx_pow_tag_sw_null_nocheck(void)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warn("%s called with NULL_NULL tag\n", __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called when we already have a NULL tag\n",
+                                __func__);
+        }
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+
+        cvmx_write_io(ptr.u64, tag_req.u64);
+
+        /* switch to NULL completes immediately */
+}
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediately,
+ * so completion should not be waited for.
+ * This function waits for any pending tag switches to complete
+ * before requesting the switch to NULL.
+ */
+static inline void cvmx_pow_tag_sw_null(void)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_null_nocheck();
+
+        /* switch to NULL completes immediately */
+}
+
+/**
+ * Submits work to an input queue.  This function updates the work
+ * queue entry in DRAM to match the arguments given.  Note that the
+ * tag provided is for the work queue entry submitted, and is
+ * unrelated to the tag that the core currently holds.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is
+ *            updated to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @qos:      Input queue to add to.
+ * @grp:      group value for the work queue entry.
+ */
+static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
+                                        enum cvmx_pow_tag_type tag_type,
+                                        uint64_t qos, uint64_t grp)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        wqp->word1.tag = tag;
+        wqp->word1.tag_type = tag_type;
+
+        cvmx_wqe_set_qos(wqp, qos);
+        cvmx_wqe_set_grp(wqp, grp);
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
+        tag_req.s.type = tag_type;
+        tag_req.s.tag = tag;
+        tag_req.s.qos = qos;
+        tag_req.s.grp = grp;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+        ptr.sio.offset = cvmx_ptr_to_phys(wqp);
+
+        /*
+         * SYNC write to memory before the work submit.  This is
+         * necessary as POW may read values from DRAM at this time.
+         */
+        CVMX_SYNCWS;
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * This function sets the group mask for a core.  The group mask
+ * indicates which groups each core will accept work from. There are
+ * 16 groups.
+ *
+ * @core_num:   core to apply mask to
+ * @mask:   Group mask. There are 16 groups, so only bits 0-15 are valid,
+ *               representing groups 0-15.
+ *               Each 1 bit in the mask enables the core to accept work from
+ *               the corresponding group.
+ */
+static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
+{
+        union cvmx_pow_pp_grp_mskx grp_msk;
+
+        grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+        grp_msk.s.grp_msk = mask;
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+}
+
+/**
+ * This function sets POW static priorities for a core. Each input queue has
+ * an associated priority value.
+ *
+ * @core_num:   core to apply priorities to
+ * @priority:   Vector of 8 priorities, one per POW Input Queue (0-7).
+ *                   Highest priority is 0 and lowest is 7. A priority value
+ *                   of 0xF instructs POW to skip the Input Queue when
+ *                   scheduling to this specific core.
+ *                   NOTE: priorities should not have gaps in values, meaning
+ *                         {0,1,1,1,1,1,1,1} is a valid configuration while
+ *                         {0,2,2,2,2,2,2,2} is not.
+ */
+static inline void cvmx_pow_set_priority(uint64_t core_num,
+                                         const uint8_t priority[])
+{
+        /* POW priorities are supported on CN5xxx and later */
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_pow_pp_grp_mskx grp_msk;
+
+                grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+                grp_msk.s.qos0_pri = priority[0];
+                grp_msk.s.qos1_pri = priority[1];
+                grp_msk.s.qos2_pri = priority[2];
+                grp_msk.s.qos3_pri = priority[3];
+                grp_msk.s.qos4_pri = priority[4];
+                grp_msk.s.qos5_pri = priority[5];
+                grp_msk.s.qos6_pri = priority[6];
+                grp_msk.s.qos7_pri = priority[7];
+
+                /* Detect gaps between priorities and flag error */
+                {
+                        int i;
+                        uint32_t prio_mask = 0;
+
+                        for (i = 0; i < 8; i++)
+                                if (priority[i] != 0xF)
+                                        prio_mask |= 1 << priority[i];
+
+                        if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) {
+                                pr_err("POW static priorities should be "
+                                       "contiguous (0x%llx)\n",
+                                     (unsigned long long)prio_mask);
+                                return;
+                        }
+                }
+
+                cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+        }
+}
+
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediately, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function does NOT wait for any prior tag switches to complete, so the
+ * calling code must do this.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @tag:      New tag value
+ * @tag_type: New tag type
+ * @group:    New group value
+ * @no_sched: Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched_nocheck(
+        uint32_t tag,
+        enum cvmx_pow_tag_type tag_type,
+        uint64_t group,
+        uint64_t no_sched)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warn("%s called with NULL_NULL tag\n", __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called with NULL tag. Deschedule not allowed from NULL state\n",
+                                __func__);
+                if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
+                        && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
+                        pr_warn("%s called where neither the before or after tag is ATOMIC\n",
+                                __func__);
+        }
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+        tag_req.s.grp = group;
+        tag_req.s.no_sched = no_sched;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+        /*
+         * since TAG3 is used, this store will clear the local pending
+         * switch bit.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediately, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function waits for any prior tag switches to complete, so the
+ * calling code may call this function with a pending tag switch.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @tag:      New tag value
+ * @tag_type: New tag type
+ * @group:    New group value
+ * @no_sched: Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
+                                           enum cvmx_pow_tag_type tag_type,
+                                           uint64_t group, uint64_t no_sched)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Need to make sure any writes to the work queue entry are complete */
+        CVMX_SYNCWS;
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
+}
+
+/**
+ * Deschedules the current work queue entry.
+ *
+ * @no_sched: no schedule flag value to be set on the work queue
+ *            entry.  If this is set the entry will not be
+ *            rescheduled.
+ */
+static inline void cvmx_pow_desched(uint64_t no_sched)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warn("%s called with NULL_NULL tag\n", __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warn("%s called with NULL tag. Deschedule not expected from NULL state\n",
+                                __func__);
+        }
+
+        /* Need to make sure any writes to the work queue entry are complete */
+        CVMX_SYNCWS;
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
+        tag_req.s.no_sched = no_sched;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+        /*
+         * since TAG3 is used, this store will clear the local pending
+         * switch bit.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/****************************************************
+* Define usage of bits within the 32 bit tag values.
+*****************************************************/
+
+/*
+ * Number of bits of the tag used by software.  The SW bits are always
+ * a contiguous block of the high starting at bit 31.  The hardware
+ * bits are always the low bits.  By default, the top 8 bits of the
+ * tag are reserved for software, and the low 24 are set by the IPD
+ * unit.
+ */
+#define CVMX_TAG_SW_BITS    (8)
+#define CVMX_TAG_SW_SHIFT   (32 - CVMX_TAG_SW_BITS)
+
+/* Below is the list of values for the top 8 bits of the tag. */
+/*
+ * Tag values with top byte of this value are reserved for internal
+ * executive uses.
+ */
+#define CVMX_TAG_SW_BITS_INTERNAL  0x1
+/* The executive divides the remaining 24 bits as follows:
+ *  - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
+ *
+ *  - the lower 16 bits (bits 15 - 0 of the tag) define are the value
+ *    with the subgroup
+ *
+ * Note that this section describes the format of tags generated by
+ * software - refer to the hardware documentation for a description of
+ * the tags values generated by the packet input hardware.  Subgroups
+ * are defined here.
+ */
+/* Mask for the value portion of the tag */
+#define CVMX_TAG_SUBGROUP_MASK  0xFFFF
+#define CVMX_TAG_SUBGROUP_SHIFT 16
+#define CVMX_TAG_SUBGROUP_PKO  0x1
+
+/* End of executive tag subgroup definitions */
+
+/*
+ * The remaining values software bit values 0x2 - 0xff are available
+ * for application use.
+ */
+
+/**
+ * This function creates a 32 bit tag value from the two values provided.
+ *
+ * @sw_bits: The upper bits (number depends on configuration) are set
+ *           to this value.  The remainder of bits are set by the
+ *           hw_bits parameter.
+ *
+ * @hw_bits: The lower bits (number depends on configuration) are set
+ *           to this value.  The remainder of bits are set by the
+ *           sw_bits parameter.
+ *
+ * Returns 32 bit value of the combined hw and sw bits.
+ */
+static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
+{
+        return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) <<
+                        CVMX_TAG_SW_SHIFT) |
+                (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
+}
+
+/**
+ * Extracts the bits allocated for software use from the tag
+ *
+ * @tag:    32 bit tag value
+ *
+ * Returns N bit software tag value, where N is configurable with the
+ * CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
+{
+        return (tag >> (32 - CVMX_TAG_SW_BITS)) &
+                cvmx_build_mask(CVMX_TAG_SW_BITS);
+}
+
+/**
+ *
+ * Extracts the bits allocated for hardware use from the tag
+ *
+ * @tag:    32 bit tag value
+ *
+ * Returns (32 - N) bit software tag value, where N is configurable
+ * with the CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
+{
+        return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS);
+}
+
+/**
+ * Store the current POW internal state into the supplied
+ * buffer. It is recommended that you pass a buffer of at least
+ * 128KB. The format of the capture may change based on SDK
+ * version and Octeon chip.
+ *
+ * @buffer: Buffer to store capture into
+ * @buffer_size:
+ *               The size of the supplied buffer
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_pow_capture(void *buffer, int buffer_size);
+
+/**
+ * Dump a POW capture to the console in a human readable format.
+ *
+ * @buffer: POW capture from cvmx_pow_capture()
+ * @buffer_size:
+ *               Size of the buffer
+ */
+extern void cvmx_pow_display(void *buffer, int buffer_size);
+
+/**
+ * Return the number of POW entries supported by this chip
+ *
+ * Returns Number of POW entries
+ */
+extern int cvmx_pow_get_num_entries(void);
+
+#endif /* __CVMX_POW_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
new file mode 100644
index 000000000..94295d2fe
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -0,0 +1,171 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_RNM_DEFS_H__
+#define __CVMX_RNM_DEFS_H__
+
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
+
+union cvmx_rnm_bist_status {
+        uint64_t u64;
+        struct cvmx_rnm_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t rrc:1;
+                uint64_t mem:1;
+#else
+                uint64_t mem:1;
+                uint64_t rrc:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_rnm_ctl_status {
+        uint64_t u64;
+        struct cvmx_rnm_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t dis_mak:1;
+                uint64_t eer_lck:1;
+                uint64_t eer_val:1;
+                uint64_t ent_sel:4;
+                uint64_t exp_ent:1;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+#else
+                uint64_t ent_en:1;
+                uint64_t rng_en:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_rst:1;
+                uint64_t exp_ent:1;
+                uint64_t ent_sel:4;
+                uint64_t eer_val:1;
+                uint64_t eer_lck:1;
+                uint64_t dis_mak:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_rnm_ctl_status_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+#else
+                uint64_t ent_en:1;
+                uint64_t rng_en:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_rst:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn30xx;
+        struct cvmx_rnm_ctl_status_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t ent_sel:4;
+                uint64_t exp_ent:1;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+#else
+                uint64_t ent_en:1;
+                uint64_t rng_en:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_rst:1;
+                uint64_t exp_ent:1;
+                uint64_t ent_sel:4;
+                uint64_t reserved_9_63:55;
+#endif
+        } cn50xx;
+        struct cvmx_rnm_ctl_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t eer_lck:1;
+                uint64_t eer_val:1;
+                uint64_t ent_sel:4;
+                uint64_t exp_ent:1;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+#else
+                uint64_t ent_en:1;
+                uint64_t rng_en:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_rst:1;
+                uint64_t exp_ent:1;
+                uint64_t ent_sel:4;
+                uint64_t eer_val:1;
+                uint64_t eer_lck:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn63xx;
+};
+
+union cvmx_rnm_eer_dbg {
+        uint64_t u64;
+        struct cvmx_rnm_eer_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+union cvmx_rnm_eer_key {
+        uint64_t u64;
+        struct cvmx_rnm_eer_key_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t key:64;
+#else
+                uint64_t key:64;
+#endif
+        } s;
+};
+
+union cvmx_rnm_serial_num {
+        uint64_t u64;
+        struct cvmx_rnm_serial_num_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-rst-defs.h b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
new file mode 100644
index 000000000..accc9977d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
@@ -0,0 +1,278 @@
+/***********************license start***************
+ * Author: Cavium Inc.
+ *
+ * Contact: support@cavium.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2014 Cavium Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Inc. for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_RST_DEFS_H__
+#define __CVMX_RST_DEFS_H__
+
+#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
+#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
+#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
+#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
+#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
+#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
+#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
+#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
+#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
+#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
+#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
+#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
+
+union cvmx_rst_boot {
+        uint64_t u64;
+        struct cvmx_rst_boot_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t vrm_err:1;
+                uint64_t reserved_37_56:20;
+                uint64_t c_mul:7;
+                uint64_t pnr_mul:6;
+                uint64_t reserved_21_23:3;
+                uint64_t lboot_oci:3;
+                uint64_t lboot_ext:6;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+#else
+                uint64_t rboot_pin:1;
+                uint64_t rboot:1;
+                uint64_t lboot:10;
+                uint64_t lboot_ext:6;
+                uint64_t lboot_oci:3;
+                uint64_t reserved_21_23:3;
+                uint64_t pnr_mul:6;
+                uint64_t c_mul:7;
+                uint64_t reserved_37_56:20;
+                uint64_t vrm_err:1;
+                uint64_t jt_tstmode:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t romen:1;
+                uint64_t ejtagdis:1;
+                uint64_t jtcsrdis:1;
+                uint64_t chipkill:1;
+#endif
+        } s;
+};
+
+union cvmx_rst_cfg {
+        uint64_t u64;
+        struct cvmx_rst_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bist_delay:58;
+                uint64_t reserved_3_5:3;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+#else
+                uint64_t soft_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t cntl_clr_bist:1;
+                uint64_t reserved_3_5:3;
+                uint64_t bist_delay:58;
+#endif
+        } s;
+};
+
+union cvmx_rst_ckill {
+        uint64_t u64;
+        struct cvmx_rst_ckill_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_47_63:17;
+                uint64_t timer:47;
+#else
+                uint64_t timer:47;
+                uint64_t reserved_47_63:17;
+#endif
+        } s;
+};
+
+union cvmx_rst_ctlx {
+        uint64_t u64;
+        struct cvmx_rst_ctlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t reserved_4_5:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+#else
+                uint64_t rst_val:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_drv:1;
+                uint64_t reserved_4_5:2;
+                uint64_t host_mode:1;
+                uint64_t rst_link:1;
+                uint64_t rst_done:1;
+                uint64_t prst_link:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_rst_delay {
+        uint64_t u64;
+        struct cvmx_rst_delay_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t warm_rst_dly:16;
+                uint64_t soft_rst_dly:16;
+#else
+                uint64_t soft_rst_dly:16;
+                uint64_t warm_rst_dly:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_rst_eco {
+        uint64_t u64;
+        struct cvmx_rst_eco_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t eco_rw:32;
+#else
+                uint64_t eco_rw:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_rst_int {
+        uint64_t u64;
+        struct cvmx_rst_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t perst:4;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link:4;
+#else
+                uint64_t rst_link:4;
+                uint64_t reserved_4_7:4;
+                uint64_t perst:4;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+        struct cvmx_rst_int_cn70xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t perst:3;
+                uint64_t reserved_3_7:5;
+                uint64_t rst_link:3;
+#else
+                uint64_t rst_link:3;
+                uint64_t reserved_3_7:5;
+                uint64_t perst:3;
+                uint64_t reserved_11_63:53;
+#endif
+        } cn70xx;
+};
+
+union cvmx_rst_ocx {
+        uint64_t u64;
+        struct cvmx_rst_ocx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t rst_link:3;
+#else
+                uint64_t rst_link:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_rst_power_dbg {
+        uint64_t u64;
+        struct cvmx_rst_power_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t str:3;
+#else
+                uint64_t str:3;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_rst_pp_power {
+        uint64_t u64;
+        struct cvmx_rst_pp_power_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t gate:48;
+#else
+                uint64_t gate:48;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+        struct cvmx_rst_pp_power_cn70xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t gate:4;
+#else
+                uint64_t gate:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } cn70xx;
+};
+
+union cvmx_rst_soft_prstx {
+        uint64_t u64;
+        struct cvmx_rst_soft_prstx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t soft_prst:1;
+#else
+                uint64_t soft_prst:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_rst_soft_rst {
+        uint64_t u64;
+        struct cvmx_rst_soft_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t soft_rst:1;
+#else
+                uint64_t soft_rst:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
new file mode 100644
index 000000000..8d21cc5e4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * This file provides support for the processor local scratch memory.
+ * Scratch memory is byte addressable - all addresses are byte addresses.
+ *
+ */
+
+#ifndef __CVMX_SCRATCH_H__
+#define __CVMX_SCRATCH_H__
+
+/*
+ * Note: This define must be a long, not a long long in order to
+ * compile without warnings for both 32bit and 64bit.
+ */
+#define CVMX_SCRATCH_BASE       (-32768l)       /* 0xffffffffffff8000 */
+
+/**
+ * Reads an 8 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint8_t cvmx_scratch_read8(uint64_t address)
+{
+        return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 16 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint16_t cvmx_scratch_read16(uint64_t address)
+{
+        return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 32 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint32_t cvmx_scratch_read32(uint64_t address)
+{
+        return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 64 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint64_t cvmx_scratch_read64(uint64_t address)
+{
+        return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Writes an 8 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =
+            (uint8_t) value;
+}
+
+/**
+ * Writes a 32 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) =
+            (uint16_t) value;
+}
+
+/**
+ * Writes a 16 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
+            (uint32_t) value;
+}
+
+/**
+ * Writes a 64 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
+}
+
+#endif /* __CVMX_SCRATCH_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 000000000..5ef6c3815
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,129 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SLI_DEFS_H__
+#define __CVMX_SLI_DEFS_H__
+
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+                return 0x0000000000003CB0ull;
+        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+                if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+                        return 0x0000000000003CB0ull;
+                fallthrough;
+        default:
+                return 0x0000000000023CB0ull;
+        }
+}
+
+
+union cvmx_sli_ctl_portx {
+        uint64_t u64;
+        struct cvmx_sli_ctl_portx_s {
+                __BITFIELD_FIELD(uint64_t reserved_22_63:42,
+                __BITFIELD_FIELD(uint64_t intd:1,
+                __BITFIELD_FIELD(uint64_t intc:1,
+                __BITFIELD_FIELD(uint64_t intb:1,
+                __BITFIELD_FIELD(uint64_t inta:1,
+                __BITFIELD_FIELD(uint64_t dis_port:1,
+                __BITFIELD_FIELD(uint64_t waitl_com:1,
+                __BITFIELD_FIELD(uint64_t intd_map:2,
+                __BITFIELD_FIELD(uint64_t intc_map:2,
+                __BITFIELD_FIELD(uint64_t intb_map:2,
+                __BITFIELD_FIELD(uint64_t inta_map:2,
+                __BITFIELD_FIELD(uint64_t ctlp_ro:1,
+                __BITFIELD_FIELD(uint64_t reserved_6_6:1,
+                __BITFIELD_FIELD(uint64_t ptlp_ro:1,
+                __BITFIELD_FIELD(uint64_t reserved_1_4:4,
+                __BITFIELD_FIELD(uint64_t wait_com:1,
+                ;))))))))))))))))
+        } s;
+};
+
+union cvmx_sli_mem_access_ctl {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_ctl_s {
+                __BITFIELD_FIELD(uint64_t reserved_14_63:50,
+                __BITFIELD_FIELD(uint64_t max_word:4,
+                __BITFIELD_FIELD(uint64_t timer:10,
+                ;)))
+        } s;
+};
+
+union cvmx_sli_s2m_portx_ctl {
+        uint64_t u64;
+        struct cvmx_sli_s2m_portx_ctl_s {
+                __BITFIELD_FIELD(uint64_t reserved_5_63:59,
+                __BITFIELD_FIELD(uint64_t wind_d:1,
+                __BITFIELD_FIELD(uint64_t bar0_d:1,
+                __BITFIELD_FIELD(uint64_t mrrs:3,
+                ;))))
+        } s;
+};
+
+union cvmx_sli_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_subidx_s {
+                __BITFIELD_FIELD(uint64_t reserved_43_63:21,
+                __BITFIELD_FIELD(uint64_t zero:1,
+                __BITFIELD_FIELD(uint64_t port:3,
+                __BITFIELD_FIELD(uint64_t nmerge:1,
+                __BITFIELD_FIELD(uint64_t esr:2,
+                __BITFIELD_FIELD(uint64_t esw:2,
+                __BITFIELD_FIELD(uint64_t wtype:2,
+                __BITFIELD_FIELD(uint64_t rtype:2,
+                __BITFIELD_FIELD(uint64_t ba:30,
+                ;)))))))))
+        } s;
+        struct cvmx_sli_mem_access_subidx_cn68xx {
+                __BITFIELD_FIELD(uint64_t reserved_43_63:21,
+                __BITFIELD_FIELD(uint64_t zero:1,
+                __BITFIELD_FIELD(uint64_t port:3,
+                __BITFIELD_FIELD(uint64_t nmerge:1,
+                __BITFIELD_FIELD(uint64_t esr:2,
+                __BITFIELD_FIELD(uint64_t esw:2,
+                __BITFIELD_FIELD(uint64_t wtype:2,
+                __BITFIELD_FIELD(uint64_t rtype:2,
+                __BITFIELD_FIELD(uint64_t ba:28,
+                __BITFIELD_FIELD(uint64_t reserved_0_1:2,
+                ;))))))))))
+        } cn68xx;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
new file mode 100644
index 000000000..d5038cc4b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
@@ -0,0 +1,269 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * This file contains defines for the SPI interface
+ */
+#ifndef __CVMX_SPI_H__
+#define __CVMX_SPI_H__
+
+#include <asm/octeon/cvmx-gmxx-defs.h>
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+typedef enum {
+        CVMX_SPI_MODE_UNKNOWN = 0,
+        CVMX_SPI_MODE_TX_HALFPLEX = 1,
+        CVMX_SPI_MODE_RX_HALFPLEX = 2,
+        CVMX_SPI_MODE_DUPLEX = 3
+} cvmx_spi_mode_t;
+
+/** Callbacks structure to customize SPI4 initialization sequence */
+typedef struct {
+    /** Called to reset SPI4 DLL */
+        int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
+
+    /** Called to setup calendar */
+        int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
+                                  int num_ports);
+
+    /** Called for Tx and Rx clock detection */
+        int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
+                                int timeout);
+
+    /** Called to perform link training */
+        int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
+
+    /** Called for calendar data synchronization */
+        int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode,
+                                 int timeout);
+
+    /** Called when interface is up */
+        int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode);
+
+} cvmx_spi_callbacks_t;
+
+/**
+ * Return true if the supplied interface is configured for SPI
+ *
+ * @interface: Interface to check
+ * Returns True if interface is SPI
+ */
+static inline int cvmx_spi_is_spi_interface(int interface)
+{
+        uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+        return (gmxState & 0x2) && (gmxState & 0x1);
+}
+
+/**
+ * Initialize and start the SPI interface.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ * @num_ports: Number of SPI ports to configure
+ *
+ * Returns Zero on success, negative of failure.
+ */
+extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
+                                    int timeout, int num_ports);
+
+/**
+ * This routine restarts the SPI interface after it has lost synchronization
+ * with its corespondant system.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ * Returns Zero on success, negative of failure.
+ */
+extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode,
+                                      int timeout);
+
+/**
+ * Return non-zero if the SPI interface has a SPI4000 attached
+ *
+ * @interface: SPI interface the SPI4000 is connected to
+ *
+ * Returns
+ */
+static inline int cvmx_spi4000_is_present(int interface)
+{
+        return 0;
+}
+
+/**
+ * Initialize the SPI4000 for use
+ *
+ * @interface: SPI interface the SPI4000 is connected to
+ */
+static inline int cvmx_spi4000_initialize(int interface)
+{
+        return 0;
+}
+
+/**
+ * Poll all the SPI4000 port and check its speed
+ *
+ * @interface: Interface the SPI4000 is on
+ * @port:      Port to poll (0-9)
+ * Returns Status of the port. 0=down. All other values the port is up.
+ */
+static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
+        int interface,
+        int port)
+{
+        union cvmx_gmxx_rxx_rx_inbnd r;
+        r.u64 = 0;
+        return r;
+}
+
+/**
+ * Get current SPI4 initialization callbacks
+ *
+ * @callbacks:  Pointer to the callbacks structure.to fill
+ *
+ * Returns Pointer to cvmx_spi_callbacks_t structure.
+ */
+extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks);
+
+/**
+ * Set new SPI4 initialization callbacks
+ *
+ * @new_callbacks:  Pointer to an updated callbacks structure.
+ */
+extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
+
+/**
+ * Callback to perform SPI4 reset
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
+
+/**
+ * Callback to setup calendar and miscellaneous settings before clock
+ * detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @num_ports: Number of ports to configure on SPI
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
+                                      int num_ports);
+
+/**
+ * Callback to perform clock detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
+                                    int timeout);
+
+/**
+ * Callback to perform link training
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for link to be trained (in seconds)
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
+                                int timeout);
+
+/**
+ * Callback to perform calendar data synchronization
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for calendar data in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
+                                     int timeout);
+
+/**
+ * Callback to handle interface up
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
+
+#endif /* __CVMX_SPI_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
new file mode 100644
index 000000000..4f09cff8b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -0,0 +1,232 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * Implementation of spinlocks for Octeon CVMX.  Although similar in
+ * function to Linux kernel spinlocks, they are not compatible.
+ * Octeon CVMX spinlocks are only used to synchronize with the boot
+ * monitor and other non-Linux programs running in the system.
+ */
+
+#ifndef __CVMX_SPINLOCK_H__
+#define __CVMX_SPINLOCK_H__
+
+#include <asm/octeon/cvmx-asm.h>
+
+/* Spinlocks for Octeon */
+
+/* define these to enable recursive spinlock debugging */
+/*#define CVMX_SPINLOCK_DEBUG */
+
+/**
+ * Spinlocks for Octeon CVMX
+ */
+typedef struct {
+        volatile uint32_t value;
+} cvmx_spinlock_t;
+
+/* note - macros not expanded in inline ASM, so values hardcoded */
+#define  CVMX_SPINLOCK_UNLOCKED_VAL  0
+#define  CVMX_SPINLOCK_LOCKED_VAL    1
+
+#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER  {CVMX_SPINLOCK_UNLOCKED_VAL}
+
+/**
+ * Initialize a spinlock
+ *
+ * @lock:   Lock to initialize
+ */
+static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
+{
+        lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+ * Return non-zero if the spinlock is currently locked
+ *
+ * @lock:   Lock to check
+ * Returns Non-zero if locked
+ */
+static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
+{
+        return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+ * Releases lock
+ *
+ * @lock:   pointer to lock structure
+ */
+static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
+{
+        CVMX_SYNCWS;
+        lock->value = 0;
+        CVMX_SYNCWS;
+}
+
+/**
+ * Attempts to take the lock, but does not spin if lock is not available.
+ * May take some time to acquire the lock even if it is available
+ * due to the ll/sc not succeeding.
+ *
+ * @lock:   pointer to lock structure
+ *
+ * Returns 0: lock successfully taken
+ *         1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+
+static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
+{
+        unsigned int tmp;
+
+        __asm__ __volatile__(".set noreorder         \n"
+                             "1: ll   %[tmp], %[val] \n"
+                        /* if lock held, fail immediately */
+                             "   bnez %[tmp], 2f     \n"
+                             "   li   %[tmp], 1      \n"
+                             "   sc   %[tmp], %[val] \n"
+                             "   beqz %[tmp], 1b     \n"
+                             "   li   %[tmp], 0      \n"
+                             "2:                     \n"
+                             ".set reorder           \n" :
+                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
+                             : : "memory");
+
+        return tmp != 0;                /* normalize to 0 or 1 */
+}
+
+/**
+ * Gets lock, spins until lock is taken
+ *
+ * @lock:   pointer to lock structure
+ */
+static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
+{
+        unsigned int tmp;
+
+        __asm__ __volatile__(".set noreorder         \n"
+                             "1: ll   %[tmp], %[val]  \n"
+                             "   bnez %[tmp], 1b     \n"
+                             "   li   %[tmp], 1      \n"
+                             "   sc   %[tmp], %[val] \n"
+                             "   beqz %[tmp], 1b     \n"
+                             "   nop                \n"
+                             ".set reorder           \n" :
+                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
+                        : : "memory");
+
+}
+
+/** ********************************************************************
+ * Bit spinlocks
+ * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
+ * The rest of the bits in the word are left undisturbed.  This enables more
+ * compact data structures as only 1 bit is consumed for the lock.
+ *
+ */
+
+/**
+ * Gets lock, spins until lock is taken
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @word:  word to lock bit 31 of
+ */
+static inline void cvmx_spinlock_bit_lock(uint32_t *word)
+{
+        unsigned int tmp;
+        unsigned int sav;
+
+        __asm__ __volatile__(".set noreorder         \n"
+                             ".set noat              \n"
+                             "1: ll    %[tmp], %[val]  \n"
+                             "   bbit1 %[tmp], 31, 1b    \n"
+                             "   li    $at, 1      \n"
+                             "   ins   %[tmp], $at, 31, 1  \n"
+                             "   sc    %[tmp], %[val] \n"
+                             "   beqz  %[tmp], 1b     \n"
+                             "   nop                \n"
+                             ".set at              \n"
+                             ".set reorder           \n" :
+                        [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
+                             : : "memory");
+
+}
+
+/**
+ * Attempts to get lock, returns immediately with success/failure
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @word:  word to lock bit 31 of
+ * Returns 0: lock successfully taken
+ *         1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
+{
+        unsigned int tmp;
+
+        __asm__ __volatile__(".set noreorder\n\t"
+                             ".set noat\n"
+                             "1: ll    %[tmp], %[val] \n"
+                        /* if lock held, fail immediately */
+                             "   bbit1 %[tmp], 31, 2f     \n"
+                             "   li    $at, 1      \n"
+                             "   ins   %[tmp], $at, 31, 1  \n"
+                             "   sc    %[tmp], %[val] \n"
+                             "   beqz  %[tmp], 1b     \n"
+                             "   li    %[tmp], 0      \n"
+                             "2:                     \n"
+                             ".set at              \n"
+                             ".set reorder           \n" :
+                        [val] "+m"(*word), [tmp] "=&r"(tmp)
+                        : : "memory");
+
+        return tmp != 0;                /* normalize to 0 or 1 */
+}
+
+/**
+ * Releases bit lock
+ *
+ * Unconditionally clears bit 31 of the lock word.  Note that this is
+ * done non-atomically, as this implementation assumes that the rest
+ * of the bits in the word are protected by the lock.
+ *
+ * @word:  word to unlock bit 31 in
+ */
+static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
+{
+        CVMX_SYNCWS;
+        *word &= ~(1UL << 31);
+        CVMX_SYNCWS;
+}
+
+#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
new file mode 100644
index 000000000..8471ed2de
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
@@ -0,0 +1,446 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SPXX_DEFS_H__
+#define __CVMX_SPXX_DEFS_H__
+
+#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
+
+void __cvmx_interrupt_spxx_int_msk_enable(int index);
+
+union cvmx_spxx_bckprs_cnt {
+        uint64_t u64;
+        struct cvmx_spxx_bckprs_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_spxx_bist_stat {
+        uint64_t u64;
+        struct cvmx_spxx_bist_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t stat2:1;
+                uint64_t stat1:1;
+                uint64_t stat0:1;
+#else
+                uint64_t stat0:1;
+                uint64_t stat1:1;
+                uint64_t stat2:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } s;
+};
+
+union cvmx_spxx_clk_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_clk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t seetrn:1;
+                uint64_t reserved_12_15:4;
+                uint64_t clkdly:5;
+                uint64_t runbist:1;
+                uint64_t statdrv:1;
+                uint64_t statrcv:1;
+                uint64_t sndtrn:1;
+                uint64_t drptrn:1;
+                uint64_t rcvtrn:1;
+                uint64_t srxdlck:1;
+#else
+                uint64_t srxdlck:1;
+                uint64_t rcvtrn:1;
+                uint64_t drptrn:1;
+                uint64_t sndtrn:1;
+                uint64_t statrcv:1;
+                uint64_t statdrv:1;
+                uint64_t runbist:1;
+                uint64_t clkdly:5;
+                uint64_t reserved_12_15:4;
+                uint64_t seetrn:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_spxx_clk_stat {
+        uint64_t u64;
+        struct cvmx_spxx_clk_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_11_63:53;
+                uint64_t stxcal:1;
+                uint64_t reserved_9_9:1;
+                uint64_t srxtrn:1;
+                uint64_t s4clk1:1;
+                uint64_t s4clk0:1;
+                uint64_t d4clk1:1;
+                uint64_t d4clk0:1;
+                uint64_t reserved_0_3:4;
+#else
+                uint64_t reserved_0_3:4;
+                uint64_t d4clk0:1;
+                uint64_t d4clk1:1;
+                uint64_t s4clk0:1;
+                uint64_t s4clk1:1;
+                uint64_t srxtrn:1;
+                uint64_t reserved_9_9:1;
+                uint64_t stxcal:1;
+                uint64_t reserved_11_63:53;
+#endif
+        } s;
+};
+
+union cvmx_spxx_dbg_deskew_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_dbg_deskew_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_30_63:34;
+                uint64_t fallnop:1;
+                uint64_t fall8:1;
+                uint64_t reserved_26_27:2;
+                uint64_t sstep_go:1;
+                uint64_t sstep:1;
+                uint64_t reserved_22_23:2;
+                uint64_t clrdly:1;
+                uint64_t dec:1;
+                uint64_t inc:1;
+                uint64_t mux:1;
+                uint64_t offset:5;
+                uint64_t bitsel:5;
+                uint64_t offdly:6;
+                uint64_t dllfrc:1;
+                uint64_t dlldis:1;
+#else
+                uint64_t dlldis:1;
+                uint64_t dllfrc:1;
+                uint64_t offdly:6;
+                uint64_t bitsel:5;
+                uint64_t offset:5;
+                uint64_t mux:1;
+                uint64_t inc:1;
+                uint64_t dec:1;
+                uint64_t clrdly:1;
+                uint64_t reserved_22_23:2;
+                uint64_t sstep:1;
+                uint64_t sstep_go:1;
+                uint64_t reserved_26_27:2;
+                uint64_t fall8:1;
+                uint64_t fallnop:1;
+                uint64_t reserved_30_63:34;
+#endif
+        } s;
+};
+
+union cvmx_spxx_dbg_deskew_state {
+        uint64_t u64;
+        struct cvmx_spxx_dbg_deskew_state_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t testres:1;
+                uint64_t unxterm:1;
+                uint64_t muxsel:2;
+                uint64_t offset:5;
+#else
+                uint64_t offset:5;
+                uint64_t muxsel:2;
+                uint64_t unxterm:1;
+                uint64_t testres:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_spxx_drv_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_0_63:64;
+#else
+                uint64_t reserved_0_63:64;
+#endif
+        } s;
+        struct cvmx_spxx_drv_ctl_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t stx4ncmp:4;
+                uint64_t stx4pcmp:4;
+                uint64_t srx4cmp:8;
+#else
+                uint64_t srx4cmp:8;
+                uint64_t stx4pcmp:4;
+                uint64_t stx4ncmp:4;
+                uint64_t reserved_16_63:48;
+#endif
+        } cn38xx;
+        struct cvmx_spxx_drv_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_24_63:40;
+                uint64_t stx4ncmp:4;
+                uint64_t stx4pcmp:4;
+                uint64_t reserved_10_15:6;
+                uint64_t srx4cmp:10;
+#else
+                uint64_t srx4cmp:10;
+                uint64_t reserved_10_15:6;
+                uint64_t stx4pcmp:4;
+                uint64_t stx4ncmp:4;
+                uint64_t reserved_24_63:40;
+#endif
+        } cn58xx;
+};
+
+union cvmx_spxx_err_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_err_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t prtnxa:1;
+                uint64_t dipcls:1;
+                uint64_t dippay:1;
+                uint64_t reserved_4_5:2;
+                uint64_t errcnt:4;
+#else
+                uint64_t errcnt:4;
+                uint64_t reserved_4_5:2;
+                uint64_t dippay:1;
+                uint64_t dipcls:1;
+                uint64_t prtnxa:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_spxx_int_dat {
+        uint64_t u64;
+        struct cvmx_spxx_int_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t mul:1;
+                uint64_t reserved_14_30:17;
+                uint64_t calbnk:2;
+                uint64_t rsvop:4;
+                uint64_t prt:8;
+#else
+                uint64_t prt:8;
+                uint64_t rsvop:4;
+                uint64_t calbnk:2;
+                uint64_t reserved_14_30:17;
+                uint64_t mul:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_spxx_int_msk {
+        uint64_t u64;
+        struct cvmx_spxx_int_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+#else
+                uint64_t prtnxa:1;
+                uint64_t abnorm:1;
+                uint64_t reserved_2_3:2;
+                uint64_t spiovr:1;
+                uint64_t clserr:1;
+                uint64_t drwnng:1;
+                uint64_t rsverr:1;
+                uint64_t tpaovr:1;
+                uint64_t diperr:1;
+                uint64_t syncerr:1;
+                uint64_t calerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_spxx_int_reg {
+        uint64_t u64;
+        struct cvmx_spxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t spf:1;
+                uint64_t reserved_12_30:19;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+#else
+                uint64_t prtnxa:1;
+                uint64_t abnorm:1;
+                uint64_t reserved_2_3:2;
+                uint64_t spiovr:1;
+                uint64_t clserr:1;
+                uint64_t drwnng:1;
+                uint64_t rsverr:1;
+                uint64_t tpaovr:1;
+                uint64_t diperr:1;
+                uint64_t syncerr:1;
+                uint64_t calerr:1;
+                uint64_t reserved_12_30:19;
+                uint64_t spf:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_spxx_int_sync {
+        uint64_t u64;
+        struct cvmx_spxx_int_sync_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_12_63:52;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+#else
+                uint64_t prtnxa:1;
+                uint64_t abnorm:1;
+                uint64_t reserved_2_3:2;
+                uint64_t spiovr:1;
+                uint64_t clserr:1;
+                uint64_t drwnng:1;
+                uint64_t rsverr:1;
+                uint64_t tpaovr:1;
+                uint64_t diperr:1;
+                uint64_t syncerr:1;
+                uint64_t calerr:1;
+                uint64_t reserved_12_63:52;
+#endif
+        } s;
+};
+
+union cvmx_spxx_tpa_acc {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_acc_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_spxx_tpa_max {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t max:32;
+#else
+                uint64_t max:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_spxx_tpa_sel {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_sel_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t prtsel:4;
+#else
+                uint64_t prtsel:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_spxx_trn4_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_trn4_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_13_63:51;
+                uint64_t trntest:1;
+                uint64_t jitter:3;
+                uint64_t clr_boot:1;
+                uint64_t set_boot:1;
+                uint64_t maxdist:5;
+                uint64_t macro_en:1;
+                uint64_t mux_en:1;
+#else
+                uint64_t mux_en:1;
+                uint64_t macro_en:1;
+                uint64_t maxdist:5;
+                uint64_t set_boot:1;
+                uint64_t clr_boot:1;
+                uint64_t jitter:3;
+                uint64_t trntest:1;
+                uint64_t reserved_13_63:51;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 000000000..34d0fadb5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1614 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
+
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_sriox_acc_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_acc_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_7_63:57;
+                uint64_t deny_adr2:1;
+                uint64_t deny_adr1:1;
+                uint64_t deny_adr0:1;
+                uint64_t reserved_3_3:1;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+#else
+                uint64_t deny_bar0:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar2:1;
+                uint64_t reserved_3_3:1;
+                uint64_t deny_adr0:1;
+                uint64_t deny_adr1:1;
+                uint64_t deny_adr2:1;
+                uint64_t reserved_7_63:57;
+#endif
+        } s;
+        struct cvmx_sriox_acc_ctrl_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_3_63:61;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+#else
+                uint64_t deny_bar0:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar2:1;
+                uint64_t reserved_3_63:61;
+#endif
+        } cn63xx;
+};
+
+union cvmx_sriox_asmbly_id {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_id_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t assy_id:16;
+                uint64_t assy_ven:16;
+#else
+                uint64_t assy_ven:16;
+                uint64_t assy_id:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_asmbly_info {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t assy_rev:16;
+                uint64_t reserved_0_15:16;
+#else
+                uint64_t reserved_0_15:16;
+                uint64_t assy_rev:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_bell_resp_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_bell_resp_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+#else
+                uint64_t rp0_pid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_sid:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_sriox_bist_status {
+        uint64_t u64;
+        struct cvmx_sriox_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_45_63:19;
+                uint64_t lram:1;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+#else
+                uint64_t omsg:7;
+                uint64_t imsg:5;
+                uint64_t rxbuf:2;
+                uint64_t txbuf:2;
+                uint64_t ospf:1;
+                uint64_t ispf:1;
+                uint64_t oarb:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb2:2;
+                uint64_t optrs:4;
+                uint64_t obulk:4;
+                uint64_t rtn:2;
+                uint64_t ofree:1;
+                uint64_t itag:1;
+                uint64_t otag:2;
+                uint64_t bell:2;
+                uint64_t cram:2;
+                uint64_t mram:2;
+                uint64_t lram:1;
+                uint64_t reserved_45_63:19;
+#endif
+        } s;
+        struct cvmx_sriox_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+#else
+                uint64_t omsg:7;
+                uint64_t imsg:5;
+                uint64_t rxbuf:2;
+                uint64_t txbuf:2;
+                uint64_t ospf:1;
+                uint64_t ispf:1;
+                uint64_t oarb:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb2:2;
+                uint64_t optrs:4;
+                uint64_t obulk:4;
+                uint64_t rtn:2;
+                uint64_t ofree:1;
+                uint64_t itag:1;
+                uint64_t otag:2;
+                uint64_t bell:2;
+                uint64_t cram:2;
+                uint64_t mram:2;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn63xx;
+        struct cvmx_sriox_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t reserved_20_23:4;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+#else
+                uint64_t omsg:7;
+                uint64_t imsg:5;
+                uint64_t rxbuf:2;
+                uint64_t txbuf:2;
+                uint64_t ospf:1;
+                uint64_t ispf:1;
+                uint64_t oarb:2;
+                uint64_t reserved_20_23:4;
+                uint64_t optrs:4;
+                uint64_t obulk:4;
+                uint64_t rtn:2;
+                uint64_t ofree:1;
+                uint64_t itag:1;
+                uint64_t otag:2;
+                uint64_t bell:2;
+                uint64_t cram:2;
+                uint64_t mram:2;
+                uint64_t reserved_44_63:20;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_sriox_imsg_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t to_mode:1;
+                uint64_t reserved_30_30:1;
+                uint64_t rsp_thr:6;
+                uint64_t reserved_22_23:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+                uint64_t reserved_15_15:1;
+                uint64_t prt_sel:3;
+                uint64_t lttr:4;
+                uint64_t prio:4;
+                uint64_t mbox:4;
+#else
+                uint64_t mbox:4;
+                uint64_t prio:4;
+                uint64_t lttr:4;
+                uint64_t prt_sel:3;
+                uint64_t reserved_15_15:1;
+                uint64_t rp0_pid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_sid:1;
+                uint64_t reserved_22_23:2;
+                uint64_t rsp_thr:6;
+                uint64_t reserved_30_30:1;
+                uint64_t to_mode:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_imsg_inst_hdrx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_inst_hdrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t r:1;
+                uint64_t reserved_58_62:5;
+                uint64_t pm:2;
+                uint64_t reserved_55_55:1;
+                uint64_t sl:7;
+                uint64_t reserved_46_47:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+                uint64_t reserved_35_41:7;
+                uint64_t rs:1;
+                uint64_t tt:2;
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tt:2;
+                uint64_t rs:1;
+                uint64_t reserved_35_41:7;
+                uint64_t ntag:1;
+                uint64_t ntt:1;
+                uint64_t ngrp:1;
+                uint64_t nqos:1;
+                uint64_t reserved_46_47:2;
+                uint64_t sl:7;
+                uint64_t reserved_55_55:1;
+                uint64_t pm:2;
+                uint64_t reserved_58_62:5;
+                uint64_t r:1;
+#endif
+        } s;
+};
+
+union cvmx_sriox_imsg_qos_grpx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_qos_grpx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_63_63:1;
+                uint64_t qos7:3;
+                uint64_t grp7:4;
+                uint64_t reserved_55_55:1;
+                uint64_t qos6:3;
+                uint64_t grp6:4;
+                uint64_t reserved_47_47:1;
+                uint64_t qos5:3;
+                uint64_t grp5:4;
+                uint64_t reserved_39_39:1;
+                uint64_t qos4:3;
+                uint64_t grp4:4;
+                uint64_t reserved_31_31:1;
+                uint64_t qos3:3;
+                uint64_t grp3:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos2:3;
+                uint64_t grp2:4;
+                uint64_t reserved_15_15:1;
+                uint64_t qos1:3;
+                uint64_t grp1:4;
+                uint64_t reserved_7_7:1;
+                uint64_t qos0:3;
+                uint64_t grp0:4;
+#else
+                uint64_t grp0:4;
+                uint64_t qos0:3;
+                uint64_t reserved_7_7:1;
+                uint64_t grp1:4;
+                uint64_t qos1:3;
+                uint64_t reserved_15_15:1;
+                uint64_t grp2:4;
+                uint64_t qos2:3;
+                uint64_t reserved_23_23:1;
+                uint64_t grp3:4;
+                uint64_t qos3:3;
+                uint64_t reserved_31_31:1;
+                uint64_t grp4:4;
+                uint64_t qos4:3;
+                uint64_t reserved_39_39:1;
+                uint64_t grp5:4;
+                uint64_t qos5:3;
+                uint64_t reserved_47_47:1;
+                uint64_t grp6:4;
+                uint64_t qos6:3;
+                uint64_t reserved_55_55:1;
+                uint64_t grp7:4;
+                uint64_t qos7:3;
+                uint64_t reserved_63_63:1;
+#endif
+        } s;
+};
+
+union cvmx_sriox_imsg_statusx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_statusx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t val1:1;
+                uint64_t err1:1;
+                uint64_t toe1:1;
+                uint64_t toc1:1;
+                uint64_t prt1:1;
+                uint64_t reserved_58_58:1;
+                uint64_t tt1:1;
+                uint64_t dis1:1;
+                uint64_t seg1:4;
+                uint64_t mbox1:2;
+                uint64_t lttr1:2;
+                uint64_t sid1:16;
+                uint64_t val0:1;
+                uint64_t err0:1;
+                uint64_t toe0:1;
+                uint64_t toc0:1;
+                uint64_t prt0:1;
+                uint64_t reserved_26_26:1;
+                uint64_t tt0:1;
+                uint64_t dis0:1;
+                uint64_t seg0:4;
+                uint64_t mbox0:2;
+                uint64_t lttr0:2;
+                uint64_t sid0:16;
+#else
+                uint64_t sid0:16;
+                uint64_t lttr0:2;
+                uint64_t mbox0:2;
+                uint64_t seg0:4;
+                uint64_t dis0:1;
+                uint64_t tt0:1;
+                uint64_t reserved_26_26:1;
+                uint64_t prt0:1;
+                uint64_t toc0:1;
+                uint64_t toe0:1;
+                uint64_t err0:1;
+                uint64_t val0:1;
+                uint64_t sid1:16;
+                uint64_t lttr1:2;
+                uint64_t mbox1:2;
+                uint64_t seg1:4;
+                uint64_t dis1:1;
+                uint64_t tt1:1;
+                uint64_t reserved_58_58:1;
+                uint64_t prt1:1;
+                uint64_t toc1:1;
+                uint64_t toe1:1;
+                uint64_t err1:1;
+                uint64_t val1:1;
+#endif
+        } s;
+};
+
+union cvmx_sriox_imsg_vport_thr {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_54_63:10;
+                uint64_t max_tot:6;
+                uint64_t reserved_46_47:2;
+                uint64_t max_s1:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s0:6;
+                uint64_t sp_vport:1;
+                uint64_t reserved_20_30:11;
+                uint64_t buf_thr:4;
+                uint64_t reserved_14_15:2;
+                uint64_t max_p1:6;
+                uint64_t reserved_6_7:2;
+                uint64_t max_p0:6;
+#else
+                uint64_t max_p0:6;
+                uint64_t reserved_6_7:2;
+                uint64_t max_p1:6;
+                uint64_t reserved_14_15:2;
+                uint64_t buf_thr:4;
+                uint64_t reserved_20_30:11;
+                uint64_t sp_vport:1;
+                uint64_t max_s0:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s1:6;
+                uint64_t reserved_46_47:2;
+                uint64_t max_tot:6;
+                uint64_t reserved_54_63:10;
+#endif
+        } s;
+};
+
+union cvmx_sriox_imsg_vport_thr2 {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_46_63:18;
+                uint64_t max_s3:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s2:6;
+                uint64_t reserved_0_31:32;
+#else
+                uint64_t reserved_0_31:32;
+                uint64_t max_s2:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s3:6;
+                uint64_t reserved_46_63:18;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int2_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int2_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t pko_rst:1;
+#else
+                uint64_t pko_rst:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int2_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int2_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t int_sum:1;
+                uint64_t reserved_1_30:30;
+                uint64_t pko_rst:1;
+#else
+                uint64_t pko_rst:1;
+                uint64_t reserved_1_30:30;
+                uint64_t int_sum:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_27_63:37;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrade:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+#else
+                uint64_t txbell:1;
+                uint64_t bell_err:1;
+                uint64_t rxbell:1;
+                uint64_t maint_op:1;
+                uint64_t bar_err:1;
+                uint64_t deny_wr:1;
+                uint64_t sli_err:1;
+                uint64_t wr_done:1;
+                uint64_t mce_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t soft_rx:1;
+                uint64_t log_erb:1;
+                uint64_t phy_erb:1;
+                uint64_t link_dwn:1;
+                uint64_t link_up:1;
+                uint64_t omsg0:1;
+                uint64_t omsg1:1;
+                uint64_t omsg_err:1;
+                uint64_t pko_err:1;
+                uint64_t rtry_err:1;
+                uint64_t f_error:1;
+                uint64_t mac_buf:1;
+                uint64_t degrade:1;
+                uint64_t fail:1;
+                uint64_t ttl_tout:1;
+                uint64_t zero_pkt:1;
+                uint64_t reserved_27_63:37;
+#endif
+        } s;
+        struct cvmx_sriox_int_enable_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+#else
+                uint64_t txbell:1;
+                uint64_t bell_err:1;
+                uint64_t rxbell:1;
+                uint64_t maint_op:1;
+                uint64_t bar_err:1;
+                uint64_t deny_wr:1;
+                uint64_t sli_err:1;
+                uint64_t wr_done:1;
+                uint64_t mce_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t soft_rx:1;
+                uint64_t log_erb:1;
+                uint64_t phy_erb:1;
+                uint64_t link_dwn:1;
+                uint64_t link_up:1;
+                uint64_t omsg0:1;
+                uint64_t omsg1:1;
+                uint64_t omsg_err:1;
+                uint64_t pko_err:1;
+                uint64_t rtry_err:1;
+                uint64_t f_error:1;
+                uint64_t reserved_22_63:42;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_sriox_int_info0 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t cmd:4;
+                uint64_t type:4;
+                uint64_t tag:8;
+                uint64_t reserved_42_47:6;
+                uint64_t length:10;
+                uint64_t status:3;
+                uint64_t reserved_16_28:13;
+                uint64_t be0:8;
+                uint64_t be1:8;
+#else
+                uint64_t be1:8;
+                uint64_t be0:8;
+                uint64_t reserved_16_28:13;
+                uint64_t status:3;
+                uint64_t length:10;
+                uint64_t reserved_42_47:6;
+                uint64_t tag:8;
+                uint64_t type:4;
+                uint64_t cmd:4;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int_info1 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t info1:64;
+#else
+                uint64_t info1:64;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int_info2 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t prio:2;
+                uint64_t tt:1;
+                uint64_t sis:1;
+                uint64_t ssize:4;
+                uint64_t did:16;
+                uint64_t xmbox:4;
+                uint64_t mbox:2;
+                uint64_t letter:2;
+                uint64_t rsrvd:30;
+                uint64_t lns:1;
+                uint64_t intr:1;
+#else
+                uint64_t intr:1;
+                uint64_t lns:1;
+                uint64_t rsrvd:30;
+                uint64_t letter:2;
+                uint64_t mbox:2;
+                uint64_t xmbox:4;
+                uint64_t did:16;
+                uint64_t ssize:4;
+                uint64_t sis:1;
+                uint64_t tt:1;
+                uint64_t prio:2;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int_info3 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t prio:2;
+                uint64_t tt:2;
+                uint64_t type:4;
+                uint64_t other:48;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t other:48;
+                uint64_t type:4;
+                uint64_t tt:2;
+                uint64_t prio:2;
+#endif
+        } s;
+};
+
+union cvmx_sriox_int_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t int2_sum:1;
+                uint64_t reserved_27_30:4;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrad:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+#else
+                uint64_t txbell:1;
+                uint64_t bell_err:1;
+                uint64_t rxbell:1;
+                uint64_t maint_op:1;
+                uint64_t bar_err:1;
+                uint64_t deny_wr:1;
+                uint64_t sli_err:1;
+                uint64_t wr_done:1;
+                uint64_t mce_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t soft_rx:1;
+                uint64_t log_erb:1;
+                uint64_t phy_erb:1;
+                uint64_t link_dwn:1;
+                uint64_t link_up:1;
+                uint64_t omsg0:1;
+                uint64_t omsg1:1;
+                uint64_t omsg_err:1;
+                uint64_t pko_err:1;
+                uint64_t rtry_err:1;
+                uint64_t f_error:1;
+                uint64_t mac_buf:1;
+                uint64_t degrad:1;
+                uint64_t fail:1;
+                uint64_t ttl_tout:1;
+                uint64_t zero_pkt:1;
+                uint64_t reserved_27_30:4;
+                uint64_t int2_sum:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_sriox_int_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+#else
+                uint64_t txbell:1;
+                uint64_t bell_err:1;
+                uint64_t rxbell:1;
+                uint64_t maint_op:1;
+                uint64_t bar_err:1;
+                uint64_t deny_wr:1;
+                uint64_t sli_err:1;
+                uint64_t wr_done:1;
+                uint64_t mce_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t soft_rx:1;
+                uint64_t log_erb:1;
+                uint64_t phy_erb:1;
+                uint64_t link_dwn:1;
+                uint64_t link_up:1;
+                uint64_t omsg0:1;
+                uint64_t omsg1:1;
+                uint64_t omsg_err:1;
+                uint64_t pko_err:1;
+                uint64_t rtry_err:1;
+                uint64_t f_error:1;
+                uint64_t reserved_22_63:42;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_sriox_ip_feature {
+        uint64_t u64;
+        struct cvmx_sriox_ip_feature_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ops:32;
+                uint64_t reserved_15_31:17;
+                uint64_t no_vmin:1;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+#else
+                uint64_t rx_pol:4;
+                uint64_t tx_pol:4;
+                uint64_t pt_width:2;
+                uint64_t tx_flow:1;
+                uint64_t reserved_11_11:1;
+                uint64_t a50:1;
+                uint64_t a66:1;
+                uint64_t no_vmin:1;
+                uint64_t reserved_15_31:17;
+                uint64_t ops:32;
+#endif
+        } s;
+        struct cvmx_sriox_ip_feature_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t ops:32;
+                uint64_t reserved_14_31:18;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+#else
+                uint64_t rx_pol:4;
+                uint64_t tx_pol:4;
+                uint64_t pt_width:2;
+                uint64_t tx_flow:1;
+                uint64_t reserved_11_11:1;
+                uint64_t a50:1;
+                uint64_t a66:1;
+                uint64_t reserved_14_31:18;
+                uint64_t ops:32;
+#endif
+        } cn63xx;
+};
+
+union cvmx_sriox_mac_buffers {
+        uint64_t u64;
+        struct cvmx_sriox_mac_buffers_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_56_63:8;
+                uint64_t tx_enb:8;
+                uint64_t reserved_44_47:4;
+                uint64_t tx_inuse:4;
+                uint64_t tx_stat:8;
+                uint64_t reserved_24_31:8;
+                uint64_t rx_enb:8;
+                uint64_t reserved_12_15:4;
+                uint64_t rx_inuse:4;
+                uint64_t rx_stat:8;
+#else
+                uint64_t rx_stat:8;
+                uint64_t rx_inuse:4;
+                uint64_t reserved_12_15:4;
+                uint64_t rx_enb:8;
+                uint64_t reserved_24_31:8;
+                uint64_t tx_stat:8;
+                uint64_t tx_inuse:4;
+                uint64_t reserved_44_47:4;
+                uint64_t tx_enb:8;
+                uint64_t reserved_56_63:8;
+#endif
+        } s;
+};
+
+union cvmx_sriox_maint_op {
+        uint64_t u64;
+        struct cvmx_sriox_maint_op_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t wr_data:32;
+                uint64_t reserved_27_31:5;
+                uint64_t fail:1;
+                uint64_t pending:1;
+                uint64_t op:1;
+                uint64_t addr:24;
+#else
+                uint64_t addr:24;
+                uint64_t op:1;
+                uint64_t pending:1;
+                uint64_t fail:1;
+                uint64_t reserved_27_31:5;
+                uint64_t wr_data:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_maint_rd_data {
+        uint64_t u64;
+        struct cvmx_sriox_maint_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_33_63:31;
+                uint64_t valid:1;
+                uint64_t rd_data:32;
+#else
+                uint64_t rd_data:32;
+                uint64_t valid:1;
+                uint64_t reserved_33_63:31;
+#endif
+        } s;
+};
+
+union cvmx_sriox_mce_tx_ctl {
+        uint64_t u64;
+        struct cvmx_sriox_mce_tx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t mce:1;
+#else
+                uint64_t mce:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_sriox_mem_op_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_mem_op_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t rr_ro:1;
+                uint64_t w_ro:1;
+                uint64_t reserved_6_7:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+#else
+                uint64_t rp0_pid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_sid:1;
+                uint64_t reserved_6_7:2;
+                uint64_t w_ro:1;
+                uint64_t rr_ro:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_sriox_omsg_ctrlx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_ctrlx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t testmode:1;
+                uint64_t reserved_37_62:26;
+                uint64_t silo_max:5;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+#else
+                uint64_t lttr_mp:4;
+                uint64_t lttr_sp:4;
+                uint64_t idm_did:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_tt:1;
+                uint64_t reserved_11_14:4;
+                uint64_t rtry_en:1;
+                uint64_t rtry_thr:16;
+                uint64_t silo_max:5;
+                uint64_t reserved_37_62:26;
+                uint64_t testmode:1;
+#endif
+        } s;
+        struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t testmode:1;
+                uint64_t reserved_32_62:31;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+#else
+                uint64_t lttr_mp:4;
+                uint64_t lttr_sp:4;
+                uint64_t idm_did:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_tt:1;
+                uint64_t reserved_11_14:4;
+                uint64_t rtry_en:1;
+                uint64_t rtry_thr:16;
+                uint64_t reserved_32_62:31;
+                uint64_t testmode:1;
+#endif
+        } cn63xxp1;
+};
+
+union cvmx_sriox_omsg_done_countsx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_done_countsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+#else
+                uint64_t good:16;
+                uint64_t bad:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_omsg_fmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_fmp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+#else
+                uint64_t all_psd:1;
+                uint64_t all_nmp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_sp:1;
+                uint64_t mbox_psd:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_sp:1;
+                uint64_t id_psd:1;
+                uint64_t id_nmp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_sp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+};
+
+union cvmx_sriox_omsg_nmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_nmp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t reserved_8_8:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t reserved_4_4:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t reserved_0_0:1;
+#else
+                uint64_t reserved_0_0:1;
+                uint64_t all_nmp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_sp:1;
+                uint64_t reserved_4_4:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_sp:1;
+                uint64_t reserved_8_8:1;
+                uint64_t id_nmp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_sp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t reserved_15_63:49;
+#endif
+        } s;
+};
+
+union cvmx_sriox_omsg_portx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_3_30:28;
+                uint64_t port:3;
+#else
+                uint64_t port:3;
+                uint64_t reserved_3_30:28;
+                uint64_t enable:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+        struct cvmx_sriox_omsg_portx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_2_30:29;
+                uint64_t port:2;
+#else
+                uint64_t port:2;
+                uint64_t reserved_2_30:29;
+                uint64_t enable:1;
+                uint64_t reserved_32_63:32;
+#endif
+        } cn63xx;
+};
+
+union cvmx_sriox_omsg_silo_thr {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_silo_thr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t tot_silo:5;
+#else
+                uint64_t tot_silo:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_sriox_omsg_sp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_sp_mrx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t xmbox_sp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+#else
+                uint64_t all_psd:1;
+                uint64_t all_nmp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_sp:1;
+                uint64_t mbox_psd:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_sp:1;
+                uint64_t id_psd:1;
+                uint64_t id_nmp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_sp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t xmbox_sp:1;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_sriox_priox_in_use {
+        uint64_t u64;
+        struct cvmx_sriox_priox_in_use_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t end_cnt:16;
+                uint64_t start_cnt:16;
+#else
+                uint64_t start_cnt:16;
+                uint64_t end_cnt:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_rx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t src_id:16;
+                uint64_t count:8;
+                uint64_t reserved_5_7:3;
+                uint64_t dest_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+#else
+                uint64_t priority:2;
+                uint64_t reserved_2_2:1;
+                uint64_t id16:1;
+                uint64_t dest_id:1;
+                uint64_t reserved_5_7:3;
+                uint64_t count:8;
+                uint64_t src_id:16;
+                uint64_t data:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_sriox_rx_bell_seq {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_seq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_40_63:24;
+                uint64_t count:8;
+                uint64_t seq:32;
+#else
+                uint64_t seq:32;
+                uint64_t count:8;
+                uint64_t reserved_40_63:24;
+#endif
+        } s;
+};
+
+union cvmx_sriox_rx_status {
+        uint64_t u64;
+        struct cvmx_sriox_rx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t rtn_pr3:8;
+                uint64_t rtn_pr2:8;
+                uint64_t rtn_pr1:8;
+                uint64_t reserved_28_39:12;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+#else
+                uint64_t post:8;
+                uint64_t n_post:5;
+                uint64_t reserved_13_15:3;
+                uint64_t comp:8;
+                uint64_t mbox:4;
+                uint64_t reserved_28_39:12;
+                uint64_t rtn_pr1:8;
+                uint64_t rtn_pr2:8;
+                uint64_t rtn_pr3:8;
+#endif
+        } s;
+};
+
+union cvmx_sriox_s2m_typex {
+        uint64_t u64;
+        struct cvmx_sriox_s2m_typex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t wr_op:3;
+                uint64_t reserved_15_15:1;
+                uint64_t rd_op:3;
+                uint64_t wr_prior:2;
+                uint64_t rd_prior:2;
+                uint64_t reserved_6_7:2;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_3:2;
+                uint64_t iaow_sel:2;
+#else
+                uint64_t iaow_sel:2;
+                uint64_t reserved_2_3:2;
+                uint64_t id16:1;
+                uint64_t src_id:1;
+                uint64_t reserved_6_7:2;
+                uint64_t rd_prior:2;
+                uint64_t wr_prior:2;
+                uint64_t rd_op:3;
+                uint64_t reserved_15_15:1;
+                uint64_t wr_op:3;
+                uint64_t reserved_19_63:45;
+#endif
+        } s;
+};
+
+union cvmx_sriox_seq {
+        uint64_t u64;
+        struct cvmx_sriox_seq_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t seq:32;
+#else
+                uint64_t seq:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_status_reg {
+        uint64_t u64;
+        struct cvmx_sriox_status_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_2_63:62;
+                uint64_t access:1;
+                uint64_t srio:1;
+#else
+                uint64_t srio:1;
+                uint64_t access:1;
+                uint64_t reserved_2_63:62;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tag_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tag_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t o_clr:1;
+                uint64_t reserved_13_15:3;
+                uint64_t otag:5;
+                uint64_t reserved_5_7:3;
+                uint64_t itag:5;
+#else
+                uint64_t itag:5;
+                uint64_t reserved_5_7:3;
+                uint64_t otag:5;
+                uint64_t reserved_13_15:3;
+                uint64_t o_clr:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tlp_credits {
+        uint64_t u64;
+        struct cvmx_sriox_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_28_63:36;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+#else
+                uint64_t post:8;
+                uint64_t n_post:5;
+                uint64_t reserved_13_15:3;
+                uint64_t comp:8;
+                uint64_t mbox:4;
+                uint64_t reserved_28_63:36;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_9_15:7;
+                uint64_t pending:1;
+                uint64_t reserved_5_7:3;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+#else
+                uint64_t priority:2;
+                uint64_t reserved_2_2:1;
+                uint64_t id16:1;
+                uint64_t src_id:1;
+                uint64_t reserved_5_7:3;
+                uint64_t pending:1;
+                uint64_t reserved_9_15:7;
+                uint64_t dest_id:16;
+                uint64_t data:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tx_bell_info {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_8_15:8;
+                uint64_t timeout:1;
+                uint64_t error:1;
+                uint64_t retry:1;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+#else
+                uint64_t priority:2;
+                uint64_t reserved_2_2:1;
+                uint64_t id16:1;
+                uint64_t src_id:1;
+                uint64_t retry:1;
+                uint64_t error:1;
+                uint64_t timeout:1;
+                uint64_t reserved_8_15:8;
+                uint64_t dest_id:16;
+                uint64_t data:16;
+                uint64_t reserved_48_63:16;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tx_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tx_ctrl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_53_63:11;
+                uint64_t tag_th2:5;
+                uint64_t reserved_45_47:3;
+                uint64_t tag_th1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t tag_th0:5;
+                uint64_t reserved_20_31:12;
+                uint64_t tx_th2:4;
+                uint64_t reserved_12_15:4;
+                uint64_t tx_th1:4;
+                uint64_t reserved_4_7:4;
+                uint64_t tx_th0:4;
+#else
+                uint64_t tx_th0:4;
+                uint64_t reserved_4_7:4;
+                uint64_t tx_th1:4;
+                uint64_t reserved_12_15:4;
+                uint64_t tx_th2:4;
+                uint64_t reserved_20_31:12;
+                uint64_t tag_th0:5;
+                uint64_t reserved_37_39:3;
+                uint64_t tag_th1:5;
+                uint64_t reserved_45_47:3;
+                uint64_t tag_th2:5;
+                uint64_t reserved_53_63:11;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tx_emphasis {
+        uint64_t u64;
+        struct cvmx_sriox_tx_emphasis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t emph:4;
+#else
+                uint64_t emph:4;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_sriox_tx_status {
+        uint64_t u64;
+        struct cvmx_sriox_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t s2m_pr3:8;
+                uint64_t s2m_pr2:8;
+                uint64_t s2m_pr1:8;
+                uint64_t s2m_pr0:8;
+#else
+                uint64_t s2m_pr0:8;
+                uint64_t s2m_pr1:8;
+                uint64_t s2m_pr2:8;
+                uint64_t s2m_pr3:8;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_sriox_wr_done_counts {
+        uint64_t u64;
+        struct cvmx_sriox_wr_done_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+#else
+                uint64_t good:16;
+                uint64_t bad:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
new file mode 100644
index 000000000..76b2a42f5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
@@ -0,0 +1,140 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRXX_DEFS_H__
+#define __CVMX_SRXX_DEFS_H__
+
+#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
+#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
+
+union cvmx_srxx_com_ctl {
+        uint64_t u64;
+        struct cvmx_srxx_com_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t prts:4;
+                uint64_t st_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t inf_en:1;
+#else
+                uint64_t inf_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t st_en:1;
+                uint64_t prts:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_srxx_ign_rx_full {
+        uint64_t u64;
+        struct cvmx_srxx_ign_rx_full_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t ignore:16;
+#else
+                uint64_t ignore:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_srxx_spi4_calx {
+        uint64_t u64;
+        struct cvmx_srxx_spi4_calx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t oddpar:1;
+                uint64_t prt3:4;
+                uint64_t prt2:4;
+                uint64_t prt1:4;
+                uint64_t prt0:4;
+#else
+                uint64_t prt0:4;
+                uint64_t prt1:4;
+                uint64_t prt2:4;
+                uint64_t prt3:4;
+                uint64_t oddpar:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_srxx_spi4_stat {
+        uint64_t u64;
+        struct cvmx_srxx_spi4_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t m:8;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+#else
+                uint64_t len:7;
+                uint64_t reserved_7_7:1;
+                uint64_t m:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_srxx_sw_tick_ctl {
+        uint64_t u64;
+        struct cvmx_srxx_sw_tick_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_14_63:50;
+                uint64_t eop:1;
+                uint64_t sop:1;
+                uint64_t mod:4;
+                uint64_t opc:4;
+                uint64_t adr:4;
+#else
+                uint64_t adr:4;
+                uint64_t opc:4;
+                uint64_t mod:4;
+                uint64_t sop:1;
+                uint64_t eop:1;
+                uint64_t reserved_14_63:50;
+#endif
+        } s;
+};
+
+union cvmx_srxx_sw_tick_dat {
+        uint64_t u64;
+        struct cvmx_srxx_sw_tick_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t dat:64;
+#else
+                uint64_t dat:64;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
new file mode 100644
index 000000000..f49d82145
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
@@ -0,0 +1,330 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (C) 2003-2018 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_STXX_DEFS_H__
+#define __CVMX_STXX_DEFS_H__
+
+#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
+#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
+
+void __cvmx_interrupt_stxx_int_msk_enable(int index);
+
+union cvmx_stxx_arb_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_arb_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t mintrn:1;
+                uint64_t reserved_4_4:1;
+                uint64_t igntpa:1;
+                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t igntpa:1;
+                uint64_t reserved_4_4:1;
+                uint64_t mintrn:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_stxx_bckprs_cnt {
+        uint64_t u64;
+        struct cvmx_stxx_bckprs_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_stxx_com_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_com_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_4_63:60;
+                uint64_t st_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t inf_en:1;
+#else
+                uint64_t inf_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t st_en:1;
+                uint64_t reserved_4_63:60;
+#endif
+        } s;
+};
+
+union cvmx_stxx_dip_cnt {
+        uint64_t u64;
+        struct cvmx_stxx_dip_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t frmmax:4;
+                uint64_t dipmax:4;
+#else
+                uint64_t dipmax:4;
+                uint64_t frmmax:4;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_stxx_ign_cal {
+        uint64_t u64;
+        struct cvmx_stxx_ign_cal_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t igntpa:16;
+#else
+                uint64_t igntpa:16;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_stxx_int_msk {
+        uint64_t u64;
+        struct cvmx_stxx_int_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+#else
+                uint64_t calpar0:1;
+                uint64_t calpar1:1;
+                uint64_t ovrbst:1;
+                uint64_t datovr:1;
+                uint64_t diperr:1;
+                uint64_t nosync:1;
+                uint64_t unxfrm:1;
+                uint64_t frmerr:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_stxx_int_reg {
+        uint64_t u64;
+        struct cvmx_stxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t syncerr:1;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+#else
+                uint64_t calpar0:1;
+                uint64_t calpar1:1;
+                uint64_t ovrbst:1;
+                uint64_t datovr:1;
+                uint64_t diperr:1;
+                uint64_t nosync:1;
+                uint64_t unxfrm:1;
+                uint64_t frmerr:1;
+                uint64_t syncerr:1;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_stxx_int_sync {
+        uint64_t u64;
+        struct cvmx_stxx_int_sync_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+#else
+                uint64_t calpar0:1;
+                uint64_t calpar1:1;
+                uint64_t ovrbst:1;
+                uint64_t datovr:1;
+                uint64_t diperr:1;
+                uint64_t nosync:1;
+                uint64_t unxfrm:1;
+                uint64_t frmerr:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_stxx_min_bst {
+        uint64_t u64;
+        struct cvmx_stxx_min_bst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_9_63:55;
+                uint64_t minb:9;
+#else
+                uint64_t minb:9;
+                uint64_t reserved_9_63:55;
+#endif
+        } s;
+};
+
+union cvmx_stxx_spi4_calx {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_calx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_17_63:47;
+                uint64_t oddpar:1;
+                uint64_t prt3:4;
+                uint64_t prt2:4;
+                uint64_t prt1:4;
+                uint64_t prt0:4;
+#else
+                uint64_t prt0:4;
+                uint64_t prt1:4;
+                uint64_t prt2:4;
+                uint64_t prt3:4;
+                uint64_t oddpar:1;
+                uint64_t reserved_17_63:47;
+#endif
+        } s;
+};
+
+union cvmx_stxx_spi4_dat {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t alpha:16;
+                uint64_t max_t:16;
+#else
+                uint64_t max_t:16;
+                uint64_t alpha:16;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_stxx_spi4_stat {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_stat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_16_63:48;
+                uint64_t m:8;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+#else
+                uint64_t len:7;
+                uint64_t reserved_7_7:1;
+                uint64_t m:8;
+                uint64_t reserved_16_63:48;
+#endif
+        } s;
+};
+
+union cvmx_stxx_stat_bytes_hi {
+        uint64_t u64;
+        struct cvmx_stxx_stat_bytes_hi_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_stxx_stat_bytes_lo {
+        uint64_t u64;
+        struct cvmx_stxx_stat_bytes_lo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_stxx_stat_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_stat_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t clr:1;
+                uint64_t bckprs:4;
+#else
+                uint64_t bckprs:4;
+                uint64_t clr:1;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_stxx_stat_pkt_xmt {
+        uint64_t u64;
+        struct cvmx_stxx_stat_pkt_xmt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+#else
+                uint64_t cnt:32;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
new file mode 100644
index 000000000..c6c3ee39c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -0,0 +1,125 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2016 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * This module provides system/board information obtained by the bootloader.
+ */
+
+#ifndef __CVMX_SYSINFO_H__
+#define __CVMX_SYSINFO_H__
+
+#include "cvmx-coremask.h"
+
+#define OCTEON_SERIAL_LEN 20
+/**
+ * Structure describing application specific information.
+ * __cvmx_app_init() populates this from the cvmx boot descriptor.
+ * This structure is private to simple executive applications, so
+ * no versioning is required.
+ *
+ * This structure must be provided with some fields set in order to
+ * use simple executive functions in other applications (Linux kernel,
+ * u-boot, etc.)  The cvmx_sysinfo_minimal_initialize() function is
+ * provided to set the required values in these cases.
+ */
+struct cvmx_sysinfo {
+        /* System wide variables */
+        /* installed DRAM in system, in bytes */
+        uint64_t system_dram_size;
+
+        /* ptr to memory descriptor block */
+        uint64_t phy_mem_desc_addr;
+
+        /* Application image specific variables */
+        /* stack top address (virtual) */
+        uint64_t stack_top;
+        /* heap base address (virtual) */
+        uint64_t heap_base;
+        /* stack size in bytes */
+        uint32_t stack_size;
+        /* heap size in bytes */
+        uint32_t heap_size;
+        /* coremask defining cores running application */
+        struct cvmx_coremask core_mask;
+        /* Deprecated, use cvmx_coremask_first_core() to select init core */
+        uint32_t init_core;
+
+        /* exception base address, as set by bootloader */
+        uint64_t exception_base_addr;
+
+        /* cpu clock speed in hz */
+        uint32_t cpu_clock_hz;
+
+        /* dram data rate in hz (data rate = 2 * clock rate */
+        uint32_t dram_data_rate_hz;
+
+
+        uint16_t board_type;
+        uint8_t board_rev_major;
+        uint8_t board_rev_minor;
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+        char board_serial_number[OCTEON_SERIAL_LEN];
+        /*
+         * Several boards support compact flash on the Octeon boot
+         * bus.  The CF memory spaces may be mapped to different
+         * addresses on different boards.  These values will be 0 if
+         * CF is not present.  Note that these addresses are physical
+         * addresses, and it is up to the application to use the
+         * proper addressing mode (XKPHYS, KSEG0, etc.)
+         */
+        uint64_t compact_flash_common_base_addr;
+        uint64_t compact_flash_attribute_base_addr;
+        /*
+         * Base address of the LED display (as on EBT3000 board) This
+         * will be 0 if LED display not present.  Note that this
+         * address is a physical address, and it is up to the
+         * application to use the proper addressing mode (XKPHYS,
+         * KSEG0, etc.)
+         */
+        uint64_t led_display_base_addr;
+        /* DFA reference clock in hz (if applicable)*/
+        uint32_t dfa_ref_clock_hz;
+        /* configuration flags from bootloader */
+        uint32_t bootloader_config_flags;
+
+        /* Uart number used for console */
+        uint8_t console_uart_num;
+};
+
+/**
+ * This function returns the system/board information as obtained
+ * by the bootloader.
+ *
+ *
+ * Returns  Pointer to the boot information structure
+ *
+ */
+
+extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
+
+#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
new file mode 100644
index 000000000..6cf228016
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -0,0 +1,386 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2012 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_UCTLX_DEFS_H__
+#define __CVMX_UCTLX_DEFS_H__
+
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+
+union cvmx_uctlx_bist_status {
+        uint64_t u64;
+        struct cvmx_uctlx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t data_bis:1;
+                uint64_t desc_bis:1;
+                uint64_t erbm_bis:1;
+                uint64_t orbm_bis:1;
+                uint64_t wrbm_bis:1;
+                uint64_t ppaf_bis:1;
+#else
+                uint64_t ppaf_bis:1;
+                uint64_t wrbm_bis:1;
+                uint64_t orbm_bis:1;
+                uint64_t erbm_bis:1;
+                uint64_t desc_bis:1;
+                uint64_t data_bis:1;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_clk_rst_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_clk_rst_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_25_63:39;
+                uint64_t clear_bist:1;
+                uint64_t start_bist:1;
+                uint64_t ehci_sm:1;
+                uint64_t ohci_clkcktrst:1;
+                uint64_t ohci_sm:1;
+                uint64_t ohci_susp_lgcy:1;
+                uint64_t app_start_clk:1;
+                uint64_t o_clkdiv_rst:1;
+                uint64_t h_clkdiv_byp:1;
+                uint64_t h_clkdiv_rst:1;
+                uint64_t h_clkdiv_en:1;
+                uint64_t o_clkdiv_en:1;
+                uint64_t h_div:4;
+                uint64_t p_refclk_sel:2;
+                uint64_t p_refclk_div:2;
+                uint64_t reserved_4_4:1;
+                uint64_t p_com_on:1;
+                uint64_t p_por:1;
+                uint64_t p_prst:1;
+                uint64_t hrst:1;
+#else
+                uint64_t hrst:1;
+                uint64_t p_prst:1;
+                uint64_t p_por:1;
+                uint64_t p_com_on:1;
+                uint64_t reserved_4_4:1;
+                uint64_t p_refclk_div:2;
+                uint64_t p_refclk_sel:2;
+                uint64_t h_div:4;
+                uint64_t o_clkdiv_en:1;
+                uint64_t h_clkdiv_en:1;
+                uint64_t h_clkdiv_rst:1;
+                uint64_t h_clkdiv_byp:1;
+                uint64_t o_clkdiv_rst:1;
+                uint64_t app_start_clk:1;
+                uint64_t ohci_susp_lgcy:1;
+                uint64_t ohci_sm:1;
+                uint64_t ohci_clkcktrst:1;
+                uint64_t ehci_sm:1;
+                uint64_t start_bist:1;
+                uint64_t clear_bist:1;
+                uint64_t reserved_25_63:39;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_ehci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_20_63:44;
+                uint64_t desc_rbm:1;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t ehci_64b_addr_en:1;
+                uint64_t l2c_addr_msb:8;
+#else
+                uint64_t l2c_addr_msb:8;
+                uint64_t ehci_64b_addr_en:1;
+                uint64_t inv_reg_a2:1;
+                uint64_t l2c_desc_emod:2;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_dc:1;
+                uint64_t reg_nb:1;
+                uint64_t desc_rbm:1;
+                uint64_t reserved_20_63:44;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_ehci_fla {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_fla_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_6_63:58;
+                uint64_t fla:6;
+#else
+                uint64_t fla:6;
+                uint64_t reserved_6_63:58;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_erto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_erto_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:27;
+                uint64_t reserved_0_4:5;
+#else
+                uint64_t reserved_0_4:5;
+                uint64_t to_val:27;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_if_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_if_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t reserved_1_63:63;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_int_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+#else
+                uint64_t pp_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t wb_psh_f:1;
+                uint64_t wb_pop_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t ec_ovf_e:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_int_reg {
+        uint64_t u64;
+        struct cvmx_uctlx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+#else
+                uint64_t pp_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t wb_psh_f:1;
+                uint64_t wb_pop_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t ec_ovf_e:1;
+                uint64_t reserved_8_63:56;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_ohci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ohci_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_19_63:45;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t reserved_8_8:1;
+                uint64_t l2c_addr_msb:8;
+#else
+                uint64_t l2c_addr_msb:8;
+                uint64_t reserved_8_8:1;
+                uint64_t inv_reg_a2:1;
+                uint64_t l2c_desc_emod:2;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_dc:1;
+                uint64_t reg_nb:1;
+                uint64_t reserved_19_63:45;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_orto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_orto_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:24;
+                uint64_t reserved_0_7:8;
+#else
+                uint64_t reserved_0_7:8;
+                uint64_t to_val:24;
+                uint64_t reserved_32_63:32;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_ppaf_wm {
+        uint64_t u64;
+        struct cvmx_uctlx_ppaf_wm_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_5_63:59;
+                uint64_t wm:5;
+#else
+                uint64_t wm:5;
+                uint64_t reserved_5_63:59;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_uphy_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_10_63:54;
+                uint64_t bist_done:1;
+                uint64_t bist_err:1;
+                uint64_t hsbist:1;
+                uint64_t fsbist:1;
+                uint64_t lsbist:1;
+                uint64_t siddq:1;
+                uint64_t vtest_en:1;
+                uint64_t uphy_bist:1;
+                uint64_t bist_en:1;
+                uint64_t ate_reset:1;
+#else
+                uint64_t ate_reset:1;
+                uint64_t bist_en:1;
+                uint64_t uphy_bist:1;
+                uint64_t vtest_en:1;
+                uint64_t siddq:1;
+                uint64_t lsbist:1;
+                uint64_t fsbist:1;
+                uint64_t hsbist:1;
+                uint64_t bist_err:1;
+                uint64_t bist_done:1;
+                uint64_t reserved_10_63:54;
+#endif
+        } s;
+};
+
+union cvmx_uctlx_uphy_portx_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t reserved_43_63:21;
+                uint64_t tdata_out:4;
+                uint64_t txbiststuffenh:1;
+                uint64_t txbiststuffen:1;
+                uint64_t dmpulldown:1;
+                uint64_t dppulldown:1;
+                uint64_t vbusvldext:1;
+                uint64_t portreset:1;
+                uint64_t txhsvxtune:2;
+                uint64_t txvreftune:4;
+                uint64_t txrisetune:1;
+                uint64_t txpreemphasistune:1;
+                uint64_t txfslstune:4;
+                uint64_t sqrxtune:3;
+                uint64_t compdistune:3;
+                uint64_t loop_en:1;
+                uint64_t tclk:1;
+                uint64_t tdata_sel:1;
+                uint64_t taddr_in:4;
+                uint64_t tdata_in:8;
+#else
+                uint64_t tdata_in:8;
+                uint64_t taddr_in:4;
+                uint64_t tdata_sel:1;
+                uint64_t tclk:1;
+                uint64_t loop_en:1;
+                uint64_t compdistune:3;
+                uint64_t sqrxtune:3;
+                uint64_t txfslstune:4;
+                uint64_t txpreemphasistune:1;
+                uint64_t txrisetune:1;
+                uint64_t txvreftune:4;
+                uint64_t txhsvxtune:2;
+                uint64_t portreset:1;
+                uint64_t vbusvldext:1;
+                uint64_t dppulldown:1;
+                uint64_t dmpulldown:1;
+                uint64_t txbiststuffen:1;
+                uint64_t txbiststuffenh:1;
+                uint64_t tdata_out:4;
+                uint64_t reserved_43_63:21;
+#endif
+        } s;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
new file mode 100644
index 000000000..9cec2299b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -0,0 +1,658 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * This header file defines the work queue entry (wqe) data structure.
+ * Since this is a commonly used structure that depends on structures
+ * from several hardware blocks, those definitions have been placed
+ * in this file to create a single point of definition of the wqe
+ * format.
+ * Data structures are still named according to the block that they
+ * relate to.
+ *
+ */
+
+#ifndef __CVMX_WQE_H__
+#define __CVMX_WQE_H__
+
+#include <asm/octeon/cvmx-packet.h>
+
+
+#define OCT_TAG_TYPE_STRING(x)                                          \
+        (((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" :              \
+                (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" :        \
+                        (((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" :    \
+                                "NULL_NULL")))
+
+/**
+ * HW decode / err_code in work queue entry
+ */
+typedef union {
+        uint64_t u64;
+
+        /* Use this struct if the hardware determines that the packet is IP */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /* HW sets this to the number of buffers used by this packet */
+                uint64_t bufs:8;
+                /* HW sets to the number of L2 bytes prior to the IP */
+                uint64_t ip_offset:8;
+                /* set to 1 if we found DSA/VLAN in the L2 */
+                uint64_t vlan_valid:1;
+                /* Set to 1 if the DSA/VLAN tag is stacked */
+                uint64_t vlan_stacked:1;
+                uint64_t unassigned:1;
+                /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+                uint64_t vlan_cfi:1;
+                /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+                uint64_t vlan_id:12;
+                /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+                uint64_t pr:4;
+                uint64_t unassigned2:8;
+                /* the packet needs to be decompressed */
+                uint64_t dec_ipcomp:1;
+                /* the packet is either TCP or UDP */
+                uint64_t tcp_or_udp:1;
+                /* the packet needs to be decrypted (ESP or AH) */
+                uint64_t dec_ipsec:1;
+                /* the packet is IPv6 */
+                uint64_t is_v6:1;
+
+                /*
+                 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
+                 * software, etc.).
+                 */
+
+                /*
+                 * reserved for software use, hardware will clear on
+                 * packet creation.
+                 */
+                uint64_t software:1;
+                /* exceptional conditions below */
+                /* the receive interface hardware detected an L4 error
+                 * (only applies if !is_frag) (only applies if
+                 * !rcv_error && !not_IP && !IP_exc && !is_frag)
+                 * failure indicated in err_code below, decode:
+                 *
+                 * - 1 = Malformed L4
+                 * - 2 = L4 Checksum Error: the L4 checksum value is
+                 * - 3 = UDP Length Error: The UDP length field would
+                 *       make the UDP data longer than what remains in
+                 *       the IP packet (as defined by the IP header
+                 *       length field).
+                 * - 4 = Bad L4 Port: either the source or destination
+                 *       TCP/UDP port is 0.
+                 * - 8 = TCP FIN Only: the packet is TCP and only the
+                 *       FIN flag set.
+                 * - 9 = TCP No Flags: the packet is TCP and no flags
+                 *       are set.
+                 * - 10 = TCP FIN RST: the packet is TCP and both FIN
+                 *        and RST are set.
+                 * - 11 = TCP SYN URG: the packet is TCP and both SYN
+                 *        and URG are set.
+                 * - 12 = TCP SYN RST: the packet is TCP and both SYN
+                 *        and RST are set.
+                 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
+                 *        and FIN are set.
+                 */
+                uint64_t L4_error:1;
+                /* set if the packet is a fragment */
+                uint64_t is_frag:1;
+                /* the receive interface hardware detected an IP error
+                 * / exception (only applies if !rcv_error && !not_IP)
+                 * failure indicated in err_code below, decode:
+                 *
+                 * - 1 = Not IP: the IP version field is neither 4 nor
+                 *       6.
+                 * - 2 = IPv4 Header Checksum Error: the IPv4 header
+                 *       has a checksum violation.
+                 * - 3 = IP Malformed Header: the packet is not long
+                 *       enough to contain the IP header.
+                 * - 4 = IP Malformed: the packet is not long enough
+                 *       to contain the bytes indicated by the IP
+                 *       header. Pad is allowed.
+                 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
+                 *       Hop Count field are zero.
+                 * - 6 = IP Options
+                 */
+                uint64_t IP_exc:1;
+                /*
+                 * Set if the hardware determined that the packet is a
+                 * broadcast.
+                 */
+                uint64_t is_bcast:1;
+                /*
+                 * St if the hardware determined that the packet is a
+                 * multi-cast.
+                 */
+                uint64_t is_mcast:1;
+                /*
+                 * Set if the packet may not be IP (must be zero in
+                 * this case).
+                 */
+                uint64_t not_IP:1;
+                /*
+                 * The receive interface hardware detected a receive
+                 * error (must be zero in this case).
+                 */
+                uint64_t rcv_error:1;
+                /* lower err_code = first-level descriptor of the
+                 * work */
+                /* zero for packet submitted by hardware that isn't on
+                 * the slow path */
+                /* type is cvmx_pip_err_t */
+                uint64_t err_code:8;
+#else
+                uint64_t err_code:8;
+                uint64_t rcv_error:1;
+                uint64_t not_IP:1;
+                uint64_t is_mcast:1;
+                uint64_t is_bcast:1;
+                uint64_t IP_exc:1;
+                uint64_t is_frag:1;
+                uint64_t L4_error:1;
+                uint64_t software:1;
+                uint64_t is_v6:1;
+                uint64_t dec_ipsec:1;
+                uint64_t tcp_or_udp:1;
+                uint64_t dec_ipcomp:1;
+                uint64_t unassigned2:4;
+                uint64_t unassigned2a:4;
+                uint64_t pr:4;
+                uint64_t vlan_id:12;
+                uint64_t vlan_cfi:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_stacked:1;
+                uint64_t vlan_valid:1;
+                uint64_t ip_offset:8;
+                uint64_t bufs:8;
+#endif
+        } s;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t bufs:8;
+                uint64_t ip_offset:8;
+                uint64_t vlan_valid:1;
+                uint64_t vlan_stacked:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_cfi:1;
+                uint64_t vlan_id:12;
+                uint64_t port:12;               /* MAC/PIP port number. */
+                uint64_t dec_ipcomp:1;
+                uint64_t tcp_or_udp:1;
+                uint64_t dec_ipsec:1;
+                uint64_t is_v6:1;
+                uint64_t software:1;
+                uint64_t L4_error:1;
+                uint64_t is_frag:1;
+                uint64_t IP_exc:1;
+                uint64_t is_bcast:1;
+                uint64_t is_mcast:1;
+                uint64_t not_IP:1;
+                uint64_t rcv_error:1;
+                uint64_t err_code:8;
+#else
+                uint64_t err_code:8;
+                uint64_t rcv_error:1;
+                uint64_t not_IP:1;
+                uint64_t is_mcast:1;
+                uint64_t is_bcast:1;
+                uint64_t IP_exc:1;
+                uint64_t is_frag:1;
+                uint64_t L4_error:1;
+                uint64_t software:1;
+                uint64_t is_v6:1;
+                uint64_t dec_ipsec:1;
+                uint64_t tcp_or_udp:1;
+                uint64_t dec_ipcomp:1;
+                uint64_t port:12;
+                uint64_t vlan_id:12;
+                uint64_t vlan_cfi:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_stacked:1;
+                uint64_t vlan_valid:1;
+                uint64_t ip_offset:8;
+                uint64_t bufs:8;
+#endif
+        } s_cn68xx;
+
+        /* use this to get at the 16 vlan bits */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t unused1:16;
+                uint64_t vlan:16;
+                uint64_t unused2:32;
+#else
+                uint64_t unused2:32;
+                uint64_t vlan:16;
+                uint64_t unused1:16;
+
+#endif
+        } svlan;
+
+        /*
+         * use this struct if the hardware could not determine that
+         * the packet is ip.
+         */
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /*
+                 * HW sets this to the number of buffers used by this
+                 * packet.
+                 */
+                uint64_t bufs:8;
+                uint64_t unused:8;
+                /* set to 1 if we found DSA/VLAN in the L2 */
+                uint64_t vlan_valid:1;
+                /* Set to 1 if the DSA/VLAN tag is stacked */
+                uint64_t vlan_stacked:1;
+                uint64_t unassigned:1;
+                /*
+                 * HW sets to the DSA/VLAN CFI flag (valid when
+                 * vlan_valid)
+                 */
+                uint64_t vlan_cfi:1;
+                /*
+                 * HW sets to the DSA/VLAN_ID field (valid when
+                 * vlan_valid).
+                 */
+                uint64_t vlan_id:12;
+                /*
+                 * Ring Identifier (if PCIe). Requires
+                 * PIP_GBL_CTL[RING_EN]=1
+                 */
+                uint64_t pr:4;
+                uint64_t unassigned2:12;
+                /*
+                 * reserved for software use, hardware will clear on
+                 * packet creation.
+                 */
+                uint64_t software:1;
+                uint64_t unassigned3:1;
+                /*
+                 * set if the hardware determined that the packet is
+                 * rarp.
+                 */
+                uint64_t is_rarp:1;
+                /*
+                 * set if the hardware determined that the packet is
+                 * arp
+                 */
+                uint64_t is_arp:1;
+                /*
+                 * set if the hardware determined that the packet is a
+                 * broadcast.
+                 */
+                uint64_t is_bcast:1;
+                /*
+                 * set if the hardware determined that the packet is a
+                 * multi-cast
+                 */
+                uint64_t is_mcast:1;
+                /*
+                 * set if the packet may not be IP (must be one in
+                 * this case)
+                 */
+                uint64_t not_IP:1;
+                /* The receive interface hardware detected a receive
+                 * error.  Failure indicated in err_code below,
+                 * decode:
+                 *
+                 * - 1 = partial error: a packet was partially
+                 *       received, but internal buffering / bandwidth
+                 *       was not adequate to receive the entire
+                 *       packet.
+                 * - 2 = jabber error: the RGMII packet was too large
+                 *       and is truncated.
+                 * - 3 = overrun error: the RGMII packet is longer
+                 *       than allowed and had an FCS error.
+                 * - 4 = oversize error: the RGMII packet is longer
+                 *       than allowed.
+                 * - 5 = alignment error: the RGMII packet is not an
+                 *       integer number of bytes
+                 *       and had an FCS error (100M and 10M only).
+                 * - 6 = fragment error: the RGMII packet is shorter
+                 *       than allowed and had an FCS error.
+                 * - 7 = GMX FCS error: the RGMII packet had an FCS
+                 *       error.
+                 * - 8 = undersize error: the RGMII packet is shorter
+                 *       than allowed.
+                 * - 9 = extend error: the RGMII packet had an extend
+                 *       error.
+                 * - 10 = length mismatch error: the RGMII packet had
+                 *        a length that did not match the length field
+                 *        in the L2 HDR.
+                 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
+                 *        packet had one or more data reception errors
+                 *        (RXERR) or the SPI4 packet had one or more
+                 *        DIP4 errors.
+                 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
+                 *        packet was not large enough to cover the
+                 *        skipped bytes or the SPI4 packet was
+                 *        terminated with an About EOPS.
+                 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
+                 *        RGMII packet had a studder error (data not
+                 *        repeated - 10/100M only) or the SPI4 packet
+                 *        was sent to an NXA.
+                 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
+                 * - 17 = Skip error: a packet was not large enough to
+                 *        cover the skipped bytes.
+                 * - 18 = L2 header malformed: the packet is not long
+                 *        enough to contain the L2.
+                 */
+
+                uint64_t rcv_error:1;
+                /*
+                 * lower err_code = first-level descriptor of the
+                 * work
+                 */
+                /*
+                 * zero for packet submitted by hardware that isn't on
+                 * the slow path
+                 */
+                /* type is cvmx_pip_err_t (union, so can't use directly */
+                uint64_t err_code:8;
+#else
+                uint64_t err_code:8;
+                uint64_t rcv_error:1;
+                uint64_t not_IP:1;
+                uint64_t is_mcast:1;
+                uint64_t is_bcast:1;
+                uint64_t is_arp:1;
+                uint64_t is_rarp:1;
+                uint64_t unassigned3:1;
+                uint64_t software:1;
+                uint64_t unassigned2:4;
+                uint64_t unassigned2a:8;
+                uint64_t pr:4;
+                uint64_t vlan_id:12;
+                uint64_t vlan_cfi:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_stacked:1;
+                uint64_t vlan_valid:1;
+                uint64_t unused:8;
+                uint64_t bufs:8;
+#endif
+        } snoip;
+
+} cvmx_pip_wqe_word2;
+
+union cvmx_pip_wqe_word0 {
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /**
+                 * raw chksum result generated by the HW
+                 */
+                uint16_t hw_chksum;
+                /**
+                 * Field unused by hardware - available for software
+                 */
+                uint8_t unused;
+                /**
+                 * Next pointer used by hardware for list maintenance.
+                 * May be written/read by HW before the work queue
+                 * entry is scheduled to a PP (Only 36 bits used in
+                 * Octeon 1)
+                 */
+                uint64_t next_ptr:40;
+#else
+                uint64_t next_ptr:40;
+                uint8_t unused;
+                uint16_t hw_chksum;
+#endif
+        } cn38xx;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t l4ptr:8;       /* 56..63 */
+                uint64_t unused0:8;     /* 48..55 */
+                uint64_t l3ptr:8;       /* 40..47 */
+                uint64_t l2ptr:8;       /* 32..39 */
+                uint64_t unused1:18;    /* 14..31 */
+                uint64_t bpid:6;        /* 8..13 */
+                uint64_t unused2:2;     /* 6..7 */
+                uint64_t pknd:6;        /* 0..5 */
+#else
+                uint64_t pknd:6;        /* 0..5 */
+                uint64_t unused2:2;     /* 6..7 */
+                uint64_t bpid:6;        /* 8..13 */
+                uint64_t unused1:18;    /* 14..31 */
+                uint64_t l2ptr:8;       /* 32..39 */
+                uint64_t l3ptr:8;       /* 40..47 */
+                uint64_t unused0:8;     /* 48..55 */
+                uint64_t l4ptr:8;       /* 56..63 */
+#endif
+        } cn68xx;
+};
+
+union cvmx_wqe_word0 {
+        uint64_t u64;
+        union cvmx_pip_wqe_word0 pip;
+};
+
+union cvmx_wqe_word1 {
+        uint64_t u64;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t len:16;
+                uint64_t varies:14;
+                /**
+                 * the type of the tag (ORDERED, ATOMIC, NULL)
+                 */
+                uint64_t tag_type:2;
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t varies:14;
+                uint64_t len:16;
+#endif
+        };
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t len:16;
+                uint64_t zero_0:1;
+                /**
+                 * HW sets this to what it thought the priority of
+                 * the input packet was
+                 */
+                uint64_t qos:3;
+
+                uint64_t zero_1:1;
+                /**
+                 * the group that the work queue entry will be scheduled to
+                 */
+                uint64_t grp:6;
+                uint64_t zero_2:3;
+                uint64_t tag_type:2;
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t zero_2:3;
+                uint64_t grp:6;
+                uint64_t zero_1:1;
+                uint64_t qos:3;
+                uint64_t zero_0:1;
+                uint64_t len:16;
+#endif
+        } cn68xx;
+        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
+                /**
+                 * HW sets to the total number of bytes in the packet
+                 */
+                uint64_t len:16;
+                /**
+                 * HW sets this to input physical port
+                 */
+                uint64_t ipprt:6;
+
+                /**
+                 * HW sets this to what it thought the priority of
+                 * the input packet was
+                 */
+                uint64_t qos:3;
+
+                /**
+                 * the group that the work queue entry will be scheduled to
+                 */
+                uint64_t grp:4;
+                /**
+                 * the type of the tag (ORDERED, ATOMIC, NULL)
+                 */
+                uint64_t tag_type:3;
+                /**
+                 * the synchronization/ordering tag
+                 */
+                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t zero_2:1;
+                uint64_t grp:4;
+                uint64_t qos:3;
+                uint64_t ipprt:6;
+                uint64_t len:16;
+#endif
+        } cn38xx;
+};
+
+/**
+ * Work queue entry format
+ *
+ * must be 8-byte aligned
+ */
+struct cvmx_wqe {
+
+    /*****************************************************************
+     * WORD 0
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+        union cvmx_wqe_word0 word0;
+
+    /*****************************************************************
+     * WORD 1
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+        union cvmx_wqe_word1 word1;
+
+    /**
+     * WORD 2 HW WRITE: the following 64-bits are filled in by
+     *   hardware when a packet arrives This indicates a variety of
+     *   status and error conditions.
+     */
+        cvmx_pip_wqe_word2 word2;
+
+    /**
+     * Pointer to the first segment of the packet.
+     */
+        union cvmx_buf_ptr packet_ptr;
+
+    /**
+     *   HW WRITE: octeon will fill in a programmable amount from the
+     *             packet, up to (at most, but perhaps less) the amount
+     *             needed to fill the work queue entry to 128 bytes
+     *
+     *   If the packet is recognized to be IP, the hardware starts
+     *   (except that the IPv4 header is padded for appropriate
+     *   alignment) writing here where the IP header starts.  If the
+     *   packet is not recognized to be IP, the hardware starts
+     *   writing the beginning of the packet here.
+     */
+        uint8_t packet_data[96];
+
+    /**
+     * If desired, SW can make the work Q entry any length. For the
+     * purposes of discussion here, Assume 128B always, as this is all that
+     * the hardware deals with.
+     *
+     */
+
+} CVMX_CACHE_LINE_ALIGNED;
+
+static inline int cvmx_wqe_get_port(struct cvmx_wqe *work)
+{
+        int port;
+
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                port = work->word2.s_cn68xx.port;
+        else
+                port = work->word1.cn38xx.ipprt;
+
+        return port;
+}
+
+static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
+{
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                work->word2.s_cn68xx.port = port;
+        else
+                work->word1.cn38xx.ipprt = port;
+}
+
+static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
+{
+        int grp;
+
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                grp = work->word1.cn68xx.grp;
+        else
+                grp = work->word1.cn38xx.grp;
+
+        return grp;
+}
+
+static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
+{
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                work->word1.cn68xx.grp = grp;
+        else
+                work->word1.cn38xx.grp = grp;
+}
+
+static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
+{
+        int qos;
+
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                qos = work->word1.cn68xx.qos;
+        else
+                qos = work->word1.cn38xx.qos;
+
+        return qos;
+}
+
+static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
+{
+        if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
+                work->word1.cn68xx.qos = qos;
+        else
+                work->word1.cn38xx.qos = qos;
+}
+
+#endif /* __CVMX_WQE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
new file mode 100644
index 000000000..25854abc9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -0,0 +1,495 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2017 Cavium, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_H__
+#define __CVMX_H__
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+
+enum cvmx_mips_space {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+};
+
+/* These macros for use when using 32 bit pointers. */
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) \
+        ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+
+#include <asm/octeon/cvmx-asm.h>
+#include <asm/octeon/cvmx-packet.h>
+#include <asm/octeon/cvmx-sysinfo.h>
+
+#include <asm/octeon/cvmx-ciu-defs.h>
+#include <asm/octeon/cvmx-ciu3-defs.h>
+#include <asm/octeon/cvmx-gpio-defs.h>
+#include <asm/octeon/cvmx-iob-defs.h>
+#include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-l2c-defs.h>
+#include <asm/octeon/cvmx-l2d-defs.h>
+#include <asm/octeon/cvmx-l2t-defs.h>
+#include <asm/octeon/cvmx-led-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-pow-defs.h>
+
+#include <asm/octeon/cvmx-bootinfo.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-l2c.h>
+
+#ifndef CVMX_ENABLE_DEBUG_PRINTS
+#define CVMX_ENABLE_DEBUG_PRINTS 1
+#endif
+
+#if CVMX_ENABLE_DEBUG_PRINTS
+#define cvmx_dprintf        printk
+#else
+#define cvmx_dprintf(...)   {}
+#endif
+
+#define CVMX_MAX_CORES          (16)
+#define CVMX_CACHE_LINE_SIZE    (128)   /* In bytes */
+#define CVMX_CACHE_LINE_MASK    (CVMX_CACHE_LINE_SIZE - 1)      /* In bytes */
+#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
+#define CAST64(v) ((long long)(long)(v))
+#define CASTPTR(type, v) ((type *)(long)(v))
+
+/*
+ * Returns processor ID, different Linux and simple exec versions
+ * provided in the cvmx-app-init*.c files.
+ */
+static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
+static inline uint32_t cvmx_get_proc_id(void)
+{
+        uint32_t id;
+        asm("mfc0 %0, $15,0" : "=r"(id));
+        return id;
+}
+
+/* turn the variable name into a string */
+#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
+#define CVMX_TMP_STR2(x) #x
+
+/**
+ * Builds a bit mask given the required size in bits.
+ *
+ * @bits:   Number of bits in the mask
+ * Returns The mask
+ */ static inline uint64_t cvmx_build_mask(uint64_t bits)
+{
+        return ~((~0x0ull) << bits);
+}
+
+/**
+ * Builds a memory address for I/O based on the Major and Sub DID.
+ *
+ * @major_did: 5 bit major did
+ * @sub_did:   3 bit sub did
+ * Returns I/O base address
+ */
+static inline uint64_t cvmx_build_io_address(uint64_t major_did,
+                                             uint64_t sub_did)
+{
+        return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
+}
+
+/**
+ * Perform mask and shift to place the supplied value into
+ * the supplied bit rage.
+ *
+ * Example: cvmx_build_bits(39,24,value)
+ * <pre>
+ * 6       5       4       3       3       2       1
+ * 3       5       7       9       1       3       5       7      0
+ * +-------+-------+-------+-------+-------+-------+-------+------+
+ * 000000000000000000000000___________value000000000000000000000000
+ * </pre>
+ *
+ * @high_bit: Highest bit value can occupy (inclusive) 0-63
+ * @low_bit:  Lowest bit value can occupy inclusive 0-high_bit
+ * @value:    Value to use
+ * Returns Value masked and shifted
+ */
+static inline uint64_t cvmx_build_bits(uint64_t high_bit,
+                                       uint64_t low_bit, uint64_t value)
+{
+        return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
+}
+
+/**
+ * Convert a memory pointer (void*) into a hardware compatible
+ * memory address (uint64_t). Octeon hardware widgets don't
+ * understand logical addresses.
+ *
+ * @ptr:    C style memory pointer
+ * Returns Hardware physical address
+ */
+static inline uint64_t cvmx_ptr_to_phys(void *ptr)
+{
+        if (sizeof(void *) == 8) {
+                /*
+                 * We're running in 64 bit mode. Normally this means
+                 * that we can use 40 bits of address space (the
+                 * hardware limit). Unfortunately there is one case
+                 * were we need to limit this to 30 bits, sign
+                 * extended 32 bit. Although these are 64 bits wide,
+                 * only 30 bits can be used.
+                 */
+                if ((CAST64(ptr) >> 62) == 3)
+                        return CAST64(ptr) & cvmx_build_mask(30);
+                else
+                        return CAST64(ptr) & cvmx_build_mask(40);
+        } else {
+                return (long)(ptr) & 0x1fffffff;
+        }
+}
+
+/**
+ * Convert a hardware physical address (uint64_t) into a
+ * memory pointer (void *).
+ *
+ * @physical_address:
+ *               Hardware physical address to memory
+ * Returns Pointer to memory
+ */
+static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
+{
+        if (sizeof(void *) == 8) {
+                /* Just set the top bit, avoiding any TLB ugliness */
+                return CASTPTR(void,
+                               CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                            physical_address));
+        } else {
+                return CASTPTR(void,
+                               CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
+                                              physical_address));
+        }
+}
+
+/* The following #if controls the definition of the macro
+    CVMX_BUILD_WRITE64. This macro is used to build a store operation to
+    a full 64bit address. With a 64bit ABI, this can be done with a simple
+    pointer access. 32bit ABIs require more complicated assembly */
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+    a simple volatile pointer */
+#define CVMX_BUILD_WRITE64(TYPE, ST)                                    \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)     \
+{                                                                       \
+    *CASTPTR(volatile TYPE##_t, addr) = val;                            \
+}
+
+
+/* The following #if controls the definition of the macro
+    CVMX_BUILD_READ64. This macro is used to build a load operation from
+    a full 64bit address. With a 64bit ABI, this can be done with a simple
+    pointer access. 32bit ABIs require more complicated assembly */
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+    a simple volatile pointer */
+#define CVMX_BUILD_READ64(TYPE, LT)                                     \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)                \
+{                                                                       \
+        return *CASTPTR(volatile TYPE##_t, addr);                       \
+}
+
+
+/* The following defines 8 functions for writing to a 64bit address. Each
+    takes two arguments, the address and the value to write.
+    cvmx_write64_int64      cvmx_write64_uint64
+    cvmx_write64_int32      cvmx_write64_uint32
+    cvmx_write64_int16      cvmx_write64_uint16
+    cvmx_write64_int8       cvmx_write64_uint8 */
+CVMX_BUILD_WRITE64(int64, "sd");
+CVMX_BUILD_WRITE64(int32, "sw");
+CVMX_BUILD_WRITE64(int16, "sh");
+CVMX_BUILD_WRITE64(int8, "sb");
+CVMX_BUILD_WRITE64(uint64, "sd");
+CVMX_BUILD_WRITE64(uint32, "sw");
+CVMX_BUILD_WRITE64(uint16, "sh");
+CVMX_BUILD_WRITE64(uint8, "sb");
+#define cvmx_write64 cvmx_write64_uint64
+
+/* The following defines 8 functions for reading from a 64bit address. Each
+    takes the address as the only argument
+    cvmx_read64_int64       cvmx_read64_uint64
+    cvmx_read64_int32       cvmx_read64_uint32
+    cvmx_read64_int16       cvmx_read64_uint16
+    cvmx_read64_int8        cvmx_read64_uint8 */
+CVMX_BUILD_READ64(int64, "ld");
+CVMX_BUILD_READ64(int32, "lw");
+CVMX_BUILD_READ64(int16, "lh");
+CVMX_BUILD_READ64(int8, "lb");
+CVMX_BUILD_READ64(uint64, "ld");
+CVMX_BUILD_READ64(uint32, "lw");
+CVMX_BUILD_READ64(uint16, "lhu");
+CVMX_BUILD_READ64(uint8, "lbu");
+#define cvmx_read64 cvmx_read64_uint64
+
+
+static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
+{
+        cvmx_write64(csr_addr, val);
+
+        /*
+         * Perform an immediate read after every write to an RSL
+         * register to force the write to complete. It doesn't matter
+         * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
+         * because it is fast and harmless.
+         */
+        if (((csr_addr >> 40) & 0x7ffff) == (0x118))
+                cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
+}
+
+static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
+{
+        cvmx_write_csr((__force uint64_t)csr_addr, val);
+}
+
+static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
+{
+        cvmx_write64(io_addr, val);
+
+}
+
+static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
+{
+        uint64_t val = cvmx_read64(csr_addr);
+        return val;
+}
+
+static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
+{
+        return cvmx_read_csr((__force uint64_t) csr_addr);
+}
+
+static inline void cvmx_send_single(uint64_t data)
+{
+        const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
+        cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
+}
+
+static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
+{
+        union {
+                uint64_t u64;
+                struct {
+                        uint64_t scraddr:8;
+                        uint64_t len:8;
+                        uint64_t addr:48;
+                } s;
+        } addr;
+        addr.u64 = csr_addr;
+        addr.s.scraddr = scraddr >> 3;
+        addr.s.len = 1;
+        cvmx_send_single(addr.u64);
+}
+
+/* Return true if Octeon is CN38XX pass 1 */
+static inline int cvmx_octeon_is_pass1(void)
+{
+#if OCTEON_IS_COMMON_BINARY()
+        return 0;       /* Pass 1 isn't supported for common binaries */
+#else
+/* Now that we know we're built for a specific model, only check CN38XX */
+#if OCTEON_IS_MODEL(OCTEON_CN38XX)
+        return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
+#else
+        return 0;       /* Built for non CN38XX chip, we're not CN38XX pass1 */
+#endif
+#endif
+}
+
+static inline unsigned int cvmx_get_core_num(void)
+{
+        unsigned int core_num;
+        CVMX_RDHWRNV(core_num, 0);
+        return core_num;
+}
+
+/* Maximum # of bits to define core in node */
+#define CVMX_NODE_NO_SHIFT      7
+#define CVMX_NODE_MASK          0x3
+static inline unsigned int cvmx_get_node_num(void)
+{
+        unsigned int core_num = cvmx_get_core_num();
+
+        return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
+}
+
+static inline unsigned int cvmx_get_local_core_num(void)
+{
+        return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
+}
+
+#define CVMX_NODE_BITS         (2)     /* Number of bits to define a node */
+#define CVMX_MAX_NODES         (1 << CVMX_NODE_BITS)
+#define CVMX_NODE_IO_SHIFT     (36)
+#define CVMX_NODE_MEM_SHIFT    (40)
+#define CVMX_NODE_IO_MASK      ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
+
+static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
+                                       uint64_t val)
+{
+        uint64_t composite_csr_addr, node_addr;
+
+        node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
+        composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
+
+        cvmx_write64_uint64(composite_csr_addr, val);
+        if (((csr_addr >> 40) & 0x7ffff) == (0x118))
+                cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
+}
+
+static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
+{
+        uint64_t node_addr;
+
+        node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
+                    (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
+        return cvmx_read_csr(node_addr);
+}
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for POP instruction.
+ *
+ * @val:    32 bit value to count set bits in
+ *
+ * Returns Number of bits set
+ */
+static inline uint32_t cvmx_pop(uint32_t val)
+{
+        uint32_t pop;
+        CVMX_POP(pop, val);
+        return pop;
+}
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for DPOP instruction.
+ *
+ * @val:    64 bit value to count set bits in
+ *
+ * Returns Number of bits set
+ */
+static inline int cvmx_dpop(uint64_t val)
+{
+        int pop;
+        CVMX_DPOP(pop, val);
+        return pop;
+}
+
+/**
+ * Provide current cycle counter as a return value
+ *
+ * Returns current cycle counter
+ */
+
+static inline uint64_t cvmx_get_cycle(void)
+{
+        uint64_t cycle;
+        CVMX_RDHWR(cycle, 31);
+        return cycle;
+}
+
+/**
+ * Reads a chip global cycle counter.  This counts CPU cycles since
+ * chip reset.  The counter is 64 bit.
+ * This register does not exist on CN38XX pass 1 silicion
+ *
+ * Returns Global chip cycle count since chip reset.
+ */
+static inline uint64_t cvmx_get_cycle_global(void)
+{
+        if (cvmx_octeon_is_pass1())
+                return 0;
+        else
+                return cvmx_read64(CVMX_IPD_CLK_COUNT);
+}
+
+/**
+ * This macro spins on a field waiting for it to reach a value. It
+ * is common in code to need to wait for a specific field in a CSR
+ * to match a specific value. Conceptually this macro expands to:
+ *
+ * 1) read csr at "address" with a csr typedef of "type"
+ * 2) Check if ("type".s."field" "op" "value")
+ * 3) If #2 isn't true loop to #1 unless too much time has passed.
+ */
+#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
+    (                                                                   \
+{                                                                       \
+        int result;                                                     \
+        do {                                                            \
+                uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
+                        cvmx_sysinfo_get()->cpu_clock_hz / 1000000;     \
+                type c;                                                 \
+                while (1) {                                             \
+                        c.u64 = cvmx_read_csr(address);                 \
+                        if ((c.s.field) op(value)) {                    \
+                                result = 0;                             \
+                                break;                                  \
+                        } else if (cvmx_get_cycle() > done) {           \
+                                result = -1;                            \
+                                break;                                  \
+                        } else                                          \
+                                __delay(100);                           \
+                }                                                       \
+        } while (0);                                                    \
+        result;                                                         \
+})
+
+/***************************************************************************/
+
+/* Return the number of cores available in the chip */
+static inline uint32_t cvmx_octeon_num_cores(void)
+{
+        u64 ciu_fuse_reg;
+        u64 ciu_fuse;
+
+        if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
+                ciu_fuse_reg = CVMX_CIU3_FUSE;
+        else
+                ciu_fuse_reg = CVMX_CIU_FUSE;
+        ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
+        return cvmx_dpop(ciu_fuse);
+}
+
+#endif /*  __CVMX_H__  */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
new file mode 100644
index 000000000..a19ca3b27
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -0,0 +1,213 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * File defining checks for different Octeon features.
+ */
+
+#ifndef __OCTEON_FEATURE_H__
+#define __OCTEON_FEATURE_H__
+#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
+
+enum octeon_feature {
+        /* CN68XX uses port kinds for packet interface */
+        OCTEON_FEATURE_PKND,
+        /* CN68XX has different fields in word0 - word2 */
+        OCTEON_FEATURE_CN68XX_WQE,
+        /*
+         * Octeon models in the CN5XXX family and higher support
+         * atomic add instructions to memory (saa/saad).
+         */
+        OCTEON_FEATURE_SAAD,
+        /* Does this Octeon support the ZIP offload engine? */
+        OCTEON_FEATURE_ZIP,
+        OCTEON_FEATURE_DORM_CRYPTO,
+        /* Does this Octeon support PCI express? */
+        OCTEON_FEATURE_PCIE,
+        /* Does this Octeon support SRIOs */
+        OCTEON_FEATURE_SRIO,
+        /*  Does this Octeon support Interlaken */
+        OCTEON_FEATURE_ILK,
+        /* Some Octeon models support internal memory for storing
+         * cryptographic keys */
+        OCTEON_FEATURE_KEY_MEMORY,
+        /* Octeon has a LED controller for banks of external LEDs */
+        OCTEON_FEATURE_LED_CONTROLLER,
+        /* Octeon has a trace buffer */
+        OCTEON_FEATURE_TRA,
+        /* Octeon has a management port */
+        OCTEON_FEATURE_MGMT_PORT,
+        /* Octeon has a raid unit */
+        OCTEON_FEATURE_RAID,
+        /* Octeon has a builtin USB */
+        OCTEON_FEATURE_USB,
+        /* Octeon IPD can run without using work queue entries */
+        OCTEON_FEATURE_NO_WPTR,
+        /* Octeon has DFA state machines */
+        OCTEON_FEATURE_DFA,
+        /* Octeon MDIO block supports clause 45 transactions for 10
+         * Gig support */
+        OCTEON_FEATURE_MDIO_CLAUSE_45,
+        /*
+         *  CN52XX and CN56XX used a block named NPEI for PCIe
+         *  access. Newer chips replaced this with SLI+DPI.
+         */
+        OCTEON_FEATURE_NPEI,
+        OCTEON_FEATURE_HFA,
+        OCTEON_FEATURE_DFM,
+        OCTEON_FEATURE_CIU2,
+        OCTEON_FEATURE_CIU3,
+        /* Octeon has FPA first seen on 78XX */
+        OCTEON_FEATURE_FPA3,
+        OCTEON_FEATURE_FAU,
+        OCTEON_MAX_FEATURE
+};
+
+enum octeon_feature_bits {
+        OCTEON_HAS_CRYPTO = 0x0001,     /* Crypto acceleration using COP2 */
+};
+extern enum octeon_feature_bits __octeon_feature_bits;
+
+/**
+ * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
+ *
+ * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
+ */
+static inline int octeon_has_crypto(void)
+{
+        return __octeon_feature_bits & OCTEON_HAS_CRYPTO;
+}
+
+/**
+ * Determine if the current Octeon supports a specific feature. These
+ * checks have been optimized to be fairly quick, but they should still
+ * be kept out of fast path code.
+ *
+ * @feature: Feature to check for. This should always be a constant so the
+ *                compiler can remove the switch statement through optimization.
+ *
+ * Returns Non zero if the feature exists. Zero if the feature does not
+ *         exist.
+ */
+static inline bool octeon_has_feature(enum octeon_feature feature)
+{
+        switch (feature) {
+        case OCTEON_FEATURE_SAAD:
+                return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
+
+        case OCTEON_FEATURE_DORM_CRYPTO:
+                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                        union cvmx_mio_fus_dat2 fus_2;
+                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                        return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
+                } else {
+                        return false;
+                }
+
+        case OCTEON_FEATURE_PCIE:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+                        || OCTEON_IS_MODEL(OCTEON_CN7XXX);
+
+        case OCTEON_FEATURE_SRIO:
+                return OCTEON_IS_MODEL(OCTEON_CN63XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN66XX);
+
+        case OCTEON_FEATURE_ILK:
+                return (OCTEON_IS_MODEL(OCTEON_CN68XX));
+
+        case OCTEON_FEATURE_KEY_MEMORY:
+                return OCTEON_IS_MODEL(OCTEON_CN38XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_LED_CONTROLLER:
+                return OCTEON_IS_MODEL(OCTEON_CN38XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN56XX);
+
+        case OCTEON_FEATURE_TRA:
+                return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN50XX));
+        case OCTEON_FEATURE_MGMT_PORT:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_RAID:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_USB:
+                return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN58XX));
+
+        case OCTEON_FEATURE_NO_WPTR:
+                return (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                          && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                          && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+
+        case OCTEON_FEATURE_MDIO_CLAUSE_45:
+                return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
+                         || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN50XX));
+
+        case OCTEON_FEATURE_NPEI:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+        case OCTEON_FEATURE_PKND:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CN68XX_WQE:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CIU2:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+        case OCTEON_FEATURE_CIU3:
+        case OCTEON_FEATURE_FPA3:
+                return OCTEON_IS_MODEL(OCTEON_CN78XX)
+                        || OCTEON_IS_MODEL(OCTEON_CNF75XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN73XX);
+        case OCTEON_FEATURE_FAU:
+                return !(OCTEON_IS_MODEL(OCTEON_CN78XX)
+                         || OCTEON_IS_MODEL(OCTEON_CNF75XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN73XX));
+
+        default:
+                break;
+        }
+        return false;
+}
+
+#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
new file mode 100644
index 000000000..6c68517c2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -0,0 +1,409 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2010 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+#ifndef __OCTEON_MODEL_H__
+#define __OCTEON_MODEL_H__
+
+/*
+ * The defines below should be used with the OCTEON_IS_MODEL() macro
+ * to determine what model of chip the software is running on.  Models
+ * ending in 'XX' match multiple models (families), while specific
+ * models match only that model.  If a pass (revision) is specified,
+ * then only that revision will be matched.  Care should be taken when
+ * checking for both specific models and families that the specific
+ * models are checked for first.  While these defines are similar to
+ * the processor ID, they are not intended to be used by anything
+ * other that the OCTEON_IS_MODEL framework, and the values are
+ * subject to change at anytime without notice.
+ *
+ * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
+ * macros should be used outside of this file.  All other macros are
+ * for internal use only, and may change without notice.
+ */
+
+#define OCTEON_FAMILY_MASK      0x00ffff00
+#define OCTEON_PRID_MASK        0x00ffffff
+
+/* Flag bits in top byte */
+/* Ignores revision in model checks */
+#define OM_IGNORE_REVISION        0x01000000
+/* Check submodels */
+#define OM_CHECK_SUBMODEL         0x02000000
+/* Match all models previous than the one specified */
+#define OM_MATCH_PREVIOUS_MODELS  0x04000000
+/* Ignores the minor revison on newer parts */
+#define OM_IGNORE_MINOR_REVISION  0x08000000
+#define OM_FLAG_MASK              0xff000000
+
+/* Match all cn5XXX Octeon models. */
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000
+/* Match all cn6XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000
+/* Match all cnf7XXX Octeon models. */
+#define OM_MATCH_F7XXX_FAMILY_MODELS    0x80000000
+/* Match all cn7XXX Octeon models. */
+#define OM_MATCH_7XXX_FAMILY_MODELS     0x10000000
+#define OM_MATCH_FAMILY_MODELS          (OM_MATCH_5XXX_FAMILY_MODELS |  \
+                                         OM_MATCH_6XXX_FAMILY_MODELS |  \
+                                         OM_MATCH_F7XXX_FAMILY_MODELS | \
+                                         OM_MATCH_7XXX_FAMILY_MODELS)
+/*
+ * CN7XXX models with new revision encoding
+ */
+
+#define OCTEON_CNF75XX_PASS1_0  0x000d9800
+#define OCTEON_CNF75XX          (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CNF75XX_PASS1_X  (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN73XX_PASS1_0   0x000d9700
+#define OCTEON_CN73XX_PASS1_1   0x000d9701
+#define OCTEON_CN73XX           (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN73XX_PASS1_X   (OCTEON_CN73XX_PASS1_0 | \
+                                 OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN70XX_PASS1_0   0x000d9600
+#define OCTEON_CN70XX_PASS1_1   0x000d9601
+#define OCTEON_CN70XX_PASS1_2   0x000d9602
+
+#define OCTEON_CN70XX_PASS2_0   0x000d9608
+
+#define OCTEON_CN70XX           (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN70XX_PASS1_X   (OCTEON_CN70XX_PASS1_0 | \
+                                 OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN70XX_PASS2_X   (OCTEON_CN70XX_PASS2_0 | \
+                                 OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN71XX           OCTEON_CN70XX
+
+#define OCTEON_CN78XX_PASS1_0   0x000d9500
+#define OCTEON_CN78XX_PASS1_1   0x000d9501
+#define OCTEON_CN78XX_PASS2_0   0x000d9508
+
+#define OCTEON_CN78XX           (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN78XX_PASS1_X   (OCTEON_CN78XX_PASS1_0 | \
+                                 OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN78XX_PASS2_X   (OCTEON_CN78XX_PASS2_0 | \
+                                 OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN76XX           (0x000d9540 | OM_CHECK_SUBMODEL)
+
+/*
+ * CNF7XXX models with new revision encoding
+ */
+#define OCTEON_CNF71XX_PASS1_0  0x000d9400
+#define OCTEON_CNF71XX_PASS1_1  0x000d9401
+
+#define OCTEON_CNF71XX          (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CNF71XX_PASS1_X  (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN68XX_PASS1_0   0x000d9100
+#define OCTEON_CN68XX_PASS1_1   0x000d9101
+#define OCTEON_CN68XX_PASS1_2   0x000d9102
+#define OCTEON_CN68XX_PASS2_0   0x000d9108
+#define OCTEON_CN68XX_PASS2_1   0x000d9109
+#define OCTEON_CN68XX_PASS2_2   0x000d910a
+
+#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN68XX_PASS1     OCTEON_CN68XX_PASS1_X
+#define OCTEON_CN68XX_PASS2     OCTEON_CN68XX_PASS2_X
+
+#define OCTEON_CN66XX_PASS1_0   0x000d9200
+#define OCTEON_CN66XX_PASS1_2   0x000d9202
+
+#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN63XX_PASS1_0   0x000d9000
+#define OCTEON_CN63XX_PASS1_1   0x000d9001
+#define OCTEON_CN63XX_PASS1_2   0x000d9002
+#define OCTEON_CN63XX_PASS2_0   0x000d9008
+#define OCTEON_CN63XX_PASS2_1   0x000d9009
+#define OCTEON_CN63XX_PASS2_2   0x000d900a
+
+#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
+/* CN62XX is same as CN63XX with 1 MB cache */
+#define OCTEON_CN62XX           OCTEON_CN63XX
+
+#define OCTEON_CN61XX_PASS1_0   0x000d9300
+#define OCTEON_CN61XX_PASS1_1   0x000d9301
+
+#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
+/* CN60XX is same as CN61XX with 512 KB cache */
+#define OCTEON_CN60XX           OCTEON_CN61XX
+
+/*
+ * CN5XXX models with new revision encoding
+ */
+#define OCTEON_CN58XX_PASS1_0   0x000d0300
+#define OCTEON_CN58XX_PASS1_1   0x000d0301
+#define OCTEON_CN58XX_PASS1_2   0x000d0303
+#define OCTEON_CN58XX_PASS2_0   0x000d0308
+#define OCTEON_CN58XX_PASS2_1   0x000d0309
+#define OCTEON_CN58XX_PASS2_2   0x000d030a
+#define OCTEON_CN58XX_PASS2_3   0x000d030b
+
+#define OCTEON_CN58XX           (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
+#define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
+
+#define OCTEON_CN56XX_PASS1_0   0x000d0400
+#define OCTEON_CN56XX_PASS1_1   0x000d0401
+#define OCTEON_CN56XX_PASS2_0   0x000d0408
+#define OCTEON_CN56XX_PASS2_1   0x000d0409
+
+#define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
+#define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
+
+#define OCTEON_CN57XX           OCTEON_CN56XX
+#define OCTEON_CN57XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN57XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN55XX           OCTEON_CN56XX
+#define OCTEON_CN55XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN55XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN54XX           OCTEON_CN56XX
+#define OCTEON_CN54XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN54XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN50XX_PASS1_0   0x000d0600
+
+#define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
+
+/*
+ * NOTE: Octeon CN5000F model is not identifiable using the
+ * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
+ */
+
+#define OCTEON_CN52XX_PASS1_0   0x000d0700
+#define OCTEON_CN52XX_PASS2_0   0x000d0708
+
+#define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
+#define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
+
+/*
+ * CN3XXX models with old revision enconding
+ */
+#define OCTEON_CN38XX_PASS1     0x000d0000
+#define OCTEON_CN38XX_PASS2     0x000d0001
+#define OCTEON_CN38XX_PASS3     0x000d0003
+#define OCTEON_CN38XX           (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN36XX           OCTEON_CN38XX
+#define OCTEON_CN36XX_PASS2     OCTEON_CN38XX_PASS2
+#define OCTEON_CN36XX_PASS3     OCTEON_CN38XX_PASS3
+
+/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
+#define OCTEON_CN31XX_PASS1     0x000d0100
+#define OCTEON_CN31XX_PASS1_1   0x000d0102
+#define OCTEON_CN31XX           (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
+
+/*
+ * This model is only used for internal checks, it is not a valid
+ * model for the OCTEON_MODEL environment variable.  This matches the
+ * CN3010 and CN3005 but NOT the CN3020.
+ */
+#define OCTEON_CN30XX_PASS1     0x000d0200
+#define OCTEON_CN30XX_PASS1_1   0x000d0202
+#define OCTEON_CN30XX           (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+#define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+#define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+/*
+ * This matches the complete family of CN3xxx CPUs, and not subsequent
+ * models
+ */
+#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
+#define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+#define OCTEON_CNF7XXX          (OCTEON_CNF71XX_PASS1_0 | \
+                                 OM_MATCH_F7XXX_FAMILY_MODELS)
+#define OCTEON_CN7XXX           (OCTEON_CN78XX_PASS1_0 | \
+                                 OM_MATCH_7XXX_FAMILY_MODELS)
+
+/* The revision byte (low byte) has two different encodings.
+ * CN3XXX:
+ *
+ *     bits
+ *     <7:5>: reserved (0)
+ *     <4>:   alternate package
+ *     <3:0>: revision
+ *
+ * CN5XXX and older models:
+ *
+ *     bits
+ *     <7>:   reserved (0)
+ *     <6>:   alternate package
+ *     <5:3>: major revision
+ *     <2:0>: minor revision
+ *
+ */
+
+/* Masks used for the various types of model/family/revision matching */
+#define OCTEON_38XX_FAMILY_MASK      0x00ffff00
+#define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
+#define OCTEON_38XX_MODEL_MASK       0x00ffff10
+#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
+
+/* CN5XXX and later use different layout of bits in the revision ID field */
+#define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
+#define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
+#define OCTEON_58XX_MODEL_MASK       0x00ffff40
+#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
+#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00ffff38)
+#define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
+
+static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
+static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
+
+#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
+
+/*
+ * __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)
+ * returns true if chip_model is identical or belong to the OCTEON
+ * model group specified in arg_model.
+ */
+/* NOTE: This for internal use only! */
+#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)              \
+((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
+                )) ||                                                   \
+        (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
+                        && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
+                        && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
+                        && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
+                        && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
+                        && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
+                        && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
+                        && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
+                )))
+
+/* NOTE: This for internal use only!!!!! */
+static inline int __octeon_is_model_runtime__(uint32_t model)
+{
+        uint32_t cpuid = cvmx_get_proc_id();
+
+        return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
+}
+
+/*
+ * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
+ * in a program.
+ * This should be kept runtime if at all possible  and must be conditionalized
+ * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
+ *
+ * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
+ * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
+ * I.e.:
+ *  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
+ */
+#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
+#define OCTEON_IS_COMMON_BINARY() 1
+#undef OCTEON_MODEL
+
+#define OCTEON_IS_OCTEON1()     OCTEON_IS_MODEL(OCTEON_CN3XXX)
+#define OCTEON_IS_OCTEONPLUS()  OCTEON_IS_MODEL(OCTEON_CN5XXX)
+#define OCTEON_IS_OCTEON2()                                             \
+        (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+
+#define OCTEON_IS_OCTEON3()     OCTEON_IS_MODEL(OCTEON_CN7XXX)
+
+#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
+
+const char *__init octeon_model_get_string(uint32_t chip_id);
+
+/*
+ * Return the octeon family, i.e., ProcessorID of the PrID register.
+ *
+ * @return the octeon family on success, ((unint32_t)-1) on error.
+ */
+static inline uint32_t cvmx_get_octeon_family(void)
+{
+        return cvmx_get_proc_id() & OCTEON_FAMILY_MASK;
+}
+
+#include <asm/octeon/octeon-feature.h>
+
+#endif /* __OCTEON_MODEL_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
new file mode 100644
index 000000000..08d48f37c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -0,0 +1,366 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#ifndef __ASM_OCTEON_OCTEON_H
+#define __ASM_OCTEON_OCTEON_H
+
+#include <asm/octeon/cvmx.h>
+#include <asm/bitfield.h>
+
+extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
+                                                uint64_t alignment,
+                                                uint64_t min_addr,
+                                                uint64_t max_addr,
+                                                int do_locking);
+extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
+                                  int do_locking);
+extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
+                                        uint64_t min_addr, uint64_t max_addr,
+                                        int do_locking);
+extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+                                        char *name);
+extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                              uint64_t max_addr, uint64_t align,
+                                              char *name);
+extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+                                                char *name);
+extern int octeon_bootmem_free_named(char *name);
+extern void octeon_bootmem_lock(void);
+extern void octeon_bootmem_unlock(void);
+
+extern int octeon_is_simulation(void);
+extern int octeon_is_pci_host(void);
+extern int octeon_usb_is_ref_clk(void);
+extern uint64_t octeon_get_clock_rate(void);
+extern u64 octeon_get_io_clock_rate(void);
+extern const char *octeon_board_type_string(void);
+extern const char *octeon_get_pci_interrupts(void);
+extern int octeon_get_southbridge_interrupt(void);
+extern int octeon_get_boot_coremask(void);
+extern int octeon_get_boot_num_arguments(void);
+extern const char *octeon_get_boot_argument(int arg);
+extern void octeon_hal_setup_reserved32(void);
+extern void octeon_user_io_init(void);
+
+extern void octeon_init_cvmcount(void);
+extern void octeon_setup_delays(void);
+extern void octeon_io_clk_delay(unsigned long);
+
+#define OCTEON_ARGV_MAX_ARGS    64
+#define OCTEON_SERIAL_LEN       20
+
+struct octeon_boot_descriptor {
+#ifdef __BIG_ENDIAN_BITFIELD
+        /* Start of block referenced by assembly code - do not change! */
+        uint32_t desc_version;
+        uint32_t desc_size;
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        /* Only used by bootloader */
+        uint64_t entry_point;
+        uint64_t desc_vaddr;
+        /* End of This block referenced by assembly code - do not change! */
+        uint32_t exception_base_addr;
+        uint32_t stack_size;
+        uint32_t heap_size;
+        /* Argc count for application. */
+        uint32_t argc;
+        uint32_t argv[OCTEON_ARGV_MAX_ARGS];
+
+#define  BOOT_FLAG_INIT_CORE            (1 << 0)
+#define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
+#define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
+        /* If set, use uart1 for console */
+#define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
+        /* If set, use PCI console */
+#define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
+        /* Call exit on break on serial port */
+#define  OCTEON_BL_FLAG_BREAK           (1 << 5)
+
+        uint32_t flags;
+        uint32_t core_mask;
+        /* DRAM size in megabyes. */
+        uint32_t dram_size;
+        /* physical address of free memory descriptor block. */
+        uint32_t phy_mem_desc_addr;
+        /* used to pass flags from app to debugger. */
+        uint32_t debugger_flags_base_addr;
+        /* CPU clock speed, in hz. */
+        uint32_t eclock_hz;
+        /* DRAM clock speed, in hz. */
+        uint32_t dclock_hz;
+        /* SPI4 clock in hz. */
+        uint32_t spi_clock_hz;
+        uint16_t board_type;
+        uint8_t board_rev_major;
+        uint8_t board_rev_minor;
+        uint16_t chip_type;
+        uint8_t chip_rev_major;
+        uint8_t chip_rev_minor;
+        char board_serial_number[OCTEON_SERIAL_LEN];
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+        uint64_t cvmx_desc_vaddr;
+#else
+        uint32_t desc_size;
+        uint32_t desc_version;
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        /* Only used by bootloader */
+        uint64_t entry_point;
+        uint64_t desc_vaddr;
+        /* End of This block referenced by assembly code - do not change! */
+        uint32_t stack_size;
+        uint32_t exception_base_addr;
+        uint32_t argc;
+        uint32_t heap_size;
+        /*
+         * Argc count for application.
+         * Warning low bit scrambled in little-endian.
+         */
+        uint32_t argv[OCTEON_ARGV_MAX_ARGS];
+
+#define  BOOT_FLAG_INIT_CORE            (1 << 0)
+#define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
+#define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
+        /* If set, use uart1 for console */
+#define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
+        /* If set, use PCI console */
+#define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
+        /* Call exit on break on serial port */
+#define  OCTEON_BL_FLAG_BREAK           (1 << 5)
+
+        uint32_t core_mask;
+        uint32_t flags;
+        /* physical address of free memory descriptor block. */
+        uint32_t phy_mem_desc_addr;
+        /* DRAM size in megabyes. */
+        uint32_t dram_size;
+        /* CPU clock speed, in hz. */
+        uint32_t eclock_hz;
+        /* used to pass flags from app to debugger. */
+        uint32_t debugger_flags_base_addr;
+        /* SPI4 clock in hz. */
+        uint32_t spi_clock_hz;
+        /* DRAM clock speed, in hz. */
+        uint32_t dclock_hz;
+        uint8_t chip_rev_minor;
+        uint8_t chip_rev_major;
+        uint16_t chip_type;
+        uint8_t board_rev_minor;
+        uint8_t board_rev_major;
+        uint16_t board_type;
+
+        uint64_t unused1[4]; /* Not even filled in by bootloader. */
+
+        uint64_t cvmx_desc_vaddr;
+#endif
+};
+
+union octeon_cvmemctl {
+        uint64_t u64;
+        struct {
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t tlbbist:1,
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t l1cbist:1,
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t l1dbist:1,
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t dcmbist:1,
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t ptgbist:1,
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                __BITFIELD_FIELD(uint64_t wbfbist:1,
+                /* Reserved */
+                __BITFIELD_FIELD(uint64_t reserved:17,
+                /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
+                 * This field selects between the TLB replacement policies:
+                 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
+                 * recently used TLB entries and avoids them as new entries
+                 * are allocated. NLU simply guarantees that the next
+                 * allocation is not the last used TLB entry. */
+                __BITFIELD_FIELD(uint64_t tlbnlu:1,
+                /* OCTEON II - Selects the bit in the counter used for
+                 * releasing a PAUSE. This counter trips every 2(8+PAUSETIME)
+                 * cycles. If not already released, the cnMIPS II core will
+                 * always release a given PAUSE instruction within
+                 * 2(8+PAUSETIME). If the counter trip happens to line up,
+                 * the cnMIPS II core may release the PAUSE instantly. */
+                __BITFIELD_FIELD(uint64_t pausetime:3,
+                /* OCTEON II - This field is an extension of
+                 * CvmMemCtl[DIDTTO] */
+                __BITFIELD_FIELD(uint64_t didtto2:1,
+                /* R/W If set, marked write-buffer entries time out
+                 * the same as other entries; if clear, marked
+                 * write-buffer entries use the maximum timeout. */
+                __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
+                /* R/W If set, a merged store does not clear the
+                 * write-buffer entry timeout state. */
+                __BITFIELD_FIELD(uint64_t dismrgclrwbto:1,
+                /* R/W Two bits that are the MSBs of the resultant
+                 * CVMSEG LM word location for an IOBDMA. The other 8
+                 * bits come from the SCRADDR field of the IOBDMA. */
+                __BITFIELD_FIELD(uint64_t iobdmascrmsb:2,
+                /* R/W If set, SYNCWS and SYNCS only order marked
+                 * stores; if clear, SYNCWS and SYNCS only order
+                 * unmarked stores. SYNCWSMARKED has no effect when
+                 * DISSYNCWS is set. */
+                __BITFIELD_FIELD(uint64_t syncwsmarked:1,
+                /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
+                 * SYNC. */
+                __BITFIELD_FIELD(uint64_t dissyncws:1,
+                /* R/W If set, no stall happens on write buffer
+                 * full. */
+                __BITFIELD_FIELD(uint64_t diswbfst:1,
+                /* R/W If set (and SX set), supervisor-level
+                 * loads/stores can use XKPHYS addresses with
+                 * VA<48>==0 */
+                __BITFIELD_FIELD(uint64_t xkmemenas:1,
+                /* R/W If set (and UX set), user-level loads/stores
+                 * can use XKPHYS addresses with VA<48>==0 */
+                __BITFIELD_FIELD(uint64_t xkmemenau:1,
+                /* R/W If set (and SX set), supervisor-level
+                 * loads/stores can use XKPHYS addresses with
+                 * VA<48>==1 */
+                __BITFIELD_FIELD(uint64_t xkioenas:1,
+                /* R/W If set (and UX set), user-level loads/stores
+                 * can use XKPHYS addresses with VA<48>==1 */
+                __BITFIELD_FIELD(uint64_t xkioenau:1,
+                /* R/W If set, all stores act as SYNCW (NOMERGE must
+                 * be set when this is set) RW, reset to 0. */
+                __BITFIELD_FIELD(uint64_t allsyncw:1,
+                /* R/W If set, no stores merge, and all stores reach
+                 * the coherent bus in order. */
+                __BITFIELD_FIELD(uint64_t nomerge:1,
+                /* R/W Selects the bit in the counter used for DID
+                 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
+                 * 214. Actual time-out is between 1x and 2x this
+                 * interval. For example, with DIDTTO=3, expiration
+                 * interval is between 16K and 32K. */
+                __BITFIELD_FIELD(uint64_t didtto:2,
+                /* R/W If set, the (mem) CSR clock never turns off. */
+                __BITFIELD_FIELD(uint64_t csrckalwys:1,
+                /* R/W If set, mclk never turns off. */
+                __BITFIELD_FIELD(uint64_t mclkalwys:1,
+                /* R/W Selects the bit in the counter used for write
+                 * buffer flush time-outs (WBFLT+11) is the bit
+                 * position in an internal counter used to determine
+                 * expiration. The write buffer expires between 1x and
+                 * 2x this interval. For example, with WBFLT = 0, a
+                 * write buffer expires between 2K and 4K cycles after
+                 * the write buffer entry is allocated. */
+                __BITFIELD_FIELD(uint64_t wbfltime:3,
+                /* R/W If set, do not put Istream in the L2 cache. */
+                __BITFIELD_FIELD(uint64_t istrnol2:1,
+                /* R/W The write buffer threshold. */
+                __BITFIELD_FIELD(uint64_t wbthresh:4,
+                /* Reserved */
+                __BITFIELD_FIELD(uint64_t reserved2:2,
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * kernel/debug mode. */
+                __BITFIELD_FIELD(uint64_t cvmsegenak:1,
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * supervisor mode. */
+                __BITFIELD_FIELD(uint64_t cvmsegenas:1,
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * user mode. */
+                __BITFIELD_FIELD(uint64_t cvmsegenau:1,
+                /* R/W Size of local memory in cache blocks, 54 (6912
+                 * bytes) is max legal value. */
+                __BITFIELD_FIELD(uint64_t lmemsz:6,
+                ;)))))))))))))))))))))))))))))))))
+        } s;
+};
+
+extern void octeon_check_cpu_bist(void);
+
+int octeon_prune_device_tree(void);
+extern const char __appended_dtb;
+extern const char __dtb_octeon_3xxx_begin;
+extern const char __dtb_octeon_68xx_begin;
+
+/**
+ * Write a 32bit value to the Octeon NPI register space
+ *
+ * @address: Address to write to
+ * @val:     Value to write
+ */
+static inline void octeon_npi_write32(uint64_t address, uint32_t val)
+{
+        cvmx_write64_uint32(address ^ 4, val);
+        cvmx_read64_uint32(address ^ 4);
+}
+
+#ifdef CONFIG_SMP
+void octeon_setup_smp(void);
+#else
+static inline void octeon_setup_smp(void) {}
+#endif
+
+struct irq_domain;
+struct device_node;
+struct irq_data;
+struct irq_chip;
+void octeon_ciu3_mbox_send(int cpu, unsigned int mbox);
+int octeon_irq_ciu3_xlat(struct irq_domain *d,
+                         struct device_node *node,
+                         const u32 *intspec,
+                         unsigned int intsize,
+                         unsigned long *out_hwirq,
+                         unsigned int *out_type);
+void octeon_irq_ciu3_enable(struct irq_data *data);
+void octeon_irq_ciu3_disable(struct irq_data *data);
+void octeon_irq_ciu3_ack(struct irq_data *data);
+void octeon_irq_ciu3_mask(struct irq_data *data);
+void octeon_irq_ciu3_mask_ack(struct irq_data *data);
+int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
+                         irq_hw_number_t hw, struct irq_chip *chip);
+
+/* Octeon multiplier save/restore routines from octeon_switch.S */
+void octeon_mult_save(void);
+void octeon_mult_restore(void);
+void octeon_mult_save_end(void);
+void octeon_mult_restore_end(void);
+void octeon_mult_save3(void);
+void octeon_mult_save3_end(void);
+void octeon_mult_save2(void);
+void octeon_mult_save2_end(void);
+void octeon_mult_restore3(void);
+void octeon_mult_restore3_end(void);
+void octeon_mult_restore2(void);
+void octeon_mult_restore2_end(void);
+
+/**
+ * Read a 32bit value from the Octeon NPI register space
+ *
+ * @address: Address to read
+ * Returns The result
+ */
+static inline uint32_t octeon_npi_read32(uint64_t address)
+{
+        return cvmx_read64_uint32(address ^ 4);
+}
+
+extern struct cvmx_bootinfo *octeon_bootinfo;
+
+extern uint64_t octeon_bootloader_entry_addr;
+
+extern void (*octeon_irq_setup_secondary)(void);
+
+typedef void (*octeon_irq_ip4_handler_t)(void);
+void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
+
+extern void octeon_fixup_irqs(void);
+
+extern struct semaphore octeon_bootbus_sem;
+
+struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);
+
+#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
new file mode 100644
index 000000000..b12d9a3fb
--- /dev/null
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -0,0 +1,69 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2009 Cavium Networks
+ */
+
+#ifndef __PCI_OCTEON_H__
+#define __PCI_OCTEON_H__
+
+#include <linux/pci.h>
+
+/*
+ * The physical memory base mapped by BAR1.  256MB at the end of the
+ * first 4GB.
+ */
+#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
+#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
+
+/*
+ * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * place BAR1 so it is the same for both.
+ */
+#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+
+/*
+ * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
+ * call the Octeon specific version pointed to by this variable. This
+ * function needs to change for PCI or PCIe based hosts.
+ */
+extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
+                                     u8 slot, u8 pin);
+
+/*
+ * For PCI (not PCIe) the BAR2 base address.
+ */
+#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
+
+/*
+ * For PCI (not PCIe) the base of the memory mapped by BAR1
+ */
+extern u64 octeon_bar1_pci_phys;
+
+/*
+ * The following defines are used when octeon_dma_bar_type =
+ * OCTEON_DMA_BAR_TYPE_BIG
+ */
+#define OCTEON_PCI_BAR1_HOLE_BITS 5
+#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
+
+enum octeon_dma_bar_type {
+        OCTEON_DMA_BAR_TYPE_INVALID,
+        OCTEON_DMA_BAR_TYPE_SMALL,
+        OCTEON_DMA_BAR_TYPE_BIG,
+        OCTEON_DMA_BAR_TYPE_PCIE,
+        OCTEON_DMA_BAR_TYPE_PCIE2
+};
+
+/*
+ * This tells the DMA mapping system in dma-octeon.c how to map PCI
+ * DMA addresses.
+ */
+extern enum octeon_dma_bar_type octeon_dma_bar_type;
+
+void octeon_pci_dma_init(void);
+extern char *octeon_swiotlb;
+
+#endif
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
new file mode 100644
index 000000000..af81ab0da
--- /dev/null
+++ b/arch/mips/include/asm/paccess.h
@@ -0,0 +1,114 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Protected memory access.  Used for everything that might take revenge
+ * by sending a DBE error like accessing possibly non-existent memory or
+ * devices.
+ */
+#ifndef _ASM_PACCESS_H
+#define _ASM_PACCESS_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_32BIT
+#define __PA_ADDR       ".word"
+#endif
+#ifdef CONFIG_64BIT
+#define __PA_ADDR       ".dword"
+#endif
+
+extern asmlinkage void handle_ibe(void);
+extern asmlinkage void handle_dbe(void);
+
+#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr)))
+#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr)))
+
+struct __large_pstruct { unsigned long buf[100]; };
+#define __mp(x) (*(struct __large_pstruct *)(x))
+
+#define __get_dbe(x, ptr, size)                                         \
+({                                                                      \
+        long __gu_err;                                                  \
+        __typeof__(*(ptr)) __gu_val;                                    \
+        unsigned long __gu_addr;                                        \
+        __asm__("":"=r" (__gu_val));                                    \
+        __gu_addr = (unsigned long) (ptr);                              \
+        __asm__("":"=r" (__gu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __get_dbe_asm("lb"); break;                             \
+        case 2: __get_dbe_asm("lh"); break;                             \
+        case 4: __get_dbe_asm("lw"); break;                             \
+        case 8:  __get_dbe_asm("ld"); break;                            \
+        default: __get_dbe_unknown(); break;                            \
+        }                                                               \
+        x = (__typeof__(*(ptr))) __gu_val;                              \
+        __gu_err;                                                       \
+})
+
+#define __get_dbe_asm(insn)                                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".insn\n\t"                                                     \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "move\t%1,$0\n\t"                                               \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        :"=r" (__gu_err), "=r" (__gu_val)                               \
+        :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
+}
+
+extern void __get_dbe_unknown(void);
+
+#define __put_dbe(x, ptr, size)                                         \
+({                                                                      \
+        long __pu_err;                                                  \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        long __pu_addr;                                                 \
+        __pu_val = (x);                                                 \
+        __pu_addr = (long) (ptr);                                       \
+        __asm__("":"=r" (__pu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __put_dbe_asm("sb"); break;                             \
+        case 2: __put_dbe_asm("sh"); break;                             \
+        case 4: __put_dbe_asm("sw"); break;                             \
+        case 8: __put_dbe_asm("sd"); break;                             \
+        default: __put_dbe_unknown(); break;                            \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_dbe_asm(insn)                                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".insn\n\t"                                                     \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        : "=r" (__pu_err)                                               \
+        : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
+}
+
+extern void __put_dbe_unknown(void);
+
+extern unsigned long search_dbe_table(unsigned long addr);
+
+#endif /* _ASM_PACCESS_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
new file mode 100644
index 000000000..6a77bc4a6
--- /dev/null
+++ b/arch/mips/include/asm/page.h
@@ -0,0 +1,261 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PAGE_H
+#define _ASM_PAGE_H
+
+#include <spaces.h>
+#include <linux/const.h>
+#include <linux/kernel.h>
+#include <asm/mipsregs.h>
+
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT      12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT      13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT      14
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define PAGE_SHIFT      15
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT      16
+#endif
+#define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+
+/*
+ * This is used for calculating the real page sizes
+ * for FTLB or VTLB + FTLB configurations.
+ */
+static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
+{
+        switch (mmuextdef) {
+        case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
+                if (PAGE_SIZE == (1 << 30))
+                        return 5;
+                if (PAGE_SIZE == (1llu << 32))
+                        return 6;
+                if (PAGE_SIZE > (256 << 10))
+                        return 7; /* reserved */
+                fallthrough;
+        case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
+                return (PAGE_SHIFT - 10) / 2;
+        default:
+                panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
+                      mmuextdef >> 14);
+        }
+}
+
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+#define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
+#define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
+#define HPAGE_MASK      (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
+#define HPAGE_SHIFT     ({BUILD_BUG(); 0; })
+#define HPAGE_SIZE      ({BUILD_BUG(); 0; })
+#define HPAGE_MASK      ({BUILD_BUG(); 0; })
+#define HUGETLB_PAGE_ORDER      ({BUILD_BUG(); 0; })
+#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#include <linux/pfn.h>
+
+extern void build_clear_page(void);
+extern void build_copy_page(void);
+
+/*
+ * It's normally defined only for FLATMEM config but it's
+ * used in our early mem init code for all memory models.
+ * So always define it.
+ */
+#ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
+extern unsigned long ARCH_PFN_OFFSET;
+# define ARCH_PFN_OFFSET        ARCH_PFN_OFFSET
+#else
+# define ARCH_PFN_OFFSET        PFN_UP(PHYS_OFFSET)
+#endif
+
+extern void clear_page(void * page);
+extern void copy_page(void * to, void * from);
+
+extern unsigned long shm_align_mask;
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+        unsigned long addr2)
+{
+        return (addr1 ^ addr2) & shm_align_mask;
+}
+
+struct page;
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
+        struct page *page)
+{
+        extern void (*flush_data_cache_page)(unsigned long addr);
+
+        clear_page(addr);
+        if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
+                flush_data_cache_page((unsigned long)addr);
+}
+
+struct vm_area_struct;
+extern void copy_user_highpage(struct page *to, struct page *from,
+        unsigned long vaddr, struct vm_area_struct *vma);
+
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+
+/*
+ * These are used to make use of C type-checking..
+ */
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+  #ifdef CONFIG_CPU_MIPS32
+    typedef struct { unsigned long pte_low, pte_high; } pte_t;
+    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+  #else
+     typedef struct { unsigned long long pte; } pte_t;
+     #define pte_val(x) ((x).pte)
+     #define __pte(x)   ((pte_t) { (x) } )
+  #endif
+#else
+typedef struct { unsigned long pte; } pte_t;
+#define pte_val(x)      ((x).pte)
+#define __pte(x)        ((pte_t) { (x) } )
+#endif
+typedef struct page *pgtable_t;
+
+/*
+ * Right now we don't support 4-level pagetables, so all pud-related
+ * definitions come from <asm-generic/pgtable-nopud.h>.
+ */
+
+/*
+ * Finall the top of the hierarchy, the pgd
+ */
+typedef struct { unsigned long pgd; } pgd_t;
+#define pgd_val(x)      ((x).pgd)
+#define __pgd(x)        ((pgd_t) { (x) } )
+
+/*
+ * Manipulate page protection bits
+ */
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pgprot_val(x)   ((x).pgprot)
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+#define pte_pgprot(x)   __pgprot(pte_val(x) & ~_PFN_MASK)
+
+/*
+ * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
+ * pair of pages we only have a single global bit per pair of pages.  When
+ * writing to the TLB make sure we always have the bit set for both pages
+ * or none.  This macro is used to access the `buddy' of the pte we're just
+ * working on.
+ */
+#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+
+/*
+ * __pa()/__va() should be used only during mem init.
+ */
+static inline unsigned long ___pa(unsigned long x)
+{
+        if (IS_ENABLED(CONFIG_64BIT)) {
+                /*
+                 * For MIPS64 the virtual address may either be in one of
+                 * the compatibility segements ckseg0 or ckseg1, or it may
+                 * be in xkphys.
+                 */
+                return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
+        }
+
+        if (!IS_ENABLED(CONFIG_EVA)) {
+                /*
+                 * We're using the standard MIPS32 legacy memory map, ie.
+                 * the address x is going to be in kseg0 or kseg1. We can
+                 * handle either case by masking out the desired bits using
+                 * CPHYSADDR.
+                 */
+                return CPHYSADDR(x);
+        }
+
+        /*
+         * EVA is in use so the memory map could be anything, making it not
+         * safe to just mask out bits.
+         */
+        return x - PAGE_OFFSET + PHYS_OFFSET;
+}
+#define __pa(x)         ___pa((unsigned long)(x))
+#define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+#include <asm/io.h>
+
+/*
+ * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
+ * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org).  The
+ * discussion can be found in lkml posting
+ * <a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is
+ * archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html
+ *
+ * It is unclear if the misscompilations mentioned in
+ * http://lkml.org/lkml/2010/8/8/138 also affect MIPS so we keep this one
+ * until GCC 3.x has been retired before we can apply
+ * https://patchwork.linux-mips.org/patch/1541/
+ */
+
+#ifndef __pa_symbol
+#define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
+#endif
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+
+#ifdef CONFIG_FLATMEM
+
+static inline int pfn_valid(unsigned long pfn)
+{
+        /* avoid <linux/mm.h> include hell */
+        extern unsigned long max_mapnr;
+        unsigned long pfn_offset = ARCH_PFN_OFFSET;
+
+        return pfn >= pfn_offset && pfn < max_mapnr;
+}
+
+#elif defined(CONFIG_SPARSEMEM)
+
+/* pfn_valid is defined in linux/mmzone.h */
+
+#elif defined(CONFIG_NEED_MULTIPLE_NODES)
+
+#define pfn_valid(pfn)                                                  \
+({                                                                      \
+        unsigned long __pfn = (pfn);                                    \
+        int __n = pfn_to_nid(__pfn);                                    \
+        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +         \
+                               NODE_DATA(__n)->node_spanned_pages)      \
+                    : 0);                                               \
+})
+
+#endif
+
+#define virt_to_pfn(kaddr)      PFN_DOWN(virt_to_phys((void *)(kaddr)))
+#define virt_to_page(kaddr)     pfn_to_page(virt_to_pfn(kaddr))
+
+extern bool __virt_addr_valid(const volatile void *kaddr);
+#define virt_addr_valid(kaddr)                                          \
+        __virt_addr_valid((const volatile void *) (kaddr))
+
+#define VM_DATA_DEFAULT_FLAGS   VM_DATA_FLAGS_TSK_EXEC
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/getorder.h>
+
+#endif /* _ASM_PAGE_H */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
new file mode 100644
index 000000000..6f4864920
--- /dev/null
+++ b/arch/mips/include/asm/pci.h
@@ -0,0 +1,149 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_PCI_H
+#define _ASM_PCI_H
+
+#include <linux/mm.h>
+
+#ifdef __KERNEL__
+
+/*
+ * This file essentially defines the interface between board
+ * specific PCI code and MIPS common PCI code.  Should potentially put
+ * into include/asm/pci.h file.
+ */
+
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/of.h>
+
+#ifdef CONFIG_PCI_DRIVERS_LEGACY
+
+/*
+ * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
+ * multiple PCI channels may have multiple PCI host controllers or a
+ * single controller supporting multiple channels.
+ */
+struct pci_controller {
+        struct list_head list;
+        struct pci_bus *bus;
+        struct device_node *of_node;
+
+        struct pci_ops *pci_ops;
+        struct resource *mem_resource;
+        unsigned long mem_offset;
+        struct resource *io_resource;
+        unsigned long io_offset;
+        unsigned long io_map_base;
+        struct resource *busn_resource;
+
+#ifndef CONFIG_PCI_DOMAINS_GENERIC
+        unsigned int index;
+        /* For compatibility with current (as of July 2003) pciutils
+           and XFree86. Eventually will be removed. */
+        unsigned int need_domain_info;
+#endif
+
+        /* Optional access methods for reading/writing the bus number
+           of the PCI controller */
+        int (*get_busno)(void);
+        void (*set_busno)(int busno);
+};
+
+/*
+ * Used by boards to register their PCI busses before the actual scanning.
+ */
+extern void register_pci_controller(struct pci_controller *hose);
+
+/*
+ * board supplied pci irq fixup routine
+ */
+extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+extern int pcibios_plat_dev_init(struct pci_dev *dev);
+
+extern char * (*pcibios_plat_setup)(char *str);
+
+#ifdef CONFIG_OF
+/* this function parses memory ranges from a device node */
+extern void pci_load_of_ranges(struct pci_controller *hose,
+                               struct device_node *node);
+#else
+static inline void pci_load_of_ranges(struct pci_controller *hose,
+                                      struct device_node *node) {}
+#endif
+
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+static inline void set_pci_need_domain_info(struct pci_controller *hose,
+                                            int need_domain_info)
+{
+        /* nothing to do */
+}
+#elif defined(CONFIG_PCI_DOMAINS)
+static inline void set_pci_need_domain_info(struct pci_controller *hose,
+                                            int need_domain_info)
+{
+        hose->need_domain_info = need_domain_info;
+}
+#endif /* CONFIG_PCI_DOMAINS */
+
+#endif
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+static inline unsigned int pcibios_assign_all_busses(void)
+{
+        return 1;
+}
+
+extern unsigned long PCIBIOS_MIN_IO;
+extern unsigned long PCIBIOS_MIN_MEM;
+
+#define PCIBIOS_MIN_CARDBUS_IO  0x4000
+
+#define HAVE_PCI_MMAP
+#define ARCH_GENERIC_PCI_MMAP_RESOURCE
+
+/*
+ * Dynamic DMA mapping stuff.
+ * MIPS has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return pci_domain_nr(bus);
+}
+#elif defined(CONFIG_PCI_DOMAINS)
+#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+        return hose->need_domain_info;
+}
+#endif /* CONFIG_PCI_DOMAINS */
+
+#endif /* __KERNEL__ */
+
+/* Do platform specific device initialization at pci_enable_device() time */
+extern int pcibios_plat_dev_init(struct pci_dev *dev);
+
+/* Chances are this interrupt is wired PC-style ...  */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? 15 : 14;
+}
+
+#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
new file mode 100644
index 000000000..9c476a040
--- /dev/null
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -0,0 +1,825 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
+ * revision 1.76.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_PCI_BRIDGE_H
+#define _ASM_PCI_BRIDGE_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <asm/xtalk/xwidget.h>          /* generic widget header */
+#include <asm/sn/types.h>
+
+/* I/O page size */
+
+#define IOPFNSHIFT              12      /* 4K per mapped page */
+
+#define IOPGSIZE                (1 << IOPFNSHIFT)
+#define IOPG(x)                 ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
+
+/* Bridge RAM sizes */
+
+#define BRIDGE_ATE_RAM_SIZE     0x00000400      /* 1kB ATE RAM */
+
+#define BRIDGE_CONFIG_BASE      0x20000
+#define BRIDGE_CONFIG1_BASE     0x28000
+#define BRIDGE_CONFIG_END       0x30000
+#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
+
+#define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
+#define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
+#define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
+#define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
+
+/* ========================================================================
+ *    Bridge address map
+ */
+
+#ifndef __ASSEMBLY__
+
+#define ATE_V           0x01
+#define ATE_CO          0x02
+#define ATE_PREC        0x04
+#define ATE_PREF        0x08
+#define ATE_BAR         0x10
+
+#define ATE_PFNSHIFT            12
+#define ATE_TIDSHIFT            8
+#define ATE_RMFSHIFT            48
+
+#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
+                                 ((xid)<<ATE_TIDSHIFT) | \
+                                 (attr))
+
+#define BRIDGE_INTERNAL_ATES    128
+
+/*
+ * It is generally preferred that hardware registers on the bridge
+ * are located from C code via this structure.
+ *
+ * Generated from Bridge spec dated 04oct95
+ */
+
+struct bridge_regs {
+        /* Local Registers                             0x000000-0x00FFFF */
+
+        /* standard widget configuration               0x000000-0x000057 */
+        widget_cfg_t        b_widget;                   /* 0x000000 */
+
+        /* helper fieldnames for accessing bridge widget */
+
+#define b_wid_id                        b_widget.w_id
+#define b_wid_stat                      b_widget.w_status
+#define b_wid_err_upper                 b_widget.w_err_upper_addr
+#define b_wid_err_lower                 b_widget.w_err_lower_addr
+#define b_wid_control                   b_widget.w_control
+#define b_wid_req_timeout               b_widget.w_req_timeout
+#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
+#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
+#define b_wid_err_cmdword               b_widget.w_err_cmd_word
+#define b_wid_llp                       b_widget.w_llp_cfg
+#define b_wid_tflush                    b_widget.w_tflush
+
+        /* bridge-specific widget configuration 0x000058-0x00007F */
+        u32     _pad_000058;
+        u32     b_wid_aux_err;          /* 0x00005C */
+        u32     _pad_000060;
+        u32     b_wid_resp_upper;               /* 0x000064 */
+        u32     _pad_000068;
+        u32     b_wid_resp_lower;               /* 0x00006C */
+        u32     _pad_000070;
+        u32      b_wid_tst_pin_ctrl;            /* 0x000074 */
+        u32     _pad_000078[2];
+
+        /* PMU & Map 0x000080-0x00008F */
+        u32     _pad_000080;
+        u32     b_dir_map;                      /* 0x000084 */
+        u32     _pad_000088[2];
+
+        /* SSRAM 0x000090-0x00009F */
+        u32     _pad_000090;
+        u32     b_ram_perr;                     /* 0x000094 */
+        u32     _pad_000098[2];
+
+        /* Arbitration 0x0000A0-0x0000AF */
+        u32     _pad_0000A0;
+        u32     b_arb;                          /* 0x0000A4 */
+        u32     _pad_0000A8[2];
+
+        /* Number In A Can 0x0000B0-0x0000BF */
+        u32     _pad_0000B0;
+        u32     b_nic;                          /* 0x0000B4 */
+        u32     _pad_0000B8[2];
+
+        /* PCI/GIO 0x0000C0-0x0000FF */
+        u32     _pad_0000C0;
+        u32     b_bus_timeout;                  /* 0x0000C4 */
+#define b_pci_bus_timeout b_bus_timeout
+
+        u32     _pad_0000C8;
+        u32     b_pci_cfg;                      /* 0x0000CC */
+        u32     _pad_0000D0;
+        u32     b_pci_err_upper;                /* 0x0000D4 */
+        u32     _pad_0000D8;
+        u32     b_pci_err_lower;                /* 0x0000DC */
+        u32     _pad_0000E0[8];
+#define b_gio_err_lower b_pci_err_lower
+#define b_gio_err_upper b_pci_err_upper
+
+        /* Interrupt 0x000100-0x0001FF */
+        u32     _pad_000100;
+        u32     b_int_status;                   /* 0x000104 */
+        u32     _pad_000108;
+        u32     b_int_enable;                   /* 0x00010C */
+        u32     _pad_000110;
+        u32     b_int_rst_stat;                 /* 0x000114 */
+        u32     _pad_000118;
+        u32     b_int_mode;                     /* 0x00011C */
+        u32     _pad_000120;
+        u32     b_int_device;                   /* 0x000124 */
+        u32     _pad_000128;
+        u32     b_int_host_err;                 /* 0x00012C */
+
+        struct {
+                u32     __pad;                  /* 0x0001{30,,,68} */
+                u32     addr;                   /* 0x0001{34,,,6C} */
+        } b_int_addr[8];                                /* 0x000130 */
+
+        u32     _pad_000170[36];
+
+        /* Device 0x000200-0x0003FF */
+        struct {
+                u32     __pad;                  /* 0x0002{00,,,38} */
+                u32     reg;                    /* 0x0002{04,,,3C} */
+        } b_device[8];                                  /* 0x000200 */
+
+        struct {
+                u32     __pad;                  /* 0x0002{40,,,78} */
+                u32     reg;                    /* 0x0002{44,,,7C} */
+        } b_wr_req_buf[8];                              /* 0x000240 */
+
+        struct {
+                u32     __pad;                  /* 0x0002{80,,,88} */
+                u32     reg;                    /* 0x0002{84,,,8C} */
+        } b_rrb_map[2];                                 /* 0x000280 */
+#define b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
+#define b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
+
+        u32     _pad_000290;
+        u32     b_resp_status;                  /* 0x000294 */
+        u32     _pad_000298;
+        u32     b_resp_clear;                   /* 0x00029C */
+
+        u32     _pad_0002A0[24];
+
+        char            _pad_000300[0x10000 - 0x000300];
+
+        /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
+        union {
+                u64     wr;                     /* write-only */
+                struct {
+                        u32     _p_pad;
+                        u32     rd;             /* read-only */
+                }                       hi;
+        }                           b_int_ate_ram[128];
+
+        char    _pad_010400[0x11000 - 0x010400];
+
+        /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
+        struct {
+                u32     _p_pad;
+                u32     rd;             /* read-only */
+        } b_int_ate_ram_lo[128];
+
+        char    _pad_011400[0x20000 - 0x011400];
+
+        /* PCI Device Configuration Spaces 0x020000-0x027FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+                union {
+                        u8      c[0x100 / 1];
+                        u16     s[0x100 / 2];
+                        u32     l[0x100 / 4];
+                        u64     d[0x100 / 8];
+                } f[8];
+        } b_type0_cfg_dev[8];                                   /* 0x020000 */
+
+        /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+        } b_type1_cfg;                                  /* 0x028000-0x029000 */
+
+        char    _pad_029000[0x007000];                  /* 0x029000-0x030000 */
+
+        /* PCI Interrupt Acknowledge Cycle 0x030000 */
+        union {
+                u8      c[8 / 1];
+                u16     s[8 / 2];
+                u32     l[8 / 4];
+                u64     d[8 / 8];
+        } b_pci_iack;                                           /* 0x030000 */
+
+        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
+
+        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
+        u64     b_ext_ate_ram[0x10000];
+
+        /* Reserved 0x100000-0x1FFFFF */
+        char    _pad_100000[0x200000-0x100000];
+
+        /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x100000 / 1];
+                u16     s[0x100000 / 2];
+                u32     l[0x100000 / 4];
+                u64     d[0x100000 / 8];
+        } b_devio_raw[10];                              /* 0x200000 */
+
+        /* b_devio macro is a bit strange; it reflects the
+         * fact that the Bridge ASIC provides 2M for the
+         * first two DevIO windows and 1M for the other six.
+         */
+#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+        /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
+        union {         /* make all access sizes available. */
+                u8      c[0x400000 / 1];        /* read-only */
+                u16     s[0x400000 / 2];        /* read-write */
+                u32     l[0x400000 / 4];        /* read-only */
+                u64     d[0x400000 / 8];        /* read-only */
+        } b_external_flash;                     /* 0xC00000 */
+};
+
+/*
+ * Field formats for Error Command Word and Auxiliary Error Command Word
+ * of bridge.
+ */
+struct bridge_err_cmdword {
+        union {
+                u32             cmd_word;
+                struct {
+                        u32     didn:4,         /* Destination ID  */
+                                sidn:4,         /* Source ID       */
+                                pactyp:4,       /* Packet type     */
+                                tnum:5,         /* Trans Number    */
+                                coh:1,          /* Coh Transaction */
+                                ds:2,           /* Data size       */
+                                gbr:1,          /* GBR enable      */
+                                vbpm:1,         /* VBPM message    */
+                                error:1,        /* Error occurred  */
+                                barr:1,         /* Barrier op      */
+                                rsvd:8;
+                } berr_st;
+        } berr_un;
+};
+
+#define berr_field      berr_un.berr_st
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The values of these macros can and should be crosschecked
+ * regularly against the offsets of the like-named fields
+ * within the bridge_regs structure above.
+ */
+
+/* Byte offset macros for Bridge internal registers */
+
+#define BRIDGE_WID_ID           WIDGET_ID
+#define BRIDGE_WID_STAT         WIDGET_STATUS
+#define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
+#define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
+#define BRIDGE_WID_CONTROL      WIDGET_CONTROL
+#define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
+#define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
+#define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
+#define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
+#define BRIDGE_WID_LLP          WIDGET_LLP_CFG
+#define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
+
+#define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
+#define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
+#define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
+#define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
+
+#define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
+
+#define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
+
+#define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
+
+#define BRIDGE_NIC              0x0000B4        /* Number In A Can */
+
+#define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
+#define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
+#define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
+#define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
+#define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
+
+#define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
+#define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
+#define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
+#define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
+#define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
+#define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
+
+#define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
+#define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
+#define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
+
+#define BRIDGE_DEVICE0          0x000204        /* Device 0 */
+#define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
+#define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
+
+#define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
+#define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
+#define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
+
+#define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
+#define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
+
+#define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
+#define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
+
+/* Byte offset macros for Bridge I/O space */
+
+#define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
+
+#define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
+#define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
+#define BRIDGE_TYPE0_CFG_DEVF(s, f)     (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
+                                         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
+
+#define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
+
+#define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
+#define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
+
+/* Byte offset macros for Bridge device IO spaces */
+
+#define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
+#define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
+#define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
+#define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
+#define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
+
+#define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
+#define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
+
+#define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
+
+#define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
+
+/* ========================================================================
+ *    Bridge register bit field definitions
+ */
+
+/* Widget part number of bridge */
+#define BRIDGE_WIDGET_PART_NUM          0xc002
+#define XBRIDGE_WIDGET_PART_NUM         0xd002
+
+/* Manufacturer of bridge */
+#define BRIDGE_WIDGET_MFGR_NUM          0x036
+#define XBRIDGE_WIDGET_MFGR_NUM         0x024
+
+/* Revision numbers for known Bridge revisions */
+#define BRIDGE_REV_A                    0x1
+#define BRIDGE_REV_B                    0x2
+#define BRIDGE_REV_C                    0x3
+#define BRIDGE_REV_D                    0x4
+
+/* Bridge widget status register bits definition */
+
+#define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
+#define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
+#define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
+#define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
+#define BRIDGE_STAT_PENDING             (0x1F << 0)
+
+/* Bridge widget control register bits definition */
+#define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)
+#define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
+#define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
+#define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
+#define BRIDGE_CTRL_RST(n)              ((n) << 24)
+#define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
+#define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
+#define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
+#define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
+#define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
+#define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
+#define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
+#define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
+#define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
+#define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
+#define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
+#define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
+#define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
+#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
+#define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
+#define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
+#define BRIDGE_CTRL_SYS_END             (0x1 << 9)
+#define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
+#define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
+#define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
+#define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
+
+/* Bridge Response buffer Error Upper Register bit fields definition */
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+#define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
+
+#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
+                        (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
+                                BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+
+#define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
+                        (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
+                                 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+
+/* Bridge direct mapping register bits definition */
+#define BRIDGE_DIRMAP_W_ID_SHFT         20
+#define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
+#define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
+#define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
+#define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
+#define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
+
+/* Bridge Arbitration register bits definition */
+#define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
+#define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
+#define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
+#define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
+#define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
+#define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
+#define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
+#define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
+#define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
+#define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
+#define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
+
+/* Bridge Bus time-out register bits definition */
+#define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
+#define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
+#define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
+#define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
+#define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
+
+/* Bridge interrupt status register bits definition */
+#define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)
+#define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)
+#define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
+#define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
+#define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
+#define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
+#define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
+#define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
+#define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
+#define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
+#define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
+#define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
+#define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
+#define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
+#define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
+#define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
+#define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
+#define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
+#define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
+#define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
+#define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
+#define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
+#define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
+#define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
+#define BRIDGE_ISR_INT_MSK              (0xff << 0)
+#define BRIDGE_ISR_INT(x)               (0x1 << (x))
+
+#define BRIDGE_ISR_LINK_ERROR           \
+                (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
+                 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
+                 BRIDGE_ISR_LLP_TCTY)
+
+#define BRIDGE_ISR_PCIBUS_PIOERR        \
+                (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+
+#define BRIDGE_ISR_PCIBUS_ERROR         \
+                (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
+                 BRIDGE_ISR_PCI_PARITY)
+
+#define BRIDGE_ISR_XTALK_ERROR          \
+                (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
+                 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
+                 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
+                 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
+                 BRIDGE_ISR_UNEXP_RESP)
+
+#define BRIDGE_ISR_ERRORS               \
+                (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
+                 BRIDGE_ISR_PMU_ESIZE_FAULT)
+
+/*
+ * List of Errors which are fatal and kill the system
+ */
+#define BRIDGE_ISR_ERROR_FATAL          \
+                ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+
+#define BRIDGE_ISR_ERROR_DUMP           \
+                (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+
+/* Bridge interrupt enable register bits definition */
+#define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
+#define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
+#define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
+#define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
+#define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
+#define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
+#define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
+#define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
+#define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
+#define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
+#define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
+#define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
+#define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
+#define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
+#define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
+#define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
+#define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
+#define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
+#define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
+#define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
+#define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
+#define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
+#define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
+#define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
+#define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
+
+/* Bridge interrupt reset register bits definition */
+#define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
+#define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
+#define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
+#define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
+#define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
+#define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
+#define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_ALL_CLR              0x7f
+
+#define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
+                                         BRIDGE_ISR_XREQ_FIFO_OFLOW)
+#define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
+                                         BRIDGE_ISR_RESP_XTLK_ERR | \
+                                         BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+#define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
+                                         BRIDGE_ISR_BAD_XREQ_PKT | \
+                                         BRIDGE_ISR_REQ_XTLK_ERR | \
+                                         BRIDGE_ISR_INVLD_ADDR)
+#define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
+                                         BRIDGE_ISR_LLP_REC_CBERR | \
+                                         BRIDGE_ISR_LLP_RCTY | \
+                                         BRIDGE_ISR_LLP_TX_RETRY | \
+                                         BRIDGE_ISR_LLP_TCTY)
+#define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
+                                         BRIDGE_ISR_PMU_ESIZE_FAULT)
+#define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
+                                         BRIDGE_ISR_PCI_PARITY | \
+                                         BRIDGE_ISR_PCI_SERR | \
+                                         BRIDGE_ISR_PCI_PERR | \
+                                         BRIDGE_ISR_PCI_MST_TIMEOUT | \
+                                         BRIDGE_ISR_PCI_RETRY_CNT)
+
+#define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
+                                         BRIDGE_ISR_GIO_MST_TIMEOUT)
+
+/* Bridge INT_DEV register bits definition */
+#define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
+#define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
+#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
+
+/* Bridge interrupt(x) register bits definition */
+#define BRIDGE_INT_ADDR_HOST            0x0003FF00
+#define BRIDGE_INT_ADDR_FLD             0x000000FF
+
+#define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
+#define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
+#define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
+
+#define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
+
+/*
+ * The NASID should be shifted by this amount and stored into the
+ * interrupt(x) register.
+ */
+#define BRIDGE_INT_ADDR_NASID_SHFT      8
+
+/*
+ * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
+ * memory.
+ */
+#define BRIDGE_INT_ADDR_DEST_IO         (1 << 17)
+#define BRIDGE_INT_ADDR_DEST_MEM        0
+#define BRIDGE_INT_ADDR_MASK            (1 << 17)
+
+/* Bridge device(x) register bits definition */
+#define BRIDGE_DEV_ERR_LOCK_EN          0x10000000
+#define BRIDGE_DEV_PAGE_CHK_DIS         0x08000000
+#define BRIDGE_DEV_FORCE_PCI_PAR        0x04000000
+#define BRIDGE_DEV_VIRTUAL_EN           0x02000000
+#define BRIDGE_DEV_PMU_WRGA_EN          0x01000000
+#define BRIDGE_DEV_DIR_WRGA_EN          0x00800000
+#define BRIDGE_DEV_DEV_SIZE             0x00400000
+#define BRIDGE_DEV_RT                   0x00200000
+#define BRIDGE_DEV_SWAP_PMU             0x00100000
+#define BRIDGE_DEV_SWAP_DIR             0x00080000
+#define BRIDGE_DEV_PREF                 0x00040000
+#define BRIDGE_DEV_PRECISE              0x00020000
+#define BRIDGE_DEV_COH                  0x00010000
+#define BRIDGE_DEV_BARRIER              0x00008000
+#define BRIDGE_DEV_GBR                  0x00004000
+#define BRIDGE_DEV_DEV_SWAP             0x00002000
+#define BRIDGE_DEV_DEV_IO_MEM           0x00001000
+#define BRIDGE_DEV_OFF_MASK             0x00000fff
+#define BRIDGE_DEV_OFF_ADDR_SHFT        20
+
+#define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_PMU)
+#define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_PREF                | \
+                                         BRIDGE_DEV_PRECISE             | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+#define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+
+/* Bridge Error Upper register bit field definition */
+#define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
+#define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
+#define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
+#define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
+#define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
+
+/* Bridge interrupt mode register bits definition */
+#define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
+
+/* this should be written to the xbow's link_control(x) register */
+#define BRIDGE_CREDIT   3
+
+/* RRB assignment register */
+#define BRIDGE_RRB_EN   0x8     /* after shifting down */
+#define BRIDGE_RRB_DEV  0x7     /* after shifting down */
+#define BRIDGE_RRB_VDEV 0x4     /* after shifting down */
+#define BRIDGE_RRB_PDEV 0x3     /* after shifting down */
+
+/* RRB status register */
+#define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
+#define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
+
+/* RRB clear register */
+#define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
+
+/* xbox system controller declarations */
+#define XBOX_BRIDGE_WID         8
+#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
+#define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
+#define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
+
+/* ========================================================================
+ */
+/*
+ * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
+ * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
+ */
+/* XTALK addresses that map into Bridge Bus addr space */
+#define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
+#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
+#define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
+#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
+#define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
+#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
+
+/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
+#define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
+#define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
+#define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
+#define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
+
+/* XTALK addresses that map into PCI addresses */
+#define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
+
+/*
+ * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
+ */
+/* Bridge Bus DMA addresses */
+#define BRIDGE_LOCAL_BASE               0
+#define BRIDGE_DMA_MAPPED_BASE          0x40000000
+#define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
+#define BRIDGE_DMA_DIRECT_BASE          0x80000000
+#define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
+
+#define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
+
+/* PCI addresses of regions decoded by Bridge for DMA */
+#define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
+#define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
+
+#define IS_PCI32_LOCAL(x)       ((ulong_t)(x) < PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)      ((ulong_t)(x) < PCI32_DIRECT_BASE && \
+                                        (ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)      ((ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI64(x)             ((ulong_t)(x) >= PCI64_BASE)
+
+/*
+ * The GIO address space.
+ */
+/* Xtalk to GIO PIO */
+#define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+
+#define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
+
+/* GIO addresses of regions decoded by Bridge for DMA */
+#define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
+#define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
+
+#define IS_GIO_LOCAL(x)         ((ulong_t)(x) < GIO_MAPPED_BASE)
+#define IS_GIO_MAPPED(x)        ((ulong_t)(x) < GIO_DIRECT_BASE && \
+                                        (ulong_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_DIRECT(x)        ((ulong_t)(x) >= GIO_MAPPED_BASE)
+
+/* PCI to xtalk mapping */
+
+/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
+ * which xtalk address is accessed
+ */
+#define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
+#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
+        ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
+                ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
+
+/* 64-bit address attribute masks */
+#define PCI64_ATTR_TARG_MASK    0xf000000000000000
+#define PCI64_ATTR_TARG_SHFT    60
+#define PCI64_ATTR_PREF         0x0800000000000000
+#define PCI64_ATTR_PREC         0x0400000000000000
+#define PCI64_ATTR_VIRTUAL      0x0200000000000000
+#define PCI64_ATTR_BAR          0x0100000000000000
+#define PCI64_ATTR_RMF_MASK     0x00ff000000000000
+#define PCI64_ATTR_RMF_SHFT     48
+
+struct bridge_controller {
+        struct resource         busn;
+        struct bridge_regs      *base;
+        unsigned long           baddr;
+        unsigned long           intr_addr;
+        struct irq_domain       *domain;
+        unsigned int            pci_int[8][2];
+        unsigned int            int_mapping[8][2];
+        u32                     ioc3_sid[8];
+        nasid_t                 nasid;
+};
+
+#define BRIDGE_CONTROLLER(bus) \
+        ((struct bridge_controller *)((bus)->sysdata))
+
+#define bridge_read(bc, reg)            __raw_readl(&bc->base->reg)
+#define bridge_write(bc, reg, val)      __raw_writel(val, &bc->base->reg)
+#define bridge_set(bc, reg, val)        \
+        __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
+#define bridge_clr(bc, reg, val)        \
+        __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
+
+#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
new file mode 100644
index 000000000..0babf6bbb
--- /dev/null
+++ b/arch/mips/include/asm/perf_event.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+/* Leave it empty here. The file is required by linux/perf_event.h */
+#endif /* __MIPS_PERF_EVENT_H__ */
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
new file mode 100644
index 000000000..71153c369
--- /dev/null
+++ b/arch/mips/include/asm/pgalloc.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGALLOC_H
+#define _ASM_PGALLOC_H
+
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+
+#define __HAVE_ARCH_PMD_ALLOC_ONE
+#define __HAVE_ARCH_PUD_ALLOC_ONE
+#define __HAVE_ARCH_PGD_FREE
+#include <asm-generic/pgalloc.h>
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+        pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+        pgtable_t pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+/*
+ * Initialize a new pmd table with invalid pointers.
+ */
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+#ifndef __PAGETABLE_PMD_FOLDED
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud((unsigned long)pmd));
+}
+#endif
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        free_pages((unsigned long)pgd, PGD_ORDER);
+}
+
+#define __pte_free_tlb(tlb,pte,address)                 \
+do {                                                    \
+        pgtable_pte_page_dtor(pte);                     \
+        tlb_remove_page((tlb), pte);                    \
+} while (0)
+
+#ifndef __PAGETABLE_PMD_FOLDED
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        pmd_t *pmd;
+        struct page *pg;
+
+        pg = alloc_pages(GFP_KERNEL_ACCOUNT, PMD_ORDER);
+        if (!pg)
+                return NULL;
+
+        if (!pgtable_pmd_page_ctor(pg)) {
+                __free_pages(pg, PMD_ORDER);
+                return NULL;
+        }
+
+        pmd = (pmd_t *)page_address(pg);
+        pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table);
+        return pmd;
+}
+
+#define __pmd_free_tlb(tlb, x, addr)    pmd_free((tlb)->mm, x)
+
+#endif
+
+#ifndef __PAGETABLE_PUD_FOLDED
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        pud_t *pud;
+
+        pud = (pud_t *) __get_free_pages(GFP_KERNEL, PUD_ORDER);
+        if (pud)
+                pud_init((unsigned long)pud, (unsigned long)invalid_pmd_table);
+        return pud;
+}
+
+static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4d, pud_t *pud)
+{
+        set_p4d(p4d, __p4d((unsigned long)pud));
+}
+
+#define __pud_free_tlb(tlb, x, addr)    pud_free((tlb)->mm, x)
+
+#endif /* __PAGETABLE_PUD_FOLDED */
+
+extern void pagetable_init(void);
+
+#endif /* _ASM_PGALLOC_H */
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
new file mode 100644
index 000000000..6c0532d7b
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -0,0 +1,248 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_32_H
+#define _ASM_PGTABLE_32_H
+
+#include <asm/addrspace.h>
+#include <asm/page.h>
+
+#include <linux/linkage.h>
+#include <asm/cachectl.h>
+#include <asm/fixmap.h>
+
+#include <asm-generic/pgtable-nopmd.h>
+
+#ifdef CONFIG_HIGHMEM
+#include <asm/highmem.h>
+#endif
+
+/*
+ * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
+ *
+ *  We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
+ * our 2-level table layout would normally have a PGD entry cover a contiguous
+ * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
+ * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
+ * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
+ * support, not one of the standard supported sizes (1MB,4MB,16MB,...).
+ *  To correct for this, when huge pages are enabled, we halve the number of
+ * pointers a PTE page holds, making its last half go to waste. Correspondingly,
+ * we double the number of PGD pages. Overall, page table memory overhead
+ * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
+ *
+ * NOTE: We don't yet support huge pages if extended-addressing is enabled
+ *       (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
+ */
+
+extern int temp_tlb_entry;
+
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *      starting at the top and working down. This is for populating the
+ *      TLB before trap_init() puts the TLB miss handler in place. It
+ *      should be used only for entries matching the actual page tables,
+ *      to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+/*
+ * Basically we have the same two-level (which is the logical three level
+ * Linux page table layout folded) page tables as the i386.  Some day
+ * when we have proper page coloring support we can have a 1% quicker
+ * tlb refill handling mechanism, but for now it is a bit slower but
+ * works even with the cache aliasing problem the R4k and above have.
+ */
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define PGDIR_SHIFT    (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2 - 1)
+#else
+# define PGDIR_SHIFT    (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
+#endif
+
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * Entries per page directory level: we use two-level, so
+ * we don't really have any PUD/PMD directory physically.
+ */
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define __PGD_ORDER    (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
+#else
+# define __PGD_ORDER    (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#endif
+
+#define PGD_ORDER       (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       aieeee_attempt_to_allocate_pmd
+#define PTE_ORDER       0
+
+#define PTRS_PER_PGD    (USER_PTRS_PER_PGD * 2)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define PTRS_PER_PTE   ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t) / 2)
+#else
+# define PTRS_PER_PTE   ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+#endif
+
+#define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0UL
+
+#define VMALLOC_START     MAP_BASE
+
+#define PKMAP_END       ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
+#define PKMAP_BASE      (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
+
+#ifdef CONFIG_HIGHMEM
+# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
+#else
+# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
+#endif
+
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#else
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern void load_pgd(unsigned long pg_dir);
+
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+static inline int pmd_bad(pmd_t pmd)
+{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+        /* pmd_huge(pmd) but inline */
+        if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+                return 0;
+#endif
+
+        if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
+                return 1;
+
+        return 0;
+}
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+#if defined(CONFIG_XPA)
+
+#define MAX_POSSIBLE_PHYSMEM_BITS 40
+#define pte_pfn(x)              (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
+static inline pte_t
+pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+        pte_t pte;
+
+        pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
+                                (pgprot_val(prot) & ~_PFNX_MASK);
+        pte.pte_high = (pfn << _PFN_SHIFT) |
+                                (pgprot_val(prot) & ~_PFN_MASK);
+        return pte;
+}
+
+#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+#define MAX_POSSIBLE_PHYSMEM_BITS 36
+#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
+
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+        pte_t pte;
+
+        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
+        pte.pte_low = pgprot_val(prot);
+
+        return pte;
+}
+
+#else
+
+#define MAX_POSSIBLE_PHYSMEM_BITS 32
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot)      __pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#endif
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
+
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#if defined(CONFIG_CPU_R3K_TLB)
+
+/* Swap entries must have VALID bit cleared. */
+#define __swp_type(x)                   (((x).val >> 10) & 0x1f)
+#define __swp_offset(x)                 ((x).val >> 15)
+#define __swp_entry(type,offset)        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+#else
+
+#if defined(CONFIG_XPA)
+
+/* Swap entries must have VALID and GLOBAL bits cleared. */
+#define __swp_type(x)                   (((x).val >> 4) & 0x1f)
+#define __swp_offset(x)                  ((x).val >> 9)
+#define __swp_entry(type,offset)        ((swp_entry_t)  { ((type) << 4) | ((offset) << 9) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)           ((pte_t) { 0, (x).val })
+
+#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/* Swap entries must have VALID and GLOBAL bits cleared. */
+#define __swp_type(x)                   (((x).val >> 2) & 0x1f)
+#define __swp_offset(x)                  ((x).val >> 7)
+#define __swp_entry(type, offset)       ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)           ((pte_t) { 0, (x).val })
+
+#else
+/*
+ * Constraints:
+ *      _PAGE_PRESENT at bit 0
+ *      _PAGE_MODIFIED at bit 4
+ *      _PAGE_GLOBAL at bit 6
+ *      _PAGE_VALID at bit 7
+ */
+#define __swp_type(x)                   (((x).val >> 8) & 0x1f)
+#define __swp_offset(x)                  ((x).val >> 13)
+#define __swp_entry(type,offset)        ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
+
+#endif /* defined(CONFIG_CPU_R3K_TLB) */
+
+#endif /* _ASM_PGTABLE_32_H */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
new file mode 100644
index 000000000..1e7d6ce9d
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -0,0 +1,346 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_64_H
+#define _ASM_PGTABLE_64_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cachectl.h>
+#include <asm/fixmap.h>
+
+#if CONFIG_PGTABLE_LEVELS == 2
+#include <asm-generic/pgtable-nopmd.h>
+#elif CONFIG_PGTABLE_LEVELS == 3
+#include <asm-generic/pgtable-nopud.h>
+#else
+#include <asm-generic/pgtable-nop4d.h>
+#endif
+
+/*
+ * Each address space has 2 4K pages as its page directory, giving 1024
+ * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
+ * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
+ * tables. Each page table is also a single 4K page, giving 512 (==
+ * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
+ * invalid_pmd_table, each pmd entry is initialized to point to
+ * invalid_pte_table, each pte is initialized to 0.
+ *
+ * Kernel mappings: kernel mappings are held in the swapper_pg_table.
+ * The layout is identical to userspace except it's indexed with the
+ * fault address - VMALLOC_START.
+ */
+
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#ifdef __PAGETABLE_PMD_FOLDED
+#define PGDIR_SHIFT     (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
+#else
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+# ifdef __PAGETABLE_PUD_FOLDED
+# define PGDIR_SHIFT    (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
+# endif
+#endif
+
+#ifndef __PAGETABLE_PUD_FOLDED
+#define PUD_SHIFT       (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
+#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_MASK        (~(PUD_SIZE-1))
+#define PGDIR_SHIFT     (PUD_SHIFT + (PAGE_SHIFT + PUD_ORDER - 3))
+#endif
+
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * For 4kB page size we use a 3 level page tree and an 8kB pud, which
+ * permits us mapping 40 bits of virtual address space.
+ *
+ * We used to implement 41 bits by having an order 1 pmd level but that seemed
+ * rather pointless.
+ *
+ * For 8kB page size we use a 3 level page tree which permits a total of
+ * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
+ * two levels would be easy to implement.
+ *
+ * For 16kB page size we use a 2 level page tree which permits a total of
+ * 36 bits of virtual address space.  We could add a third level but it seems
+ * like at the moment there's no need for this.
+ *
+ * For 64kB page size we use a 2 level page table tree for a total of 42 bits
+ * of virtual address space.
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+# ifdef CONFIG_MIPS_VA_BITS_48
+#  define PGD_ORDER             0
+#  define PUD_ORDER             0
+# else
+#  define PGD_ORDER             1
+#  define PUD_ORDER             aieeee_attempt_to_allocate_pud
+# endif
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#ifdef CONFIG_MIPS_VA_BITS_48
+#define PGD_ORDER               1
+#else
+#define PGD_ORDER               0
+#endif
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#ifdef CONFIG_MIPS_VA_BITS_48
+#define PMD_ORDER               0
+#else
+#define PMD_ORDER               aieeee_attempt_to_allocate_pmd
+#endif
+#define PTE_ORDER               0
+#endif
+
+#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#ifndef __PAGETABLE_PUD_FOLDED
+#define PTRS_PER_PUD    ((PAGE_SIZE << PUD_ORDER) / sizeof(pud_t))
+#endif
+#ifndef __PAGETABLE_PMD_FOLDED
+#define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
+#endif
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
+#define FIRST_USER_ADDRESS      0UL
+
+/*
+ * TLB refill handlers also map the vmalloc area into xuseg.  Avoid
+ * the first couple of pages so NULL pointer dereferences will still
+ * reliably trap.
+ */
+#define VMALLOC_START           (MAP_BASE + (2 * PAGE_SIZE))
+#define VMALLOC_END     \
+        (MAP_BASE + \
+         min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
+             (1UL << cpu_vmbits)) - (1UL << 32))
+
+#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
+        VMALLOC_START != CKSSEG
+/* Load modules into 32bit-compatible segment. */
+#define MODULE_START    CKSSEG
+#define MODULE_END      (FIXADDR_START-2*PAGE_SIZE)
+#endif
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+#ifndef __PAGETABLE_PMD_FOLDED
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#endif
+#ifndef __PAGETABLE_PUD_FOLDED
+#define pud_ERROR(e) \
+        printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
+#endif
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
+
+#ifndef __PAGETABLE_PUD_FOLDED
+/*
+ * For 4-level pagetables we defines these ourselves, for 3-level the
+ * definitions are below, for 2-level the
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+typedef struct { unsigned long pud; } pud_t;
+#define pud_val(x)      ((x).pud)
+#define __pud(x)        ((pud_t) { (x) })
+
+extern pud_t invalid_pud_table[PTRS_PER_PUD];
+
+/*
+ * Empty pgd entries point to the invalid_pud_table.
+ */
+static inline int p4d_none(p4d_t p4d)
+{
+        return p4d_val(p4d) == (unsigned long)invalid_pud_table;
+}
+
+static inline int p4d_bad(p4d_t p4d)
+{
+        if (unlikely(p4d_val(p4d) & ~PAGE_MASK))
+                return 1;
+
+        return 0;
+}
+
+static inline int p4d_present(p4d_t p4d)
+{
+        return p4d_val(p4d) != (unsigned long)invalid_pud_table;
+}
+
+static inline void p4d_clear(p4d_t *p4dp)
+{
+        p4d_val(*p4dp) = (unsigned long)invalid_pud_table;
+}
+
+static inline unsigned long p4d_page_vaddr(p4d_t p4d)
+{
+        return p4d_val(p4d);
+}
+
+#define p4d_phys(p4d)           virt_to_phys((void *)p4d_val(p4d))
+#define p4d_page(p4d)           (pfn_to_page(p4d_phys(p4d) >> PAGE_SHIFT))
+
+#define p4d_index(address)      (((address) >> P4D_SHIFT) & (PTRS_PER_P4D - 1))
+
+static inline void set_p4d(p4d_t *p4d, p4d_t p4dval)
+{
+        *p4d = p4dval;
+}
+
+#endif
+
+#ifndef __PAGETABLE_PMD_FOLDED
+/*
+ * For 3-level pagetables we defines these ourselves, for 2-level the
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+typedef struct { unsigned long pmd; } pmd_t;
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x)        ((pmd_t) { (x) } )
+
+
+extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
+#endif
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+static inline int pmd_bad(pmd_t pmd)
+{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+        /* pmd_huge(pmd) but inline */
+        if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+                return 0;
+#endif
+
+        if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
+                return 1;
+
+        return 0;
+}
+
+static inline int pmd_present(pmd_t pmd)
+{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+        if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+                return pmd_val(pmd) & _PAGE_PRESENT;
+#endif
+
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+#ifndef __PAGETABLE_PMD_FOLDED
+
+/*
+ * Empty pud entries point to the invalid_pmd_table.
+ */
+static inline int pud_none(pud_t pud)
+{
+        return pud_val(pud) == (unsigned long) invalid_pmd_table;
+}
+
+static inline int pud_bad(pud_t pud)
+{
+        return pud_val(pud) & ~PAGE_MASK;
+}
+
+static inline int pud_present(pud_t pud)
+{
+        return pud_val(pud) != (unsigned long) invalid_pmd_table;
+}
+
+static inline void pud_clear(pud_t *pudp)
+{
+        pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
+}
+#endif
+
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot)      __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#endif
+
+#ifndef __PAGETABLE_PMD_FOLDED
+static inline unsigned long pud_page_vaddr(pud_t pud)
+{
+        return pud_val(pud);
+}
+#define pud_phys(pud)           virt_to_phys((void *)pud_val(pud))
+#define pud_page(pud)           (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
+
+#endif
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+extern void pud_init(unsigned long page, unsigned long pagetable);
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+/*
+ * Non-present pages:  high 40 bits are offset, next 8 bits type,
+ * low 16 bits zero.
+ */
+static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
+{ pte_t pte; pte_val(pte) = (type << 16) | (offset << 24); return pte; }
+
+#define __swp_type(x)           (((x).val >> 16) & 0xff)
+#define __swp_offset(x)         ((x).val >> 24)
+#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+#endif /* _ASM_PGTABLE_64_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
new file mode 100644
index 000000000..2362842ee
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -0,0 +1,285 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software.  We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.  On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things.  The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_XPA)
+
+/*
+ * Page table bit offsets used for 64 bit physical addressing on
+ * MIPS32r5 with XPA.
+ */
+enum pgtable_bits {
+        /* Used by TLB hardware (placed in EntryLo*) */
+        _PAGE_NO_EXEC_SHIFT,
+        _PAGE_NO_READ_SHIFT,
+        _PAGE_GLOBAL_SHIFT,
+        _PAGE_VALID_SHIFT,
+        _PAGE_DIRTY_SHIFT,
+        _CACHE_SHIFT,
+
+        /* Used only by software (masked out before writing EntryLo*) */
+        _PAGE_PRESENT_SHIFT = 24,
+        _PAGE_WRITE_SHIFT,
+        _PAGE_ACCESSED_SHIFT,
+        _PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+        _PAGE_SPECIAL_SHIFT,
+#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+        _PAGE_SOFT_DIRTY_SHIFT,
+#endif
+};
+
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK              0xffffff
+
+#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/*
+ * Page table bit offsets used for 36 bit physical addressing on MIPS32,
+ * for example with Alchemy or Netlogic XLP/XLR.
+ */
+enum pgtable_bits {
+        /* Used by TLB hardware (placed in EntryLo*) */
+        _PAGE_GLOBAL_SHIFT,
+        _PAGE_VALID_SHIFT,
+        _PAGE_DIRTY_SHIFT,
+        _CACHE_SHIFT,
+
+        /* Used only by software (masked out before writing EntryLo*) */
+        _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
+        _PAGE_NO_READ_SHIFT,
+        _PAGE_WRITE_SHIFT,
+        _PAGE_ACCESSED_SHIFT,
+        _PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+        _PAGE_SPECIAL_SHIFT,
+#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+        _PAGE_SOFT_DIRTY_SHIFT,
+#endif
+};
+
+#elif defined(CONFIG_CPU_R3K_TLB)
+
+/* Page table bits used for r3k systems */
+enum pgtable_bits {
+        /* Used only by software (writes to EntryLo ignored) */
+        _PAGE_PRESENT_SHIFT,
+        _PAGE_NO_READ_SHIFT,
+        _PAGE_WRITE_SHIFT,
+        _PAGE_ACCESSED_SHIFT,
+        _PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+        _PAGE_SPECIAL_SHIFT,
+#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+        _PAGE_SOFT_DIRTY_SHIFT,
+#endif
+
+        /* Used by TLB hardware (placed in EntryLo) */
+        _PAGE_GLOBAL_SHIFT = 8,
+        _PAGE_VALID_SHIFT,
+        _PAGE_DIRTY_SHIFT,
+        _CACHE_UNCACHED_SHIFT,
+};
+
+#else
+
+/* Page table bits used for r4k systems */
+enum pgtable_bits {
+        /* Used only by software (masked out before writing EntryLo*) */
+        _PAGE_PRESENT_SHIFT,
+#if !defined(CONFIG_CPU_HAS_RIXI)
+        _PAGE_NO_READ_SHIFT,
+#endif
+        _PAGE_WRITE_SHIFT,
+        _PAGE_ACCESSED_SHIFT,
+        _PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+        _PAGE_HUGE_SHIFT,
+#endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+        _PAGE_SPECIAL_SHIFT,
+#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+        _PAGE_SOFT_DIRTY_SHIFT,
+#endif
+        /* Used by TLB hardware (placed in EntryLo*) */
+#if defined(CONFIG_CPU_HAS_RIXI)
+        _PAGE_NO_EXEC_SHIFT,
+        _PAGE_NO_READ_SHIFT,
+#endif
+        _PAGE_GLOBAL_SHIFT,
+        _PAGE_VALID_SHIFT,
+        _PAGE_DIRTY_SHIFT,
+        _CACHE_SHIFT,
+};
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+
+/* Used only by software */
+#define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+# define _PAGE_HUGE             (1 << _PAGE_HUGE_SHIFT)
+#endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+# define _PAGE_SPECIAL          (1 << _PAGE_SPECIAL_SHIFT)
+#else
+# define _PAGE_SPECIAL          0
+#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+# define _PAGE_SOFT_DIRTY       (1 << _PAGE_SOFT_DIRTY_SHIFT)
+#else
+# define _PAGE_SOFT_DIRTY       0
+#endif
+
+/* Used by TLB hardware (placed in EntryLo*) */
+#if defined(CONFIG_XPA)
+# define _PAGE_NO_EXEC          (1 << _PAGE_NO_EXEC_SHIFT)
+#elif defined(CONFIG_CPU_HAS_RIXI)
+# define _PAGE_NO_EXEC          (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+#endif
+#define _PAGE_NO_READ           (1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)
+#if defined(CONFIG_CPU_R3K_TLB)
+# define _CACHE_UNCACHED        (1 << _CACHE_UNCACHED_SHIFT)
+# define _CACHE_MASK            _CACHE_UNCACHED
+# define _PFN_SHIFT             PAGE_SHIFT
+#else
+# define _CACHE_MASK            (7 << _CACHE_SHIFT)
+# define _PFN_SHIFT             (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+#endif
+
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC           0
+#endif
+
+#define _PAGE_SILENT_READ       _PAGE_VALID
+#define _PAGE_SILENT_WRITE      _PAGE_DIRTY
+
+#define _PFN_MASK               (~((1 << (_PFN_SHIFT)) - 1))
+
+/*
+ * The final layouts of the PTE bits are:
+ *
+ *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
+ *   32-bit, R1 or earler:      CCC D V G M A W R P
+ *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
+ *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
+ */
+
+
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+#ifdef CONFIG_CPU_HAS_RIXI
+        if (cpu_has_rixi) {
+                int sa;
+#ifdef CONFIG_32BIT
+                sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+                sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+                /*
+                 * C has no way to express that this is a DSRL
+                 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
+                 * in the fast path this is done in assembly
+                 */
+                return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+                        ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+        }
+#endif
+
+        return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3K_TLB)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+
+#endif
+
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA           (0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA              (1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED                 (2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT     (3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE              (4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW             (5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW             (6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED     (7<<_CACHE_SHIFT)
+#endif
+
+#define __READABLE      (_PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE     (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK  (_PAGE_ACCESSED | _PAGE_MODIFIED |      \
+                         _PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
new file mode 100644
index 000000000..e5ef0fdd4
--- /dev/null
+++ b/arch/mips/include/asm/pgtable.h
@@ -0,0 +1,744 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_PGTABLE_H
+#define _ASM_PGTABLE_H
+
+#include <linux/mm_types.h>
+#include <linux/mmzone.h>
+#ifdef CONFIG_32BIT
+#include <asm/pgtable-32.h>
+#endif
+#ifdef CONFIG_64BIT
+#include <asm/pgtable-64.h>
+#endif
+
+#include <asm/cmpxchg.h>
+#include <asm/io.h>
+#include <asm/pgtable-bits.h>
+#include <asm/cpu-features.h>
+
+struct mm_struct;
+struct vm_area_struct;
+
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \
+                                 _page_cachable_default)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
+                                 _page_cachable_default)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \
+                                 _page_cachable_default)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | \
+                                 _page_cachable_default)
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+                                 _PAGE_GLOBAL | _page_cachable_default)
+#define PAGE_KERNEL_NC  __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+                                 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+                        __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
+
+/*
+ * If _PAGE_NO_EXEC is not defined, we can't do page protection for
+ * execute, and consider it to be the same as read. Also, write
+ * permissions imply read permissions. This is the closest we can get
+ * by reasonable means..
+ */
+
+/*
+ * Dummy values to fill the table in mmap.c
+ * The real values will be generated at runtime
+ */
+#define __P000 __pgprot(0)
+#define __P001 __pgprot(0)
+#define __P010 __pgprot(0)
+#define __P011 __pgprot(0)
+#define __P100 __pgprot(0)
+#define __P101 __pgprot(0)
+#define __P110 __pgprot(0)
+#define __P111 __pgprot(0)
+
+#define __S000 __pgprot(0)
+#define __S001 __pgprot(0)
+#define __S010 __pgprot(0)
+#define __S011 __pgprot(0)
+#define __S100 __pgprot(0)
+#define __S101 __pgprot(0)
+#define __S110 __pgprot(0)
+#define __S111 __pgprot(0)
+
+extern unsigned long _page_cachable_default;
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero; used
+ * for zero-mapped memory areas etc..
+ */
+
+extern unsigned long empty_zero_page;
+extern unsigned long zero_page_mask;
+
+#define ZERO_PAGE(vaddr) \
+        (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
+#define __HAVE_COLOR_ZERO_PAGE
+
+extern void paging_init(void);
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
+
+#define __pmd_page(pmd)         (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+#ifndef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_page(pmd)           __pmd_page(pmd)
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */
+
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
+
+#define htw_stop()                                                      \
+do {                                                                    \
+        unsigned long flags;                                            \
+                                                                        \
+        if (cpu_has_htw) {                                              \
+                local_irq_save(flags);                                  \
+                if(!raw_current_cpu_data.htw_seq++) {                   \
+                        write_c0_pwctl(read_c0_pwctl() &                \
+                                       ~(1 << MIPS_PWCTL_PWEN_SHIFT));  \
+                        back_to_back_c0_hazard();                       \
+                }                                                       \
+                local_irq_restore(flags);                               \
+        }                                                               \
+} while(0)
+
+#define htw_start()                                                     \
+do {                                                                    \
+        unsigned long flags;                                            \
+                                                                        \
+        if (cpu_has_htw) {                                              \
+                local_irq_save(flags);                                  \
+                if (!--raw_current_cpu_data.htw_seq) {                  \
+                        write_c0_pwctl(read_c0_pwctl() |                \
+                                       (1 << MIPS_PWCTL_PWEN_SHIFT));   \
+                        back_to_back_c0_hazard();                       \
+                }                                                       \
+                local_irq_restore(flags);                               \
+        }                                                               \
+} while(0)
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval);
+
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+#ifdef CONFIG_XPA
+# define pte_none(pte)          (!(((pte).pte_high) & ~_PAGE_GLOBAL))
+#else
+# define pte_none(pte)          (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
+#endif
+
+#define pte_present(pte)        ((pte).pte_low & _PAGE_PRESENT)
+#define pte_no_exec(pte)        ((pte).pte_low & _PAGE_NO_EXEC)
+
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+
+#ifdef CONFIG_XPA
+        if (pte.pte_high & _PAGE_GLOBAL) {
+#else
+        if (pte.pte_low & _PAGE_GLOBAL) {
+#endif
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+                if (pte_none(*buddy)) {
+                        if (!IS_ENABLED(CONFIG_XPA))
+                                buddy->pte_low |= _PAGE_GLOBAL;
+                        buddy->pte_high |= _PAGE_GLOBAL;
+                }
+        }
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        pte_t null = __pte(0);
+
+        htw_stop();
+        /* Preserve global status for the pair */
+        if (IS_ENABLED(CONFIG_XPA)) {
+                if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
+                        null.pte_high = _PAGE_GLOBAL;
+        } else {
+                if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
+                        null.pte_low = null.pte_high = _PAGE_GLOBAL;
+        }
+
+        set_pte_at(mm, addr, ptep, null);
+        htw_start();
+}
+#else
+
+#define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+#define pte_no_exec(pte)        (pte_val(pte) & _PAGE_NO_EXEC)
+
+/*
+ * Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        *ptep = pteval;
+#if !defined(CONFIG_CPU_R3K_TLB)
+        if (pte_val(pteval) & _PAGE_GLOBAL) {
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+# if defined(CONFIG_PHYS_ADDR_T_64BIT) && !defined(CONFIG_CPU_MIPS32)
+                cmpxchg64(&buddy->pte, 0, _PAGE_GLOBAL);
+# else
+                cmpxchg(&buddy->pte, 0, _PAGE_GLOBAL);
+# endif
+        }
+#endif
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        htw_stop();
+#if !defined(CONFIG_CPU_R3K_TLB)
+        /* Preserve global status for the pair */
+        if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
+                set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
+        else
+#endif
+                set_pte_at(mm, addr, ptep, __pte(0));
+        htw_start();
+}
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval)
+{
+        extern void __update_cache(unsigned long address, pte_t pte);
+
+        if (!pte_present(pteval))
+                goto cache_sync_done;
+
+        if (pte_present(*ptep) && (pte_pfn(*ptep) == pte_pfn(pteval)))
+                goto cache_sync_done;
+
+        __update_cache(addr, pteval);
+cache_sync_done:
+        set_pte(ptep, pteval);
+}
+
+/*
+ * (pmds are folded into puds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
+
+#ifndef __PAGETABLE_PMD_FOLDED
+/*
+ * (puds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
+#endif
+
+#define PGD_T_LOG2      (__builtin_ffs(sizeof(pgd_t)) - 1)
+#define PMD_T_LOG2      (__builtin_ffs(sizeof(pmd_t)) - 1)
+#define PTE_T_LOG2      (__builtin_ffs(sizeof(pte_t)) - 1)
+
+/*
+ * We used to declare this array with size but gcc 3.3 and older are not able
+ * to find that this expression is a constant, so the size is dropped.
+ */
+extern pgd_t swapper_pg_dir[];
+
+/*
+ * Platform specific pte_special() and pte_mkspecial() definitions
+ * are required only when ARCH_HAS_PTE_SPECIAL is enabled.
+ */
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+static inline int pte_special(pte_t pte)
+{
+        return pte.pte_low & _PAGE_SPECIAL;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        pte.pte_low |= _PAGE_SPECIAL;
+        return pte;
+}
+#else
+static inline int pte_special(pte_t pte)
+{
+        return pte_val(pte) & _PAGE_SPECIAL;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_SPECIAL;
+        return pte;
+}
+#endif
+#endif /* CONFIG_ARCH_HAS_PTE_SPECIAL */
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+static inline int pte_write(pte_t pte)  { return pte.pte_low & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return pte.pte_low & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return pte.pte_low & _PAGE_ACCESSED; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte.pte_low  &= ~_PAGE_WRITE;
+        if (!IS_ENABLED(CONFIG_XPA))
+                pte.pte_low &= ~_PAGE_SILENT_WRITE;
+        pte.pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte.pte_low  &= ~_PAGE_MODIFIED;
+        if (!IS_ENABLED(CONFIG_XPA))
+                pte.pte_low &= ~_PAGE_SILENT_WRITE;
+        pte.pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte.pte_low  &= ~_PAGE_ACCESSED;
+        if (!IS_ENABLED(CONFIG_XPA))
+                pte.pte_low &= ~_PAGE_SILENT_READ;
+        pte.pte_high &= ~_PAGE_SILENT_READ;
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte.pte_low |= _PAGE_WRITE;
+        if (pte.pte_low & _PAGE_MODIFIED) {
+                if (!IS_ENABLED(CONFIG_XPA))
+                        pte.pte_low |= _PAGE_SILENT_WRITE;
+                pte.pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte.pte_low |= _PAGE_MODIFIED;
+        if (pte.pte_low & _PAGE_WRITE) {
+                if (!IS_ENABLED(CONFIG_XPA))
+                        pte.pte_low |= _PAGE_SILENT_WRITE;
+                pte.pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte.pte_low |= _PAGE_ACCESSED;
+        if (!(pte.pte_low & _PAGE_NO_READ)) {
+                if (!IS_ENABLED(CONFIG_XPA))
+                        pte.pte_low |= _PAGE_SILENT_READ;
+                pte.pte_high |= _PAGE_SILENT_READ;
+        }
+        return pte;
+}
+#else
+static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_WRITE;
+        if (pte_val(pte) & _PAGE_MODIFIED)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
+        if (pte_val(pte) & _PAGE_WRITE)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_ACCESSED;
+        if (!(pte_val(pte) & _PAGE_NO_READ))
+                pte_val(pte) |= _PAGE_SILENT_READ;
+        return pte;
+}
+
+#define pte_sw_mkyoung  pte_mkyoung
+
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+static inline int pte_huge(pte_t pte)   { return pte_val(pte) & _PAGE_HUGE; }
+
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_HUGE;
+        return pte;
+}
+#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline bool pte_soft_dirty(pte_t pte)
+{
+        return pte_val(pte) & _PAGE_SOFT_DIRTY;
+}
+#define pte_swp_soft_dirty pte_soft_dirty
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_SOFT_DIRTY;
+        return pte;
+}
+#define pte_swp_mksoft_dirty pte_mksoft_dirty
+
+static inline pte_t pte_clear_soft_dirty(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_SOFT_DIRTY);
+        return pte;
+}
+#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
+
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
+#endif
+
+/*
+ * Macro to make mark a page protection value as "uncacheable".  Note
+ * that "protection" is really a misnomer here as the protection value
+ * contains the memory attribute bits, dirty bits, and various other
+ * bits as well.
+ */
+#define pgprot_noncached pgprot_noncached
+
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+        unsigned long prot = pgprot_val(_prot);
+
+        prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
+
+        return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+        unsigned long prot = pgprot_val(_prot);
+
+        /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
+        prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
+
+        return __pgprot(prot);
+}
+
+static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
+                                                unsigned long address)
+{
+}
+
+#define __HAVE_ARCH_PTE_SAME
+static inline int pte_same(pte_t pte_a, pte_t pte_b)
+{
+        return pte_val(pte_a) == pte_val(pte_b);
+}
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline int ptep_set_access_flags(struct vm_area_struct *vma,
+                                        unsigned long address, pte_t *ptep,
+                                        pte_t entry, int dirty)
+{
+        if (!pte_same(*ptep, entry))
+                set_pte_at(vma->vm_mm, address, ptep, entry);
+        /*
+         * update_mmu_cache will unconditionally execute, handling both
+         * the case that the PTE changed and the spurious fault case.
+         */
+        return true;
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+#if defined(CONFIG_XPA)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low  &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
+        pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
+        pte.pte_low  |= pgprot_val(newprot) & ~_PFNX_MASK;
+        pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
+        return pte;
+}
+#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low  &= _PAGE_CHG_MASK;
+        pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
+        pte.pte_low  |= pgprot_val(newprot);
+        pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
+        return pte;
+}
+#else
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte_val(pte) &= _PAGE_CHG_MASK;
+        pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_CHG_MASK;
+        if ((pte_val(pte) & _PAGE_ACCESSED) && !(pte_val(pte) & _PAGE_NO_READ))
+                pte_val(pte) |= _PAGE_SILENT_READ;
+        return pte;
+}
+#endif
+
+
+extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
+
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+        unsigned long address, pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        __update_tlb(vma, address, pte);
+}
+
+#define __HAVE_ARCH_UPDATE_MMU_TLB
+#define update_mmu_tlb  update_mmu_cache
+
+static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
+        unsigned long address, pmd_t *pmdp)
+{
+        pte_t pte = *(pte_t *)pmdp;
+
+        __update_tlb(vma, address, pte);
+}
+
+#define kern_addr_valid(addr)   (1)
+
+/*
+ * Allow physical addresses to be fixed up to help 36-bit peripherals.
+ */
+#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
+phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
+int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
+                unsigned long pfn, unsigned long size, pgprot_t prot);
+#define io_remap_pfn_range io_remap_pfn_range
+#else
+#define fixup_bigphys_addr(addr, size)  (addr)
+#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+/* We don't have hardware dirty/accessed bits, generic_pmdp_establish is fine.*/
+#define pmdp_establish generic_pmdp_establish
+
+#define has_transparent_hugepage has_transparent_hugepage
+extern int has_transparent_hugepage(void);
+
+static inline int pmd_trans_huge(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_HUGE);
+}
+
+static inline pmd_t pmd_mkhuge(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_HUGE;
+
+        return pmd;
+}
+
+extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                       pmd_t *pmdp, pmd_t pmd);
+
+#define pmd_write pmd_write
+static inline int pmd_write(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_WRITE);
+}
+
+static inline pmd_t pmd_wrprotect(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        return pmd;
+}
+
+static inline pmd_t pmd_mkwrite(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_WRITE;
+        if (pmd_val(pmd) & _PAGE_MODIFIED)
+                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
+
+        return pmd;
+}
+
+static inline int pmd_dirty(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_MODIFIED);
+}
+
+static inline pmd_t pmd_mkclean(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
+        return pmd;
+}
+
+static inline pmd_t pmd_mkdirty(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
+        if (pmd_val(pmd) & _PAGE_WRITE)
+                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
+
+        return pmd;
+}
+
+static inline int pmd_young(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_ACCESSED);
+}
+
+static inline pmd_t pmd_mkold(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+
+        return pmd;
+}
+
+static inline pmd_t pmd_mkyoung(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_ACCESSED;
+
+        if (!(pmd_val(pmd) & _PAGE_NO_READ))
+                pmd_val(pmd) |= _PAGE_SILENT_READ;
+
+        return pmd;
+}
+
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline int pmd_soft_dirty(pmd_t pmd)
+{
+        return !!(pmd_val(pmd) & _PAGE_SOFT_DIRTY);
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_SOFT_DIRTY;
+        return pmd;
+}
+
+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_SOFT_DIRTY);
+        return pmd;
+}
+
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
+/* Extern to avoid header file madness */
+extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
+
+static inline unsigned long pmd_pfn(pmd_t pmd)
+{
+        return pmd_val(pmd) >> _PFN_SHIFT;
+}
+
+static inline struct page *pmd_page(pmd_t pmd)
+{
+        if (pmd_trans_huge(pmd))
+                return pfn_to_page(pmd_pfn(pmd));
+
+        return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
+}
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        pmd_val(pmd) = (pmd_val(pmd) & (_PAGE_CHG_MASK | _PAGE_HUGE)) |
+                       (pgprot_val(newprot) & ~_PAGE_CHG_MASK);
+        return pmd;
+}
+
+static inline pmd_t pmd_mkinvalid(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
+
+        return pmd;
+}
+
+/*
+ * The generic version pmdp_huge_get_and_clear uses a version of pmd_clear() with a
+ * different prototype.
+ */
+#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
+static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
+                                            unsigned long address, pmd_t *pmdp)
+{
+        pmd_t old = *pmdp;
+
+        pmd_clear(pmdp);
+
+        return old;
+}
+
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
+#ifdef _PAGE_HUGE
+#define pmd_leaf(pmd)   ((pmd_val(pmd) & _PAGE_HUGE) != 0)
+#define pud_leaf(pud)   ((pud_val(pud) & _PAGE_HUGE) != 0)
+#endif
+
+#define gup_fast_permitted(start, end)  (!cpu_has_dc_aliases)
+
+/*
+ * We provide our own get_unmapped area to cope with the virtual aliasing
+ * constraints placed on us by the cache architecture.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+#endif /* _ASM_PGTABLE_H */
diff --git a/arch/mips/include/asm/pm-cps.h b/arch/mips/include/asm/pm-cps.h
new file mode 100644
index 000000000..efd96e919
--- /dev/null
+++ b/arch/mips/include/asm/pm-cps.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2014 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_PM_CPS_H__
+#define __MIPS_ASM_PM_CPS_H__
+
+/*
+ * The CM & CPC can only handle coherence & power control on a per-core basis,
+ * thus in an MT system the VP(E)s within each core are coupled and can only
+ * enter or exit states requiring CM or CPC assistance in unison.
+ */
+#if defined(CONFIG_CPU_MIPSR6)
+# define coupled_coherence cpu_has_vp
+#elif defined(CONFIG_MIPS_MT)
+# define coupled_coherence cpu_has_mipsmt
+#else
+# define coupled_coherence 0
+#endif
+
+/* Enumeration of possible PM states */
+enum cps_pm_state {
+        CPS_PM_NC_WAIT,         /* MIPS wait instruction, non-coherent */
+        CPS_PM_CLOCK_GATED,     /* Core clock gated */
+        CPS_PM_POWER_GATED,     /* Core power gated */
+        CPS_PM_STATE_COUNT,
+};
+
+/**
+ * cps_pm_support_state - determine whether the system supports a PM state
+ * @state: the state to test for support
+ *
+ * Returns true if the system supports the given state, otherwise false.
+ */
+extern bool cps_pm_support_state(enum cps_pm_state state);
+
+/**
+ * cps_pm_enter_state - enter a PM state
+ * @state: the state to enter
+ *
+ * Enter the given PM state. If coupled_coherence is non-zero then it is
+ * expected that this function be called at approximately the same time on
+ * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
+ */
+extern int cps_pm_enter_state(enum cps_pm_state state);
+
+#endif /* __MIPS_ASM_PM_CPS_H__ */
diff --git a/arch/mips/include/asm/pm.h b/arch/mips/include/asm/pm.h
new file mode 100644
index 000000000..10bb7b640
--- /dev/null
+++ b/arch/mips/include/asm/pm.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2014 Imagination Technologies Ltd
+ *
+ * PM helper macros for CPU power off (e.g. Suspend-to-RAM).
+ */
+
+#ifndef __ASM_PM_H
+#define __ASM_PM_H
+
+#ifdef __ASSEMBLY__
+
+#include <asm/asm-offsets.h>
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+/* Save CPU state to stack for suspend to RAM */
+.macro SUSPEND_SAVE_REGS
+        subu    sp, PT_SIZE
+        /* Call preserved GPRs */
+        LONG_S  $16, PT_R16(sp)
+        LONG_S  $17, PT_R17(sp)
+        LONG_S  $18, PT_R18(sp)
+        LONG_S  $19, PT_R19(sp)
+        LONG_S  $20, PT_R20(sp)
+        LONG_S  $21, PT_R21(sp)
+        LONG_S  $22, PT_R22(sp)
+        LONG_S  $23, PT_R23(sp)
+        LONG_S  $28, PT_R28(sp)
+        LONG_S  $30, PT_R30(sp)
+        LONG_S  $31, PT_R31(sp)
+        /* A couple of CP0 registers with space in pt_regs */
+        mfc0    k0, CP0_STATUS
+        LONG_S  k0, PT_STATUS(sp)
+.endm
+
+/* Restore CPU state from stack after resume from RAM */
+.macro RESUME_RESTORE_REGS_RETURN
+        .set    push
+        .set    noreorder
+        /* A couple of CP0 registers with space in pt_regs */
+        LONG_L  k0, PT_STATUS(sp)
+        mtc0    k0, CP0_STATUS
+        /* Call preserved GPRs */
+        LONG_L  $16, PT_R16(sp)
+        LONG_L  $17, PT_R17(sp)
+        LONG_L  $18, PT_R18(sp)
+        LONG_L  $19, PT_R19(sp)
+        LONG_L  $20, PT_R20(sp)
+        LONG_L  $21, PT_R21(sp)
+        LONG_L  $22, PT_R22(sp)
+        LONG_L  $23, PT_R23(sp)
+        LONG_L  $28, PT_R28(sp)
+        LONG_L  $30, PT_R30(sp)
+        LONG_L  $31, PT_R31(sp)
+        /* Pop and return */
+        jr      ra
+         addiu  sp, PT_SIZE
+        .set    pop
+.endm
+
+/* Get address of static suspend state into t1 */
+.macro LA_STATIC_SUSPEND
+        la      t1, mips_static_suspend_state
+.endm
+
+/* Save important CPU state for early restoration to global data */
+.macro SUSPEND_SAVE_STATIC
+#ifdef CONFIG_EVA
+        /*
+         * Segment configuration is saved in global data where it can be easily
+         * reloaded without depending on the segment configuration.
+         */
+        mfc0    k0, CP0_PAGEMASK, 2     /* SegCtl0 */
+        LONG_S  k0, SSS_SEGCTL0(t1)
+        mfc0    k0, CP0_PAGEMASK, 3     /* SegCtl1 */
+        LONG_S  k0, SSS_SEGCTL1(t1)
+        mfc0    k0, CP0_PAGEMASK, 4     /* SegCtl2 */
+        LONG_S  k0, SSS_SEGCTL2(t1)
+#endif
+        /* save stack pointer (pointing to GPRs) */
+        LONG_S  sp, SSS_SP(t1)
+.endm
+
+/* Restore important CPU state early from global data */
+.macro RESUME_RESTORE_STATIC
+#ifdef CONFIG_EVA
+        /*
+         * Segment configuration must be restored prior to any access to
+         * allocated memory, as it may reside outside of the legacy kernel
+         * segments.
+         */
+        LONG_L  k0, SSS_SEGCTL0(t1)
+        mtc0    k0, CP0_PAGEMASK, 2     /* SegCtl0 */
+        LONG_L  k0, SSS_SEGCTL1(t1)
+        mtc0    k0, CP0_PAGEMASK, 3     /* SegCtl1 */
+        LONG_L  k0, SSS_SEGCTL2(t1)
+        mtc0    k0, CP0_PAGEMASK, 4     /* SegCtl2 */
+        tlbw_use_hazard
+#endif
+        /* restore stack pointer (pointing to GPRs) */
+        LONG_L  sp, SSS_SP(t1)
+.endm
+
+/* flush caches to make sure context has reached memory */
+.macro SUSPEND_CACHE_FLUSH
+        .extern __wback_cache_all
+        .set    push
+        .set    noreorder
+        la      t1, __wback_cache_all
+        LONG_L  t0, 0(t1)
+        jalr    t0
+         nop
+        .set    pop
+ .endm
+
+/* Save suspend state and flush data caches to RAM */
+.macro SUSPEND_SAVE
+        SUSPEND_SAVE_REGS
+        LA_STATIC_SUSPEND
+        SUSPEND_SAVE_STATIC
+        SUSPEND_CACHE_FLUSH
+.endm
+
+/* Restore saved state after resume from RAM and return */
+.macro RESUME_RESTORE_RETURN
+        LA_STATIC_SUSPEND
+        RESUME_RESTORE_STATIC
+        RESUME_RESTORE_REGS_RETURN
+.endm
+
+#else /* __ASSEMBLY__ */
+
+/**
+ * struct mips_static_suspend_state - Core saved CPU state across S2R.
+ * @segctl:     CP0 Segment control registers.
+ * @sp:         Stack frame where GP register context is saved.
+ *
+ * This structure contains minimal CPU state that must be saved in static kernel
+ * data in order to be able to restore the rest of the state. This includes
+ * segmentation configuration in the case of EVA being enabled, as they must be
+ * restored prior to any kmalloc'd memory being referenced (even the stack
+ * pointer).
+ */
+struct mips_static_suspend_state {
+#ifdef CONFIG_EVA
+        unsigned long segctl[3];
+#endif
+        unsigned long sp;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_PM_HELPERS_H */
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h
new file mode 100644
index 000000000..a56594f36
--- /dev/null
+++ b/arch/mips/include/asm/prefetch.h
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_PREFETCH_H
+#define __ASM_PREFETCH_H
+
+
+/*
+ * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
+ * rather than wasting time we pretend these processors don't support
+ * prefetching at all.
+ *
+ * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
+ * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
+ *
+ * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
+ *
+ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
+ * Pref_PrepareForStore also.
+ *
+ * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
+ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
+ * current versions due to erratum G105.
+ *
+ * VR5500 (including VR5701 and VR7701) only implement load prefetch.
+ *
+ * Finally MIPS32 and MIPS64 implement all of the following hints.
+ */
+
+#define Pref_Load                       0
+#define Pref_Store                      1
+                                                /* 2 and 3 are reserved */
+#define Pref_LoadStreamed               4
+#define Pref_StoreStreamed              5
+#define Pref_LoadRetained               6
+#define Pref_StoreRetained              7
+                                                /* 8 ... 24 are reserved */
+#define Pref_WriteBackInvalidate        25
+#define Pref_PrepareForStore            30
+
+#ifdef __ASSEMBLY__
+
+        .macro  __pref hint addr
+#ifdef CONFIG_CPU_HAS_PREFETCH
+        pref    \hint, \addr
+#endif
+        .endm
+
+        .macro  pref_load addr
+        __pref  Pref_Load, \addr
+        .endm
+
+        .macro  pref_store addr
+        __pref  Pref_Store, \addr
+        .endm
+
+        .macro  pref_load_streamed addr
+        __pref  Pref_LoadStreamed, \addr
+        .endm
+
+        .macro  pref_store_streamed addr
+        __pref  Pref_StoreStreamed, \addr
+        .endm
+
+        .macro  pref_load_retained addr
+        __pref  Pref_LoadRetained, \addr
+        .endm
+
+        .macro  pref_store_retained addr
+        __pref  Pref_StoreRetained, \addr
+        .endm
+
+        .macro  pref_wback_inv addr
+        __pref  Pref_WriteBackInvalidate, \addr
+        .endm
+
+        .macro  pref_prepare_for_store addr
+        __pref  Pref_PrepareForStore, \addr
+        .endm
+
+#endif
+
+#endif /* __ASM_PREFETCH_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
new file mode 100644
index 000000000..7834e7c0c
--- /dev/null
+++ b/arch/mips/include/asm/processor.h
@@ -0,0 +1,425 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <linux/atomic.h>
+#include <linux/cpumask.h>
+#include <linux/sizes.h>
+#include <linux/threads.h>
+
+#include <asm/cachectl.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <asm/dsemul.h>
+#include <asm/mipsregs.h>
+#include <asm/prefetch.h>
+#include <asm/vdso/processor.h>
+
+/*
+ * System setup and hardware flags..
+ */
+
+extern unsigned int vced_count, vcei_count;
+extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+/* User space process size is limited to 1GB in KVM Guest Mode */
+#define TASK_SIZE       0x3fff8000UL
+#else
+/*
+ * User space process size: 2GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE       0x80000000UL
+#endif
+
+#define STACK_TOP_MAX   TASK_SIZE
+
+#define TASK_IS_32BIT_ADDR 1
+
+#endif
+
+#ifdef CONFIG_64BIT
+/*
+ * User space process size: 1TB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.  TASK_SIZE
+ * is limited to 1TB by the R4000 architecture; R10000 and better can
+ * support 16TB; the architectural reserve for future expansion is
+ * 8192EB ...
+ */
+#define TASK_SIZE32     0x7fff8000UL
+#ifdef CONFIG_MIPS_VA_BITS_48
+#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
+#else
+#define TASK_SIZE64     0x10000000000UL
+#endif
+#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+#define STACK_TOP_MAX   TASK_SIZE64
+
+#define TASK_SIZE_OF(tsk)                                               \
+        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+
+#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
+
+#endif
+
+#define VDSO_RANDOMIZE_SIZE     (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
+
+extern unsigned long mips_stack_top(void);
+#define STACK_TOP               mips_stack_top()
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
+
+#define NUM_FPU_REGS    32
+
+#ifdef CONFIG_CPU_HAS_MSA
+# define FPU_REG_WIDTH  128
+#else
+# define FPU_REG_WIDTH  64
+#endif
+
+union fpureg {
+        __u32   val32[FPU_REG_WIDTH / 32];
+        __u64   val64[FPU_REG_WIDTH / 64];
+};
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+# define FPR_IDX(width, idx)    (idx)
+#else
+# define FPR_IDX(width, idx)    ((idx) ^ ((64 / (width)) - 1))
+#endif
+
+#define BUILD_FPR_ACCESS(width) \
+static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
+{                                                                       \
+        return fpr->val##width[FPR_IDX(width, idx)];                    \
+}                                                                       \
+                                                                        \
+static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
+                                  u##width val)                         \
+{                                                                       \
+        fpr->val##width[FPR_IDX(width, idx)] = val;                     \
+}
+
+BUILD_FPR_ACCESS(32)
+BUILD_FPR_ACCESS(64)
+
+/*
+ * It would be nice to add some more fields for emulator statistics,
+ * the additional information is private to the FPU emulator for now.
+ * See arch/mips/include/asm/fpu_emulator.h.
+ */
+
+struct mips_fpu_struct {
+        union fpureg    fpr[NUM_FPU_REGS];
+        unsigned int    fcr31;
+        unsigned int    msacsr;
+};
+
+#define NUM_DSP_REGS   6
+
+typedef unsigned long dspreg_t;
+
+struct mips_dsp_state {
+        dspreg_t        dspr[NUM_DSP_REGS];
+        unsigned int    dspcontrol;
+};
+
+#define INIT_CPUMASK { \
+        {0,} \
+}
+
+struct mips3264_watch_reg_state {
+        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
+           64 bit kernel.  We use unsigned long as it has the same
+           property. */
+        unsigned long watchlo[NUM_WATCH_REGS];
+        /* Only the mask and IRW bits from watchhi. */
+        u16 watchhi[NUM_WATCH_REGS];
+};
+
+union mips_watch_reg_state {
+        struct mips3264_watch_reg_state mips3264;
+};
+
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
+
+struct octeon_cop2_state {
+        /* DMFC2 rt, 0x0201 */
+        unsigned long   cop2_crc_iv;
+        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
+        unsigned long   cop2_crc_length;
+        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
+        unsigned long   cop2_crc_poly;
+        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
+        unsigned long   cop2_llm_dat[2];
+       /* DMFC2 rt, 0x0084 */
+        unsigned long   cop2_3des_iv;
+        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
+        unsigned long   cop2_3des_key[3];
+        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
+        unsigned long   cop2_3des_result;
+        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
+        unsigned long   cop2_aes_inp0;
+        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
+        unsigned long   cop2_aes_iv[2];
+        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
+         * rt, 0x0107 */
+        unsigned long   cop2_aes_key[4];
+        /* DMFC2 rt, 0x0110 */
+        unsigned long   cop2_aes_keylen;
+        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
+        unsigned long   cop2_aes_result[2];
+        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
+         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
+         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
+         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
+         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
+        unsigned long   cop2_hsh_datw[15];
+        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
+         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
+         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
+        unsigned long   cop2_hsh_ivw[8];
+        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
+        unsigned long   cop2_gfm_mult[2];
+        /* DMFC2 rt, 0x025E - Pass2 */
+        unsigned long   cop2_gfm_poly;
+        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
+        unsigned long   cop2_gfm_result[2];
+        /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
+        unsigned long   cop2_sha3[2];
+};
+#define COP2_INIT                                               \
+        .cp2                    = {0,},
+
+struct octeon_cvmseg_state {
+        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
+                            [cpu_dcache_line_size() / sizeof(unsigned long)];
+};
+
+#elif defined(CONFIG_CPU_XLP)
+struct nlm_cop2_state {
+        u64     rx[4];
+        u64     tx[4];
+        u32     tx_msg_status;
+        u32     rx_msg_status;
+};
+
+#define COP2_INIT                                               \
+        .cp2                    = {{0}, {0}, 0, 0},
+#else
+#define COP2_INIT
+#endif
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#ifdef CONFIG_CPU_HAS_MSA
+# define ARCH_MIN_TASKALIGN     16
+# define FPU_ALIGN              __aligned(16)
+#else
+# define ARCH_MIN_TASKALIGN     8
+# define FPU_ALIGN
+#endif
+
+struct mips_abi;
+
+/*
+ * If you change thread_struct remember to change the #defines below too!
+ */
+struct thread_struct {
+        /* Saved main processor registers. */
+        unsigned long reg16;
+        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+        unsigned long reg29, reg30, reg31;
+
+        /* Saved cp0 stuff. */
+        unsigned long cp0_status;
+
+#ifdef CONFIG_MIPS_FP_SUPPORT
+        /* Saved fpu/fpu emulator stuff. */
+        struct mips_fpu_struct fpu FPU_ALIGN;
+        /* Assigned branch delay slot 'emulation' frame */
+        atomic_t bd_emu_frame;
+        /* PC of the branch from a branch delay slot 'emulation' */
+        unsigned long bd_emu_branch_pc;
+        /* PC to continue from following a branch delay slot 'emulation' */
+        unsigned long bd_emu_cont_pc;
+#endif
+#ifdef CONFIG_MIPS_MT_FPAFF
+        /* Emulated instruction count */
+        unsigned long emulated_fp;
+        /* Saved per-thread scheduler affinity mask */
+        cpumask_t user_cpus_allowed;
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+        /* Saved state of the DSP ASE, if available. */
+        struct mips_dsp_state dsp;
+
+        /* Saved watch register state, if available. */
+        union mips_watch_reg_state watch;
+
+        /* Other stuff associated with the thread. */
+        unsigned long cp0_badvaddr;     /* Last user fault */
+        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
+        unsigned long error_code;
+        unsigned long trap_nr;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
+        struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+#endif
+#ifdef CONFIG_CPU_XLP
+        struct nlm_cop2_state cp2;
+#endif
+        struct mips_abi *abi;
+};
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+#define FPAFF_INIT                                              \
+        .emulated_fp                    = 0,                    \
+        .user_cpus_allowed              = INIT_CPUMASK,
+#else
+#define FPAFF_INIT
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+#ifdef CONFIG_MIPS_FP_SUPPORT
+# define FPU_INIT                                               \
+        .fpu                    = {                             \
+                .fpr            = {{{0,},},},                   \
+                .fcr31          = 0,                            \
+                .msacsr         = 0,                            \
+        },                                                      \
+        /* Delay slot emulation */                              \
+        .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),          \
+        .bd_emu_branch_pc = 0,                                  \
+        .bd_emu_cont_pc = 0,
+#else
+# define FPU_INIT
+#endif
+
+#define INIT_THREAD  {                                          \
+        /*                                                      \
+         * Saved main processor registers                       \
+         */                                                     \
+        .reg16                  = 0,                            \
+        .reg17                  = 0,                            \
+        .reg18                  = 0,                            \
+        .reg19                  = 0,                            \
+        .reg20                  = 0,                            \
+        .reg21                  = 0,                            \
+        .reg22                  = 0,                            \
+        .reg23                  = 0,                            \
+        .reg29                  = 0,                            \
+        .reg30                  = 0,                            \
+        .reg31                  = 0,                            \
+        /*                                                      \
+         * Saved cp0 stuff                                      \
+         */                                                     \
+        .cp0_status             = 0,                            \
+        /*                                                      \
+         * Saved FPU/FPU emulator stuff                         \
+         */                                                     \
+        FPU_INIT                                                \
+        /*                                                      \
+         * FPU affinity state (null if not FPAFF)               \
+         */                                                     \
+        FPAFF_INIT                                              \
+        /*                                                      \
+         * Saved DSP stuff                                      \
+         */                                                     \
+        .dsp                    = {                             \
+                .dspr           = {0, },                        \
+                .dspcontrol     = 0,                            \
+        },                                                      \
+        /*                                                      \
+         * saved watch register stuff                           \
+         */                                                     \
+        .watch = {{{0,},},},                                    \
+        /*                                                      \
+         * Other stuff associated with the process              \
+         */                                                     \
+        .cp0_badvaddr           = 0,                            \
+        .cp0_baduaddr           = 0,                            \
+        .error_code             = 0,                            \
+        .trap_nr                = 0,                            \
+        /*                                                      \
+         * Platform specific cop2 registers(null if no COP2)    \
+         */                                                     \
+        COP2_INIT                                               \
+}
+
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
+
+static inline void flush_thread(void)
+{
+}
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
+                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
+#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
+#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
+#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
+#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
+
+/*
+ * Return_address is a replacement for __builtin_return_address(count)
+ * which on certain architectures cannot reasonably be implemented in GCC
+ * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
+ * aborts compilation on some CPUs.  It's simply not possible to unwind
+ * some CPU's stackframes.
+ *
+ * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * overhead of a function call by forcing the compiler to save the return
+ * address register on the stack.
+ */
+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
+
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+#define prefetch(x) __builtin_prefetch((x), 0, 1)
+
+#define ARCH_HAS_PREFETCHW
+#define prefetchw(x) __builtin_prefetch((x), 1, 1)
+
+#endif
+
+/*
+ * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
+ * to the prctl syscall.
+ */
+extern int mips_get_process_fp_mode(struct task_struct *task);
+extern int mips_set_process_fp_mode(struct task_struct *task,
+                                    unsigned int value);
+
+#define GET_FP_MODE(task)               mips_get_process_fp_mode(task)
+#define SET_FP_MODE(task,value)         mips_set_process_fp_mode(task, value)
+
+#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
new file mode 100644
index 000000000..c42e07671
--- /dev/null
+++ b/arch/mips/include/asm/prom.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *  arch/mips/include/asm/prom.h
+ *
+ *  Copyright (C) 2010 Cisco Systems Inc. <dediao@cisco.com>
+ */
+#ifndef __ASM_PROM_H
+#define __ASM_PROM_H
+
+#ifdef CONFIG_USE_OF
+#include <linux/bug.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <asm/bootinfo.h>
+
+extern void device_tree_init(void);
+
+struct boot_param_header;
+
+extern void __dt_setup_arch(void *bph);
+extern int __dt_register_buses(const char *bus0, const char *bus1);
+
+#else /* CONFIG_OF */
+static inline void device_tree_init(void) { }
+#endif /* CONFIG_OF */
+
+extern char *mips_get_machine_name(void);
+extern void mips_set_machine_name(const char *name);
+
+#endif /* __ASM_PROM_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
new file mode 100644
index 000000000..1e76774b3
--- /dev/null
+++ b/arch/mips/include/asm/ptrace.h
@@ -0,0 +1,189 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <asm/isadep.h>
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <uapi/asm/ptrace.h>
+
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ *
+ * If you add a register here, also add it to regoffset_table[] in
+ * arch/mips/kernel/ptrace.c.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+        /* Pad bytes for argument save space on the stack. */
+        unsigned long pad0[8];
+#endif
+
+        /* Saved main processor registers. */
+        unsigned long regs[32];
+
+        /* Saved special registers. */
+        unsigned long cp0_status;
+        unsigned long hi;
+        unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+        unsigned long acx;
+#endif
+        unsigned long cp0_badvaddr;
+        unsigned long cp0_cause;
+        unsigned long cp0_epc;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        unsigned long long mpl[6];        /* MTM{0-5} */
+        unsigned long long mtp[6];        /* MTP{0-5} */
+#endif
+        unsigned long __last[0];
+} __aligned(8);
+
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+        return regs->regs[31];
+}
+
+static inline void instruction_pointer_set(struct pt_regs *regs,
+                                           unsigned long val)
+{
+        regs->cp0_epc = val;
+}
+
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:       pt_regs from which register value is gotten.
+ * @offset:     offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                              unsigned int offset)
+{
+        if (unlikely(offset > MAX_REG_OFFSET))
+                return 0;
+
+        return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @addr:       address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+static inline int regs_within_kernel_stack(struct pt_regs *regs,
+                                           unsigned long addr)
+{
+        return ((addr & ~(THREAD_SIZE - 1))  ==
+                (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @n:          stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                                      unsigned int n)
+{
+        unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+
+        addr += n;
+        if (regs_within_kernel_stack(regs, (unsigned long)addr))
+                return *addr;
+        else
+                return 0;
+}
+
+struct task_struct;
+
+extern int ptrace_getregs(struct task_struct *child,
+        struct user_pt_regs __user *data);
+extern int ptrace_setregs(struct task_struct *child,
+        struct user_pt_regs __user *data);
+
+extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
+extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
+
+extern int ptrace_get_watch_regs(struct task_struct *child,
+        struct pt_watch_regs __user *addr);
+extern int ptrace_set_watch_regs(struct task_struct *child,
+        struct pt_watch_regs __user *addr);
+
+/*
+ * Does the process account for user or for system time?
+ */
+#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
+
+static inline int is_syscall_success(struct pt_regs *regs)
+{
+        return !regs->regs[7];
+}
+
+static inline long regs_return_value(struct pt_regs *regs)
+{
+        if (is_syscall_success(regs) || !user_mode(regs))
+                return regs->regs[2];
+        else
+                return -regs->regs[2];
+}
+
+#define instruction_pointer(regs) ((regs)->cp0_epc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+extern asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall);
+extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
+
+extern void die(const char *, struct pt_regs *) __noreturn;
+
+static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+{
+        if (unlikely(!user_mode(regs)))
+                die(str, regs);
+}
+
+#define current_pt_regs()                                               \
+({                                                                      \
+        unsigned long sp = (unsigned long)__builtin_frame_address(0);   \
+        (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1;      \
+})
+
+/* Helpers for working with the user stack pointer */
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+        return regs->regs[29];
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+        unsigned long val)
+{
+        regs->regs[29] = val;
+}
+
+#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
new file mode 100644
index 000000000..6e7361629
--- /dev/null
+++ b/arch/mips/include/asm/r4k-timer.h
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_R4K_TIMER_H
+#define __ASM_R4K_TIMER_H
+
+#include <linux/compiler.h>
+
+#ifdef CONFIG_SYNC_R4K
+
+extern void synchronise_count_master(int cpu);
+extern void synchronise_count_slave(int cpu);
+
+#else
+
+static inline void synchronise_count_master(int cpu)
+{
+}
+
+static inline void synchronise_count_slave(int cpu)
+{
+}
+
+#endif
+
+#endif /* __ASM_R4K_TIMER_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
new file mode 100644
index 000000000..15ab16f99
--- /dev/null
+++ b/arch/mips/include/asm/r4kcache.h
@@ -0,0 +1,379 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Inline assembly cache operations.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_R4KCACHE_H
+#define _ASM_R4KCACHE_H
+
+#include <linux/stringify.h>
+
+#include <asm/asm.h>
+#include <asm/asm-eva.h>
+#include <asm/cacheops.h>
+#include <asm/compiler.h>
+#include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
+#include <asm/mipsmtregs.h>
+#include <asm/mmzone.h>
+#include <asm/unroll.h>
+#include <linux/uaccess.h> /* for uaccess_kernel() */
+
+extern void (*r4k_blast_dcache)(void);
+extern void (*r4k_blast_icache)(void);
+
+/*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations.  Two issues here:
+ *
+ *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
+ *    the index bits from the virtual address.  This breaks with tradition
+ *    set by the R4000.  To keep unpleasant surprises from happening we pick
+ *    an address in KSEG0 / CKSEG0.
+ *  - We need a properly sign extended address for 64-bit code.  To get away
+ *    without ifdefs we let the compiler do it by a type cast.
+ */
+#define INDEX_BASE      CKSEG0
+
+#define _cache_op(insn, op, addr)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noreorder                               \n"     \
+        "       .set "MIPS_ISA_ARCH_LEVEL"                      \n"     \
+        "       " insn("%0", "%1") "                            \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#define cache_op(op, addr)                                              \
+        _cache_op(kernel_cache, op, addr)
+
+static inline void flush_icache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Invalidate_I, addr);
+}
+
+static inline void flush_dcache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Writeback_Inv_D, addr);
+}
+
+static inline void flush_scache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Writeback_Inv_SD, addr);
+}
+
+static inline void flush_icache_line(unsigned long addr)
+{
+        switch (boot_cpu_type()) {
+        case CPU_LOONGSON2EF:
+                cache_op(Hit_Invalidate_I_Loongson2, addr);
+                break;
+
+        default:
+                cache_op(Hit_Invalidate_I, addr);
+                break;
+        }
+}
+
+static inline void flush_dcache_line(unsigned long addr)
+{
+        cache_op(Hit_Writeback_Inv_D, addr);
+}
+
+static inline void invalidate_dcache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_D, addr);
+}
+
+static inline void invalidate_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_SD, addr);
+}
+
+static inline void flush_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Writeback_Inv_SD, addr);
+}
+
+#define protected_cache_op(op,addr)                             \
+({                                                              \
+        int __err = 0;                                          \
+        __asm__ __volatile__(                                   \
+        "       .set    push                    \n"             \
+        "       .set    noreorder               \n"             \
+        "       .set "MIPS_ISA_ARCH_LEVEL"      \n"             \
+        "1:     cache   %1, (%2)                \n"             \
+        "2:     .insn                           \n"             \
+        "       .set    pop                     \n"             \
+        "       .section .fixup,\"ax\"          \n"             \
+        "3:     li      %0, %3                  \n"             \
+        "       j       2b                      \n"             \
+        "       .previous                       \n"             \
+        "       .section __ex_table,\"a\"       \n"             \
+        "       "STR(PTR)" 1b, 3b               \n"             \
+        "       .previous"                                      \
+        : "+r" (__err)                                          \
+        : "i" (op), "r" (addr), "i" (-EFAULT));                 \
+        __err;                                                  \
+})
+
+
+#define protected_cachee_op(op,addr)                            \
+({                                                              \
+        int __err = 0;                                          \
+        __asm__ __volatile__(                                   \
+        "       .set    push                    \n"             \
+        "       .set    noreorder               \n"             \
+        "       .set    mips0                   \n"             \
+        "       .set    eva                     \n"             \
+        "1:     cachee  %1, (%2)                \n"             \
+        "2:     .insn                           \n"             \
+        "       .set    pop                     \n"             \
+        "       .section .fixup,\"ax\"          \n"             \
+        "3:     li      %0, %3                  \n"             \
+        "       j       2b                      \n"             \
+        "       .previous                       \n"             \
+        "       .section __ex_table,\"a\"       \n"             \
+        "       "STR(PTR)" 1b, 3b               \n"             \
+        "       .previous"                                      \
+        : "+r" (__err)                                          \
+        : "i" (op), "r" (addr), "i" (-EFAULT));                 \
+        __err;                                                  \
+})
+
+/*
+ * The next two are for badland addresses like signal trampolines.
+ */
+static inline int protected_flush_icache_line(unsigned long addr)
+{
+        switch (boot_cpu_type()) {
+        case CPU_LOONGSON2EF:
+                return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+
+        default:
+#ifdef CONFIG_EVA
+                return protected_cachee_op(Hit_Invalidate_I, addr);
+#else
+                return protected_cache_op(Hit_Invalidate_I, addr);
+#endif
+        }
+}
+
+/*
+ * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
+ * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
+ * caches.  We're talking about one cacheline unnecessarily getting invalidated
+ * here so the penalty isn't overly hard.
+ */
+static inline int protected_writeback_dcache_line(unsigned long addr)
+{
+#ifdef CONFIG_EVA
+        return protected_cachee_op(Hit_Writeback_Inv_D, addr);
+#else
+        return protected_cache_op(Hit_Writeback_Inv_D, addr);
+#endif
+}
+
+static inline int protected_writeback_scache_line(unsigned long addr)
+{
+#ifdef CONFIG_EVA
+        return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
+#else
+        return protected_cache_op(Hit_Writeback_Inv_SD, addr);
+#endif
+}
+
+/*
+ * This one is RM7000-specific
+ */
+static inline void invalidate_tcache_page(unsigned long addr)
+{
+        cache_op(Page_Invalidate_T, addr);
+}
+
+#define cache_unroll(times, insn, op, addr, lsize) do {                 \
+        int i = 0;                                                      \
+        unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));   \
+} while (0)
+
+/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)    \
+static inline void extra##blast_##pfx##cache##lsize(void)               \
+{                                                                       \
+        unsigned long start = INDEX_BASE;                               \
+        unsigned long end = start + current_cpu_data.desc.waysize;      \
+        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
+        unsigned long ws_end = current_cpu_data.desc.ways <<            \
+                               current_cpu_data.desc.waybit;            \
+        unsigned long ws, addr;                                         \
+                                                                        \
+        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
+                for (addr = start; addr < end; addr += lsize * 32)      \
+                        cache_unroll(32, kernel_cache, indexop,         \
+                                     addr | ws, lsize);                 \
+}                                                                       \
+                                                                        \
+static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
+{                                                                       \
+        unsigned long start = page;                                     \
+        unsigned long end = page + PAGE_SIZE;                           \
+                                                                        \
+        do {                                                            \
+                cache_unroll(32, kernel_cache, hitop, start, lsize);    \
+                start += lsize * 32;                                    \
+        } while (start < end);                                          \
+}                                                                       \
+                                                                        \
+static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
+{                                                                       \
+        unsigned long indexmask = current_cpu_data.desc.waysize - 1;    \
+        unsigned long start = INDEX_BASE + (page & indexmask);          \
+        unsigned long end = start + PAGE_SIZE;                          \
+        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
+        unsigned long ws_end = current_cpu_data.desc.ways <<            \
+                               current_cpu_data.desc.waybit;            \
+        unsigned long ws, addr;                                         \
+                                                                        \
+        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
+                for (addr = start; addr < end; addr += lsize * 32)      \
+                        cache_unroll(32, kernel_cache, indexop,         \
+                                     addr | ws, lsize);                 \
+}
+
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+
+#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
+{                                                                       \
+        unsigned long start = page;                                     \
+        unsigned long end = page + PAGE_SIZE;                           \
+                                                                        \
+        do {                                                            \
+                cache_unroll(32, user_cache, hitop, start, lsize);      \
+                start += lsize * 32;                                    \
+        } while (start < end);                                          \
+}
+
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         16)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         32)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         64)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+
+/* build blast_xxx_range, protected_blast_xxx_range */
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)        \
+static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
+                                                    unsigned long end)  \
+{                                                                       \
+        unsigned long lsize = cpu_##desc##_line_size();                 \
+        unsigned long addr = start & ~(lsize - 1);                      \
+        unsigned long aend = (end - 1) & ~(lsize - 1);                  \
+                                                                        \
+        while (1) {                                                     \
+                prot##cache_op(hitop, addr);                            \
+                if (addr == aend)                                       \
+                        break;                                          \
+                addr += lsize;                                          \
+        }                                                               \
+}
+
+#ifndef CONFIG_EVA
+
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+
+#else
+
+#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop)                \
+static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
+                                                        unsigned long end) \
+{                                                                       \
+        unsigned long lsize = cpu_##desc##_line_size();                 \
+        unsigned long addr = start & ~(lsize - 1);                      \
+        unsigned long aend = (end - 1) & ~(lsize - 1);                  \
+                                                                        \
+        if (!uaccess_kernel()) {                                        \
+                while (1) {                                             \
+                        protected_cachee_op(hitop, addr);               \
+                        if (addr == aend)                               \
+                                break;                                  \
+                        addr += lsize;                                  \
+                }                                                       \
+        } else {                                                        \
+                while (1) {                                             \
+                        protected_cache_op(hitop, addr);                \
+                        if (addr == aend)                               \
+                                break;                                  \
+                        addr += lsize;                                  \
+                }                                                       \
+                                                                        \
+        }                                                               \
+}
+
+__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
+
+#endif
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+        protected_, loongson2_)
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
+/* blast_inv_dcache_range */
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
+
+/* Currently, this is very specific to Loongson-3 */
+#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)      \
+static inline void blast_##pfx##cache##lsize##_node(long node)          \
+{                                                                       \
+        unsigned long start = CAC_BASE | nid_to_addrbase(node);         \
+        unsigned long end = start + current_cpu_data.desc.waysize;      \
+        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
+        unsigned long ws_end = current_cpu_data.desc.ways <<            \
+                               current_cpu_data.desc.waybit;            \
+        unsigned long ws, addr;                                         \
+                                                                        \
+        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
+                for (addr = start; addr < end; addr += lsize * 32)      \
+                        cache_unroll(32, kernel_cache, indexop,         \
+                                     addr | ws, lsize);                 \
+}
+
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+
+#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h
new file mode 100644
index 000000000..e48c0bfab
--- /dev/null
+++ b/arch/mips/include/asm/reboot.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void (*_machine_restart)(char *command);
+extern void (*_machine_halt)(void);
+
+#endif /* _ASM_REBOOT_H */
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
new file mode 100644
index 000000000..84dc7e2e2
--- /dev/null
+++ b/arch/mips/include/asm/reg.h
@@ -0,0 +1 @@
+#include <uapi/asm/reg.h>
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
new file mode 100644
index 000000000..3c687df1d
--- /dev/null
+++ b/arch/mips/include/asm/regdef.h
@@ -0,0 +1,106 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+#define zero    $0      /* wired zero */
+#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
+#define v0      $2      /* return value */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8      /* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define ta0     $12
+#define t5      $13
+#define ta1     $13
+#define t6      $14
+#define ta2     $14
+#define t7      $15
+#define ta3     $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define zero    $0      /* wired zero */
+#define AT      $at     /* assembler temp - uppercase because of ".set at" */
+#define v0      $2      /* return value - caller saved */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define a4      $8      /* arg reg 64 bit; caller saved in 32 bit */
+#define ta0     $8
+#define a5      $9
+#define ta1     $9
+#define a6      $10
+#define ta2     $10
+#define a7      $11
+#define ta3     $11
+#define t0      $12     /* caller saved */
+#define t1      $13
+#define t2      $14
+#define t3      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25     /* callee address for PIC/temp */
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel temporary */
+#define k1      $27
+#define gp      $28     /* global pointer - caller saved for PIC */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* callee saved */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_REGDEF_H */
diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
new file mode 100644
index 000000000..c10206548
--- /dev/null
+++ b/arch/mips/include/asm/rtlx.h
@@ -0,0 +1,88 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#ifndef __ASM_RTLX_H_
+#define __ASM_RTLX_H_
+
+#include <irq.h>
+
+#define RTLX_MODULE_NAME "rtlx"
+
+#define LX_NODE_BASE 10
+
+#define MIPS_CPU_RTLX_IRQ 0
+
+#define RTLX_VERSION 2
+#define RTLX_xID 0x12345600
+#define RTLX_ID (RTLX_xID | RTLX_VERSION)
+#define RTLX_BUFFER_SIZE 2048
+#define RTLX_CHANNELS 8
+
+#define RTLX_CHANNEL_STDIO      0
+#define RTLX_CHANNEL_DBG        1
+#define RTLX_CHANNEL_SYSIO      2
+
+void rtlx_starting(int vpe);
+void rtlx_stopping(int vpe);
+
+int rtlx_open(int index, int can_sleep);
+int rtlx_release(int index);
+ssize_t rtlx_read(int index, void __user *buff, size_t count);
+ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
+unsigned int rtlx_read_poll(int index, int can_sleep);
+unsigned int rtlx_write_poll(int index);
+
+int __init rtlx_module_init(void);
+void __exit rtlx_module_exit(void);
+
+void _interrupt_sp(void);
+
+extern struct vpe_notifications rtlx_notify;
+extern const struct file_operations rtlx_fops;
+extern void (*aprp_hook)(void);
+
+enum rtlx_state {
+        RTLX_STATE_UNUSED = 0,
+        RTLX_STATE_INITIALISED,
+        RTLX_STATE_REMOTE_READY,
+        RTLX_STATE_OPENED
+};
+
+extern struct chan_waitqueues {
+        wait_queue_head_t rt_queue;
+        wait_queue_head_t lx_queue;
+        atomic_t in_open;
+        struct mutex mutex;
+} channel_wqs[RTLX_CHANNELS];
+
+/* each channel supports read and write.
+   linux (vpe0) reads lx_buffer and writes rt_buffer
+   SP (vpe1) reads rt_buffer and writes lx_buffer
+*/
+struct rtlx_channel {
+        enum rtlx_state rt_state;
+        enum rtlx_state lx_state;
+
+        int buffer_size;
+
+        /* read and write indexes per buffer */
+        int rt_write, rt_read;
+        char *rt_buffer;
+
+        int lx_write, lx_read;
+        char *lx_buffer;
+};
+
+extern struct rtlx_info {
+        unsigned long id;
+        enum rtlx_state state;
+        int ap_int_pending;     /* Status of 0 or 1 for CONFIG_MIPS_CMP only */
+
+        struct rtlx_channel channel[RTLX_CHANNELS];
+} *rtlx;
+#endif /* __ASM_RTLX_H_ */
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
new file mode 100644
index 000000000..aa809589a
--- /dev/null
+++ b/arch/mips/include/asm/seccomp.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#ifdef CONFIG_COMPAT
+static inline const int *get_compat_mode1_syscalls(void)
+{
+        static const int syscalls_O32[] = {
+                __NR_O32_Linux + 3, __NR_O32_Linux + 4,
+                __NR_O32_Linux + 1, __NR_O32_Linux + 193,
+                -1, /* negative terminated */
+        };
+        static const int syscalls_N32[] = {
+                __NR_N32_Linux + 0, __NR_N32_Linux + 1,
+                __NR_N32_Linux + 58, __NR_N32_Linux + 211,
+                -1, /* negative terminated */
+        };
+
+        if (IS_ENABLED(CONFIG_MIPS32_O32) && test_thread_flag(TIF_32BIT_REGS))
+                return syscalls_O32;
+
+        if (IS_ENABLED(CONFIG_MIPS32_N32))
+                return syscalls_N32;
+
+        BUG();
+}
+
+#define get_compat_mode1_syscalls get_compat_mode1_syscalls
+
+#endif /* CONFIG_COMPAT */
+
+#include <asm-generic/seccomp.h>
+
+#endif /* __ASM_SECCOMP_H */
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
new file mode 100644
index 000000000..8c56b862f
--- /dev/null
+++ b/arch/mips/include/asm/setup.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MIPS_SETUP_H
+#define _MIPS_SETUP_H
+
+#include <linux/types.h>
+#include <uapi/asm/setup.h>
+
+extern void prom_putchar(char);
+extern void setup_early_printk(void);
+
+#ifdef CONFIG_EARLY_PRINTK_8250
+extern void setup_8250_early_printk_port(unsigned long base,
+        unsigned int reg_shift, unsigned int timeout);
+#else
+static inline void setup_8250_early_printk_port(unsigned long base,
+        unsigned int reg_shift, unsigned int timeout) {}
+#endif
+
+void set_handler(unsigned long offset, const void *addr, unsigned long len);
+extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
+
+typedef void (*vi_handler_t)(void);
+extern void *set_vi_handler(int n, vi_handler_t addr);
+
+extern void *set_except_vector(int n, void *addr);
+extern unsigned long ebase;
+extern unsigned int hwrena;
+extern void per_cpu_trap_init(bool);
+extern void cpu_cache_init(void);
+
+#endif /* __SETUP_H */
diff --git a/arch/mips/include/asm/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h
new file mode 100644
index 000000000..24be2b425
--- /dev/null
+++ b/arch/mips/include/asm/sgi/gio.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * gio.h: Definitions for SGI GIO bus
+ *
+ * Copyright (C) 2002 Ladislav Michl
+ */
+
+#ifndef _SGI_GIO_H
+#define _SGI_GIO_H
+
+/*
+ * GIO bus addresses
+ *
+ * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
+ * three physical connectors, but only two slots, GFX and EXP0.
+ *
+ * There is 10MB of GIO address space for GIO64 slot devices
+ * slot#   slot type address range            size
+ * -----   --------- ----------------------- -----
+ *   0     GFX       0x1f000000 - 0x1f3fffff   4MB
+ *   1     EXP0      0x1f400000 - 0x1f5fffff   2MB
+ *   2     EXP1      0x1f600000 - 0x1f9fffff   4MB
+ *
+ * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
+ * into the HPC address space.
+ *   -     MISC      0x1fb00000 - 0x1fbfffff   1MB
+ *
+ * Following space is reserved and unused
+ *   -     RESERVED  0x18000000 - 0x1effffff 112MB
+ *
+ * GIO bus IDs
+ *
+ * Each GIO bus device identifies itself to the system by answering a
+ * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
+ * than 128 are 8 bits long, with the most significant 24 bits read from
+ * the slot undefined.
+ *
+ * 32-bit IDs are divided into
+ *      bits 0:6        the product ID; ranges from 0x00 to 0x7F.
+ *      bit 7           0=GIO Product ID is 8 bits wide
+ *                      1=GIO Product ID is 32 bits wide.
+ *      bits 8:15       manufacturer version for the product.
+ *      bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
+ *      bit 17          0=no ROM present
+ *                      1=ROM present on this board AND next three words
+ *                      space define the ROM.
+ *      bits 18:31      up to manufacturer.
+ *
+ * IDs above 0x50/0xd0 are of 3rd party boards.
+ *
+ * 8-bit IDs
+ *      0x01            XPI low cost FDDI
+ *      0x02            GTR TokenRing
+ *      0x04            Synchronous ISDN
+ *      0x05            ATM board [*]
+ *      0x06            Canon Interface
+ *      0x07            16 bit SCSI Card [*]
+ *      0x08            JPEG (Double Wide)
+ *      0x09            JPEG (Single Wide)
+ *      0x0a            XPI mez. FDDI device 0
+ *      0x0b            XPI mez. FDDI device 1
+ *      0x0c            SMPTE 259M Video [*]
+ *      0x0d            Babblefish Compression [*]
+ *      0x0e            E-Plex 8-port Ethernet
+ *      0x30            Lyon Lamb IVAS
+ *      0xb8            GIO 100BaseTX Fast Ethernet (gfe)
+ *
+ * [*] Device provide 32-bit ID.
+ *
+ */
+
+#define GIO_ID(x)               (x & 0x7f)
+#define GIO_32BIT_ID            0x80
+#define GIO_REV(x)              ((x >> 8) & 0xff)
+#define GIO_64BIT_IFACE         0x10000
+#define GIO_ROM_PRESENT         0x20000
+#define GIO_VENDOR_CODE(x)      ((x >> 18) & 0x3fff)
+
+#define GIO_SLOT_GFX_BASE       0x1f000000
+#define GIO_SLOT_EXP0_BASE      0x1f400000
+#define GIO_SLOT_EXP1_BASE      0x1f600000
+
+#endif /* _SGI_GIO_H */
diff --git a/arch/mips/include/asm/sgi/heart.h b/arch/mips/include/asm/sgi/heart.h
new file mode 100644
index 000000000..0d0375195
--- /dev/null
+++ b/arch/mips/include/asm/sgi/heart.h
@@ -0,0 +1,323 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * HEART chip definitions
+ *
+ * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
+ *               2009 Johannes Dickgreber <tanzy@gmx.de>
+ *               2007-2015 Joshua Kinard <kumba@gentoo.org>
+ */
+#ifndef __ASM_SGI_HEART_H
+#define __ASM_SGI_HEART_H
+
+#include <linux/types.h>
+#include <linux/time.h>
+
+/*
+ * There are 8 DIMM slots on an IP30 system
+ * board, which are grouped into four banks
+ */
+#define HEART_MEMORY_BANKS      4
+
+/* HEART can support up to four CPUs */
+#define HEART_MAX_CPUS          4
+
+#define HEART_XKPHYS_BASE       ((void *)(IO_BASE | 0x000000000ff00000ULL))
+
+/**
+ * struct ip30_heart_regs - struct that maps IP30 HEART registers.
+ * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
+ * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
+ * @mem_refresh: HEART_MEM_REF - purpose unknown.
+ * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
+ * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
+ * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
+ * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control.
+ * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown.
+ * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown.
+ * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown.
+ * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown.
+ * @status: HEART_STATUS - HEART status information.
+ * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS.
+ * @bus_err_misc: HEART_BERR_MISC - purpose unknown.
+ * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err.
+ * @mem_err_data: HEART_MEMERR_DATA - purpose unknown.
+ * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs.
+ * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider.
+ * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control.
+ * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
+ * @undefined: Undefined/diag register, write to it triggers PIUR_ACC_ERR.
+ * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
+ * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register.
+ * @set_isr: HEART_SET_ISR - set interrupt status register.
+ * @clear_isr: HEART_CLR_ISR - clear interrupt status register.
+ * @isr: HEART_ISR - interrupt status register (read-only).
+ * @imsr: HEART_IMSR - purpose unknown.
+ * @cause: HEART_CAUSE - HEART cause information.
+ * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
+ * @count: HEART_COUNT - 52-bit counter.
+ * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
+ * @compare: HEART_COMPARE - 24-bit compare.
+ * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
+ * @trigger: HEART_TRIGGER - purpose unknown.
+ * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
+ * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART.
+ * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
+ * @sync: HEART_SYNC - purpose unknown.
+ *
+ * HEART is the main system controller ASIC for IP30 system.  It incorporates
+ * a memory controller, interrupt status/cause/set/clear management, basic
+ * timer with count/compare, and other functionality.  For Linux, not all of
+ * HEART's functions are fully understood.
+ *
+ * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg
+ * register only reports correct values if queried in 32bits.  Hence the need
+ * for a union.  Even though mem_cfg.l has 8 array slots, we only ever query
+ * up to 4 of those.  IP30 has 8 DIMM slots arranged into 4 banks, w/ 2 DIMMs
+ * per bank.  Each 32bit read accesses one of these banks.  Perhaps HEART was
+ * designed to address up to 8 banks (16 DIMMs)?  We may never know.
+ */
+struct ip30_heart_regs {                /* 0x0ff00000 */
+        u64 mode;                       /* +  0x00000 */
+        /* Memory */
+        u64 sdram_mode;                 /* +  0x00008 */
+        u64 mem_refresh;                /* +  0x00010 */
+        u64 mem_req_arb;                /* +  0x00018 */
+        union {
+                u64 q[HEART_MEMORY_BANKS];      /* readq() */
+                u32 l[HEART_MEMORY_BANKS * 2];  /* readl() */
+        } mem_cfg;                      /* +  0x00020 */
+        /* Flow control (gfx?) */
+        u64 fc_mode;                    /* +  0x00040 */
+        u64 fc_timer_limit;             /* +  0x00048 */
+        u64 fc_addr[2];                 /* +  0x00050 */
+        u64 fc_credit_cnt[2];           /* +  0x00060 */
+        u64 fc_timer[2];                /* +  0x00070 */
+        /* Status */
+        u64 status;                     /* +  0x00080 */
+        /* Bus error */
+        u64 bus_err_addr;               /* +  0x00088 */
+        u64 bus_err_misc;               /* +  0x00090 */
+        /* Memory error */
+        u64 mem_err_addr;               /* +  0x00098 */
+        u64 mem_err_data;               /* +  0x000a0 */
+        /* Misc */
+        u64 piur_acc_err;               /* +  0x000a8 */
+        u64 mlan_clock_div;             /* +  0x000b0 */
+        u64 mlan_ctrl;                  /* +  0x000b8 */
+        u64 __pad0[0x01e8];             /* +  0x000c0 + 0x0f40 */
+        /* Undefined */
+        u64 undefined;                  /* +  0x01000 */
+        u64 __pad1[0x1dff];             /* +  0x01008 + 0xeff8 */
+        /* Interrupts */
+        u64 imr[HEART_MAX_CPUS];        /* +  0x10000 */
+        u64 set_isr;                    /* +  0x10020 */
+        u64 clear_isr;                  /* +  0x10028 */
+        u64 isr;                        /* +  0x10030 */
+        u64 imsr;                       /* +  0x10038 */
+        u64 cause;                      /* +  0x10040 */
+        u64 __pad2[0x1ff7];             /* +  0x10048 + 0xffb8 */
+        /* Timer */
+        u64 count;                      /* +  0x20000 */
+        u64 __pad3[0x1fff];             /* +  0x20008 + 0xfff8 */
+        u64 compare;                    /* +  0x30000 */
+        u64 __pad4[0x1fff];             /* +  0x30008 + 0xfff8 */
+        u64 trigger;                    /* +  0x40000 */
+        u64 __pad5[0x1fff];             /* +  0x40008 + 0xfff8 */
+        /* Misc */
+        u64 cpuid;                      /* +  0x50000 */
+        u64 __pad6[0x1fff];             /* +  0x50008 + 0xfff8 */
+        u64 sync;                       /* +  0x60000 */
+};
+
+
+/* For timer-related bits. */
+#define HEART_NS_PER_CYCLE      80
+#define HEART_CYCLES_PER_SEC    (NSEC_PER_SEC / HEART_NS_PER_CYCLE)
+
+
+/*
+ * XXX: Everything below this comment will either go away or be cleaned
+ *      up to fit in better with Linux.  A lot of the bit definitions for
+ *      HEART were derived from IRIX's sys/RACER/heart.h header file.
+ */
+
+/* HEART Masks */
+#define HEART_ATK_MASK          0x0007ffffffffffff      /* HEART attack mask */
+#define HEART_ACK_ALL_MASK      0xffffffffffffffff      /* Ack everything */
+#define HEART_CLR_ALL_MASK      0x0000000000000000      /* Clear all */
+#define HEART_BR_ERR_MASK       0x7ff8000000000000      /* BRIDGE error mask */
+#define HEART_CPU0_ERR_MASK     0x8ff8000000000000      /* CPU0 error mask */
+#define HEART_CPU1_ERR_MASK     0x97f8000000000000      /* CPU1 error mask */
+#define HEART_CPU2_ERR_MASK     0xa7f8000000000000      /* CPU2 error mask */
+#define HEART_CPU3_ERR_MASK     0xc7f8000000000000      /* CPU3 error mask */
+#define HEART_ERR_MASK          0x1ff                   /* HEART error mask */
+#define HEART_ERR_MASK_START    51                      /* HEART error start */
+#define HEART_ERR_MASK_END      63                      /* HEART error end */
+
+/* Bits in the HEART_MODE register. */
+#define HM_PROC_DISABLE_SHFT            60
+#define HM_PROC_DISABLE_MSK             (0xfUL << HM_PROC_DISABLE_SHFT)
+#define HM_PROC_DISABLE(x)              (0x1UL << (x) + HM_PROC_DISABLE_SHFT)
+#define HM_MAX_PSR                      (0x7UL << 57)
+#define HM_MAX_IOSR                     (0x7UL << 54)
+#define HM_MAX_PEND_IOSR                (0x7UL << 51)
+#define HM_TRIG_SRC_SEL_MSK             (0x7UL << 48)
+#define HM_TRIG_HEART_EXC               (0x0UL << 48)
+#define HM_TRIG_REG_BIT                 (0x1UL << 48)
+#define HM_TRIG_SYSCLK                  (0x2UL << 48)
+#define HM_TRIG_MEMCLK_2X               (0x3UL << 48)
+#define HM_TRIG_MEMCLK                  (0x4UL << 48)
+#define HM_TRIG_IOCLK                   (0x5UL << 48)
+#define HM_PIU_TEST_MODE                (0xfUL << 40)
+#define HM_GP_FLAG_MSK                  (0xfUL << 36)
+#define HM_GP_FLAG(x)                   BIT((x) + 36)
+#define HM_MAX_PROC_HYST                (0xfUL << 32)
+#define HM_LLP_WRST_AFTER_RST           BIT(28)
+#define HM_LLP_LINK_RST                 BIT(27)
+#define HM_LLP_WARM_RST                 BIT(26)
+#define HM_COR_ECC_LCK                  BIT(25)
+#define HM_REDUCED_PWR                  BIT(24)
+#define HM_COLD_RST                     BIT(23)
+#define HM_SW_RST                       BIT(22)
+#define HM_MEM_FORCE_WR                 BIT(21)
+#define HM_DB_ERR_GEN                   BIT(20)
+#define HM_SB_ERR_GEN                   BIT(19)
+#define HM_CACHED_PIO_EN                BIT(18)
+#define HM_CACHED_PROM_EN               BIT(17)
+#define HM_PE_SYS_COR_ERE               BIT(16)
+#define HM_GLOBAL_ECC_EN                BIT(15)
+#define HM_IO_COH_EN                    BIT(14)
+#define HM_INT_EN                       BIT(13)
+#define HM_DATA_CHK_EN                  BIT(12)
+#define HM_REF_EN                       BIT(11)
+#define HM_BAD_SYSWR_ERE                BIT(10)
+#define HM_BAD_SYSRD_ERE                BIT(9)
+#define HM_SYSSTATE_ERE                 BIT(8)
+#define HM_SYSCMD_ERE                   BIT(7)
+#define HM_NCOR_SYS_ERE                 BIT(6)
+#define HM_COR_SYS_ERE                  BIT(5)
+#define HM_DATA_ELMNT_ERE               BIT(4)
+#define HM_MEM_ADDR_PROC_ERE            BIT(3)
+#define HM_MEM_ADDR_IO_ERE              BIT(2)
+#define HM_NCOR_MEM_ERE                 BIT(1)
+#define HM_COR_MEM_ERE                  BIT(0)
+
+/* Bits in the HEART_MEM_REF register. */
+#define HEART_MEMREF_REFS(x)            ((0xfUL & (x)) << 16)
+#define HEART_MEMREF_PERIOD(x)          ((0xffffUL & (x)))
+#define HEART_MEMREF_REFS_VAL           HEART_MEMREF_REFS(8)
+#define HEART_MEMREF_PERIOD_VAL         HEART_MEMREF_PERIOD(0x4000)
+#define HEART_MEMREF_VAL                (HEART_MEMREF_REFS_VAL | \
+                                         HEART_MEMREF_PERIOD_VAL)
+
+/* Bits in the HEART_MEM_REQ_ARB register. */
+#define HEART_MEMARB_IODIS              (1  << 20)
+#define HEART_MEMARB_MAXPMWRQS          (15 << 16)
+#define HEART_MEMARB_MAXPMRRQS          (15 << 12)
+#define HEART_MEMARB_MAXPMRQS           (15 << 8)
+#define HEART_MEMARB_MAXRRRQS           (15 << 4)
+#define HEART_MEMARB_MAXGBRRQS          (15)
+
+/* Bits in the HEART_MEMCFG<x> registers. */
+#define HEART_MEMCFG_VALID              0x80000000      /* Bank is valid */
+#define HEART_MEMCFG_DENSITY            0x01c00000      /* Mem density */
+#define HEART_MEMCFG_SIZE_MASK          0x003f0000      /* Mem size mask */
+#define HEART_MEMCFG_ADDR_MASK          0x000001ff      /* Base addr mask */
+#define HEART_MEMCFG_SIZE_SHIFT         16              /* Mem size shift */
+#define HEART_MEMCFG_DENSITY_SHIFT      22              /* Density Shift */
+#define HEART_MEMCFG_UNIT_SHIFT         25              /* Unit Shift, 32MB */
+
+/* Bits in the HEART_STATUS register */
+#define HEART_STAT_HSTL_SDRV            BIT(14)
+#define HEART_STAT_FC_CR_OUT(x)         BIT((x) + 12)
+#define HEART_STAT_DIR_CNNCT            BIT(11)
+#define HEART_STAT_TRITON               BIT(10)
+#define HEART_STAT_R4K                  BIT(9)
+#define HEART_STAT_BIG_ENDIAN           BIT(8)
+#define HEART_STAT_PROC_SHFT            4
+#define HEART_STAT_PROC_MSK             (0xfUL << HEART_STAT_PROC_SHFT)
+#define HEART_STAT_PROC_ACTIVE(x)       (0x1UL << ((x) + HEART_STAT_PROC_SHFT))
+#define HEART_STAT_WIDGET_ID            0xf
+
+/* Bits in the HEART_CAUSE register */
+#define HC_PE_SYS_COR_ERR_MSK           (0xfUL << 60)
+#define HC_PE_SYS_COR_ERR(x)            BIT((x) + 60)
+#define HC_PIOWDB_OFLOW                 BIT(44)
+#define HC_PIORWRB_OFLOW                BIT(43)
+#define HC_PIUR_ACC_ERR                 BIT(42)
+#define HC_BAD_SYSWR_ERR                BIT(41)
+#define HC_BAD_SYSRD_ERR                BIT(40)
+#define HC_SYSSTATE_ERR_MSK             (0xfUL << 36)
+#define HC_SYSSTATE_ERR(x)              BIT((x) + 36)
+#define HC_SYSCMD_ERR_MSK               (0xfUL << 32)
+#define HC_SYSCMD_ERR(x)                BIT((x) + 32)
+#define HC_NCOR_SYSAD_ERR_MSK           (0xfUL << 28)
+#define HC_NCOR_SYSAD_ERR(x)            BIT((x) + 28)
+#define HC_COR_SYSAD_ERR_MSK            (0xfUL << 24)
+#define HC_COR_SYSAD_ERR(x)             BIT((x) + 24)
+#define HC_DATA_ELMNT_ERR_MSK           (0xfUL << 20)
+#define HC_DATA_ELMNT_ERR(x)            BIT((x) + 20)
+#define HC_WIDGET_ERR                   BIT(16)
+#define HC_MEM_ADDR_ERR_PROC_MSK        (0xfUL << 4)
+#define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4)
+#define HC_MEM_ADDR_ERR_IO              BIT(2)
+#define HC_NCOR_MEM_ERR                 BIT(1)
+#define HC_COR_MEM_ERR                  BIT(0)
+
+/*
+ * HEART has 64 interrupt vectors available to it, subdivided into five
+ * priority levels.  They are numbered 0 to 63.
+ */
+#define HEART_NUM_IRQS                  64
+
+/*
+ * These are the five interrupt priority levels and their corresponding
+ * CPU IPx interrupt pins.
+ *
+ * Level 4 - Error Interrupts.
+ * Level 3 - HEART timer interrupt.
+ * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
+ * Level 1 - General device interrupts.
+ * Level 0 - General device GFX flow control interrupts.
+ */
+#define HEART_L4_INT_MASK               0xfff8000000000000ULL   /* IP6 */
+#define HEART_L3_INT_MASK               0x0004000000000000ULL   /* IP5 */
+#define HEART_L2_INT_MASK               0x0003ffff00000000ULL   /* IP4 */
+#define HEART_L1_INT_MASK               0x00000000ffff0000ULL   /* IP3 */
+#define HEART_L0_INT_MASK               0x000000000000ffffULL   /* IP2 */
+
+/* HEART L0 Interrupts (Low Priority) */
+#define HEART_L0_INT_GENERIC             0
+#define HEART_L0_INT_FLOW_CTRL_HWTR_0    1
+#define HEART_L0_INT_FLOW_CTRL_HWTR_1    2
+
+/* HEART L2 Interrupts (High Priority) */
+#define HEART_L2_INT_RESCHED_CPU_0      46
+#define HEART_L2_INT_RESCHED_CPU_1      47
+#define HEART_L2_INT_CALL_CPU_0         48
+#define HEART_L2_INT_CALL_CPU_1         49
+
+/* HEART L3 Interrupts (Compare/Counter Timer) */
+#define HEART_L3_INT_TIMER              50
+
+/* HEART L4 Interrupts (Errors) */
+#define HEART_L4_INT_XWID_ERR_9         51
+#define HEART_L4_INT_XWID_ERR_A         52
+#define HEART_L4_INT_XWID_ERR_B         53
+#define HEART_L4_INT_XWID_ERR_C         54
+#define HEART_L4_INT_XWID_ERR_D         55
+#define HEART_L4_INT_XWID_ERR_E         56
+#define HEART_L4_INT_XWID_ERR_F         57
+#define HEART_L4_INT_XWID_ERR_XBOW      58
+#define HEART_L4_INT_CPU_BUS_ERR_0      59
+#define HEART_L4_INT_CPU_BUS_ERR_1      60
+#define HEART_L4_INT_CPU_BUS_ERR_2      61
+#define HEART_L4_INT_CPU_BUS_ERR_3      62
+#define HEART_L4_INT_HEART_EXCP         63
+
+extern struct ip30_heart_regs __iomem *heart_regs;
+
+#define heart_read      ____raw_readq
+#define heart_write     ____raw_writeq
+
+#endif /* __ASM_SGI_HEART_H */
diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
new file mode 100644
index 000000000..c0e3dc029
--- /dev/null
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -0,0 +1,317 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * hpc3.h: Definitions for SGI HPC3 controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1998 Ralf Baechle
+ */
+
+#ifndef _SGI_HPC3_H
+#define _SGI_HPC3_H
+
+#include <linux/types.h>
+#include <asm/page.h>
+
+/* An HPC DMA descriptor. */
+struct hpc_dma_desc {
+        u32 pbuf;       /* physical address of data buffer */
+        u32 cntinfo;    /* counter and info bits */
+#define HPCDMA_EOX      0x80000000 /* last desc in chain for tx */
+#define HPCDMA_EOR      0x80000000 /* last desc in chain for rx */
+#define HPCDMA_EOXP     0x40000000 /* end of packet for tx */
+#define HPCDMA_EORP     0x40000000 /* end of packet for rx */
+#define HPCDMA_XIE      0x20000000 /* irq generated when at end of this desc */
+#define HPCDMA_XIU      0x01000000 /* Tx buffer in use by CPU. */
+#define HPCDMA_EIPC     0x00ff0000 /* SEEQ ethernet special xternal bytecount */
+#define HPCDMA_ETXD     0x00008000 /* set to one by HPC when packet tx'd */
+#define HPCDMA_OWN      0x00004000 /* Denotes ring buffer ownership on rx */
+#define HPCDMA_BCNT     0x00003fff /* size in bytes of this dma buffer */
+
+        u32 pnext;      /* paddr of next hpc_dma_desc if any */
+};
+
+/* The set of regs for each HPC3 PBUS DMA channel. */
+struct hpc3_pbus_dmacregs {
+        volatile u32 pbdma_bptr;        /* pbus dma channel buffer ptr */
+        volatile u32 pbdma_dptr;        /* pbus dma channel desc ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 pbdma_ctrl;        /* pbus dma channel control register has
+                                         * completely different meaning for read
+                                         * compared with write */
+        /* read */
+#define HPC3_PDMACTRL_INT       0x00000001 /* interrupt (cleared after read) */
+#define HPC3_PDMACTRL_ISACT     0x00000002 /* channel active */
+        /* write */
+#define HPC3_PDMACTRL_SEL       0x00000002 /* little endian transfer */
+#define HPC3_PDMACTRL_RCV       0x00000004 /* direction is receive */
+#define HPC3_PDMACTRL_FLSH      0x00000008 /* enable flush for receive DMA */
+#define HPC3_PDMACTRL_ACT       0x00000010 /* start dma transfer */
+#define HPC3_PDMACTRL_LD        0x00000020 /* load enable for ACT */
+#define HPC3_PDMACTRL_RT        0x00000040 /* Use realtime GIO bus servicing */
+#define HPC3_PDMACTRL_HW        0x0000ff00 /* DMA High-water mark */
+#define HPC3_PDMACTRL_FB        0x003f0000 /* Ptr to beginning of fifo */
+#define HPC3_PDMACTRL_FE        0x3f000000 /* Ptr to end of fifo */
+
+        u32 _unused1[0x1000/4 - 1];     /* padding */
+};
+
+/* The HPC3 SCSI registers, this does not include external ones. */
+struct hpc3_scsiregs {
+        volatile u32 cbptr;     /* current dma buffer ptr, diagnostic use only */
+        volatile u32 ndptr;     /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 bcd;       /* byte count info */
+#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
+#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
+#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
+
+        volatile u32 ctrl;    /* control register */
+#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
+#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
+#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
+#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
+#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
+#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
+#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
+#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
+
+        volatile u32 gfptr;     /* current GIO fifo ptr */
+        volatile u32 dfptr;     /* current device fifo ptr */
+        volatile u32 dconfig;   /* DMA configuration register */
+#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
+#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
+#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
+#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
+#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
+#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
+#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
+#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
+#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
+#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
+#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
+#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
+#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
+#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
+#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
+#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
+#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
+
+        u32 _unused1[0x1000/4 - 6];     /* padding */
+};
+
+/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
+struct hpc3_ethregs {
+        /* Receiver registers. */
+        volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
+        volatile u32 rx_ndptr;   /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 rx_bcd;    /* byte count info */
+#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
+#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
+#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
+
+        volatile u32 rx_ctrl;   /* control register */
+#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
+#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
+#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
+#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
+#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
+#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
+#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
+
+        volatile u32 rx_gfptr;  /* current GIO fifo ptr */
+        volatile u32 rx_dfptr;  /* current device fifo ptr */
+        u32 _unused1;           /* padding */
+        volatile u32 reset;     /* reset register */
+#define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
+#define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
+#define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
+
+        volatile u32 dconfig;    /* DMA configuration register */
+#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
+#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
+#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
+#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
+#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
+#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
+#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
+#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
+#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
+#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
+#define HPC3_EPCFG_TST   0x1000 /* Diagnostic ram test feature bit */
+
+        u32 _unused2[0x1000/4 - 8];     /* padding */
+
+        /* Transmitter registers. */
+        volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
+        volatile u32 tx_ndptr;  /* next dma descriptor ptr */
+        u32 _unused3[0x1000/4 - 2];     /* padding */
+        volatile u32 tx_bcd;            /* byte count info */
+#define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
+#define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
+#define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
+#define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
+#define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
+
+        volatile u32 tx_ctrl;           /* control register */
+#define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
+#define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
+#define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
+#define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
+#define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
+#define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
+
+        volatile u32 tx_gfptr;          /* current GIO fifo ptr */
+        volatile u32 tx_dfptr;          /* current device fifo ptr */
+        u32 _unused4[0x1000/4 - 4];     /* padding */
+};
+
+struct hpc3_regs {
+        /* First regs for the PBUS 8 dma channels. */
+        struct hpc3_pbus_dmacregs pbdma[8];
+
+        /* Now the HPC scsi registers, we get two scsi reg sets. */
+        struct hpc3_scsiregs scsi_chan0, scsi_chan1;
+
+        /* The SEEQ hpc3 ethernet dma/control registers. */
+        struct hpc3_ethregs ethregs;
+
+        /* Here are where the hpc3 fifo's can be directly accessed
+         * via PIO accesses.  Under normal operation we never stick
+         * our grubby paws in here so it's just padding. */
+        u32 _unused0[0x18000/4];
+
+        /* HPC3 irq status regs.  Due to a peculiar bug you need to
+         * look at two different register addresses to get at all of
+         * the status bits.  The first reg can only reliably report
+         * bits 4:0 of the status, and the second reg can only
+         * reliably report bits 9:5 of the hpc3 irq status.  I told
+         * you it was a peculiar bug. ;-)
+         */
+        volatile u32 istat0;            /* Irq status, only bits <4:0> reliable. */
+#define HPC3_ISTAT_PBIMASK      0x0ff   /* irq bits for pbus devs 0 --> 7 */
+#define HPC3_ISTAT_SC0MASK      0x100   /* irq bit for scsi channel 0 */
+#define HPC3_ISTAT_SC1MASK      0x200   /* irq bit for scsi channel 1 */
+
+        volatile u32 gio_misc;          /* GIO misc control bits. */
+#define HPC3_GIOMISC_ERTIME     0x1     /* Enable external timer real time. */
+#define HPC3_GIOMISC_DENDIAN    0x2     /* dma descriptor endian, 1=lit 0=big */
+
+        u32 eeprom;                     /* EEPROM data reg. */
+#define HPC3_EEPROM_EPROT       0x01    /* Protect register enable */
+#define HPC3_EEPROM_CSEL        0x02    /* Chip select */
+#define HPC3_EEPROM_ECLK        0x04    /* EEPROM clock */
+#define HPC3_EEPROM_DATO        0x08    /* Data out */
+#define HPC3_EEPROM_DATI        0x10    /* Data in */
+
+        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
+        volatile u32 bestat;            /* Bus error interrupt status reg. */
+#define HPC3_BESTAT_BLMASK      0x000ff /* Bus lane where bad parity occurred */
+#define HPC3_BESTAT_CTYPE       0x00100 /* Bus cycle type, 0=PIO 1=DMA */
+#define HPC3_BESTAT_PIDSHIFT    9
+#define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
+
+        u32 _unused1[0x14000/4 - 5];    /* padding */
+
+        /* Now direct PIO per-HPC3 peripheral access to external regs. */
+        volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
+        u32 _unused2[0x7c00/4];
+        volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
+        u32 _unused3[0x7c00/4];
+        volatile u32 eth_ext[320];      /* Ethernet external registers */
+        u32 _unused4[0x3b00/4];
+
+        /* Per-peripheral device external registers and DMA/PIO control. */
+        volatile u32 pbus_extregs[16][256];
+        volatile u32 pbus_dmacfg[8][128];
+        /* Cycles to spend in D3 for reads */
+#define HPC3_DMACFG_D3R_MASK            0x00000001
+#define HPC3_DMACFG_D3R_SHIFT           0
+        /* Cycles to spend in D4 for reads */
+#define HPC3_DMACFG_D4R_MASK            0x0000001e
+#define HPC3_DMACFG_D4R_SHIFT           1
+        /* Cycles to spend in D5 for reads */
+#define HPC3_DMACFG_D5R_MASK            0x000001e0
+#define HPC3_DMACFG_D5R_SHIFT           5
+        /* Cycles to spend in D3 for writes */
+#define HPC3_DMACFG_D3W_MASK            0x00000200
+#define HPC3_DMACFG_D3W_SHIFT           9
+        /* Cycles to spend in D4 for writes */
+#define HPC3_DMACFG_D4W_MASK            0x00003c00
+#define HPC3_DMACFG_D4W_SHIFT           10
+        /* Cycles to spend in D5 for writes */
+#define HPC3_DMACFG_D5W_MASK            0x0003c000
+#define HPC3_DMACFG_D5W_SHIFT           14
+        /* Enable 16-bit DMA access mode */
+#define HPC3_DMACFG_DS16                0x00040000
+        /* Places halfwords on high 16 bits of bus */
+#define HPC3_DMACFG_EVENHI              0x00080000
+        /* Make this device real time */
+#define HPC3_DMACFG_RTIME               0x00200000
+        /* 5 bit burst count for DMA device */
+#define HPC3_DMACFG_BURST_MASK          0x07c00000
+#define HPC3_DMACFG_BURST_SHIFT 22
+        /* Use live pbus_dreq unsynchronized signal */
+#define HPC3_DMACFG_DRQLIVE             0x08000000
+        volatile u32 pbus_piocfg[16][64];
+        /* Cycles to spend in P2 state for reads */
+#define HPC3_PIOCFG_P2R_MASK            0x00001
+#define HPC3_PIOCFG_P2R_SHIFT           0
+        /* Cycles to spend in P3 state for reads */
+#define HPC3_PIOCFG_P3R_MASK            0x0001e
+#define HPC3_PIOCFG_P3R_SHIFT           1
+        /* Cycles to spend in P4 state for reads */
+#define HPC3_PIOCFG_P4R_MASK            0x001e0
+#define HPC3_PIOCFG_P4R_SHIFT           5
+        /* Cycles to spend in P2 state for writes */
+#define HPC3_PIOCFG_P2W_MASK            0x00200
+#define HPC3_PIOCFG_P2W_SHIFT           9
+        /* Cycles to spend in P3 state for writes */
+#define HPC3_PIOCFG_P3W_MASK            0x03c00
+#define HPC3_PIOCFG_P3W_SHIFT           10
+        /* Cycles to spend in P4 state for writes */
+#define HPC3_PIOCFG_P4W_MASK            0x3c000
+#define HPC3_PIOCFG_P4W_SHIFT           14
+        /* Enable 16-bit PIO accesses */
+#define HPC3_PIOCFG_DS16                0x40000
+        /* Place even address bits in bits <15:8> */
+#define HPC3_PIOCFG_EVENHI              0x80000
+
+        /* PBUS PROM control regs. */
+        volatile u32 pbus_promwe;       /* PROM write enable register */
+#define HPC3_PROM_WENAB 0x1     /* Enable writes to the PROM */
+
+        u32 _unused5[0x0800/4 - 1];
+        volatile u32 pbus_promswap;     /* Chip select swap reg */
+#define HPC3_PROM_SWAP  0x1     /* invert GIO addr bit to select prom0 or prom1 */
+
+        u32 _unused6[0x0800/4 - 1];
+        volatile u32 pbus_gout; /* PROM general purpose output reg */
+#define HPC3_PROM_STAT  0x1     /* General purpose status bit in gout */
+
+        u32 _unused7[0x1000/4 - 1];
+        volatile u32 rtcregs[14];       /* Dallas clock registers */
+        u32 _unused8[50];
+        volatile u32 bbram[8192-50-14]; /* Battery backed ram */
+};
+
+/*
+ * It is possible to have two HPC3's within the address space on
+ * one machine, though only having one is more likely on an Indy.
+ */
+extern struct hpc3_regs *hpc3c0, *hpc3c1;
+#define HPC3_CHIP0_BASE         0x1fb80000      /* physical */
+#define HPC3_CHIP1_BASE         0x1fb00000      /* physical */
+
+extern void sgihpc_init(void);
+
+#endif /* _SGI_HPC3_H */
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
new file mode 100644
index 000000000..53c6b1ca6
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -0,0 +1,200 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ioc.h: Definitions for SGI I/O Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2001, 2003 Ladislav Michl
+ */
+
+#ifndef _SGI_IOC_H
+#define _SGI_IOC_H
+
+#include <linux/types.h>
+#include <asm/sgi/pi1.h>
+
+/*
+ * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
+ * happen if you try word access them. You have been warned.
+ */
+
+struct sgioc_uart_regs {
+        u8 _ctrl1[3];
+        volatile u8 ctrl1;
+        u8 _data1[3];
+        volatile u8 data1;
+        u8 _ctrl2[3];
+        volatile u8 ctrl2;
+        u8 _data2[3];
+        volatile u8 data2;
+};
+
+struct sgioc_keyb_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _command[3];
+        volatile u8 command;
+};
+
+struct sgint_regs {
+        u8 _istat0[3];
+        volatile u8 istat0;             /* Interrupt status zero */
+#define SGINT_ISTAT0_FFULL      0x01
+#define SGINT_ISTAT0_SCSI0      0x02
+#define SGINT_ISTAT0_SCSI1      0x04
+#define SGINT_ISTAT0_ENET       0x08
+#define SGINT_ISTAT0_GFXDMA     0x10
+#define SGINT_ISTAT0_PPORT      0x20
+#define SGINT_ISTAT0_HPC2       0x40
+#define SGINT_ISTAT0_LIO2       0x80
+        u8 _imask0[3];
+        volatile u8 imask0;             /* Interrupt mask zero */
+        u8 _istat1[3];
+        volatile u8 istat1;             /* Interrupt status one */
+#define SGINT_ISTAT1_ISDNI      0x01
+#define SGINT_ISTAT1_PWR        0x02
+#define SGINT_ISTAT1_ISDNH      0x04
+#define SGINT_ISTAT1_LIO3       0x08
+#define SGINT_ISTAT1_HPC3       0x10
+#define SGINT_ISTAT1_AFAIL      0x20
+#define SGINT_ISTAT1_VIDEO      0x40
+#define SGINT_ISTAT1_GIO2       0x80
+        u8 _imask1[3];
+        volatile u8 imask1;             /* Interrupt mask one */
+        u8 _vmeistat[3];
+        volatile u8 vmeistat;           /* VME interrupt status */
+        u8 _cmeimask0[3];
+        volatile u8 cmeimask0;          /* VME interrupt mask zero */
+        u8 _cmeimask1[3];
+        volatile u8 cmeimask1;          /* VME interrupt mask one */
+        u8 _cmepol[3];
+        volatile u8 cmepol;             /* VME polarity */
+        u8 _tclear[3];
+        volatile u8 tclear;
+        u8 _errstat[3];
+        volatile u8 errstat;    /* Error status reg, reserved on INT2 */
+        u32 _unused0[2];
+        u8 _tcnt0[3];
+        volatile u8 tcnt0;              /* counter 0 */
+        u8 _tcnt1[3];
+        volatile u8 tcnt1;              /* counter 1 */
+        u8 _tcnt2[3];
+        volatile u8 tcnt2;              /* counter 2 */
+        u8 _tcword[3];
+        volatile u8 tcword;             /* control word */
+#define SGINT_TCWORD_BCD        0x01    /* Use BCD mode for counters */
+#define SGINT_TCWORD_MMASK      0x0e    /* Mode bitmask. */
+#define SGINT_TCWORD_MITC       0x00    /* IRQ on terminal count (doesn't work) */
+#define SGINT_TCWORD_MOS        0x02    /* One-shot IRQ mode. */
+#define SGINT_TCWORD_MRGEN      0x04    /* Normal rate generation */
+#define SGINT_TCWORD_MSWGEN     0x06    /* Square wave generator mode */
+#define SGINT_TCWORD_MSWST      0x08    /* Software strobe */
+#define SGINT_TCWORD_MHWST      0x0a    /* Hardware strobe */
+#define SGINT_TCWORD_CMASK      0x30    /* Command mask */
+#define SGINT_TCWORD_CLAT       0x00    /* Latch command */
+#define SGINT_TCWORD_CLSB       0x10    /* LSB read/write */
+#define SGINT_TCWORD_CMSB       0x20    /* MSB read/write */
+#define SGINT_TCWORD_CALL       0x30    /* Full counter read/write */
+#define SGINT_TCWORD_CNT0       0x00    /* Select counter zero */
+#define SGINT_TCWORD_CNT1       0x40    /* Select counter one */
+#define SGINT_TCWORD_CNT2       0x80    /* Select counter two */
+#define SGINT_TCWORD_CRBCK      0xc0    /* Readback command */
+};
+
+/*
+ * The timer is the good old 8254.  Unlike in PCs it's clocked at exactly 1MHz
+ */
+#define SGINT_TIMER_CLOCK       1000000
+
+/*
+ * This is the constant we're using for calibrating the counter.
+ */
+#define SGINT_TCSAMP_COUNTER    ((SGINT_TIMER_CLOCK / HZ) + 255)
+
+/* We need software copies of these because they are write only. */
+extern u8 sgi_ioc_reset, sgi_ioc_write;
+
+struct sgioc_regs {
+        struct pi1_regs pport;
+        u32 _unused0[2];
+        struct sgioc_uart_regs uart;
+        struct sgioc_keyb_regs kbdmouse;
+        u8 _gcsel[3];
+        volatile u8 gcsel;
+        u8 _genctrl[3];
+        volatile u8 genctrl;
+        u8 _panel[3];
+        volatile u8 panel;
+#define SGIOC_PANEL_POWERON     0x01
+#define SGIOC_PANEL_POWERINTR   0x02
+#define SGIOC_PANEL_VOLDNINTR   0x10
+#define SGIOC_PANEL_VOLDNHOLD   0x20
+#define SGIOC_PANEL_VOLUPINTR   0x40
+#define SGIOC_PANEL_VOLUPHOLD   0x80
+        u32 _unused1;
+        u8 _sysid[3];
+        volatile u8 sysid;
+#define SGIOC_SYSID_FULLHOUSE   0x01
+#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
+#define SGIOC_SYSID_CHIPREV(x)  (((x) & 0xe0) >> 5)
+        u32 _unused2;
+        u8 _read[3];
+        volatile u8 read;
+        u32 _unused3;
+        u8 _dmasel[3];
+        volatile u8 dmasel;
+#define SGIOC_DMASEL_SCLK10MHZ  0x00    /* use 10MHZ serial clock */
+#define SGIOC_DMASEL_ISDNB      0x01    /* enable isdn B */
+#define SGIOC_DMASEL_ISDNA      0x02    /* enable isdn A */
+#define SGIOC_DMASEL_PPORT      0x04    /* use parallel DMA */
+#define SGIOC_DMASEL_SCLK667MHZ 0x10    /* use 6.67MHZ serial clock */
+#define SGIOC_DMASEL_SCLKEXT    0x20    /* use external serial clock */
+        u32 _unused4;
+        u8 _reset[3];
+        volatile u8 reset;
+#define SGIOC_RESET_PPORT       0x01    /* 0=parport reset, 1=nornal */
+#define SGIOC_RESET_KBDMOUSE    0x02    /* 0=kbdmouse reset, 1=normal */
+#define SGIOC_RESET_EISA        0x04    /* 0=eisa reset, 1=normal */
+#define SGIOC_RESET_ISDN        0x08    /* 0=isdn reset, 1=normal */
+#define SGIOC_RESET_LC0OFF      0x10    /* guiness: turn led off (red, else green) */
+#define SGIOC_RESET_LC1OFF      0x20    /* guiness: turn led off (green, else amber) */
+        u32 _unused5;
+        u8 _write[3];
+        volatile u8 write;
+#define SGIOC_WRITE_NTHRESH     0x01    /* use 4.5db threshold */
+#define SGIOC_WRITE_TPSPEED     0x02    /* use 100ohm TP speed */
+#define SGIOC_WRITE_EPSEL       0x04    /* force cable mode: 1=AUI 0=TP */
+#define SGIOC_WRITE_EASEL       0x08    /* 1=autoselect 0=manual cable selection */
+#define SGIOC_WRITE_U1AMODE     0x10    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_U0AMODE     0x20    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_MLO         0x40    /* 1=4.75V 0=+5V */
+#define SGIOC_WRITE_MHI         0x80    /* 1=5.25V 0=+5V */
+        u32 _unused6;
+        struct sgint_regs int3;
+        u32 _unused7[16];
+        volatile u32 extio;             /* FullHouse only */
+#define EXTIO_S0_IRQ_3          0x8000  /* S0: vid.vsync */
+#define EXTIO_S0_IRQ_2          0x4000  /* S0: gfx.fifofull */
+#define EXTIO_S0_IRQ_1          0x2000  /* S0: gfx.int */
+#define EXTIO_S0_RETRACE        0x1000
+#define EXTIO_SG_IRQ_3          0x0800  /* SG: vid.vsync */
+#define EXTIO_SG_IRQ_2          0x0400  /* SG: gfx.fifofull */
+#define EXTIO_SG_IRQ_1          0x0200  /* SG: gfx.int */
+#define EXTIO_SG_RETRACE        0x0100
+#define EXTIO_GIO_33MHZ         0x0080
+#define EXTIO_EISA_BUSERR       0x0040
+#define EXTIO_MC_BUSERR         0x0020
+#define EXTIO_HPC3_BUSERR       0x0010
+#define EXTIO_S0_STAT_1         0x0008
+#define EXTIO_S0_STAT_0         0x0004
+#define EXTIO_SG_STAT_1         0x0002
+#define EXTIO_SG_STAT_0         0x0001
+};
+
+extern struct sgioc_regs *sgioc;
+extern struct sgint_regs *sgint;
+
+#endif
diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
new file mode 100644
index 000000000..87ec9eaa0
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -0,0 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ip22.h: Definitions for SGI IP22 machines
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ */
+
+#ifndef _SGI_IP22_H
+#define _SGI_IP22_H
+
+/*
+ * These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
+ * are not supported this way. Driver is supposed to allocate HPC/MC
+ * interrupt as shareable and then look to proper status bit (see
+ * HAL2 driver). This will prevent many complications, trust me ;-)
+ */
+
+#include <irq.h>
+#include <asm/sgi/ioc.h>
+
+#define SGINT_EISA      0       /* 16 EISA irq levels (Indigo2) */
+#define SGINT_CPU       MIPS_CPU_IRQ_BASE       /* MIPS CPU define 8 interrupt sources */
+#define SGINT_LOCAL0    (SGINT_CPU+8)   /* 8 local0 irq levels */
+#define SGINT_LOCAL1    (SGINT_CPU+16)  /* 8 local1 irq levels */
+#define SGINT_LOCAL2    (SGINT_CPU+24)  /* 8 local2 vectored irq levels */
+#define SGINT_LOCAL3    (SGINT_CPU+32)  /* 8 local3 vectored irq levels */
+#define SGINT_END       (SGINT_CPU+40)  /* End of 'spaces' */
+
+/*
+ * Individual interrupt definitions for the Indy and Indigo2
+ */
+
+#define SGI_SOFT_0_IRQ  SGINT_CPU + 0
+#define SGI_SOFT_1_IRQ  SGINT_CPU + 1
+#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
+#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
+#define SGI_8254_0_IRQ  SGINT_CPU + 4
+#define SGI_8254_1_IRQ  SGINT_CPU + 5
+#define SGI_BUSERR_IRQ  SGINT_CPU + 6
+#define SGI_TIMER_IRQ   SGINT_CPU + 7
+
+#define SGI_FIFO_IRQ    SGINT_LOCAL0 + 0        /* FIFO full */
+#define SGI_GIO_0_IRQ   SGI_FIFO_IRQ            /* GIO-0 */
+#define SGI_WD93_0_IRQ  SGINT_LOCAL0 + 1        /* 1st onboard WD93 */
+#define SGI_WD93_1_IRQ  SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
+#define SGI_ENET_IRQ    SGINT_LOCAL0 + 3        /* onboard ethernet */
+#define SGI_MCDMA_IRQ   SGINT_LOCAL0 + 4        /* MC DMA done */
+#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5        /* Parallel port */
+#define SGI_GIO_1_IRQ   SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
+#define SGI_MAP_0_IRQ   SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
+
+#define SGI_GPL0_IRQ    SGINT_LOCAL1 + 0        /* General Purpose LOCAL1_N<0> */
+#define SGI_PANEL_IRQ   SGINT_LOCAL1 + 1        /* front panel */
+#define SGI_GPL2_IRQ    SGINT_LOCAL1 + 2        /* General Purpose LOCAL1_N<2> */
+#define SGI_MAP_1_IRQ   SGINT_LOCAL1 + 3        /* Mappable interrupt 1 */
+#define SGI_HPCDMA_IRQ  SGINT_LOCAL1 + 4        /* HPC DMA done */
+#define SGI_ACFAIL_IRQ  SGINT_LOCAL1 + 5        /* AC fail */
+#define SGI_VINO_IRQ    SGINT_LOCAL1 + 6        /* Indy VINO */
+#define SGI_GIO_2_IRQ   SGINT_LOCAL1 + 7        /* Vert retrace / GIO-2 */
+
+/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
+#define SGI_VERT_IRQ    SGINT_LOCAL2 + 0        /* INT3: newport vertical status */
+#define SGI_EISA_IRQ    SGINT_LOCAL2 + 3        /* EISA interrupts */
+#define SGI_KEYBD_IRQ   SGINT_LOCAL2 + 4        /* keyboard */
+#define SGI_SERIAL_IRQ  SGINT_LOCAL2 + 5        /* onboard serial */
+#define SGI_GIOEXP0_IRQ (SGINT_LOCAL2 + 6)      /* Indy GIO EXP0 */
+#define SGI_GIOEXP1_IRQ (SGINT_LOCAL2 + 7)      /* Indy GIO EXP1 */
+
+#define ip22_is_fullhouse()     (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
+
+extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
+extern unsigned short ip22_nvram_read(int reg);
+
+#endif
diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
new file mode 100644
index 000000000..3a070cec9
--- /dev/null
+++ b/arch/mips/include/asm/sgi/mc.h
@@ -0,0 +1,231 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * mc.h: Definitions for SGI Memory Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#ifndef _SGI_MC_H
+#define _SGI_MC_H
+
+struct sgimc_regs {
+        u32 _unused0;
+        volatile u32 cpuctrl0;  /* CPU control register 0, readwrite */
+#define SGIMC_CCTRL0_REFS       0x0000000f /* REFS mask */
+#define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
+#define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
+#define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
+#define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
+#define SGIMC_CCTRL0_WDOG       0x00000100 /* Watchdog timer enable */
+#define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
+#define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
+#define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
+#define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
+#define SGIMC_CCTRL0_IENAB      0x00002000 /* Allow interrupts from MC */
+#define SGIMC_CCTRL0_ESNOOP     0x00004000 /* Snooping I/O enable */
+#define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
+#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
+#define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
+#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
+#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
+#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
+#define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
+        u32 _unused1;
+        volatile u32 cpuctrl1;  /* CPU control register 1, readwrite */
+#define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
+#define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
+#define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
+#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
+#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
+
+        u32 _unused2;
+        volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
+
+        u32 _unused3;
+        volatile u32 systemid;  /* MC system ID register, readonly */
+#define SGIMC_SYSID_MASKREV     0x0000000f /* Revision of MC controller */
+#define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
+
+        u32 _unused4[3];
+        volatile u32 divider;   /* Divider reg for RPSS */
+
+        u32 _unused5;
+        u32 eeprom;             /* EEPROM byte reg for r4k */
+#define SGIMC_EEPROM_PRE        0x00000001 /* eeprom chip PRE pin assertion */
+#define SGIMC_EEPROM_CSEL       0x00000002 /* Active high, eeprom chip select */
+#define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
+#define SGIMC_EEPROM_SDATAO     0x00000008 /* Serial EEPROM data-out */
+#define SGIMC_EEPROM_SDATAI     0x00000010 /* Serial EEPROM data-in */
+
+        u32 _unused6[3];
+        volatile u32 rcntpre;   /* Preload refresh counter */
+
+        u32 _unused7;
+        volatile u32 rcounter;  /* Readonly refresh counter */
+
+        u32 _unused8[13];
+        volatile u32 giopar;    /* Parameter word for GIO64 */
+#define SGIMC_GIOPAR_HPC64      0x00000001 /* HPC talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_GFX64      0x00000002 /* GFX talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_EXP064     0x00000004 /* EXP(slot0) talks using 64-bits */
+#define SGIMC_GIOPAR_EXP164     0x00000008 /* EXP(slot1) talks using 64-bits */
+#define SGIMC_GIOPAR_EISA64     0x00000010 /* EISA bus talks 64-bits to GIO */
+#define SGIMC_GIOPAR_HPC264     0x00000020 /* 2nd HPX talks 64-bits to GIO */
+#define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
+#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
+#define SGIMC_GIOPAR_ONEBUS     0x00000400 /* Exists one GIO64 pipelined bus */
+#define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
+#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
+#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
+#define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
+#define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
+
+        u32 _unused9;
+        volatile u32 cputp;     /* CPU bus arb time period */
+
+        u32 _unused10[3];
+        volatile u32 lbursttp;  /* Time period for long bursts */
+
+        /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
+         * be the same size. The size encoding for supported SIMMs is bellow */
+        u32 _unused11[9];
+        volatile u32 mconfig0;  /* Memory config register zero */
+        u32 _unused12;
+        volatile u32 mconfig1;  /* Memory config register one */
+#define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
+#define SGIMC_MCONFIG_RMASK     0x00001f00 /* Ram config bitmask */
+#define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
+#define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
+
+        u32 _unused13;
+        volatile u32 cmacc;        /* Mem access config for CPU */
+        u32 _unused14;
+        volatile u32 gmacc;        /* Mem access config for GIO */
+
+        /* This define applies to both cmacc and gmacc registers above. */
+#define SGIMC_MACC_ALIASBIG     0x20000000 /* 512MB home for alias */
+
+        /* Error address/status regs from GIO and CPU perspectives. */
+        u32 _unused15;
+        volatile u32 cerr;      /* Error address reg for CPU */
+        u32 _unused16;
+        volatile u32 cstat;     /* Status reg for CPU */
+#define SGIMC_CSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_CSTAT_PAR         0x00000200 /* CPU parity error */
+#define SGIMC_CSTAT_ADDR        0x00000400 /* memory bus error bad addr */
+#define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
+#define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
+#define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
+#define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
+#define SGIMC_CSTAT_RD_PAR      (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
+
+        u32 _unused17;
+        volatile u32 gerr;      /* Error address reg for GIO */
+        u32 _unused18;
+        volatile u32 gstat;     /* Status reg for GIO */
+#define SGIMC_GSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_GSTAT_WR          0x00000200 /* write parity error */
+#define SGIMC_GSTAT_TIME        0x00000400 /* GIO bus timed out */
+#define SGIMC_GSTAT_PROM        0x00000800 /* write to PROM when PROM_EN not set */
+#define SGIMC_GSTAT_ADDR        0x00001000 /* parity error on addr cycle */
+#define SGIMC_GSTAT_BC          0x00002000 /* parity error on byte count cycle */
+#define SGIMC_GSTAT_PIO_RD      0x00004000 /* read data parity on pio */
+#define SGIMC_GSTAT_PIO_WR      0x00008000 /* write data parity on pio */
+
+        /* Special hard bus locking registers. */
+        u32 _unused19;
+        volatile u32 syssembit;         /* Uni-bit system semaphore */
+        u32 _unused20;
+        volatile u32 mlock;             /* Global GIO memory access lock */
+        u32 _unused21;
+        volatile u32 elock;             /* Locks EISA from GIO accesses */
+
+        /* GIO dma control registers. */
+        u32 _unused22[15];
+        volatile u32 gio_dma_trans;     /* DMA mask to translation GIO addrs */
+        u32 _unused23;
+        volatile u32 gio_dma_sbits;     /* DMA GIO addr substitution bits */
+        u32 _unused24;
+        volatile u32 dma_intr_cause;    /* DMA IRQ cause indicator bits */
+        u32 _unused25;
+        volatile u32 dma_ctrl;          /* Main DMA control reg */
+
+        /* DMA TLB entry 0 */
+        u32 _unused26[5];
+        volatile u32 dtlb_hi0;
+        u32 _unused27;
+        volatile u32 dtlb_lo0;
+
+        /* DMA TLB entry 1 */
+        u32 _unused28;
+        volatile u32 dtlb_hi1;
+        u32 _unused29;
+        volatile u32 dtlb_lo1;
+
+        /* DMA TLB entry 2 */
+        u32 _unused30;
+        volatile u32 dtlb_hi2;
+        u32 _unused31;
+        volatile u32 dtlb_lo2;
+
+        /* DMA TLB entry 3 */
+        u32 _unused32;
+        volatile u32 dtlb_hi3;
+        u32 _unused33;
+        volatile u32 dtlb_lo3;
+
+        u32 _unused34[0x0392];
+
+        u32 _unused35;
+        volatile u32 rpsscounter;       /* Chirps at 100ns */
+
+        u32 _unused36[0x1000/4-2*4];
+
+        u32 _unused37;
+        volatile u32 maddronly;         /* Address DMA goes at */
+        u32 _unused38;
+        volatile u32 maddrpdeflts;      /* Same as above, plus set defaults */
+        u32 _unused39;
+        volatile u32 dmasz;             /* DMA count */
+        u32 _unused40;
+        volatile u32 ssize;             /* DMA stride size */
+        u32 _unused41;
+        volatile u32 gmaddronly;        /* Set GIO DMA but don't start trans */
+        u32 _unused42;
+        volatile u32 dmaddnpgo;         /* Set GIO DMA addr + start transfer */
+        u32 _unused43;
+        volatile u32 dmamode;           /* DMA mode config bit settings */
+        u32 _unused44;
+        volatile u32 dmaccount;         /* Zoom and byte count for DMA */
+        u32 _unused45;
+        volatile u32 dmastart;          /* Pedal to the metal. */
+        u32 _unused46;
+        volatile u32 dmarunning;        /* DMA op is in progress */
+        u32 _unused47;
+        volatile u32 maddrdefstart;     /* Set dma addr, defaults, and kick it */
+};
+
+extern struct sgimc_regs *sgimc;
+#define SGIMC_BASE              0x1fa00000      /* physical */
+
+/* Base location of the two ram banks found in IP2[0268] machines. */
+#define SGIMC_SEG0_BADDR        0x08000000
+#define SGIMC_SEG1_BADDR        0x20000000
+
+/* Maximum size of the above banks are per machine. */
+#define SGIMC_SEG0_SIZE_ALL             0x10000000 /* 256MB */
+#define SGIMC_SEG1_SIZE_IP20_IP22       0x08000000 /* 128MB */
+#define SGIMC_SEG1_SIZE_IP26_IP28       0x20000000 /* 512MB */
+
+extern void sgimc_init(void);
+
+#endif /* _SGI_MC_H */
diff --git a/arch/mips/include/asm/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h
new file mode 100644
index 000000000..88b814ef3
--- /dev/null
+++ b/arch/mips/include/asm/sgi/pi1.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * pi1.h: Definitions for SGI PI1 parallel port
+ */
+
+#ifndef _SGI_PI1_H
+#define _SGI_PI1_H
+
+struct pi1_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _ctrl[3];
+        volatile u8 ctrl;
+#define PI1_CTRL_STROBE_N       0x01
+#define PI1_CTRL_AFD_N          0x02
+#define PI1_CTRL_INIT_N         0x04
+#define PI1_CTRL_SLIN_N         0x08
+#define PI1_CTRL_IRQ_ENA        0x10
+#define PI1_CTRL_DIR            0x20
+#define PI1_CTRL_SEL            0x40
+        u8 _status[3];
+        volatile u8 status;
+#define PI1_STAT_DEVID          0x03    /* bits 0-1 */
+#define PI1_STAT_NOINK          0x04    /* SGI MODE only */
+#define PI1_STAT_ERROR          0x08
+#define PI1_STAT_ONLINE         0x10
+#define PI1_STAT_PE             0x20
+#define PI1_STAT_ACK            0x40
+#define PI1_STAT_BUSY           0x80
+        u8 _dmactrl[3];
+        volatile u8 dmactrl;
+#define PI1_DMACTRL_FIFO_EMPTY  0x01    /* fifo empty R/O */
+#define PI1_DMACTRL_ABORT       0x02    /* reset DMA and internal fifo W/O */
+#define PI1_DMACTRL_STDMODE     0x00    /* bits 2-3 */
+#define PI1_DMACTRL_SGIMODE     0x04    /* bits 2-3 */
+#define PI1_DMACTRL_RICOHMODE   0x08    /* bits 2-3 */
+#define PI1_DMACTRL_HPMODE      0x0c    /* bits 2-3 */
+#define PI1_DMACTRL_BLKMODE     0x10    /* block mode */
+#define PI1_DMACTRL_FIFO_CLEAR  0x20    /* clear fifo W/O */
+#define PI1_DMACTRL_READ        0x40    /* read */
+#define PI1_DMACTRL_RUN         0x80    /* pedal to the metal */
+        u8 _intstat[3];
+        volatile u8 intstat;
+#define PI1_INTSTAT_ACK         0x04
+#define PI1_INTSTAT_FEMPTY      0x08
+#define PI1_INTSTAT_NOINK       0x10
+#define PI1_INTSTAT_ONLINE      0x20
+#define PI1_INTSTAT_ERR         0x40
+#define PI1_INTSTAT_PE          0x80
+        u8 _intmask[3];
+        volatile u8 intmask;            /* enabled low, reset high*/
+#define PI1_INTMASK_ACK         0x04
+#define PI1_INTMASK_FIFO_EMPTY  0x08
+#define PI1_INTMASK_NOINK       0x10
+#define PI1_INTMASK_ONLINE      0x20
+#define PI1_INTMASK_ERR         0x40
+#define PI1_INTMASK_PE          0x80
+        u8 _timer1[3];
+        volatile u8 timer1;
+#define PI1_TIME1               0x27
+        u8 _timer2[3];
+        volatile u8 timer2;
+#define PI1_TIME2               0x13
+        u8 _timer3[3];
+        volatile u8 timer3;
+#define PI1_TIME3               0x10
+        u8 _timer4[3];
+        volatile u8 timer4;
+#define PI1_TIME4               0x00
+};
+
+#endif
diff --git a/arch/mips/include/asm/sgi/seeq.h b/arch/mips/include/asm/sgi/seeq.h
new file mode 100644
index 000000000..af0ffd768
--- /dev/null
+++ b/arch/mips/include/asm/sgi/seeq.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_SGI_SEEQ_H
+#define __ASM_SGI_SEEQ_H
+
+#include <linux/if_ether.h>
+
+#include <asm/sgi/hpc3.h>
+
+struct sgiseeq_platform_data {
+        struct hpc3_regs *hpc;
+        unsigned int irq;
+        unsigned char mac[ETH_ALEN];
+};
+
+#endif /* __ASM_SGI_SEEQ_H */
diff --git a/arch/mips/include/asm/sgi/wd.h b/arch/mips/include/asm/sgi/wd.h
new file mode 100644
index 000000000..0d6c3a4da
--- /dev/null
+++ b/arch/mips/include/asm/sgi/wd.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_SGI_WD_H
+#define __ASM_SGI_WD_H
+
+#include <asm/sgi/hpc3.h>
+
+struct sgiwd93_platform_data {
+        unsigned int unit;
+        unsigned int irq;
+        struct hpc3_scsiregs *hregs;
+        unsigned char *wdregs;
+};
+
+#endif /* __ASM_SGI_WD_H */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
new file mode 100644
index 000000000..80f900417
--- /dev/null
+++ b/arch/mips/include/asm/sgialib.h
@@ -0,0 +1,61 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI ARCS firmware interface library for the Linux kernel.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGIALIB_H
+#define _ASM_SGIALIB_H
+
+#include <linux/compiler.h>
+#include <asm/sgiarcs.h>
+
+extern struct linux_romvec *romvec;
+
+extern int prom_flags;
+
+#define PROM_FLAG_ARCS                  1
+#define PROM_FLAG_USE_AS_CONSOLE        2
+#define PROM_FLAG_DONT_FREE_TEMP        4
+
+/* Simple char-by-char console I/O. */
+extern char prom_getchar(void);
+
+/* Get next memory descriptor after CURR, returns first descriptor
+ * in chain is CURR is NULL.
+ */
+extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
+#define PROM_NULL_MDESC   ((struct linux_mdesc *) 0)
+
+/* Called by prom_init to setup the physical memory pmemblock
+ * array.
+ */
+extern void prom_meminit(void);
+
+/* PROM device tree library routines. */
+#define PROM_NULL_COMPONENT ((pcomponent *) 0)
+
+/* This is called at prom_init time to identify the
+ * ARC architecture we are running on
+ */
+extern void prom_identify_arch(void);
+
+/* Environment variable routines. */
+extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
+
+/* ARCS command line parsing. */
+extern void prom_init_cmdline(int argc, LONG *argv);
+
+/* File operations. */
+extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+
+/* Misc. routines. */
+extern VOID ArcEnterInteractiveMode(VOID) __noreturn;
+extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
+
+#endif /* _ASM_SGIALIB_H */
diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
new file mode 100644
index 000000000..e1512cab1
--- /dev/null
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -0,0 +1,505 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ARC firmware interface defines.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SGIARCS_H
+#define _ASM_SGIARCS_H
+
+#include <linux/kernel.h>
+
+#include <asm/types.h>
+#include <asm/fw/arc/types.h>
+
+/* Various ARCS error codes. */
+#define PROM_ESUCCESS                   0x00
+#define PROM_E2BIG                      0x01
+#define PROM_EACCESS                    0x02
+#define PROM_EAGAIN                     0x03
+#define PROM_EBADF                      0x04
+#define PROM_EBUSY                      0x05
+#define PROM_EFAULT                     0x06
+#define PROM_EINVAL                     0x07
+#define PROM_EIO                        0x08
+#define PROM_EISDIR                     0x09
+#define PROM_EMFILE                     0x0a
+#define PROM_EMLINK                     0x0b
+#define PROM_ENAMETOOLONG               0x0c
+#define PROM_ENODEV                     0x0d
+#define PROM_ENOENT                     0x0e
+#define PROM_ENOEXEC                    0x0f
+#define PROM_ENOMEM                     0x10
+#define PROM_ENOSPC                     0x11
+#define PROM_ENOTDIR                    0x12
+#define PROM_ENOTTY                     0x13
+#define PROM_ENXIO                      0x14
+#define PROM_EROFS                      0x15
+/* SGI ARCS specific errno's. */
+#define PROM_EADDRNOTAVAIL              0x1f
+#define PROM_ETIMEDOUT                  0x20
+#define PROM_ECONNABORTED               0x21
+#define PROM_ENOCONNECT                 0x22
+
+/* Device classes, types, and identifiers for prom
+ * device inventory queries.
+ */
+enum linux_devclass {
+        system, processor, cache, adapter, controller, peripheral, memory
+};
+
+enum linux_devtypes {
+        /* Generic stuff. */
+        Arc, Cpu, Fpu,
+
+        /* Primary insn and data caches. */
+        picache, pdcache,
+
+        /* Secondary insn, data, and combined caches. */
+        sicache, sdcache, sccache,
+
+        memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter,
+        multifunc_adapter, dsk_controller, tp_controller, cdrom_controller,
+        worm_controller, serial_controller, net_controller, disp_controller,
+        parallel_controller, ptr_controller, kbd_controller, audio_controller,
+        misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral,
+        modem_peripheral, monitor_peripheral, printer_peripheral,
+        ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral,
+        net_peripheral, misc_peripheral, anon
+};
+
+enum linux_identifier {
+        bogus, ronly, removable, consin, consout, input, output
+};
+
+/* A prom device tree component. */
+struct linux_component {
+        enum linux_devclass     class;  /* node class */
+        enum linux_devtypes     type;   /* node type */
+        enum linux_identifier   iflags; /* node flags */
+        USHORT                  vers;   /* node version */
+        USHORT                  rev;    /* node revision */
+        ULONG                   key;    /* completely magic */
+        ULONG                   amask;  /* XXX affinity mask??? */
+        ULONG                   cdsize; /* size of configuration data */
+        ULONG                   ilen;   /* length of string identifier */
+        _PULONG                 iname;  /* string identifier */
+};
+typedef struct linux_component pcomponent;
+
+struct linux_sysid {
+        char vend[8], prod[8];
+};
+
+/* ARCS prom memory descriptors. */
+enum arcs_memtypes {
+        arcs_eblock,  /* exception block */
+        arcs_rvpage,  /* ARCS romvec page */
+        arcs_fcontig, /* Contiguous and free */
+        arcs_free,    /* Generic free memory */
+        arcs_bmem,    /* Borken memory, don't use */
+        arcs_prog,    /* A loaded program resides here */
+        arcs_atmp,    /* ARCS temporary storage area, wish Sparc OpenBoot told this */
+        arcs_aperm,   /* ARCS permanent storage... */
+};
+
+/* ARC has slightly different types than ARCS */
+enum arc_memtypes {
+        arc_eblock,  /* exception block */
+        arc_rvpage,  /* romvec page */
+        arc_free,    /* Generic free memory */
+        arc_bmem,    /* Borken memory, don't use */
+        arc_prog,    /* A loaded program resides here */
+        arc_atmp,    /* temporary storage area */
+        arc_aperm,   /* permanent storage */
+        arc_fcontig, /* Contiguous and free */
+};
+
+union linux_memtypes {
+    enum arcs_memtypes arcs;
+    enum arc_memtypes arc;
+};
+
+struct linux_mdesc {
+        union linux_memtypes type;
+        ULONG base;
+        ULONG pages;
+};
+
+/* Time of day descriptor. */
+struct linux_tinfo {
+        unsigned short yr;
+        unsigned short mnth;
+        unsigned short day;
+        unsigned short hr;
+        unsigned short min;
+        unsigned short sec;
+        unsigned short msec;
+};
+
+/* ARCS virtual dirents. */
+struct linux_vdirent {
+        ULONG namelen;
+        unsigned char attr;
+        char fname[32]; /* XXX empirical, should be a define */
+};
+
+/* Other stuff for files. */
+enum linux_omode {
+        rdonly, wronly, rdwr, wronly_creat, rdwr_creat,
+        wronly_ssede, rdwr_ssede, dirent, dirent_creat
+};
+
+enum linux_seekmode {
+        absolute, relative
+};
+
+enum linux_mountops {
+        media_load, media_unload
+};
+
+/* This prom has a bolixed design. */
+struct linux_bigint {
+#ifdef __MIPSEL__
+        u32 lo;
+        s32 hi;
+#else /* !(__MIPSEL__) */
+        s32 hi;
+        u32 lo;
+#endif
+};
+
+struct linux_finfo {
+        struct linux_bigint   begin;
+        struct linux_bigint   end;
+        struct linux_bigint   cur;
+        enum linux_devtypes   dtype;
+        unsigned long         namelen;
+        unsigned char         attr;
+        char                  name[32]; /* XXX empirical, should be define */
+};
+
+/* This describes the vector containing function pointers to the ARC
+   firmware functions.  */
+struct linux_romvec {
+        LONG    load;                   /* Load an executable image. */
+        LONG    invoke;                 /* Invoke a standalong image. */
+        LONG    exec;                   /* Load and begin execution of a
+                                           standalone image. */
+        LONG    halt;                   /* Halt the machine. */
+        LONG    pdown;                  /* Power down the machine. */
+        LONG    restart;                /* XXX soft reset??? */
+        LONG    reboot;                 /* Reboot the machine. */
+        LONG    imode;                  /* Enter PROM interactive mode. */
+        LONG    _unused1;               /* Was ReturnFromMain(). */
+
+        /* PROM device tree interface. */
+        LONG    next_component;
+        LONG    child_component;
+        LONG    parent_component;
+        LONG    component_data;
+        LONG    child_add;
+        LONG    comp_del;
+        LONG    component_by_path;
+
+        /* Misc. stuff. */
+        LONG    cfg_save;
+        LONG    get_sysid;
+
+        /* Probing for memory. */
+        LONG    get_mdesc;
+        LONG    _unused2;               /* was Signal() */
+
+        LONG    get_tinfo;
+        LONG    get_rtime;
+
+        /* File type operations. */
+        LONG    get_vdirent;
+        LONG    open;
+        LONG    close;
+        LONG    read;
+        LONG    get_rstatus;
+        LONG    write;
+        LONG    seek;
+        LONG    mount;
+
+        /* Dealing with firmware environment variables. */
+        LONG    get_evar;
+        LONG    set_evar;
+
+        LONG    get_finfo;
+        LONG    set_finfo;
+
+        /* Miscellaneous. */
+        LONG    cache_flush;
+        LONG    TestUnicodeCharacter;           /* ARC; not sure if ARCS too */
+        LONG    GetDisplayStatus;
+};
+
+/* The SGI ARCS parameter block is in a fixed location for standalone
+ * programs to access PROM facilities easily.
+ */
+typedef struct _SYSTEM_PARAMETER_BLOCK {
+        ULONG                   magic;          /* magic cookie */
+#define PROMBLOCK_MAGIC      0x53435241
+
+        ULONG                   len;            /* length of parm block */
+        USHORT                  ver;            /* ARCS firmware version */
+        USHORT                  rev;            /* ARCS firmware revision */
+        _PLONG                  rs_block;       /* Restart block. */
+        _PLONG                  dbg_block;      /* Debug block. */
+        _PLONG                  gevect;         /* XXX General vector??? */
+        _PLONG                  utlbvect;       /* XXX UTLB vector??? */
+        ULONG                   rveclen;        /* Size of romvec struct. */
+        _PVOID                  romvec;         /* Function interface. */
+        ULONG                   pveclen;        /* Length of private vector. */
+        _PVOID                  pvector;        /* Private vector. */
+        ULONG                   adap_cnt;       /* Adapter count. */
+        ULONG                   adap_typ0;      /* First adapter type. */
+        ULONG                   adap_vcnt0;     /* Adapter 0 vector count. */
+        _PVOID                  adap_vector;    /* Adapter 0 vector ptr. */
+        ULONG                   adap_typ1;      /* Second adapter type. */
+        ULONG                   adap_vcnt1;     /* Adapter 1 vector count. */
+        _PVOID                  adap_vector1;   /* Adapter 1 vector ptr. */
+        /* More adapter vectors go here... */
+} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK;
+
+#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000)
+#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec)
+
+/* Cache layout parameter block. */
+union linux_cache_key {
+        struct param {
+#ifdef __MIPSEL__
+                unsigned short size;
+                unsigned char lsize;
+                unsigned char bsize;
+#else /* !(__MIPSEL__) */
+                unsigned char bsize;
+                unsigned char lsize;
+                unsigned short size;
+#endif
+        } info;
+        unsigned long allinfo;
+};
+
+/* Configuration data. */
+struct linux_cdata {
+        char *name;
+        int mlen;
+        enum linux_devtypes type;
+};
+
+/* Common SGI ARCS firmware file descriptors. */
+#define SGIPROM_STDIN     0
+#define SGIPROM_STDOUT    1
+
+/* Common SGI ARCS firmware file types. */
+#define SGIPROM_ROFILE    0x01  /* read-only file */
+#define SGIPROM_HFILE     0x02  /* hidden file */
+#define SGIPROM_SFILE     0x04  /* System file */
+#define SGIPROM_AFILE     0x08  /* Archive file */
+#define SGIPROM_DFILE     0x10  /* Directory file */
+#define SGIPROM_DELFILE   0x20  /* Deleted file */
+
+/* SGI ARCS boot record information. */
+struct sgi_partition {
+        unsigned char flag;
+#define SGIPART_UNUSED 0x00
+#define SGIPART_ACTIVE 0x80
+
+        unsigned char shead, ssect, scyl; /* unused */
+        unsigned char systype; /* OS type, Irix or NT */
+        unsigned char ehead, esect, ecyl; /* unused */
+        unsigned char rsect0, rsect1, rsect2, rsect3;
+        unsigned char tsect0, tsect1, tsect2, tsect3;
+};
+
+#define SGIBBLOCK_MAGIC   0xaa55
+#define SGIBBLOCK_MAXPART 0x0004
+
+struct sgi_bootblock {
+        unsigned char _unused[446];
+        struct sgi_partition partitions[SGIBBLOCK_MAXPART];
+        unsigned short magic;
+};
+
+/* BIOS parameter block. */
+struct sgi_bparm_block {
+        unsigned short bytes_sect;    /* bytes per sector */
+        unsigned char  sect_clust;    /* sectors per cluster */
+        unsigned short sect_resv;     /* reserved sectors */
+        unsigned char  nfats;         /* # of allocation tables */
+        unsigned short nroot_dirents; /* # of root directory entries */
+        unsigned short sect_volume;   /* sectors in volume */
+        unsigned char  media_type;    /* media descriptor */
+        unsigned short sect_fat;      /* sectors per allocation table */
+        unsigned short sect_track;    /* sectors per track */
+        unsigned short nheads;        /* # of heads */
+        unsigned short nhsects;       /* # of hidden sectors */
+};
+
+struct sgi_bsector {
+        unsigned char   jmpinfo[3];
+        unsigned char   manuf_name[8];
+        struct sgi_bparm_block info;
+};
+
+/* Debugging block used with SGI symmon symbolic debugger. */
+#define SMB_DEBUG_MAGIC   0xfeeddead
+struct linux_smonblock {
+        unsigned long   magic;
+        void            (*handler)(void);  /* Breakpoint routine. */
+        unsigned long   dtable_base;       /* Base addr of dbg table. */
+        int             (*printf)(const char *fmt, ...);
+        unsigned long   btable_base;       /* Breakpoint table. */
+        unsigned long   mpflushreqs;       /* SMP cache flush request list. */
+        unsigned long   ntab;              /* Name table. */
+        unsigned long   stab;              /* Symbol table. */
+        int             smax;              /* Max # of symbols. */
+};
+
+/*
+ * Macros for calling a 32-bit ARC implementation from 64-bit code
+ */
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
+
+extern long call_o32(long vec, void *stack, ...);
+
+extern u64 o32_stk[4096];
+#define O32_STK (&o32_stk[ARRAY_SIZE(o32_stk)])
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK);                               \
+        __res;                                                          \
+})
+
+#define ARC_CALL1(dest, a1)                                             \
+({      long __res;                                                     \
+        int  __a1 = (int) (long) (a1);                                  \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK, __a1);                         \
+        __res;                                                          \
+})
+
+#define ARC_CALL2(dest, a1, a2)                                         \
+({      long __res;                                                     \
+        int  __a1 = (int) (long) (a1);                                  \
+        int  __a2 = (int) (long) (a2);                                  \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK, __a1, __a2);                   \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest, a1, a2, a3)                                     \
+({      long __res;                                                     \
+        int  __a1 = (int) (long) (a1);                                  \
+        int  __a2 = (int) (long) (a2);                                  \
+        int  __a3 = (int) (long) (a3);                                  \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK, __a1, __a2, __a3);             \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
+({      long __res;                                                     \
+        int  __a1 = (int) (long) (a1);                                  \
+        int  __a2 = (int) (long) (a2);                                  \
+        int  __a3 = (int) (long) (a3);                                  \
+        int  __a4 = (int) (long) (a4);                                  \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK, __a1, __a2, __a3, __a4);       \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                             \
+({      long __res;                                                     \
+        int  __a1 = (int) (long) (a1);                                  \
+        int  __a2 = (int) (long) (a2);                                  \
+        int  __a3 = (int) (long) (a3);                                  \
+        int  __a4 = (int) (long) (a4);                                  \
+        int  __a5 = (int) (long) (a5);                                  \
+        long __vec = (long) romvec->dest;                               \
+        __res = call_o32(__vec, O32_STK, __a1, __a2, __a3, __a4, __a5); \
+        __res;                                                          \
+})
+
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) */
+
+#if (defined(CONFIG_32BIT) && defined(CONFIG_FW_ARC32)) ||              \
+    (defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC64))
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long (*__vec)(void) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec();                                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL1(dest, a1)                                             \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long (*__vec)(long) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec(__a1);                                            \
+        __res;                                                          \
+})
+
+#define ARC_CALL2(dest, a1, a2)                                         \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long (*__vec)(long, long) = (void *) romvec->dest;              \
+                                                                        \
+        __res = __vec(__a1, __a2);                                      \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest, a1, a2, a3)                                     \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long (*__vec)(long, long, long) = (void *) romvec->dest;        \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3);                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long (*__vec)(long, long, long, long) = (void *) romvec->dest;  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4);                          \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                             \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long __a5 = (long) (a5);                                        \
+        long (*__vec)(long, long, long, long, long);                    \
+        __vec = (void *) romvec->dest;                                  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4, __a5);                    \
+        __res;                                                          \
+})
+#endif /* both kernel and ARC either 32-bit or 64-bit */
+
+#endif /* _ASM_SGIARCS_H */
diff --git a/arch/mips/include/asm/shmparam.h b/arch/mips/include/asm/shmparam.h
new file mode 100644
index 000000000..324d04042
--- /dev/null
+++ b/arch/mips/include/asm/shmparam.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_SHMPARAM_H
+#define _ASM_SHMPARAM_H
+
+#define __ARCH_FORCE_SHMLBA     1
+
+#define SHMLBA 0x40000                  /* attach addr a multiple of this */
+
+#endif /* _ASM_SHMPARAM_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
new file mode 100644
index 000000000..18cf4b105
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
@@ -0,0 +1,299 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: bcm1480_int.h
+    *
+    *  This module contains constants for manipulating the
+    *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
+    *  definitions for the interrupt sources.
+    *
+    *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_INT_H
+#define _BCM1480_INT_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * The interrupt mapper deals with 128-bit logical registers that are
+ * implemented as pairs of 64-bit registers, with the "low" 64 bits in
+ * a register that has an address 0x1000 higher(!) than the
+ * corresponding "high" register.
+ *
+ * For appropriate registers, bit 0 of the "high" register is a
+ * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
+ * register.
+ */
+
+/*
+ * This entire file uses _BCM1480_ in all the symbols because it is
+ * entirely BCM1480 specific.
+ */
+
+/*
+ * Interrupt sources (Table 22)
+ */
+
+#define K_BCM1480_INT_SOURCES               128
+
+#define _BCM1480_INT_HIGH(k)   (k)
+#define _BCM1480_INT_LOW(k)    ((k)+64)
+
+#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
+#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
+#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
+#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
+#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
+#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
+#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
+#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
+#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
+#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
+#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
+#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
+#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
+#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
+#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
+#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
+#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
+#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
+#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
+#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
+#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
+#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
+#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
+#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
+#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
+#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
+#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
+#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
+#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
+#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
+#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
+#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
+#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
+#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
+#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
+#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
+#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
+#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
+#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
+#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
+#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
+
+#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
+#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
+#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
+#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
+#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
+#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
+#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
+#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
+#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
+#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
+#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
+#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
+#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
+#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
+#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
+#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
+#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
+#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
+#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
+#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
+#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
+#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
+#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
+#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
+#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
+#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
+#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
+#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
+#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
+#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
+#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
+#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
+#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
+#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
+#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
+#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
+#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
+#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
+#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
+#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
+#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
+#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
+#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
+#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
+#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define _BCM1480_INT_MASK(w, n)              _SB_MAKEMASK(w, ((n) & 0x3F))
+#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
+#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
+
+#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
+
+#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
+#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
+#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
+#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
+#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
+#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
+#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
+#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
+#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
+#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
+#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
+#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
+#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
+#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
+#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
+#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
+#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
+#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
+#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
+#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
+#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
+#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
+#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
+#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
+#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
+#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
+#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
+#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
+#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
+#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
+#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
+#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
+#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
+#define M_BCM1480_INT_MBOX_ALL              _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
+#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
+#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
+#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
+#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
+#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
+#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
+#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
+#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
+#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
+#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
+#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
+#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
+#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
+#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
+#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
+#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
+#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
+#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
+#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
+#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
+#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
+#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
+#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
+#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
+#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
+#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
+#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
+#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
+#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
+#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
+#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
+#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
+#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
+#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
+#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
+#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
+#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
+#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
+#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
+#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
+#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
+#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
+#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
+#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
+#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
+#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
+#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
+#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
+#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
+#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
+#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
+
+/*
+ * Interrupt mappings (Table 18)
+ */
+
+#define K_BCM1480_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_BCM1480_INT_MAP_I1    1
+#define K_BCM1480_INT_MAP_I2    2
+#define K_BCM1480_INT_MAP_I3    3
+#define K_BCM1480_INT_MAP_I4    4
+#define K_BCM1480_INT_MAP_I5    5
+#define K_BCM1480_INT_MAP_NMI   6               /* nonmaskable */
+#define K_BCM1480_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * Interrupt LDT Set Register (Table 19)
+ */
+
+#define S_BCM1480_INT_HT_INTMSG             0
+#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
+#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
+#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
+
+#define K_BCM1480_INT_HT_INTMSG_FIXED       0
+#define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
+#define K_BCM1480_INT_HT_INTMSG_SMI         2
+#define K_BCM1480_INT_HT_INTMSG_NMI         3
+#define K_BCM1480_INT_HT_INTMSG_INIT        4
+#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
+#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
+#define K_BCM1480_INT_HT_INTMSG_RESERVED    7
+
+#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
+#define V_BCM1480_INT_HT_EDGETRIGGER        0
+#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
+
+#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
+#define V_BCM1480_INT_HT_PHYSICALDEST       0
+#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
+
+#define S_BCM1480_INT_HT_INTDEST            5
+#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
+#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
+#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
+
+#define S_BCM1480_INT_HT_VECTOR             13
+#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
+#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
+#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
+
+/*
+ * Vector prefix (Table 4-7)
+ */
+
+#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
+#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
+#define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
+#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
+
+#endif /* _BCM1480_INT_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
new file mode 100644
index 000000000..f6f3a1989
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: bcm1480_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  BCM1400 specification level:  1280-UM100-D2 (11/14/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_L2C_H
+#define _BCM1480_L2C_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Format of level 2 cache management address (Table 55)
+ */
+
+#define S_BCM1480_L2C_MGMT_INDEX            5
+#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
+#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
+#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
+
+#define S_BCM1480_L2C_MGMT_WAY              17
+#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
+#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
+#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
+
+#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
+#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
+
+#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
+#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
+
+#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define BCM1480_L2C_ENTRIES_PER_WAY         4096
+#define BCM1480_L2C_NUM_WAYS                8
+
+
+/*
+ * Level 2 Cache Tag register (Table 59)
+ */
+
+#define S_BCM1480_L2C_TAG_MBZ               0
+#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
+
+#define S_BCM1480_L2C_TAG_INDEX             5
+#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
+#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
+#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
+
+/* Note that index bit 16 is also tag bit 40 */
+#define S_BCM1480_L2C_TAG_TAG               17
+#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
+#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
+#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
+
+#define S_BCM1480_L2C_TAG_ECC               40
+#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
+#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
+#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
+
+#define S_BCM1480_L2C_TAG_WAY               46
+#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
+#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
+#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
+
+#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
+#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
+
+#define S_BCM1480_L2C_DATA_ECC              51
+#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
+#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
+#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
+
+
+/*
+ * L2 Misc0 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
+#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
+
+#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
+#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
+
+#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
+#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
+#define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
+#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
+#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
+
+#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
+#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
+
+#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
+#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
+
+
+/*
+ * L2 Misc1 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
+
+
+/*
+ * L2 Misc2 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
+
+
+#endif /* _BCM1480_L2C_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
new file mode 100644
index 000000000..1d9b62d47
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
@@ -0,0 +1,971 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Memory Controller constants              File: bcm1480_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  BCM1400 specification level:  1280-UM100-D1 (11/14/03 Review Copy)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_MC_H
+#define _BCM1480_MC_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Memory Channel Configuration Register (Table 81)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
+
+#define S_BCM1480_MC_INTLV2                 16
+#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
+#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
+
+#define S_BCM1480_MC_CS_MODE                32
+#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
+#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
+
+#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
+                                     V_BCM1480_MC_CS_MODE_DEFAULT)
+
+#define K_BCM1480_MC_CS01_MODE              0x03
+#define K_BCM1480_MC_CS02_MODE              0x05
+#define K_BCM1480_MC_CS0123_MODE            0x0F
+#define K_BCM1480_MC_CS0246_MODE            0x55
+#define K_BCM1480_MC_CS0145_MODE            0x33
+#define K_BCM1480_MC_CS0167_MODE            0xC3
+#define K_BCM1480_MC_CSFULL_MODE            0xFF
+
+/*
+ * Chip Select Start Address Register (Table 82)
+ */
+
+#define S_BCM1480_MC_CS0_START              0
+#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
+#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
+#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
+
+#define S_BCM1480_MC_CS1_START              16
+#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
+#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
+#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
+
+#define S_BCM1480_MC_CS2_START              32
+#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
+#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
+#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
+
+#define S_BCM1480_MC_CS3_START              48
+#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
+#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
+#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 83)
+ */
+
+#define S_BCM1480_MC_CS0_END                0
+#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
+#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
+#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
+
+#define S_BCM1480_MC_CS1_END                16
+#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
+#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
+#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
+
+#define S_BCM1480_MC_CS2_END                32
+#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
+#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
+#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
+
+#define S_BCM1480_MC_CS3_END                48
+#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
+#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
+#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
+
+/*
+ * Row Address Bit Select Register 0 (Table 84)
+ */
+
+#define S_BCM1480_MC_ROW00                  0
+#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
+#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
+#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
+
+#define S_BCM1480_MC_ROW01                  8
+#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
+#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
+#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
+
+#define S_BCM1480_MC_ROW02                  16
+#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
+#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
+#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
+
+#define S_BCM1480_MC_ROW03                  24
+#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
+#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
+#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
+
+#define S_BCM1480_MC_ROW04                  32
+#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
+#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
+#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
+
+#define S_BCM1480_MC_ROW05                  40
+#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
+#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
+#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
+
+#define S_BCM1480_MC_ROW06                  48
+#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
+#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
+#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
+
+#define S_BCM1480_MC_ROW07                  56
+#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
+#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
+#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
+
+/*
+ * Row Address Bit Select Register 1 (Table 85)
+ */
+
+#define S_BCM1480_MC_ROW08                  0
+#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
+#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
+#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
+
+#define S_BCM1480_MC_ROW09                  8
+#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
+#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
+#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
+
+#define S_BCM1480_MC_ROW10                  16
+#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
+#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
+#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
+
+#define S_BCM1480_MC_ROW11                  24
+#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
+#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
+#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
+
+#define S_BCM1480_MC_ROW12                  32
+#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
+#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
+#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
+
+#define S_BCM1480_MC_ROW13                  40
+#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
+#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
+#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
+
+#define S_BCM1480_MC_ROW14                  48
+#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
+#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
+#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
+
+#define K_BCM1480_MC_ROWX_BIT_SPACING       8
+
+/*
+ * Column Address Bit Select Register 0 (Table 86)
+ */
+
+#define S_BCM1480_MC_COL00                  0
+#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
+#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
+#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
+
+#define S_BCM1480_MC_COL01                  8
+#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
+#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
+#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
+
+#define S_BCM1480_MC_COL02                  16
+#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
+#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
+#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
+
+#define S_BCM1480_MC_COL03                  24
+#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
+#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
+#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
+
+#define S_BCM1480_MC_COL04                  32
+#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
+#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
+#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
+
+#define S_BCM1480_MC_COL05                  40
+#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
+#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
+#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
+
+#define S_BCM1480_MC_COL06                  48
+#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
+#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
+#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
+
+#define S_BCM1480_MC_COL07                  56
+#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
+#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
+#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
+
+/*
+ * Column Address Bit Select Register 1 (Table 87)
+ */
+
+#define S_BCM1480_MC_COL08                  0
+#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
+#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
+#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
+
+#define S_BCM1480_MC_COL09                  8
+#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
+#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
+#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
+
+#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
+
+#define S_BCM1480_MC_COL11                  24
+#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
+#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
+#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
+
+#define S_BCM1480_MC_COL12                  32
+#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
+#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
+#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
+
+#define S_BCM1480_MC_COL13                  40
+#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
+#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
+#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
+
+#define S_BCM1480_MC_COL14                  48
+#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
+#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
+#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
+
+#define K_BCM1480_MC_COLX_BIT_SPACING       8
+
+/*
+ * CS0 and CS1 Bank Address Bit Select Register (Table 88)
+ */
+
+#define S_BCM1480_MC_CS01_BANK0             0
+#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
+#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
+#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
+
+#define S_BCM1480_MC_CS01_BANK1             8
+#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
+#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
+#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
+
+#define S_BCM1480_MC_CS01_BANK2             16
+#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
+#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
+#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
+
+/*
+ * CS2 and CS3 Bank Address Bit Select Register (Table 89)
+ */
+
+#define S_BCM1480_MC_CS23_BANK0             0
+#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
+#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
+#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
+
+#define S_BCM1480_MC_CS23_BANK1             8
+#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
+#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
+#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
+
+#define S_BCM1480_MC_CS23_BANK2             16
+#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
+#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
+#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
+
+#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
+
+/*
+ * DRAM Command Register (Table 90)
+ */
+
+#define S_BCM1480_MC_COMMAND                0
+#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
+#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
+#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
+
+#define K_BCM1480_MC_COMMAND_EMRS           0
+#define K_BCM1480_MC_COMMAND_MRS            1
+#define K_BCM1480_MC_COMMAND_PRE            2
+#define K_BCM1480_MC_COMMAND_AR             3
+#define K_BCM1480_MC_COMMAND_SETRFSH        4
+#define K_BCM1480_MC_COMMAND_CLRRFSH        5
+#define K_BCM1480_MC_COMMAND_SETPWRDN       6
+#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_COMMAND_EMRS2          8
+#define K_BCM1480_MC_COMMAND_EMRS3          9
+#define K_BCM1480_MC_COMMAND_ENABLE_MCLK    10
+#define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
+#endif
+
+#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
+#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
+#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
+#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
+#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
+#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
+#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
+#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
+#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
+#define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
+#define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
+#endif
+
+#define S_BCM1480_MC_CS0                    4
+#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
+
+#define M_BCM1480_MC_CS                  _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
+#define V_BCM1480_MC_CS(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
+#define G_BCM1480_MC_CS(x)               _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
+
+#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
+
+/*
+ * DRAM Mode Register (Table 91)
+ */
+
+#define S_BCM1480_MC_EMODE                  0
+#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
+#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
+
+#define S_BCM1480_MC_MODE                   16
+#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
+#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
+
+#define S_BCM1480_MC_DRAM_TYPE              32
+#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
+#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
+#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
+
+#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
+#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_DRAM_TYPE_DDR2         2
+#endif
+
+#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0
+
+#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
+#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_DRAM_TYPE_DDR2         V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
+#endif
+
+#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
+
+#define S_BCM1480_MC_PG_POLICY              40
+#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
+#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
+#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
+
+#define K_BCM1480_MC_PG_POLICY_CLOSED       0
+#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
+
+#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
+#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_2T_CMD                 _SB_MAKEMASK1(42)
+#define M_BCM1480_MC_ECC_COR_DIS            _SB_MAKEMASK1(43)
+#endif
+
+#define V_BCM1480_MC_DRAMMODE_DEFAULT   V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
+                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+/*
+ * Memory Clock Configuration Register (Table 92)
+ */
+
+#define S_BCM1480_MC_CLK_RATIO              0
+#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
+#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
+
+#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
+
+#define S_BCM1480_MC_REF_RATE               8
+#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
+#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
+#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
+
+#define K_BCM1480_MC_REF_RATE_100MHz        0x31
+#define K_BCM1480_MC_REF_RATE_200MHz        0x62
+#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
+
+#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
+#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
+#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
+#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_AUTO_REF_DIS           _SB_MAKEMASK1(16)
+#endif
+
+/*
+ * ODT Register (Table 99)
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_RD_ODT0_CS0            _SB_MAKEMASK1(0)
+#define M_BCM1480_MC_RD_ODT0_CS2            _SB_MAKEMASK1(1)
+#define M_BCM1480_MC_RD_ODT0_CS4            _SB_MAKEMASK1(2)
+#define M_BCM1480_MC_RD_ODT0_CS6            _SB_MAKEMASK1(3)
+#define M_BCM1480_MC_WR_ODT0_CS0            _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_WR_ODT0_CS2            _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_WR_ODT0_CS4            _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_WR_ODT0_CS6            _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_RD_ODT2_CS0            _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RD_ODT2_CS2            _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_RD_ODT2_CS4            _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_RD_ODT2_CS6            _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_WR_ODT2_CS0            _SB_MAKEMASK1(12)
+#define M_BCM1480_MC_WR_ODT2_CS2            _SB_MAKEMASK1(13)
+#define M_BCM1480_MC_WR_ODT2_CS4            _SB_MAKEMASK1(14)
+#define M_BCM1480_MC_WR_ODT2_CS6            _SB_MAKEMASK1(15)
+#define M_BCM1480_MC_RD_ODT4_CS0            _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_RD_ODT4_CS2            _SB_MAKEMASK1(17)
+#define M_BCM1480_MC_RD_ODT4_CS4            _SB_MAKEMASK1(18)
+#define M_BCM1480_MC_RD_ODT4_CS6            _SB_MAKEMASK1(19)
+#define M_BCM1480_MC_WR_ODT4_CS0            _SB_MAKEMASK1(20)
+#define M_BCM1480_MC_WR_ODT4_CS2            _SB_MAKEMASK1(21)
+#define M_BCM1480_MC_WR_ODT4_CS4            _SB_MAKEMASK1(22)
+#define M_BCM1480_MC_WR_ODT4_CS6            _SB_MAKEMASK1(23)
+#define M_BCM1480_MC_RD_ODT6_CS0            _SB_MAKEMASK1(24)
+#define M_BCM1480_MC_RD_ODT6_CS2            _SB_MAKEMASK1(25)
+#define M_BCM1480_MC_RD_ODT6_CS4            _SB_MAKEMASK1(26)
+#define M_BCM1480_MC_RD_ODT6_CS6            _SB_MAKEMASK1(27)
+#define M_BCM1480_MC_WR_ODT6_CS0            _SB_MAKEMASK1(28)
+#define M_BCM1480_MC_WR_ODT6_CS2            _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_WR_ODT6_CS4            _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_WR_ODT6_CS6            _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CS_ODD_ODT_EN          _SB_MAKEMASK1(32)
+
+#define S_BCM1480_MC_ODT0                   0
+#define M_BCM1480_MC_ODT0                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
+#define V_BCM1480_MC_ODT0(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
+
+#define S_BCM1480_MC_ODT2                   8
+#define M_BCM1480_MC_ODT2                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
+#define V_BCM1480_MC_ODT2(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
+
+#define S_BCM1480_MC_ODT4                   16
+#define M_BCM1480_MC_ODT4                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
+#define V_BCM1480_MC_ODT4(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
+
+#define S_BCM1480_MC_ODT6                   24
+#define M_BCM1480_MC_ODT6                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
+#define V_BCM1480_MC_ODT6(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
+#endif
+
+/*
+ * Memory DLL Configuration Register (Table 93)
+ */
+
+#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
+#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_ADDR_FREQ_RANGE            8
+#define M_BCM1480_MC_ADDR_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT    V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_ADDR_FINE_ADJ          8
+#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQI_COARSE_ADJ         16
+#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQI_FREQ_RANGE             24
+#define M_BCM1480_MC_DQI_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define G_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQI_FINE_ADJ           24
+#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
+#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQO_COARSE_ADJ         32
+#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQO_FREQ_RANGE             40
+#define M_BCM1480_MC_DQO_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define G_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQO_FINE_ADJ           40
+#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
+#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_PDSEL            44
+#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
+#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
+
+#define M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
+#define M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
+#endif
+
+#define S_BCM1480_MC_DLL_DEFAULT           48
+#define M_BCM1480_MC_DLL_DEFAULT           _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
+#define G_BCM1480_MC_DLL_DEFAULT(x)        _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT   V_BCM1480_MC_DLL_DEFAULT(0x10)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_REGCTRL          54
+#define M_BCM1480_MC_DLL_REGCTRL          _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
+#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
+#endif
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_FREQ_RANGE             56
+#define M_BCM1480_MC_DLL_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define G_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DLL_STEP_SIZE          56
+#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
+#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_BGCTRL   60
+#define M_BCM1480_MC_DLL_BGCTRL           _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
+#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
+#endif
+
+#define M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
+
+/*
+ * Memory Drive Configuration Register (Table 94)
+ */
+
+#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
+#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
+
+#define S_BCM1480_MC_RTT_BYP_PULLUP         6
+#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
+
+#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
+#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
+#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN    20
+#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
+#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
+
+#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
+#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
+
+#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
+#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
+
+/*
+ * ECC Test Data Register (Table 95)
+ */
+
+#define S_BCM1480_MC_DATA_INVERT            0
+#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * ECC Test ECC Register (Table 96)
+ */
+
+#define S_BCM1480_MC_ECC_INVERT             0
+#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * SDRAM Timing Register  (Table 97)
+ */
+
+#define S_BCM1480_MC_tRCD                   0
+#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
+#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
+#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
+#define K_BCM1480_MC_tRCD_DEFAULT           3
+#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
+
+#define S_BCM1480_MC_tCL                    4
+#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
+#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
+#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
+#define K_BCM1480_MC_tCL_DEFAULT            2
+#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
+
+#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
+
+#define S_BCM1480_MC_tWR                    9
+#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
+#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
+#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
+#define K_BCM1480_MC_tWR_DEFAULT            2
+#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
+
+#define S_BCM1480_MC_tCwD                   12
+#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
+#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
+#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
+#define K_BCM1480_MC_tCwD_DEFAULT           1
+#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
+
+#define S_BCM1480_MC_tRP                    16
+#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
+#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
+#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
+#define K_BCM1480_MC_tRP_DEFAULT            4
+#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
+
+#define S_BCM1480_MC_tRRD                   20
+#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
+#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
+#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
+#define K_BCM1480_MC_tRRD_DEFAULT           2
+#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
+
+#define S_BCM1480_MC_tRCw                   24
+#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
+#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
+#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
+#define K_BCM1480_MC_tRCw_DEFAULT           10
+#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
+
+#define S_BCM1480_MC_tRCr                   32
+#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
+#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
+#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
+#define K_BCM1480_MC_tRCr_DEFAULT           9
+#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_tFAW                   40
+#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
+#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
+#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
+#define K_BCM1480_MC_tFAW_DEFAULT           0
+#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
+#endif
+
+#define S_BCM1480_MC_tRFC                   48
+#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
+#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
+#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
+#define K_BCM1480_MC_tRFC_DEFAULT           12
+#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
+
+#define S_BCM1480_MC_tFIFO                  56
+#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
+#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
+#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
+#define K_BCM1480_MC_tFIFO_DEFAULT          0
+#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
+
+#define S_BCM1480_MC_tW2R                  58
+#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
+#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
+#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
+#define K_BCM1480_MC_tW2R_DEFAULT          1
+#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
+
+#define S_BCM1480_MC_tR2W                  60
+#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
+#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
+#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
+#define K_BCM1480_MC_tR2W_DEFAULT          0
+#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
+
+#define M_BCM1480_MC_tR2R                   _SB_MAKEMASK1(62)
+
+#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
+                                     V_BCM1480_MC_tFIFO_DEFAULT | \
+                                     V_BCM1480_MC_tR2W_DEFAULT | \
+                                     V_BCM1480_MC_tW2R_DEFAULT | \
+                                     V_BCM1480_MC_tRFC_DEFAULT | \
+                                     V_BCM1480_MC_tRCr_DEFAULT | \
+                                     V_BCM1480_MC_tRCw_DEFAULT | \
+                                     V_BCM1480_MC_tRRD_DEFAULT | \
+                                     V_BCM1480_MC_tRP_DEFAULT | \
+                                     V_BCM1480_MC_tCwD_DEFAULT | \
+                                     V_BCM1480_MC_tWR_DEFAULT | \
+                                     M_BCM1480_MC_tCrDh | \
+                                     V_BCM1480_MC_tCL_DEFAULT | \
+                                     V_BCM1480_MC_tRCD_DEFAULT)
+
+/*
+ * SDRAM Timing Register 2
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+
+#define S_BCM1480_MC_tAL                   0
+#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
+#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
+#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
+#define K_BCM1480_MC_tAL_DEFAULT           0
+#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
+
+#define S_BCM1480_MC_tRTP                   4
+#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
+#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
+#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
+#define K_BCM1480_MC_tRTP_DEFAULT           2
+#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
+
+#define S_BCM1480_MC_tW2W                   8
+#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
+#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
+#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
+#define K_BCM1480_MC_tW2W_DEFAULT           0
+#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
+
+#define S_BCM1480_MC_tRAP                   12
+#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
+#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
+#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
+#define K_BCM1480_MC_tRAP_DEFAULT           0
+#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
+
+#endif
+
+
+
+/*
+ * Global Registers: single instances per BCM1480
+ */
+
+/*
+ * Global Configuration Register (Table 99)
+ */
+
+#define S_BCM1480_MC_BLK_SET_MARK           8
+#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
+#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
+#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
+
+#define S_BCM1480_MC_BLK_CLR_MARK           12
+#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
+#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
+#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
+
+#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
+
+#define S_BCM1480_MC_MAX_AGE                20
+#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
+#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
+#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
+
+#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
+
+#define S_BCM1480_MC_SLEW                   33
+#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
+#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
+#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
+
+#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
+
+/*
+ * Global Channel Interleave Register (Table 100)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+
+#define S_BCM1480_MC_INTLV_MODE             16
+#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
+#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
+#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
+
+#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
+#define K_BCM1480_MC_INTLV_MODE_01          0x1
+#define K_BCM1480_MC_INTLV_MODE_23          0x2
+#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
+#define K_BCM1480_MC_INTLV_MODE_0123        0x4
+
+#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
+#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
+#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
+#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
+#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
+
+/*
+ * ECC Status Register
+ */
+
+#define S_BCM1480_MC_ECC_ERR_ADDR           0
+#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
+#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
+#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
+#endif
+
+#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
+#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
+#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
+
+/*
+ * Global ECC Address Register (Table 102)
+ */
+
+#define S_BCM1480_MC_ECC_CORR_ADDR          0
+#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
+#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
+#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
+
+/*
+ * Global ECC Correction Register (Table 103)
+ */
+
+#define S_BCM1480_MC_ECC_CORRECT            0
+#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
+#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
+#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
+
+/*
+ * Global ECC Performance Counters Control Register (Table 104)
+ */
+
+#define S_BCM1480_MC_CHANNEL_SELECT         0
+#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
+#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
+#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
+#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
+#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
+#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
+#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
+
+#endif /* _BCM1480_MC_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
new file mode 100644
index 000000000..ef12ede26
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
@@ -0,0 +1,889 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
+    *
+    *  Register Definitions                     File: bcm1480_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the BCM1280 and BCM1480.
+    *
+    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+#ifndef _BCM1480_REGS_H
+#define _BCM1480_REGS_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's registers since a great deal of the 1480's
+    *  functions are the same as the BCM1250.
+    ********************************************************************* */
+
+#include <asm/sibyte/sb1250_regs.h>
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  Register addresses are grouped by function and follow the order
+    *  of the User Manual.
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the BCM1X55/BCM1X80
+    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+
+/*  *********************************************************************
+    * Memory Controller Registers (Section 6)
+    ********************************************************************* */
+
+#define A_BCM1480_MC_BASE_0                 0x0010050000
+#define A_BCM1480_MC_BASE_1                 0x0010051000
+#define A_BCM1480_MC_BASE_2                 0x0010052000
+#define A_BCM1480_MC_BASE_3                 0x0010053000
+#define BCM1480_MC_REGISTER_SPACING         0x1000
+
+#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
+#define A_BCM1480_MC_REGISTER(ctlid, reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
+
+#define R_BCM1480_MC_CONFIG                 0x0000000100
+#define R_BCM1480_MC_CS_START               0x0000000120
+#define R_BCM1480_MC_CS_END                 0x0000000140
+#define S_BCM1480_MC_CS_STARTEND            24
+
+#define R_BCM1480_MC_CS01_ROW0              0x0000000180
+#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
+#define R_BCM1480_MC_CS23_ROW0              0x0000000200
+#define R_BCM1480_MC_CS23_ROW1              0x0000000220
+#define R_BCM1480_MC_CS01_COL0              0x0000000280
+#define R_BCM1480_MC_CS01_COL1              0x00000002A0
+#define R_BCM1480_MC_CS23_COL0              0x0000000300
+#define R_BCM1480_MC_CS23_COL1              0x0000000320
+
+#define R_BCM1480_MC_CSX_BASE               0x0000000180
+#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
+#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
+
+#define R_BCM1480_MC_CS01_BA                0x0000000380
+#define R_BCM1480_MC_CS23_BA                0x00000003A0
+#define R_BCM1480_MC_DRAMCMD                0x0000000400
+#define R_BCM1480_MC_DRAMMODE               0x0000000420
+#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
+#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
+#define R_BCM1480_MC_TEST_DATA              0x0000000480
+#define R_BCM1480_MC_TEST_ECC               0x00000004A0
+#define R_BCM1480_MC_TIMING1                0x00000004C0
+#define R_BCM1480_MC_TIMING2                0x00000004E0
+#define R_BCM1480_MC_DLL_CFG                0x0000000500
+#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define R_BCM1480_MC_ODT                    0x0000000460
+#define R_BCM1480_MC_ECC_STATUS             0x0000000540
+#endif
+
+/* Global registers (single instance) */
+#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
+#define A_BCM1480_MC_GLB_INTLV              0x0010054120
+#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
+#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
+#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
+#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
+
+/*  *********************************************************************
+    * L2 Cache Control Registers (Section 5)
+    ********************************************************************* */
+
+#define A_BCM1480_L2_BASE                   0x0010040000
+
+#define A_BCM1480_L2_READ_TAG               0x0010040018
+#define A_BCM1480_L2_ECC_TAG                0x0010040038
+#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
+#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
+#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
+#define A_BCM1480_L2_MISC_CONFIG            0x0010040040        /* x040 */
+#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060        /* x060 */
+#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080        /* x080 */
+#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0        /* x0A0 */
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100        /* x100 */
+#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120        /* x120 */
+#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140        /* x140 */
+#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160        /* x160 */
+#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0        /* xxC0 */
+#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0        /* xxE0 */
+#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
+#define A_BCM1480_L2_BANK_BASE              0x00D0300000
+#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
+#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
+
+
+/*  *********************************************************************
+    * PCI-X Interface Registers (Section 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PCI_BASE                  0x0010061400
+
+#define A_BCM1480_PCI_RESET                 0x0010061400
+#define A_BCM1480_PCI_DLL                   0x0010061500
+
+#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
+
+/*  *********************************************************************
+    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
+    ********************************************************************* */
+
+/* No register changes with Rev.C BCM1250, but one additional MAC */
+
+#define A_BCM1480_MAC_BASE_2        0x0010066000
+
+#ifndef A_MAC_BASE_2
+#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
+#endif
+
+#define A_BCM1480_MAC_BASE_3        0x0010067000
+#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
+
+#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
+
+#ifndef R_MAC_DMA_OODPKTLOST
+#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
+#endif
+
+
+/*  *********************************************************************
+    * DUART Registers (Section 14)
+    ********************************************************************* */
+
+/* No significant differences from BCM1250, two DUARTs */
+
+/*  Conventions, per user manual:
+ *     DUART    generic, channels A,B,C,D
+ *     DUART0   implementing channels A,B
+ *     DUART1   inplementing channels C,D
+ */
+
+#define BCM1480_DUART_NUM_PORTS           4
+
+#define A_BCM1480_DUART0                    0x0010060000
+#define A_BCM1480_DUART1                    0x0010060400
+#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
+
+#define BCM1480_DUART_CHANREG_SPACING       0x100
+#define A_BCM1480_DUART_CHANREG(chan, reg)                              \
+        (A_BCM1480_DUART(chan) +                                        \
+         BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
+#define A_BCM1480_DUART_CTRLREG(chan, reg)                              \
+        (A_BCM1480_DUART(chan) +                                        \
+         BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
+
+#define DUART_IMRISR_SPACING        0x20
+#define DUART_INCHNG_SPACING        0x10
+
+#define R_BCM1480_DUART_IMRREG(chan)                                    \
+        (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_ISRREG(chan)                                    \
+        (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_INCHREG(chan)                                   \
+        (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
+
+#define A_BCM1480_DUART_IMRREG(chan)                                    \
+        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
+#define A_BCM1480_DUART_ISRREG(chan)                                    \
+        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan)))
+
+#define A_BCM1480_DUART_IN_PORT(chan)                                   \
+        (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT))
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
+#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
+#define A_BCM1480_DUART_STATUS_C            0x0010060420
+#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
+#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
+#define A_BCM1480_DUART_CMD_C               0x0010060450
+#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
+#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
+#define A_BCM1480_DUART_OPCR_C              0x0010060480
+#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
+
+#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
+#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
+#define A_BCM1480_DUART_STATUS_D            0x0010060520
+#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
+#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
+#define A_BCM1480_DUART_CMD_D               0x0010060550
+#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
+#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
+#define A_BCM1480_DUART_OPCR_D              0x0010060580
+#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
+
+#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
+#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
+#define A_BCM1480_DUART_ISR_C               0x0010060620
+#define A_BCM1480_DUART_IMR_C               0x0010060630
+#define A_BCM1480_DUART_ISR_D               0x0010060640
+#define A_BCM1480_DUART_IMR_D               0x0010060650
+#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
+#define A_BCM1480_DUART_OPCR_CD             0x0010060670
+#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
+#define A_BCM1480_DUART_ISR_CD              0x0010060690
+#define A_BCM1480_DUART_IMR_CD              0x00100606A0
+#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
+#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
+#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
+#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
+
+
+/*  *********************************************************************
+    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
+    ********************************************************************* */
+
+#define A_BCM1480_IO_PCMCIA_CFG_B       0x0010061A58
+#define A_BCM1480_IO_PCMCIA_STATUS_B    0x0010061A68
+
+/*  *********************************************************************
+    * GPIO Registers (Section 17)
+    ********************************************************************* */
+
+/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
+
+#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
+#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
+
+#define A_GPIO_INT_ADD_TYPE     A_BCM1480_GPIO_INT_ADD_TYPE
+#define R_GPIO_INT_ADD_TYPE     R_BCM1480_GPIO_INT_ADD_TYPE
+
+/*  *********************************************************************
+    * SMBus Registers (Section 18)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * Timer Registers (Sections 4.6)
+    ********************************************************************* */
+
+/* BCM1480 has two additional watchdogs */
+
+/* Watchdog timers */
+
+#define A_BCM1480_SCD_WDOG_2                0x0010022050
+#define A_BCM1480_SCD_WDOG_3                0x0010022150
+
+#define BCM1480_SCD_NUM_WDOGS               4
+
+#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
+#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
+
+#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
+#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
+#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
+
+#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
+#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
+#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
+
+/* BCM1480 has two additional compare registers */
+
+#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT         A_SCD_ZBBUS_CYCLE_COUNT
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
+
+/*  *********************************************************************
+    * System Control Registers (Section 4.2)
+    ********************************************************************* */
+
+/* Scratch register in different place */
+
+#define A_BCM1480_SCD_SCRATCH           0x100200A0
+
+/*  *********************************************************************
+    * System Address Trap Registers (Section 4.9)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * System Interrupt Mapper Registers (Sections 4.3-4.5)
+    ********************************************************************* */
+
+#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
+#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
+#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
+#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
+#define BCM1480_IMR_REGISTER_SPACING        0x2000
+#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
+
+#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
+#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
+
+/* Most IMR registers are 128 bits, implemented as non-contiguous
+   64-bit registers high (_H) and low (_L) */
+#define BCM1480_IMR_HL_SPACING                  0x1000
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
+#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
+#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
+#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
+#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
+#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
+#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
+#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
+#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
+#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
+#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
+#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
+#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
+#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
+                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
+#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
+
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008
+
+/*
+ * these macros work together to build the address of a mailbox
+ * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
+ * for mbox_0_set_cpu2 returns 0x00100240C8
+ */
+#define R_BCM1480_IMR_MAILBOX_CPU         0x00
+#define R_BCM1480_IMR_MAILBOX_SET         0x08
+#define R_BCM1480_IMR_MAILBOX_CLR         0x10
+#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
+#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
+    (A_BCM1480_IMR_CPU0_BASE + \
+     (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
+     (cpu * BCM1480_IMR_REGISTER_SPACING) + \
+     (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
+
+/*  *********************************************************************
+    * System Performance Counter Registers (Section 4.7)
+    ********************************************************************* */
+
+/* BCM1480 has four more performance counter registers, and two control
+   registers. */
+
+#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
+
+#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
+#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
+#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
+
+#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
+#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
+#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
+#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
+
+#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
+#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
+#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
+#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
+
+#define BCM1480_SCD_NUM_PERF_CNT 8
+#define BCM1480_SCD_PERF_CNT_SPACING 8
+#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
+
+/*  *********************************************************************
+    * System Bus Watcher Registers (Section 4.8)
+    ********************************************************************* */
+
+
+/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
+
+#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
+
+/*  *********************************************************************
+    * System Debug Controller Registers (Section 19)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * System Trace Unit Registers (Sections 4.10)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * Data Mover DMA Registers (Section 10.7)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+
+/*  *********************************************************************
+    * HyperTransport Interface Registers (Section 8)
+    ********************************************************************* */
+
+#define BCM1480_HT_NUM_PORTS               3
+#define BCM1480_HT_PORT_SPACING            0x800
+#define A_BCM1480_HT_PORT_HEADER(x)        (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
+
+#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
+#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
+#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
+#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
+
+
+/*  *********************************************************************
+    * Node Controller Registers (Section 9)
+    ********************************************************************* */
+
+#define A_BCM1480_NC_BASE                   0x00DFBD0000
+
+#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
+#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
+#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
+#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
+#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
+#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
+#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
+
+#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
+#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
+#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
+#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
+
+#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
+#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
+#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
+#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
+#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
+#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
+#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
+#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
+#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
+#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
+#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
+#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
+#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
+
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
+
+
+/*  *********************************************************************
+    * H&R Block Configuration Registers (Section 12.4)
+    ********************************************************************* */
+
+#define A_BCM1480_HR_BASE_0                 0x00DF820000
+#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
+#define A_BCM1480_HR_BASE_2                 0x00DF920000
+#define BCM1480_HR_REGISTER_SPACING         0x80000
+
+#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
+#define A_BCM1480_HR_REGISTER(idx, reg)      (A_BCM1480_HR_BASE(idx) + (reg))
+
+#define R_BCM1480_HR_CFG                    0x0000000000
+
+#define R_BCM1480_HR_MAPPING                0x0000010010
+
+#define BCM1480_HR_RULE_SPACING             0x0000000010
+#define BCM1480_HR_NUM_RULES                16
+#define BCM1480_HR_OP_OFFSET                0x0000000100
+#define BCM1480_HR_TYPE_OFFSET              0x0000000108
+#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+
+#define BCM1480_HR_LEAF_SPACING             0x0000000010
+#define BCM1480_HR_NUM_LEAVES               10
+#define BCM1480_HR_LEAF_OFFSET              0x0000000300
+#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
+
+#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
+
+#define BCM1480_HR_PATH_SPACING             0x0000000010
+#define BCM1480_HR_NUM_PATHS                16
+#define BCM1480_HR_PATH_OFFSET              0x0000000600
+#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
+
+#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
+
+#define BCM1480_HR_ROUTE_SPACING            8
+#define BCM1480_HR_NUM_ROUTES               512
+#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
+#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
+
+
+/* checked to here - ehs */
+/*  *********************************************************************
+    * Packet Manager DMA Registers (Section 12.5)
+    ********************************************************************* */
+
+#define A_BCM1480_PM_BASE                   0x0010056000
+
+#define A_BCM1480_PMI_LCL_0                 0x0010058000
+#define A_BCM1480_PMO_LCL_0                 0x001005C000
+#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
+
+#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
+#define BCM1480_PM_NUM_CHANNELS             32
+
+#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMI_LCL_REGISTER(idx, reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMO_LCL_REGISTER(idx, reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
+
+#define BCM1480_PM_INT_PACKING              8
+#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
+#define BCM1480_PM_INT_NUM_FUNCTIONS        3
+
+/*
+ * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
+ */
+
+#define R_BCM1480_PM_BASE_SIZE              0x0000000000
+#define R_BCM1480_PM_CNT                    0x0000000008
+#define R_BCM1480_PM_PFCNT                  0x0000000010
+#define R_BCM1480_PM_LAST                   0x0000000018
+#define R_BCM1480_PM_PFINDX                 0x0000000020
+#define R_BCM1480_PM_INT_WMK                0x0000000028
+#define R_BCM1480_PM_CONFIG0                0x0000000030
+#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
+#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
+#define R_BCM1480_PM_INT_CNFG               0x0000000088
+#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
+#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
+#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
+
+/*
+ * Global Registers (Not Channelized)
+ */
+
+#define A_BCM1480_PMI_GLB_0                 0x0010056000
+#define A_BCM1480_PMO_GLB_0                 0x0010057000
+
+/*
+ * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
+ */
+
+#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
+
+#define A_BCM1480_PM_PMO_MAPPING        (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
+
+/*
+ * Interrupt mapping registers
+ */
+
+
+#define A_BCM1480_PMI_INT_0                 0x0010056800
+#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_INT_0                 0x0010057800
+#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
+
+/*
+ * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
+ */
+
+#define R_BCM1480_PM_INT_ST                 0x0000000000
+#define R_BCM1480_PM_INT_MSK                0x0000000040
+#define R_BCM1480_PM_INT_CLR                0x0000000080
+#define R_BCM1480_PM_MRGD_INT               0x00000000C0
+
+/*
+ * Debug registers (global)
+ */
+
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
+#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
+#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
+#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
+#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
+
+/*  *********************************************************************
+    *  Switch performance counters
+    ********************************************************************* */
+
+#define A_BCM1480_SWPERF_CFG    0xdfb91800
+#define A_BCM1480_SWPERF_CNT0   0xdfb91880
+#define A_BCM1480_SWPERF_CNT1   0xdfb91888
+#define A_BCM1480_SWPERF_CNT2   0xdfb91890
+#define A_BCM1480_SWPERF_CNT3   0xdfb91898
+
+
+/*  *********************************************************************
+    *  Switch Trace Unit
+    ********************************************************************* */
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL_0         0xDFB91000
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0      0xDFB91100
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0       0xDFB91108
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0       0xDFB91200
+#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0        0xDFB91208
+#define A_BCM1480_SWTRC_EVENT_0                 0xDFB91300
+#define A_BCM1480_SWTRC_SEQUENCE_0              0xDFB91400
+
+#define A_BCM1480_SWTRC_CFG                     0xDFB91500
+#define A_BCM1480_SWTRC_READ                    0xDFB91508
+
+#define A_BCM1480_SWDEBUG_SCHEDSTOP             0xDFB92000
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
+#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
+#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
+
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
+
+
+
+/*  *********************************************************************
+    *  High-Speed Port Registers (Section 13)
+    ********************************************************************* */
+
+#define A_BCM1480_HSP_BASE_0                0x00DF810000
+#define A_BCM1480_HSP_BASE_1                0x00DF890000
+#define A_BCM1480_HSP_BASE_2                0x00DF910000
+#define BCM1480_HSP_REGISTER_SPACING        0x80000
+
+#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
+#define A_BCM1480_HSP_REGISTER(idx, reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
+
+#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
+#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
+
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
+
+#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
+#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
+#define R_BCM1480_HSP_RX_TEST                 0x0000000810
+#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
+#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
+#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
+#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
+#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
+
+#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
+
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
+
+/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
+
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
+
+#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
+#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
+#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
+#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
+#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
+#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
+#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
+
+#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
+#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
+#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
+
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
+#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
+#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
+
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
+#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
+
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
+#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
+
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
+
+#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
+#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
+#define R_BCM1480_HSP_TX_TEST                 0x0000040810
+
+#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
+#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
+#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
+#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
+#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
+#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
+#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
+
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
+
+#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
+#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
+
+
+
+/*  *********************************************************************
+    *  Physical Address Map (Table 10 and Figure 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
+#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
+#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
+#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
+#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
+#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
+#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
+
+
+/*  *********************************************************************
+    *  L2 Cache as RAM (Table 54)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
+#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
+#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
+#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
+#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
+#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
+#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
+#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
+
+#endif /* _BCM1480_REGS_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
new file mode 100644
index 000000000..87f37086d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
@@ -0,0 +1,393 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  BCM1280/BCM1400 Board Support Package
+    *
+    *  SCD Constants and Macros                     File: bcm1480_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module.
+    *
+    *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003,2004,2005
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+#ifndef _BCM1480_SCD_H
+#define _BCM1480_SCD_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's SCD since lots of stuff is the same.
+    ********************************************************************* */
+
+#include <asm/sibyte/sb1250_scd.h>
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Identification and Revision Register (Table 12)
+ * Register: SCD_SYSTEM_REVISION
+ * This register is field compatible with the 1250.
+ */
+
+/*
+ * New part definitions
+ */
+
+#define K_SYS_PART_BCM1480          0x1406
+#define K_SYS_PART_BCM1280          0x1206
+#define K_SYS_PART_BCM1455          0x1407
+#define K_SYS_PART_BCM1255          0x1257
+#define K_SYS_PART_BCM1158          0x1156
+
+/*
+ * Manufacturing Information Register (Table 14)
+ * Register: SCD_SYSTEM_MANUF
+ */
+
+/*
+ * System Configuration Register (Table 15)
+ * Register: SCD_SYSTEM_CFG
+ * Entire register is different from 1250, all new constants below
+ */
+
+#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
+#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
+#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
+#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
+#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
+#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
+
+#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
+#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
+#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
+#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
+
+#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
+#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
+#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
+#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
+
+#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
+
+#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
+#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
+#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
+#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
+#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
+#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
+#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
+
+#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
+#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
+#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
+#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SYS_CONFIG                26
+#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
+#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
+#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
+
+#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32, 15)
+
+#define S_BCM1480_SYS_NODEID                47
+#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
+#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
+#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
+
+#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
+#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
+#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
+#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
+#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
+#define S_BCM1480_SYS_DISABLECPU0           56
+#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
+#define S_BCM1480_SYS_DISABLECPU1           57
+#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
+#define S_BCM1480_SYS_DISABLECPU2           58
+#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
+#define S_BCM1480_SYS_DISABLECPU3           59
+#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
+
+#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
+#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
+#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
+#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+
+/*
+ * Scratch Register (Table 16)
+ * Register: SCD_SYSTEM_SCRATCH
+ * Same as BCM1250
+ */
+
+
+/*
+ * Mailbox Registers (Table 17)
+ * Registers: SCD_MBOX_{0,1}_CPU_x
+ * Same as BCM1250
+ */
+
+
+/*
+ * See bcm1480_int.h for interrupt mapper registers.
+ */
+
+
+/*
+ * Watchdog Timer Initial Count Registers (Table 23)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ *
+ * The watchdogs are almost the same as the 1250, except
+ * the configuration register has more bits to control the
+ * other CPUs.
+ */
+
+
+/*
+ * Watchdog Timer Configuration Registers (Table 25)
+ * Registers: SCD_WDOG_CFG_x
+ */
+
+#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
+
+#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
+#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
+
+#define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
+#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
+#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
+#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
+#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
+#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
+
+
+#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
+
+/*
+ * General Timer Initial Count Registers (Table 26)
+ * Registers: SCD_TIMER_INIT_x
+ *
+ * The timer registers are the same as the BCM1250
+ */
+
+
+/*
+ * ZBbus Count Register (Table 29)
+ * Register: ZBBUS_CYCLE_COUNT
+ *
+ * Same as BCM1250
+ */
+
+/*
+ * ZBbus Compare Registers (Table 30)
+ * Registers: ZBBUS_CYCLE_CPx
+ *
+ * Same as BCM1250
+ */
+
+
+/*
+ * System Performance Counter Configuration Register (Table 31)
+ * Register: PERF_CNT_CFG_0
+ *
+ * SPC_CFG_SRC[0-3] is the same as the 1250.
+ * SPC_CFG_SRC[4-7] only exist on the 1480
+ * The clear/enable bits are in different locations on the 1250 and 1480.
+ */
+
+#define S_SPC_CFG_SRC4              32
+#define M_SPC_CFG_SRC4              _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
+#define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
+#define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
+
+#define S_SPC_CFG_SRC5              40
+#define M_SPC_CFG_SRC5              _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
+#define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
+#define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
+
+#define S_SPC_CFG_SRC6              48
+#define M_SPC_CFG_SRC6              _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
+#define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
+#define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
+
+#define S_SPC_CFG_SRC7              56
+#define M_SPC_CFG_SRC7              _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
+#define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
+#define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
+
+/*
+ * System Performance Counter Control Register (Table 32)
+ * Register: PERF_CNT_CFG_1
+ * BCM1480 specific
+ */
+#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)
+#define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_SPC_CFG_CLEAR                 M_BCM1480_SPC_CFG_CLEAR
+#define M_SPC_CFG_ENABLE                M_BCM1480_SPC_CFG_ENABLE
+#endif
+
+/*
+ * System Performance Counters (Table 33)
+ * Registers: PERF_CNT_x
+ */
+
+#define S_BCM1480_SPC_CNT_COUNT             0
+#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
+#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
+#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
+
+#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
+
+
+/*
+ * Bus Watcher Error Status Register (Tables 36, 37)
+ * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher Error Data Registers (Table 38)
+ * Registers: BUS_ERR_DATA_x
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher L2 ECC Counter Register (Table 39)
+ * Register: BUS_L2_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Bus Watcher Memory and I/O Error Counter Register (Table 40)
+ * Register: BUS_MEM_IO_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Address Trap Registers
+ *
+ * Register layout same as BCM1250, almost.  The bus agents
+ * are different, and the address trap configuration bits are
+ * slightly different.
+ */
+
+#define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
+#define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
+
+#define S_BCM1480_ATRAP_CFG_CNT            0
+#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
+#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
+#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
+
+#define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_BCM1480_ATRAP_CFG_AGENTID     8
+#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
+#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
+#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
+
+
+#define K_BCM1480_BUS_AGENT_CPU0            0
+#define K_BCM1480_BUS_AGENT_CPU1            1
+#define K_BCM1480_BUS_AGENT_NC              2
+#define K_BCM1480_BUS_AGENT_IOB             3
+#define K_BCM1480_BUS_AGENT_SCD             4
+#define K_BCM1480_BUS_AGENT_L2C             6
+#define K_BCM1480_BUS_AGENT_MC              7
+#define K_BCM1480_BUS_AGENT_CPU2            8
+#define K_BCM1480_BUS_AGENT_CPU3            9
+#define K_BCM1480_BUS_AGENT_PM              10
+
+#define S_BCM1480_ATRAP_CFG_CATTR           12
+#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
+#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
+#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
+
+#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
+#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
+#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
+#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
+
+#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
+
+
+/*
+ * Trace Event Registers (Table 47)
+ * Same as BCM1250.
+ */
+
+/*
+ * Trace Sequence Control Registers (Table 48)
+ * Registers: TRACE_SEQUENCE_x
+ *
+ * Same as BCM1250 except for two new fields.
+ */
+
+
+#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
+#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
+
+/*
+ * Trace Control Register (Table 49)
+ * Register: TRACE_CFG
+ *
+ * BCM1480 changes to this register (other than location of the CUR_ADDR field)
+ * are defined below.
+ */
+
+#define S_BCM1480_SCD_TRACE_CFG_MODE        16
+#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
+
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
+#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
+
+#endif /* _BCM1480_SCD_H */
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
new file mode 100644
index 000000000..86c876196
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ */
+#ifndef __ASM_SIBYTE_BIGSUR_H
+#define __ASM_SIBYTE_BIGSUR_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/bcm1480_int.h>
+
+#ifdef CONFIG_SIBYTE_BIGSUR
+#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_BIGSUR_H */
diff --git a/arch/mips/include/asm/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h
new file mode 100644
index 000000000..20fe2f16c
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/board.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ */
+
+#ifndef _SIBYTE_BOARD_H
+#define _SIBYTE_BOARD_H
+
+#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
+    defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
+#include <asm/sibyte/swarm.h>
+#endif
+
+#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
+#include <asm/sibyte/sentosa.h>
+#endif
+
+#ifdef CONFIG_SIBYTE_CARMEL
+#include <asm/sibyte/carmel.h>
+#endif
+
+#ifdef CONFIG_SIBYTE_BIGSUR
+#include <asm/sibyte/bigsur.h>
+#endif
+
+#ifdef __ASSEMBLY__
+
+#ifdef LEDS_PHYS
+#define setleds(t0, t1, c0, c1, c2, c3) \
+        li      t0, (LEDS_PHYS|0xa0000000); \
+        li      t1, c0; \
+        sb      t1, 0x18(t0); \
+        li      t1, c1; \
+        sb      t1, 0x10(t0); \
+        li      t1, c2; \
+        sb      t1, 0x08(t0); \
+        li      t1, c3; \
+        sb      t1, 0x00(t0)
+#else
+#define setleds(t0, t1, c0, c1, c2, c3)
+#endif /* LEDS_PHYS */
+
+#else
+
+void swarm_setup(void);
+
+#ifdef LEDS_PHYS
+extern void setleds(char *str);
+#else
+#define setleds(s) do { } while (0)
+#endif /* LEDS_PHYS */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SIBYTE_BOARD_H */
diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h
new file mode 100644
index 000000000..c6730d7a6
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/carmel.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2002 Broadcom Corporation
+ */
+#ifndef __ASM_SIBYTE_CARMEL_H
+#define __ASM_SIBYTE_CARMEL_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#define SIBYTE_BOARD_NAME "Carmel"
+
+#define GPIO_PHY_INTERRUPT      2
+#define GPIO_NONMASKABLE_INT    3
+#define GPIO_CF_INSERTED        6
+#define GPIO_MONTEREY_RESET     7
+#define GPIO_QUADUART_INT       8
+#define GPIO_CF_INT             9
+#define GPIO_FPGA_CCLK          10
+#define GPIO_FPGA_DOUT          11
+#define GPIO_FPGA_DIN           12
+#define GPIO_FPGA_PGM           13
+#define GPIO_FPGA_DONE          14
+#define GPIO_FPGA_INIT          15
+
+#define LEDS_CS                 2
+#define LEDS_PHYS               0x100C0000
+#define MLEDS_CS                3
+#define MLEDS_PHYS              0x100A0000
+#define UART_CS                 4
+#define UART_PHYS               0x100D0000
+#define ARAVALI_CS              5
+#define ARAVALI_PHYS            0x11000000
+#define IDE_CS                  6
+#define IDE_PHYS                0x100B0000
+#define ARAVALI2_CS             7
+#define ARAVALI2_PHYS           0x100E0000
+
+#if defined(CONFIG_SIBYTE_CARMEL)
+#define K_GPIO_GB_IDE   9
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+
+#endif /* __ASM_SIBYTE_CARMEL_H */
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
new file mode 100644
index 000000000..dbde5f93f
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ */
+
+#ifndef _ASM_SIBYTE_SB1250_H
+#define _ASM_SIBYTE_SB1250_H
+
+/*
+ * yymmddpp: year, month, day, patch.
+ * should sync with Makefile EXTRAVERSION
+ */
+#define SIBYTE_RELEASE 0x02111403
+
+#define SB1250_NR_IRQS 64
+
+#define BCM1480_NR_IRQS                 128
+#define BCM1480_NR_IRQS_HALF            64
+
+#define SB1250_DUART_MINOR_BASE         64
+
+#ifndef __ASSEMBLY__
+
+#include <asm/addrspace.h>
+
+/* For revision/pass information */
+#include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/bcm1480_scd.h>
+extern unsigned int sb1_pass;
+extern unsigned int soc_pass;
+extern unsigned int soc_type;
+extern unsigned int periph_rev;
+extern unsigned int zbbus_mhz;
+
+extern void sb1250_time_init(void);
+extern void sb1250_mask_irq(int cpu, int irq);
+extern void sb1250_unmask_irq(int cpu, int irq);
+
+extern void bcm1480_time_init(void);
+extern void bcm1480_mask_irq(int cpu, int irq);
+extern void bcm1480_unmask_irq(int cpu, int irq);
+
+#define AT_spin \
+        __asm__ __volatile__ (          \
+                ".set noat\n"           \
+                "li $at, 0\n"           \
+                "1: beqz $at, 1b\n"     \
+                ".set at\n"             \
+                )
+
+#endif
+
+#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h
new file mode 100644
index 000000000..68cd7c0b3
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_defs.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Global constants and macros              File: sb1250_defs.h
+    *
+    *  This file contains macros and definitions used by the other
+    *  include files.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+#ifndef _SB1250_DEFS_H
+#define _SB1250_DEFS_H
+
+/*
+ * These headers require ANSI C89 string concatenation, and GCC or other
+ * 'long long' (64-bit integer) support.
+ */
+#if !defined(__STDC__) && !defined(_MSC_VER)
+#error SiByte headers require ANSI C89 support
+#endif
+
+
+/*  *********************************************************************
+    *  Macros for feature tests, used to enable include file features
+    *  for chip features only present in certain chip revisions.
+    *
+    *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
+    *  which is to be exposed by the headers.  If undefined, it defaults to
+    *  "all features."
+    *
+    *  Use like:
+    *
+    *    #define SIBYTE_HDR_FEATURES    SIBYTE_HDR_FMASK_112x_PASS1
+    *
+    *           Generate defines only for that revision of chip.
+    *
+    *    #if SIBYTE_HDR_FEATURE(chip,pass)
+    *
+    *           True if header features for that revision or later of
+    *           that particular chip type are enabled in SIBYTE_HDR_FEATURES.
+    *           (Use this to bracket #defines for features present in a given
+    *           revision and later.)
+    *
+    *           Note that there is no implied ordering between chip types.
+    *
+    *           Note also that 'chip' and 'pass' must textually exactly
+    *           match the defines below.  So, for example,
+    *           SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
+    *           SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
+    *
+    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but true for the named revision
+    *           and earlier revisions of the named chip type.
+    *
+    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but only true for the named
+    *           revision of the named chip type.  (Note that this CANNOT
+    *           be used to verify that you're compiling only for that
+    *           particular chip/revision.  It will be true any time this
+    *           chip/revision is included in SIBYTE_HDR_FEATURES.)
+    *
+    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
+    *
+    *           True if header features for (any revision of) that chip type
+    *           are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
+    *           #defines for features specific to a given chip type.)
+    *
+    *  Mask values currently include room for additional revisions of each
+    *  chip type, but can be renumbered at will.  Note that they MUST fit
+    *  into 31 bits and may not include C type constructs, for safe use in
+    *  CPP conditionals.  Bit positions within chip types DO indicate
+    *  ordering, so be careful when adding support for new minor revs.
+    ********************************************************************* */
+
+#define SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
+#define SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
+#define SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
+#define SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
+
+#define SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
+
+#define SIBYTE_HDR_FMASK_1480_ALL               0x0000f000
+#define SIBYTE_HDR_FMASK_1480_PASS1             0x00001000
+#define SIBYTE_HDR_FMASK_1480_PASS2             0x00002000
+
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
+#define SIBYTE_HDR_FMASK(chip, pass)                                    \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
+#define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
+
+/* Default constant value for all chips, all revisions */
+#define SIBYTE_HDR_FMASK_ALL                                            \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL              \
+     | SIBYTE_HDR_FMASK_1480_ALL)
+
+/* This one is used for the "original" BCM1250/BCM112x chips.  We use this
+   to weed out constants and macros that do not exist on later chips like
+   the BCM1480  */
+#define SIBYTE_HDR_FMASK_1250_112x_ALL                                  \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
+#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
+
+#ifndef SIBYTE_HDR_FEATURES
+#define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
+#endif
+
+
+/* Bit mask for revisions of chip exclusively before the named revision.  */
+#define SIBYTE_HDR_FMASK_BEFORE(chip, pass)                             \
+    ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+/* Bit mask for revisions of chip exclusively after the named revision.  */
+#define SIBYTE_HDR_FMASK_AFTER(chip, pass)                              \
+    (~(SIBYTE_HDR_FMASK(chip, pass)                                     \
+     | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+
+/* True if header features enabled for (any revision of) that chip type.  */
+#define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
+    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
+
+/* True for all versions of the BCM1250 and BCM1125, but not true for
+   anything else */
+#define SIBYTE_HDR_FEATURE_1250_112x \
+      (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+/*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
+
+/* True if header features enabled for that rev or later, inclusive.  */
+#define SIBYTE_HDR_FEATURE(chip, pass)                                  \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+          | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for exactly that rev.  */
+#define SIBYTE_HDR_FEATURE_EXACT(chip, pass)                            \
+    (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for that rev or before, inclusive.  */
+#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)                            \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+         | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+
+/*  *********************************************************************
+    *  Naming schemes for constants in these files:
+    *
+    *  M_xxx           MASK constant (identifies bits in a register).
+    *                  For multi-bit fields, all bits in the field will
+    *                  be set.
+    *
+    *  K_xxx           "Code" constant (value for data in a multi-bit
+    *                  field).  The value is right justified.
+    *
+    *  V_xxx           "Value" constant.  This is the same as the
+    *                  corresponding "K_xxx" constant, except it is
+    *                  shifted to the correct position in the register.
+    *
+    *  S_xxx           SHIFT constant.  This is the number of bits that
+    *                  a field value (code) needs to be shifted
+    *                  (towards the left) to put the value in the right
+    *                  position for the register.
+    *
+    *  A_xxx           ADDRESS constant.  This will be a physical
+    *                  address.  Use the PHYS_TO_K1 macro to generate
+    *                  a K1SEG address.
+    *
+    *  R_xxx           RELATIVE offset constant.  This is an offset from
+    *                  an A_xxx constant (usually the first register in
+    *                  a group).
+    *
+    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
+    *                  from a register, masks it, and shifts it to
+    *                  the bottom of the register (retrieving a K_xxx
+    *                  value, for example).
+    *
+    *  V_xxx(X)        VALUE.  This macro computes the value of a
+    *                  K_xxx constant shifted to the correct position
+    *                  in the register.
+    ********************************************************************* */
+
+
+
+
+/*
+ * Cast to 64-bit number.  Presumably the syntax is different in
+ * assembly language.
+ *
+ * Note: you'll need to define uint32_t and uint64_t in your headers.
+ */
+
+#if !defined(__ASSEMBLY__)
+#define _SB_MAKE64(x) ((uint64_t)(x))
+#define _SB_MAKE32(x) ((uint32_t)(x))
+#else
+#define _SB_MAKE64(x) (x)
+#define _SB_MAKE32(x) (x)
+#endif
+
+
+/*
+ * Make a mask for 1 bit at position 'n'
+ */
+
+#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
+
+/*
+ * Make a mask for 'v' bits at position 'n'
+ */
+
+#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
+
+/*
+ * Make a value at 'v' at bit position 'n'
+ */
+
+#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
+#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
+
+#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
+#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
+
+/*
+ * Macros to read/write on-chip registers
+ * XXX should we do the PHYS_TO_K1 here?
+ */
+
+
+#if defined(__mips64) && !defined(__ASSEMBLY__)
+#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
+#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
new file mode 100644
index 000000000..d9678b98c
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
@@ -0,0 +1,581 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  DMA definitions                          File: sb1250_dma.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the SB1250's DMA controllers, both the data mover
+    *  and the Ethernet DMA.
+    *
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's manual 11/24/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_DMA_H
+#define _SB1250_DMA_H
+
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  DMA Registers
+    ********************************************************************* */
+
+/*
+ * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
+ * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
+ * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
+ * Registers: DMA_CONFIG0_SER_x_RX
+ * Registers: DMA_CONFIG0_SER_x_TX
+ */
+
+
+#define M_DMA_DROP                  _SB_MAKEMASK1(0)
+
+#define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
+#define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
+
+#define S_DMA_DESC_TYPE             _SB_MAKE64(1)
+#define M_DMA_DESC_TYPE             _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
+#define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
+#define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
+
+#define K_DMA_DESC_TYPE_RING_AL         0
+#define K_DMA_DESC_TYPE_CHAIN_AL        1
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define K_DMA_DESC_TYPE_RING_UAL_WI     2
+#define K_DMA_DESC_TYPE_RING_UAL_RMW    3
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
+#define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
+#define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
+#define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
+#define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
+
+#define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
+#define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
+#define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
+#define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
+
+#define S_DMA_RINGSZ                _SB_MAKE64(16)
+#define M_DMA_RINGSZ                _SB_MAKEMASK(16, S_DMA_RINGSZ)
+#define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x, S_DMA_RINGSZ)
+#define G_DMA_RINGSZ(x)             _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
+
+#define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
+#define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
+#define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
+#define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
+
+#define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
+#define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
+#define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
+#define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
+
+/*
+ * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
+ * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
+ * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
+ * Registers: DMA_CONFIG1_SER_x_RX
+ * Registers: DMA_CONFIG1_SER_x_TX
+ */
+
+#define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
+#define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
+#define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
+#define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
+#define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
+#define M_DMA_L2CA                  _SB_MAKEMASK1(5)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
+#define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
+#define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_MBZ1                  _SB_MAKEMASK(6, 15)
+
+#define S_DMA_HDR_SIZE              _SB_MAKE64(21)
+#define M_DMA_HDR_SIZE              _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
+#define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
+#define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
+
+#define M_DMA_MBZ2                  _SB_MAKEMASK(5, 32)
+
+#define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
+#define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
+#define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
+#define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
+
+#define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
+#define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
+#define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
+#define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
+
+/*
+ * Ethernet and Serial DMA Descriptor base address (Table 7-6)
+ */
+
+#define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4, 0)
+
+
+/*
+ * ASIC Mode Base Address (Table 7-7)
+ */
+
+#define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20, 0)
+
+/*
+ * DMA Descriptor Count Registers (Table 7-8)
+ */
+
+/* No bitfields */
+
+
+/*
+ * Current Descriptor Address Register (Table 7-11)
+ */
+
+#define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
+#define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
+#define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
+#define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * Receive Packet Drop Registers
+ */
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_OODLOST_RX           _SB_MAKE64(0)
+#define M_DMA_OODLOST_RX           _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
+#define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
+
+#define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
+#define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
+#define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*  *********************************************************************
+    *  DMA Descriptors
+    ********************************************************************* */
+
+/*
+ * Descriptor doubleword "A"  (Table 7-12)
+ */
+
+#define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
+#define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
+#define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
+#define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
+
+#define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
+#define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
+#define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
+#define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
+#define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
+#define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
+#define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
+
+#define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
+#define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
+#define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
+#define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
+
+/*
+ * Descriptor doubleword "B"  (Table 7-13)
+ */
+
+
+#define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
+#define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
+#define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
+#define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
+#define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
+#define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
+#define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
+
+#define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
+#define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
+#define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
+
+#define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
+#define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
+#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
+#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
+#define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
+#define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
+#define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
+
+/*
+ * from pass2 some bits in dscr_b are also used for rx status
+ */
+#define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
+#define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
+#define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
+#define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
+
+/*
+ * Ethernet Descriptor Status Bits (Table 7-15)
+ */
+
+#define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
+#define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: This bit is in the DSCR_B options field */
+#define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: These bits are in the DSCR_B options field */
+#define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
+#define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_ETHRX_RXCH            53
+#define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
+#define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
+#define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
+
+#define S_DMA_ETHRX_PKTTYPE         55
+#define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
+#define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
+#define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
+
+#define K_DMA_ETHRX_PKTTYPE_IPV4    0
+#define K_DMA_ETHRX_PKTTYPE_ARPV4   1
+#define K_DMA_ETHRX_PKTTYPE_802     2
+#define K_DMA_ETHRX_PKTTYPE_OTHER   3
+#define K_DMA_ETHRX_PKTTYPE_USER0   4
+#define K_DMA_ETHRX_PKTTYPE_USER1   5
+#define K_DMA_ETHRX_PKTTYPE_USER2   6
+#define K_DMA_ETHRX_PKTTYPE_USER3   7
+
+#define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
+#define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
+#define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
+#define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
+#define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
+#define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Ethernet Transmit Status Bits (Table 7-16)
+ */
+
+#define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Ethernet Transmit Options (Table 7-17)
+ */
+
+#define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
+#define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
+#define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
+#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
+#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
+#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
+#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
+#define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
+#define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
+#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
+#define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
+
+/*
+ * Serial Receive Options (Table 7-18)
+ */
+#define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
+#define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
+#define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
+#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
+#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
+#define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
+#define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
+#define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Status Bits (Table 7-20)
+ */
+
+#define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Options (Table 7-21)
+ */
+
+#define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
+#define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
+#define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
+#define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
+
+
+/*  *********************************************************************
+    *  Data Mover Registers
+    ********************************************************************* */
+
+/*
+ * Data Mover Descriptor Base Address Register (Table 7-22)
+ * Register: DM_DSCR_BASE_0
+ * Register: DM_DSCR_BASE_1
+ * Register: DM_DSCR_BASE_2
+ * Register: DM_DSCR_BASE_3
+ */
+
+#define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4, 0)
+
+/*  Note: Just mask the base address and then OR it in. */
+#define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
+#define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
+
+#define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
+#define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
+#define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
+#define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
+
+#define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
+#define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
+#define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
+#define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
+
+#define K_DM_DSCR_BASE_PRIORITY_1   0
+#define K_DM_DSCR_BASE_PRIORITY_2   1
+#define K_DM_DSCR_BASE_PRIORITY_4   2
+#define K_DM_DSCR_BASE_PRIORITY_8   3
+#define K_DM_DSCR_BASE_PRIORITY_16  4
+
+#define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
+#define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
+#define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
+#define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
+#define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
+#define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
+
+/*
+ * Data Mover Descriptor Count Register (Table 7-25)
+ */
+
+/* no bitfields */
+
+/*
+ * Data Mover Current Descriptor Address (Table 7-24)
+ * Register: DM_CUR_DSCR_ADDR_0
+ * Register: DM_CUR_DSCR_ADDR_1
+ * Register: DM_CUR_DSCR_ADDR_2
+ * Register: DM_CUR_DSCR_ADDR_3
+ */
+
+#define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
+#define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
+
+#define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
+#define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
+#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
+#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
+                                     M_DM_CUR_DSCR_DSCR_COUNT)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover Channel Partial Result Registers
+ * Register: DM_PARTIAL_0
+ * Register: DM_PARTIAL_1
+ * Register: DM_PARTIAL_2
+ * Register: DM_PARTIAL_3
+ */
+#define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
+#define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
+#define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
+#define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
+                                       M_DM_PARTIAL_CRC_PARTIAL)
+
+#define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
+#define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
+#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
+#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
+                                       M_DM_PARTIAL_TCPCS_PARTIAL)
+
+#define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover CRC Definition Registers
+ * Register: CRC_DEF_0
+ * Register: CRC_DEF_1
+ */
+#define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
+#define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
+#define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
+#define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
+                                       M_CRC_DEF_CRC_INIT)
+
+#define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
+#define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
+#define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
+#define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
+                                       M_CRC_DEF_CRC_POLY)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover CRC/Checksum Definition Registers
+ * Register: CTCP_DEF_0
+ * Register: CTCP_DEF_1
+ */
+#define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
+#define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
+#define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
+#define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
+                                       M_CTCP_DEF_CRC_TXOR)
+
+#define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
+#define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
+#define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
+#define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
+                                       M_CTCP_DEF_TCPCS_INIT)
+
+#define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
+#define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
+#define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
+#define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
+                                       M_CTCP_DEF_CRC_WIDTH)
+
+#define K_CTCP_DEF_CRC_WIDTH_4        0
+#define K_CTCP_DEF_CRC_WIDTH_2        1
+#define K_CTCP_DEF_CRC_WIDTH_1        2
+
+#define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+/*
+ * Data Mover Descriptor Doubleword "A"  (Table 7-26)
+ */
+
+#define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
+
+#define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
+#define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
+#define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
+#endif /* up to 1250 PASS1 */
+
+#define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
+#define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
+#define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
+
+#define K_DM_DSCRA_DIR_DEST_INCR    0
+#define K_DM_DSCRA_DIR_DEST_DECR    1
+#define K_DM_DSCRA_DIR_DEST_CONST   2
+
+#define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
+
+#define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
+#define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
+#define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
+
+#define K_DM_DSCRA_DIR_SRC_INCR     0
+#define K_DM_DSCRA_DIR_SRC_DECR     1
+#define K_DM_DSCRA_DIR_SRC_CONST    2
+
+#define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
+
+
+#define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
+#define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
+#define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
+#define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
+#define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
+#define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
+#define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
+#define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
+#define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
+#define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
+#define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
+#define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3, 61)
+
+/*
+ * Data Mover Descriptor Doubleword "B"  (Table 7-25)
+ */
+
+#define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
+
+#define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
+#define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
+#define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
+#define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
new file mode 100644
index 000000000..ddeb8edf5
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
@@ -0,0 +1,461 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Generic Bus Constants                     File: sb1250_genbus.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's Generic Bus interface
+    *
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's Manual 11/14/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_GENBUS_H
+#define _SB1250_GENBUS_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Generic Bus Region Configuration Registers (Table 11-4)
+ */
+
+#define S_IO_RDY_ACTIVE         0
+#define M_IO_RDY_ACTIVE         _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
+
+#define S_IO_ENA_RDY            1
+#define M_IO_ENA_RDY            _SB_MAKEMASK1(S_IO_ENA_RDY)
+
+#define S_IO_WIDTH_SEL          2
+#define M_IO_WIDTH_SEL          _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
+#define K_IO_WIDTH_SEL_1        0
+#define K_IO_WIDTH_SEL_2        1
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define K_IO_WIDTH_SEL_1L       2
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define K_IO_WIDTH_SEL_4        3
+#define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
+#define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
+
+#define S_IO_PARITY_ENA         4
+#define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_IO_BURST_EN           5
+#define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define S_IO_PARITY_ODD         6
+#define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
+#define S_IO_NONMUX             7
+#define M_IO_NONMUX             _SB_MAKEMASK1(S_IO_NONMUX)
+
+#define S_IO_TIMEOUT            8
+#define M_IO_TIMEOUT            _SB_MAKEMASK(8, S_IO_TIMEOUT)
+#define V_IO_TIMEOUT(x)         _SB_MAKEVALUE(x, S_IO_TIMEOUT)
+#define G_IO_TIMEOUT(x)         _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
+
+/*
+ * Generic Bus Region Size register (Table 11-5)
+ */
+
+#define S_IO_MULT_SIZE          0
+#define M_IO_MULT_SIZE          _SB_MAKEMASK(12, S_IO_MULT_SIZE)
+#define V_IO_MULT_SIZE(x)       _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
+#define G_IO_MULT_SIZE(x)       _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
+
+#define S_IO_REGSIZE            16       /* # bits to shift size for this reg */
+
+/*
+ * Generic Bus Region Address (Table 11-6)
+ */
+
+#define S_IO_START_ADDR         0
+#define M_IO_START_ADDR         _SB_MAKEMASK(14, S_IO_START_ADDR)
+#define V_IO_START_ADDR(x)      _SB_MAKEVALUE(x, S_IO_START_ADDR)
+#define G_IO_START_ADDR(x)      _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
+
+#define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
+
+#define M_IO_BLK_CACHE          _SB_MAKEMASK1(15)
+
+
+/*
+ * Generic Bus Timing 0 Registers (Table 11-7)
+ */
+
+#define S_IO_ALE_WIDTH          0
+#define M_IO_ALE_WIDTH          _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
+#define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
+#define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_ALE_TO_CS          4
+#define M_IO_ALE_TO_CS          _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
+#define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
+#define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_IO_BURST_WIDTH           _SB_MAKE64(6)
+#define M_IO_BURST_WIDTH           _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
+#define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
+#define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_CS_WIDTH           8
+#define M_IO_CS_WIDTH           _SB_MAKEMASK(5, S_IO_CS_WIDTH)
+#define V_IO_CS_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
+#define G_IO_CS_WIDTH(x)        _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
+
+#define S_IO_RDY_SMPLE          13
+#define M_IO_RDY_SMPLE          _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
+#define V_IO_RDY_SMPLE(x)       _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
+#define G_IO_RDY_SMPLE(x)       _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
+
+
+/*
+ * Generic Bus Timing 1 Registers (Table 11-8)
+ */
+
+#define S_IO_ALE_TO_WRITE       0
+#define M_IO_ALE_TO_WRITE       _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
+#define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
+#define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_WRITE_WIDTH        4
+#define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
+#define V_IO_WRITE_WIDTH(x)     _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
+#define G_IO_WRITE_WIDTH(x)     _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
+
+#define S_IO_IDLE_CYCLE         8
+#define M_IO_IDLE_CYCLE         _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
+#define V_IO_IDLE_CYCLE(x)      _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
+#define G_IO_IDLE_CYCLE(x)      _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
+
+#define S_IO_OE_TO_CS           12
+#define M_IO_OE_TO_CS           _SB_MAKEMASK(2, S_IO_OE_TO_CS)
+#define V_IO_OE_TO_CS(x)        _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
+#define G_IO_OE_TO_CS(x)        _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
+
+#define S_IO_CS_TO_OE           14
+#define M_IO_CS_TO_OE           _SB_MAKEMASK(2, S_IO_CS_TO_OE)
+#define V_IO_CS_TO_OE(x)        _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
+#define G_IO_CS_TO_OE(x)        _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
+
+/*
+ * Generic Bus Interrupt Status Register (Table 11-9)
+ */
+
+#define M_IO_CS_ERR_INT         _SB_MAKEMASK(0, 8)
+#define M_IO_CS0_ERR_INT        _SB_MAKEMASK1(0)
+#define M_IO_CS1_ERR_INT        _SB_MAKEMASK1(1)
+#define M_IO_CS2_ERR_INT        _SB_MAKEMASK1(2)
+#define M_IO_CS3_ERR_INT        _SB_MAKEMASK1(3)
+#define M_IO_CS4_ERR_INT        _SB_MAKEMASK1(4)
+#define M_IO_CS5_ERR_INT        _SB_MAKEMASK1(5)
+#define M_IO_CS6_ERR_INT        _SB_MAKEMASK1(6)
+#define M_IO_CS7_ERR_INT        _SB_MAKEMASK1(7)
+
+#define M_IO_RD_PAR_INT         _SB_MAKEMASK1(9)
+#define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
+#define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
+#define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_COH_ERR            _SB_MAKEMASK1(14)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/*
+ * Generic Bus Output Drive Control Register 0 (Table 14-18)
+ */
+
+#define S_IO_SLEW0              0
+#define M_IO_SLEW0              _SB_MAKEMASK(2, S_IO_SLEW0)
+#define V_IO_SLEW0(x)           _SB_MAKEVALUE(x, S_IO_SLEW0)
+#define G_IO_SLEW0(x)           _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
+
+#define S_IO_DRV_A              2
+#define M_IO_DRV_A              _SB_MAKEMASK(2, S_IO_DRV_A)
+#define V_IO_DRV_A(x)           _SB_MAKEVALUE(x, S_IO_DRV_A)
+#define G_IO_DRV_A(x)           _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
+
+#define S_IO_DRV_B              6
+#define M_IO_DRV_B              _SB_MAKEMASK(2, S_IO_DRV_B)
+#define V_IO_DRV_B(x)           _SB_MAKEVALUE(x, S_IO_DRV_B)
+#define G_IO_DRV_B(x)           _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
+
+#define S_IO_DRV_C              10
+#define M_IO_DRV_C              _SB_MAKEMASK(2, S_IO_DRV_C)
+#define V_IO_DRV_C(x)           _SB_MAKEVALUE(x, S_IO_DRV_C)
+#define G_IO_DRV_C(x)           _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
+
+#define S_IO_DRV_D              14
+#define M_IO_DRV_D              _SB_MAKEMASK(2, S_IO_DRV_D)
+#define V_IO_DRV_D(x)           _SB_MAKEVALUE(x, S_IO_DRV_D)
+#define G_IO_DRV_D(x)           _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
+
+/*
+ * Generic Bus Output Drive Control Register 1 (Table 14-19)
+ */
+
+#define S_IO_DRV_E              2
+#define M_IO_DRV_E              _SB_MAKEMASK(2, S_IO_DRV_E)
+#define V_IO_DRV_E(x)           _SB_MAKEVALUE(x, S_IO_DRV_E)
+#define G_IO_DRV_E(x)           _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
+
+#define S_IO_DRV_F              6
+#define M_IO_DRV_F              _SB_MAKEMASK(2, S_IO_DRV_F)
+#define V_IO_DRV_F(x)           _SB_MAKEVALUE(x, S_IO_DRV_F)
+#define G_IO_DRV_F(x)           _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
+
+#define S_IO_SLEW1              8
+#define M_IO_SLEW1              _SB_MAKEMASK(2, S_IO_SLEW1)
+#define V_IO_SLEW1(x)           _SB_MAKEVALUE(x, S_IO_SLEW1)
+#define G_IO_SLEW1(x)           _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
+
+#define S_IO_DRV_G              10
+#define M_IO_DRV_G              _SB_MAKEMASK(2, S_IO_DRV_G)
+#define V_IO_DRV_G(x)           _SB_MAKEVALUE(x, S_IO_DRV_G)
+#define G_IO_DRV_G(x)           _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
+
+#define S_IO_SLEW2              12
+#define M_IO_SLEW2              _SB_MAKEMASK(2, S_IO_SLEW2)
+#define V_IO_SLEW2(x)           _SB_MAKEVALUE(x, S_IO_SLEW2)
+#define G_IO_SLEW2(x)           _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
+
+#define S_IO_DRV_H              14
+#define M_IO_DRV_H              _SB_MAKEMASK(2, S_IO_DRV_H)
+#define V_IO_DRV_H(x)           _SB_MAKEVALUE(x, S_IO_DRV_H)
+#define G_IO_DRV_H(x)           _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
+
+/*
+ * Generic Bus Output Drive Control Register 2 (Table 14-20)
+ */
+
+#define S_IO_DRV_J              2
+#define M_IO_DRV_J              _SB_MAKEMASK(2, S_IO_DRV_J)
+#define V_IO_DRV_J(x)           _SB_MAKEVALUE(x, S_IO_DRV_J)
+#define G_IO_DRV_J(x)           _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
+
+#define S_IO_DRV_K              6
+#define M_IO_DRV_K              _SB_MAKEMASK(2, S_IO_DRV_K)
+#define V_IO_DRV_K(x)           _SB_MAKEVALUE(x, S_IO_DRV_K)
+#define G_IO_DRV_K(x)           _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
+
+#define S_IO_DRV_L              10
+#define M_IO_DRV_L              _SB_MAKEMASK(2, S_IO_DRV_L)
+#define V_IO_DRV_L(x)           _SB_MAKEVALUE(x, S_IO_DRV_L)
+#define G_IO_DRV_L(x)           _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
+
+#define S_IO_DRV_M              14
+#define M_IO_DRV_M              _SB_MAKEMASK(2, S_IO_DRV_M)
+#define V_IO_DRV_M(x)           _SB_MAKEVALUE(x, S_IO_DRV_M)
+#define G_IO_DRV_M(x)           _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
+
+/*
+ * Generic Bus Output Drive Control Register 3 (Table 14-21)
+ */
+
+#define S_IO_SLEW3              0
+#define M_IO_SLEW3              _SB_MAKEMASK(2, S_IO_SLEW3)
+#define V_IO_SLEW3(x)           _SB_MAKEVALUE(x, S_IO_SLEW3)
+#define G_IO_SLEW3(x)           _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
+
+#define S_IO_DRV_N              2
+#define M_IO_DRV_N              _SB_MAKEMASK(2, S_IO_DRV_N)
+#define V_IO_DRV_N(x)           _SB_MAKEVALUE(x, S_IO_DRV_N)
+#define G_IO_DRV_N(x)           _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
+
+#define S_IO_DRV_P              6
+#define M_IO_DRV_P              _SB_MAKEMASK(2, S_IO_DRV_P)
+#define V_IO_DRV_P(x)           _SB_MAKEVALUE(x, S_IO_DRV_P)
+#define G_IO_DRV_P(x)           _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
+
+#define S_IO_DRV_Q              10
+#define M_IO_DRV_Q              _SB_MAKEMASK(2, S_IO_DRV_Q)
+#define V_IO_DRV_Q(x)           _SB_MAKEVALUE(x, S_IO_DRV_Q)
+#define G_IO_DRV_Q(x)           _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
+
+#define S_IO_DRV_R              14
+#define M_IO_DRV_R              _SB_MAKEMASK(2, S_IO_DRV_R)
+#define V_IO_DRV_R(x)           _SB_MAKEVALUE(x, S_IO_DRV_R)
+#define G_IO_DRV_R(x)           _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
+
+
+/*
+ * PCMCIA configuration register (Table 12-6)
+ */
+
+#define M_PCMCIA_CFG_ATTRMEM    _SB_MAKEMASK1(0)
+#define M_PCMCIA_CFG_3VEN       _SB_MAKEMASK1(1)
+#define M_PCMCIA_CFG_5VEN       _SB_MAKEMASK1(2)
+#define M_PCMCIA_CFG_VPPEN      _SB_MAKEMASK1(3)
+#define M_PCMCIA_CFG_RESET      _SB_MAKEMASK1(4)
+#define M_PCMCIA_CFG_APWRONEN   _SB_MAKEMASK1(5)
+#define M_PCMCIA_CFG_CDMASK     _SB_MAKEMASK1(6)
+#define M_PCMCIA_CFG_WPMASK     _SB_MAKEMASK1(7)
+#define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
+#define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_PCMCIA_MODE           16
+#define M_PCMCIA_MODE           _SB_MAKEMASK(3, S_PCMCIA_MODE)
+#define V_PCMCIA_MODE(x)        _SB_MAKEVALUE(x, S_PCMCIA_MODE)
+#define G_PCMCIA_MODE(x)        _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
+
+#define K_PCMCIA_MODE_PCMA_NOB  0       /* standard PCMCIA "A", no "B" */
+#define K_PCMCIA_MODE_IDEA_NOB  1       /* IDE "A", no "B" */
+#define K_PCMCIA_MODE_PCMIOA_NOB 2      /* PCMCIA with I/O "A", no "B" */
+#define K_PCMCIA_MODE_PCMA_PCMB 4       /* standard PCMCIA "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_IDEA_PCMB 5       /* IDE "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_PCMA_IDEB 6       /* standard PCMCIA "A", IDE "B" */
+#define K_PCMCIA_MODE_IDEA_IDEB 7       /* IDE "A", IDE "B" */
+#endif
+
+
+/*
+ * PCMCIA status register (Table 12-7)
+ */
+
+#define M_PCMCIA_STATUS_CD1     _SB_MAKEMASK1(0)
+#define M_PCMCIA_STATUS_CD2     _SB_MAKEMASK1(1)
+#define M_PCMCIA_STATUS_VS1     _SB_MAKEMASK1(2)
+#define M_PCMCIA_STATUS_VS2     _SB_MAKEMASK1(3)
+#define M_PCMCIA_STATUS_WP      _SB_MAKEMASK1(4)
+#define M_PCMCIA_STATUS_RDY     _SB_MAKEMASK1(5)
+#define M_PCMCIA_STATUS_3VEN    _SB_MAKEMASK1(6)
+#define M_PCMCIA_STATUS_5VEN    _SB_MAKEMASK1(7)
+#define M_PCMCIA_STATUS_CDCHG   _SB_MAKEMASK1(8)
+#define M_PCMCIA_STATUS_WPCHG   _SB_MAKEMASK1(9)
+#define M_PCMCIA_STATUS_RDYCHG  _SB_MAKEMASK1(10)
+
+/*
+ * GPIO Interrupt Type Register (table 13-3)
+ */
+
+#define K_GPIO_INTR_DISABLE     0
+#define K_GPIO_INTR_EDGE        1
+#define K_GPIO_INTR_LEVEL       2
+#define K_GPIO_INTR_SPLIT       3
+
+#define S_GPIO_INTR_TYPEX(n)    (((n)/2)*2)
+#define M_GPIO_INTR_TYPEX(n)    _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
+#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
+#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
+
+#define S_GPIO_INTR_TYPE0       0
+#define M_GPIO_INTR_TYPE0       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
+#define V_GPIO_INTR_TYPE0(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
+#define G_GPIO_INTR_TYPE0(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
+
+#define S_GPIO_INTR_TYPE2       2
+#define M_GPIO_INTR_TYPE2       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
+#define V_GPIO_INTR_TYPE2(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
+#define G_GPIO_INTR_TYPE2(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
+
+#define S_GPIO_INTR_TYPE4       4
+#define M_GPIO_INTR_TYPE4       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
+#define V_GPIO_INTR_TYPE4(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
+#define G_GPIO_INTR_TYPE4(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
+
+#define S_GPIO_INTR_TYPE6       6
+#define M_GPIO_INTR_TYPE6       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
+#define V_GPIO_INTR_TYPE6(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
+#define G_GPIO_INTR_TYPE6(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
+
+#define S_GPIO_INTR_TYPE8       8
+#define M_GPIO_INTR_TYPE8       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
+#define V_GPIO_INTR_TYPE8(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
+#define G_GPIO_INTR_TYPE8(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
+
+#define S_GPIO_INTR_TYPE10      10
+#define M_GPIO_INTR_TYPE10      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
+#define V_GPIO_INTR_TYPE10(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
+#define G_GPIO_INTR_TYPE10(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
+
+#define S_GPIO_INTR_TYPE12      12
+#define M_GPIO_INTR_TYPE12      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
+#define V_GPIO_INTR_TYPE12(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
+#define G_GPIO_INTR_TYPE12(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
+
+#define S_GPIO_INTR_TYPE14      14
+#define M_GPIO_INTR_TYPE14      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
+#define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
+#define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+
+/*
+ * GPIO Interrupt Additional Type Register
+ */
+
+#define K_GPIO_INTR_BOTHEDGE    0
+#define K_GPIO_INTR_RISEEDGE    1
+#define K_GPIO_INTR_UNPRED1     2
+#define K_GPIO_INTR_UNPRED2     3
+
+#define S_GPIO_INTR_ATYPEX(n)   (((n)/2)*2)
+#define M_GPIO_INTR_ATYPEX(n)   _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
+#define V_GPIO_INTR_ATYPEX(n, x)        _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
+#define G_GPIO_INTR_ATYPEX(n, x)        _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
+
+#define S_GPIO_INTR_ATYPE0      0
+#define M_GPIO_INTR_ATYPE0      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
+#define V_GPIO_INTR_ATYPE0(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
+#define G_GPIO_INTR_ATYPE0(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
+
+#define S_GPIO_INTR_ATYPE2      2
+#define M_GPIO_INTR_ATYPE2      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
+#define V_GPIO_INTR_ATYPE2(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
+#define G_GPIO_INTR_ATYPE2(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
+
+#define S_GPIO_INTR_ATYPE4      4
+#define M_GPIO_INTR_ATYPE4      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
+#define V_GPIO_INTR_ATYPE4(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
+#define G_GPIO_INTR_ATYPE4(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
+
+#define S_GPIO_INTR_ATYPE6      6
+#define M_GPIO_INTR_ATYPE6      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
+#define V_GPIO_INTR_ATYPE6(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
+#define G_GPIO_INTR_ATYPE6(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
+
+#define S_GPIO_INTR_ATYPE8      8
+#define M_GPIO_INTR_ATYPE8      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
+#define V_GPIO_INTR_ATYPE8(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
+#define G_GPIO_INTR_ATYPE8(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
+
+#define S_GPIO_INTR_ATYPE10     10
+#define M_GPIO_INTR_ATYPE10     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
+#define V_GPIO_INTR_ATYPE10(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
+#define G_GPIO_INTR_ATYPE10(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
+
+#define S_GPIO_INTR_ATYPE12     12
+#define M_GPIO_INTR_ATYPE12     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
+#define V_GPIO_INTR_ATYPE12(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
+#define G_GPIO_INTR_ATYPE12(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
+
+#define S_GPIO_INTR_ATYPE14     14
+#define M_GPIO_INTR_ATYPE14     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
+#define V_GPIO_INTR_ATYPE14(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
+#define G_GPIO_INTR_ATYPE14(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
+#endif
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
new file mode 100644
index 000000000..2e0adb055
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
@@ -0,0 +1,235 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: sb1250_int.h
+    *
+    *  This module contains constants for manipulating the SB1250's
+    *  interrupt mapper and definitions for the interrupt sources.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_INT_H
+#define _SB1250_INT_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * Interrupt sources (Table 4-8, UM 0.2)
+ *
+ * First, the interrupt numbers.
+ */
+
+#define K_INT_SOURCES               64
+
+#define K_INT_WATCHDOG_TIMER_0      0
+#define K_INT_WATCHDOG_TIMER_1      1
+#define K_INT_TIMER_0               2
+#define K_INT_TIMER_1               3
+#define K_INT_TIMER_2               4
+#define K_INT_TIMER_3               5
+#define K_INT_SMB_0                 6
+#define K_INT_SMB_1                 7
+#define K_INT_UART_0                8
+#define K_INT_UART_1                9
+#define K_INT_SER_0                 10
+#define K_INT_SER_1                 11
+#define K_INT_PCMCIA                12
+#define K_INT_ADDR_TRAP             13
+#define K_INT_PERF_CNT              14
+#define K_INT_TRACE_FREEZE          15
+#define K_INT_BAD_ECC               16
+#define K_INT_COR_ECC               17
+#define K_INT_IO_BUS                18
+#define K_INT_MAC_0                 19
+#define K_INT_MAC_1                 20
+#define K_INT_MAC_2                 21
+#define K_INT_DM_CH_0               22
+#define K_INT_DM_CH_1               23
+#define K_INT_DM_CH_2               24
+#define K_INT_DM_CH_3               25
+#define K_INT_MBOX_0                26
+#define K_INT_MBOX_1                27
+#define K_INT_MBOX_2                28
+#define K_INT_MBOX_3                29
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_CYCLE_CP0_INT         30
+#define K_INT_CYCLE_CP1_INT         31
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define K_INT_GPIO_0                32
+#define K_INT_GPIO_1                33
+#define K_INT_GPIO_2                34
+#define K_INT_GPIO_3                35
+#define K_INT_GPIO_4                36
+#define K_INT_GPIO_5                37
+#define K_INT_GPIO_6                38
+#define K_INT_GPIO_7                39
+#define K_INT_GPIO_8                40
+#define K_INT_GPIO_9                41
+#define K_INT_GPIO_10               42
+#define K_INT_GPIO_11               43
+#define K_INT_GPIO_12               44
+#define K_INT_GPIO_13               45
+#define K_INT_GPIO_14               46
+#define K_INT_GPIO_15               47
+#define K_INT_LDT_FATAL             48
+#define K_INT_LDT_NONFATAL          49
+#define K_INT_LDT_SMI               50
+#define K_INT_LDT_NMI               51
+#define K_INT_LDT_INIT              52
+#define K_INT_LDT_STARTUP           53
+#define K_INT_LDT_EXT               54
+#define K_INT_PCI_ERROR             55
+#define K_INT_PCI_INTA              56
+#define K_INT_PCI_INTB              57
+#define K_INT_PCI_INTC              58
+#define K_INT_PCI_INTD              59
+#define K_INT_SPARE_2               60
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_MAC_0_CH1             61
+#define K_INT_MAC_1_CH1             62
+#define K_INT_MAC_2_CH1             63
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
+#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
+#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
+#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
+#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
+#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
+#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
+#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
+#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
+#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
+#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
+#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
+#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
+#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
+#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
+#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
+#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
+#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
+#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
+#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
+#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
+#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
+#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
+#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
+#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
+#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
+#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
+#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
+#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
+#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
+#define M_INT_MBOX_ALL              _SB_MAKEMASK(4, K_INT_MBOX_0)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_CYCLE_CP0_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
+#define M_INT_CYCLE_CP1_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
+#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
+#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
+#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
+#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
+#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
+#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
+#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
+#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
+#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
+#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
+#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
+#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
+#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
+#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
+#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
+#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
+#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
+#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
+#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
+#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
+#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
+#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
+#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
+#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
+#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
+#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
+#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
+#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_MAC_0_CH1             _SB_MAKEMASK1(K_INT_MAC_0_CH1)
+#define M_INT_MAC_1_CH1             _SB_MAKEMASK1(K_INT_MAC_1_CH1)
+#define M_INT_MAC_2_CH1             _SB_MAKEMASK1(K_INT_MAC_2_CH1)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Interrupt mappings
+ */
+
+#define K_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_INT_MAP_I1    1
+#define K_INT_MAP_I2    2
+#define K_INT_MAP_I3    3
+#define K_INT_MAP_I4    4
+#define K_INT_MAP_I5    5
+#define K_INT_MAP_NMI   6               /* nonmaskable */
+#define K_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * LDT Interrupt Set Register (table 4-5)
+ */
+
+#define S_INT_LDT_INTMSG              0
+#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
+#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
+#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
+
+#define K_INT_LDT_INTMSG_FIXED        0
+#define K_INT_LDT_INTMSG_ARBITRATED   1
+#define K_INT_LDT_INTMSG_SMI          2
+#define K_INT_LDT_INTMSG_NMI          3
+#define K_INT_LDT_INTMSG_INIT         4
+#define K_INT_LDT_INTMSG_STARTUP      5
+#define K_INT_LDT_INTMSG_EXTINT       6
+#define K_INT_LDT_INTMSG_RESERVED     7
+
+#define M_INT_LDT_EDGETRIGGER         0
+#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
+
+#define M_INT_LDT_PHYSICALDEST        0
+#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
+
+#define S_INT_LDT_INTDEST             5
+#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
+#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
+#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
+
+#define S_INT_LDT_VECTOR              13
+#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
+#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
+#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
+
+/*
+ * Vector format (Table 4-6)
+ */
+
+#define M_LDTVECT_RAISEINT              0x00
+#define M_LDTVECT_RAISEMBOX             0x40
+
+
+#endif  /* 1250/112x */
diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
new file mode 100644
index 000000000..cd8de844b
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: sb1250_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_L2C_H
+#define _SB1250_L2C_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Level 2 Cache Tag register (Table 5-3)
+ */
+
+#define S_L2C_TAG_MBZ               0
+#define M_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
+
+#define S_L2C_TAG_INDEX             5
+#define M_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
+#define V_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
+#define G_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
+
+#define S_L2C_TAG_TAG               17
+#define M_L2C_TAG_TAG               _SB_MAKEMASK(23, S_L2C_TAG_TAG)
+#define V_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
+#define G_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
+
+#define S_L2C_TAG_ECC               40
+#define M_L2C_TAG_ECC               _SB_MAKEMASK(6, S_L2C_TAG_ECC)
+#define V_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
+#define G_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
+
+#define S_L2C_TAG_WAY               46
+#define M_L2C_TAG_WAY               _SB_MAKEMASK(2, S_L2C_TAG_WAY)
+#define V_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
+#define G_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
+
+#define M_L2C_TAG_DIRTY             _SB_MAKEMASK1(48)
+#define M_L2C_TAG_VALID             _SB_MAKEMASK1(49)
+
+/*
+ * Format of level 2 cache management address (table 5-2)
+ */
+
+#define S_L2C_MGMT_INDEX            5
+#define M_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
+#define V_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
+#define G_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
+
+#define S_L2C_MGMT_QUADRANT         15
+#define M_L2C_MGMT_QUADRANT         _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
+#define V_L2C_MGMT_QUADRANT(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
+#define G_L2C_MGMT_QUADRANT(x)      _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
+
+#define S_L2C_MGMT_HALF             16
+#define M_L2C_MGMT_HALF             _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
+
+#define S_L2C_MGMT_WAY              17
+#define M_L2C_MGMT_WAY              _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
+#define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
+#define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
+
+#define S_L2C_MGMT_ECC_DIAG         21
+#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
+#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
+#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
+
+#define S_L2C_MGMT_TAG              23
+#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
+#define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
+#define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
+
+#define M_L2C_MGMT_DIRTY            _SB_MAKEMASK1(19)
+#define M_L2C_MGMT_VALID            _SB_MAKEMASK1(20)
+
+#define A_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define L2C_ENTRIES_PER_WAY       4096
+#define L2C_NUM_WAYS              4
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * L2 Read Misc. register (A_L2_READ_MISC)
+ */
+#define S_L2C_MISC_NO_WAY               10
+#define M_L2C_MISC_NO_WAY               _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
+#define V_L2C_MISC_NO_WAY(x)            _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
+#define G_L2C_MISC_NO_WAY(x)            _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
+
+#define M_L2C_MISC_ECC_CLEANUP_DIS      _SB_MAKEMASK1(9)
+#define M_L2C_MISC_MC_PRIO_LOW          _SB_MAKEMASK1(8)
+#define M_L2C_MISC_SOFT_DISABLE_T       _SB_MAKEMASK1(7)
+#define M_L2C_MISC_SOFT_DISABLE_B       _SB_MAKEMASK1(6)
+#define M_L2C_MISC_SOFT_DISABLE_R       _SB_MAKEMASK1(5)
+#define M_L2C_MISC_SOFT_DISABLE_L       _SB_MAKEMASK1(4)
+#define M_L2C_MISC_SCACHE_DISABLE_T     _SB_MAKEMASK1(3)
+#define M_L2C_MISC_SCACHE_DISABLE_B     _SB_MAKEMASK1(2)
+#define M_L2C_MISC_SCACHE_DISABLE_R     _SB_MAKEMASK1(1)
+#define M_L2C_MISC_SCACHE_DISABLE_L     _SB_MAKEMASK1(0)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
new file mode 100644
index 000000000..c22df8dbb
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -0,0 +1,409 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  LDT constants                            File: sb1250_ldt.h
+    *
+    *  This module contains constants and macros to describe
+    *  the LDT interface on the SB1250.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_LDT_H
+#define _SB1250_LDT_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+#define K_LDT_VENDOR_SIBYTE     0x166D
+#define K_LDT_DEVICE_SB1250     0x0002
+
+/*
+ * LDT Interface Type 1 (bridge) configuration header
+ */
+
+#define R_LDT_TYPE1_DEVICEID    0x0000
+#define R_LDT_TYPE1_CMDSTATUS   0x0004
+#define R_LDT_TYPE1_CLASSREV    0x0008
+#define R_LDT_TYPE1_DEVHDR      0x000C
+#define R_LDT_TYPE1_BAR0        0x0010  /* not used */
+#define R_LDT_TYPE1_BAR1        0x0014  /* not used */
+
+#define R_LDT_TYPE1_BUSID       0x0018  /* bus ID register */
+#define R_LDT_TYPE1_SECSTATUS   0x001C  /* secondary status / I/O base/limit */
+#define R_LDT_TYPE1_MEMLIMIT    0x0020
+#define R_LDT_TYPE1_PREFETCH    0x0024
+#define R_LDT_TYPE1_PREF_BASE   0x0028
+#define R_LDT_TYPE1_PREF_LIMIT  0x002C
+#define R_LDT_TYPE1_IOLIMIT     0x0030
+#define R_LDT_TYPE1_CAPPTR      0x0034
+#define R_LDT_TYPE1_ROMADDR     0x0038
+#define R_LDT_TYPE1_BRCTL       0x003C
+#define R_LDT_TYPE1_CMD         0x0040
+#define R_LDT_TYPE1_LINKCTRL    0x0044
+#define R_LDT_TYPE1_LINKFREQ    0x0048
+#define R_LDT_TYPE1_RESERVED1   0x004C
+#define R_LDT_TYPE1_SRICMD      0x0050
+#define R_LDT_TYPE1_SRITXNUM    0x0054
+#define R_LDT_TYPE1_SRIRXNUM    0x0058
+#define R_LDT_TYPE1_ERRSTATUS   0x0068
+#define R_LDT_TYPE1_SRICTRL     0x006C
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_LDT_TYPE1_ADDSTATUS   0x0070
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define R_LDT_TYPE1_TXBUFCNT    0x00C8
+#define R_LDT_TYPE1_EXPCRC      0x00DC
+#define R_LDT_TYPE1_RXCRC       0x00F0
+
+
+/*
+ * LDT Device ID register
+ */
+
+#define S_LDT_DEVICEID_VENDOR           0
+#define M_LDT_DEVICEID_VENDOR           _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
+#define V_LDT_DEVICEID_VENDOR(x)        _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
+#define G_LDT_DEVICEID_VENDOR(x)        _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
+
+#define S_LDT_DEVICEID_DEVICEID         16
+#define M_LDT_DEVICEID_DEVICEID         _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
+#define V_LDT_DEVICEID_DEVICEID(x)      _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
+#define G_LDT_DEVICEID_DEVICEID(x)      _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
+
+
+/*
+ * LDT Command Register (Table 8-13)
+ */
+
+#define M_LDT_CMD_IOSPACE_EN            _SB_MAKEMASK1_32(0)
+#define M_LDT_CMD_MEMSPACE_EN           _SB_MAKEMASK1_32(1)
+#define M_LDT_CMD_MASTER_EN             _SB_MAKEMASK1_32(2)
+#define M_LDT_CMD_SPECCYC_EN            _SB_MAKEMASK1_32(3)
+#define M_LDT_CMD_MEMWRINV_EN           _SB_MAKEMASK1_32(4)
+#define M_LDT_CMD_VGAPALSNP_EN          _SB_MAKEMASK1_32(5)
+#define M_LDT_CMD_PARERRRESP            _SB_MAKEMASK1_32(6)
+#define M_LDT_CMD_WAITCYCCTRL           _SB_MAKEMASK1_32(7)
+#define M_LDT_CMD_SERR_EN               _SB_MAKEMASK1_32(8)
+#define M_LDT_CMD_FASTB2B_EN            _SB_MAKEMASK1_32(9)
+
+/*
+ * LDT class and revision registers
+ */
+
+#define S_LDT_CLASSREV_REV              0
+#define M_LDT_CLASSREV_REV              _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
+#define V_LDT_CLASSREV_REV(x)           _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
+#define G_LDT_CLASSREV_REV(x)           _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
+
+#define S_LDT_CLASSREV_CLASS            8
+#define M_LDT_CLASSREV_CLASS            _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
+#define V_LDT_CLASSREV_CLASS(x)         _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
+#define G_LDT_CLASSREV_CLASS(x)         _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
+
+#define K_LDT_REV                       0x01
+#define K_LDT_CLASS                     0x060000
+
+/*
+ * Device Header (offset 0x0C)
+ */
+
+#define S_LDT_DEVHDR_CLINESZ            0
+#define M_LDT_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
+#define V_LDT_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
+#define G_LDT_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
+
+#define S_LDT_DEVHDR_LATTMR             8
+#define M_LDT_DEVHDR_LATTMR             _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
+#define V_LDT_DEVHDR_LATTMR(x)          _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
+#define G_LDT_DEVHDR_LATTMR(x)          _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
+
+#define S_LDT_DEVHDR_HDRTYPE            16
+#define M_LDT_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
+#define V_LDT_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
+#define G_LDT_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
+
+#define K_LDT_DEVHDR_HDRTYPE_TYPE1      1
+
+#define S_LDT_DEVHDR_BIST               24
+#define M_LDT_DEVHDR_BIST               _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
+#define V_LDT_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
+#define G_LDT_DEVHDR_BIST(x)            _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
+
+
+
+/*
+ * LDT Status Register (Table 8-14).  Note that these constants
+ * assume you've read the command and status register
+ * together (32-bit read at offset 0x04)
+ *
+ * These bits also apply to the secondary status
+ * register (Table 8-15), offset 0x1C
+ */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_STATUS_VGAEN              _SB_MAKEMASK1_32(3)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_LDT_STATUS_CAPLIST            _SB_MAKEMASK1_32(20)
+#define M_LDT_STATUS_66MHZCAP           _SB_MAKEMASK1_32(21)
+#define M_LDT_STATUS_RESERVED2          _SB_MAKEMASK1_32(22)
+#define M_LDT_STATUS_FASTB2BCAP         _SB_MAKEMASK1_32(23)
+#define M_LDT_STATUS_MSTRDPARERR        _SB_MAKEMASK1_32(24)
+
+#define S_LDT_STATUS_DEVSELTIMING       25
+#define M_LDT_STATUS_DEVSELTIMING       _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
+#define V_LDT_STATUS_DEVSELTIMING(x)    _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
+#define G_LDT_STATUS_DEVSELTIMING(x)    _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
+
+#define M_LDT_STATUS_SIGDTGTABORT       _SB_MAKEMASK1_32(27)
+#define M_LDT_STATUS_RCVDTGTABORT       _SB_MAKEMASK1_32(28)
+#define M_LDT_STATUS_RCVDMSTRABORT      _SB_MAKEMASK1_32(29)
+#define M_LDT_STATUS_SIGDSERR           _SB_MAKEMASK1_32(30)
+#define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
+
+/*
+ * Bridge Control Register (Table 8-16).  Note that these
+ * constants assume you've read the register as a 32-bit
+ * read (offset 0x3C)
+ */
+
+#define M_LDT_BRCTL_PARERRRESP_EN       _SB_MAKEMASK1_32(16)
+#define M_LDT_BRCTL_SERR_EN             _SB_MAKEMASK1_32(17)
+#define M_LDT_BRCTL_ISA_EN              _SB_MAKEMASK1_32(18)
+#define M_LDT_BRCTL_VGA_EN              _SB_MAKEMASK1_32(19)
+#define M_LDT_BRCTL_MSTRABORTMODE       _SB_MAKEMASK1_32(21)
+#define M_LDT_BRCTL_SECBUSRESET         _SB_MAKEMASK1_32(22)
+#define M_LDT_BRCTL_FASTB2B_EN          _SB_MAKEMASK1_32(23)
+#define M_LDT_BRCTL_PRIDISCARD          _SB_MAKEMASK1_32(24)
+#define M_LDT_BRCTL_SECDISCARD          _SB_MAKEMASK1_32(25)
+#define M_LDT_BRCTL_DISCARDSTAT         _SB_MAKEMASK1_32(26)
+#define M_LDT_BRCTL_DISCARDSERR_EN      _SB_MAKEMASK1_32(27)
+
+/*
+ * LDT Command Register (Table 8-17).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x40
+ */
+
+#define M_LDT_CMD_WARMRESET             _SB_MAKEMASK1_32(16)
+#define M_LDT_CMD_DOUBLEENDED           _SB_MAKEMASK1_32(17)
+
+#define S_LDT_CMD_CAPTYPE               29
+#define M_LDT_CMD_CAPTYPE               _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
+#define V_LDT_CMD_CAPTYPE(x)            _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
+#define G_LDT_CMD_CAPTYPE(x)            _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
+
+/*
+ * LDT link control register (Table 8-18), and (Table 8-19)
+ */
+
+#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN  _SB_MAKEMASK1_32(1)
+#define M_LDT_LINKCTRL_CRCSTARTTEST     _SB_MAKEMASK1_32(2)
+#define M_LDT_LINKCTRL_CRCFORCEERR      _SB_MAKEMASK1_32(3)
+#define M_LDT_LINKCTRL_LINKFAIL         _SB_MAKEMASK1_32(4)
+#define M_LDT_LINKCTRL_INITDONE         _SB_MAKEMASK1_32(5)
+#define M_LDT_LINKCTRL_EOC              _SB_MAKEMASK1_32(6)
+#define M_LDT_LINKCTRL_XMITOFF          _SB_MAKEMASK1_32(7)
+
+#define S_LDT_LINKCTRL_CRCERR           8
+#define M_LDT_LINKCTRL_CRCERR           _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
+#define V_LDT_LINKCTRL_CRCERR(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
+#define G_LDT_LINKCTRL_CRCERR(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
+
+#define S_LDT_LINKCTRL_MAXIN            16
+#define M_LDT_LINKCTRL_MAXIN            _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
+#define V_LDT_LINKCTRL_MAXIN(x)         _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
+#define G_LDT_LINKCTRL_MAXIN(x)         _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
+
+#define M_LDT_LINKCTRL_DWFCLN           _SB_MAKEMASK1_32(19)
+
+#define S_LDT_LINKCTRL_MAXOUT           20
+#define M_LDT_LINKCTRL_MAXOUT           _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
+#define V_LDT_LINKCTRL_MAXOUT(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
+#define G_LDT_LINKCTRL_MAXOUT(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT          _SB_MAKEMASK1_32(23)
+
+#define S_LDT_LINKCTRL_WIDTHIN          24
+#define M_LDT_LINKCTRL_WIDTHIN          _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
+#define V_LDT_LINKCTRL_WIDTHIN(x)       _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
+#define G_LDT_LINKCTRL_WIDTHIN(x)       _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
+
+#define M_LDT_LINKCTRL_DWFCLIN_EN       _SB_MAKEMASK1_32(27)
+
+#define S_LDT_LINKCTRL_WIDTHOUT         28
+#define M_LDT_LINKCTRL_WIDTHOUT         _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
+#define V_LDT_LINKCTRL_WIDTHOUT(x)      _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
+#define G_LDT_LINKCTRL_WIDTHOUT(x)      _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT_EN       _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Link frequency register  (Table 8-20) offset 0x48
+ */
+
+#define S_LDT_LINKFREQ_FREQ             8
+#define M_LDT_LINKFREQ_FREQ             _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
+#define V_LDT_LINKFREQ_FREQ(x)          _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
+#define G_LDT_LINKFREQ_FREQ(x)          _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
+
+#define K_LDT_LINKFREQ_200MHZ           0
+#define K_LDT_LINKFREQ_300MHZ           1
+#define K_LDT_LINKFREQ_400MHZ           2
+#define K_LDT_LINKFREQ_500MHZ           3
+#define K_LDT_LINKFREQ_600MHZ           4
+#define K_LDT_LINKFREQ_800MHZ           5
+#define K_LDT_LINKFREQ_1000MHZ          6
+
+/*
+ * LDT SRI Command Register (Table 8-21).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x50
+ */
+
+#define M_LDT_SRICMD_SIPREADY           _SB_MAKEMASK1_32(16)
+#define M_LDT_SRICMD_SYNCPTRCTL         _SB_MAKEMASK1_32(17)
+#define M_LDT_SRICMD_REDUCESYNCZERO     _SB_MAKEMASK1_32(18)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_LDT_SRICMD_DISSTARVATIONCNT   _SB_MAKEMASK1_32(19)    /* PASS1 */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_SRICMD_DISMULTTXVLD       _SB_MAKEMASK1_32(19)
+#define M_LDT_SRICMD_EXPENDIAN          _SB_MAKEMASK1_32(26)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+#define S_LDT_SRICMD_RXMARGIN           20
+#define M_LDT_SRICMD_RXMARGIN           _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
+#define V_LDT_SRICMD_RXMARGIN(x)        _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
+#define G_LDT_SRICMD_RXMARGIN(x)        _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
+
+#define M_LDT_SRICMD_LDTPLLCOMPAT       _SB_MAKEMASK1_32(25)
+
+#define S_LDT_SRICMD_TXINITIALOFFSET    28
+#define M_LDT_SRICMD_TXINITIALOFFSET    _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
+#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
+#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
+
+#define M_LDT_SRICMD_LINKFREQDIRECT     _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Error control and status register (Table 8-22) (Table 8-23)
+ */
+
+#define M_LDT_ERRCTL_PROTFATAL_EN       _SB_MAKEMASK1_32(0)
+#define M_LDT_ERRCTL_PROTNONFATAL_EN    _SB_MAKEMASK1_32(1)
+#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN   _SB_MAKEMASK1_32(2)
+#define M_LDT_ERRCTL_OVFFATAL_EN        _SB_MAKEMASK1_32(3)
+#define M_LDT_ERRCTL_OVFNONFATAL_EN     _SB_MAKEMASK1_32(4)
+#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN    _SB_MAKEMASK1_32(5)
+#define M_LDT_ERRCTL_EOCNXAFATAL_EN     _SB_MAKEMASK1_32(6)
+#define M_LDT_ERRCTL_EOCNXANONFATAL_EN  _SB_MAKEMASK1_32(7)
+#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
+#define M_LDT_ERRCTL_CRCFATAL_EN        _SB_MAKEMASK1_32(9)
+#define M_LDT_ERRCTL_CRCNONFATAL_EN     _SB_MAKEMASK1_32(10)
+#define M_LDT_ERRCTL_SERRFATAL_EN       _SB_MAKEMASK1_32(11)
+#define M_LDT_ERRCTL_SRCTAGFATAL_EN     _SB_MAKEMASK1_32(12)
+#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN  _SB_MAKEMASK1_32(13)
+#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
+#define M_LDT_ERRCTL_MAPNXAFATAL_EN     _SB_MAKEMASK1_32(15)
+#define M_LDT_ERRCTL_MAPNXANONFATAL_EN  _SB_MAKEMASK1_32(16)
+#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
+
+#define M_LDT_ERRCTL_PROTOERR           _SB_MAKEMASK1_32(24)
+#define M_LDT_ERRCTL_OVFERR             _SB_MAKEMASK1_32(25)
+#define M_LDT_ERRCTL_EOCNXAERR          _SB_MAKEMASK1_32(26)
+#define M_LDT_ERRCTL_SRCTAGERR          _SB_MAKEMASK1_32(27)
+#define M_LDT_ERRCTL_MAPNXAERR          _SB_MAKEMASK1_32(28)
+
+/*
+ * SRI Control register (Table 8-24, 8-25)  Offset 0x6C
+ */
+
+#define S_LDT_SRICTRL_NEEDRESP          0
+#define M_LDT_SRICTRL_NEEDRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
+#define V_LDT_SRICTRL_NEEDRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
+#define G_LDT_SRICTRL_NEEDRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
+
+#define S_LDT_SRICTRL_NEEDNPREQ         2
+#define M_LDT_SRICTRL_NEEDNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
+#define V_LDT_SRICTRL_NEEDNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
+#define G_LDT_SRICTRL_NEEDNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
+
+#define S_LDT_SRICTRL_NEEDPREQ          4
+#define M_LDT_SRICTRL_NEEDPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
+#define V_LDT_SRICTRL_NEEDPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
+#define G_LDT_SRICTRL_NEEDPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
+
+#define S_LDT_SRICTRL_WANTRESP          8
+#define M_LDT_SRICTRL_WANTRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
+#define V_LDT_SRICTRL_WANTRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
+#define G_LDT_SRICTRL_WANTRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
+
+#define S_LDT_SRICTRL_WANTNPREQ         10
+#define M_LDT_SRICTRL_WANTNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
+#define V_LDT_SRICTRL_WANTNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
+#define G_LDT_SRICTRL_WANTNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
+
+#define S_LDT_SRICTRL_WANTPREQ          12
+#define M_LDT_SRICTRL_WANTPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
+#define V_LDT_SRICTRL_WANTPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
+#define G_LDT_SRICTRL_WANTPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
+
+#define S_LDT_SRICTRL_BUFRELSPACE       16
+#define M_LDT_SRICTRL_BUFRELSPACE       _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
+#define V_LDT_SRICTRL_BUFRELSPACE(x)    _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
+#define G_LDT_SRICTRL_BUFRELSPACE(x)    _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
+
+/*
+ * LDT SRI Transmit Buffer Count register (Table 8-26)
+ */
+
+#define S_LDT_TXBUFCNT_PCMD             0
+#define M_LDT_TXBUFCNT_PCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
+#define V_LDT_TXBUFCNT_PCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
+#define G_LDT_TXBUFCNT_PCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
+
+#define S_LDT_TXBUFCNT_PDATA            4
+#define M_LDT_TXBUFCNT_PDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
+#define V_LDT_TXBUFCNT_PDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
+#define G_LDT_TXBUFCNT_PDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
+
+#define S_LDT_TXBUFCNT_NPCMD            8
+#define M_LDT_TXBUFCNT_NPCMD            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
+#define V_LDT_TXBUFCNT_NPCMD(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
+#define G_LDT_TXBUFCNT_NPCMD(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
+
+#define S_LDT_TXBUFCNT_NPDATA           12
+#define M_LDT_TXBUFCNT_NPDATA           _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
+#define V_LDT_TXBUFCNT_NPDATA(x)        _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
+#define G_LDT_TXBUFCNT_NPDATA(x)        _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
+
+#define S_LDT_TXBUFCNT_RCMD             16
+#define M_LDT_TXBUFCNT_RCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
+#define V_LDT_TXBUFCNT_RCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
+#define G_LDT_TXBUFCNT_RCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
+
+#define S_LDT_TXBUFCNT_RDATA            20
+#define M_LDT_TXBUFCNT_RDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
+#define V_LDT_TXBUFCNT_RDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
+#define G_LDT_TXBUFCNT_RDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Additional Status Register
+ */
+
+#define S_LDT_ADDSTATUS_TGTDONE         0
+#define M_LDT_ADDSTATUS_TGTDONE         _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
+#define V_LDT_ADDSTATUS_TGTDONE(x)      _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
+#define G_LDT_ADDSTATUS_TGTDONE(x)      _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
new file mode 100644
index 000000000..3ddbd4b5d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -0,0 +1,643 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  MAC constants and macros                 File: sb1250_mac.h
+    *
+    *  This module contains constants and macros for the SB1250's
+    *  ethernet controllers.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MAC_H
+#define _SB1250_MAC_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  Ethernet MAC Registers
+    ********************************************************************* */
+
+/*
+ * MAC Configuration Register (Table 9-13)
+ * Register: MAC_CFG_0
+ * Register: MAC_CFG_1
+ * Register: MAC_CFG_2
+ */
+
+
+#define M_MAC_RESERVED0             _SB_MAKEMASK1(0)
+#define M_MAC_TX_HOLD_SOP_EN        _SB_MAKEMASK1(1)
+#define M_MAC_RETRY_EN              _SB_MAKEMASK1(2)
+#define M_MAC_RET_DRPREQ_EN         _SB_MAKEMASK1(3)
+#define M_MAC_RET_UFL_EN            _SB_MAKEMASK1(4)
+#define M_MAC_BURST_EN              _SB_MAKEMASK1(5)
+
+#define S_MAC_TX_PAUSE              _SB_MAKE64(6)
+#define M_MAC_TX_PAUSE_CNT          _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
+#define V_MAC_TX_PAUSE_CNT(x)       _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
+
+#define K_MAC_TX_PAUSE_CNT_512      0
+#define K_MAC_TX_PAUSE_CNT_1K       1
+#define K_MAC_TX_PAUSE_CNT_2K       2
+#define K_MAC_TX_PAUSE_CNT_4K       3
+#define K_MAC_TX_PAUSE_CNT_8K       4
+#define K_MAC_TX_PAUSE_CNT_16K      5
+#define K_MAC_TX_PAUSE_CNT_32K      6
+#define K_MAC_TX_PAUSE_CNT_64K      7
+
+#define V_MAC_TX_PAUSE_CNT_512      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
+#define V_MAC_TX_PAUSE_CNT_1K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
+#define V_MAC_TX_PAUSE_CNT_2K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
+#define V_MAC_TX_PAUSE_CNT_4K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
+#define V_MAC_TX_PAUSE_CNT_8K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
+#define V_MAC_TX_PAUSE_CNT_16K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
+#define V_MAC_TX_PAUSE_CNT_32K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
+#define V_MAC_TX_PAUSE_CNT_64K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
+
+#define M_MAC_RESERVED1             _SB_MAKEMASK(8, 9)
+
+#define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TIMESTAMP             _SB_MAKEMASK1(18)
+#endif
+#define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
+#define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
+#define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
+#define M_MAC_DRP_DRBLERRPKT_EN     _SB_MAKEMASK1(22)
+#define M_MAC_DRP_RNTPKT_EN         _SB_MAKEMASK1(23)
+#define M_MAC_DRP_OSZPKT_EN         _SB_MAKEMASK1(24)
+#define M_MAC_DRP_LENERRPKT_EN      _SB_MAKEMASK1(25)
+
+#define M_MAC_RESERVED3             _SB_MAKEMASK(6, 26)
+
+#define M_MAC_BYPASS_SEL            _SB_MAKEMASK1(32)
+#define M_MAC_HDX_EN                _SB_MAKEMASK1(33)
+
+#define S_MAC_SPEED_SEL             _SB_MAKE64(34)
+#define M_MAC_SPEED_SEL             _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
+#define V_MAC_SPEED_SEL(x)          _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
+#define G_MAC_SPEED_SEL(x)          _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
+
+#define K_MAC_SPEED_SEL_10MBPS      0
+#define K_MAC_SPEED_SEL_100MBPS     1
+#define K_MAC_SPEED_SEL_1000MBPS    2
+#define K_MAC_SPEED_SEL_RESERVED    3
+
+#define V_MAC_SPEED_SEL_10MBPS      V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
+#define V_MAC_SPEED_SEL_100MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
+#define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
+#define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
+
+#define M_MAC_TX_CLK_EDGE_SEL       _SB_MAKEMASK1(36)
+#define M_MAC_LOOPBACK_SEL          _SB_MAKEMASK1(37)
+#define M_MAC_FAST_SYNC             _SB_MAKEMASK1(38)
+#define M_MAC_SS_EN                 _SB_MAKEMASK1(39)
+
+#define S_MAC_BYPASS_CFG            _SB_MAKE64(40)
+#define M_MAC_BYPASS_CFG            _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
+#define V_MAC_BYPASS_CFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
+#define G_MAC_BYPASS_CFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
+
+#define K_MAC_BYPASS_GMII           0
+#define K_MAC_BYPASS_ENCODED        1
+#define K_MAC_BYPASS_SOP            2
+#define K_MAC_BYPASS_EOP            3
+
+#define M_MAC_BYPASS_16             _SB_MAKEMASK1(42)
+#define M_MAC_BYPASS_FCS_CHK        _SB_MAKEMASK1(43)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
+#define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
+#define V_MAC_BYPASS_IFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
+#define G_MAC_BYPASS_IFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
+
+#define K_MAC_FC_CMD_DISABLED       0
+#define K_MAC_FC_CMD_ENABLED        1
+#define K_MAC_FC_CMD_ENAB_FALSECARR 2
+
+#define V_MAC_FC_CMD_DISABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
+#define V_MAC_FC_CMD_ENABLED        V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
+#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
+
+#define M_MAC_FC_SEL                _SB_MAKEMASK1(54)
+
+#define S_MAC_FC_CMD                _SB_MAKE64(55)
+#define M_MAC_FC_CMD                _SB_MAKEMASK(2, S_MAC_FC_CMD)
+#define V_MAC_FC_CMD(x)             _SB_MAKEVALUE(x, S_MAC_FC_CMD)
+#define G_MAC_FC_CMD(x)             _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
+
+#define S_MAC_RX_CH_SEL             _SB_MAKE64(57)
+#define M_MAC_RX_CH_SEL             _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
+#define V_MAC_RX_CH_SEL(x)          _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
+#define G_MAC_RX_CH_SEL(x)          _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
+
+
+/*
+ * MAC Enable Registers
+ * Register: MAC_ENABLE_0
+ * Register: MAC_ENABLE_1
+ * Register: MAC_ENABLE_2
+ */
+
+#define M_MAC_RXDMA_EN0             _SB_MAKEMASK1(0)
+#define M_MAC_RXDMA_EN1             _SB_MAKEMASK1(1)
+#define M_MAC_TXDMA_EN0             _SB_MAKEMASK1(4)
+#define M_MAC_TXDMA_EN1             _SB_MAKEMASK1(5)
+
+#define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
+
+#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+#define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
+#define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
+#define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
+#define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+#endif
+
+/*
+ * MAC reset information register (1280/1255)
+ */
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH0_PAUSE_ON   _SB_MAKEMASK1(8)
+#define M_MAC_RX_CH1_PAUSE_ON   _SB_MAKEMASK1(16)
+#define M_MAC_TX_CH0_PAUSE_ON   _SB_MAKEMASK1(24)
+#define M_MAC_TX_CH1_PAUSE_ON   _SB_MAKEMASK1(32)
+#endif
+
+/*
+ * MAC DMA Control Register
+ * Register: MAC_TXD_CTL_0
+ * Register: MAC_TXD_CTL_1
+ * Register: MAC_TXD_CTL_2
+ */
+
+#define S_MAC_TXD_WEIGHT0           _SB_MAKE64(0)
+#define M_MAC_TXD_WEIGHT0           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
+#define V_MAC_TXD_WEIGHT0(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
+#define G_MAC_TXD_WEIGHT0(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
+
+#define S_MAC_TXD_WEIGHT1           _SB_MAKE64(4)
+#define M_MAC_TXD_WEIGHT1           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
+#define V_MAC_TXD_WEIGHT1(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
+#define G_MAC_TXD_WEIGHT1(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
+
+/*
+ * MAC Fifo Threshold registers (Table 9-14)
+ * Register: MAC_THRSH_CFG_0
+ * Register: MAC_THRSH_CFG_1
+ * Register: MAC_THRSH_CFG_2
+ */
+
+#define S_MAC_TX_WR_THRSH           _SB_MAKE64(0)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define V_MAC_TX_WR_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
+#define G_MAC_TX_WR_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
+
+#define S_MAC_TX_RD_THRSH           _SB_MAKE64(8)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define V_MAC_TX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
+#define G_MAC_TX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
+
+#define S_MAC_TX_RL_THRSH           _SB_MAKE64(16)
+#define M_MAC_TX_RL_THRSH           _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
+#define V_MAC_TX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
+#define G_MAC_TX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
+
+#define S_MAC_RX_PL_THRSH           _SB_MAKE64(24)
+#define M_MAC_RX_PL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
+#define V_MAC_RX_PL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
+#define G_MAC_RX_PL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
+
+#define S_MAC_RX_RD_THRSH           _SB_MAKE64(32)
+#define M_MAC_RX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
+#define V_MAC_RX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
+#define G_MAC_RX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
+
+#define S_MAC_RX_RL_THRSH           _SB_MAKE64(40)
+#define M_MAC_RX_RL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
+#define V_MAC_RX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
+#define G_MAC_RX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_ENC_FC_THRSH           _SB_MAKE64(56)
+#define M_MAC_ENC_FC_THRSH           _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
+#define V_MAC_ENC_FC_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
+#define G_MAC_ENC_FC_THRSH(x)        _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Frame Configuration Registers (Table 9-15)
+ * Register: MAC_FRAME_CFG_0
+ * Register: MAC_FRAME_CFG_1
+ * Register: MAC_FRAME_CFG_2
+ */
+
+/* XXXCGD: ??? Unused in pass2? */
+#define S_MAC_IFG_RX                _SB_MAKE64(0)
+#define M_MAC_IFG_RX                _SB_MAKEMASK(6, S_MAC_IFG_RX)
+#define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_RX)
+#define G_MAC_IFG_RX(x)             _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_PRE_LEN               _SB_MAKE64(0)
+#define M_MAC_PRE_LEN               _SB_MAKEMASK(6, S_MAC_PRE_LEN)
+#define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
+#define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_MAC_IFG_TX                _SB_MAKE64(6)
+#define M_MAC_IFG_TX                _SB_MAKEMASK(6, S_MAC_IFG_TX)
+#define V_MAC_IFG_TX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_TX)
+#define G_MAC_IFG_TX(x)             _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
+
+#define S_MAC_IFG_THRSH             _SB_MAKE64(12)
+#define M_MAC_IFG_THRSH             _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
+#define V_MAC_IFG_THRSH(x)          _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
+#define G_MAC_IFG_THRSH(x)          _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
+
+#define S_MAC_BACKOFF_SEL           _SB_MAKE64(18)
+#define M_MAC_BACKOFF_SEL           _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
+#define V_MAC_BACKOFF_SEL(x)        _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
+#define G_MAC_BACKOFF_SEL(x)        _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
+
+#define S_MAC_LFSR_SEED             _SB_MAKE64(22)
+#define M_MAC_LFSR_SEED             _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
+#define V_MAC_LFSR_SEED(x)          _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
+#define G_MAC_LFSR_SEED(x)          _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
+
+#define S_MAC_SLOT_SIZE             _SB_MAKE64(30)
+#define M_MAC_SLOT_SIZE             _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
+#define V_MAC_SLOT_SIZE(x)          _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
+#define G_MAC_SLOT_SIZE(x)          _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
+
+#define S_MAC_MIN_FRAMESZ           _SB_MAKE64(40)
+#define M_MAC_MIN_FRAMESZ           _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
+#define V_MAC_MIN_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
+#define G_MAC_MIN_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
+
+#define S_MAC_MAX_FRAMESZ           _SB_MAKE64(48)
+#define M_MAC_MAX_FRAMESZ           _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
+#define V_MAC_MAX_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
+#define G_MAC_MAX_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
+
+/*
+ * These constants are used to configure the fields within the Frame
+ * Configuration Register.
+ */
+
+#define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
+#define K_MAC_IFG_RX_100            _SB_MAKE64(0)
+#define K_MAC_IFG_RX_1000           _SB_MAKE64(0)
+
+#define K_MAC_IFG_TX_10             _SB_MAKE64(20)
+#define K_MAC_IFG_TX_100            _SB_MAKE64(20)
+#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)
+
+#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)
+
+#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)
+
+#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)
+#define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
+#define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
+
+#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)
+#define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
+#define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
+
+#define V_MAC_IFG_THRSH_10     V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
+#define V_MAC_IFG_THRSH_100    V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
+#define V_MAC_IFG_THRSH_1000   V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
+
+#define V_MAC_SLOT_SIZE_10     V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
+#define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
+#define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
+
+#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)
+#define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
+#define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)
+#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)
+
+#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
+#define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
+
+/*
+ * MAC VLAN Tag Registers (Table 9-16)
+ * Register: MAC_VLANTAG_0
+ * Register: MAC_VLANTAG_1
+ * Register: MAC_VLANTAG_2
+ */
+
+#define S_MAC_VLAN_TAG           _SB_MAKE64(0)
+#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
+#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
+#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)
+#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
+#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
+#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
+
+#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)
+#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
+#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
+#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
+
+#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * MAC Status Registers (Table 9-17)
+ * Also used for the MAC Interrupt Mask Register (Table 9-18)
+ * Register: MAC_STATUS_0
+ * Register: MAC_STATUS_1
+ * Register: MAC_STATUS_2
+ * Register: MAC_INT_MASK_0
+ * Register: MAC_INT_MASK_1
+ * Register: MAC_INT_MASK_2
+ */
+
+/*
+ * Use these constants to shift the appropriate channel
+ * into the CH0 position so the same tests can be used
+ * on each channel.
+ */
+
+#define S_MAC_RX_CH0                _SB_MAKE64(0)
+#define S_MAC_RX_CH1                _SB_MAKE64(8)
+#define S_MAC_TX_CH0                _SB_MAKE64(16)
+#define S_MAC_TX_CH1                _SB_MAKE64(24)
+
+#define S_MAC_TXCHANNELS            _SB_MAKE64(16)      /* this is 1st TX chan */
+#define S_MAC_CHANWIDTH             _SB_MAKE64(8)       /* bits between channels */
+
+/*
+ *  These are the same as RX channel 0.  The idea here
+ *  is that you'll use one of the "S_" things above
+ *  and pass just the six bits to a DMA-channel-specific ISR
+ */
+#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8, 0)
+#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)
+#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)
+#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)
+#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)
+#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)
+#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)
+#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)
+#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)    /* only for TX channels */
+#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)    /* only for RX channels */
+
+/*
+ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
+ * also DMA_TX/DMA_RX in sb_regs.h).
+ */
+#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
+
+#define M_MAC_STATUS_CHANNEL(ch, txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_SEEN(ch, txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_HWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_LWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DSCR(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_ERR(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DZERO(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DROP(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_OTHER_ERR           _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
+
+
+#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)
+#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)
+#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)
+#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)
+#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)
+#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)
+#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_SPLIT_EN              _SB_MAKEMASK1(47)   /* interrupt mask only */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)
+#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
+#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
+#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
+ * Register: MAC_FIFO_PTRS_0
+ * Register: MAC_FIFO_PTRS_1
+ * Register: MAC_FIFO_PTRS_2
+ */
+
+#define S_MAC_TX_WRPTR              _SB_MAKE64(0)
+#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
+#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
+#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
+
+#define S_MAC_TX_RDPTR              _SB_MAKE64(8)
+#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
+#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
+#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
+
+#define S_MAC_RX_WRPTR              _SB_MAKE64(16)
+#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
+#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
+#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
+
+#define S_MAC_RX_RDPTR              _SB_MAKE64(24)
+#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
+#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
+#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
+
+/*
+ * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register]
+ * Register: MAC_EOPCNT_0
+ * Register: MAC_EOPCNT_1
+ * Register: MAC_EOPCNT_2
+ */
+
+#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)
+#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
+#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
+#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
+
+#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)
+#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
+#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
+#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
+
+/*
+ * MAC Receive Address Filter Exact Match Registers (Table 9-21)
+ * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
+ * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
+ * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Receive Address Filter Mask Registers
+ * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
+ * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
+ * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Receive Address Filter Hash Match Registers (Table 9-22)
+ * Registers: MAC_HASH0_0 through MAC_HASH7_0
+ * Registers: MAC_HASH0_1 through MAC_HASH7_1
+ * Registers: MAC_HASH0_2 through MAC_HASH7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Transmit Source Address Registers (Table 9-23)
+ * Register: MAC_ETHERNET_ADDR_0
+ * Register: MAC_ETHERNET_ADDR_1
+ * Register: MAC_ETHERNET_ADDR_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Packet Type Configuration Register
+ * Register: MAC_TYPE_CFG_0
+ * Register: MAC_TYPE_CFG_1
+ * Register: MAC_TYPE_CFG_2
+ */
+
+#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)
+
+#define S_TYPECFG_TYPE0         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
+#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
+#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
+
+#define S_TYPECFG_TYPE1         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
+#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
+#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
+
+#define S_TYPECFG_TYPE2         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
+#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
+#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
+
+#define S_TYPECFG_TYPE3         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
+#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
+#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
+
+/*
+ * MAC Receive Address Filter Control Registers (Table 9-24)
+ * Register: MAC_ADFILTER_CFG_0
+ * Register: MAC_ADFILTER_CFG_1
+ * Register: MAC_ADFILTER_CFG_2
+ */
+
+#define M_MAC_ALLPKT_EN         _SB_MAKEMASK1(0)
+#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)
+#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)
+#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)
+#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)
+#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)
+#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_ALLMCAST_EN       _SB_MAKEMASK1(7)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)
+#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
+#define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
+#define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
+#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
+#define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
+#define G_MAC_RX_CRC_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
+
+#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)
+#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
+#define V_MAC_RX_PKT_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
+#define G_MAC_RX_PKT_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
+
+#define M_MAC_FWDPAUSE_EN       _SB_MAKEMASK1(32)
+#define M_MAC_VLAN_DET_EN       _SB_MAKEMASK1(33)
+
+#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)
+#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
+#define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
+#define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Receive Channel Select Registers (Table 9-25)
+ */
+
+/* no bitfields */
+
+/*
+ * MAC MII Management Interface Registers (Table 9-26)
+ * Register: MAC_MDIO_0
+ * Register: MAC_MDIO_1
+ * Register: MAC_MDIO_2
+ */
+
+#define S_MAC_MDC               0
+#define S_MAC_MDIO_DIR          1
+#define S_MAC_MDIO_OUT          2
+#define S_MAC_GENC              3
+#define S_MAC_MDIO_IN           4
+
+#define M_MAC_MDC               _SB_MAKEMASK1(S_MAC_MDC)
+#define M_MAC_MDIO_DIR          _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_DIR_INPUT    _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_OUT          _SB_MAKEMASK1(S_MAC_MDIO_OUT)
+#define M_MAC_GENC              _SB_MAKEMASK1(S_MAC_GENC)
+#define M_MAC_MDIO_IN           _SB_MAKEMASK1(S_MAC_MDIO_IN)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
new file mode 100644
index 000000000..c02fe823e
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Memory Controller constants              File: sb1250_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MC_H
+#define _SB1250_MC_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Memory Channel Config Register (table 6-14)
+ */
+
+#define S_MC_RESERVED0              0
+#define M_MC_RESERVED0              _SB_MAKEMASK(8, S_MC_RESERVED0)
+
+#define S_MC_CHANNEL_SEL            8
+#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
+#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
+#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
+
+#define S_MC_BANK0_MAP              16
+#define M_MC_BANK0_MAP              _SB_MAKEMASK(4, S_MC_BANK0_MAP)
+#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
+#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
+
+#define K_MC_BANK0_MAP_DEFAULT      0x00
+#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
+
+#define S_MC_BANK1_MAP              20
+#define M_MC_BANK1_MAP              _SB_MAKEMASK(4, S_MC_BANK1_MAP)
+#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
+#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
+
+#define K_MC_BANK1_MAP_DEFAULT      0x08
+#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
+
+#define S_MC_BANK2_MAP              24
+#define M_MC_BANK2_MAP              _SB_MAKEMASK(4, S_MC_BANK2_MAP)
+#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
+#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
+
+#define K_MC_BANK2_MAP_DEFAULT      0x09
+#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
+
+#define S_MC_BANK3_MAP              28
+#define M_MC_BANK3_MAP              _SB_MAKEMASK(4, S_MC_BANK3_MAP)
+#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
+#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
+
+#define K_MC_BANK3_MAP_DEFAULT      0x0C
+#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
+
+#define M_MC_RESERVED1              _SB_MAKEMASK(8, 32)
+
+#define S_MC_QUEUE_SIZE             40
+#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
+#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)
+
+#define S_MC_AGE_LIMIT              44
+#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
+#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)
+
+#define S_MC_WR_LIMIT               48
+#define M_MC_WR_LIMIT               _SB_MAKEMASK(4, S_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
+#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)
+
+#define M_MC_IOB1HIGHPRIORITY       _SB_MAKEMASK1(52)
+
+#define M_MC_RESERVED2              _SB_MAKEMASK(3, 53)
+
+#define S_MC_CS_MODE                56
+#define M_MC_CS_MODE                _SB_MAKEMASK(4, S_MC_CS_MODE)
+#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_MC_CS_MODE)
+#define G_MC_CS_MODE(x)             _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
+
+#define K_MC_CS_MODE_MSB_CS         0
+#define K_MC_CS_MODE_INTLV_CS       15
+#define K_MC_CS_MODE_MIXED_CS_10    12
+#define K_MC_CS_MODE_MIXED_CS_30    6
+#define K_MC_CS_MODE_MIXED_CS_32    3
+
+#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
+#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
+#define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
+#define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
+#define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
+
+#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)
+#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)
+#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)
+#define M_MC_DEBUG                  _SB_MAKEMASK1(63)
+
+#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
+                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
+                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
+                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
+
+
+/*
+ * Memory clock config register (Table 6-15)
+ *
+ * Note: this field has been updated to be consistent with the errata to 0.2
+ */
+
+#define S_MC_CLK_RATIO              0
+#define M_MC_CLK_RATIO              _SB_MAKEMASK(4, S_MC_CLK_RATIO)
+#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
+#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
+
+#define K_MC_CLK_RATIO_2X           4
+#define K_MC_CLK_RATIO_25X          5
+#define K_MC_CLK_RATIO_3X           6
+#define K_MC_CLK_RATIO_35X          7
+#define K_MC_CLK_RATIO_4X           8
+#define K_MC_CLK_RATIO_45X          9
+
+#define V_MC_CLK_RATIO_2X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
+#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
+#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
+#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
+#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
+#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
+#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X
+
+#define S_MC_REF_RATE                8
+#define M_MC_REF_RATE                _SB_MAKEMASK(8, S_MC_REF_RATE)
+#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x, S_MC_REF_RATE)
+#define G_MC_REF_RATE(x)             _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
+
+#define K_MC_REF_RATE_100MHz         0x62
+#define K_MC_REF_RATE_133MHz         0x81
+#define K_MC_REF_RATE_200MHz         0xC4
+
+#define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
+#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
+#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
+#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz
+
+#define S_MC_CLOCK_DRIVE             16
+#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
+#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
+
+#define S_MC_DATA_DRIVE              20
+#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
+#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)
+
+#define S_MC_ADDR_DRIVE              24
+#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
+#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)
+
+#define S_MC_DQI_SKEW               32
+#define M_MC_DQI_SKEW               _SB_MAKEMASK(8, S_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
+#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)
+
+#define S_MC_DQO_SKEW               40
+#define M_MC_DQO_SKEW               _SB_MAKEMASK(8, S_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
+#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)
+
+#define S_MC_ADDR_SKEW               48
+#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
+#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)
+
+#define S_MC_DLL_DEFAULT             56
+#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
+#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
+
+#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \
+                                     V_MC_ADDR_SKEW_DEFAULT | \
+                                     V_MC_DQO_SKEW_DEFAULT | \
+                                     V_MC_DQI_SKEW_DEFAULT | \
+                                     V_MC_ADDR_DRIVE_DEFAULT | \
+                                     V_MC_DATA_DRIVE_DEFAULT | \
+                                     V_MC_CLOCK_DRIVE_DEFAULT | \
+                                     V_MC_REF_RATE_DEFAULT
+
+
+
+/*
+ * DRAM Command Register (Table 6-13)
+ */
+
+#define S_MC_COMMAND                0
+#define M_MC_COMMAND                _SB_MAKEMASK(4, S_MC_COMMAND)
+#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_MC_COMMAND)
+#define G_MC_COMMAND(x)             _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
+
+#define K_MC_COMMAND_EMRS           0
+#define K_MC_COMMAND_MRS            1
+#define K_MC_COMMAND_PRE            2
+#define K_MC_COMMAND_AR             3
+#define K_MC_COMMAND_SETRFSH        4
+#define K_MC_COMMAND_CLRRFSH        5
+#define K_MC_COMMAND_SETPWRDN       6
+#define K_MC_COMMAND_CLRPWRDN       7
+
+#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)
+#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)
+#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)
+#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)
+#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
+#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
+#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
+#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
+
+#define M_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_MC_CS3                    _SB_MAKEMASK1(7)
+
+/*
+ * DRAM Mode Register (Table 6-14)
+ */
+
+#define S_MC_EMODE                  0
+#define M_MC_EMODE                  _SB_MAKEMASK(15, S_MC_EMODE)
+#define V_MC_EMODE(x)               _SB_MAKEVALUE(x, S_MC_EMODE)
+#define G_MC_EMODE(x)               _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
+#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)
+
+#define S_MC_MODE                   16
+#define M_MC_MODE                   _SB_MAKEMASK(15, S_MC_MODE)
+#define V_MC_MODE(x)                _SB_MAKEVALUE(x, S_MC_MODE)
+#define G_MC_MODE(x)                _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
+#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)
+
+#define S_MC_DRAM_TYPE              32
+#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
+#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
+#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
+
+#define K_MC_DRAM_TYPE_JEDEC        0
+#define K_MC_DRAM_TYPE_FCRAM        1
+#define K_MC_DRAM_TYPE_SGRAM        2
+
+#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
+#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
+#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
+
+#define M_MC_EXTERNALDECODE         _SB_MAKEMASK1(35)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
+#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(37)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+
+/*
+ * SDRAM Timing Register  (Table 6-15)
+ */
+
+#define M_MC_w2rIDLE_TWOCYCLES    _SB_MAKEMASK1(60)
+#define M_MC_r2wIDLE_TWOCYCLES    _SB_MAKEMASK1(61)
+#define M_MC_r2rIDLE_TWOCYCLES    _SB_MAKEMASK1(62)
+
+#define S_MC_tFIFO                56
+#define M_MC_tFIFO                _SB_MAKEMASK(4, S_MC_tFIFO)
+#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x, S_MC_tFIFO)
+#define G_MC_tFIFO(x)             _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
+#define K_MC_tFIFO_DEFAULT        1
+#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
+
+#define S_MC_tRFC                 52
+#define M_MC_tRFC                 _SB_MAKEMASK(4, S_MC_tRFC)
+#define V_MC_tRFC(x)              _SB_MAKEVALUE(x, S_MC_tRFC)
+#define G_MC_tRFC(x)              _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
+#define K_MC_tRFC_DEFAULT         12
+#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)     /* 1250C3 and later.  */
+#endif
+
+#define S_MC_tCwCr                40
+#define M_MC_tCwCr                _SB_MAKEMASK(4, S_MC_tCwCr)
+#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x, S_MC_tCwCr)
+#define G_MC_tCwCr(x)             _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
+#define K_MC_tCwCr_DEFAULT        4
+#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
+
+#define S_MC_tRCr                 28
+#define M_MC_tRCr                 _SB_MAKEMASK(4, S_MC_tRCr)
+#define V_MC_tRCr(x)              _SB_MAKEVALUE(x, S_MC_tRCr)
+#define G_MC_tRCr(x)              _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
+#define K_MC_tRCr_DEFAULT         9
+#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)
+
+#define S_MC_tRCw                 24
+#define M_MC_tRCw                 _SB_MAKEMASK(4, S_MC_tRCw)
+#define V_MC_tRCw(x)              _SB_MAKEVALUE(x, S_MC_tRCw)
+#define G_MC_tRCw(x)              _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
+#define K_MC_tRCw_DEFAULT         10
+#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)
+
+#define S_MC_tRRD                 20
+#define M_MC_tRRD                 _SB_MAKEMASK(4, S_MC_tRRD)
+#define V_MC_tRRD(x)              _SB_MAKEVALUE(x, S_MC_tRRD)
+#define G_MC_tRRD(x)              _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
+#define K_MC_tRRD_DEFAULT         2
+#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)
+
+#define S_MC_tRP                  16
+#define M_MC_tRP                  _SB_MAKEMASK(4, S_MC_tRP)
+#define V_MC_tRP(x)               _SB_MAKEVALUE(x, S_MC_tRP)
+#define G_MC_tRP(x)               _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
+#define K_MC_tRP_DEFAULT          4
+#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)
+
+#define S_MC_tCwD                 8
+#define M_MC_tCwD                 _SB_MAKEMASK(4, S_MC_tCwD)
+#define V_MC_tCwD(x)              _SB_MAKEVALUE(x, S_MC_tCwD)
+#define G_MC_tCwD(x)              _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
+#define K_MC_tCwD_DEFAULT         1
+#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)
+
+#define M_tCrDh                   _SB_MAKEMASK1(7)
+#define M_MC_tCrDh                M_tCrDh
+
+#define S_MC_tCrD                 4
+#define M_MC_tCrD                 _SB_MAKEMASK(3, S_MC_tCrD)
+#define V_MC_tCrD(x)              _SB_MAKEVALUE(x, S_MC_tCrD)
+#define G_MC_tCrD(x)              _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
+#define K_MC_tCrD_DEFAULT         2
+#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)
+
+#define S_MC_tRCD                 0
+#define M_MC_tRCD                 _SB_MAKEMASK(4, S_MC_tRCD)
+#define V_MC_tRCD(x)              _SB_MAKEVALUE(x, S_MC_tRCD)
+#define G_MC_tRCD(x)              _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
+#define K_MC_tRCD_DEFAULT         3
+#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)
+
+#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
+                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
+                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
+                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
+                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
+                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
+                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
+                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
+                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
+                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
+                                M_MC_r2rIDLE_TWOCYCLES
+
+/*
+ * Errata says these are not the default
+ *                               M_MC_w2rIDLE_TWOCYCLES | \
+ *                               M_MC_r2wIDLE_TWOCYCLES | \
+ */
+
+
+/*
+ * Chip Select Start Address Register (Table 6-17)
+ */
+
+#define S_MC_CS0_START              0
+#define M_MC_CS0_START              _SB_MAKEMASK(16, S_MC_CS0_START)
+#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_MC_CS0_START)
+#define G_MC_CS0_START(x)           _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
+
+#define S_MC_CS1_START              16
+#define M_MC_CS1_START              _SB_MAKEMASK(16, S_MC_CS1_START)
+#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_MC_CS1_START)
+#define G_MC_CS1_START(x)           _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
+
+#define S_MC_CS2_START              32
+#define M_MC_CS2_START              _SB_MAKEMASK(16, S_MC_CS2_START)
+#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_MC_CS2_START)
+#define G_MC_CS2_START(x)           _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
+
+#define S_MC_CS3_START              48
+#define M_MC_CS3_START              _SB_MAKEMASK(16, S_MC_CS3_START)
+#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_MC_CS3_START)
+#define G_MC_CS3_START(x)           _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 6-18)
+ */
+
+#define S_MC_CS0_END                0
+#define M_MC_CS0_END                _SB_MAKEMASK(16, S_MC_CS0_END)
+#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_MC_CS0_END)
+#define G_MC_CS0_END(x)             _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
+
+#define S_MC_CS1_END                16
+#define M_MC_CS1_END                _SB_MAKEMASK(16, S_MC_CS1_END)
+#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_MC_CS1_END)
+#define G_MC_CS1_END(x)             _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
+
+#define S_MC_CS2_END                32
+#define M_MC_CS2_END                _SB_MAKEMASK(16, S_MC_CS2_END)
+#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_MC_CS2_END)
+#define G_MC_CS2_END(x)             _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
+
+#define S_MC_CS3_END                48
+#define M_MC_CS3_END                _SB_MAKEMASK(16, S_MC_CS3_END)
+#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_MC_CS3_END)
+#define G_MC_CS3_END(x)             _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
+
+/*
+ * Chip Select Interleave Register (Table 6-19)
+ */
+
+#define S_MC_INTLV_RESERVED         0
+#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
+
+#define S_MC_INTERLEAVE             7
+#define M_MC_INTERLEAVE             _SB_MAKEMASK(18, S_MC_INTERLEAVE)
+#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
+
+#define S_MC_INTLV_MBZ              25
+#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
+
+/*
+ * Row Address Bits Register (Table 6-20)
+ */
+
+#define S_MC_RAS_RESERVED           0
+#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
+
+#define S_MC_RAS_SELECT             12
+#define M_MC_RAS_SELECT             _SB_MAKEMASK(25, S_MC_RAS_SELECT)
+#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
+
+#define S_MC_RAS_MBZ                37
+#define M_MC_RAS_MBZ                _SB_MAKEMASK(27, S_MC_RAS_MBZ)
+
+
+/*
+ * Column Address Bits Register (Table 6-21)
+ */
+
+#define S_MC_CAS_RESERVED           0
+#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
+
+#define S_MC_CAS_SELECT             5
+#define M_MC_CAS_SELECT             _SB_MAKEMASK(18, S_MC_CAS_SELECT)
+#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
+
+#define S_MC_CAS_MBZ                23
+#define M_MC_CAS_MBZ                _SB_MAKEMASK(41, S_MC_CAS_MBZ)
+
+
+/*
+ * Bank Address Address Bits Register (Table 6-22)
+ */
+
+#define S_MC_BA_RESERVED            0
+#define M_MC_BA_RESERVED            _SB_MAKEMASK(5, S_MC_BA_RESERVED)
+
+#define S_MC_BA_SELECT              5
+#define M_MC_BA_SELECT              _SB_MAKEMASK(20, S_MC_BA_SELECT)
+#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x, S_MC_BA_SELECT)
+
+#define S_MC_BA_MBZ                 25
+#define M_MC_BA_MBZ                 _SB_MAKEMASK(39, S_MC_BA_MBZ)
+
+/*
+ * Chip Select Attribute Register (Table 6-23)
+ */
+
+#define K_MC_CS_ATTR_CLOSED         0
+#define K_MC_CS_ATTR_CASCHECK       1
+#define K_MC_CS_ATTR_HINT           2
+#define K_MC_CS_ATTR_OPEN           3
+
+#define S_MC_CS0_PAGE               0
+#define M_MC_CS0_PAGE               _SB_MAKEMASK(2, S_MC_CS0_PAGE)
+#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
+#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
+
+#define S_MC_CS1_PAGE               16
+#define M_MC_CS1_PAGE               _SB_MAKEMASK(2, S_MC_CS1_PAGE)
+#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
+#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
+
+#define S_MC_CS2_PAGE               32
+#define M_MC_CS2_PAGE               _SB_MAKEMASK(2, S_MC_CS2_PAGE)
+#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
+#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
+
+#define S_MC_CS3_PAGE               48
+#define M_MC_CS3_PAGE               _SB_MAKEMASK(2, S_MC_CS3_PAGE)
+#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
+#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
+
+/*
+ * ECC Test ECC Register (Table 6-25)
+ */
+
+#define S_MC_ECC_INVERT             0
+#define M_MC_ECC_INVERT             _SB_MAKEMASK(8, S_MC_ECC_INVERT)
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
new file mode 100644
index 000000000..cdac01832
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
@@ -0,0 +1,880 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Register Definitions                     File: sb1250_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the SB1250.
+    *
+    *  SB1250 specification level:  01/02/2002
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_REGS_H
+#define _SB1250_REGS_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the SB1250 SOC
+    *  manual version 0.2, July 2000.
+    ********************************************************************* */
+
+
+/*  *********************************************************************
+    * Memory Controller Registers
+    ********************************************************************* */
+
+/*
+ * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
+ * since there is one reg there (but it could get its addr/offset constant).
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
+#define A_MC_BASE_0                 0x0010051000
+#define A_MC_BASE_1                 0x0010052000
+#define MC_REGISTER_SPACING         0x1000
+
+#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
+#define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
+
+#define R_MC_CONFIG                 0x0000000100
+#define R_MC_DRAMCMD                0x0000000120
+#define R_MC_DRAMMODE               0x0000000140
+#define R_MC_TIMING1                0x0000000160
+#define R_MC_TIMING2                0x0000000180
+#define R_MC_CS_START               0x00000001A0
+#define R_MC_CS_END                 0x00000001C0
+#define R_MC_CS_INTERLEAVE          0x00000001E0
+#define S_MC_CS_STARTEND            16
+
+#define R_MC_CSX_BASE               0x0000000200
+#define R_MC_CSX_ROW                0x0000000000        /* relative to CSX_BASE, above */
+#define R_MC_CSX_COL                0x0000000020        /* relative to CSX_BASE, above */
+#define R_MC_CSX_BA                 0x0000000040        /* relative to CSX_BASE, above */
+#define MC_CSX_SPACING              0x0000000060        /* relative to CSX_BASE, above */
+
+#define R_MC_CS0_ROW                0x0000000200
+#define R_MC_CS0_COL                0x0000000220
+#define R_MC_CS0_BA                 0x0000000240
+#define R_MC_CS1_ROW                0x0000000260
+#define R_MC_CS1_COL                0x0000000280
+#define R_MC_CS1_BA                 0x00000002A0
+#define R_MC_CS2_ROW                0x00000002C0
+#define R_MC_CS2_COL                0x00000002E0
+#define R_MC_CS2_BA                 0x0000000300
+#define R_MC_CS3_ROW                0x0000000320
+#define R_MC_CS3_COL                0x0000000340
+#define R_MC_CS3_BA                 0x0000000360
+#define R_MC_CS_ATTR                0x0000000380
+#define R_MC_TEST_DATA              0x0000000400
+#define R_MC_TEST_ECC               0x0000000420
+#define R_MC_MCLK_CFG               0x0000000500
+
+#endif  /* 1250 & 112x */
+
+/*  *********************************************************************
+    * L2 Cache Control Registers
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
+
+#define A_L2_READ_TAG               0x0010040018
+#define A_L2_ECC_TAG                0x0010040038
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_READ_MISC              0x0010040058
+#endif /* 1250 PASS3 || 112x PASS1 */
+#define A_L2_WAY_DISABLE            0x0010041000
+#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
+#define A_L2_MGMT_TAG_BASE          0x00D0000000
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_CACHE_DISABLE         0x0010042000
+#define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
+#define A_L2_MISC_CONFIG           0x0010043000
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/* Backward-compatibility definitions.  */
+/* XXX: discourage people from using these constants.  */
+#define A_L2_READ_ADDRESS           A_L2_READ_TAG
+#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
+
+#endif
+
+
+/*  *********************************************************************
+    * PCI Interface Registers
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
+#define A_PCI_TYPE00_HEADER         0x00DE000000
+#define A_PCI_TYPE01_HEADER         0x00DE000800
+#endif
+
+
+/*  *********************************************************************
+    * Ethernet DMA and MACs
+    ********************************************************************* */
+
+#define A_MAC_BASE_0                0x0010064000
+#define A_MAC_BASE_1                0x0010065000
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+#define A_MAC_BASE_2                0x0010066000
+#endif /* 1250 */
+
+#define MAC_SPACING                 0x1000
+#define MAC_DMA_TXRX_SPACING        0x0400
+#define MAC_DMA_CHANNEL_SPACING     0x0100
+#define DMA_RX                      0
+#define DMA_TX                      1
+#define MAC_NUM_DMACHAN             2               /* channels per direction */
+
+/* XXX: not correct; depends on SOC type.  */
+#define MAC_NUM_PORTS               3
+
+#define A_MAC_CHANNEL_BASE(macnum)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum))
+
+#define A_MAC_REGISTER(macnum,reg)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum) + (reg))
+
+
+#define R_MAC_DMA_CHANNELS              0x800 /* Relative to A_MAC_CHANNEL_BASE */
+
+#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \
+             ((A_MAC_CHANNEL_BASE(macnum)) +        \
+             R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define R_MAC_DMA_CHANNEL_BASE(txrx, chan)              \
+             (R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)           \
+            (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
+            (reg))
+
+#define R_MAC_DMA_REGISTER(txrx, chan, reg)           \
+            (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
+            (reg))
+
+/*
+ * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
+ */
+
+#define R_MAC_DMA_CONFIG0               0x00000000
+#define R_MAC_DMA_CONFIG1               0x00000008
+#define R_MAC_DMA_DSCR_BASE             0x00000010
+#define R_MAC_DMA_DSCR_CNT              0x00000018
+#define R_MAC_DMA_CUR_DSCRA             0x00000020
+#define R_MAC_DMA_CUR_DSCRB             0x00000028
+#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_MAC_DMA_OODPKTLOST_RX         0x00000038      /* rx only */
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * RMON Counters
+ */
+
+#define R_MAC_RMON_TX_BYTES             0x00000000
+#define R_MAC_RMON_COLLISIONS           0x00000008
+#define R_MAC_RMON_LATE_COL             0x00000010
+#define R_MAC_RMON_EX_COL               0x00000018
+#define R_MAC_RMON_FCS_ERROR            0x00000020
+#define R_MAC_RMON_TX_ABORT             0x00000028
+/* Counter #6 (0x30) now reserved */
+#define R_MAC_RMON_TX_BAD               0x00000038
+#define R_MAC_RMON_TX_GOOD              0x00000040
+#define R_MAC_RMON_TX_RUNT              0x00000048
+#define R_MAC_RMON_TX_OVERSIZE          0x00000050
+#define R_MAC_RMON_RX_BYTES             0x00000080
+#define R_MAC_RMON_RX_MCAST             0x00000088
+#define R_MAC_RMON_RX_BCAST             0x00000090
+#define R_MAC_RMON_RX_BAD               0x00000098
+#define R_MAC_RMON_RX_GOOD              0x000000A0
+#define R_MAC_RMON_RX_RUNT              0x000000A8
+#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
+#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
+#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
+#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
+#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
+
+/* Updated to spec 0.2 */
+#define R_MAC_CFG                       0x00000100
+#define R_MAC_THRSH_CFG                 0x00000108
+#define R_MAC_VLANTAG                   0x00000110
+#define R_MAC_FRAMECFG                  0x00000118
+#define R_MAC_EOPCNT                    0x00000120
+#define R_MAC_FIFO_PTRS                 0x00000128
+#define R_MAC_ADFILTER_CFG              0x00000200
+#define R_MAC_ETHERNET_ADDR             0x00000208
+#define R_MAC_PKT_TYPE                  0x00000210
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_MAC_ADMASK0                   0x00000218
+#define R_MAC_ADMASK1                   0x00000220
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+#define R_MAC_HASH_BASE                 0x00000240
+#define R_MAC_ADDR_BASE                 0x00000280
+#define R_MAC_CHLO0_BASE                0x00000300
+#define R_MAC_CHUP0_BASE                0x00000320
+#define R_MAC_ENABLE                    0x00000400
+#define R_MAC_STATUS                    0x00000408
+#define R_MAC_INT_MASK                  0x00000410
+#define R_MAC_TXD_CTL                   0x00000420
+#define R_MAC_MDIO                      0x00000428
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_MAC_STATUS1                   0x00000430
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define R_MAC_DEBUG_STATUS              0x00000448
+
+#define MAC_HASH_COUNT                  8
+#define MAC_ADDR_COUNT                  8
+#define MAC_CHMAP_COUNT                 4
+
+
+/*  *********************************************************************
+    * DUART Registers
+    ********************************************************************* */
+
+
+#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
+#define R_DUART_NUM_PORTS           2
+
+#define A_DUART                     0x0010060000
+
+#define DUART_CHANREG_SPACING       0x100
+
+#define A_DUART_CHANREG(chan, reg)                                      \
+        (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
+#endif  /* 1250 & 112x */
+
+#define R_DUART_MODE_REG_1          0x000
+#define R_DUART_MODE_REG_2          0x010
+#define R_DUART_STATUS              0x020
+#define R_DUART_CLK_SEL             0x030
+#define R_DUART_CMD                 0x050
+#define R_DUART_RX_HOLD             0x060
+#define R_DUART_TX_HOLD             0x070
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_DUART_FULL_CTL            0x040
+#define R_DUART_OPCR_X              0x080
+#define R_DUART_AUXCTL_X            0x090
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/*
+ * The IMR and ISR can't be addressed with A_DUART_CHANREG,
+ * so use these macros instead.
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
+#define DUART_IMRISR_SPACING        0x20
+#define DUART_INCHNG_SPACING        0x10
+
+#define A_DUART_CTRLREG(reg)                                            \
+        (A_DUART + DUART_CHANREG_SPACING * 3 + (reg))
+
+#define R_DUART_IMRREG(chan)                                            \
+        (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING)
+#define R_DUART_ISRREG(chan)                                            \
+        (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING)
+#define R_DUART_INCHREG(chan)                                           \
+        (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING)
+
+#define A_DUART_IMRREG(chan)        A_DUART_CTRLREG(R_DUART_IMRREG(chan))
+#define A_DUART_ISRREG(chan)        A_DUART_CTRLREG(R_DUART_ISRREG(chan))
+#define A_DUART_INCHREG(chan)       A_DUART_CTRLREG(R_DUART_INCHREG(chan))
+#endif  /* 1250 & 112x */
+
+#define R_DUART_AUX_CTRL            0x010
+#define R_DUART_ISR_A               0x020
+#define R_DUART_IMR_A               0x030
+#define R_DUART_ISR_B               0x040
+#define R_DUART_IMR_B               0x050
+#define R_DUART_OUT_PORT            0x060
+#define R_DUART_OPCR                0x070
+#define R_DUART_IN_PORT             0x080
+
+#define R_DUART_SET_OPR             0x0B0
+#define R_DUART_CLEAR_OPR           0x0C0
+#define R_DUART_IN_CHNG_A           0x0D0
+#define R_DUART_IN_CHNG_B           0x0E0
+
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_DUART_MODE_REG_1_A        0x0010060100
+#define A_DUART_MODE_REG_2_A        0x0010060110
+#define A_DUART_STATUS_A            0x0010060120
+#define A_DUART_CLK_SEL_A           0x0010060130
+#define A_DUART_CMD_A               0x0010060150
+#define A_DUART_RX_HOLD_A           0x0010060160
+#define A_DUART_TX_HOLD_A           0x0010060170
+
+#define A_DUART_MODE_REG_1_B        0x0010060200
+#define A_DUART_MODE_REG_2_B        0x0010060210
+#define A_DUART_STATUS_B            0x0010060220
+#define A_DUART_CLK_SEL_B           0x0010060230
+#define A_DUART_CMD_B               0x0010060250
+#define A_DUART_RX_HOLD_B           0x0010060260
+#define A_DUART_TX_HOLD_B           0x0010060270
+
+#define A_DUART_INPORT_CHNG         0x0010060300
+#define A_DUART_AUX_CTRL            0x0010060310
+#define A_DUART_ISR_A               0x0010060320
+#define A_DUART_IMR_A               0x0010060330
+#define A_DUART_ISR_B               0x0010060340
+#define A_DUART_IMR_B               0x0010060350
+#define A_DUART_OUT_PORT            0x0010060360
+#define A_DUART_OPCR                0x0010060370
+#define A_DUART_IN_PORT             0x0010060380
+#define A_DUART_ISR                 0x0010060390
+#define A_DUART_IMR                 0x00100603A0
+#define A_DUART_SET_OPR             0x00100603B0
+#define A_DUART_CLEAR_OPR           0x00100603C0
+#define A_DUART_INPORT_CHNG_A       0x00100603D0
+#define A_DUART_INPORT_CHNG_B       0x00100603E0
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DUART_FULL_CTL_A          0x0010060140
+#define A_DUART_FULL_CTL_B          0x0010060240
+
+#define A_DUART_OPCR_A              0x0010060180
+#define A_DUART_OPCR_B              0x0010060280
+
+#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*  *********************************************************************
+    * Synchronous Serial Registers
+    ********************************************************************* */
+
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
+
+#define A_SER_BASE_0                0x0010060400
+#define A_SER_BASE_1                0x0010060800
+#define SER_SPACING                 0x400
+
+#define SER_DMA_TXRX_SPACING        0x80
+
+#define SER_NUM_PORTS               2
+
+#define A_SER_CHANNEL_BASE(sernum)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum))
+
+#define A_SER_REGISTER(sernum,reg)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum) + (reg))
+
+
+#define R_SER_DMA_CHANNELS              0   /* Relative to A_SER_BASE_x */
+
+#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
+             ((A_SER_CHANNEL_BASE(sernum)) +        \
+             R_SER_DMA_CHANNELS +                   \
+             (SER_DMA_TXRX_SPACING*(txrx)))
+
+#define A_SER_DMA_REGISTER(sernum, txrx, reg)           \
+            (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
+            (reg))
+
+
+/*
+ * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
+ */
+
+#define R_SER_DMA_CONFIG0           0x00000000
+#define R_SER_DMA_CONFIG1           0x00000008
+#define R_SER_DMA_DSCR_BASE         0x00000010
+#define R_SER_DMA_DSCR_CNT          0x00000018
+#define R_SER_DMA_CUR_DSCRA         0x00000020
+#define R_SER_DMA_CUR_DSCRB         0x00000028
+#define R_SER_DMA_CUR_DSCRADDR      0x00000030
+
+#define R_SER_DMA_CONFIG0_RX        0x00000000
+#define R_SER_DMA_CONFIG1_RX        0x00000008
+#define R_SER_DMA_DSCR_BASE_RX      0x00000010
+#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
+#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
+#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
+#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
+
+#define R_SER_DMA_CONFIG0_TX        0x00000080
+#define R_SER_DMA_CONFIG1_TX        0x00000088
+#define R_SER_DMA_DSCR_BASE_TX      0x00000090
+#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
+#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
+#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
+#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
+
+#define R_SER_MODE                  0x00000100
+#define R_SER_MINFRM_SZ             0x00000108
+#define R_SER_MAXFRM_SZ             0x00000110
+#define R_SER_ADDR                  0x00000118
+#define R_SER_USR0_ADDR             0x00000120
+#define R_SER_USR1_ADDR             0x00000128
+#define R_SER_USR2_ADDR             0x00000130
+#define R_SER_USR3_ADDR             0x00000138
+#define R_SER_CMD                   0x00000140
+#define R_SER_TX_RD_THRSH           0x00000160
+#define R_SER_TX_WR_THRSH           0x00000168
+#define R_SER_RX_RD_THRSH           0x00000170
+#define R_SER_LINE_MODE             0x00000178
+#define R_SER_DMA_ENABLE            0x00000180
+#define R_SER_INT_MASK              0x00000190
+#define R_SER_STATUS                0x00000188
+#define R_SER_STATUS_DEBUG          0x000001A8
+#define R_SER_RX_TABLE_BASE         0x00000200
+#define SER_RX_TABLE_COUNT          16
+#define R_SER_TX_TABLE_BASE         0x00000300
+#define SER_TX_TABLE_COUNT          16
+
+/* RMON Counters */
+#define R_SER_RMON_TX_BYTE_LO       0x000001C0
+#define R_SER_RMON_TX_BYTE_HI       0x000001C8
+#define R_SER_RMON_RX_BYTE_LO       0x000001D0
+#define R_SER_RMON_RX_BYTE_HI       0x000001D8
+#define R_SER_RMON_TX_UNDERRUN      0x000001E0
+#define R_SER_RMON_RX_OVERFLOW      0x000001E8
+#define R_SER_RMON_RX_ERRORS        0x000001F0
+#define R_SER_RMON_RX_BADADDR       0x000001F8
+
+#endif  /* 1250/112x */
+
+/*  *********************************************************************
+    * Generic Bus Registers
+    ********************************************************************* */
+
+#define IO_EXT_CFG_COUNT            8
+
+#define A_IO_EXT_BASE               0x0010061000
+#define A_IO_EXT_REG(r)             (A_IO_EXT_BASE + (r))
+
+#define A_IO_EXT_CFG_BASE           0x0010061000
+#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
+#define A_IO_EXT_START_ADDR_BASE    0x0010061200
+#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
+#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
+
+#define IO_EXT_REGISTER_SPACING     8
+#define A_IO_EXT_CS_BASE(cs)        (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
+#define R_IO_EXT_REG(reg, cs)       ((cs)*IO_EXT_REGISTER_SPACING + (reg))
+
+#define R_IO_EXT_CFG                0x0000
+#define R_IO_EXT_MULT_SIZE          0x0100
+#define R_IO_EXT_START_ADDR         0x0200
+#define R_IO_EXT_TIME_CFG0          0x0600
+#define R_IO_EXT_TIME_CFG1          0x0700
+
+
+#define A_IO_INTERRUPT_STATUS       0x0010061A00
+#define A_IO_INTERRUPT_DATA0        0x0010061A10
+#define A_IO_INTERRUPT_DATA1        0x0010061A18
+#define A_IO_INTERRUPT_DATA2        0x0010061A20
+#define A_IO_INTERRUPT_DATA3        0x0010061A28
+#define A_IO_INTERRUPT_ADDR0        0x0010061A30
+#define A_IO_INTERRUPT_ADDR1        0x0010061A40
+#define A_IO_INTERRUPT_PARITY       0x0010061A50
+#define A_IO_PCMCIA_CFG             0x0010061A60
+#define A_IO_PCMCIA_STATUS          0x0010061A70
+#define A_IO_DRIVE_0                0x0010061300
+#define A_IO_DRIVE_1                0x0010061308
+#define A_IO_DRIVE_2                0x0010061310
+#define A_IO_DRIVE_3                0x0010061318
+#define A_IO_DRIVE_BASE             A_IO_DRIVE_0
+#define IO_DRIVE_REGISTER_SPACING   8
+#define R_IO_DRIVE(x)               ((x)*IO_DRIVE_REGISTER_SPACING)
+#define A_IO_DRIVE(x)               (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
+
+#define R_IO_INTERRUPT_STATUS       0x0A00
+#define R_IO_INTERRUPT_DATA0        0x0A10
+#define R_IO_INTERRUPT_DATA1        0x0A18
+#define R_IO_INTERRUPT_DATA2        0x0A20
+#define R_IO_INTERRUPT_DATA3        0x0A28
+#define R_IO_INTERRUPT_ADDR0        0x0A30
+#define R_IO_INTERRUPT_ADDR1        0x0A40
+#define R_IO_INTERRUPT_PARITY       0x0A50
+#define R_IO_PCMCIA_CFG             0x0A60
+#define R_IO_PCMCIA_STATUS          0x0A70
+
+/*  *********************************************************************
+    * GPIO Registers
+    ********************************************************************* */
+
+#define A_GPIO_CLR_EDGE             0x0010061A80
+#define A_GPIO_INT_TYPE             0x0010061A88
+#define A_GPIO_INPUT_INVERT         0x0010061A90
+#define A_GPIO_GLITCH               0x0010061A98
+#define A_GPIO_READ                 0x0010061AA0
+#define A_GPIO_DIRECTION            0x0010061AA8
+#define A_GPIO_PIN_CLR              0x0010061AB0
+#define A_GPIO_PIN_SET              0x0010061AB8
+
+#define A_GPIO_BASE                 0x0010061A80
+
+#define R_GPIO_CLR_EDGE             0x00
+#define R_GPIO_INT_TYPE             0x08
+#define R_GPIO_INPUT_INVERT         0x10
+#define R_GPIO_GLITCH               0x18
+#define R_GPIO_READ                 0x20
+#define R_GPIO_DIRECTION            0x28
+#define R_GPIO_PIN_CLR              0x30
+#define R_GPIO_PIN_SET              0x38
+
+/*  *********************************************************************
+    * SMBus Registers
+    ********************************************************************* */
+
+#define A_SMB_XTRA_0                0x0010060000
+#define A_SMB_XTRA_1                0x0010060008
+#define A_SMB_FREQ_0                0x0010060010
+#define A_SMB_FREQ_1                0x0010060018
+#define A_SMB_STATUS_0              0x0010060020
+#define A_SMB_STATUS_1              0x0010060028
+#define A_SMB_CMD_0                 0x0010060030
+#define A_SMB_CMD_1                 0x0010060038
+#define A_SMB_START_0               0x0010060040
+#define A_SMB_START_1               0x0010060048
+#define A_SMB_DATA_0                0x0010060050
+#define A_SMB_DATA_1                0x0010060058
+#define A_SMB_CONTROL_0             0x0010060060
+#define A_SMB_CONTROL_1             0x0010060068
+#define A_SMB_PEC_0                 0x0010060070
+#define A_SMB_PEC_1                 0x0010060078
+
+#define A_SMB_0                     0x0010060000
+#define A_SMB_1                     0x0010060008
+#define SMB_REGISTER_SPACING        0x8
+#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
+#define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
+
+#define R_SMB_XTRA                  0x0000000000
+#define R_SMB_FREQ                  0x0000000010
+#define R_SMB_STATUS                0x0000000020
+#define R_SMB_CMD                   0x0000000030
+#define R_SMB_START                 0x0000000040
+#define R_SMB_DATA                  0x0000000050
+#define R_SMB_CONTROL               0x0000000060
+#define R_SMB_PEC                   0x0000000070
+
+/*  *********************************************************************
+    * Timer Registers
+    ********************************************************************* */
+
+/*
+ * Watchdog timers
+ */
+
+#define A_SCD_WDOG_0                0x0010020050
+#define A_SCD_WDOG_1                0x0010020150
+#define SCD_WDOG_SPACING            0x100
+#define SCD_NUM_WDOGS               2
+#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
+#define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
+
+#define R_SCD_WDOG_INIT             0x0000000000
+#define R_SCD_WDOG_CNT              0x0000000008
+#define R_SCD_WDOG_CFG              0x0000000010
+
+#define A_SCD_WDOG_INIT_0           0x0010020050
+#define A_SCD_WDOG_CNT_0            0x0010020058
+#define A_SCD_WDOG_CFG_0            0x0010020060
+
+#define A_SCD_WDOG_INIT_1           0x0010020150
+#define A_SCD_WDOG_CNT_1            0x0010020158
+#define A_SCD_WDOG_CFG_1            0x0010020160
+
+/*
+ * Generic timers
+ */
+
+#define A_SCD_TIMER_0               0x0010020070
+#define A_SCD_TIMER_1               0x0010020078
+#define A_SCD_TIMER_2               0x0010020170
+#define A_SCD_TIMER_3               0x0010020178
+#define SCD_NUM_TIMERS              4
+#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
+#define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
+
+#define R_SCD_TIMER_INIT            0x0000000000
+#define R_SCD_TIMER_CNT             0x0000000010
+#define R_SCD_TIMER_CFG             0x0000000020
+
+#define A_SCD_TIMER_INIT_0          0x0010020070
+#define A_SCD_TIMER_CNT_0           0x0010020080
+#define A_SCD_TIMER_CFG_0           0x0010020090
+
+#define A_SCD_TIMER_INIT_1          0x0010020078
+#define A_SCD_TIMER_CNT_1           0x0010020088
+#define A_SCD_TIMER_CFG_1           0x0010020098
+
+#define A_SCD_TIMER_INIT_2          0x0010020170
+#define A_SCD_TIMER_CNT_2           0x0010020180
+#define A_SCD_TIMER_CFG_2           0x0010020190
+
+#define A_SCD_TIMER_INIT_3          0x0010020178
+#define A_SCD_TIMER_CNT_3           0x0010020188
+#define A_SCD_TIMER_CFG_3           0x0010020198
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_SCRATCH              0x0010020C10
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
+#define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
+#define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
+#endif
+
+/*  *********************************************************************
+    * System Control Registers
+    ********************************************************************* */
+
+#define A_SCD_SYSTEM_REVISION       0x0010020000
+#define A_SCD_SYSTEM_CFG            0x0010020008
+#define A_SCD_SYSTEM_MANUF          0x0010038000
+
+/*  *********************************************************************
+    * System Address Trap Registers
+    ********************************************************************* */
+
+#define A_ADDR_TRAP_INDEX           0x00100200B0
+#define A_ADDR_TRAP_REG             0x00100200B8
+#define A_ADDR_TRAP_UP_0            0x0010020400
+#define A_ADDR_TRAP_UP_1            0x0010020408
+#define A_ADDR_TRAP_UP_2            0x0010020410
+#define A_ADDR_TRAP_UP_3            0x0010020418
+#define A_ADDR_TRAP_DOWN_0          0x0010020420
+#define A_ADDR_TRAP_DOWN_1          0x0010020428
+#define A_ADDR_TRAP_DOWN_2          0x0010020430
+#define A_ADDR_TRAP_DOWN_3          0x0010020438
+#define A_ADDR_TRAP_CFG_0           0x0010020440
+#define A_ADDR_TRAP_CFG_1           0x0010020448
+#define A_ADDR_TRAP_CFG_2           0x0010020450
+#define A_ADDR_TRAP_CFG_3           0x0010020458
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define A_ADDR_TRAP_REG_DEBUG       0x0010020460
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define ADDR_TRAP_SPACING 8
+#define NUM_ADDR_TRAP 4
+#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
+#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
+#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
+
+
+/*  *********************************************************************
+    * System Interrupt Mapper Registers
+    ********************************************************************* */
+
+#define A_IMR_CPU0_BASE                 0x0010020000
+#define A_IMR_CPU1_BASE                 0x0010022000
+#define IMR_REGISTER_SPACING            0x2000
+#define IMR_REGISTER_SPACING_SHIFT      13
+
+#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
+#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
+
+#define R_IMR_INTERRUPT_DIAG            0x0010
+#define R_IMR_INTERRUPT_LDT             0x0018
+#define R_IMR_INTERRUPT_MASK            0x0028
+#define R_IMR_INTERRUPT_TRACE           0x0038
+#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
+#define R_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_IMR_LDT_INTERRUPT             0x0018
+#define R_IMR_LDT_INTERRUPT_CLR         0x0020
+#define R_IMR_MAILBOX_CPU               0x00c0
+#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
+#define R_IMR_MAILBOX_SET_CPU           0x00C8
+#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
+#define R_IMR_MAILBOX_CLR_CPU           0x00D0
+#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
+#define R_IMR_INTERRUPT_STATUS_COUNT    7
+#define R_IMR_INTERRUPT_MAP_BASE        0x0200
+#define R_IMR_INTERRUPT_MAP_COUNT       64
+
+/*
+ * these macros work together to build the address of a mailbox
+ * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
+ * for mbox_0_set_cpu2 returns 0x00100240C8
+ */
+#define A_MAILBOX_REGISTER(reg,cpu) \
+    (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
+
+/*  *********************************************************************
+    * System Performance Counter Registers
+    ********************************************************************* */
+
+#define A_SCD_PERF_CNT_CFG          0x00100204C0
+#define A_SCD_PERF_CNT_0            0x00100204D0
+#define A_SCD_PERF_CNT_1            0x00100204D8
+#define A_SCD_PERF_CNT_2            0x00100204E0
+#define A_SCD_PERF_CNT_3            0x00100204E8
+
+#define SCD_NUM_PERF_CNT 4
+#define SCD_PERF_CNT_SPACING 8
+#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
+
+/*  *********************************************************************
+    * System Bus Watcher Registers
+    ********************************************************************* */
+
+#define A_SCD_BUS_ERR_STATUS        0x0010020880
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define A_BUS_ERR_DATA_0            0x00100208A0
+#define A_BUS_ERR_DATA_1            0x00100208A8
+#define A_BUS_ERR_DATA_2            0x00100208B0
+#define A_BUS_ERR_DATA_3            0x00100208B8
+#define A_BUS_L2_ERRORS             0x00100208C0
+#define A_BUS_MEM_IO_ERRORS         0x00100208C8
+
+/*  *********************************************************************
+    * System Debug Controller Registers
+    ********************************************************************* */
+
+#define A_SCD_JTAG_BASE             0x0010000000
+
+/*  *********************************************************************
+    * System Trace Buffer Registers
+    ********************************************************************* */
+
+#define A_SCD_TRACE_CFG             0x0010020A00
+#define A_SCD_TRACE_READ            0x0010020A08
+#define A_SCD_TRACE_EVENT_0         0x0010020A20
+#define A_SCD_TRACE_EVENT_1         0x0010020A28
+#define A_SCD_TRACE_EVENT_2         0x0010020A30
+#define A_SCD_TRACE_EVENT_3         0x0010020A38
+#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
+#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
+#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
+#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
+#define A_SCD_TRACE_EVENT_4         0x0010020A60
+#define A_SCD_TRACE_EVENT_5         0x0010020A68
+#define A_SCD_TRACE_EVENT_6         0x0010020A70
+#define A_SCD_TRACE_EVENT_7         0x0010020A78
+#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
+#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
+#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
+#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
+
+#define TRACE_REGISTER_SPACING 8
+#define TRACE_NUM_REGISTERS    8
+#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
+   (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
+   (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
+#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
+   (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
+   (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
+
+/*  *********************************************************************
+    * System Generic DMA Registers
+    ********************************************************************* */
+
+#define A_DM_0                      0x0010020B00
+#define A_DM_1                      0x0010020B20
+#define A_DM_2                      0x0010020B40
+#define A_DM_3                      0x0010020B60
+#define DM_REGISTER_SPACING         0x20
+#define DM_NUM_CHANNELS             4
+#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
+#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
+
+#define R_DM_DSCR_BASE              0x0000000000
+#define R_DM_DSCR_COUNT             0x0000000008
+#define R_DM_CUR_DSCR_ADDR          0x0000000010
+#define R_DM_DSCR_BASE_DEBUG        0x0000000018
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_PARTIAL_0              0x0010020ba0
+#define A_DM_PARTIAL_1              0x0010020ba8
+#define A_DM_PARTIAL_2              0x0010020bb0
+#define A_DM_PARTIAL_3              0x0010020bb8
+#define DM_PARTIAL_REGISTER_SPACING 0x8
+#define A_DM_PARTIAL(idx)           (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_CRC_0                  0x0010020b80
+#define A_DM_CRC_1                  0x0010020b90
+#define DM_CRC_REGISTER_SPACING     0x10
+#define DM_CRC_NUM_CHANNELS         2
+#define A_DM_CRC_BASE(idx)          (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
+#define A_DM_CRC_REGISTER(idx, reg)  (A_DM_CRC_BASE(idx) + (reg))
+
+#define R_CRC_DEF_0                 0x00
+#define R_CTCP_DEF_0                0x08
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*  *********************************************************************
+    *  Physical Address Map
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_PHYS_GENBUS_END               _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
+#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
+#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
+#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
+#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
+#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
+#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
+
+#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define PHYS_L2CACHE_NUM_WAYS           4
+#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
+#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
+#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
+#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
+#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+#endif
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
new file mode 100644
index 000000000..d099dcbef
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
@@ -0,0 +1,641 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  SCD Constants and Macros                 File: sb1250_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module on the 1250.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003,2004,2005
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+#ifndef _SB1250_SCD_H
+#define _SB1250_SCD_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Revision Register (Table 4-1)
+ */
+
+#define M_SYS_RESERVED              _SB_MAKEMASK(8, 0)
+
+#define S_SYS_REVISION              _SB_MAKE64(8)
+#define M_SYS_REVISION              _SB_MAKEMASK(8, S_SYS_REVISION)
+#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x, S_SYS_REVISION)
+#define G_SYS_REVISION(x)           _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
+
+#define K_SYS_REVISION_BCM1250_PASS1    0x01
+
+#define K_SYS_REVISION_BCM1250_PASS2    0x03
+#define K_SYS_REVISION_BCM1250_A1       0x03    /* Pass 2.0 WB */
+#define K_SYS_REVISION_BCM1250_A2       0x04    /* Pass 2.0 FC */
+#define K_SYS_REVISION_BCM1250_A3       0x05    /* Pass 2.1 FC */
+#define K_SYS_REVISION_BCM1250_A4       0x06    /* Pass 2.1 WB */
+#define K_SYS_REVISION_BCM1250_A6       0x07    /* OR 0x04 (A2) w/WID != 0 */
+#define K_SYS_REVISION_BCM1250_A8       0x0b    /* A8/A10 */
+#define K_SYS_REVISION_BCM1250_A9       0x08
+#define K_SYS_REVISION_BCM1250_A10      K_SYS_REVISION_BCM1250_A8
+
+#define K_SYS_REVISION_BCM1250_PASS2_2  0x10
+#define K_SYS_REVISION_BCM1250_B0       K_SYS_REVISION_BCM1250_B1
+#define K_SYS_REVISION_BCM1250_B1       0x10
+#define K_SYS_REVISION_BCM1250_B2       0x11
+
+#define K_SYS_REVISION_BCM1250_C0       0x20
+#define K_SYS_REVISION_BCM1250_C1       0x21
+#define K_SYS_REVISION_BCM1250_C2       0x22
+#define K_SYS_REVISION_BCM1250_C3       0x23
+
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
+#define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
+#define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
+#define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
+#define K_SYS_REVISION_BCM1250_PASS3    K_SYS_REVISION_BCM1250_C0
+#endif /* 1250 */
+
+#define K_SYS_REVISION_BCM112x_A1       0x20
+#define K_SYS_REVISION_BCM112x_A2       0x21
+#define K_SYS_REVISION_BCM112x_A3       0x22
+#define K_SYS_REVISION_BCM112x_A4       0x23
+#define K_SYS_REVISION_BCM112x_B0       0x30
+
+#define K_SYS_REVISION_BCM1480_S0       0x01
+#define K_SYS_REVISION_BCM1480_A1       0x02
+#define K_SYS_REVISION_BCM1480_A2       0x03
+#define K_SYS_REVISION_BCM1480_A3       0x04
+#define K_SYS_REVISION_BCM1480_B0       0x11
+
+/*Cache size - 23:20  of revision register*/
+#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
+#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
+#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
+#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
+
+#define K_SYS_L2C_SIZE_1MB      0
+#define K_SYS_L2C_SIZE_512KB    5
+#define K_SYS_L2C_SIZE_256KB    2
+#define K_SYS_L2C_SIZE_128KB    1
+
+#define K_SYS_L2C_SIZE_BCM1250  K_SYS_L2C_SIZE_512KB
+#define K_SYS_L2C_SIZE_BCM1125  K_SYS_L2C_SIZE_256KB
+#define K_SYS_L2C_SIZE_BCM1122  K_SYS_L2C_SIZE_128KB
+
+
+/* Number of CPU cores, bits 27:24  of revision register*/
+#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
+#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
+#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
+#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
+
+
+/* XXX: discourage people from using these constants.  */
+#define S_SYS_PART                  _SB_MAKE64(16)
+#define M_SYS_PART                  _SB_MAKEMASK(16, S_SYS_PART)
+#define V_SYS_PART(x)               _SB_MAKEVALUE(x, S_SYS_PART)
+#define G_SYS_PART(x)               _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
+
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_PART_SB1250           0x1250
+#define K_SYS_PART_BCM1120          0x1121
+#define K_SYS_PART_BCM1125          0x1123
+#define K_SYS_PART_BCM1125H         0x1124
+#define K_SYS_PART_BCM1122          0x1113
+
+
+/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
+#define S_SYS_SOC_TYPE              _SB_MAKE64(16)
+#define M_SYS_SOC_TYPE              _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
+#define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
+#define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
+
+#define K_SYS_SOC_TYPE_BCM1250      0x0
+#define K_SYS_SOC_TYPE_BCM1120      0x1
+#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2         /* 1250pass2 w/ 1/4 L2.  */
+#define K_SYS_SOC_TYPE_BCM1125      0x3
+#define K_SYS_SOC_TYPE_BCM1125H     0x4
+#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
+#define K_SYS_SOC_TYPE_BCM1x80      0x6
+#define K_SYS_SOC_TYPE_BCM1x55      0x7
+
+/*
+ * Calculate correct SOC type given a copy of system revision register.
+ *
+ * (For the assembler version, sysrev and dest may be the same register.
+ * Also, it clobbers AT.)
+ */
+#ifdef __ASSEMBLER__
+#define SYS_SOC_TYPE(dest, sysrev)                                      \
+        .set push ;                                                     \
+        .set reorder ;                                                  \
+        dsrl    dest, sysrev, S_SYS_SOC_TYPE ;                          \
+        andi    dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);         \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;                \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f  ;              \
+        b       992f ;                                                  \
+991:    li      dest, K_SYS_SOC_TYPE_BCM1250 ;                          \
+992:                                                                    \
+        .set pop
+#else
+#define SYS_SOC_TYPE(sysrev)                                            \
+        ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT          \
+          || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)     \
+         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
+#endif
+
+#define S_SYS_WID                   _SB_MAKE64(32)
+#define M_SYS_WID                   _SB_MAKEMASK(32, S_SYS_WID)
+#define V_SYS_WID(x)                _SB_MAKEVALUE(x, S_SYS_WID)
+#define G_SYS_WID(x)                _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
+
+/*
+ * System Manufacturing Register
+ * Register: SCD_SYSTEM_MANUF
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+/* Wafer ID: bits 31:0 */
+#define S_SYS_WAFERID1_200        _SB_MAKE64(0)
+#define M_SYS_WAFERID1_200        _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
+#define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
+#define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
+
+#define S_SYS_BIN                 _SB_MAKE64(32)
+#define M_SYS_BIN                 _SB_MAKEMASK(4, S_SYS_BIN)
+#define V_SYS_BIN(x)              _SB_MAKEVALUE(x, S_SYS_BIN)
+#define G_SYS_BIN(x)              _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
+
+/* Wafer ID: bits 39:36 */
+#define S_SYS_WAFERID2_200        _SB_MAKE64(36)
+#define M_SYS_WAFERID2_200        _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
+#define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
+#define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
+
+/* Wafer ID: bits 39:0 */
+#define S_SYS_WAFERID_300         _SB_MAKE64(0)
+#define M_SYS_WAFERID_300         _SB_MAKEMASK(40, S_SYS_WAFERID_300)
+#define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
+#define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
+
+#define S_SYS_XPOS                _SB_MAKE64(40)
+#define M_SYS_XPOS                _SB_MAKEMASK(6, S_SYS_XPOS)
+#define V_SYS_XPOS(x)             _SB_MAKEVALUE(x, S_SYS_XPOS)
+#define G_SYS_XPOS(x)             _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
+
+#define S_SYS_YPOS                _SB_MAKE64(46)
+#define M_SYS_YPOS                _SB_MAKEMASK(6, S_SYS_YPOS)
+#define V_SYS_YPOS(x)             _SB_MAKEVALUE(x, S_SYS_YPOS)
+#define G_SYS_YPOS(x)             _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
+#endif
+
+
+/*
+ * System Config Register (Table 4-2)
+ * Register: SCD_SYSTEM_CFG
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
+#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
+#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
+#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
+
+#define S_SYS_PLL_DIV               _SB_MAKE64(7)
+#define M_SYS_PLL_DIV               _SB_MAKEMASK(5, S_SYS_PLL_DIV)
+#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
+#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
+
+#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
+#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
+#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
+#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
+#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+
+#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
+#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
+#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
+#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
+#define K_SYS_BOOT_MODE_ROM32       0
+#define K_SYS_BOOT_MODE_ROM8        1
+#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_SYS_BOOT_MODE_SMBUS_BIG   3
+
+#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
+#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
+#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
+#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
+#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
+
+#define S_SYS_CONFIG                26
+#define M_SYS_CONFIG                _SB_MAKEMASK(6, S_SYS_CONFIG)
+#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_SYS_CONFIG)
+#define G_SYS_CONFIG(x)             _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
+
+/* The following bits are writeable by JTAG only. */
+
+#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
+#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
+
+#define S_SYS_CLKCOUNT              34
+#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
+#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
+#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
+
+#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
+
+#define S_SYS_PLL_IREF              43
+#define M_SYS_PLL_IREF              _SB_MAKEMASK(2, S_SYS_PLL_IREF)
+
+#define S_SYS_PLL_VCO               45
+#define M_SYS_PLL_VCO               _SB_MAKEMASK(2, S_SYS_PLL_VCO)
+
+#define S_SYS_PLL_VREG              47
+#define M_SYS_PLL_VREG              _SB_MAKEMASK(2, S_SYS_PLL_VREG)
+
+#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
+#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
+#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
+#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
+#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
+
+/* End of bits writable by JTAG only. */
+
+#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
+#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
+
+#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
+#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
+
+#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
+#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
+#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
+
+#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
+#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
+
+
+/*
+ * Mailbox Registers (Table 4-3)
+ * Registers: SCD_MBOX_CPU_x
+ */
+
+#define S_MBOX_INT_3                0
+#define M_MBOX_INT_3                _SB_MAKEMASK(16, S_MBOX_INT_3)
+#define S_MBOX_INT_2                16
+#define M_MBOX_INT_2                _SB_MAKEMASK(16, S_MBOX_INT_2)
+#define S_MBOX_INT_1                32
+#define M_MBOX_INT_1                _SB_MAKEMASK(16, S_MBOX_INT_1)
+#define S_MBOX_INT_0                48
+#define M_MBOX_INT_0                _SB_MAKEMASK(16, S_MBOX_INT_0)
+
+/*
+ * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ */
+
+#define V_SCD_WDOG_FREQ             1000000
+
+#define S_SCD_WDOG_INIT             0
+#define M_SCD_WDOG_INIT             _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
+
+#define S_SCD_WDOG_CNT              0
+#define M_SCD_WDOG_CNT              _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
+
+#define S_SCD_WDOG_ENABLE           0
+#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
+
+#define S_SCD_WDOG_RESET_TYPE       2
+#define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
+#define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
+#define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
+
+#define K_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_SCD_WDOG_RESET_SOFT       1
+#define K_SCD_WDOG_RESET_CPU0       3
+#define K_SCD_WDOG_RESET_CPU1       5
+#define K_SCD_WDOG_RESET_BOTH_CPUS  7
+
+/* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define S_SCD_WDOG_HAS_RESET        8
+#define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
+#endif
+
+
+/*
+ * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
+ */
+
+#define V_SCD_TIMER_FREQ            1000000
+
+#define S_SCD_TIMER_INIT            0
+#define M_SCD_TIMER_INIT            _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
+#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
+#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
+
+#define V_SCD_TIMER_WIDTH           23
+#define S_SCD_TIMER_CNT             0
+#define M_SCD_TIMER_CNT             _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
+#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
+#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
+
+#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
+#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
+#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
+
+/*
+ * System Performance Counters
+ */
+
+#define S_SPC_CFG_SRC0            0
+#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
+#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
+#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
+
+#define S_SPC_CFG_SRC1            8
+#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
+#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
+#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
+
+#define S_SPC_CFG_SRC2            16
+#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
+#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
+#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
+
+#define S_SPC_CFG_SRC3            24
+#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
+#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
+#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
+#define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
+#endif
+
+
+/*
+ * Bus Watcher
+ */
+
+#define S_SCD_BERR_TID            8
+#define M_SCD_BERR_TID            _SB_MAKEMASK(10, S_SCD_BERR_TID)
+#define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_TID)
+#define G_SCD_BERR_TID(x)         _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
+
+#define S_SCD_BERR_RID            18
+#define M_SCD_BERR_RID            _SB_MAKEMASK(4, S_SCD_BERR_RID)
+#define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_RID)
+#define G_SCD_BERR_RID(x)         _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
+
+#define S_SCD_BERR_DCODE          22
+#define M_SCD_BERR_DCODE          _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
+#define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
+#define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
+
+#define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
+
+
+#define S_SCD_L2ECC_CORR_D        0
+#define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
+#define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
+#define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
+
+#define S_SCD_L2ECC_BAD_D         8
+#define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
+#define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
+#define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
+
+#define S_SCD_L2ECC_CORR_T        16
+#define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
+#define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
+#define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
+
+#define S_SCD_L2ECC_BAD_T         24
+#define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
+#define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
+#define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
+
+#define S_SCD_MEM_ECC_CORR        0
+#define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
+#define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
+#define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
+
+#define S_SCD_MEM_ECC_BAD         8
+#define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
+#define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
+#define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
+
+#define S_SCD_MEM_BUSERR          16
+#define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
+#define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
+#define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
+
+
+/*
+ * Address Trap Registers
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
+#define M_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
+
+#define S_ATRAP_CFG_CNT            0
+#define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
+#define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
+#define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
+
+#define M_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_ATRAP_CFG_AGENTID     8
+#define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
+#define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
+#define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
+
+#define K_BUS_AGENT_CPU0        0
+#define K_BUS_AGENT_CPU1        1
+#define K_BUS_AGENT_IOB0        2
+#define K_BUS_AGENT_IOB1        3
+#define K_BUS_AGENT_SCD 4
+#define K_BUS_AGENT_L2C 6
+#define K_BUS_AGENT_MC  7
+
+#define S_ATRAP_CFG_CATTR     12
+#define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
+#define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
+#define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
+
+#define K_ATRAP_CFG_CATTR_IGNORE        0
+#define K_ATRAP_CFG_CATTR_UNC           1
+#define K_ATRAP_CFG_CATTR_CACHEABLE     2
+#define K_ATRAP_CFG_CATTR_NONCOH        3
+#define K_ATRAP_CFG_CATTR_COHERENT      4
+#define K_ATRAP_CFG_CATTR_NOTUNC        5
+#define K_ATRAP_CFG_CATTR_NOTNONCOH     6
+#define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
+
+#endif  /* 1250/112x */
+
+/*
+ * Trace Buffer Config register
+ */
+
+#define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
+#define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
+#define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
+#define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
+#define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
+#define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
+#define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
+#define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+/*
+ * This field is the same on the 1250/112x and 1480, just located in
+ * a slightly different place in the register.
+ */
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define S_SCD_TRACE_CFG_CUR_ADDR        10
+#else
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SCD_TRACE_CFG_CUR_ADDR        24
+#endif  /* 1480 */
+#endif  /* 1250/112x */
+
+#define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
+#define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
+#define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
+
+/*
+ * Trace Event registers
+ */
+
+#define S_SCD_TREVT_ADDR_MATCH          0
+#define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
+#define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
+#define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
+
+#define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
+#define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
+#define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
+#define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
+#define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
+#define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
+#define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
+
+#define S_SCD_TREVT_REQID               12
+#define M_SCD_TREVT_REQID               _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
+#define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
+#define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
+
+#define S_SCD_TREVT_RESPID              16
+#define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
+#define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
+#define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
+
+#define S_SCD_TREVT_DATAID              20
+#define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
+#define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
+#define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
+
+#define S_SCD_TREVT_COUNT               24
+#define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
+#define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
+#define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
+
+/*
+ * Trace Sequence registers
+ */
+
+#define S_SCD_TRSEQ_EVENT4              0
+#define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
+#define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
+#define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
+
+#define S_SCD_TRSEQ_EVENT3              4
+#define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
+#define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
+#define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
+
+#define S_SCD_TRSEQ_EVENT2              8
+#define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
+#define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
+#define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
+
+#define S_SCD_TRSEQ_EVENT1              12
+#define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
+#define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
+#define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
+
+#define K_SCD_TRSEQ_E0                  0
+#define K_SCD_TRSEQ_E1                  1
+#define K_SCD_TRSEQ_E2                  2
+#define K_SCD_TRSEQ_E3                  3
+#define K_SCD_TRSEQ_E0_E1               4
+#define K_SCD_TRSEQ_E1_E2               5
+#define K_SCD_TRSEQ_E2_E3               6
+#define K_SCD_TRSEQ_E0_E1_E2            7
+#define K_SCD_TRSEQ_E0_E1_E2_E3         8
+#define K_SCD_TRSEQ_E0E1                9
+#define K_SCD_TRSEQ_E0E1E2              10
+#define K_SCD_TRSEQ_E0E1E2E3            11
+#define K_SCD_TRSEQ_E0E1_E2             12
+#define K_SCD_TRSEQ_E0E1_E2E3           13
+#define K_SCD_TRSEQ_E0E1_E2_E3          14
+#define K_SCD_TRSEQ_IGNORED             15
+
+#define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
+
+#define S_SCD_TRSEQ_FUNCTION            16
+#define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
+#define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
+#define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
+
+#define K_SCD_TRSEQ_FUNC_NOP            0
+#define K_SCD_TRSEQ_FUNC_START          1
+#define K_SCD_TRSEQ_FUNC_STOP           2
+#define K_SCD_TRSEQ_FUNC_FREEZE         3
+
+#define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
+#define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
+#define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
+#define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
+
+#define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
+#define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
+#define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
+#define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
+#define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
+#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
+#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
new file mode 100644
index 000000000..e854f96ff
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  SMBUS Constants                          File: sb1250_smbus.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's SMbus devices.
+    *
+    *  SB1250 specification level:  10/21/02
+    *  BCM1280 specification level:  11/24/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SMBUS_H
+#define _SB1250_SMBUS_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * SMBus Clock Frequency Register (Table 14-2)
+ */
+
+#define S_SMB_FREQ_DIV              0
+#define M_SMB_FREQ_DIV              _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
+#define V_SMB_FREQ_DIV(x)           _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
+
+#define K_SMB_FREQ_400KHZ           0x1F
+#define K_SMB_FREQ_100KHZ           0x7D
+#define K_SMB_FREQ_10KHZ            1250
+
+#define S_SMB_CMD                   0
+#define M_SMB_CMD                   _SB_MAKEMASK(8, S_SMB_CMD)
+#define V_SMB_CMD(x)                _SB_MAKEVALUE(x, S_SMB_CMD)
+
+/*
+ * SMBus control register (Table 14-4)
+ */
+
+#define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
+#define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
+
+#define S_SMB_DATA_OUT              4
+#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
+#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
+
+#define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
+#define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
+#define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
+#define M_SMB_DIRECT_ENABLE         _SB_MAKEMASK1(7)
+
+/*
+ * SMBus status registers (Table 14-5)
+ */
+
+#define M_SMB_BUSY                  _SB_MAKEMASK1(0)
+#define M_SMB_ERROR                 _SB_MAKEMASK1(1)
+#define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SMB_SCL_IN                5
+#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
+#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x, S_SMB_SCL_IN)
+#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_SMB_REF                   6
+#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
+#define V_SMB_REF(x)                _SB_MAKEVALUE(x, S_SMB_REF)
+#define G_SMB_REF(x)                _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
+
+#define S_SMB_DATA_IN               7
+#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
+#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x, S_SMB_DATA_IN)
+#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
+
+/*
+ * SMBus Start/Command registers (Table 14-9)
+ */
+
+#define S_SMB_ADDR                  0
+#define M_SMB_ADDR                  _SB_MAKEMASK(7, S_SMB_ADDR)
+#define V_SMB_ADDR(x)               _SB_MAKEVALUE(x, S_SMB_ADDR)
+#define G_SMB_ADDR(x)               _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
+
+#define M_SMB_QDATA                 _SB_MAKEMASK1(7)
+
+#define S_SMB_TT                    8
+#define M_SMB_TT                    _SB_MAKEMASK(3, S_SMB_TT)
+#define V_SMB_TT(x)                 _SB_MAKEVALUE(x, S_SMB_TT)
+#define G_SMB_TT(x)                 _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
+
+#define K_SMB_TT_WR1BYTE            0
+#define K_SMB_TT_WR2BYTE            1
+#define K_SMB_TT_WR3BYTE            2
+#define K_SMB_TT_CMD_RD1BYTE        3
+#define K_SMB_TT_CMD_RD2BYTE        4
+#define K_SMB_TT_RD1BYTE            5
+#define K_SMB_TT_QUICKCMD           6
+#define K_SMB_TT_EEPROMREAD         7
+
+#define V_SMB_TT_WR1BYTE            V_SMB_TT(K_SMB_TT_WR1BYTE)
+#define V_SMB_TT_WR2BYTE            V_SMB_TT(K_SMB_TT_WR2BYTE)
+#define V_SMB_TT_WR3BYTE            V_SMB_TT(K_SMB_TT_WR3BYTE)
+#define V_SMB_TT_CMD_RD1BYTE        V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
+#define V_SMB_TT_CMD_RD2BYTE        V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
+#define V_SMB_TT_RD1BYTE            V_SMB_TT(K_SMB_TT_RD1BYTE)
+#define V_SMB_TT_QUICKCMD           V_SMB_TT(K_SMB_TT_QUICKCMD)
+#define V_SMB_TT_EEPROMREAD         V_SMB_TT(K_SMB_TT_EEPROMREAD)
+
+#define M_SMB_PEC                   _SB_MAKEMASK1(15)
+
+/*
+ * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
+ */
+
+#define S_SMB_LB                    0
+#define M_SMB_LB                    _SB_MAKEMASK(8, S_SMB_LB)
+#define V_SMB_LB(x)                 _SB_MAKEVALUE(x, S_SMB_LB)
+
+#define S_SMB_MB                    8
+#define M_SMB_MB                    _SB_MAKEMASK(8, S_SMB_MB)
+#define V_SMB_MB(x)                 _SB_MAKEVALUE(x, S_SMB_MB)
+
+
+/*
+ * SMBus Packet Error Check register (Table 14-8)
+ */
+
+#define S_SPEC_PEC                  0
+#define M_SPEC_PEC                  _SB_MAKEMASK(8, S_SPEC_PEC)
+#define V_SPEC_MB(x)                _SB_MAKEVALUE(x, S_SPEC_PEC)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+
+#define S_SMB_CMDH                  8
+#define M_SMB_CMDH                  _SB_MAKEMASK(8, S_SMB_CMDH)
+#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x, S_SMB_CMDH)
+
+#define M_SMB_EXTEND                _SB_MAKEMASK1(14)
+
+#define S_SMB_DFMT                  8
+#define M_SMB_DFMT                  _SB_MAKEMASK(3, S_SMB_DFMT)
+#define V_SMB_DFMT(x)               _SB_MAKEVALUE(x, S_SMB_DFMT)
+#define G_SMB_DFMT(x)               _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
+
+#define K_SMB_DFMT_1BYTE            0
+#define K_SMB_DFMT_2BYTE            1
+#define K_SMB_DFMT_3BYTE            2
+#define K_SMB_DFMT_4BYTE            3
+#define K_SMB_DFMT_NODATA           4
+#define K_SMB_DFMT_CMD4BYTE         5
+#define K_SMB_DFMT_CMD5BYTE         6
+#define K_SMB_DFMT_RESERVED         7
+
+#define V_SMB_DFMT_1BYTE            V_SMB_DFMT(K_SMB_DFMT_1BYTE)
+#define V_SMB_DFMT_2BYTE            V_SMB_DFMT(K_SMB_DFMT_2BYTE)
+#define V_SMB_DFMT_3BYTE            V_SMB_DFMT(K_SMB_DFMT_3BYTE)
+#define V_SMB_DFMT_4BYTE            V_SMB_DFMT(K_SMB_DFMT_4BYTE)
+#define V_SMB_DFMT_NODATA           V_SMB_DFMT(K_SMB_DFMT_NODATA)
+#define V_SMB_DFMT_CMD4BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
+#define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
+#define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
+
+#define S_SMB_AFMT                  11
+#define M_SMB_AFMT                  _SB_MAKEMASK(2, S_SMB_AFMT)
+#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x, S_SMB_AFMT)
+#define G_SMB_AFMT(x)               _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
+
+#define K_SMB_AFMT_NONE             0
+#define K_SMB_AFMT_ADDR             1
+#define K_SMB_AFMT_ADDR_CMD1BYTE    2
+#define K_SMB_AFMT_ADDR_CMD2BYTE    3
+
+#define V_SMB_AFMT_NONE             V_SMB_AFMT(K_SMB_AFMT_NONE)
+#define V_SMB_AFMT_ADDR             V_SMB_AFMT(K_SMB_AFMT_ADDR)
+#define V_SMB_AFMT_ADDR_CMD1BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
+#define V_SMB_AFMT_ADDR_CMD2BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
+
+#define M_SMB_DIR                   _SB_MAKEMASK1(13)
+
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
new file mode 100644
index 000000000..8b40e3f05
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Synchronous Serial Constants              File: sb1250_syncser.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's Synchronous Serial
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SYNCSER_H
+#define _SB1250_SYNCSER_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/*
+ * Serial Mode Configuration Register
+ */
+
+#define M_SYNCSER_CRC_MODE                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_MSB_FIRST                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_FLAG_NUM                 2
+#define M_SYNCSER_FLAG_NUM                 _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
+#define V_SYNCSER_FLAG_NUM                 _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
+
+#define M_SYNCSER_FLAG_EN                  _SB_MAKEMASK1(6)
+#define M_SYNCSER_HDLC_EN                  _SB_MAKEMASK1(7)
+#define M_SYNCSER_LOOP_MODE                _SB_MAKEMASK1(8)
+#define M_SYNCSER_LOOPBACK                 _SB_MAKEMASK1(9)
+
+/*
+ * Serial Clock Source and Line Interface Mode Register
+ */
+
+#define M_SYNCSER_RXCLK_INV                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RXCLK_EXT                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_RXSYNC_DLY               2
+#define M_SYNCSER_RXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
+#define V_SYNCSER_RXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
+
+#define M_SYNCSER_RXSYNC_LOW               _SB_MAKEMASK1(4)
+#define M_SYNCSER_RXSTRB_LOW               _SB_MAKEMASK1(5)
+
+#define M_SYNCSER_RXSYNC_EDGE              _SB_MAKEMASK1(6)
+#define M_SYNCSER_RXSYNC_INT               _SB_MAKEMASK1(7)
+
+#define M_SYNCSER_TXCLK_INV                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TXCLK_EXT                _SB_MAKEMASK1(9)
+
+#define S_SYNCSER_TXSYNC_DLY               10
+#define M_SYNCSER_TXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
+#define V_SYNCSER_TXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
+
+#define M_SYNCSER_TXSYNC_LOW               _SB_MAKEMASK1(12)
+#define M_SYNCSER_TXSTRB_LOW               _SB_MAKEMASK1(13)
+
+#define M_SYNCSER_TXSYNC_EDGE              _SB_MAKEMASK1(14)
+#define M_SYNCSER_TXSYNC_INT               _SB_MAKEMASK1(15)
+
+/*
+ * Serial Command Register
+ */
+
+#define M_SYNCSER_CMD_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_CMD_TX_EN                _SB_MAKEMASK1(1)
+#define M_SYNCSER_CMD_RX_RESET             _SB_MAKEMASK1(2)
+#define M_SYNCSER_CMD_TX_RESET             _SB_MAKEMASK1(3)
+#define M_SYNCSER_CMD_TX_PAUSE             _SB_MAKEMASK1(5)
+
+/*
+ * Serial DMA Enable Register
+ */
+
+#define M_SYNCSER_DMA_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_DMA_TX_EN                _SB_MAKEMASK1(4)
+
+/*
+ * Serial Status Register
+ */
+
+#define M_SYNCSER_RX_CRCERR                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RX_ABORT                 _SB_MAKEMASK1(1)
+#define M_SYNCSER_RX_OCTET                 _SB_MAKEMASK1(2)
+#define M_SYNCSER_RX_LONGFRM               _SB_MAKEMASK1(3)
+#define M_SYNCSER_RX_SHORTFRM              _SB_MAKEMASK1(4)
+#define M_SYNCSER_RX_OVERRUN               _SB_MAKEMASK1(5)
+#define M_SYNCSER_RX_SYNC_ERR              _SB_MAKEMASK1(6)
+#define M_SYNCSER_TX_CRCERR                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TX_UNDERRUN              _SB_MAKEMASK1(9)
+#define M_SYNCSER_TX_SYNC_ERR              _SB_MAKEMASK1(10)
+#define M_SYNCSER_TX_PAUSE_COMPLETE        _SB_MAKEMASK1(11)
+#define M_SYNCSER_RX_EOP_COUNT             _SB_MAKEMASK1(16)
+#define M_SYNCSER_RX_EOP_TIMER             _SB_MAKEMASK1(17)
+#define M_SYNCSER_RX_EOP_SEEN              _SB_MAKEMASK1(18)
+#define M_SYNCSER_RX_HWM                   _SB_MAKEMASK1(19)
+#define M_SYNCSER_RX_LWM                   _SB_MAKEMASK1(20)
+#define M_SYNCSER_RX_DSCR                  _SB_MAKEMASK1(21)
+#define M_SYNCSER_RX_DERR                  _SB_MAKEMASK1(22)
+#define M_SYNCSER_TX_EOP_COUNT             _SB_MAKEMASK1(24)
+#define M_SYNCSER_TX_EOP_TIMER             _SB_MAKEMASK1(25)
+#define M_SYNCSER_TX_EOP_SEEN              _SB_MAKEMASK1(26)
+#define M_SYNCSER_TX_HWM                   _SB_MAKEMASK1(27)
+#define M_SYNCSER_TX_LWM                   _SB_MAKEMASK1(28)
+#define M_SYNCSER_TX_DSCR                  _SB_MAKEMASK1(29)
+#define M_SYNCSER_TX_DERR                  _SB_MAKEMASK1(30)
+#define M_SYNCSER_TX_DZERO                 _SB_MAKEMASK1(31)
+
+/*
+ * Sequencer Table Entry format
+ */
+
+#define M_SYNCSER_SEQ_LAST                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_SEQ_BYTE                 _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_SEQ_COUNT                2
+#define M_SYNCSER_SEQ_COUNT                _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
+#define V_SYNCSER_SEQ_COUNT(x)             _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
+
+#define M_SYNCSER_SEQ_ENABLE               _SB_MAKEMASK1(6)
+#define M_SYNCSER_SEQ_STROBE               _SB_MAKEMASK1(7)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
new file mode 100644
index 000000000..da782e643
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  UART Constants                           File: sb1250_uart.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's UARTs
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    ********************************************************************* */
+
+
+#ifndef _SB1250_UART_H
+#define _SB1250_UART_H
+
+#include <asm/sibyte/sb1250_defs.h>
+
+/* **********************************************************************
+   * DUART Registers
+   ********************************************************************** */
+
+/*
+ * DUART Mode Register #1 (Table 10-3)
+ * Register: DUART_MODE_REG_1_A
+ * Register: DUART_MODE_REG_1_B
+ */
+
+#define S_DUART_BITS_PER_CHAR       0
+#define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
+#define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
+
+#define K_DUART_BITS_PER_CHAR_RSV0  0
+#define K_DUART_BITS_PER_CHAR_RSV1  1
+#define K_DUART_BITS_PER_CHAR_7     2
+#define K_DUART_BITS_PER_CHAR_8     3
+
+#define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
+#define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
+#define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
+#define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
+
+
+#define M_DUART_PARITY_TYPE_EVEN    0x00
+#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
+
+#define S_DUART_PARITY_MODE          3
+#define M_DUART_PARITY_MODE         _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
+#define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
+
+#define K_DUART_PARITY_MODE_ADD       0
+#define K_DUART_PARITY_MODE_ADD_FIXED 1
+#define K_DUART_PARITY_MODE_NONE      2
+
+#define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
+#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
+#define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
+
+#define M_DUART_TX_IRQ_SEL_TXRDY    0
+#define M_DUART_TX_IRQ_SEL_TXEMPT   _SB_MAKEMASK1(5)
+
+#define M_DUART_RX_IRQ_SEL_RXRDY    0
+#define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
+
+#define M_DUART_RX_RTS_ENA          _SB_MAKEMASK1(7)
+
+/*
+ * DUART Mode Register #2 (Table 10-4)
+ * Register: DUART_MODE_REG_2_A
+ * Register: DUART_MODE_REG_2_B
+ */
+
+#define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3, 0)   /* ignored */
+
+#define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
+#define M_DUART_STOP_BIT_LEN_1      0
+
+#define M_DUART_TX_CTS_ENA          _SB_MAKEMASK1(4)
+
+
+#define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
+
+#define S_DUART_CHAN_MODE           6
+#define M_DUART_CHAN_MODE           _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
+#define V_DUART_CHAN_MODE(x)        _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
+
+#define K_DUART_CHAN_MODE_NORMAL    0
+#define K_DUART_CHAN_MODE_LCL_LOOP  2
+#define K_DUART_CHAN_MODE_REM_LOOP  3
+
+#define V_DUART_CHAN_MODE_NORMAL    V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
+#define V_DUART_CHAN_MODE_LCL_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
+#define V_DUART_CHAN_MODE_REM_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
+
+/*
+ * DUART Command Register (Table 10-5)
+ * Register: DUART_CMD_A
+ * Register: DUART_CMD_B
+ */
+
+#define M_DUART_RX_EN               _SB_MAKEMASK1(0)
+#define M_DUART_RX_DIS              _SB_MAKEMASK1(1)
+#define M_DUART_TX_EN               _SB_MAKEMASK1(2)
+#define M_DUART_TX_DIS              _SB_MAKEMASK1(3)
+
+#define S_DUART_MISC_CMD            4
+#define M_DUART_MISC_CMD            _SB_MAKEMASK(3, S_DUART_MISC_CMD)
+#define V_DUART_MISC_CMD(x)         _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
+
+#define K_DUART_MISC_CMD_NOACTION0       0
+#define K_DUART_MISC_CMD_NOACTION1       1
+#define K_DUART_MISC_CMD_RESET_RX        2
+#define K_DUART_MISC_CMD_RESET_TX        3
+#define K_DUART_MISC_CMD_NOACTION4       4
+#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
+#define K_DUART_MISC_CMD_START_BREAK     6
+#define K_DUART_MISC_CMD_STOP_BREAK      7
+
+#define V_DUART_MISC_CMD_NOACTION0       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
+#define V_DUART_MISC_CMD_NOACTION1       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
+#define V_DUART_MISC_CMD_RESET_RX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
+#define V_DUART_MISC_CMD_RESET_TX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
+#define V_DUART_MISC_CMD_NOACTION4       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
+#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
+#define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
+#define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
+
+#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
+
+/*
+ * DUART Status Register (Table 10-6)
+ * Register: DUART_STATUS_A
+ * Register: DUART_STATUS_B
+ * READ-ONLY
+ */
+
+#define M_DUART_RX_RDY              _SB_MAKEMASK1(0)
+#define M_DUART_RX_FFUL             _SB_MAKEMASK1(1)
+#define M_DUART_TX_RDY              _SB_MAKEMASK1(2)
+#define M_DUART_TX_EMT              _SB_MAKEMASK1(3)
+#define M_DUART_OVRUN_ERR           _SB_MAKEMASK1(4)
+#define M_DUART_PARITY_ERR          _SB_MAKEMASK1(5)
+#define M_DUART_FRM_ERR             _SB_MAKEMASK1(6)
+#define M_DUART_RCVD_BRK            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Baud Rate Register (Table 10-7)
+ * Register: DUART_CLK_SEL_A
+ * Register: DUART_CLK_SEL_B
+ */
+
+#define M_DUART_CLK_COUNTER         _SB_MAKEMASK(12, 0)
+#define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
+
+/*
+ * DUART Data Registers (Table 10-8 and 10-9)
+ * Register: DUART_RX_HOLD_A
+ * Register: DUART_RX_HOLD_B
+ * Register: DUART_TX_HOLD_A
+ * Register: DUART_TX_HOLD_B
+ */
+
+#define M_DUART_RX_DATA             _SB_MAKEMASK(8, 0)
+#define M_DUART_TX_DATA             _SB_MAKEMASK(8, 0)
+
+/*
+ * DUART Input Port Register (Table 10-10)
+ * Register: DUART_IN_PORT
+ */
+
+#define M_DUART_IN_PIN0_VAL         _SB_MAKEMASK1(0)
+#define M_DUART_IN_PIN1_VAL         _SB_MAKEMASK1(1)
+#define M_DUART_IN_PIN2_VAL         _SB_MAKEMASK1(2)
+#define M_DUART_IN_PIN3_VAL         _SB_MAKEMASK1(3)
+#define M_DUART_IN_PIN4_VAL         _SB_MAKEMASK1(4)
+#define M_DUART_IN_PIN5_VAL         _SB_MAKEMASK1(5)
+#define M_DUART_RIN0_PIN            _SB_MAKEMASK1(6)
+#define M_DUART_RIN1_PIN            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
+ * Register: DUART_INPORT_CHNG
+ */
+
+#define S_DUART_IN_PIN_VAL          0
+#define M_DUART_IN_PIN_VAL          _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
+
+#define S_DUART_IN_PIN_CHNG         4
+#define M_DUART_IN_PIN_CHNG         _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
+
+
+/*
+ * DUART Output port control register (Table 10-14)
+ * Register: DUART_OPCR
+ */
+
+#define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
+#define M_DUART_OPC2_SEL            _SB_MAKEMASK1(1)
+#define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
+#define M_DUART_OPC3_SEL            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4, 4)  /* must be zero */
+
+/*
+ * DUART Aux Control Register (Table 10-15)
+ * Register: DUART_AUX_CTRL
+ */
+
+#define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
+#define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
+#define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
+#define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4, 4)
+
+#define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
+
+/*
+ * DUART Interrupt Status Register (Table 10-16)
+ * Register: DUART_ISR
+ */
+
+#define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
+
+#define S_DUART_ISR_RX_A            1
+#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
+#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
+#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
+
+#define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_ISR_ALL_A           _SB_MAKEMASK(4, 0)
+
+#define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_ISR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_ISR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_ISR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_ISR_ALL_B           _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Channel A Interrupt Status Register (Table 10-17)
+ * DUART Channel B Interrupt Status Register (Table 10-18)
+ * Register: DUART_ISR_A
+ * Register: DUART_ISR_B
+ */
+
+#define M_DUART_ISR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_ISR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_ISR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_ISR_ALL             _SB_MAKEMASK(4, 0)
+#define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Interrupt Mask Register (Table 10-19)
+ * Register: DUART_IMR
+ */
+
+#define M_DUART_IMR_TX_A            _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX_A            _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL_A           _SB_MAKEMASK(4, 0)
+
+#define M_DUART_IMR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_IMR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_IMR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_IMR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_IMR_ALL_B           _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Channel A Interrupt Mask Register (Table 10-20)
+ * DUART Channel B Interrupt Mask Register (Table 10-21)
+ * Register: DUART_IMR_A
+ * Register: DUART_IMR_B
+ */
+
+#define M_DUART_IMR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL             _SB_MAKEMASK(4, 0)
+#define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4, 4)
+
+
+/*
+ * DUART Output Port Set Register (Table 10-22)
+ * Register: DUART_SET_OPR
+ */
+
+#define M_DUART_SET_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_SET_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_SET_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_SET_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Output Port Clear Register (Table 10-23)
+ * Register: DUART_CLEAR_OPR
+ */
+
+#define M_DUART_CLR_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_CLR_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_CLR_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_CLR_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Output Port RTS Register (Table 10-24)
+ * Register: DUART_OUT_PORT
+ */
+
+#define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
+#define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
+#define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
+#define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
+#define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4, 4)
+
+#define M_DUART_OUT_PIN_SET(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
+#define M_DUART_OUT_PIN_CLR(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Full Interrupt Control Register
+ */
+
+#define S_DUART_SIG_FULL           _SB_MAKE64(0)
+#define M_DUART_SIG_FULL           _SB_MAKEMASK(4, S_DUART_SIG_FULL)
+#define V_DUART_SIG_FULL(x)        _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
+#define G_DUART_SIG_FULL(x)        _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
+
+#define S_DUART_INT_TIME           _SB_MAKE64(4)
+#define M_DUART_INT_TIME           _SB_MAKEMASK(4, S_DUART_INT_TIME)
+#define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x, S_DUART_INT_TIME)
+#define G_DUART_INT_TIME(x)        _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/* ********************************************************************** */
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h
new file mode 100644
index 000000000..a27cda344
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sentosa.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SIBYTE_SENTOSA_H
+#define __ASM_SIBYTE_SENTOSA_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SENTOSA
+#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
+#endif
+#ifdef CONFIG_SIBYTE_RHONE
+#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
+#endif
+
+/* Generic bus chip selects */
+#ifdef CONFIG_SIBYTE_RHONE
+#define LEDS_CS         6
+#define LEDS_PHYS       0x1d0a0000
+#endif
+
+/* GPIOs */
+#define K_GPIO_DBG_LED  0
+
+#endif /* __ASM_SIBYTE_SENTOSA_H */
diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h
new file mode 100644
index 000000000..947122f48
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/swarm.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ */
+#ifndef __ASM_SIBYTE_SWARM_H
+#define __ASM_SIBYTE_SWARM_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SWARM
+#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+#ifdef CONFIG_SIBYTE_LITTLESUR
+#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_DEFAULT_CONSOLE "cfe0"
+#endif
+#ifdef CONFIG_SIBYTE_CRHONE
+#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+#ifdef CONFIG_SIBYTE_CRHINE
+#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_SWARM_H */
diff --git a/arch/mips/include/asm/sigcontext.h b/arch/mips/include/asm/sigcontext.h
new file mode 100644
index 000000000..eeeb0f48c
--- /dev/null
+++ b/arch/mips/include/asm/sigcontext.h
@@ -0,0 +1,37 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGCONTEXT_H
+#define _ASM_SIGCONTEXT_H
+
+#include <uapi/asm/sigcontext.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+struct sigcontext32 {
+        __u32           sc_regmask;     /* Unused */
+        __u32           sc_status;      /* Unused */
+        __u64           sc_pc;
+        __u64           sc_regs[32];
+        __u64           sc_fpregs[32];
+        __u32           sc_acx;         /* Only MIPS32; was sc_ownedfp */
+        __u32           sc_fpc_csr;
+        __u32           sc_fpc_eir;     /* Unused */
+        __u32           sc_used_math;
+        __u32           sc_dsp;         /* dsp status, was sc_ssflags */
+        __u64           sc_mdhi;
+        __u64           sc_mdlo;
+        __u32           sc_hi1;         /* Was sc_cause */
+        __u32           sc_lo1;         /* Was sc_badvaddr */
+        __u32           sc_hi2;         /* Was sc_sigset[4] */
+        __u32           sc_lo2;
+        __u32           sc_hi3;
+        __u32           sc_lo3;
+};
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+#endif /* _ASM_SIGCONTEXT_H */
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
new file mode 100644
index 000000000..23d6b8015
--- /dev/null
+++ b/arch/mips/include/asm/signal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGNAL_H
+#define _ASM_SIGNAL_H
+
+#include <uapi/asm/signal.h>
+
+#ifdef CONFIG_MIPS32_O32
+extern struct mips_abi mips_abi_32;
+
+#define sig_uses_siginfo(ka, abi)                               \
+        ((abi != &mips_abi_32) ? 1 :                            \
+                ((ka)->sa.sa_flags & SA_SIGINFO))
+#else
+#define sig_uses_siginfo(ka, abi)                               \
+        (IS_ENABLED(CONFIG_64BIT) ? 1 :                     \
+                (IS_ENABLED(CONFIG_TRAD_SIGNALS) ?          \
+                        ((ka)->sa.sa_flags & SA_SIGINFO) : 1) )
+#endif
+
+#include <asm/sigcontext.h>
+#include <asm/siginfo.h>
+
+#define __ARCH_HAS_IRIX_SIGACTION
+
+extern int protected_save_fp_context(void __user *sc);
+extern int protected_restore_fp_context(void __user *sc);
+
+#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/asm/sim.h b/arch/mips/include/asm/sim.h
new file mode 100644
index 000000000..59f31a95f
--- /dev/null
+++ b/arch/mips/include/asm/sim.h
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIM_H
+#define _ASM_SIM_H
+
+
+#include <asm/asm-offsets.h>
+
+#define __str2(x) #x
+#define __str(x) __str2(x)
+
+#ifdef CONFIG_32BIT
+
+#define save_static_function(symbol)                                    \
+__asm__(                                                                \
+        ".text\n\t"                                                     \
+        ".globl\t__" #symbol "\n\t"                                     \
+        ".align\t2\n\t"                                                 \
+        ".type\t__" #symbol ", @function\n\t"                           \
+        ".ent\t__" #symbol ", 0\n__"                                    \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sw\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sw\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sw\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sw\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sw\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sw\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sw\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sw\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t" #symbol "\n\t"                                            \
+        ".end\t__" #symbol "\n\t"                                       \
+        ".size\t__" #symbol",. - __" #symbol)
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#define save_static_function(symbol)                                    \
+__asm__(                                                                \
+        ".text\n\t"                                                     \
+        ".globl\t__" #symbol "\n\t"                                     \
+        ".align\t2\n\t"                                                 \
+        ".type\t__" #symbol ", @function\n\t"                           \
+        ".ent\t__" #symbol ", 0\n__"                                    \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sd\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sd\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sd\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sd\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sd\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sd\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sd\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sd\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t" #symbol "\n\t"                                            \
+        ".end\t__" #symbol "\n\t"                                       \
+        ".size\t__" #symbol",. - __" #symbol)
+
+#endif /* CONFIG_64BIT */
+
+#endif /* _ASM_SIM_H */
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h
new file mode 100644
index 000000000..7e5b9411f
--- /dev/null
+++ b/arch/mips/include/asm/smp-cps.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_SMP_CPS_H__
+#define __MIPS_ASM_SMP_CPS_H__
+
+#ifndef __ASSEMBLY__
+
+struct vpe_boot_config {
+        unsigned long pc;
+        unsigned long sp;
+        unsigned long gp;
+};
+
+struct core_boot_config {
+        atomic_t vpe_mask;
+        struct vpe_boot_config *vpe_config;
+};
+
+extern struct core_boot_config *mips_cps_core_bootcfg;
+
+extern void mips_cps_core_entry(void);
+extern void mips_cps_core_init(void);
+
+extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
+
+extern void mips_cps_pm_save(void);
+extern void mips_cps_pm_restore(void);
+
+#ifdef CONFIG_MIPS_CPS
+
+extern bool mips_cps_smp_in_use(void);
+
+#else /* !CONFIG_MIPS_CPS */
+
+static inline bool mips_cps_smp_in_use(void) { return false; }
+
+#endif /* !CONFIG_MIPS_CPS */
+
+#else /* __ASSEMBLY__ */
+
+.extern mips_cps_bootcfg;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MIPS_ASM_SMP_CPS_H__ */
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
new file mode 100644
index 000000000..65618ff12
--- /dev/null
+++ b/arch/mips/include/asm/smp-ops.h
@@ -0,0 +1,121 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
+ * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001, 2002 Ralf Baechle
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SMP_OPS_H
+#define __ASM_SMP_OPS_H
+
+#include <linux/errno.h>
+
+#include <asm/mips-cps.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/cpumask.h>
+
+struct task_struct;
+
+struct plat_smp_ops {
+        void (*send_ipi_single)(int cpu, unsigned int action);
+        void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action);
+        void (*init_secondary)(void);
+        void (*smp_finish)(void);
+        int (*boot_secondary)(int cpu, struct task_struct *idle);
+        void (*smp_setup)(void);
+        void (*prepare_cpus)(unsigned int max_cpus);
+        void (*prepare_boot_cpu)(void);
+#ifdef CONFIG_HOTPLUG_CPU
+        int (*cpu_disable)(void);
+        void (*cpu_die)(unsigned int cpu);
+#endif
+#ifdef CONFIG_KEXEC
+        void (*kexec_nonboot_cpu)(void);
+#endif
+};
+
+extern void register_smp_ops(const struct plat_smp_ops *ops);
+
+static inline void plat_smp_setup(void)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        mp_ops->smp_setup();
+}
+
+extern void mips_smp_send_ipi_single(int cpu, unsigned int action);
+extern void mips_smp_send_ipi_mask(const struct cpumask *mask,
+                                      unsigned int action);
+
+#else /* !CONFIG_SMP */
+
+struct plat_smp_ops;
+
+static inline void plat_smp_setup(void)
+{
+        /* UP, nothing to do ...  */
+}
+
+static inline void register_smp_ops(const struct plat_smp_ops *ops)
+{
+}
+
+#endif /* !CONFIG_SMP */
+
+static inline int register_up_smp_ops(void)
+{
+#ifdef CONFIG_SMP_UP
+        extern const struct plat_smp_ops up_smp_ops;
+
+        register_smp_ops(&up_smp_ops);
+
+        return 0;
+#else
+        return -ENODEV;
+#endif
+}
+
+static inline int register_cmp_smp_ops(void)
+{
+#ifdef CONFIG_MIPS_CMP
+        extern const struct plat_smp_ops cmp_smp_ops;
+
+        if (!mips_cm_present())
+                return -ENODEV;
+
+        register_smp_ops(&cmp_smp_ops);
+
+        return 0;
+#else
+        return -ENODEV;
+#endif
+}
+
+static inline int register_vsmp_smp_ops(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+        extern const struct plat_smp_ops vsmp_smp_ops;
+
+        register_smp_ops(&vsmp_smp_ops);
+
+        return 0;
+#else
+        return -ENODEV;
+#endif
+}
+
+#ifdef CONFIG_MIPS_CPS
+extern int register_cps_smp_ops(void);
+#else
+static inline int register_cps_smp_ops(void)
+{
+        return -ENODEV;
+}
+#endif
+
+#endif /* __ASM_SMP_OPS_H */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
new file mode 100644
index 000000000..5d9ff6100
--- /dev/null
+++ b/arch/mips/include/asm/smp.h
@@ -0,0 +1,138 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
+ * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001, 2002 Ralf Baechle
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SMP_H
+#define __ASM_SMP_H
+
+#include <linux/bitops.h>
+#include <linux/linkage.h>
+#include <linux/smp.h>
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+
+#include <linux/atomic.h>
+#include <asm/smp-ops.h>
+
+extern int smp_num_siblings;
+extern cpumask_t cpu_sibling_map[];
+extern cpumask_t cpu_core_map[];
+extern cpumask_t cpu_foreign_map[];
+
+static inline int raw_smp_processor_id(void)
+{
+#if defined(__VDSO__)
+        extern int vdso_smp_processor_id(void)
+                __compiletime_error("VDSO should not call smp_processor_id()");
+        return vdso_smp_processor_id();
+#else
+        return current_thread_info()->cpu;
+#endif
+}
+#define raw_smp_processor_id raw_smp_processor_id
+
+/* Map from cpu id to sequential logical cpu number.  This will only
+   not be idempotent when cpus failed to come on-line.  */
+extern int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
+
+#define NO_PROC_ID      (-1)
+
+#define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
+#define SMP_CALL_FUNCTION       0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH        0x4
+#define SMP_ASK_C0COUNT         0x8
+
+/* Mask of CPUs which are currently definitely operating coherently */
+extern cpumask_t cpu_coherent_mask;
+
+extern asmlinkage void smp_bootstrap(void);
+
+extern void calculate_cpu_foreign_map(void);
+
+/*
+ * this function sends a 'reschedule' IPI to another CPU.
+ * it goes straight through and wastes no time serializing
+ * anything. Worst case is that we lose a reschedule ...
+ */
+static inline void smp_send_reschedule(int cpu)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static inline int __cpu_disable(void)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        return mp_ops->cpu_disable();
+}
+
+static inline void __cpu_die(unsigned int cpu)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        mp_ops->cpu_die(cpu);
+}
+
+extern void play_dead(void);
+#endif
+
+#ifdef CONFIG_KEXEC
+static inline void kexec_nonboot_cpu(void)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        return mp_ops->kexec_nonboot_cpu();
+}
+
+static inline void *kexec_nonboot_cpu_func(void)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        return mp_ops->kexec_nonboot_cpu;
+}
+#endif
+
+/*
+ * This function will set up the necessary IPIs for Linux to communicate
+ * with the CPUs in mask.
+ * Return 0 on success.
+ */
+int mips_smp_ipi_allocate(const struct cpumask *mask);
+
+/*
+ * This function will free up IPIs allocated with mips_smp_ipi_allocate to the
+ * CPUs in mask, which must be a subset of the IPIs that have been configured.
+ * Return 0 on success.
+ */
+int mips_smp_ipi_free(const struct cpumask *mask);
+
+static inline void arch_send_call_function_single_ipi(int cpu)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        mp_ops->send_ipi_single(cpu, SMP_CALL_FUNCTION);
+}
+
+static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
+{
+        extern const struct plat_smp_ops *mp_ops;       /* private */
+
+        mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
+}
+
+#endif /* __ASM_SMP_H */
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
new file mode 100644
index 000000000..837d23e24
--- /dev/null
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -0,0 +1,377 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_ADDRS_H
+#define _ASM_SN_ADDRS_H
+
+
+#ifndef __ASSEMBLY__
+#include <linux/smp.h>
+#include <linux/types.h>
+#endif /* !__ASSEMBLY__ */
+
+#include <asm/addrspace.h>
+#include <asm/sn/kldir.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/addrs.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/addrs.h>
+#endif
+
+
+#ifndef __ASSEMBLY__
+
+#define UINT64_CAST             (unsigned long)
+
+#else /* __ASSEMBLY__ */
+
+#define UINT64_CAST
+
+#endif /* __ASSEMBLY__ */
+
+
+#define NASID_GET_META(_n)      ((_n) >> NASID_LOCAL_BITS)
+#ifdef CONFIG_SGI_IP27
+#define NASID_GET_LOCAL(_n)     ((_n) & 0xf)
+#endif
+#define NASID_MAKE(_m, _l)      (((_m) << NASID_LOCAL_BITS) | (_l))
+
+#define NODE_ADDRSPACE_MASK     (NODE_ADDRSPACE_SIZE - 1)
+#define TO_NODE_ADDRSPACE(_pa)  (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
+
+#define CHANGE_ADDR_NASID(_pa, _nasid)  \
+                ((UINT64_CAST(_pa) & ~NASID_MASK) | \
+                 (UINT64_CAST(_nasid) <<  NASID_SHFT))
+
+
+/*
+ * The following macros are used to index to the beginning of a specific
+ * node's address space.
+ */
+
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+
+#define NODE_CAC_BASE(_n)       (CAC_BASE   + NODE_OFFSET(_n))
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_IO_BASE(_n)        (IO_BASE    + NODE_OFFSET(_n))
+#define NODE_MSPEC_BASE(_n)     (MSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_UNCAC_BASE(_n)     (UNCAC_BASE + NODE_OFFSET(_n))
+
+#define TO_NODE(_n, _x)         (NODE_OFFSET(_n)     | ((_x)               ))
+#define TO_NODE_CAC(_n, _x)     (NODE_CAC_BASE(_n)   | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_UNCAC(_n, _x)   (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_MSPEC(_n, _x)   (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_HSPEC(_n, _x)   (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+
+
+#define RAW_NODE_SWIN_BASE(nasid, widget)                               \
+        (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
+
+#define WIDGETID_GET(addr)      ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS          24
+#define SWIN_SIZE               (UINT64_CAST 1 << 24)
+#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
+#define SWIN_WIDGET_MASK        0xF
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
+#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to small window address on node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+#define NODE_SWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
+                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
+                 ))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN.
+ *      UALIAS -- 256MB in size, reads in the UALIAS result in
+ *                      uncached references to the memory of the reader's node.
+ *      CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
+ *                      depending on which CPU does the access to provide
+ *                      all CPUs with unique uncached memory at low addresses.
+ *      LBOOT  -- 256MB in size, reads in the LBOOT area result in
+ *                      uncached references to the local hub's boot prom and
+ *                      other directory-bus connected devices.
+ *      IALIAS -- 8MB in size, reads in the IALIAS result in uncached
+ *                      references to the local hub's registers.
+ */
+
+#define UALIAS_BASE             HSPEC_BASE
+#define UALIAS_SIZE             0x10000000      /* 256 Megabytes */
+#define UALIAS_LIMIT            (UALIAS_BASE + UALIAS_SIZE)
+
+/*
+ * The bottom of ualias space is flipped depending on whether you're
+ * processor 0 or 1 within a node.
+ */
+#ifdef CONFIG_SGI_IP27
+#define UALIAS_FLIP_BASE        UALIAS_BASE
+#define UALIAS_FLIP_SIZE        0x20000
+#define UALIAS_FLIP_BIT         0x10000
+#define UALIAS_FLIP_ADDR(_x)    (cputoslice(smp_processor_id()) ? \
+                                 (_x) ^ UALIAS_FLIP_BIT : (_x))
+
+#define LBOOT_BASE              (HSPEC_BASE + 0x10000000)
+#define LBOOT_SIZE              0x10000000
+#define LBOOT_LIMIT             (LBOOT_BASE + LBOOT_SIZE)
+#define LBOOT_STRIDE            0               /* IP27 has only one CPU PROM */
+
+#endif
+
+#define HUB_REGISTER_WIDGET     1
+#define IALIAS_BASE             NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#define IALIAS_SIZE             0x800000        /* 8 Megabytes */
+#define IS_IALIAS(_a)           (((_a) >= IALIAS_BASE) &&               \
+                                 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
+
+/*
+ * Macro for referring to Hub's RBOOT space
+ */
+
+#ifdef CONFIG_SGI_IP27
+#define RBOOT_SIZE              0x10000000      /* 256 Megabytes */
+#define NODE_RBOOT_BASE(_n)     (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_RBOOT_LIMIT(_n)    (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
+
+#endif
+
+/*
+ * Macros for referring the Hub's back door space
+ *
+ *   These macros correctly process addresses in any node's space.
+ *   WARNING: They won't work in assembler.
+ *
+ *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
+ *                  entry corresponding to a physical (Cac or Uncac) address.
+ *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
+ *   BDPRT_ENTRY    returns the address of the double-word protection entry
+ *                  corresponding to the page containing the physical address.
+ *   BDPRT_ENTRY_S  Stores the value into the protection entry.
+ *   BDPRT_ENTRY_L  Load the value from the protection entry.
+ *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
+ *                  double-word at a specified physical address.
+ *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
+ *                  quad-word at a specified physical address.
+ */
+#define NODE_BDOOR_BASE(_n)     (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
+
+#define NODE_BDECC_BASE(_n)     (NODE_BDOOR_BASE(_n))
+#define NODE_BDDIR_BASE(_n)     (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
+#ifdef CONFIG_SGI_IP27
+#define BDDIR_ENTRY_LO(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x200)                                    | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
+
+#define BDDIR_ENTRY_HI(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x208)                                    | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
+
+#define BDPRT_ENTRY(_pa, _rgn)  ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4)              | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 (_rgn) << 3)
+#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
+#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
+#define BDPRT_ENTRY_L(_pa, _rgn)        (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
+
+#define BDECC_ENTRY(_pa)        ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE / 2)                  | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 3)
+
+/*
+ * Macro to convert a back door directory or protection address into the
+ *   raw physical address of the associated cache line or protection page.
+ */
+#define BDADDR_IS_DIR(_ba)      ((UINT64_CAST  (_ba) & 0x200) != 0)
+#define BDADDR_IS_PRT(_ba)      ((UINT64_CAST  (_ba) & 0x200) == 0)
+
+#define BDDIR_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK            | \
+                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
+
+#define BDPRT_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
+                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
+
+#define BDECC_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
+                                 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST(_ba) & 3) << 3)
+#endif /* CONFIG_SGI_IP27 */
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers.  The LOCAL_HUB_* macros produce the appropriate
+ * address for the local registers.  The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for _x.
+ */
+
+/*
+ * WARNING:
+ *      When certain Hub chip workaround are defined, it's not sufficient
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *      They're always safe.
+ */
+#define LOCAL_HUB_ADDR(_x)      (IALIAS_BASE + (_x))
+#define REMOTE_HUB_ADDR(_n, _x) ((NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))
+
+#ifndef __ASSEMBLY__
+
+#define LOCAL_HUB_PTR(_x)       ((u64 *)LOCAL_HUB_ADDR((_x)))
+#define REMOTE_HUB_PTR(_n, _x)  ((u64 *)REMOTE_HUB_ADDR((_n), (_x)))
+
+#define LOCAL_HUB_L(_r)                 __raw_readq(LOCAL_HUB_PTR(_r))
+#define LOCAL_HUB_S(_r, _d)             __raw_writeq((_d), LOCAL_HUB_PTR(_r))
+#define REMOTE_HUB_L(_n, _r)            __raw_readq(REMOTE_HUB_PTR((_n), (_r)))
+#define REMOTE_HUB_S(_n, _r, _d)        __raw_writeq((_d),              \
+                                                REMOTE_HUB_PTR((_n), (_r)))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Software structure locations -- permanently fixed
+ *    See diagram in kldir.h
+ */
+
+#define PHYS_RAMBASE            0x0
+#define K0_RAMBASE              PHYS_TO_K0(PHYS_RAMBASE)
+
+#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
+#define EX_HANDLER_ADDR(nasid, slice)                                   \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
+#define EX_HANDLER_SIZE         0x0400
+
+#define EX_FRAME_OFFSET(slice)  ((slice) << 16 | 0x400)
+#define EX_FRAME_ADDR(nasid, slice)                                     \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
+#define EX_FRAME_SIZE           0x0c00
+
+#define ARCS_SPB_OFFSET         0x1000
+#define ARCS_SPB_ADDR(nasid)                                            \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
+#define ARCS_SPB_SIZE           0x0400
+
+#define KLDIR_OFFSET            0x2000
+#define KLDIR_ADDR(nasid)                                               \
+        TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
+#define KLDIR_SIZE              0x0400
+
+
+/*
+ * Software structure locations -- indirected through KLDIR
+ *    See diagram in kldir.h
+ *
+ * Important:   All low memory structures must only be accessed
+ *              uncached, except for the symmon stacks.
+ */
+
+#define KLI_LAUNCH              0               /* Dir. entries */
+#define KLI_KLCONFIG            1
+#define KLI_NMI                 2
+#define KLI_GDA                 3
+#define KLI_FREEMEM             4
+#define KLI_SYMMON_STK          5
+#define KLI_PI_ERROR            6
+#define KLI_KERN_VARS           7
+#define KLI_KERN_XP             8
+#define KLI_KERN_PARTID         9
+
+#ifndef __ASSEMBLY__
+
+#define KLD_BASE(nasid)         ((kldir_ent_t *) KLDIR_ADDR(nasid))
+#define KLD_LAUNCH(nasid)       (KLD_BASE(nasid) + KLI_LAUNCH)
+#define KLD_NMI(nasid)          (KLD_BASE(nasid) + KLI_NMI)
+#define KLD_KLCONFIG(nasid)     (KLD_BASE(nasid) + KLI_KLCONFIG)
+#define KLD_PI_ERROR(nasid)     (KLD_BASE(nasid) + KLI_PI_ERROR)
+#define KLD_GDA(nasid)          (KLD_BASE(nasid) + KLI_GDA)
+#define KLD_SYMMON_STK(nasid)   (KLD_BASE(nasid) + KLI_SYMMON_STK)
+#define KLD_FREEMEM(nasid)      (KLD_BASE(nasid) + KLI_FREEMEM)
+#define KLD_KERN_VARS(nasid)    (KLD_BASE(nasid) + KLI_KERN_VARS)
+#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
+#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
+
+#define LAUNCH_OFFSET(nasid, slice)                                     \
+        (KLD_LAUNCH(nasid)->offset +                                    \
+         KLD_LAUNCH(nasid)->stride * (slice))
+#define LAUNCH_ADDR(nasid, slice)                                       \
+        TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
+#define LAUNCH_SIZE(nasid)      KLD_LAUNCH(nasid)->size
+
+#define SN_NMI_OFFSET(nasid, slice)                                     \
+        (KLD_NMI(nasid)->offset +                                       \
+         KLD_NMI(nasid)->stride * (slice))
+#define NMI_ADDR(nasid, slice)                                          \
+        TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice))
+#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
+
+#define KLCONFIG_OFFSET(nasid)  KLD_KLCONFIG(nasid)->offset
+#define KLCONFIG_ADDR(nasid)                                            \
+        TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+#define KLCONFIG_SIZE(nasid)    KLD_KLCONFIG(nasid)->size
+
+#define GDA_ADDR(nasid)         KLD_GDA(nasid)->pointer
+#define GDA_SIZE(nasid)         KLD_GDA(nasid)->size
+
+#define SYMMON_STK_OFFSET(nasid, slice)                                 \
+        (KLD_SYMMON_STK(nasid)->offset +                                \
+         KLD_SYMMON_STK(nasid)->stride * (slice))
+#define SYMMON_STK_STRIDE(nasid)        KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_ADDR(nasid, slice)                                   \
+        TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
+
+#define SYMMON_STK_SIZE(nasid)  KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_END(nasid)   (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
+
+#define NODE_OFFSET_TO_K0(_nasid, _off)                                 \
+        PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
+#define NODE_OFFSET_TO_K1(_nasid, _off)                                 \
+        TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
+
+#define KERN_VARS_ADDR(nasid)   KLD_KERN_VARS(nasid)->pointer
+#define KERN_VARS_SIZE(nasid)   KLD_KERN_VARS(nasid)->size
+
+#endif /* !__ASSEMBLY__ */
+
+
+#endif /* _ASM_SN_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
new file mode 100644
index 000000000..7e9b32717
--- /dev/null
+++ b/arch/mips/include/asm/sn/agent.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file has definitions for the hub and snac interfaces.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
+ * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGI_SN_AGENT_H
+#define _ASM_SGI_SN_AGENT_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hub.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/hub.h>
+#endif  /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+/*
+ * NIC register macros
+ */
+
+#if defined(CONFIG_SGI_IP27)
+#define HUB_NIC_ADDR(_cpuid)                                               \
+        REMOTE_HUB_ADDR(cpu_to_node(_cpuid),                               \
+                MD_MLAN_CTL)
+#endif
+
+#define SET_HUB_NIC(_my_cpuid, _val)                                       \
+        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
+
+#define SET_MY_HUB_NIC(_v)                                                 \
+        SET_HUB_NIC(cpuid(), (_v))
+
+#define GET_HUB_NIC(_my_cpuid)                                             \
+        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
+
+#define GET_MY_HUB_NIC()                                                   \
+        GET_HUB_NIC(cpuid())
+
+#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
new file mode 100644
index 000000000..9a9682543
--- /dev/null
+++ b/arch/mips/include/asm/sn/arch.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_ARCH_H
+#define _ASM_SN_ARCH_H
+
+#include <linux/types.h>
+#include <asm/sn/types.h>
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/sn0/arch.h>
+#endif
+
+#define cputonasid(cpu)         (sn_cpu_info[(cpu)].p_nasid)
+#define cputoslice(cpu)         (sn_cpu_info[(cpu)].p_slice)
+
+#define INVALID_NASID           (nasid_t)-1
+#define INVALID_PNODEID         (pnodeid_t)-1
+#define INVALID_MODULE          (moduleid_t)-1
+#define INVALID_PARTID          (partid_t)-1
+
+#endif /* _ASM_SN_ARCH_H */
diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h
new file mode 100644
index 000000000..bbb83257c
--- /dev/null
+++ b/arch/mips/include/asm/sn/fru.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
+ */
+#ifndef __ASM_SN_FRU_H
+#define __ASM_SN_FRU_H
+
+#define MAX_DIMMS                       8        /* max # of dimm banks */
+#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+        confidence_t km_confidence; /* confidence level that the memory is bad
+                                     * is this necessary ?
+                                     */
+        confidence_t km_dimm[MAX_DIMMS];
+                                    /* confidence level that dimm[i] is bad
+                                     *I think this is the right number
+                                     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+typedef struct kf_pci_bus_s {
+        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
+        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
+                                        /* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+#endif /* __ASM_SN_FRU_H */
diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h
new file mode 100644
index 000000000..d52f81620
--- /dev/null
+++ b/arch/mips/include/asm/sn/gda.h
@@ -0,0 +1,105 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/gda.h>.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ *
+ * gda.h -- Contains the data structure for the global data area,
+ *      The GDA contains information communicated between the
+ *      PROM, SYMMON, and the kernel.
+ */
+#ifndef _ASM_SN_GDA_H
+#define _ASM_SN_GDA_H
+
+#include <asm/sn/addrs.h>
+
+#define GDA_MAGIC       0x58464552
+
+/*
+ * GDA Version History
+ *
+ * Version #    | Change
+ * -------------+-------------------------------------------------------
+ *      1       | Initial SN0 version
+ *      2       | Prom sets g_partid field to the partition number. 0 IS
+ *              | a valid partition #.
+ */
+
+#define GDA_VERSION     2       /* Current GDA version # */
+
+#define G_MAGICOFF      0
+#define G_VERSIONOFF    4
+#define G_PROMOPOFF     6
+#define G_MASTEROFF     8
+#define G_VDSOFF        12
+#define G_HKDNORMOFF    16
+#define G_HKDUTLBOFF    24
+#define G_HKDXUTLBOFF   32
+#define G_PARTIDOFF     40
+#define G_TABLEOFF      128
+
+#ifndef __ASSEMBLY__
+
+typedef struct gda {
+        u32     g_magic;        /* GDA magic number */
+        u16     g_version;      /* Version of this structure */
+        u16     g_masterid;     /* The NASID:CPUNUM of the master cpu */
+        u32     g_promop;       /* Passes requests from the kernel to prom */
+        u32     g_vds;          /* Store the virtual dipswitches here */
+        void    **g_hooked_norm;/* ptr to pda loc for norm hndlr */
+        void    **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
+        void    **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
+        int     g_partid;       /* partition id */
+        int     g_symmax;       /* Max symbols in name table. */
+        void    *g_dbstab;      /* Address of idbg symbol table */
+        char    *g_nametab;     /* Address of idbg name table */
+        void    *g_ktext_repmask;
+                                /* Pointer to a mask of nodes with copies
+                                 * of the kernel. */
+        char    g_padding[56];  /* pad out to 128 bytes */
+        nasid_t g_nasidtable[MAX_NUMNODES]; /* NASID of each node */
+} gda_t;
+
+#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
+
+#endif /* !__ASSEMBLY__ */
+/*
+ * Define:      PART_GDA_VERSION
+ * Purpose:     Define the minimum version of the GDA required, lower
+ *              revisions assume GDA is NOT set up, and read partition
+ *              information from the board info.
+ */
+#define PART_GDA_VERSION        2
+
+/*
+ * The following requests can be sent to the PROM during startup.
+ */
+
+#define PROMOP_MAGIC            0x0ead0000
+#define PROMOP_MAGIC_MASK       0x0fff0000
+
+#define PROMOP_BIST_SHIFT       11
+#define PROMOP_BIST_MASK        (0x3 << 11)
+
+#define PROMOP_REG              PI_ERR_STACK_ADDR_A
+
+#define PROMOP_INVALID          (PROMOP_MAGIC | 0x00)
+#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+
+#define PROMOP_CMD_MASK         0x00f0
+#define PROMOP_OPTIONS_MASK     0xfff0
+
+#define PROMOP_SKIP_DIAGS       0x0100          /* don't bother running diags */
+#define PROMOP_SKIP_MEMINIT     0x0200          /* don't bother initing memory */
+#define PROMOP_SKIP_DEVINIT     0x0400          /* don't bother initing devices */
+#define PROMOP_BIST1            0x0800          /* keep track of which BIST ran */
+#define PROMOP_BIST2            0x1000          /* keep track of which BIST ran */
+
+#endif /* _ASM_SN_GDA_H */
diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
new file mode 100644
index 000000000..3d6954d37
--- /dev/null
+++ b/arch/mips/include/asm/sn/intr.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_INTR_H
+#define __ASM_SN_INTR_H
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(level)                              \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
+#define REMOTE_HUB_SEND_INTR(hub, level)                        \
+        REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
+
+/*
+ * When clearing the interrupt, make sure this clear does make it
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(level)                               \
+do {                                                            \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
+        LOCAL_HUB_L(PI_INT_PEND0);                              \
+} while (0);
+
+#define REMOTE_HUB_CLR_INTR(hub, level)                         \
+do {                                                            \
+        nasid_t  __hub = (hub);                                 \
+                                                                \
+        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
+        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
+} while (0);
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *      L0 = SW1
+ *      L1 = SW2
+ *      L2 = INT_PEND0
+ *      L3 = INT_PEND1
+ *      L4 = RTC
+ *      L5 = Profiling Timer
+ *      L6 = Hub Errors
+ *      L7 = Count/Compare (T5 counters)
+ */
+
+
+/*
+ * INT_PEND0 hard-coded bits.
+ */
+
+/*
+ * INT_PEND0 bits determined by hardware:
+ */
+#define RESERVED_INTR            0      /* What is this bit? */
+#define GFX_INTR_A               1
+#define GFX_INTR_B               2
+#define PG_MIG_INTR              3
+#define UART_INTR                4
+#define CC_PEND_A                5
+#define CC_PEND_B                6
+
+/*
+ * INT_PEND0 used by the kernel for itself ...
+ */
+#define CPU_RESCHED_A_IRQ        7
+#define CPU_RESCHED_B_IRQ        8
+#define CPU_CALL_A_IRQ           9
+#define CPU_CALL_B_IRQ          10
+
+/*
+ * INT_PEND1 hard-coded bits:
+ */
+#define NI_BRDCAST_ERR_A        39
+#define NI_BRDCAST_ERR_B        40
+
+#define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_B        42
+
+#define TLB_INTR_A              43      /* used for tlb flush random */
+#define TLB_INTR_B              44
+
+#define IP27_INTR_0             45      /* Reserved for PROM use */
+#define IP27_INTR_1             46      /* do not use in Kernel */
+#define IP27_INTR_2             47
+#define IP27_INTR_3             48
+#define IP27_INTR_4             49
+#define IP27_INTR_5             50
+#define IP27_INTR_6             51
+#define IP27_INTR_7             52
+
+#define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
+                                        /* Bridge Errors */
+#define DEBUG_INTR_A            54
+#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define IO_ERROR_INTR           57      /* Setup by PROM */
+#define CLK_ERR_INTR            58
+#define COR_ERR_INTR_A          59
+#define COR_ERR_INTR_B          60
+#define MD_COR_ERR_INTR         61
+#define NI_ERROR_INTR           62
+#define MSC_PANIC_INTR          63
+
+#endif /* __ASM_SN_INTR_H */
diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
new file mode 100644
index 000000000..211f1e83b
--- /dev/null
+++ b/arch/mips/include/asm/sn/io.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2003 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hubio.h>
+#endif
+
+
+#define IIO_ITTE_BASE           0x400160 /* base of translation table entries */
+#define IIO_ITTE(bigwin)        (IIO_ITTE_BASE + 8*(bigwin))
+
+#define IIO_ITTE_OFFSET_BITS    5       /* size of offset field */
+#define IIO_ITTE_OFFSET_MASK    ((1<<IIO_ITTE_OFFSET_BITS)-1)
+#define IIO_ITTE_OFFSET_SHIFT   0
+
+#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
+#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
+#define IIO_ITTE_WIDGET_SHIFT   8
+
+#define IIO_ITTE_IOSP           1       /* I/O Space bit */
+#define IIO_ITTE_IOSP_MASK      1
+#define IIO_ITTE_IOSP_SHIFT     12
+#define HUB_PIO_MAP_TO_MEM      0
+#define HUB_PIO_MAP_TO_IO       1
+
+#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
+
+#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
+        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
+                (((((addr) >> BWIN_SIZE_BITS) & \
+                   IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
+                (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
+                (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
+
+#define IIO_ITTE_DISABLE(nasid, bigwin) \
+        IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
+                     (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
+
+#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_PTR((nasid), IIO_ITTE(bigwin))
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+#endif /* _ASM_SN_IO_H */
diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
new file mode 100644
index 000000000..2c09c17ca
--- /dev/null
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -0,0 +1,606 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1999, 2000 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef MIPS_SN_IOC3_H
+#define MIPS_SN_IOC3_H
+
+#include <linux/types.h>
+
+/* serial port register map */
+struct ioc3_serialregs {
+        u32     sscr;
+        u32     stpir;
+        u32     stcir;
+        u32     srpir;
+        u32     srcir;
+        u32     srtr;
+        u32     shadow;
+};
+
+/* SUPERIO uart register map */
+struct ioc3_uartregs {
+        u8      iu_lcr;
+        union {
+                u8      iu_iir; /* read only */
+                u8      iu_fcr; /* write only */
+        };
+        union {
+                u8      iu_ier; /* DLAB == 0 */
+                u8      iu_dlm; /* DLAB == 1 */
+        };
+        union {
+                u8      iu_rbr; /* read only, DLAB == 0 */
+                u8      iu_thr; /* write only, DLAB == 0 */
+                u8      iu_dll; /* DLAB == 1 */
+        };
+        u8      iu_scr;
+        u8      iu_msr;
+        u8      iu_lsr;
+        u8      iu_mcr;
+};
+
+struct ioc3_sioregs {
+        u8      fill[0x141];    /* starts at 0x141 */
+
+        u8      kbdcg;
+        u8      uartc;
+
+        u8      fill0[0x151 - 0x142 - 1];
+
+        u8      pp_dcr;
+        u8      pp_dsr;
+        u8      pp_data;
+
+        u8      fill1[0x159 - 0x153 - 1];
+
+        u8      pp_ecr;
+        u8      pp_cfgb;
+        u8      pp_fifa;
+
+        u8      fill2[0x16a - 0x15b - 1];
+
+        u8      rtcdat;
+        u8      rtcad;
+
+        u8      fill3[0x170 - 0x16b - 1];
+
+        struct ioc3_uartregs    uartb;  /* 0x20170  */
+        struct ioc3_uartregs    uarta;  /* 0x20178  */
+};
+
+struct ioc3_ethregs {
+        u32     emcr;           /* 0x000f0  */
+        u32     eisr;           /* 0x000f4  */
+        u32     eier;           /* 0x000f8  */
+        u32     ercsr;          /* 0x000fc  */
+        u32     erbr_h;         /* 0x00100  */
+        u32     erbr_l;         /* 0x00104  */
+        u32     erbar;          /* 0x00108  */
+        u32     ercir;          /* 0x0010c  */
+        u32     erpir;          /* 0x00110  */
+        u32     ertr;           /* 0x00114  */
+        u32     etcsr;          /* 0x00118  */
+        u32     ersr;           /* 0x0011c  */
+        u32     etcdc;          /* 0x00120  */
+        u32     ebir;           /* 0x00124  */
+        u32     etbr_h;         /* 0x00128  */
+        u32     etbr_l;         /* 0x0012c  */
+        u32     etcir;          /* 0x00130  */
+        u32     etpir;          /* 0x00134  */
+        u32     emar_h;         /* 0x00138  */
+        u32     emar_l;         /* 0x0013c  */
+        u32     ehar_h;         /* 0x00140  */
+        u32     ehar_l;         /* 0x00144  */
+        u32     micr;           /* 0x00148  */
+        u32     midr_r;         /* 0x0014c  */
+        u32     midr_w;         /* 0x00150  */
+};
+
+struct ioc3_serioregs {
+        u32     km_csr;         /* 0x0009c  */
+        u32     k_rd;           /* 0x000a0  */
+        u32     m_rd;           /* 0x000a4  */
+        u32     k_wd;           /* 0x000a8  */
+        u32     m_wd;           /* 0x000ac  */
+};
+
+/* Register layout of IOC3 in configuration space.  */
+struct ioc3 {
+        /* PCI Config Space registers  */
+        u32     pci_id;         /* 0x00000  */
+        u32     pci_scr;        /* 0x00004  */
+        u32     pci_rev;        /* 0x00008  */
+        u32     pci_lat;        /* 0x0000c  */
+        u32     pci_addr;       /* 0x00010  */
+        u32     pci_err_addr_l; /* 0x00014  */
+        u32     pci_err_addr_h; /* 0x00018  */
+
+        u32     sio_ir;         /* 0x0001c  */
+        u32     sio_ies;        /* 0x00020  */
+        u32     sio_iec;        /* 0x00024  */
+        u32     sio_cr;         /* 0x00028  */
+        u32     int_out;        /* 0x0002c  */
+        u32     mcr;            /* 0x00030  */
+
+        /* General Purpose I/O registers  */
+        u32     gpcr_s;         /* 0x00034  */
+        u32     gpcr_c;         /* 0x00038  */
+        u32     gpdr;           /* 0x0003c  */
+        u32     gppr[16];       /* 0x00040  */
+
+        /* Parallel Port Registers  */
+        u32     ppbr_h_a;       /* 0x00080  */
+        u32     ppbr_l_a;       /* 0x00084  */
+        u32     ppcr_a;         /* 0x00088  */
+        u32     ppcr;           /* 0x0008c  */
+        u32     ppbr_h_b;       /* 0x00090  */
+        u32     ppbr_l_b;       /* 0x00094  */
+        u32     ppcr_b;         /* 0x00098  */
+
+        /* Keyboard and Mouse Registers  */
+        struct ioc3_serioregs   serio;
+
+        /* Serial Port Registers  */
+        u32     sbbr_h;         /* 0x000b0  */
+        u32     sbbr_l;         /* 0x000b4  */
+        struct ioc3_serialregs  port_a;
+        struct ioc3_serialregs  port_b;
+
+        /* Ethernet Registers */
+        struct ioc3_ethregs     eth;
+        u32     pad1[(0x20000 - 0x00154) / 4];
+
+        /* SuperIO Registers  XXX */
+        struct ioc3_sioregs     sregs;  /* 0x20000 */
+        u32     pad2[(0x40000 - 0x20180) / 4];
+
+        /* SSRAM Diagnostic Access */
+        u32     ssram[(0x80000 - 0x40000) / 4];
+
+        /* Bytebus device offsets
+           0x80000 -   Access to the generic devices selected with   DEV0
+           0x9FFFF     bytebus DEV_SEL_0
+           0xA0000 -   Access to the generic devices selected with   DEV1
+           0xBFFFF     bytebus DEV_SEL_1
+           0xC0000 -   Access to the generic devices selected with   DEV2
+           0xDFFFF     bytebus DEV_SEL_2
+           0xE0000 -   Access to the generic devices selected with   DEV3
+           0xFFFFF     bytebus DEV_SEL_3  */
+};
+
+
+#define PCI_LAT                 0xc             /* Latency Timer */
+#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
+#define UARTA_BASE              0x178
+#define UARTB_BASE              0x170
+
+/*
+ * Bytebus device space
+ */
+#define IOC3_BYTEBUS_DEV0       0x80000L
+#define IOC3_BYTEBUS_DEV1       0xa0000L
+#define IOC3_BYTEBUS_DEV2       0xc0000L
+#define IOC3_BYTEBUS_DEV3       0xe0000L
+
+/*
+ * Ethernet RX Buffer
+ */
+struct ioc3_erxbuf {
+        u32     w0;                     /* first word (valid,bcnt,cksum) */
+        u32     err;                    /* second word various errors */
+        /* next comes n bytes of padding */
+        /* then the received ethernet frame itself */
+};
+
+#define ERXBUF_IPCKSUM_MASK     0x0000ffff
+#define ERXBUF_BYTECNT_MASK     0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT    16
+#define ERXBUF_V                0x80000000
+
+#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
+#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
+#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
+#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
+#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
+#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
+#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
+#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
+#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
+#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
+#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
+#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
+
+/*
+ * Ethernet TX Descriptor
+ */
+#define ETXD_DATALEN    104
+struct ioc3_etxd {
+        u32     cmd;                            /* command field */
+        u32     bufcnt;                         /* buffer counts field */
+        u64     p1;                             /* buffer pointer 1 */
+        u64     p2;                             /* buffer pointer 2 */
+        u8      data[ETXD_DATALEN];             /* opt. tx data */
+};
+
+#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
+#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
+#define ETXD_D0V                0x00010000      /* data 0 valid */
+#define ETXD_B1V                0x00020000      /* buf 1 valid */
+#define ETXD_B2V                0x00040000      /* buf 2 valid */
+#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
+#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT       20
+
+#define ETXD_D0CNT_MASK         0x0000007f
+#define ETXD_B1CNT_MASK         0x0007ff00
+#define ETXD_B1CNT_SHIFT        8
+#define ETXD_B2CNT_MASK         0x7ff00000
+#define ETXD_B2CNT_SHIFT        20
+
+/* ------------------------------------------------------------------------- */
+
+/* Superio Registers (PIO Access) */
+#define IOC3_SIO_BASE           0x20000
+#define IOC3_SIO_UARTC          (IOC3_SIO_BASE+0x141)   /* UART Config */
+#define IOC3_SIO_KBDCG          (IOC3_SIO_BASE+0x142)   /* KBD Config */
+#define IOC3_SIO_PP_BASE        (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
+#define IOC3_SIO_RTC_BASE       (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
+#define IOC3_SIO_UB_BASE        (IOC3_SIO_BASE+UARTB_BASE)      /* UART B */
+#define IOC3_SIO_UA_BASE        (IOC3_SIO_BASE+UARTA_BASE)      /* UART A */
+
+/* SSRAM Diagnostic Access */
+#define IOC3_SSRAM      IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
+#define IOC3_SSRAM_LEN  0x40000 /* 256kb (addrspc sz, may not be populated) */
+#define IOC3_SSRAM_DM   0x0000ffff      /* data mask */
+#define IOC3_SSRAM_PM   0x00010000      /* parity mask */
+
+/* bitmasks for PCI_SCR */
+#define PCI_SCR_PAR_RESP_EN     0x00000040      /* enb PCI parity checking */
+#define PCI_SCR_SERR_EN         0x00000100      /* enable the SERR# driver */
+#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
+#define PCI_SCR_RX_SERR         (0x1 << 16)
+#define PCI_SCR_DROP_MODE       (0x1 << 17)
+#define PCI_SCR_SIG_PAR_ERR     (0x1 << 24)
+#define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
+#define PCI_SCR_RX_TAR_ABRT     (0x1 << 28)
+#define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
+#define PCI_SCR_SIG_SERR        (0x1 << 30)
+#define PCI_SCR_PAR_ERR         (0x1 << 31)
+
+/* bitmasks for IOC3_KM_CSR */
+#define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
+#define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
+#define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
+#define KM_CSR_M_LCB      0x00000008    /* same for mouse */
+#define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
+#define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
+#define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
+#define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
+#define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
+#define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
+#define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
+#define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
+#define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
+#define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
+#define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
+#define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
+#define KM_CSR_K_TO       0x00010000    /* Keyboard trying to send/receive */
+#define KM_CSR_M_TO       0x00020000    /* Mouse trying to send/receive */
+#define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_K_CLAMP_1  0x00100000    /* Pull K_CLK low aft recv 1 char */
+#define KM_CSR_M_CLAMP_1  0x00200000    /* Pull M_CLK low aft recv 1 char */
+#define KM_CSR_K_CLAMP_3  0x00400000    /* Pull K_CLK low aft recv 3 chars */
+#define KM_CSR_M_CLAMP_3  0x00800000    /* Pull M_CLK low aft recv 3 chars */
+
+/* bitmasks for IOC3_K_RD and IOC3_M_RD */
+#define KM_RD_DATA_2    0x000000ff      /* 3rd char recvd since last read */
+#define KM_RD_DATA_2_SHIFT 0
+#define KM_RD_DATA_1    0x0000ff00      /* 2nd char recvd since last read */
+#define KM_RD_DATA_1_SHIFT 8
+#define KM_RD_DATA_0    0x00ff0000      /* 1st char recvd since last read */
+#define KM_RD_DATA_0_SHIFT 16
+#define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
+#define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
+#define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
+
+#define KM_RD_KBD_MSE   0x08000000      /* 0 if from kbd, 1 if from mouse */
+#define KM_RD_OFLO      0x10000000      /* 4th char recvd before this read */
+#define KM_RD_VALID_2   0x20000000      /* DATA_2 valid */
+#define KM_RD_VALID_1   0x40000000      /* DATA_1 valid */
+#define KM_RD_VALID_0   0x80000000      /* DATA_0 valid */
+#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
+
+/* bitmasks for IOC3_K_WD & IOC3_M_WD */
+#define KM_WD_WRT_DATA  0x000000ff      /* write to keyboard/mouse port */
+#define KM_WD_WRT_DATA_SHIFT 0
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN    0x01    /* char(s) lost */
+#define RXSB_PAR_ERR    0x02    /* parity error */
+#define RXSB_FRAME_ERR  0x04    /* framing error */
+#define RXSB_BREAK      0x08    /* break character */
+#define RXSB_CTS        0x10    /* state of CTS */
+#define RXSB_DCD        0x20    /* state of DCD */
+#define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
+#define TXCB_INVALID    0x00    /* byte is invalid */
+#define TXCB_VALID      0x40    /* byte is valid */
+#define TXCB_MCR        0x80    /* data<7:0> to modem control register */
+#define TXCB_DELAY      0xc0    /* delay data<7:0> mSec */
+
+/* bitmasks for IOC3_SBBR_L */
+#define SBBR_L_SIZE     0x00000001      /* 0 == 1KB rings, 1 == 4KB rings */
+#define SBBR_L_BASE     0xfffff000      /* lower serial ring base addr */
+
+/* bitmasks for IOC3_SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
+#define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
+#define SSCR_HFC_EN     0x00020000      /* hardware flow control enabled */
+#define SSCR_RX_RING_DCD 0x00040000     /* post RX record on delta-DCD */
+#define SSCR_RX_RING_CTS 0x00080000     /* post RX record on delta-CTS */
+#define SSCR_HIGH_SPD   0x00100000      /* 4X speed */
+#define SSCR_DIAG       0x00200000      /* bypass clock divider for sim */
+#define SSCR_RX_DRAIN   0x08000000      /* drain RX buffer to memory */
+#define SSCR_DMA_EN     0x10000000      /* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE  0x20000000      /* pause DMA */
+#define SSCR_PAUSE_STATE 0x40000000     /* sets when PAUSE takes effect */
+#define SSCR_RESET      0x80000000      /* reset DMA channels */
+
+/* all producer/consumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K 0x00000ff8     /* for 4K buffers */
+#define PROD_CONS_PTR_1K 0x000003f8     /* for 1K buffers */
+#define PROD_CONS_PTR_OFF 3
+
+/* bitmasks for IOC3_SRCIR_<A:B> */
+#define SRCIR_ARM       0x80000000      /* arm RX timer */
+
+/* bitmasks for IOC3_SRPIR_<A:B> */
+#define SRPIR_BYTE_CNT  0x07000000      /* bytes in packer */
+#define SRPIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_STCIR_<A:B> */
+#define STCIR_BYTE_CNT  0x0f000000      /* bytes in unpacker */
+#define STCIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_SHADOW_<A:B> */
+#define SHADOW_DR       0x00000001      /* data ready */
+#define SHADOW_OE       0x00000002      /* overrun error */
+#define SHADOW_PE       0x00000004      /* parity error */
+#define SHADOW_FE       0x00000008      /* framing error */
+#define SHADOW_BI       0x00000010      /* break interrupt */
+#define SHADOW_THRE     0x00000020      /* transmit holding register empty */
+#define SHADOW_TEMT     0x00000040      /* transmit shift register empty */
+#define SHADOW_RFCE     0x00000080      /* char in RX fifo has an error */
+#define SHADOW_DCTS     0x00010000      /* delta clear to send */
+#define SHADOW_DDCD     0x00080000      /* delta data carrier detect */
+#define SHADOW_CTS      0x00100000      /* clear to send */
+#define SHADOW_DCD      0x00800000      /* data carrier detect */
+#define SHADOW_DTR      0x01000000      /* data terminal ready */
+#define SHADOW_RTS      0x02000000      /* request to send */
+#define SHADOW_OUT1     0x04000000      /* 16550 OUT1 bit */
+#define SHADOW_OUT2     0x08000000      /* 16550 OUT2 bit */
+#define SHADOW_LOOP     0x10000000      /* loopback enabled */
+
+/* bitmasks for IOC3_SRTR_<A:B> */
+#define SRTR_CNT        0x00000fff      /* reload value for RX timer */
+#define SRTR_CNT_VAL    0x0fff0000      /* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT 16
+#define SRTR_HZ         16000   /* SRTR clock frequency */
+
+/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
+#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
+#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
+#define SIO_IR_SB_TX_MT         0x00000200      /* */
+#define SIO_IR_SB_RX_FULL       0x00000400      /* */
+#define SIO_IR_SB_RX_HIGH       0x00000800      /* */
+#define SIO_IR_SB_RX_TIMER      0x00001000      /* */
+#define SIO_IR_SB_DELTA_DCD     0x00002000      /* */
+#define SIO_IR_SB_DELTA_CTS     0x00004000      /* */
+#define SIO_IR_SB_INT           0x00008000      /* */
+#define SIO_IR_SB_TX_EXPLICIT   0x00010000      /* */
+#define SIO_IR_SB_MEMERR        0x00020000      /* */
+#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
+#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
+#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
+#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
+#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
+#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
+#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT    28
+
+/* per device interrupt masks */
+#define SIO_IR_SA               (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
+                                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
+                                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
+                                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
+                                 SIO_IR_SA_MEMERR)
+#define SIO_IR_SB               (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
+                                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
+                                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
+                                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
+                                 SIO_IR_SB_MEMERR)
+#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_SIO_RESET        0x00000001      /* reset the SIO */
+#define SIO_CR_SER_A_BASE       0x000000fe      /* DMA poll addr port A */
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE       0x00007f00      /* DMA poll addr port B */
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_SR_CMD_PULSE        0x00078000      /* byte bus strobe length */
+#define SIO_CR_CMD_PULSE_SHIFT  15
+#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA     0x00000000
+#define SIO_CR_ARB_DIAG_RXA     0x00080000
+#define SIO_CR_ARB_DIAG_TXB     0x00100000
+#define SIO_CR_ARB_DIAG_RXB     0x00180000
+#define SIO_CR_ARB_DIAG_PP      0x00200000
+#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
+
+/* bitmasks for INT_OUT */
+#define INT_OUT_COUNT   0x0000ffff      /* pulse interval timer */
+#define INT_OUT_MODE    0x00070000      /* mode mask */
+#define INT_OUT_MODE_0  0x00000000      /* set output to 0 */
+#define INT_OUT_MODE_1  0x00040000      /* set output to 1 */
+#define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
+#define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
+#define INT_OUT_MODE_SQW 0x00070000     /* toggle output every interval */
+#define INT_OUT_DIAG    0x40000000      /* diag mode */
+#define INT_OUT_INT_OUT 0x80000000      /* current state of INT_OUT */
+
+/* time constants for INT_OUT */
+#define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
+#define INT_OUT_TICKS_PER_PULSE 3       /* outgoing pulse lasts 3 ticks */
+#define INT_OUT_US_TO_COUNT(x)          /* convert uS to a count value */ \
+        (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *       \
+         100 / INT_OUT_NS_PER_TICK - 1)
+#define INT_OUT_COUNT_TO_US(x)          /* convert count value to uS */ \
+        (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
+#define INT_OUT_MIN_TICKS 3     /* min period is width of pulse in "ticks" */
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT         /* largest possible count */
+
+/* bitmasks for GPCR */
+#define GPCR_DIR        0x000000ff      /* tristate pin input or output */
+#define GPCR_DIR_PIN(x) (1<<(x))        /* access one of the DIR bits */
+#define GPCR_EDGE       0x000f0000      /* extint edge or level sensitive */
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
+
+/* values for GPCR */
+#define GPCR_INT_OUT_EN 0x00100000      /* enable INT_OUT to pin 0 */
+#define GPCR_MLAN_EN    0x00200000      /* enable MCR to pin 8 */
+#define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
+#define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
+#define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN      5       /* GIO pin cntrlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin cntrlling uart b mode sel */
+#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin cntrlling uart a mode sel */
+
+/* ethernet */
+#define EMCR_DUPLEX             0x00000001
+#define EMCR_PROMISC            0x00000002
+#define EMCR_PADEN              0x00000004
+#define EMCR_RXOFF_MASK         0x000001f8
+#define EMCR_RXOFF_SHIFT        3
+#define EMCR_RAMPAR             0x00000200
+#define EMCR_BADPAR             0x00000800
+#define EMCR_BUFSIZ             0x00001000
+#define EMCR_TXDMAEN            0x00002000
+#define EMCR_TXEN               0x00004000
+#define EMCR_RXDMAEN            0x00008000
+#define EMCR_RXEN               0x00010000
+#define EMCR_LOOPBACK           0x00020000
+#define EMCR_ARB_DIAG           0x001c0000
+#define EMCR_ARB_DIAG_IDLE      0x00200000
+#define EMCR_RST                0x80000000
+
+#define EISR_RXTIMERINT         0x00000001
+#define EISR_RXTHRESHINT        0x00000002
+#define EISR_RXOFLO             0x00000004
+#define EISR_RXBUFOFLO          0x00000008
+#define EISR_RXMEMERR           0x00000010
+#define EISR_RXPARERR           0x00000020
+#define EISR_TXEMPTY            0x00010000
+#define EISR_TXRTRY             0x00020000
+#define EISR_TXEXDEF            0x00040000
+#define EISR_TXLCOL             0x00080000
+#define EISR_TXGIANT            0x00100000
+#define EISR_TXBUFUFLO          0x00200000
+#define EISR_TXEXPLICIT         0x00400000
+#define EISR_TXCOLLWRAP         0x00800000
+#define EISR_TXDEFERWRAP        0x01000000
+#define EISR_TXMEMERR           0x02000000
+#define EISR_TXPARERR           0x04000000
+
+#define ERCSR_THRESH_MASK       0x000001ff      /* enet RX threshold */
+#define ERCSR_RX_TMR            0x40000000      /* simulation only */
+#define ERCSR_DIAG_OFLO         0x80000000      /* simulation only */
+
+#define ERBR_ALIGNMENT          4096
+#define ERBR_L_RXRINGBASE_MASK  0xfffff000
+
+#define ERBAR_BARRIER_BIT       0x0100
+#define ERBAR_RXBARR_MASK       0xffff0000
+#define ERBAR_RXBARR_SHIFT      16
+
+#define ERCIR_RXCONSUME_MASK    0x00000fff
+
+#define ERPIR_RXPRODUCE_MASK    0x00000fff
+#define ERPIR_ARM               0x80000000
+
+#define ERTR_CNT_MASK           0x000007ff
+
+#define ETCSR_IPGT_MASK         0x0000007f
+#define ETCSR_IPGR1_MASK        0x00007f00
+#define ETCSR_IPGR1_SHIFT       8
+#define ETCSR_IPGR2_MASK        0x007f0000
+#define ETCSR_IPGR2_SHIFT       16
+#define ETCSR_NOTXCLK           0x80000000
+
+#define ETCDC_COLLCNT_MASK      0x0000ffff
+#define ETCDC_DEFERCNT_MASK     0xffff0000
+#define ETCDC_DEFERCNT_SHIFT    16
+
+#define ETBR_ALIGNMENT          (64*1024)
+#define ETBR_L_RINGSZ_MASK      0x00000001
+#define ETBR_L_RINGSZ128        0
+#define ETBR_L_RINGSZ512        1
+#define ETBR_L_TXRINGBASE_MASK  0xffffc000
+
+#define ETCIR_TXCONSUME_MASK    0x0000ffff
+#define ETCIR_IDLE              0x80000000
+
+#define ETPIR_TXPRODUCE_MASK    0x0000ffff
+
+#define EBIR_TXBUFPROD_MASK     0x0000001f
+#define EBIR_TXBUFCONS_MASK     0x00001f00
+#define EBIR_TXBUFCONS_SHIFT    8
+#define EBIR_RXBUFPROD_MASK     0x007fc000
+#define EBIR_RXBUFPROD_SHIFT    14
+#define EBIR_RXBUFCONS_MASK     0xff800000
+#define EBIR_RXBUFCONS_SHIFT    23
+
+#define MICR_REGADDR_MASK       0x0000001f
+#define MICR_PHYADDR_MASK       0x000003e0
+#define MICR_PHYADDR_SHIFT      5
+#define MICR_READTRIG           0x00000400
+#define MICR_BUSY               0x00000800
+
+#define MIDR_DATA_MASK          0x0000ffff
+
+/* subsystem IDs supplied by card detection in pci-xtalk-bridge */
+#define IOC3_SUBSYS_IP27_BASEIO6G       0xc300
+#define IOC3_SUBSYS_IP27_MIO            0xc301
+#define IOC3_SUBSYS_IP27_BASEIO         0xc302
+#define IOC3_SUBSYS_IP29_SYSBOARD       0xc303
+#define IOC3_SUBSYS_IP30_SYSBOARD       0xc304
+#define IOC3_SUBSYS_MENET               0xc305
+#define IOC3_SUBSYS_MENET4              0xc306
+#define IOC3_SUBSYS_IO7                 0xc307
+#define IOC3_SUBSYS_IO8                 0xc308
+#define IOC3_SUBSYS_IO9                 0xc309
+#define IOC3_SUBSYS_IP34_SYSBOARD       0xc30A
+
+#endif /* MIPS_SN_IOC3_H */
diff --git a/arch/mips/include/asm/sn/irq_alloc.h b/arch/mips/include/asm/sn/irq_alloc.h
new file mode 100644
index 000000000..09b89cecf
--- /dev/null
+++ b/arch/mips/include/asm/sn/irq_alloc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_SN_IRQ_ALLOC_H
+#define __ASM_SN_IRQ_ALLOC_H
+
+struct irq_alloc_info {
+        void *ctrl;
+        nasid_t nasid;
+        int pin;
+};
+
+#endif /* __ASM_SN_IRQ_ALLOC_H */
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
new file mode 100644
index 000000000..117f85e4b
--- /dev/null
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -0,0 +1,894 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLCONFIG_H
+#define _ASM_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+/*
+ * WARNING:
+ *      Certain assembly language routines (notably xxxxx.s) in the IP27PROM
+ *      will depend on the format of the data structures in this file.  In
+ *      most cases, rearranging the fields can seriously break things.
+ *      Adding fields in the beginning or middle can also break things.
+ *      Add fields if necessary, to the end of a struct in such a way
+ *      that offsets of existing fields do not change.
+ */
+
+#include <linux/types.h>
+#include <asm/sn/types.h>
+
+#if defined(CONFIG_SGI_IP27)
+
+#include <asm/sn/sn0/addrs.h>
+//#include <sys/SN/router.h>
+// XXX Stolen from <sys/SN/router.h>:
+#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+#include <asm/sn/fru.h>
+//#include <sys/graph.h>
+//#include <sys/xtalk/xbow.h>
+
+#elif defined(CONFIG_SGI_IP35)
+
+#include <asm/sn/sn1/addrs.h>
+#include <sys/sn/router.h>
+#include <sys/graph.h>
+#include <asm/xtalk/xbow.h>
+
+#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
+#include <asm/sn/agent.h>
+#include <asm/fw/arc/types.h>
+#include <asm/fw/arc/hinv.h>
+#if defined(CONFIG_SGI_IP35)
+// The hack file has to be before vector and after sn0_fru....
+#include <asm/hack.h>
+#include <asm/sn/vector.h>
+#include <asm/xtalk/xtalk.h>
+#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
+
+typedef u64  nic_t;
+
+#define KLCFGINFO_MAGIC 0xbeedbabe
+
+typedef s32 klconf_off_t;
+
+/*
+ * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
+ */
+#define MAX_MODULE_ID           255
+#define SIZE_PAD                4096 /* 4k padding for structures */
+/*
+ * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
+ * 2 Midplanes assuming no pci card cages
+ */
+#define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
+
+/* XXX if each node is guaranteed to have some memory */
+
+#define MAX_PCI_DEVS            8
+
+/* lboard_t->brd_flags fields */
+/* All bits in this field are currently used. Try the pad fields if
+   you need more flag bits */
+
+#define ENABLE_BOARD            0x01
+#define FAILED_BOARD            0x02
+#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
+                                           are discovered twice. Use one of them */
+#define VISITED_BOARD           0x08    /* Used for compact hub numbering. */
+#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
+#define GLOBAL_MASTER_IO6       0x20
+#define THIRD_NIC_PRESENT       0x40    /* for future use */
+#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
+
+/* klinfo->flags fields */
+
+#define KLINFO_ENABLE           0x01    /* This component is enabled */
+#define KLINFO_FAILED           0x02    /* This component failed */
+#define KLINFO_DEVICE           0x04    /* This component is a device */
+#define KLINFO_VISITED          0x08    /* This component has been visited */
+#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
+#define KLINFO_INSTALL          0x20    /* Install a driver */
+#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
+#define IS_CONSOLE_IOC3(i)      ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
+
+#define GB2             0x80000000
+
+#define MAX_RSV_PTRS    32
+
+/* Structures to manage various data storage areas */
+/* The numbers must be contiguous since the array index i
+   is used in the code to allocate various areas.
+*/
+
+#define BOARD_STRUCT            0
+#define COMPONENT_STRUCT        1
+#define ERRINFO_STRUCT          2
+#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT           3
+
+
+typedef struct console_s {
+        unsigned long   uart_base;
+        unsigned long   config_base;
+        unsigned long   memory_base;
+        short           baud;
+        short           flag;
+        int             type;
+        nasid_t         nasid;
+        char            wid;
+        char            npci;
+        nic_t           baseio_nic;
+} console_t;
+
+typedef struct klc_malloc_hdr {
+        klconf_off_t km_base;
+        klconf_off_t km_limit;
+        klconf_off_t km_current;
+} klc_malloc_hdr_t;
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
+        u32             ch_version;    /* structure version number */
+        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
+        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
+        klconf_off_t    ch_board_info;  /* the link list of boards */
+        console_t       ch_cons_info;   /* address info of the console */
+        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
+        confidence_t    ch_sw_belief;   /* confidence that software is bad*/
+        confidence_t    ch_sn0net_belief; /* confidence that sn0net is bad */
+} kl_config_hdr_t;
+
+
+#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#define KL_CONFIG_INFO_OFFSET(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                         \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+
+#define KL_CONFIG_INFO(_nasid)                                          \
+        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
+         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
+         0)
+#define KL_CONFIG_MAGIC(_nasid)         (KL_CONFIG_HDR(_nasid)->ch_magic)
+
+#define KL_CONFIG_CHECK_MAGIC(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+
+#define KL_CONFIG_HDR_INIT_MAGIC(_nasid)        \
+                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+
+/* --- New Macros for the changed kl_config_hdr_t structure --- */
+
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
+
+#define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
+
+#define PTR_CH_CONS_INFO(_k)    ((console_t *)\
+                        ((unsigned long)_k + (_k->ch_cons_off)))
+
+#define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
+
+/* ------------------------------------------------------------- */
+
+#define KL_CONFIG_INFO_START(_nasid)    \
+        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+
+#define KL_CONFIG_BOARD_NASID(_brd)     ((_brd)->brd_nasid)
+#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)    ((_brd)->brd_next = (_off))
+
+#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
+
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link)  \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+
+#define XBOW_PORT_IO     0x1
+#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_ENABLE 0x4
+
+#define SN0_PORT_FENCE_SHFT     0
+#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
+ * First board info on the remote node. The remote node list is
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ *
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error
+ * information specific to the COMPONENT is present in the respective
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ *
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+/*
+ * Values for CPU types
+ */
+#define KL_CPU_R4000            0x1     /* Standard R4000 */
+#define KL_CPU_TFP              0x2     /* TFP processor */
+#define KL_CPU_R10000           0x3     /* R10000 (T5) */
+#define KL_CPU_NONE             (-1)    /* no cpu present in slot */
+
+/*
+ * IP27 BOARD classes
+ */
+
+#define KLCLASS_MASK    0xf0
+#define KLCLASS_NONE    0x00
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU     KLCLASS_NODE
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
+                                            and the non-graphics widget boards */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_GFX     0x50            /* graphics boards */
+
+#define KLCLASS_PSEUDO_GFX      0x60    /* HDTV type cards that use a gfx
+                                         * hw ifc to xtalk and are not gfx
+                                         * class for sw purposes */
+
+#define KLCLASS_MAX     7               /* Bump this if a new CLASS is added */
+#define KLTYPE_MAX      10              /* Bump this if a new CLASS is added */
+
+#define KLCLASS_UNKNOWN 0xf0
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+/*
+ * IP27 board types
+ */
+
+#define KLTYPE_MASK     0x0f
+#define KLTYPE_NONE     0x00
+#define KLTYPE_EMPTY    0x00
+
+#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
+#define KLTYPE_IP27     (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
+
+#define KLTYPE_WEIRDIO  (KLCLASS_IO  | 0x0)
+#define KLTYPE_BASEIO   (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
+#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_4CHSCSI  (KLCLASS_IO  | 0x2)
+#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
+#define KLTYPE_UNUSED   (KLCLASS_IO  | 0x5) /* XXX UNUSED */
+#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_PCI      KLTYPE_HAROLD
+#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
+#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+
+#define KLTYPE_GFX      (KLCLASS_GFX | 0x0) /* unknown graphics type */
+#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
+#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
+
+#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
+#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+
+#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
+#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
+#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_PBRICK_XBOW      (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_IBRICK           (KLCLASS_IOBRICK | 0x1)
+#define KLTYPE_PBRICK           (KLCLASS_IOBRICK | 0x2)
+#define KLTYPE_XBRICK           (KLCLASS_IOBRICK | 0x3)
+
+#define KLTYPE_PBRICK_BRIDGE    KLTYPE_PBRICK
+
+/* The value of type should be more than 8 so that hinv prints
+ * out the board name from the NIC string. For values less than
+ * 8 the name of the board needs to be hard coded in a few places.
+ * When bringup started nic names had not standardized and so we
+ * had to hard code. (For people interested in history.)
+ */
+#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
+
+#define KLTYPE_UNKNOWN  (KLCLASS_UNKNOWN | 0xf)
+
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+#define IS_MIO_PRESENT(l)       ((l->brd_type == KLTYPE_BASEIO) && \
+                                 (l->brd_flags & SECOND_NIC_PRESENT))
+#define IS_MIO_IOC3(l, n)       (IS_MIO_PRESENT(l) && (n > 2))
+
+/*
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+#define LOCAL_BOARD 1
+#define REMOTE_BOARD 2
+
+#define LBOARD_STRUCT_VERSION   2
+
+typedef struct lboard_s {
+        klconf_off_t    brd_next;         /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        moduleid_t      brd_module;       /* module to which it belongs */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
+        struct lboard_s *brd_parent;      /* Logical parent for this brd */
+        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
+        confidence_t    brd_confidence;   /* confidence that the board is bad */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        char            brd_name[32];
+} lboard_t;
+
+
+/*
+ *      Make sure we pass back the calias space address for local boards.
+ *      klconfig board traversal and error structure extraction defines.
+ */
+
+#define BOARD_SLOT(_brd)        ((_brd)->brd_slot)
+
+#define KLCF_CLASS(_brd)        KLCLASS((_brd)->brd_type)
+#define KLCF_TYPE(_brd)         KLTYPE((_brd)->brd_type)
+#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
+#define KLCF_MODULE_ID(_brd)    ((_brd)->brd_module)
+
+#define KLCF_NEXT(_brd)         \
+        ((_brd)->brd_next ?     \
+         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
+         NULL)
+#define KLCF_COMP(_brd, _ndx)   \
+                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
+                                               (_brd)->brd_compts[(_ndx)]))
+
+#define KLCF_COMP_ERROR(_brd, _comp)    \
+               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+
+#define KLCF_COMP_TYPE(_comp)   ((_comp)->struct_type)
+#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
+
+
+
+/*
+ * Generic info structure. This stores common info about a
+ * component.
+ */
+
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
+        char            pad1;             /* pad out structure. */
+        char            pad2;             /* pad out structure. */
+        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+#define KLCONFIG_INFO_ENABLED(_i)       ((_i)->flags & KLINFO_ENABLE)
+/*
+ * Component structures.
+ * Following are the currently identified components:
+ *      CPU, HUB, MEM_BANK,
+ *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
+ *      ROUTER
+ *      GRAPHICS
+ */
+#define KLSTRUCT_UNKNOWN        0
+#define KLSTRUCT_CPU            1
+#define KLSTRUCT_HUB            2
+#define KLSTRUCT_MEMBNK         3
+#define KLSTRUCT_XBOW           4
+#define KLSTRUCT_BRI            5
+#define KLSTRUCT_IOC3           6
+#define KLSTRUCT_PCI            7
+#define KLSTRUCT_VME            8
+#define KLSTRUCT_ROU            9
+#define KLSTRUCT_GFX            10
+#define KLSTRUCT_SCSI           11
+#define KLSTRUCT_FDDI           12
+#define KLSTRUCT_MIO            13
+#define KLSTRUCT_DISK           14
+#define KLSTRUCT_TAPE           15
+#define KLSTRUCT_CDROM          16
+#define KLSTRUCT_HUB_UART       17
+#define KLSTRUCT_IOC3ENET       18
+#define KLSTRUCT_IOC3UART       19
+#define KLSTRUCT_UNUSED         20 /* XXX UNUSED */
+#define KLSTRUCT_IOC3PCKM       21
+#define KLSTRUCT_RAD            22
+#define KLSTRUCT_HUB_TTY        23
+#define KLSTRUCT_IOC3_TTY       24
+
+/* Early Access IO proms are compatible
+   only with KLSTRUCT values up to 24. */
+
+#define KLSTRUCT_FIBERCHANNEL   25
+#define KLSTRUCT_MOD_SERIAL_NUM 26
+#define KLSTRUCT_IOC3MS         27
+#define KLSTRUCT_TPU            28
+#define KLSTRUCT_GSN_A          29
+#define KLSTRUCT_GSN_B          30
+#define KLSTRUCT_XTHD           31
+
+/*
+ * These are the indices of various components within a lboard structure.
+ */
+
+#define IP27_CPU0_INDEX 0
+#define IP27_CPU1_INDEX 1
+#define IP27_HUB_INDEX 2
+#define IP27_MEM_INDEX 3
+
+#define BASEIO_BRIDGE_INDEX 0
+#define BASEIO_IOC3_INDEX 1
+#define BASEIO_SCSI1_INDEX 2
+#define BASEIO_SCSI2_INDEX 3
+
+#define MIDPLANE_XBOW_INDEX 0
+#define ROUTER_COMPONENT_INDEX 0
+
+#define CH4SCSI_BRIDGE_INDEX 0
+
+/* Info holders for various hardware components */
+
+typedef u64 *pci_t;
+typedef u64 *vmeb_t;
+typedef u64 *vmed_t;
+typedef u64 *fddi_t;
+typedef u64 *scsi_t;
+typedef u64 *mio_t;
+typedef u64 *graphics_t;
+typedef u64 *router_t;
+
+/*
+ * The port info in ip27_cfg area translates to a lboart_t in the
+ * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
+ * is stored in terms of a nasid and a offset from start of KLCONFIG
+ * area  on that nasid.
+ */
+typedef struct klport_s {
+        nasid_t         port_nasid;
+        unsigned char   port_flag;
+        klconf_off_t    port_offset;
+} klport_t;
+
+typedef struct klcpu_s {                          /* CPU */
+        klinfo_t        cpu_info;
+        unsigned short  cpu_prid;       /* Processor PRID value */
+        unsigned short  cpu_fpirr;      /* FPU IRR value */
+        unsigned short  cpu_speed;      /* Speed in MHZ */
+        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
+        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
+} klcpu_t ;
+
+#define CPU_STRUCT_VERSION   2
+
+typedef struct klhub_s {                        /* HUB */
+        klinfo_t        hub_info;
+        unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
+        klport_t        hub_port;               /* hub is connected to this */
+        nic_t           hub_box_nic;            /* nic of containing box */
+        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
+        u64             hub_speed;              /* Speed of hub in HZ */
+} klhub_t ;
+
+typedef struct klhub_uart_s {                   /* HUB */
+        klinfo_t        hubuart_info;
+        unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
+        nic_t           hubuart_box_nic;        /* nic of containing box */
+} klhub_uart_t ;
+
+#define MEMORY_STRUCT_VERSION   2
+
+typedef struct klmembnk_s {                     /* MEMORY BANK */
+        klinfo_t        membnk_info;
+        short           membnk_memsz;           /* Total memory in megabytes */
+        short           membnk_dimm_select; /* bank to physical addr mapping*/
+        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
+        short           membnk_attr;
+} klmembnk_t ;
+
+#define KLCONFIG_MEMBNK_SIZE(_info, _bank)      \
+                            ((_info)->membnk_bnksz[(_bank)])
+
+
+#define MEMBNK_PREMIUM 1
+#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)   \
+                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+
+#define MAX_SERIAL_NUM_SIZE 10
+
+typedef struct klmod_serial_num_s {
+      klinfo_t        snum_info;
+      union {
+              char snum_str[MAX_SERIAL_NUM_SIZE];
+              unsigned long long       snum_int;
+      } snum;
+} klmod_serial_num_t;
+
+/* Macros needed to access serial number structure in lboard_t.
+   Hard coded values are necessary since we cannot treat
+   serial number struct as a component without losing compatibility
+   between prom versions. */
+
+#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
+                                KLCF_COMP(_l, _l->brd_numcompts))
+
+#define MAX_XBOW_LINKS 16
+
+typedef struct klxbow_s {                          /* XBOW */
+        klinfo_t        xbow_info ;
+        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
+        int             xbow_master_hub_link;
+        /* type of brd connected+component struct ptr+flags */
+} klxbow_t ;
+
+#define MAX_PCI_SLOTS 8
+
+typedef struct klpci_device_s {
+        s32     pci_device_id;  /* 32 bits of vendor/device ID. */
+        s32     pci_device_pad; /* 32 bits of padding. */
+} klpci_device_t;
+
+#define BRIDGE_STRUCT_VERSION   2
+
+typedef struct klbri_s {                          /* BRIDGE */
+        klinfo_t        bri_info ;
+        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
+        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+        pci_t           pci_specific  ;    /* PCI Board config info */
+        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
+        klconf_off_t    bri_mfg_nic ;
+} klbri_t ;
+
+#define MAX_IOC3_TTY    2
+
+typedef struct klioc3_s {                          /* IOC3 */
+        klinfo_t        ioc3_info ;
+        unsigned char   ioc3_ssram ;        /* Info about ssram */
+        unsigned char   ioc3_nvram ;        /* Info about nvram */
+        klinfo_t        ioc3_superio ;      /* Info about superio */
+        klconf_off_t    ioc3_tty_off ;
+        klinfo_t        ioc3_enet ;
+        klconf_off_t    ioc3_enet_off ;
+        klconf_off_t    ioc3_kbd_off ;
+} klioc3_t ;
+
+#define MAX_VME_SLOTS 8
+
+typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
+        klinfo_t        vmeb_info ;
+        vmeb_t          vmeb_specific ;
+        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmeb_t ;
+
+typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+        klinfo_t        vmed_info ;
+        vmed_t          vmed_specific ;
+        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmed_t ;
+
+#define ROUTER_VECTOR_VERS      2
+
+/* XXX - Don't we need the number of ports here?!? */
+typedef struct klrou_s {                          /* ROUTER */
+        klinfo_t        rou_info ;
+        unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
+        nic_t           rou_box_nic ;         /* nic of the containing module */
+        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
+        u64     rou_vector;       /* vector from master node */
+} klrou_t ;
+
+/*
+ *  Graphics Controller/Device
+ *
+ *  (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
+ *  used a couple different structures to store graphics information.
+ *  For compatibility reasons, the newer data structure preserves some
+ *  of the layout so that fields that are used in the old versions remain
+ *  in the same place (with the same info).  Determination of what version
+ *  of this structure we have is done by checking the cookie field.
+ */
+#define KLGFX_COOKIE    0x0c0de000
+
+typedef struct klgfx_s {                /* GRAPHICS Device */
+        klinfo_t        gfx_info;
+        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
+        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
+        unsigned int            cookie;         /* for compatibility with older proms */
+        unsigned int            moduleslot;
+        struct klgfx_s  *gfx_next_pipe;
+        graphics_t      gfx_specific;
+        klconf_off_t    pad0;           /* for compatibility with older proms */
+        klconf_off_t    gfx_mfg_nic;
+} klgfx_t;
+
+typedef struct klxthd_s {
+        klinfo_t        xthd_info ;
+        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
+} klxthd_t ;
+
+typedef struct kltpu_s {                     /* TPU board */
+        klinfo_t        tpu_info ;
+        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
+} kltpu_t ;
+
+typedef struct klgsn_s {                     /* GSN board */
+        klinfo_t        gsn_info ;
+        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
+} klgsn_t ;
+
+#define MAX_SCSI_DEVS 16
+
+/*
+ * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
+ * to allocate space of type COMPONENT. Make sure that if the size of
+ * any other component struct becomes more than this, then redefine
+ * that as the size to be klmalloced.
+ */
+
+typedef struct klscsi_s {                          /* SCSI Controller */
+        klinfo_t        scsi_info ;
+        scsi_t          scsi_specific   ;
+        unsigned char   scsi_numdevs ;
+        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
+} klscsi_t ;
+
+typedef struct klscdev_s {                          /* SCSI device */
+        klinfo_t        scdev_info ;
+        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
+} klscdev_t ;
+
+typedef struct klttydev_s {                          /* TTY device */
+        klinfo_t        ttydev_info ;
+        struct terminal_data *ttydev_cfg ; /* driver fills up this */
+} klttydev_t ;
+
+typedef struct klenetdev_s {                          /* ENET device */
+        klinfo_t        enetdev_info ;
+        struct net_data *enetdev_cfg ; /* driver fills up this */
+} klenetdev_t ;
+
+typedef struct klkbddev_s {                          /* KBD device */
+        klinfo_t        kbddev_info ;
+        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
+} klkbddev_t ;
+
+typedef struct klmsdev_s {                          /* mouse device */
+        klinfo_t        msdev_info ;
+        void            *msdev_cfg ;
+} klmsdev_t ;
+
+#define MAX_FDDI_DEVS 10 /* XXX Is this true */
+
+typedef struct klfddi_s {                          /* FDDI */
+        klinfo_t        fddi_info ;
+        fddi_t          fddi_specific ;
+        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
+} klfddi_t ;
+
+typedef struct klmio_s {                          /* MIO */
+        klinfo_t        mio_info ;
+        mio_t           mio_specific   ;
+} klmio_t ;
+
+
+typedef union klcomp_s {
+        klcpu_t         kc_cpu;
+        klhub_t         kc_hub;
+        klmembnk_t      kc_mem;
+        klxbow_t        kc_xbow;
+        klbri_t         kc_bri;
+        klioc3_t        kc_ioc3;
+        klvmeb_t        kc_vmeb;
+        klvmed_t        kc_vmed;
+        klrou_t         kc_rou;
+        klgfx_t         kc_gfx;
+        klscsi_t        kc_scsi;
+        klscdev_t       kc_scsi_dev;
+        klfddi_t        kc_fddi;
+        klmio_t         kc_mio;
+        klmod_serial_num_t kc_snum ;
+} klcomp_t;
+
+typedef union kldev_s {      /* for device structure allocation */
+        klscdev_t       kc_scsi_dev ;
+        klttydev_t      kc_tty_dev ;
+        klenetdev_t     kc_enet_dev ;
+        klkbddev_t      kc_kbd_dev ;
+} kldev_t ;
+
+/* Data structure interface routines. TBD */
+
+/* Include launch info in this file itself? TBD */
+
+/*
+ * TBD - Can the ARCS and device driver related info also be included in the
+ * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
+ * structure, viz private to the IO4prom.
+ */
+
+/*
+ * TBD - Allocation issues.
+ *
+ * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
+ * errinfo and allocate from them, or have a single heap and allocate all
+ * structures from it. Debug is easier in the former method since we can
+ * dump all similar structs in one command, but there will be lots of holes,
+ * in memory and max limits are needed for number of structures.
+ * Another way to make it organized, is to have a union of all components
+ * and allocate a aligned chunk of memory greater than the biggest
+ * component.
+ */
+
+typedef union {
+        lboard_t *lbinfo ;
+} biptr_t ;
+
+
+#define BRI_PER_XBOW 6
+#define PCI_PER_BRI  8
+#define DEV_PER_PCI  16
+
+
+/* Virtual dipswitch values (starting from switch "7"): */
+
+#define VDS_NOGFX               0x8000  /* Don't enable gfx and autoboot */
+#define VDS_NOMP                0x100   /* Don't start slave processors */
+#define VDS_MANUMODE            0x80    /* Manufacturing mode */
+#define VDS_NOARB               0x40    /* No bootmaster arbitration */
+#define VDS_PODMODE             0x20    /* Go straight to POD mode */
+#define VDS_NO_DIAGS            0x10    /* Don't run any diags after BM arb */
+#define VDS_DEFAULTS            0x08    /* Use default environment values */
+#define VDS_NOMEMCLEAR          0x04    /* Don't run mem cfg code */
+#define VDS_2ND_IO4             0x02    /* Boot from the second IO4 */
+#define VDS_DEBUG_PROM          0x01    /* Print PROM debugging messages */
+
+/* external declarations of Linux kernel functions. */
+
+extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
+extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
+extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
+extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
+
+#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
new file mode 100644
index 000000000..245f59bf3
--- /dev/null
+++ b/arch/mips/include/asm/sn/kldir.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_SN_KLDIR_H
+#define _ASM_SN_KLDIR_H
+
+#define KLDIR_MAGIC             0x434d5f53505f5357
+
+#define KLDIR_OFF_MAGIC                 0x00
+#define KLDIR_OFF_OFFSET                0x08
+#define KLDIR_OFF_POINTER               0x10
+#define KLDIR_OFF_SIZE                  0x18
+#define KLDIR_OFF_COUNT                 0x20
+#define KLDIR_OFF_STRIDE                0x28
+
+#define KLDIR_ENT_SIZE                  0x40
+#define KLDIR_MAX_ENTRIES               (0x400 / 0x40)
+
+#ifndef __ASSEMBLY__
+typedef struct kldir_ent_s {
+        u64             magic;          /* Indicates validity of entry      */
+        off_t           offset;         /* Offset from start of node space  */
+        unsigned long   pointer;        /* Pointer to area in some cases    */
+        size_t          size;           /* Size in bytes                    */
+        u64             count;          /* Repeat count if array, 1 if not  */
+        size_t          stride;         /* Stride if array, 0 if not        */
+        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
+        /* NOTE: These 16 bytes are used in the Partition KLDIR
+           entry to store partition info. Refer to klpart.h for this. */
+} kldir_ent_t;
+#endif /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/sn0/kldir.h>
+#endif
+
+#endif /* _ASM_SN_KLDIR_H */
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
new file mode 100644
index 000000000..ea6b21795
--- /dev/null
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_KLKERNVARS_H
+#define __ASM_SN_KLKERNVARS_H
+
+#define KV_MAGIC_OFFSET         0x0
+#define KV_RO_NASID_OFFSET      0x4
+#define KV_RW_NASID_OFFSET      0x6
+
+#define KV_MAGIC                0x5f4b565f
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sn/types.h>
+
+typedef struct kern_vars_s {
+        int             kv_magic;
+        nasid_t         kv_ro_nasid;
+        nasid_t         kv_rw_nasid;
+        unsigned long   kv_ro_baseaddr;
+        unsigned long   kv_rw_baseaddr;
+} kern_vars_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_SN_KLKERNVARS_H */
diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h
new file mode 100644
index 000000000..04226d8d3
--- /dev/null
+++ b/arch/mips/include/asm/sn/launch.h
@@ -0,0 +1,106 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_LAUNCH_H
+#define _ASM_SN_LAUNCH_H
+
+#include <asm/sn/types.h>
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, then returns to the slave loop.  The master may poll or wait
+ * for the slaves to finish.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per local CPU.
+ */
+
+#define LAUNCH_MAGIC            0xaddbead2addbead3
+#ifdef CONFIG_SGI_IP27
+#define LAUNCH_SIZEOF           0x100
+#define LAUNCH_PADSZ            0xa0
+#endif
+
+#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
+#define LAUNCH_OFF_BUSY         0x08
+#define LAUNCH_OFF_CALL         0x10
+#define LAUNCH_OFF_CALLC        0x18
+#define LAUNCH_OFF_CALLPARM     0x20
+#define LAUNCH_OFF_STACK        0x28
+#define LAUNCH_OFF_GP           0x30
+#define LAUNCH_OFF_BEVUTLB      0x38
+#define LAUNCH_OFF_BEVNORMAL    0x40
+#define LAUNCH_OFF_BEVECC       0x48
+
+#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
+#define LAUNCH_STATE_SENT       1
+#define LAUNCH_STATE_RECD       2
+
+/*
+ * The launch routine is called only if the complement address is correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ * The slave_launch routine turns on the BUSY flag, and the slave loop
+ * clears the BUSY flag after control is returned to it.
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef int launch_state_t;
+typedef void (*launch_proc_t)(u64 call_parm);
+
+typedef struct launch_s {
+        volatile u64            magic;  /* Magic number                     */
+        volatile u64            busy;   /* Slave currently active           */
+        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
+        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
+        volatile u64            call_parm;      /* Single parm passed to call*/
+        volatile void *stack_addr;      /* Stack pointer for slave function */
+        volatile void *gp_addr;         /* Global pointer for slave func.   */
+        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
+        volatile char           *bevnormal;/*Address of bev normal ex handler */
+        volatile char           *bevecc;/* Address of bev cache err handler */
+        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
+} launch_t;
+
+/*
+ * PROM entry points for launch routines are determined by IPxxprom/start.s
+ */
+
+#define LAUNCH_SLAVE    (*(void (*)(int nasid, int cpu, \
+                                    launch_proc_t call_addr, \
+                                    u64 call_parm, \
+                                    void *stack_addr, \
+                                    void *gp_addr)) \
+                         IP27PROM_LAUNCHSLAVE)
+
+#define LAUNCH_WAIT     (*(void (*)(int nasid, int cpu, int timeout_msec)) \
+                         IP27PROM_WAITSLAVE)
+
+#define LAUNCH_POLL     (*(launch_state_t (*)(int nasid, int cpu)) \
+                         IP27PROM_POLLSLAVE)
+
+#define LAUNCH_LOOP     (*(void (*)(void)) \
+                         IP27PROM_SLAVELOOP)
+
+#define LAUNCH_FLASH    (*(void (*)(void)) \
+                         IP27PROM_FLASHLEDS)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SN_LAUNCH_H */
diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
new file mode 100644
index 000000000..3f1049807
--- /dev/null
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * File created by Kanoj Sarcar 06/06/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_MAPPED_KERNEL_H
+#define __ASM_SN_MAPPED_KERNEL_H
+
+#include <linux/mmzone.h>
+
+/*
+ * Note on how mapped kernels work: the text and data section is
+ * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
+ * init/setup/data section gets a 16M virtual address bump in the
+ * ld.script file (so that tlblo0 and tlblo1 maps the sections).
+ * The vmlinux.64 section addresses are put in the xkseg range
+ * using the change-addresses makefile option. Use elfdump -of
+ * on IRIX to see where the sections go. The Origin loader loads
+ * the two sections contiguously in physical memory. The loader
+ * sets the entry point into kernel_entry using a xkphys address,
+ * but instead of using 0xa800000001160000, it uses the address
+ * 0xa800000000160000, which is where it physically loaded that
+ * code. So no jumps can be done before we have switched to using
+ * cksseg addresses.
+ */
+#include <asm/addrspace.h>
+
+#define REP_BASE        CAC_BASE
+
+#ifdef CONFIG_MAPPED_KERNEL
+
+#define MAPPED_ADDR_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_ADDR_RW_TO_PHYS(x)       (x - REP_BASE - 16777216)
+
+#define MAPPED_KERN_RO_PHYSBASE(n) (hub_data(n)->kern_vars.kv_ro_baseaddr)
+#define MAPPED_KERN_RW_PHYSBASE(n) (hub_data(n)->kern_vars.kv_rw_baseaddr)
+
+#define MAPPED_KERN_RO_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
+                                MAPPED_KERN_RO_PHYSBASE(get_nasid()))
+#define MAPPED_KERN_RW_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
+                                MAPPED_KERN_RW_PHYSBASE(get_nasid()))
+
+#else /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_KERN_RW_TO_PHYS(x)       (x - REP_BASE)
+
+#endif /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
+#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
+
+#endif /* __ASM_SN_MAPPED_KERNEL_H  */
diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
new file mode 100644
index 000000000..12ac210f1
--- /dev/null
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -0,0 +1,125 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/nmi.h>, Revision 1.5.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_NMI_H
+#define __ASM_SN_NMI_H
+
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, followed by an optional rendezvous function, then returns to
+ * the slave loop.  The master does not wait for the slaves before
+ * returning.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per CPU.
+ */
+
+#define NMI_MAGIC               0x48414d4d455201
+#define NMI_SIZEOF              0x40
+
+#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
+#define NMI_OFF_FLAGS           0x08
+#define NMI_OFF_CALL            0x10
+#define NMI_OFF_CALLC           0x18
+#define NMI_OFF_CALLPARM        0x20
+#define NMI_OFF_GMASTER         0x28
+
+/*
+ * The NMI routine is called only if the complement address is
+ * correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct nmi_s {
+        volatile unsigned long   magic;         /* Magic number */
+        volatile unsigned long   flags;         /* Combination of flags above */
+        volatile void *call_addr;       /* Routine for slave to call        */
+        volatile void *call_addr_c;     /* 1's complement of address        */
+        volatile void *call_parm;       /* Single parm passed to call       */
+        volatile unsigned long   gmaster;       /* Flag true only on global master*/
+} nmi_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/* Following definitions are needed both in the prom & the kernel
+ * to identify the format of the nmi cpu register save area in the
+ * low memory on each node.
+ */
+#ifndef __ASSEMBLY__
+
+struct reg_struct {
+        unsigned long   gpr[32];
+        unsigned long   sr;
+        unsigned long   cause;
+        unsigned long   epc;
+        unsigned long   badva;
+        unsigned long   error_epc;
+        unsigned long   cache_err;
+        unsigned long   nmi_sr;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+/* These are the assembly language offsets into the reg_struct structure */
+
+#define R0_OFF          0x0
+#define R1_OFF          0x8
+#define R2_OFF          0x10
+#define R3_OFF          0x18
+#define R4_OFF          0x20
+#define R5_OFF          0x28
+#define R6_OFF          0x30
+#define R7_OFF          0x38
+#define R8_OFF          0x40
+#define R9_OFF          0x48
+#define R10_OFF         0x50
+#define R11_OFF         0x58
+#define R12_OFF         0x60
+#define R13_OFF         0x68
+#define R14_OFF         0x70
+#define R15_OFF         0x78
+#define R16_OFF         0x80
+#define R17_OFF         0x88
+#define R18_OFF         0x90
+#define R19_OFF         0x98
+#define R20_OFF         0xa0
+#define R21_OFF         0xa8
+#define R22_OFF         0xb0
+#define R23_OFF         0xb8
+#define R24_OFF         0xc0
+#define R25_OFF         0xc8
+#define R26_OFF         0xd0
+#define R27_OFF         0xd8
+#define R28_OFF         0xe0
+#define R29_OFF         0xe8
+#define R30_OFF         0xf0
+#define R31_OFF         0xf8
+#define SR_OFF          0x100
+#define CAUSE_OFF       0x108
+#define EPC_OFF         0x110
+#define BADVA_OFF       0x118
+#define ERROR_EPC_OFF   0x120
+#define CACHE_ERR_OFF   0x128
+#define NMISR_OFF       0x130
+
+#endif /* __ASM_SN_NMI_H */
diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
new file mode 100644
index 000000000..f13df84ed
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -0,0 +1,283 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_ADDRS_H
+#define _ASM_SN_SN0_ADDRS_H
+
+
+/*
+ * SN0 (on a T5) Address map
+ *
+ * This file contains a set of definitions and macros which are used
+ * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
+ * and UNCAC) used by the SN0 architecture.  It also contains addresses
+ * for "major" statically locatable PROM/Kernel data structures, such as
+ * the partition table, the configuration data structure, etc.
+ * We make an implicit assumption that the processor using this file
+ * follows the R10K's provisions for specifying uncached attributes;
+ * should this change, the base registers may very well become processor-
+ * dependent.
+ *
+ * For more information on the address spaces, see the "Local Resources"
+ * chapter of the Hub specification.
+ *
+ * NOTE: This header file is included both by C and by assembler source
+ *       files.  Please bracket any language-dependent definitions
+ *       appropriately.
+ */
+
+/*
+ * Some of the macros here need to be casted to appropriate types when used
+ * from C.  They definitely must not be casted from assembly language so we
+ * use some new ANSI preprocessor stuff to paste these on where needed.
+ */
+
+/*
+ * The following couple of definitions will eventually need to be variables,
+ * since the amount of address space assigned to each node depends on
+ * whether the system is running in N-mode (more nodes with less memory)
+ * or M-mode (fewer nodes with more memory).  We expect that it will
+ * be a while before we need to make this decision dynamically, though,
+ * so for now we just use defines bracketed by an ifdef.
+ */
+
+#ifdef CONFIG_SGI_SN_N_MODE
+
+#define NODE_SIZE_BITS          31
+#define BWIN_SIZE_BITS          28
+
+#define NASID_BITS              9
+#define NASID_BITMASK           (0x1ffLL)
+#define NASID_SHFT              31
+#define NASID_META_BITS         5
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
+
+#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
+
+#define NODE_SIZE_BITS          32
+#define BWIN_SIZE_BITS          29
+
+#define NASID_BITMASK           (0xffLL)
+#define NASID_BITS              8
+#define NASID_SHFT              32
+#define NASID_META_BITS         4
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
+
+#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#if !defined(__ASSEMBLY__)
+
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else /* __ASSEMBLY__ */
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN0.
+ *      CALIAS -- Varies in size, points to the first n bytes of memory
+ *                      on the reader's node.
+ */
+
+#define CALIAS_BASE             CAC_BASE
+
+#define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
+
+/* Turn on sable logging for the processors whose bits are set. */
+#define SABLE_LOG_TRIGGER(_map)
+
+#ifndef __ASSEMBLY__
+#define KERN_NMI_ADDR(nasid, slice)                                     \
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
+                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
+#endif /* !__ASSEMBLY__ */
+
+#ifdef PROM
+
+#define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
+#define MISC_PROM_SIZE          0x200000
+
+#define DIAG_BASE               PHYS_TO_K0(0x01500000)
+#define DIAG_SIZE               0x300000
+
+#define ROUTE_BASE              PHYS_TO_K0(0x01800000)
+#define ROUTE_SIZE              0x200000
+
+#define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
+#define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
+#define IP27PROM_CORP_MAX       32
+#define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
+#define IP27PROM_CORP_SIZE      0x10000
+#define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
+#define IP27PROM_CORP_STKSIZE   0x2000
+#define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
+#define IP27PROM_DECOMP_SIZE    0xfff00
+
+#define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
+#define IP27PROM_BASE_MAPPED    (UNCAC_BASE | 0x1fc00000)
+#define IP27PROM_SIZE_MAX       0x100000
+
+#define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
+#define IP27PROM_PCFG_SIZE      0xd0000
+#define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_ERRDMP_SIZE    0xf000
+
+#define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
+#define IP27PROM_CONSOLE_SIZE   0x200
+#define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
+#define IP27PROM_NETUART_SIZE   0x100
+#define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
+#define IP27PROM_UNUSED1_SIZE   0x500
+#define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
+#define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
+#define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
+#define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
+#define IP27PROM_STACK_SHFT     16
+#define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
+#define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
+
+#define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
+#define SLAVESTACK_SIZE         0x40000
+
+#define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
+#define ENETBUFS_SIZE           0x20000
+
+#define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
+#define IO6PROM_SIZE            0x400000
+#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
+#define IO6DPROM_SIZE           0x200000
+
+#define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
+#define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
+
+#define IP27PROM_INT_LAUNCH     10      /* and 11 */
+#define IP27PROM_INT_NETUART    12      /* through 17 */
+
+#endif /* PROM */
+
+/*
+ * needed by symmon so it needs to be outside #if PROM
+ */
+#define IP27PROM_ELSC_SHFT      10
+#define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
+
+/*
+ * This address is used by IO6PROM to build MemoryDescriptors of
+ * free memory. This address is important since unix gets loaded
+ * at this address, and this memory has to be FREE if unix is to
+ * be loaded.
+ */
+
+#define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
+
+#define IO6PROM_STACK_SHFT      14      /* stack per cpu */
+#define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
+
+/*
+ * IP27 PROM vectors
+ */
+
+#define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
+#define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
+#define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
+#define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
+#define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
+#define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
+#define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
+#define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
+#define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
+#define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
+
+#define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
+#define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
+#define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
+#define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
+
+#ifndef __ASSEMBLY__
+
+/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
+ * CACHE_ERR_SP_PTR could either contain an address to the stack, or
+ * the stack could start at CACHE_ERR_SP_PTR
+ */
+#if defined(HUB_ERR_STS_WAR)
+#define CACHE_ERR_EFRAME        0x480
+#else /* HUB_ERR_STS_WAR */
+#define CACHE_ERR_EFRAME        0x400
+#endif /* HUB_ERR_STS_WAR */
+
+#define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
+#define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
+#define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
+#define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
+#define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
+
+#endif  /* !__ASSEMBLY__ */
+
+#define _ARCSPROM
+
+#if defined(HUB_ERR_STS_WAR)
+
+#define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
+#define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
+#define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
+                                /* Used to match addr in error reg. */
+#define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
+
+#endif /* HUB_ERR_STS_WAR */
+
+#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
new file mode 100644
index 000000000..12f4c4649
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/arch.h
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI IP27 specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_ARCH_H
+#define _ASM_SN_SN0_ARCH_H
+
+
+/*
+ * MAXCPUS refers to the maximum number of CPUs in a single kernel.
+ * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
+ */
+#define MAXCPUS                 (MAX_NUMNODES * CPUS_PER_NODE)
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              256
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define MAX_REGIONS             64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS          MAX_REGIONS
+
+#define NASID_MASK_BYTES        ((MAX_NASIDS + 7) / 8)
+
+/*
+ * Slot constants for SN0
+ */
+#ifdef CONFIG_SGI_SN_N_MODE
+#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
+#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#endif /* CONFIG_SGI_SN_M_MODE */
+
+#define SLOT_SHIFT              (27)
+#define SLOT_MIN_MEM_SIZE       (32*1024*1024)
+
+#define CPUS_PER_NODE           2       /* CPUs on a single hub */
+
+#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
new file mode 100644
index 000000000..c84adde36
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hub.h
@@ -0,0 +1,62 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUB_H
+#define _ASM_SN_SN0_HUB_H
+
+/* The secret password; used to release protection */
+#define HUB_PASSWORD            0x53474972756c6573ull
+
+#define CHIPID_HUB              0
+#define CHIPID_ROUTER           1
+
+#define HUB_REV_1_0             1
+#define HUB_REV_2_0             2
+#define HUB_REV_2_1             3
+#define HUB_REV_2_2             4
+#define HUB_REV_2_3             5
+#define HUB_REV_2_4             6
+
+#define MAX_HUB_PATH            80
+
+#include <asm/sn/sn0/addrs.h>
+#include <asm/sn/sn0/hubpi.h>
+#include <asm/sn/sn0/hubmd.h>
+#include <asm/sn/sn0/hubio.h>
+#include <asm/sn/sn0/hubni.h>
+//#include <asm/sn/sn0/hubcore.h>
+
+/* Translation of uncached attributes */
+#define UATTR_HSPEC     0
+#define UATTR_IO        1
+#define UATTR_MSPEC     2
+#define UATTR_UNCAC     3
+
+#ifdef __ASSEMBLY__
+/*
+ * Returns the local nasid into res.
+ */
+        .macro GET_NASID_ASM res
+        dli     \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+        ld      \res, (\res)
+        and     \res, NSRI_NODEID_MASK
+        dsrl    \res, NSRI_NODEID_SHFT
+        .endm
+#else
+
+/*
+ * get_nasid() returns the physical node id number of the caller.
+ */
+static inline nasid_t get_nasid(void)
+{
+        return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK)
+                         >> NSRI_NODEID_SHFT);
+}
+#endif
+
+#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
new file mode 100644
index 000000000..57ece90f8
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -0,0 +1,972 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * In general, the longer software name should be used when available.
+ */
+
+/*
+ * Slightly friendlier names for some common registers.
+ * The hardware definitions follow.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
+#define IIO_WIDGET_FLUSH        IIO_WTFR     /* Widget target flush */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/*
+ * The following definitions use the names defined in the IO interface
+ * document for ease of reference.  When possible, software should
+ * generally use the longer but clearer names defined above.
+ */
+
+#define IIO_BASE        0x400000
+#define IIO_BASE_BTE0   0x410000
+#define IIO_BASE_BTE1   0x420000
+#define IIO_BASE_PERF   0x430000
+#define IIO_PERF_CNT    0x430008
+
+#define IO_PERF_SETS    32
+
+#define IIO_WID         0x400000        /* Widget identification */
+#define IIO_WSTAT       0x400008        /* Widget status */
+#define IIO_WCR         0x400020        /* Widget control */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+#define IIO_ILAPR       0x400100        /* Local Access Protection */
+#define IIO_ILAPO       0x400108        /* Protection override */
+#define IIO_IOWA        0x400110        /* outbound widget access */
+#define IIO_IIWA        0x400118        /* inbound widget access */
+#define IIO_IIDEM       0x400120        /* Inbound Device Error Mask */
+#define IIO_ILCSR       0x400128        /* LLP control and status */
+#define IIO_ILLR        0x400130        /* LLP Log */
+#define IIO_IIDSR       0x400138        /* Interrupt destination */
+
+#define IIO_IIBUSERR    0x1400208       /* Reads here cause a bus error. */
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000003f
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_0      0x400140        /* gfx node/widget register 0 */
+#define IIO_IGFX_1      0x400148        /* gfx node/widget register 1 */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_N_NUM_BITS     9       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    4
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_VLD_BITS       1       /* size of valid field */
+#define IIO_IGFX_VLD_MASK       ((1<<IIO_IGFX_VLD_BITS)-1)
+#define IIO_IGFX_VLD_SHIFT      20
+#define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+
+/* Scratch registers (not all bits available) */
+#define IIO_SCRATCH_REG0        0x400150
+#define IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_MASK        0x0000000f00f11fff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000800000000
+#define IIO_SCRATCH_BIT0_1      0x0000000400000000
+#define IIO_SCRATCH_BIT0_2      0x0000000200000000
+#define IIO_SCRATCH_BIT0_3      0x0000000100000000
+#define IIO_SCRATCH_BIT0_4      0x0000000000800000
+#define IIO_SCRATCH_BIT0_5      0x0000000000400000
+#define IIO_SCRATCH_BIT0_6      0x0000000000200000
+#define IIO_SCRATCH_BIT0_7      0x0000000000100000
+#define IIO_SCRATCH_BIT0_8      0x0000000000010000
+#define IIO_SCRATCH_BIT0_9      0x0000000000001000
+#define IIO_SCRATCH_BIT0_R      0x0000000000000fff
+
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the hub, we've
+ * redefined big window 7 as small window 0.
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+/*
+ * The IO LLP control status register and widget control register
+ */
+#ifndef __ASSEMBLY__
+
+typedef union hubii_wid_u {
+        u64     wid_reg_value;
+        struct {
+                u64     wid_rsvd:       32,     /* unused */
+                        wid_rev_num:     4,     /* revision number */
+                        wid_part_num:   16,     /* the widget type: hub=c101 */
+                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
+                        wid_rsvd1:       1;     /* Reserved */
+        } wid_fields_s;
+} hubii_wid_t;
+
+
+typedef union hubii_wcr_u {
+        u64     wcr_reg_value;
+        struct {
+                u64     wcr_rsvd:       41,     /* unused */
+                        wcr_e_thresh:    5,     /* elasticity threshold */
+                        wcr_dir_con:     1,     /* widget direct connect */
+                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
+                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
+                        wcr_rsvd1:       8,     /* Reserved */
+                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_widget_id:   4;     /* LLP crossbar credit */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+typedef union hubii_wstat_u {
+        u64      reg_value;
+        struct {
+                u64     rsvd1:          31,
+                        crazy:           1,     /* Crazy bit            */
+                        rsvd2:           8,
+                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                        rsvd3:           6,
+                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
+                        rsvd4:           2,
+                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
+                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                        pending:         4;     /* Pending Requests     */
+        } wstat_fields_s;
+} hubii_wstat_t;
+
+
+typedef union hubii_ilcsr_u {
+        u64     icsr_reg_value;
+        struct {
+                u64     icsr_rsvd:      22,     /* unused */
+                        icsr_max_burst: 10,     /* max burst */
+                        icsr_rsvd4:      6,     /* reserved */
+                        icsr_max_retry: 10,     /* max retry */
+                        icsr_rsvd3:      2,     /* reserved */
+                        icsr_lnk_stat:   2,     /* link status */
+                        icsr_bm8:        1,     /* Bit mode 8 */
+                        icsr_llp_en:     1,     /* LLP enable bit */
+                        icsr_rsvd2:      1,     /* reserver */
+                        icsr_wrm_reset:  1,     /* Warm reset bit */
+                        icsr_rsvd1:      2,     /* Data ready offset */
+                        icsr_null_to:    6;     /* Null timeout   */
+
+        } icsr_fields_s;
+} hubii_ilcsr_t;
+
+
+typedef union hubii_iowa_u {
+        u64     iowa_reg_value;
+        struct {
+                u64     iowa_rsvd:      48,     /* unused */
+                        iowa_wxoac:      8,     /* xtalk widget access bits */
+                        iowa_rsvd1:      7,     /* xtalk widget access bits */
+                        iowa_w0oac:      1;     /* xtalk widget access bits */
+        } iowa_fields_s;
+} hubii_iowa_t;
+
+typedef union hubii_iiwa_u {
+        u64     iiwa_reg_value;
+        struct {
+                u64     iiwa_rsvd:      48,     /* unused */
+                        iiwa_wxiac:      8,     /* hub wid access bits */
+                        iiwa_rsvd1:      7,     /* reserved */
+                        iiwa_w0iac:      1;     /* hub wid0 access */
+        } iiwa_fields_s;
+} hubii_iiwa_t;
+
+typedef union   hubii_illr_u {
+        u64     illr_reg_value;
+        struct {
+                u64     illr_rsvd:      32,     /* unused */
+                        illr_cb_cnt:    16,     /* checkbit error count */
+                        illr_sn_cnt:    16;     /* sequence number count */
+        } illr_fields_s;
+} hubii_illr_t;
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+typedef union io_perf_sel {
+        u64 perf_sel_reg;
+        struct {
+                u64     perf_rsvd  : 48,
+                        perf_icct  :  8,
+                        perf_ippr1 :  4,
+                        perf_ippr0 :  4;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the hub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        u64     perf_cnt;
+        struct {
+                u64     perf_rsvd1 : 32,
+                        perf_rsvd2 : 12,
+                        perf_cnt   : 20;
+        } perf_cnt_bits;
+} io_perf_cnt_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define LNK_STAT_WORKING        0x2
+
+#define IIO_LLP_CB_MAX  0xffff
+#define IIO_LLP_SN_MAX  0xffff
+
+/* IO PRB Entries */
+#define IIO_NUM_IPRBS   (9)
+#define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
+#define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
+#define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
+#define IIO_IOPRB_A     0x4001b0        /* PRB entry a */
+#define IIO_IOPRB_B     0x4001b8        /* PRB entry b */
+#define IIO_IOPRB_C     0x4001c0        /* PRB entry c */
+#define IIO_IOPRB_D     0x4001c8        /* PRB entry d */
+#define IIO_IOPRB_E     0x4001d0        /* PRB entry e */
+#define IIO_IOPRB_F     0x4001d8        /* PRB entry f */
+
+
+#define IIO_IXCC        0x4001e0        /* Crosstalk credit count timeout */
+#define IIO_IXTCC       IIO_IXCC
+#define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
+#define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
+#define IIO_IECLR       0x4001f8        /* IO error clear */
+#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/* PIO Read address Table Entries */
+#define IIO_IPCA        0x400300        /* PRB Counter adjust */
+#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
+#define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
+#define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
+#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_IPDR        0x400388        /* PIO table entry deallocation */
+#define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
+#define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
+#define IIO_IIAP        0x4003a0        /* IIQ Arbitration Parameters */
+#define IIO_IMMR        IIO_IIAP
+#define IIO_ICMR        0x4003a8        /* CRB Management Register */
+#define IIO_ICCR        0x4003b0        /* CRB Control Register */
+#define IIO_ICTO        0x4003b8        /* CRB Time Out Register */
+#define IIO_ICTP        0x4003c0        /* CRB Time Out Prescalar */
+
+
+/*
+ * ICMR register fields
+ */
+#define IIO_ICMR_PC_VLD_SHFT    36
+#define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_P_CNT_SHFT     0
+#define IIO_ICMR_P_CNT_MASK     (0xf << IIO_ICMR_P_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR
+ */
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      (0x800)
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              0x400400
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+
+/* XXX - IBUE register coming for Hub 2 */
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to hub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Fields in CRB Register A
+ */
+#ifndef __ASSEMBLY__
+typedef union icrba_u {
+        u64     reg_value;
+        struct {
+                u64     resvd:  6,
+                        stall_bte0: 1,  /* Stall BTE 0 */
+                        stall_bte1: 1,  /* Stall BTE 1 */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  3,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } icrba_fields_s;
+} icrba_t;
+
+/* This is an alternate typedef for the HUB1 CRB A in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrba_u {
+        u64     reg_value;
+
+        struct {
+                u64     resvd:  6,
+                        unused: 1,      /* Unused but RW!!      */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  4,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } h1_icrba_fields_s;
+} h1_icrba_t;
+
+/* XXX - Is this still right?  Check the spec. */
+#define ICRBN_A_CERR_SHFT       54
+#define ICRBN_A_ERR_MASK        0x3ff
+
+#endif /* !__ASSEMBLY__ */
+
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line.
+                                         */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+
+
+/*
+ * Fields in CRB Register B
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  5,
+                btenum: 1,      /* BTE to which entry belongs to */
+                cohtrans: 1,    /* Coherent transaction */
+                xtsize: 2,      /* Xtalk operation size
+                                 * 0: Double Word
+                                 * 1: 32 Bytes.
+                                 * 2: 128 Bytes,
+                                 * 3: Reserved.
+                                 */
+                srcnode: 9,     /* Source Node ID               */
+                srcinit: 2,     /* Source Initiator:
+                                 * See below for field values.
+                                 */
+                useold: 1,      /* Use OLD command for processing */
+                imsgtype: 2,    /* Incoming message type
+                                 * see below for field values
+                                 */
+                imsg:   8,      /* Incoming message     */
+                initator: 3,    /* Initiator of original request
+                                 * See below for field values.
+                                 */
+                reqtype: 5,     /* Identifies type of request
+                                 * See below for field values.
+                                 */
+                rsvd2:  7,
+                ackcnt: 11,     /* Invalidate ack count */
+                resp:   1,      /* data response  given to processor */
+                ack:    1,      /* indicates data ack received  */
+                hold:   1,      /* entry is gathering inval acks */
+                wb_pend:1,      /* waiting for writeback to complete */
+                intvn:  1,      /* Intervention */
+                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
+                stall_intr: 1;  /* Stall internal interrupts */
+        } icrbb_field_s;
+} icrbb_t;
+
+/* This is an alternate typedef for the HUB1 CRB B in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrbb_u {
+        u64     reg_value;
+        struct {
+                u64     rsvd1:  5,
+                        btenum: 1,      /* BTE to which entry belongs to */
+                        cohtrans: 1,    /* Coherent transaction */
+                        xtsize: 2,      /* Xtalk operation size
+                                         * 0: Double Word
+                                         * 1: 32 Bytes.
+                                         * 2: 128 Bytes,
+                                         * 3: Reserved.
+                                         */
+                        srcnode: 9,     /* Source Node ID               */
+                        srcinit: 2,     /* Source Initiator:
+                                         * See below for field values.
+                                         */
+                        useold: 1,      /* Use OLD command for processing */
+                        imsgtype: 2,    /* Incoming message type
+                                         * see below for field values
+                                         */
+                        imsg:   8,      /* Incoming message     */
+                        initator: 3,    /* Initiator of original request
+                                         * See below for field values.
+                                         */
+                        rsvd2:  1,
+                        pcache: 1,      /* entry belongs to partial cache */
+                        reqtype: 5,     /* Identifies type of request
+                                         * See below for field values.
+                                         */
+                        stl_ib: 1,      /* stall Ibus coming from xtalk */
+                        stl_intr: 1,    /* Stall internal interrupts */
+                        stl_bte0: 1,    /* Stall BTE 0  */
+                        stl_bte1: 1,    /* Stall BTE 1  */
+                        intrvn: 1,      /* Req was target of intervention */
+                        ackcnt: 11,     /* Invalidate ack count */
+                        resp:   1,      /* data response  given to processor */
+                        ack:    1,      /* indicates data ack received  */
+                        hold:   1,      /* entry is gathering inval acks */
+                        wb_pend:1,      /* waiting for writeback to complete */
+                        sleep:  1,      /* xtalk req sleeping till IO-sync */
+                        pnd_reply: 1,   /* replies not issed due to IOQ full */
+                        pnd_req: 1;     /* reqs not issued due to IOQ full */
+        } h1_icrbb_field_s;
+} h1_icrbb_t;
+
+
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_btenum        icrbb_field_s.btenum
+#define b_cohtrans      icrbb_field_s.cohtrans
+#define b_xtsize        icrbb_field_s.xtsize
+#define b_srcnode       icrbb_field_s.srcnode
+#define b_srcinit       icrbb_field_s.srcinit
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_imsg          icrbb_field_s.imsg
+#define b_initiator     icrbb_field_s.initiator
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for field xtsize
+ */
+#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+
+/*
+ * values for field srcinit
+ */
+#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
+#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Message from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Values for field reqtype.
+ */
+/* XXX - Need to fix this for Hub 2 */
+#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+
+/*
+ * Fields in CRB Register C
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union icrbc_s {
+        u64     reg_value;
+        struct {
+                u64     rsvd:   6,
+                        sleep:  1,
+                        pricnt: 4,      /* Priority count sent with Read req */
+                        pripsc: 4,      /* Priority Pre scalar  */
+                        bteop:  1,      /* BTE Operation        */
+                        push_be: 34,    /* Push address Byte enable
+                                         * Holds push addr, if CRB is for BTE
+                                         * If CRB belongs to Partial cache,
+                                         * this contains byte enables bits
+                                         * ([47:46] = 0)
+                                         */
+                        suppl:  11,     /* Supplemental field   */
+                        barrop: 1,      /* Barrier Op bit set in xtalk req */
+                        doresp: 1,      /* Xtalk req needs a response   */
+                        gbr:    1;      /* GBR bit set in xtalk packet  */
+        } icrbc_field_s;
+} icrbc_t;
+
+#define c_pricnt        icrbc_field_s.pricnt
+#define c_pripsc        icrbc_field_s.pripsc
+#define c_bteop         icrbc_field_s.bteop
+#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl         icrbc_field_s.suppl
+#define c_barrop        icrbc_field_s.barrop
+#define c_doresp        icrbc_field_s.doresp
+#define c_gbr   icrbc_field_s.gbr
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Fields in CRB Register D
+ */
+
+#ifndef __ASSEMBLY__
+typedef union icrbd_s {
+        u64     reg_value;
+        struct {
+            u64 rsvd:   38,
+                toutvld: 1,     /* Timeout in progress for this CRB */
+                ctxtvld: 1,     /* Context field below is valid */
+                rsvd2:  1,
+                context: 15,    /* Bit vector:
+                                 * Has a bit set for each CRB entry
+                                 * which needs to be deallocated
+                                 * before this CRB entry is processed.
+                                 * Set only for barrier operations.
+                                 */
+                timeout: 8;     /* Timeout Upper 8 bits */
+        } icrbd_field_s;
+} icrbd_t;
+
+#define icrbd_toutvld   icrbd_field_s.toutvld
+#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
+#define icrbd_context   icrbd_field_s.context
+
+
+typedef union hubii_ifdr_u {
+        u64     hi_ifdr_value;
+        struct {
+                u64     ifdr_rsvd:      49,
+                        ifdr_maxrp:      7,
+                        ifdr_rsvd1:      1,
+                        ifdr_maxrq:      7;
+        } hi_ifdr_fields;
+} hubii_ifdr_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Hardware designed names for the BTE control registers.
+ */
+#define IIO_IBLS_0      0x410000        /* BTE length/status 0 */
+#define IIO_IBSA_0      0x410008        /* BTE source address 0 */
+#define IIO_IBDA_0      0x410010        /* BTE destination address 0 */
+#define IIO_IBCT_0      0x410018        /* BTE control/terminate 0 */
+#define IIO_IBNA_0      0x410020        /* BTE notification address 0 */
+#define IIO_IBNR_0      IIO_IBNA_0
+#define IIO_IBIA_0      0x410028        /* BTE interrupt address 0 */
+
+#define IIO_IBLS_1      0x420000        /* BTE length/status 1 */
+#define IIO_IBSA_1      0x420008        /* BTE source address 1 */
+#define IIO_IBDA_1      0x420010        /* BTE destination address 1 */
+#define IIO_IBCT_1      0x420018        /* BTE control/terminate 1 */
+#define IIO_IBNA_1      0x420020        /* BTE notification address 1 */
+#define IIO_IBNR_1      IIO_IBNA_1
+#define IIO_IBIA_1      0x420028        /* BTE interrupt address 1 */
+
+/*
+ * More miscellaneous registers
+ */
+#define IIO_IPCR        0x430000        /* Performance Control */
+#define IIO_IPPR        0x430008        /* Performance Profiling */
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_BTE1              (1 << 18)  /* clear bte error 1 ??? */
+#define IECLR_BTE0              (1 << 17)  /* clear bte error 0 ??? */
+#define IECLR_CRAZY             (1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IO PIO Read Table Entry format
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union iprte_a {
+        u64     entry;
+        struct {
+            u64 rsvd1     : 7,  /* Reserved field               */
+                valid     : 1,  /* Maps to a timeout entry      */
+                rsvd2     : 1,
+                srcnode   : 9,  /* Node which did this PIO      */
+                initiator : 2,  /* If T5A or T5B or IO          */
+                rsvd3     : 3,
+                addr      : 38, /* Physical address of PIO      */
+                rsvd4     : 3;
+        } iprte_fields;
+} iprte_a_t;
+
+#define iprte_valid     iprte_fields.valid
+#define iprte_timeout   iprte_fields.timeout
+#define iprte_srcnode   iprte_fields.srcnode
+#define iprte_init      iprte_fields.initiator
+#define iprte_addr      iprte_fields.addr
+
+#endif /* !__ASSEMBLY__ */
+
+#define IPRTE_ADDRSHFT  3
+
+/*
+ * Hub IIO PRB Register format.
+ */
+
+#ifndef __ASSEMBLY__
+/*
+ * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
+ * "Status" fields, and should only be used in case of clean up after errors.
+ */
+
+typedef union iprb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  15,
+                error:  1,      /* Widget rcvd wr resp pkt w/ error */
+                ovflow: 5,      /* Overflow count. perf measurement */
+                fire_and_forget: 1, /* Launch Write without response */
+                mode:   2,      /* Widget operation Mode        */
+                rsvd2:  2,
+                bnakctr: 14,
+                rsvd3:  2,
+                anakctr: 14,
+                xtalkctr: 8;
+        } iprb_fields_s;
+} iprb_t;
+
+#define iprb_regval     reg_value
+
+#define iprb_error      iprb_fields_s.error
+#define iprb_ovflow     iprb_fields_s.ovflow
+#define iprb_ff         iprb_fields_s.fire_and_forget
+#define iprb_mode       iprb_fields_s.mode
+#define iprb_bnakctr    iprb_fields_s.bnakctr
+#define iprb_anakctr    iprb_fields_s.anakctr
+#define iprb_xtalkctr   iprb_fields_s.xtalkctr
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for mode field in iprb_t.
+ * For details of the meanings of NAK and Accept, refer the PIO flow
+ * document
+ */
+#define IPRB_MODE_NORMAL        (0)
+#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+
+/*
+ * IO CRB entry C_A to E_A : Partial (cache) CRBS
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbp_a {
+        u64   ip_reg;       /* the entire register value        */
+        struct {
+             u64 error: 1,  /*    63, error occurred            */
+                ln_uce: 1,  /*    62: uncorrectable memory      */
+                ln_ae:  1,  /*    61: protection violation      */
+                ln_werr:1,  /*    60: write access error        */
+                ln_aerr:1,  /*    59: sn0net: Address error     */
+                ln_perr:1,  /*    58: sn0net: poison error      */
+                timeout:1,  /*    57: CRB timed out             */
+                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+                c_err:  1,  /*    54: incoming xtalk req, err set*/
+                rsvd1: 12,  /* 53-42: reserved                  */
+                valid:  1,  /*    41: Valid status              */
+                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
+                tnum:   5,  /* 36-32: TNUM of xtalk request     */
+                bo:     1,  /*    31: barrier op set in xtalk rqst*/
+                resprqd:1,  /*    30: xtalk rqst requires response*/
+                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+                size:   2,  /* 28-27: size of xtalk request     */
+                excl:   4,  /* 26-23: exclusive bit(s)          */
+                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
+                intvn:  1,  /*    19: rqst target of intervention*/
+                resp:   1,  /*    18: Data response given to t5 */
+                ack:    1,  /*    17: Data ack received.        */
+                hold:   1,  /*    16: crb gathering invalidate acks*/
+                wb:     1,  /*    15: writeback pending.        */
+                ack_cnt:11, /* 14-04: counter of invalidate acks*/
+                tscaler:4;  /* 03-00: Timeout prescaler         */
+        } ip_fmt;
+} icrbp_a_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * A couple of defines to go with the above structure.
+ */
+#define ICRBP_A_CERR_SHFT       54
+#define ICRBP_A_ERR_MASK        0x3ff
+
+#ifndef __ASSEMBLY__
+typedef union hubii_idsr {
+        u64 iin_reg;
+        struct {
+                u64 rsvd1 : 35,
+                    isent : 1,
+                    rsvd2 : 3,
+                    ienable: 1,
+                    rsvd  : 7,
+                    node  : 9,
+                    rsvd4 : 1,
+                    level : 7;
+        } iin_fmt;
+} hubii_idsr_t;
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1 << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1 << 8)
+#define IBCT_NOTIFY             (0x1 << 4)
+#define IBCT_ZFIL_MODE          (0x1 << 0)
+
+/*
+ * IO BTE Interrupt Address Register (IBIA) register bit field definitions
+ */
+#define IBIA_LEVEL_SHFT         16
+#define IBIA_LEVEL_MASK         (0x7f << IBIA_LEVEL_SHFT)
+#define IBIA_NODE_ID_SHFT       0
+#define IBIA_NODE_ID_MASK       (0x1ff)
+
+/*
+ * Miscellaneous hub constants
+ */
+
+/* Number of widgets supported by hub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc101
+#define MAX_HUBS_PER_XBOW       2
+
+/*
+ * Get a hub's widget id from widget control register
+ */
+#define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
+#define IIO_WST_ERROR_MASK      (UINT64_CAST 1 << 32) /* Widget status error */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
new file mode 100644
index 000000000..305d002be
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
@@ -0,0 +1,789 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H
+
+
+/*
+ * Hub Memory/Directory interface registers
+ */
+#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
+
+#define MAX_REGIONS             64
+
+/* Hardware page size and shift */
+
+#define MD_PAGE_SIZE            4096     /* Page size in bytes              */
+#define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
+
+/* Register offsets from LOCAL_HUB or REMOTE_HUB */
+
+#define MD_BASE                 0x200000
+#define MD_BASE_PERF            0x210000
+#define MD_BASE_JUNK            0x220000
+
+#define MD_IO_PROTECT           0x200000 /* MD and core register protection */
+#define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
+#define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
+#define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
+#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
+#define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
+#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
+#define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
+#define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
+#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
+#define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
+
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
+
+#define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
+#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
+
+#ifdef CONFIG_SGI_SN_N_MODE
+#define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
+#else
+#define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
+#endif
+
+/*
+ * MD_MEMORY_CONFIG fields
+ *
+ *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
+ *   (SIMM pair).  They correspond to the values needed for the bit
+ *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
+ *   Bits not used by the MD are used by software.
+ */
+
+#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_8MB             1
+#define MD_SIZE_16MB            2
+#define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
+#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_256MB           6
+#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_1GB             8
+#define MD_SIZE_2GB             9
+#define MD_SIZE_4GB             10
+
+#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
+#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
+
+#define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
+#define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
+#define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
+#define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
+#define MMC_UCTLR_CYC_SHFT      39
+#define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
+#define MMC_UCTLR_WR_SHFT       34
+#define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
+#define MMC_DIMM0_SEL_SHFT      32
+#define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
+#define MMC_IO_PROT_EN_SHFT     31
+#define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
+#define MMC_IO_PROT             (UINT64_CAST 1 << 31)
+#define MMC_ARB_MLSS_SHFT       30
+#define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
+#define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
+#define MMC_IGNORE_ECC_SHFT     29
+#define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
+#define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
+#define MMC_DIR_PREMIUM_SHFT    28
+#define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
+#define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
+#define MMC_REPLY_GUAR_SHFT     24
+#define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
+#define MMC_BANK_SHFT(_b)       ((_b) * 3)
+#define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
+#define MMC_BANK_ALL_MASK       0xffffff
+#define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
+                                 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
+                                 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
+                                 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
+                                 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
+                                 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
+                                 MMC_BANK_ALL_MASK)
+
+/* MD_REFRESH_CONTROL fields */
+
+#define MRC_ENABLE_SHFT         63
+#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
+#define MRC_ENABLE              (UINT64_CAST 1 << 63)
+#define MRC_COUNTER_SHFT        12
+#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
+#define MRC_CNT_THRESH_MASK     0xfff
+#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
+
+/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
+
+#define MDI_SELECT_SHFT         32
+#define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
+#define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
+
+/* MD_MOQ_SIZE fields */
+
+#define MMS_RP_SIZE_SHFT        8
+#define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
+#define MMS_RQ_SIZE_SHFT        0
+#define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
+#define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
+
+/* MD_FANDOP_CAC_STAT fields */
+
+#define MFC_VALID_SHFT          63
+#define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
+#define MFC_VALID               (UINT64_CAST 1 << 63)
+#define MFC_ADDR_SHFT           6
+#define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
+
+/* MD_MLAN_CTL fields */
+
+#define MLAN_PHI1_SHFT          27
+#define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PHI0_SHFT          20
+#define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PULSE_SHFT         10
+#define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
+#define MLAN_SAMPLE_SHFT        2
+#define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
+#define MLAN_DONE_SHFT          1
+#define MLAN_DONE_MASK          2
+#define MLAN_DONE               (UINT64_CAST 0x02)
+#define MLAN_RD_DATA            (UINT64_CAST 0x01)
+#define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
+                                 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
+
+/* MD_SLOTID_USTAT bit definitions */
+
+#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
+#define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
+#define MSU_CORECLK             (UINT64_CAST 1 << 6)
+#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
+#define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
+#define MSU_NETSYNC             (UINT64_CAST 1 << 5)
+#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
+#define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
+#define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
+#define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
+#define MSU_I2CINTR             (UINT64_CAST 1 << 3)
+#define MSU_SLOTID_MASK         0xff
+#define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
+#define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
+#define MSU_SN00_SLOTID_SHFT    7
+#define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
+
+#define MSU_PIMM_PSC_SHFT       4
+#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+
+/* MD_MIG_DIFF_THRESH bit definitions */
+
+#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_DIFF_THRES_VALID_SHFT 63
+#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_VALUE_THRESH bit definitions */
+
+#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_VALUE_THRES_VALID_SHFT 63
+#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_CANDIDATE bit definitions */
+
+#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_CANDIDATE_VALID_SHFT 63
+#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
+#define MD_MIG_CANDIDATE_TYPE_SHFT 30
+#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
+#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
+#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
+#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
+#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
+#define MD_MIG_CANDIDATE_NODEID_SHFT 20
+#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
+#define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
+
+/* Other MD definitions */
+
+#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
+#define MD_BANK_MASK            (UINT64_CAST 7 << 29)
+#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
+#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*
+ * The following definitions cover the bit field definitions for the
+ * various MD registers.  For multi-bit registers, we define both
+ * a shift amount and a mask value.  By convention, if you want to
+ * isolate a field, you should mask the field and then shift it down,
+ * since this makes the masks useful without a shift.
+ */
+
+/* Directory entry states for both premium and standard SIMMs. */
+
+#define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
+#define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
+#define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
+#define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
+#define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
+#define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
+#define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
+
+/*
+ * The MD_DIR_FORCE_ECC bit can be added directory entry write data
+ * to forcing the ECC to be written as-is instead of recalculated.
+ */
+
+#define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
+
+/*
+ * Premium SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A, B, and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE = shared, FINE = 1
+ * Format B:  STATE = shared, FINE = 0
+ * Format C:  STATE != shared (FINE must be 0)
+ */
+
+#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
+#define MD_PDIR_ECC_MASK        0x7f
+#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
+#define MD_PDIR_PRIO_MASK       (0xf << 8)
+#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
+#define MD_PDIR_AX_MASK         (1 << 7)
+#define MD_PDIR_AX              (1 << 7)
+#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
+#define MD_PDIR_FINE_MASK       (1 << 12)
+#define MD_PDIR_FINE            (1 << 12)
+#define MD_PDIR_OCT_SHFT        13                      /* A low            */
+#define MD_PDIR_OCT_MASK        (7 << 13)
+#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
+#define MD_PDIR_STATE_MASK      (7 << 13)
+#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
+#define MD_PDIR_ONECNT_MASK     (0x3f << 16)
+#define MD_PDIR_PTR_SHFT        22                      /* C low            */
+#define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
+#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
+#define MD_PDIR_VECMSB_BITMASK  0x3ffffff
+#define MD_PDIR_VECMSB_BITSHFT  27
+#define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
+#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
+#define MD_PDIR_CWOFF_MASK      (7 << 7)
+#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
+#define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
+#define MD_PDIR_VECLSB_BITSHFT  0
+#define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
+                                 MD_PDIR_AX)
+#define MD_PDIR_INIT_HI         0
+#define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
+                                 MD_PROT_RW << MD_PPROT_SHFT)
+
+/*
+ * Standard SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE == shared
+ * Format C:  STATE != shared
+ */
+
+#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
+#define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
+#define MD_SDIR_ECC_MASK        0x1f
+#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
+#define MD_SDIR_PRIO_MASK       (1 << 6)
+#define MD_SDIR_AX_SHFT         5                       /* AC low           */
+#define MD_SDIR_AX_MASK         (1 << 5)
+#define MD_SDIR_AX              (1 << 5)
+#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
+#define MD_SDIR_STATE_MASK      (7 << 7)
+#define MD_SDIR_PTR_SHFT        10                      /* C low            */
+#define MD_SDIR_PTR_MASK        (0x3f << 10)
+#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
+#define MD_SDIR_CWOFF_MASK      (7 << 5)
+#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
+#define MD_SDIR_VECMSB_BITMASK  0x1f
+#define MD_SDIR_VECMSB_BITSHFT  7
+#define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
+#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
+#define MD_SDIR_VECLSB_BITMASK  0x7ff
+#define MD_SDIR_VECLSB_BITSHFT  0
+#define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
+                                 MD_SDIR_AX)
+#define MD_SDIR_INIT_HI         0
+#define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
+
+/* Protection and migration field values */
+
+#define MD_PROT_RW              (UINT64_CAST 0x6)
+#define MD_PROT_RO              (UINT64_CAST 0x3)
+#define MD_PROT_NO              (UINT64_CAST 0x0)
+#define MD_PROT_BAD             (UINT64_CAST 0x5)
+
+/* Premium SIMM protection entry shifts and masks. */
+
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_MASK           7
+#define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_PPROT_MIGMD_MASK     (3 << 3)
+#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_PPROT_REFCNT_WIDTH   0x7ffff
+#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
+
+#define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
+#define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
+
+/* Standard SIMM protection entry shifts and masks. */
+
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_MASK           7
+#define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_SPROT_MIGMD_MASK     (3 << 3)
+#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_SPROT_REFCNT_WIDTH   0x7ff
+#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
+
+/* Migration modes used in protection entries */
+
+#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
+#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
+#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
+#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
+
+
+/*
+ * Operations on page migration threshold register
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * LED register macros
+ */
+
+#define CPU_LED_ADDR(_nasid, _slice)                                       \
+        (private.p_sn00 ?                                                  \
+         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
+
+#define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
+        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
+
+#define SET_MY_LEDS(_v)                                                    \
+        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
+
+/*
+ * Operations on Memory/Directory DIMM control register
+ */
+
+#define DIRTYPE_PREMIUM 1
+#define DIRTYPE_STANDARD 0
+#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
+        (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
+        MMC_DIR_PREMIUM_SHFT)
+
+
+/*
+ * Operations on page migration count difference and absolute threshold
+ * registers
+ */
+
+#define MD_MIG_DIFF_THRESH_GET(region) ( \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
+        MD_MIG_DIFF_THRES_VALUE_MASK)
+
+#define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                MD_MIG_DIFF_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             & ~MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             | MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
+               MD_MIG_DIFF_THRES_VALID_MASK)
+
+#define MD_MIG_VALUE_THRESH_GET(region) (                               \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
+        MD_MIG_VALUE_THRES_VALUE_MASK)
+
+#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
+                             & ~MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
+                             | MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
+               MD_MIG_VALUE_THRES_VALID_MASK)
+
+/*
+ * Operations on page migration candidate register
+ */
+
+#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
+        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
+
+#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
+
+#define MD_MIG_CANDIDATE_NODEID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
+
+#define MD_MIG_CANDIDATE_TYPE(value) ( \
+        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
+
+#define MD_MIG_CANDIDATE_VALID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
+
+/*
+ * Macros to retrieve fields in the protection entry
+ */
+
+/* for Premium SIMM */
+#define MD_PPROT_REFCNT_GET(value) ( \
+        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
+
+#define MD_PPROT_MIGMD_GET(value) ( \
+        ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
+
+/* for Standard SIMM */
+#define MD_SPROT_REFCNT_GET(value) ( \
+        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
+
+#define MD_SPROT_MIGMD_GET(value) ( \
+        ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
+
+/*
+ * Format of dir_error, mem_error, protocol_error and misc_error registers
+ */
+
+struct dir_error_reg {
+        u64     uce_vld:   1,   /*    63: valid directory uce   */
+                ae_vld:    1,   /*    62: valid dir prot ecc error */
+                ce_vld:    1,   /*    61: valid correctable ECC err*/
+                rsvd1:    19,   /* 60-42: reserved              */
+                bad_prot:  3,   /* 41-39: encoding, bad access rights*/
+                bad_syn:   7,   /* 38-32: bad dir syndrome      */
+                rsvd2:     2,   /* 31-30: reserved              */
+                hspec_addr:27,  /* 29-03: bddir space bad entry */
+                uce_ovr:   1,   /*     2: multiple dir uce's    */
+                ae_ovr:    1,   /*     1: multiple prot ecc errs*/
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+typedef union md_dir_error {
+        u64     derr_reg;       /* the entire register          */
+        struct dir_error_reg derr_fmt;  /* the register format          */
+} md_dir_error_t;
+
+
+struct mem_error_reg {
+        u64     uce_vld:   1,   /*    63: valid memory uce      */
+                ce_vld:    1,   /*    62: valid correctable ECC err*/
+                rsvd1:    22,   /* 61-40: reserved              */
+                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
+                address:  29,   /* 31-03: bad entry pointer     */
+                rsvd2:     1,   /*     2: reserved              */
+                uce_ovr:   1,   /*     1: multiple mem uce's    */
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+
+typedef union md_mem_error {
+        u64     merr_reg;       /* the entire register          */
+        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+} md_mem_error_t;
+
+
+struct proto_error_reg {
+        u64     valid:     1,   /*    63: valid protocol error  */
+                rsvd1:     2,   /* 62-61: reserved              */
+                initiator:11,   /* 60-50: id of request initiator*/
+                backoff:   2,   /* 49-48: backoff control       */
+                msg_type:  8,   /* 47-40: type of request       */
+                access:    2,   /* 39-38: access rights of initiator*/
+                priority:  1,   /*    37: priority level of requestor*/
+                dir_state: 4,   /* 36-33: state of directory    */
+                pointer_me:1,   /*    32: initiator same as dir ptr */
+                address:  29,   /* 31-03: request address       */
+                rsvd2:     2,   /* 02-01: reserved              */
+                overrun:   1;   /*     0: multiple protocol errs */
+};
+
+typedef union md_proto_error {
+        u64     perr_reg;       /* the entire register          */
+        struct proto_error_reg  perr_fmt; /* format of the register     */
+} md_proto_error_t;
+
+
+struct md_sdir_high_fmt {
+        unsigned short sd_hi_bvec : 11,
+                       sd_hi_ecc  : 5;
+};
+
+
+typedef union md_sdir_high {
+        /* The 16 bits of standard directory, upper word */
+        unsigned short sd_hi_val;
+        struct  md_sdir_high_fmt sd_hi_fmt;
+}md_sdir_high_t;
+
+
+struct md_sdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        unsigned short  sds_lo_bvec  : 5,
+                        sds_lo_unused: 1,
+                        sds_lo_state : 3,
+                        sds_lo_prio  : 1,
+                        sds_lo_ax    : 1,
+                        sds_lo_ecc   : 5;
+};
+
+struct md_sdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        unsigned short  sde_lo_ptr   : 6,
+                        sde_lo_state : 3,
+                        sde_lo_prio  : 1,
+                        sde_lo_ax    : 1,
+                        sde_lo_ecc   : 5;
+};
+
+
+typedef union md_sdir_low {
+        /* The 16 bits of standard directory, lower word */
+        unsigned short  sd_lo_val;
+        struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
+        struct  md_sdir_low_shared_fmt sds_lo_fmt;
+}md_sdir_low_t;
+
+
+
+struct md_pdir_high_fmt {
+        u64     pd_hi_unused   : 16,
+                pd_hi_bvec     : 38,
+                pd_hi_unused1  : 3,
+                pd_hi_ecc      : 7;
+};
+
+
+typedef union md_pdir_high {
+        /* The 48 bits of standard directory, upper word */
+        u64     pd_hi_val;
+        struct md_pdir_high_fmt pd_hi_fmt;
+}md_pdir_high_t;
+
+
+struct md_pdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        u64     pds_lo_unused   : 16,
+                pds_lo_bvec     : 26,
+                pds_lo_cnt      :  6,
+                pds_lo_state    :  3,
+                pds_lo_ste      :  1,
+                pds_lo_prio     :  4,
+                pds_lo_ax       :  1,
+                pds_lo_ecc      :  7;
+};
+
+struct md_pdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        u64     pde_lo_unused   : 31,
+                pde_lo_ptr      : 11,
+                pde_lo_unused1  :  6,
+                pde_lo_state    :  3,
+                pde_lo_ste      :  1,
+                pde_lo_prio     :  4,
+                pde_lo_ax       :  1,
+                pde_lo_ecc      :  7;
+};
+
+
+typedef union md_pdir_loent {
+        /* The 48 bits of premium directory, lower word */
+        u64     pd_lo_val;
+        struct md_pdir_low_exclusive_fmt pde_lo_fmt;
+        struct md_pdir_low_shared_fmt   pds_lo_fmt;
+}md_pdir_low_t;
+
+
+/*
+ *   the following two "union" definitions and two
+ *   "struct" definitions are used in vmdump.c to
+ *   represent directory memory information.
+ */
+
+typedef union   md_dir_high     {
+        md_sdir_high_t  md_sdir_high;
+        md_pdir_high_t  md_pdir_high;
+} md_dir_high_t;
+
+typedef union   md_dir_low      {
+        md_sdir_low_t   md_sdir_low;
+        md_pdir_low_t   md_pdir_low;
+} md_dir_low_t;
+
+typedef struct  bddir_entry     {
+        md_dir_low_t    md_dir_low;
+        md_dir_high_t   md_dir_high;
+} bddir_entry_t;
+
+typedef struct  dir_mem_entry   {
+        u64             prcpf[MAX_REGIONS];
+        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+} dir_mem_entry_t;
+
+
+
+typedef union md_perf_sel {
+        u64     perf_sel_reg;
+        struct  {
+                u64     perf_rsvd : 60,
+                        perf_en   :  1,
+                        perf_sel  :  3;
+        } perf_sel_bits;
+} md_perf_sel_t;
+
+typedef union md_perf_cnt {
+        u64     perf_cnt;
+        struct  {
+                u64     perf_rsvd : 44,
+                        perf_cnt  : 20;
+        } perf_cnt_bits;
+} md_perf_cnt_t;
+
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define DIR_ERROR_VALID_MASK    0xe000000000000000
+#define DIR_ERROR_VALID_SHFT    61
+#define DIR_ERROR_VALID_UCE     0x8000000000000000
+#define DIR_ERROR_VALID_AE      0x4000000000000000
+#define DIR_ERROR_VALID_CE      0x2000000000000000
+
+#define MEM_ERROR_VALID_MASK    0xc000000000000000
+#define MEM_ERROR_VALID_SHFT    62
+#define MEM_ERROR_VALID_UCE     0x8000000000000000
+#define MEM_ERROR_VALID_CE      0x4000000000000000
+
+#define PROTO_ERROR_VALID_MASK  0x8000000000000000
+
+#define MISC_ERROR_VALID_MASK   0x3ff
+
+/*
+ * Mask for hspec address that is stored in the dir error register.
+ * This represents bits 29 through 3.
+ */
+#define DIR_ERR_HSPEC_MASK      0x3ffffff8
+#define ERROR_HSPEC_MASK        0x3ffffff8
+#define ERROR_HSPEC_SHFT        3
+#define ERROR_ADDR_MASK         0xfffffff8
+#define ERROR_ADDR_SHFT         3
+
+/*
+ * MD_MISC_ERROR register defines.
+ */
+
+#define MMCE_VALID_MASK         0x3ff
+#define MMCE_ILL_MSG_SHFT       8
+#define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
+#define MMCE_ILL_REV_SHFT       6
+#define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
+#define MMCE_LONG_PACK_SHFT     4
+#define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
+#define MMCE_SHORT_PACK_SHFT    2
+#define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
+#define MMCE_BAD_DATA_SHFT      0
+#define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
+
+
+#define MD_PERF_COUNTERS        6
+#define MD_PERF_SETS            6
+
+#define MEM_DIMM_MASK                           0xe0000000
+#define MEM_DIMM_SHFT                           29
+
+#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
new file mode 100644
index 000000000..b8253142c
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
@@ -0,0 +1,263 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
+ *
+ * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN0_HUBNI_H
+#define _ASM_SGI_SN0_HUBNI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
+/*
+ * Hub Network Interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ */
+
+#define NI_BASE                 0x600000
+#define NI_BASE_TABLES          0x630000
+
+#define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
+#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
+#define NI_PROTECTION           0x600010 /* NI register access permissions  */
+#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
+#define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
+#define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
+#define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
+
+#define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
+#define NI_VECTOR               0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
+#define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
+
+#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
+#define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
+#define NI_AGE_REG_MAX          NI_AGE_IO_PIO
+
+#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
+
+#define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
+#define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
+#define NI_META_ENTRIES         32
+
+#define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
+#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
+#define NI_LOCAL_ENTRIES        16
+
+/*
+ * NI_STATUS_REV_ID mask and shift definitions
+ * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
+ */
+
+#define NSRI_8BITMODE_SHFT      30
+#define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
+#define NSRI_LINKUP_SHFT        29
+#define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
+#define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
+#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_MORENODES_SHFT     18
+#define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
+#define  MORE_MEMORY            0
+#define  MORE_NODES             1
+#define NSRI_REGIONSIZE_SHFT    17
+#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
+#define  REGIONSIZE_FINE        1
+#define  REGIONSIZE_COARSE      0
+#define NSRI_NODEID_SHFT        8
+#define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
+#define NSRI_REV_SHFT           4
+#define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
+#define NSRI_CHIPID_SHFT        0
+#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
+
+/*
+ * In fine mode, each node is a region.  In coarse mode, there are
+ * eight nodes per region.
+ */
+#define NASID_TO_FINEREG_SHFT   0
+#define NASID_TO_COARSEREG_SHFT 3
+
+/* NI_PORT_RESET mask definitions */
+
+#define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
+#define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
+#define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
+
+/* NI_PROTECTION mask and shift definitions */
+
+#define NPROT_RESETOK           (UINT64_CAST 1)
+
+/* NI_GLOBAL_PARMS mask and shift definitions */
+
+#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
+#define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
+#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
+
+#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
+#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
+
+/* NI_DIAG_PARMS mask and shift definitions */
+
+#define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
+#define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
+
+/*
+ * NI_VECTOR_PARMS mask and shift definitions.
+ * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
+ */
+
+#define NVP_PIOID_SHFT          40
+#define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVP_WRITEID_SHFT        32
+#define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_TYPE_SHFT           0
+#define NVP_TYPE_MASK           (UINT64_CAST 0x3)
+
+/* NI_VECTOR_STATUS mask and shift definitions */
+
+#define NVS_VALID               (UINT64_CAST 1 << 63)
+#define NVS_OVERRUN             (UINT64_CAST 1 << 62)
+#define NVS_TARGET_SHFT         51
+#define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
+#define NVS_PIOID_SHFT          40
+#define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVS_WRITEID_SHFT        32
+#define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_TYPE_SHFT           0
+#define NVS_TYPE_MASK           (UINT64_CAST 0x7)
+#define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
+
+
+#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+
+/* NI_AGE_XXX mask and shift definitions */
+
+#define NAGE_VCH_SHFT           10
+#define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
+#define NAGE_CC_SHFT            8
+#define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
+#define NAGE_AGE_SHFT           0
+#define NAGE_AGE_MASK           (UINT64_CAST 0xff)
+#define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
+
+#define  VCHANNEL_A             0
+#define  VCHANNEL_B             1
+#define  VCHANNEL_ANY           2
+
+/* NI_PORT_PARMS mask and shift definitions */
+
+#define NPP_NULLTO_SHFT         10
+#define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
+#define NPP_MAXBURST_SHFT       0
+#define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
+#define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+#define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+
+
+/* NI_PORT_ERROR mask and shift definitions */
+
+#define NPE_LINKRESET           (UINT64_CAST 1 << 37)
+#define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
+#define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
+#define NPE_BADDEST             (UINT64_CAST 1 << 34)
+#define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
+#define NPE_CREDITTO_SHFT       28
+#define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
+#define NPE_TAILTO_SHFT         24
+#define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
+#define NPE_RETRYCOUNT_SHFT     16
+#define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
+#define NPE_CBERRCOUNT_SHFT     8
+#define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
+#define NPE_SNERRCOUNT_SHFT     0
+#define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
+#define NPE_MASK                0x3effffffff
+
+#define NPE_COUNT_MAX           0xff
+
+#define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
+                                 NPE_BADMESSAGE | NPE_BADDEST |         \
+                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                 NPE_TAILTO_MASK)
+
+/* NI_META_TABLE mask and shift definitions */
+
+#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+/* NI_LOCAL_TABLE mask and shift definitions */
+
+#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+#ifndef __ASSEMBLY__
+
+typedef union   hubni_port_error_u {
+        u64     nipe_reg_value;
+        struct {
+            u64 nipe_rsvd:      26,     /* unused */
+                nipe_lnk_reset:  1,     /* link reset */
+                nipe_intl_err:   1,     /* internal error */
+                nipe_bad_msg:    1,     /* bad message */
+                nipe_bad_dest:   1,     /* bad dest     */
+                nipe_fifo_ovfl:  1,     /* fifo overflow */
+                nipe_rsvd1:      1,     /* unused */
+                nipe_credit_to:  4,     /* credit timeout */
+                nipe_tail_to:    4,     /* tail timeout */
+                nipe_retry_cnt:  8,     /* retry error count */
+                nipe_cb_cnt:     8,     /* checkbit error count */
+                nipe_sn_cnt:     8;     /* sequence number count */
+        } nipe_fields_s;
+} hubni_port_error_t;
+
+#define NI_LLP_RETRY_MAX        0xff
+#define NI_LLP_CB_MAX           0xff
+#define NI_LLP_SN_MAX           0xff
+
+static inline int get_region_shift(void)
+{
+        if (LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK)
+                return NASID_TO_FINEREG_SHFT;
+
+        return NASID_TO_COARSEREG_SHFT;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
new file mode 100644
index 000000000..7b8365591
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
@@ -0,0 +1,409 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H
+
+#include <linux/types.h>
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * All register "addresses" are actually offsets.  Use the LOCAL_HUB
+ * or REMOTE_HUB macros to synthesize an actual address
+ */
+
+#define PI_BASE                 0x000000
+
+/* General protection and control registers */
+
+#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
+#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
+#define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
+
+/* CALIAS values */
+#define PI_CALIAS_SIZE_0        0
+#define PI_CALIAS_SIZE_4K       1
+#define PI_CALIAS_SIZE_8K       2
+#define PI_CALIAS_SIZE_16K      3
+#define PI_CALIAS_SIZE_32K      4
+#define PI_CALIAS_SIZE_64K      5
+#define PI_CALIAS_SIZE_128K     6
+#define PI_CALIAS_SIZE_256K     7
+#define PI_CALIAS_SIZE_512K     8
+#define PI_CALIAS_SIZE_1M       9
+#define PI_CALIAS_SIZE_2M       10
+#define PI_CALIAS_SIZE_4M       11
+#define PI_CALIAS_SIZE_8M       12
+#define PI_CALIAS_SIZE_16M      13
+#define PI_CALIAS_SIZE_32M      14
+#define PI_CALIAS_SIZE_64M      15
+
+/* Processor control and status checking */
+
+#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
+#define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
+#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
+#define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
+#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
+
+/* Regular Interrupt register checking.  */
+
+#define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
+#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
+
+#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
+
+/* Crosscall interrupts */
+
+#define PI_CC_PEND_SET_A        0x0000c8 /* CC Interrupt Pending Set, CPU A */
+#define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
+#define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
+#define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
+#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
+
+#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
+
+/* Realtime Counter and Profiler control registers */
+
+#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
+#define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
+#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
+#define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
+#define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
+#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
+#define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
+
+#define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
+
+/* Built-In Self Test support */
+
+#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
+
+/* Graphics control registers */
+
+#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
+#define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
+#define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
+#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
+#define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
+#define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
+
+#define PI_GFX_OFFSET           (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
+#define PI_GFX_PAGE_ENABLE      0x0000010000000000LL
+
+/* Error and timeout registers */
+#define PI_ERR_INT_PEND         0x000400 /* Error Interrupt Pending         */
+#define PI_ERR_INT_MASK_A       0x000408 /* Error Interrupt mask for CPU A  */
+#define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
+#define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
+#define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
+#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
+#define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
+#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
+#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
+#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
+#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
+#define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
+#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
+#define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
+#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
+#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
+#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
+
+/* Bits in PI_ERR_INT_PEND */
+#define PI_ERR_SPOOL_CMP_B      0x00000001      /* Spool end hit high water */
+#define PI_ERR_SPOOL_CMP_A      0x00000002
+#define PI_ERR_SPUR_MSG_B       0x00000004      /* Spurious message intr.   */
+#define PI_ERR_SPUR_MSG_A       0x00000008
+#define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
+#define PI_ERR_WRB_TERR_A       0x00000020
+#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_A       0x00000080
+#define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
+#define PI_ERR_SYSSTATE_A       0x00000200
+#define PI_ERR_SYSAD_DATA_B     0x00000400      /* SysAD data parity error  */
+#define PI_ERR_SYSAD_DATA_A     0x00000800
+#define PI_ERR_SYSAD_ADDR_B     0x00001000      /* SysAD addr parity error  */
+#define PI_ERR_SYSAD_ADDR_A     0x00002000
+#define PI_ERR_SYSCMD_DATA_B    0x00004000      /* SysCmd data parity error */
+#define PI_ERR_SYSCMD_DATA_A    0x00008000
+#define PI_ERR_SYSCMD_ADDR_B    0x00010000      /* SysCmd addr parity error */
+#define PI_ERR_SYSCMD_ADDR_A    0x00020000
+#define PI_ERR_BAD_SPOOL_B      0x00040000      /* Error spooling to memory */
+#define PI_ERR_BAD_SPOOL_A      0x00080000
+#define PI_ERR_UNCAC_UNCORR_B   0x00100000      /* Uncached uncorrectable   */
+#define PI_ERR_UNCAC_UNCORR_A   0x00200000
+#define PI_ERR_SYSSTATE_TAG_B   0x00400000      /* SysState tag parity error */
+#define PI_ERR_SYSSTATE_TAG_A   0x00800000
+#define PI_ERR_MD_UNCORR        0x01000000      /* Must be cleared in MD    */
+
+#define PI_ERR_CLEAR_ALL_A      0x00aaaaaa
+#define PI_ERR_CLEAR_ALL_B      0x00555555
+
+
+/*
+ * The following three macros define all possible error int pends.
+ */
+
+#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
+                                 PI_ERR_BAD_SPOOL_A     | \
+                                 PI_ERR_SYSCMD_ADDR_A   | \
+                                 PI_ERR_SYSCMD_DATA_A   | \
+                                 PI_ERR_SYSAD_ADDR_A    | \
+                                 PI_ERR_SYSAD_DATA_A    | \
+                                 PI_ERR_SYSSTATE_A)
+
+#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
+                                 PI_ERR_WRB_WERR_A      | \
+                                 PI_ERR_WRB_TERR_A      | \
+                                 PI_ERR_SPUR_MSG_A      | \
+                                 PI_ERR_SPOOL_CMP_A)
+
+#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
+                                 PI_ERR_BAD_SPOOL_B     | \
+                                 PI_ERR_SYSCMD_ADDR_B   | \
+                                 PI_ERR_SYSCMD_DATA_B   | \
+                                 PI_ERR_SYSAD_ADDR_B    | \
+                                 PI_ERR_SYSAD_DATA_B    | \
+                                 PI_ERR_SYSSTATE_B)
+
+#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
+                                 PI_ERR_WRB_WERR_B      | \
+                                 PI_ERR_WRB_TERR_B      | \
+                                 PI_ERR_SPUR_MSG_B      | \
+                                 PI_ERR_SPOOL_CMP_B)
+
+#define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
+
+/*
+ * Error types for PI_ERR_STATUS0_[AB] and error stack:
+ * Use the write types if WRBRRB is 1 else use the read types
+ */
+
+/* Fields in PI_ERR_STATUS0_[AB] */
+#define PI_ERR_ST0_TYPE_MASK    0x0000000000000007
+#define PI_ERR_ST0_TYPE_SHFT    0
+#define PI_ERR_ST0_REQNUM_MASK  0x0000000000000038
+#define PI_ERR_ST0_REQNUM_SHFT  3
+#define PI_ERR_ST0_SUPPL_MASK   0x000000000001ffc0
+#define PI_ERR_ST0_SUPPL_SHFT   6
+#define PI_ERR_ST0_CMD_MASK     0x0000000001fe0000
+#define PI_ERR_ST0_CMD_SHFT     17
+#define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
+#define PI_ERR_ST0_ADDR_SHFT    25
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62
+#define PI_ERR_ST0_VALID_MASK   0x8000000000000000
+#define PI_ERR_ST0_VALID_SHFT   63
+
+/* Fields in PI_ERR_STATUS1_[AB] */
+#define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
+#define PI_ERR_ST1_SPOOL_SHFT   0
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21
+#define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
+#define PI_ERR_ST1_INVCNT_SHFT  29
+#define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
+#define PI_ERR_ST1_CRBNUM_SHFT  39
+#define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
+#define PI_ERR_ST1_WRBRRB_SHFT  42
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43
+#define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
+#define PI_ERR_ST1_MSGSRC_SHFT  53
+
+/* Fields in the error stack */
+#define PI_ERR_STK_TYPE_MASK    0x0000000000000003
+#define PI_ERR_STK_TYPE_SHFT    0
+#define PI_ERR_STK_SUPPL_MASK   0x0000000000000038
+#define PI_ERR_STK_SUPPL_SHFT   3
+#define PI_ERR_STK_REQNUM_MASK  0x00000000000001c0
+#define PI_ERR_STK_REQNUM_SHFT  6
+#define PI_ERR_STK_CRBNUM_MASK  0x0000000000000e00
+#define PI_ERR_STK_CRBNUM_SHFT  9
+#define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
+#define PI_ERR_STK_WRBRRB_SHFT  12
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13
+#define PI_ERR_STK_CMD_MASK     0x000000007f800000
+#define PI_ERR_STK_CMD_SHFT     23
+#define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
+#define PI_ERR_STK_ADDR_SHFT    31
+
+/* Error type in the error status or stack on Read CRBs */
+#define PI_ERR_RD_PRERR         1
+#define PI_ERR_RD_DERR          2
+#define PI_ERR_RD_TERR          3
+
+/* Error type in the error status or stack on Write CRBs */
+#define PI_ERR_WR_WERR          0
+#define PI_ERR_WR_PWERR         1
+#define PI_ERR_WR_TERR          3
+
+/* Read or Write CRB in error status or stack */
+#define PI_ERR_RRB      0
+#define PI_ERR_WRB      1
+#define PI_ERR_ANY_CRB  2
+
+/* Address masks in the error status and error stack are not the same */
+#define ERR_STK_ADDR_SHFT       7
+#define ERR_STAT0_ADDR_SHFT     3
+
+#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
+#define PI_STACK_SIZE_SHFT      12      /* 4k */
+
+#define ERR_STACK_SIZE_BYTES(_sz) \
+       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
+
+#ifndef __ASSEMBLY__
+/*
+ * format of error stack and error status registers.
+ */
+
+struct err_stack_format {
+        u64     sk_addr    : 33,   /* address */
+                sk_cmd     :  8,   /* message command */
+                sk_crb_sts : 10,   /* status from RRB or WRB */
+                sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                sk_t5_req  :  3,   /* RRB T5 request number */
+                sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+                sk_err_type:  3;   /* error type        */
+};
+
+typedef union pi_err_stack {
+        u64     pi_stk_word;
+        struct  err_stack_format pi_stk_fmt;
+} pi_err_stack_t;
+
+struct err_status0_format {
+        u64     s0_valid   :  1,   /* Valid */
+                s0_ovr_run :  1,   /* Overrun, spooled to memory */
+                s0_addr    : 37,   /* address */
+                s0_cmd     :  8,   /* message command */
+                s0_supl    : 11,   /* message supplemental field */
+                s0_t5_req  :  3,   /* RRB T5 request number */
+                s0_err_type:  3;   /* error type */
+};
+
+typedef union pi_err_stat0 {
+        u64     pi_stat0_word;
+        struct err_status0_format pi_stat0_fmt;
+} pi_err_stat0_t;
+
+struct err_status1_format {
+        u64     s1_src     : 11,   /* message source */
+                s1_crb_sts : 10,   /* status from RRB or WRB */
+                s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                s1_inval_cnt:10,   /* signed invalidate counter RRB */
+                s1_to_cnt  :  8,   /* crb timeout counter */
+                s1_spl_cnt : 21;   /* number spooled to memory */
+};
+
+typedef union pi_err_stat1 {
+        u64     pi_stat1_word;
+        struct err_status1_format pi_stat1_fmt;
+} pi_err_stat1_t;
+
+typedef u64     rtc_time_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* Bits in PI_SYSAD_ERRCHK_EN */
+#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
+#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
+
+/* Interrupt pending bits on R10000 */
+
+#define HUB_IP_PEND0            0x0400
+#define HUB_IP_PEND1_CC         0x0800
+#define HUB_IP_RT               0x1000
+#define HUB_IP_PROF             0x2000
+#define HUB_IP_ERROR            0x4000
+#define HUB_IP_MASK             0x7c00
+
+/* PI_RT_LOCAL_CTRL mask and shift definitions */
+
+#define PRLC_USE_INT_SHFT       16
+#define PRLC_USE_INT_MASK       (UINT64_CAST 1 << 16)
+#define PRLC_USE_INT            (UINT64_CAST 1 << 16)
+#define PRLC_GCLK_SHFT          15
+#define PRLC_GCLK_MASK          (UINT64_CAST 1 << 15)
+#define PRLC_GCLK               (UINT64_CAST 1 << 15)
+#define PRLC_GCLK_COUNT_SHFT    8
+#define PRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x7f << 8)
+#define PRLC_MAX_COUNT_SHFT     1
+#define PRLC_MAX_COUNT_MASK     (UINT64_CAST 0x7f << 1)
+#define PRLC_GCLK_EN_SHFT       0
+#define PRLC_GCLK_EN_MASK       (UINT64_CAST 1)
+#define PRLC_GCLK_EN            (UINT64_CAST 1)
+
+/* PI_RT_FILTER_CTRL mask and shift definitions */
+
+/*
+ * Bits for NACK_CNT_A/B and NACK_CMP
+ */
+#define PI_NACK_CNT_EN_SHFT     20
+#define PI_NACK_CNT_EN_MASK     0x100000
+#define PI_NACK_CNT_MASK        0x0fffff
+#define PI_NACK_CNT_MAX         0x0fffff
+
+#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/arch/mips/include/asm/sn/sn0/kldir.h b/arch/mips/include/asm/sn/sn0/kldir.h
new file mode 100644
index 000000000..1b10af6cb
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/kldir.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_KLDIR_H
+#define _ASM_SN_SN0_KLDIR_H
+
+
+/*
+ * The kldir memory area resides at a fixed place in each node's memory and
+ * provides pointers to most other IP27 memory areas.  This allows us to
+ * resize and/or relocate memory areas at a later time without breaking all
+ * firmware and kernels that use them.  Indices in the array are
+ * permanently dedicated to areas listed below.  Some memory areas (marked
+ * below) reside at a permanently fixed location, but are included in the
+ * directory for completeness.
+ */
+
+/*
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)         +-----------------------------------------+
+ *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)         +-----------------------------------------+
+ *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)         +-----------------------------------------+
+ *                         |      IP27 CFG                           |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Graphics PROM                      |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)         +-----------------------------------------+
+ *                         |      SYMMON                             |
+ *                         |      (For UNIX Debug only)              |
+ * 0x34000 (208K)          +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x25000 (148K)          +-----------------------------------------+
+ *                         |      KLCONFIG - II (temp)               |
+ *                         |                                         |
+ *                         |    ----------------------------         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP27PROM, IO6PROM and IRIX.
+ *
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (32K)              |
+ *                         |                                         |
+ * 0x12000 (72K)           +-----------------------------------------+
+ *                         |      Unused                             |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Eframe area              |
+ * 0x11a00 (70.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Eframe area              |
+ * 0x11800 (70K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x11000 (68K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x10800  (66k)          +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      KLCONFIG - I (permanent) (48K)     |
+ *                         |                                         |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x4000 (16K)            +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)            +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)            +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)            +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)             +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)             +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)             +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x800  (2k)             +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x400 (1K)              +-----------------------------------------+
+ *                         |      Exception Handlers                 |
+ * 0x0   (0K)              +-----------------------------------------+
+ */
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE               0x8000
+
+#if defined(PROM)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP27
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET              0x2400
+#define IP27_LAUNCH_SIZE                0x400
+#define IP27_LAUNCH_COUNT               2
+#define IP27_LAUNCH_STRIDE              0x200
+
+#define IP27_KLCONFIG_OFFSET            0x4000
+#define IP27_KLCONFIG_SIZE              0xc000
+#define IP27_KLCONFIG_COUNT             1
+#define IP27_KLCONFIG_STRIDE            0
+
+#define IP27_NMI_OFFSET                 0x3000
+#define IP27_NMI_SIZE                   0x40
+#define IP27_NMI_COUNT                  2
+#define IP27_NMI_STRIDE                 0x40
+
+#define IP27_PI_ERROR_OFFSET            0x12000
+#define IP27_PI_ERROR_SIZE              0x4000
+#define IP27_PI_ERROR_COUNT             1
+#define IP27_PI_ERROR_STRIDE            0
+
+#define IP27_SYMMON_STK_OFFSET          0x25000
+#define IP27_SYMMON_STK_SIZE            0xe000
+#define IP27_SYMMON_STK_COUNT           2
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE          0x7000
+
+#define IP27_FREEMEM_OFFSET             0x19000
+#define IP27_FREEMEM_SIZE               -1
+#define IP27_FREEMEM_COUNT              1
+#define IP27_FREEMEM_STRIDE             0
+
+#endif /* PROM */
+/*
+ * There will be only one of these in a partition so the IO6 must set it up.
+ */
+#define IO6_GDA_OFFSET                  0x11000
+#define IO6_GDA_SIZE                    0x400
+#define IO6_GDA_COUNT                   1
+#define IO6_GDA_STRIDE                  0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET           0x11400
+#define IP27_NMI_KREGS_CPU_SIZE         0x200
+/*
+ * save area of kernel nmi regs in eframe format
+ */
+#define IP27_NMI_EFRAME_OFFSET          0x11800
+#define IP27_NMI_EFRAME_SIZE            0x200
+
+#endif /* _ASM_SN_SN0_KLDIR_H */
diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
new file mode 100644
index 000000000..451ba1ee4
--- /dev/null
+++ b/arch/mips/include/asm/sn/types.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_TYPES_H
+#define _ASM_SN_TYPES_H
+
+#include <linux/types.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long   cpuid_t;
+typedef signed short    nasid_t;        /* node id in numa-as-id space */
+typedef signed char     partid_t;       /* partition ID type */
+typedef signed short    moduleid_t;     /* user-visible module number type */
+
+typedef dev_t           vertex_hdl_t;   /* hardware graph vertex handle */
+
+#endif
+
+#endif /* _ASM_SN_TYPES_H */
diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h
new file mode 100644
index 000000000..7dfa297ce
--- /dev/null
+++ b/arch/mips/include/asm/sni.h
@@ -0,0 +1,246 @@
+/*
+ * SNI specific definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998 by Ralf Baechle
+ * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ */
+#ifndef __ASM_SNI_H
+#define __ASM_SNI_H
+
+#include <linux/irqreturn.h>
+
+extern unsigned int sni_brd_type;
+
+#define SNI_BRD_10                 2
+#define SNI_BRD_10NEW              3
+#define SNI_BRD_TOWER_OASIC        4
+#define SNI_BRD_MINITOWER          5
+#define SNI_BRD_PCI_TOWER          6
+#define SNI_BRD_RM200              7
+#define SNI_BRD_PCI_MTOWER         8
+#define SNI_BRD_PCI_DESKTOP        9
+#define SNI_BRD_PCI_TOWER_CPLUS   10
+#define SNI_BRD_PCI_MTOWER_CPLUS  11
+
+/* RM400 cpu types */
+#define SNI_CPU_M8021           0x01
+#define SNI_CPU_M8030           0x04
+#define SNI_CPU_M8031           0x06
+#define SNI_CPU_M8034           0x0f
+#define SNI_CPU_M8037           0x07
+#define SNI_CPU_M8040           0x05
+#define SNI_CPU_M8043           0x09
+#define SNI_CPU_M8050           0x0b
+#define SNI_CPU_M8053           0x0d
+
+#define SNI_PORT_BASE           CKSEG1ADDR(0xb4000000)
+
+#ifndef __MIPSEL__
+/*
+ * ASIC PCI registers for big endian configuration.
+ */
+#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0004)
+#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff000c)
+#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0014)
+#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff001c)
+#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0024)
+#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff002c)
+#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0034)
+#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff003c)
+#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0044)
+#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff004c)
+#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0054)
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff005c)
+#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0064)
+#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff006c)
+#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0074)
+#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff007c)  /* read */
+#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff007c)  /* write */
+#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0084)
+#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff008c)
+#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0094)
+#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff009c)
+#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a4)
+#else
+/*
+ * ASIC PCI registers for little endian configuration.
+ */
+#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0000)
+#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff0008)
+#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0010)
+#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff0018)
+#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0020)
+#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff0028)
+#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0030)
+#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff0038)
+#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0040)
+#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff0048)
+#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0050)
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff0058)
+#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0060)
+#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff0068)
+#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0070)
+#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff0078)  /* read */
+#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff0078)  /* write */
+#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0080)
+#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff0088)
+#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0090)
+#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff0098)
+#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a0)
+#endif
+
+#define PCIMT_PCI_CONF          CKSEG1ADDR(0xbfff0100)
+
+/*
+ * Data port for the PCI bus in IO space
+ */
+#define PCIMT_CONFIG_DATA       0x0cfc
+
+/*
+ * Board specific registers
+ */
+#define PCIMT_CSMSR             CKSEG1ADDR(0xbfd00000)
+#define PCIMT_CSSWITCH          CKSEG1ADDR(0xbfd10000)
+#define PCIMT_CSITPEND          CKSEG1ADDR(0xbfd20000)
+#define PCIMT_AUTO_PO_EN        CKSEG1ADDR(0xbfd30000)
+#define PCIMT_CLR_TEMP          CKSEG1ADDR(0xbfd40000)
+#define PCIMT_AUTO_PO_DIS       CKSEG1ADDR(0xbfd50000)
+#define PCIMT_EXMSR             CKSEG1ADDR(0xbfd60000)
+#define PCIMT_UNUSED1           CKSEG1ADDR(0xbfd70000)
+#define PCIMT_CSWCSM            CKSEG1ADDR(0xbfd80000)
+#define PCIMT_UNUSED2           CKSEG1ADDR(0xbfd90000)
+#define PCIMT_CSLED             CKSEG1ADDR(0xbfda0000)
+#define PCIMT_CSMAPISA          CKSEG1ADDR(0xbfdb0000)
+#define PCIMT_CSRSTBP           CKSEG1ADDR(0xbfdc0000)
+#define PCIMT_CLRPOFF           CKSEG1ADDR(0xbfdd0000)
+#define PCIMT_CSTIMER           CKSEG1ADDR(0xbfde0000)
+#define PCIMT_PWDN              CKSEG1ADDR(0xbfdf0000)
+
+/*
+ * A20R based boards
+ */
+#define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
+#define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
+#define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
+
+#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
+#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
+
+#define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
+
+#define SNI_PCIT_INT_START      24
+#define SNI_PCIT_INT_END        30
+
+#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
+#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
+
+
+/*
+ * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
+ * to the other interrupts generated by ASIC PCI.
+ *
+ * INT2 is a wired-or of the push button interrupt, high temperature interrupt
+ * ASIC PCI interrupt.
+ */
+#define PCIMT_KEYBOARD_IRQ       1
+#define PCIMT_IRQ_INT2          24
+#define PCIMT_IRQ_INTD          25
+#define PCIMT_IRQ_INTC          26
+#define PCIMT_IRQ_INTB          27
+#define PCIMT_IRQ_INTA          28
+#define PCIMT_IRQ_EISA          29
+#define PCIMT_IRQ_SCSI          30
+
+#define PCIMT_IRQ_ETHERNET      (MIPS_CPU_IRQ_BASE+6)
+
+#if 0
+#define PCIMT_IRQ_TEMPERATURE   24
+#define PCIMT_IRQ_EISA_NMI      25
+#define PCIMT_IRQ_POWER_OFF     26
+#define PCIMT_IRQ_BUTTON        27
+#endif
+
+/*
+ * Base address for the mapped 16mb EISA bus segment.
+ */
+#define PCIMT_EISA_BASE         CKSEG1ADDR(0xb0000000)
+
+/* PCI EISA Interrupt acknowledge  */
+#define PCIMT_INT_ACKNOWLEDGE   CKSEG1ADDR(0xba000000)
+
+/*
+ *  SNI ID PROM
+ *
+ * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
+ * SNI_IDPROM_BRDTYPE  Board Type
+ * SNI_IDPROM_CPUTYPE  CPU Type on RM400
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __SNI_END 0
+#endif
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define __SNI_END 3
+#endif
+#define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
+#define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
+#define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
+#define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
+
+#define SNI_IDPROM_SIZE 0x1000
+
+/* board specific init functions */
+extern void sni_a20r_init(void);
+extern void sni_pcit_init(void);
+extern void sni_rm200_init(void);
+extern void sni_pcimt_init(void);
+
+/* board specific irq init functions */
+extern void sni_a20r_irq_init(void);
+extern void sni_pcit_irq_init(void);
+extern void sni_pcit_cplus_irq_init(void);
+extern void sni_rm200_irq_init(void);
+extern void sni_pcimt_irq_init(void);
+
+/* timer inits */
+extern void sni_cpu_time_init(void);
+
+/* eisa init for RM200/400 */
+#ifdef CONFIG_EISA
+extern int sni_eisa_root_init(void);
+#else
+static inline int sni_eisa_root_init(void)
+{
+        return 0;
+}
+#endif
+
+/* common irq stuff */
+extern void (*sni_hwint)(void);
+extern irqreturn_t sni_isa_irq_handler(int dummy, void *p);
+
+#endif /* __ASM_SNI_H */
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
new file mode 100644
index 000000000..4724a563c
--- /dev/null
+++ b/arch/mips/include/asm/socket.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <uapi/asm/socket.h>
+
+
+/** sock_type - Socket types
+ *
+ * Please notice that for binary compat reasons MIPS has to
+ * override the enum sock_type in include/linux/net.h, so
+ * we define ARCH_HAS_SOCKET_TYPES here.
+ *
+ * @SOCK_DGRAM - datagram (conn.less) socket
+ * @SOCK_STREAM - stream (connection) socket
+ * @SOCK_RAW - raw socket
+ * @SOCK_RDM - reliably-delivered message
+ * @SOCK_SEQPACKET - sequential packet socket
+ * @SOCK_PACKET - linux specific way of getting packets at the dev level.
+ *                For writing rarp and other similar things on the user level.
+ */
+enum sock_type {
+        SOCK_DGRAM      = 1,
+        SOCK_STREAM     = 2,
+        SOCK_RAW        = 3,
+        SOCK_RDM        = 4,
+        SOCK_SEQPACKET  = 5,
+        SOCK_DCCP       = 6,
+        SOCK_PACKET     = 10,
+};
+
+#define SOCK_MAX (SOCK_PACKET + 1)
+/* Mask which covers at least up to SOCK_MASK-1.  The
+ *  * remaining bits are used as flags. */
+#define SOCK_TYPE_MASK 0xf
+
+/* Flags for socket, socketpair, paccept */
+#define SOCK_CLOEXEC    O_CLOEXEC
+#define SOCK_NONBLOCK   O_NONBLOCK
+
+#define ARCH_HAS_SOCKET_TYPES 1
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
new file mode 100644
index 000000000..b0686ca3d
--- /dev/null
+++ b/arch/mips/include/asm/sparsemem.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MIPS_SPARSEMEM_H
+#define _MIPS_SPARSEMEM_H
+#ifdef CONFIG_SPARSEMEM
+
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
+# define SECTION_SIZE_BITS      29
+#else
+# define SECTION_SIZE_BITS      28
+#endif
+#define MAX_PHYSMEM_BITS        48
+
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _MIPS_SPARSEMEM_H */
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
new file mode 100644
index 000000000..8a88eb265
--- /dev/null
+++ b/arch/mips/include/asm/spinlock.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SPINLOCK_H
+#define _ASM_SPINLOCK_H
+
+#include <asm/processor.h>
+#include <asm/qrwlock.h>
+
+#include <asm-generic/qspinlock_types.h>
+
+#define queued_spin_unlock queued_spin_unlock
+/**
+ * queued_spin_unlock - release a queued spinlock
+ * @lock : Pointer to queued spinlock structure
+ */
+static inline void queued_spin_unlock(struct qspinlock *lock)
+{
+        /* This could be optimised with ARCH_HAS_MMIOWB */
+        mmiowb();
+        smp_store_release(&lock->locked, 0);
+}
+
+#include <asm/qspinlock.h>
+
+#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
new file mode 100644
index 000000000..28fd4b140
--- /dev/null
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_SPINLOCK_TYPES_H
+#define _ASM_SPINLOCK_TYPES_H
+
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
+
+#endif
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
new file mode 100644
index 000000000..63cb90fd4
--- /dev/null
+++ b/arch/mips/include/asm/spram.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MIPS_SPRAM_H
+#define _MIPS_SPRAM_H
+
+#if defined(CONFIG_MIPS_SPRAM)
+extern __init void spram_config(void);
+#else
+static inline void spram_config(void) { };
+#endif /* CONFIG_MIPS_SPRAM */
+
+#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
new file mode 100644
index 000000000..aa430a6c6
--- /dev/null
+++ b/arch/mips/include/asm/stackframe.h
@@ -0,0 +1,492 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_STACKFRAME_H
+#define _ASM_STACKFRAME_H
+
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+
+/* Make the addition of cfi info a little easier. */
+        .macro cfi_rel_offset reg offset=0 docfi=0
+        .if \docfi
+        .cfi_rel_offset \reg, \offset
+        .endif
+        .endm
+
+        .macro cfi_st reg offset=0 docfi=0
+        LONG_S  \reg, \offset(sp)
+        cfi_rel_offset \reg, \offset, \docfi
+        .endm
+
+        .macro cfi_restore reg offset=0 docfi=0
+        .if \docfi
+        .cfi_restore \reg
+        .endif
+        .endm
+
+        .macro cfi_ld reg offset=0 docfi=0
+        LONG_L  \reg, \offset(sp)
+        cfi_restore \reg \offset \docfi
+        .endm
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#define STATMASK 0x3f
+#else
+#define STATMASK 0x1f
+#endif
+
+                .macro  SAVE_AT docfi=0
+                .set    push
+                .set    noat
+                cfi_st  $1, PT_R1, \docfi
+                .set    pop
+                .endm
+
+                .macro  SAVE_TEMP docfi=0
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+                mflhxu  v1
+                LONG_S  v1, PT_LO(sp)
+                mflhxu  v1
+                LONG_S  v1, PT_HI(sp)
+                mflhxu  v1
+                LONG_S  v1, PT_ACX(sp)
+#elif !defined(CONFIG_CPU_MIPSR6)
+                mfhi    v1
+#endif
+#ifdef CONFIG_32BIT
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
+#endif
+                cfi_st  $10, PT_R10, \docfi
+                cfi_st  $11, PT_R11, \docfi
+                cfi_st  $12, PT_R12, \docfi
+#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
+                LONG_S  v1, PT_HI(sp)
+                mflo    v1
+#endif
+                cfi_st  $13, PT_R13, \docfi
+                cfi_st  $14, PT_R14, \docfi
+                cfi_st  $15, PT_R15, \docfi
+                cfi_st  $24, PT_R24, \docfi
+#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
+                LONG_S  v1, PT_LO(sp)
+#endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+                /*
+                 * The Octeon multiplier state is affected by general
+                 * multiply instructions. It must be saved before and
+                 * kernel code might corrupt it
+                 */
+                jal     octeon_mult_save
+#endif
+                .endm
+
+                .macro  SAVE_STATIC docfi=0
+                cfi_st  $16, PT_R16, \docfi
+                cfi_st  $17, PT_R17, \docfi
+                cfi_st  $18, PT_R18, \docfi
+                cfi_st  $19, PT_R19, \docfi
+                cfi_st  $20, PT_R20, \docfi
+                cfi_st  $21, PT_R21, \docfi
+                cfi_st  $22, PT_R22, \docfi
+                cfi_st  $23, PT_R23, \docfi
+                cfi_st  $30, PT_R30, \docfi
+                .endm
+
+/*
+ * get_saved_sp returns the SP for the current CPU by looking in the
+ * kernelsp array for it.  If tosp is set, it stores the current sp in
+ * k0 and loads the new value in sp.  If not, it clobbers k0 and
+ * stores the new value in k1, leaving sp unaffected.
+ */
+#ifdef CONFIG_SMP
+
+                /* SMP variation */
+                .macro  get_saved_sp docfi=0 tosp=0
+                ASM_CPUID_MFC0  k0, ASM_SMP_CPUID_REG
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+                lui     k1, %hi(kernelsp)
+#else
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, 16
+#endif
+                LONG_SRL        k0, SMP_CPUID_PTRSHIFT
+                LONG_ADDU       k1, k0
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
+                LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+                ASM_CPUID_MFC0  \temp, ASM_SMP_CPUID_REG
+                LONG_SRL        \temp, SMP_CPUID_PTRSHIFT
+                LONG_S  \stackp, kernelsp(\temp)
+                .endm
+#else /* !CONFIG_SMP */
+                /* Uniprocessor variation */
+                .macro  get_saved_sp docfi=0 tosp=0
+#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
+                /*
+                 * Clear BTB (branch target buffer), forbid RAS (return address
+                 * stack) to workaround the Out-of-order Issue in Loongson2F
+                 * via its diagnostic register.
+                 */
+                move    k0, ra
+                jal     1f
+                 nop
+1:              jal     1f
+                 nop
+1:              jal     1f
+                 nop
+1:              jal     1f
+                 nop
+1:              move    ra, k0
+                li      k0, 3
+                mtc0    k0, $22
+#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+                lui     k1, %hi(kernelsp)
+#else
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, k1, 16
+#endif
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
+                LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+                LONG_S  \stackp, kernelsp
+                .endm
+#endif
+
+                .macro  SAVE_SOME docfi=0
+                .set    push
+                .set    noat
+                .set    reorder
+                mfc0    k0, CP0_STATUS
+                sll     k0, 3           /* extract cu0 bit */
+                .set    noreorder
+                bltz    k0, 8f
+                 move   k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+#ifdef CONFIG_EVA
+                /*
+                 * Flush interAptiv's Return Prediction Stack (RPS) by writing
+                 * EntryHi. Toggling Config7.RPS is slower and less portable.
+                 *
+                 * The RPS isn't automatically flushed when exceptions are
+                 * taken, which can result in kernel mode speculative accesses
+                 * to user addresses if the RPS mispredicts. That's harmless
+                 * when user and kernel share the same address space, but with
+                 * EVA the same user segments may be unmapped to kernel mode,
+                 * even containing sensitive MMIO regions or invalid memory.
+                 *
+                 * This can happen when the kernel sets the return address to
+                 * ret_from_* and jr's to the exception handler, which looks
+                 * more like a tail call than a function call. If nested calls
+                 * don't evict the last user address in the RPS, it will
+                 * mispredict the return and fetch from a user controlled
+                 * address into the icache.
+                 *
+                 * More recent EVA-capable cores with MAAR to restrict
+                 * speculative accesses aren't affected.
+                 */
+                MFC0    k0, CP0_ENTRYHI
+                MTC0    k0, CP0_ENTRYHI
+#endif
+                .set    reorder
+                /* Called from user mode, new stack. */
+                get_saved_sp docfi=\docfi tosp=1
+8:
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+                .set    at=k1
+#endif
+                PTR_SUBU sp, PT_SIZE
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+                .set    noat
+#endif
+                .if \docfi
+                .cfi_def_cfa sp,0
+                .endif
+                cfi_st  k0, PT_R29, \docfi
+                cfi_rel_offset  sp, PT_R29, \docfi
+                cfi_st  v1, PT_R3, \docfi
+                /*
+                 * You might think that you don't need to save $0,
+                 * but the FPU emulator and gdb remote debug stub
+                 * need it to operate correctly
+                 */
+                LONG_S  $0, PT_R0(sp)
+                mfc0    v1, CP0_STATUS
+                cfi_st  v0, PT_R2, \docfi
+                LONG_S  v1, PT_STATUS(sp)
+                cfi_st  $4, PT_R4, \docfi
+                mfc0    v1, CP0_CAUSE
+                cfi_st  $5, PT_R5, \docfi
+                LONG_S  v1, PT_CAUSE(sp)
+                cfi_st  $6, PT_R6, \docfi
+                cfi_st  ra, PT_R31, \docfi
+                MFC0    ra, CP0_EPC
+                cfi_st  $7, PT_R7, \docfi
+#ifdef CONFIG_64BIT
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
+#endif
+                LONG_S  ra, PT_EPC(sp)
+                .if \docfi
+                .cfi_rel_offset ra, PT_EPC
+                .endif
+                cfi_st  $25, PT_R25, \docfi
+                cfi_st  $28, PT_R28, \docfi
+
+                /* Set thread_info if we're coming from user mode */
+                mfc0    k0, CP0_STATUS
+                sll     k0, 3           /* extract cu0 bit */
+                bltz    k0, 9f
+
+                ori     $28, sp, _THREAD_MASK
+                xori    $28, _THREAD_MASK
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+                .set    mips64
+                pref    0, 0($28)       /* Prefetch the current pointer */
+#endif
+9:
+                .set    pop
+                .endm
+
+                .macro  SAVE_ALL docfi=0
+                SAVE_SOME \docfi
+                SAVE_AT \docfi
+                SAVE_TEMP \docfi
+                SAVE_STATIC \docfi
+                .endm
+
+                .macro  RESTORE_AT docfi=0
+                .set    push
+                .set    noat
+                cfi_ld  $1, PT_R1, \docfi
+                .set    pop
+                .endm
+
+                .macro  RESTORE_TEMP docfi=0
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+                /* Restore the Octeon multiplier state */
+                jal     octeon_mult_restore
+#endif
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_L  $24, PT_ACX(sp)
+                mtlhx   $24
+                LONG_L  $24, PT_HI(sp)
+                mtlhx   $24
+                LONG_L  $24, PT_LO(sp)
+                mtlhx   $24
+#elif !defined(CONFIG_CPU_MIPSR6)
+                LONG_L  $24, PT_LO(sp)
+                mtlo    $24
+                LONG_L  $24, PT_HI(sp)
+                mthi    $24
+#endif
+#ifdef CONFIG_32BIT
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
+#endif
+                cfi_ld  $10, PT_R10, \docfi
+                cfi_ld  $11, PT_R11, \docfi
+                cfi_ld  $12, PT_R12, \docfi
+                cfi_ld  $13, PT_R13, \docfi
+                cfi_ld  $14, PT_R14, \docfi
+                cfi_ld  $15, PT_R15, \docfi
+                cfi_ld  $24, PT_R24, \docfi
+                .endm
+
+                .macro  RESTORE_STATIC docfi=0
+                cfi_ld  $16, PT_R16, \docfi
+                cfi_ld  $17, PT_R17, \docfi
+                cfi_ld  $18, PT_R18, \docfi
+                cfi_ld  $19, PT_R19, \docfi
+                cfi_ld  $20, PT_R20, \docfi
+                cfi_ld  $21, PT_R21, \docfi
+                cfi_ld  $22, PT_R22, \docfi
+                cfi_ld  $23, PT_R23, \docfi
+                cfi_ld  $30, PT_R30, \docfi
+                .endm
+
+                .macro  RESTORE_SP docfi=0
+                cfi_ld  sp, PT_R29, \docfi
+                .endm
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+                .macro  RESTORE_SOME docfi=0
+                .set    push
+                .set    reorder
+                .set    noat
+                mfc0    a0, CP0_STATUS
+                li      v1, ST0_CU1 | ST0_IM
+                ori     a0, STATMASK
+                xori    a0, STATMASK
+                mtc0    a0, CP0_STATUS
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET docfi=0
+                .set    push
+                .set    noreorder
+                LONG_L  k0, PT_EPC(sp)
+                RESTORE_SP \docfi
+                jr      k0
+                 rfe
+                .set    pop
+                .endm
+
+#else
+                .macro  RESTORE_SOME docfi=0
+                .set    push
+                .set    reorder
+                .set    noat
+                mfc0    a0, CP0_STATUS
+                ori     a0, STATMASK
+                xori    a0, STATMASK
+                mtc0    a0, CP0_STATUS
+                li      v1, ST0_CU1 | ST0_FR | ST0_IM
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+                LONG_L  v1, PT_EPC(sp)
+                MTC0    v1, CP0_EPC
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
+#ifdef CONFIG_64BIT
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
+#endif
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET docfi=0
+                RESTORE_SP \docfi
+#if defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
+                eretnc
+#else
+                .set    push
+                .set    arch=r4000
+                eret
+                .set    pop
+#endif
+                .endm
+
+#endif
+
+                .macro  RESTORE_ALL docfi=0
+                RESTORE_TEMP \docfi
+                RESTORE_STATIC \docfi
+                RESTORE_AT \docfi
+                RESTORE_SOME \docfi
+                RESTORE_SP \docfi
+                .endm
+
+/*
+ * Move to kernel mode and disable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  CLI
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_KERNEL_CUMASK | STATMASK
+                or      t0, t1
+                xori    t0, STATMASK
+                mtc0    t0, CP0_STATUS
+                irq_disable_hazard
+                .endm
+
+/*
+ * Move to kernel mode and enable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  STI
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_KERNEL_CUMASK | STATMASK
+                or      t0, t1
+                xori    t0, STATMASK & ~1
+                mtc0    t0, CP0_STATUS
+                irq_enable_hazard
+                .endm
+
+/*
+ * Just move to kernel mode and leave interrupts as they are.  Note
+ * for the R3000 this means copying the previous enable from IEp.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  KMODE
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_KERNEL_CUMASK | (STATMASK & ~1)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+                andi    t2, t0, ST0_IEP
+                srl     t2, 2
+                or      t0, t2
+#endif
+                or      t0, t1
+                xori    t0, STATMASK & ~1
+                mtc0    t0, CP0_STATUS
+                irq_disable_hazard
+                .endm
+
+#endif /* _ASM_STACKFRAME_H */
diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h
new file mode 100644
index 000000000..68d4be9e1
--- /dev/null
+++ b/arch/mips/include/asm/stackprotector.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * GCC stack protector support.
+ *
+ * (This is directly adopted from the ARM implementation)
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on MIPS.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+        unsigned long canary;
+
+        /* Try to get a semi random initial value. */
+        get_random_bytes(&canary, sizeof(canary));
+        canary ^= LINUX_VERSION_CODE;
+
+        current->stack_canary = canary;
+        __stack_chk_guard = current->stack_canary;
+}
+
+#endif  /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h
new file mode 100644
index 000000000..8ad25c25b
--- /dev/null
+++ b/arch/mips/include/asm/stacktrace.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_STACKTRACE_H
+#define _ASM_STACKTRACE_H
+
+#include <asm/ptrace.h>
+#include <asm/asm.h>
+#include <linux/stringify.h>
+
+#ifdef CONFIG_KALLSYMS
+extern int raw_show_trace;
+extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+                                  unsigned long pc, unsigned long *ra);
+extern unsigned long unwind_stack_by_address(unsigned long stack_page,
+                                             unsigned long *sp,
+                                             unsigned long pc,
+                                             unsigned long *ra);
+#else
+#define raw_show_trace 1
+static inline unsigned long unwind_stack(struct task_struct *task,
+        unsigned long *sp, unsigned long pc, unsigned long *ra)
+{
+        return 0;
+}
+#endif
+
+#define STR_PTR_LA    __stringify(PTR_LA)
+#define STR_LONG_S    __stringify(LONG_S)
+#define STR_LONG_L    __stringify(LONG_L)
+#define STR_LONGSIZE  __stringify(LONGSIZE)
+
+#define STORE_ONE_REG(r) \
+    STR_LONG_S   " $" __stringify(r)",("STR_LONGSIZE"*"__stringify(r)")(%1)\n\t"
+
+static __always_inline void prepare_frametrace(struct pt_regs *regs)
+{
+#ifndef CONFIG_KALLSYMS
+        /*
+         * Remove any garbage that may be in regs (specially func
+         * addresses) to avoid show_raw_backtrace() to report them
+         */
+        memset(regs, 0, sizeof(*regs));
+#endif
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noat\n\t"
+                /* Store $1 so we can use it */
+                STR_LONG_S " $1,"STR_LONGSIZE"(%1)\n\t"
+                /* Store the PC */
+                "1: " STR_PTR_LA " $1, 1b\n\t"
+                STR_LONG_S " $1,%0\n\t"
+                STORE_ONE_REG(2)
+                STORE_ONE_REG(3)
+                STORE_ONE_REG(4)
+                STORE_ONE_REG(5)
+                STORE_ONE_REG(6)
+                STORE_ONE_REG(7)
+                STORE_ONE_REG(8)
+                STORE_ONE_REG(9)
+                STORE_ONE_REG(10)
+                STORE_ONE_REG(11)
+                STORE_ONE_REG(12)
+                STORE_ONE_REG(13)
+                STORE_ONE_REG(14)
+                STORE_ONE_REG(15)
+                STORE_ONE_REG(16)
+                STORE_ONE_REG(17)
+                STORE_ONE_REG(18)
+                STORE_ONE_REG(19)
+                STORE_ONE_REG(20)
+                STORE_ONE_REG(21)
+                STORE_ONE_REG(22)
+                STORE_ONE_REG(23)
+                STORE_ONE_REG(24)
+                STORE_ONE_REG(25)
+                STORE_ONE_REG(26)
+                STORE_ONE_REG(27)
+                STORE_ONE_REG(28)
+                STORE_ONE_REG(29)
+                STORE_ONE_REG(30)
+                STORE_ONE_REG(31)
+                /* Restore $1 */
+                STR_LONG_L " $1,"STR_LONGSIZE"(%1)\n\t"
+                ".set pop\n\t"
+                : "=m" (regs->cp0_epc)
+                : "r" (regs->regs)
+                : "memory");
+}
+
+#endif /* _ASM_STACKTRACE_H */
diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
new file mode 100644
index 000000000..1de3bbce8
--- /dev/null
+++ b/arch/mips/include/asm/string.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#endif /* _ASM_STRING_H */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
new file mode 100644
index 000000000..a4374b4cb
--- /dev/null
+++ b/arch/mips/include/asm/switch_to.h
@@ -0,0 +1,142 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SWITCH_TO_H
+#define _ASM_SWITCH_TO_H
+
+#include <asm/cpu-features.h>
+#include <asm/watch.h>
+#include <asm/dsp.h>
+#include <asm/cop2.h>
+#include <asm/fpu.h>
+
+struct task_struct;
+
+/**
+ * resume - resume execution of a task
+ * @prev:       The task previously executed.
+ * @next:       The task to begin executing.
+ * @next_ti:    task_thread_info(next).
+ *
+ * This function is used whilst scheduling to save the context of prev & load
+ * the context of next. Returns prev.
+ */
+extern asmlinkage struct task_struct *resume(struct task_struct *prev,
+                struct task_struct *next, struct thread_info *next_ti);
+
+extern unsigned int ll_bit;
+extern struct task_struct *ll_task;
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+
+/*
+ * Handle the scheduler resume end of FPU affinity management.  We do this
+ * inline to try to keep the overhead down. If we have been forced to run on
+ * a "CPU" with an FPU because of a previous high level of FP computation,
+ * but did not actually use the FPU during the most recent time-slice (CU1
+ * isn't set), we undo the restriction on cpus_mask.
+ *
+ * We're not calling set_cpus_allowed() here, because we have no need to
+ * force prompt migration - we're already switching the current CPU to a
+ * different thread.
+ */
+
+#define __mips_mt_fpaff_switch_to(prev)                                 \
+do {                                                                    \
+        struct thread_info *__prev_ti = task_thread_info(prev);         \
+                                                                        \
+        if (cpu_has_fpu &&                                              \
+            test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
+            (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
+                clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
+                prev->cpus_mask = prev->thread.user_cpus_allowed;       \
+        }                                                               \
+        next->thread.emulated_fp = 0;                                   \
+} while(0)
+
+#else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
+
+/*
+ * Clear LLBit during context switches on MIPSr5+ such that eretnc can be used
+ * unconditionally when returning to userland in entry.S.
+ */
+#define __clear_r5_hw_ll_bit() do {                                     \
+        if (cpu_has_mips_r5 || cpu_has_mips_r6)                         \
+                write_c0_lladdr(0);                                     \
+} while (0)
+
+#define __clear_software_ll_bit() do {                                  \
+        if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)       \
+                ll_bit = 0;                                             \
+} while (0)
+
+/*
+ * Check FCSR for any unmasked exceptions pending set with `ptrace',
+ * clear them and send a signal.
+ */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+# define __sanitize_fcr31(next)                                         \
+do {                                                                    \
+        unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31);     \
+        void __user *pc;                                                \
+                                                                        \
+        if (unlikely(fcr31)) {                                          \
+                pc = (void __user *)task_pt_regs(next)->cp0_epc;        \
+                next->thread.fpu.fcr31 &= ~fcr31;                       \
+                force_fcr31_sig(fcr31, pc, next);                       \
+        }                                                               \
+} while (0)
+#else
+# define __sanitize_fcr31(next)
+#endif
+
+/*
+ * For newly created kernel threads switch_to() will return to
+ * ret_from_kernel_thread, newly created user threads to ret_from_fork.
+ * That is, everything following resume() will be skipped for new threads.
+ * So everything that matters to new threads should be placed before resume().
+ */
+#define switch_to(prev, next, last)                                     \
+do {                                                                    \
+        __mips_mt_fpaff_switch_to(prev);                                \
+        lose_fpu_inatomic(1, prev);                                     \
+        if (tsk_used_math(next))                                        \
+                __sanitize_fcr31(next);                                 \
+        if (cpu_has_dsp) {                                              \
+                __save_dsp(prev);                                       \
+                __restore_dsp(next);                                    \
+        }                                                               \
+        if (cop2_present) {                                             \
+                u32 status = read_c0_status();                          \
+                                                                        \
+                set_c0_status(ST0_CU2);                                 \
+                if ((KSTK_STATUS(prev) & ST0_CU2)) {                    \
+                        if (cop2_lazy_restore)                          \
+                                KSTK_STATUS(prev) &= ~ST0_CU2;          \
+                        cop2_save(prev);                                \
+                }                                                       \
+                if (KSTK_STATUS(next) & ST0_CU2 &&                      \
+                    !cop2_lazy_restore) {                               \
+                        cop2_restore(next);                             \
+                }                                                       \
+                write_c0_status(status);                                \
+        }                                                               \
+        __clear_r5_hw_ll_bit();                                         \
+        __clear_software_ll_bit();                                      \
+        if (cpu_has_userlocal)                                          \
+                write_c0_userlocal(task_thread_info(next)->tp_value);   \
+        __restore_watch(next);                                          \
+        (last) = resume(prev, next, task_thread_info(next));            \
+} while (0)
+
+#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
new file mode 100644
index 000000000..aabd09793
--- /dev/null
+++ b/arch/mips/include/asm/sync.h
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __MIPS_ASM_SYNC_H__
+#define __MIPS_ASM_SYNC_H__
+
+/*
+ * sync types are defined by the MIPS64 Instruction Set documentation in Volume
+ * II-A of the MIPS Architecture Reference Manual, which can be found here:
+ *
+ *   https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06
+ *
+ * Two types of barrier are provided:
+ *
+ *   1) Completion barriers, which ensure that a memory operation has actually
+ *      completed & often involve stalling the CPU pipeline to do so.
+ *
+ *   2) Ordering barriers, which only ensure that affected memory operations
+ *      won't be reordered in the CPU pipeline in a manner that violates the
+ *      restrictions imposed by the barrier.
+ *
+ * Ordering barriers can be more efficient than completion barriers, since:
+ *
+ *   a) Ordering barriers only require memory access instructions which preceed
+ *      them in program order (older instructions) to reach a point in the
+ *      load/store datapath beyond which reordering is not possible before
+ *      allowing memory access instructions which follow them (younger
+ *      instructions) to be performed.  That is, older instructions don't
+ *      actually need to complete - they just need to get far enough that all
+ *      other coherent CPUs will observe their completion before they observe
+ *      the effects of younger instructions.
+ *
+ *   b) Multiple variants of ordering barrier are provided which allow the
+ *      effects to be restricted to different combinations of older or younger
+ *      loads or stores. By way of example, if we only care that stores older
+ *      than a barrier are observed prior to stores that are younger than a
+ *      barrier & don't care about the ordering of loads then the 'wmb'
+ *      ordering barrier can be used. Limiting the barrier's effects to stores
+ *      allows loads to continue unaffected & potentially allows the CPU to
+ *      make progress faster than if younger loads had to wait for older stores
+ *      to complete.
+ */
+
+/*
+ * No sync instruction at all; used to allow code to nullify the effect of the
+ * __SYNC() macro without needing lots of #ifdefery.
+ */
+#define __SYNC_none     -1
+
+/*
+ * A full completion barrier; all memory accesses appearing prior to this sync
+ * instruction in program order must complete before any memory accesses
+ * appearing after this sync instruction in program order.
+ */
+#define __SYNC_full     0x00
+
+/*
+ * For now we use a full completion barrier to implement all sync types, until
+ * we're satisfied that lightweight ordering barriers defined by MIPSr6 are
+ * sufficient to uphold our desired memory model.
+ */
+#define __SYNC_aq       __SYNC_full
+#define __SYNC_rl       __SYNC_full
+#define __SYNC_mb       __SYNC_full
+
+/*
+ * ...except on Cavium Octeon CPUs, which have been using the 'wmb' ordering
+ * barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform
+ * speculative reads.
+ */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+# define __SYNC_rmb     __SYNC_none
+# define __SYNC_wmb     0x04
+#else
+# define __SYNC_rmb     __SYNC_full
+# define __SYNC_wmb     __SYNC_full
+#endif
+
+/*
+ * A GINV sync is a little different; it doesn't relate directly to loads or
+ * stores, but instead causes synchronization of an icache or TLB global
+ * invalidation operation triggered by the ginvi or ginvt instructions
+ * respectively. In cases where we need to know that a ginvi or ginvt operation
+ * has been performed by all coherent CPUs, we must issue a sync instruction of
+ * this type. Once this instruction graduates all coherent CPUs will have
+ * observed the invalidation.
+ */
+#define __SYNC_ginv     0x14
+
+/* Trivial; indicate that we always need this sync instruction. */
+#define __SYNC_always   (1 << 0)
+
+/*
+ * Indicate that we need this sync instruction only on systems with weakly
+ * ordered memory access. In general this is most MIPS systems, but there are
+ * exceptions which provide strongly ordered memory.
+ */
+#ifdef CONFIG_WEAK_ORDERING
+# define __SYNC_weak_ordering   (1 << 1)
+#else
+# define __SYNC_weak_ordering   0
+#endif
+
+/*
+ * Indicate that we need this sync instruction only on systems where LL/SC
+ * don't implicitly provide a memory barrier. In general this is most MIPS
+ * systems.
+ */
+#ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC
+# define __SYNC_weak_llsc       (1 << 2)
+#else
+# define __SYNC_weak_llsc       0
+#endif
+
+/*
+ * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
+ * store or prefetch) in between an LL & SC can cause the SC instruction to
+ * erroneously succeed, breaking atomicity. Whilst it's unusual to write code
+ * containing such sequences, this bug bites harder than we might otherwise
+ * expect due to reordering & speculation:
+ *
+ * 1) A memory access appearing prior to the LL in program order may actually
+ *    be executed after the LL - this is the reordering case.
+ *
+ *    In order to avoid this we need to place a memory barrier (ie. a SYNC
+ *    instruction) prior to every LL instruction, in between it and any earlier
+ *    memory access instructions.
+ *
+ *    This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
+ *
+ * 2) If a conditional branch exists between an LL & SC with a target outside
+ *    of the LL-SC loop, for example an exit upon value mismatch in cmpxchg()
+ *    or similar, then misprediction of the branch may allow speculative
+ *    execution of memory accesses from outside of the LL-SC loop.
+ *
+ *    In order to avoid this we need a memory barrier (ie. a SYNC instruction)
+ *    at each affected branch target.
+ *
+ *    This case affects all current Loongson 3 CPUs.
+ *
+ * The above described cases cause an error in the cache coherence protocol;
+ * such that the Invalidate of a competing LL-SC goes 'missing' and SC
+ * erroneously observes its core still has Exclusive state and lets the SC
+ * proceed.
+ *
+ * Therefore the error only occurs on SMP systems.
+ */
+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
+# define __SYNC_loongson3_war   (1 << 31)
+#else
+# define __SYNC_loongson3_war   0
+#endif
+
+/*
+ * Some Cavium Octeon CPUs suffer from a bug that causes a single wmb ordering
+ * barrier to be ineffective, requiring the use of 2 in sequence to provide an
+ * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use
+ * optimized memory barrier primitives."). Here we specify that the affected
+ * sync instructions should be emitted twice.
+ * Note that this expression is evaluated by the assembler (not the compiler),
+ * and that the assembler evaluates '==' as 0 or -1, not 0 or 1.
+ */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+# define __SYNC_rpt(type)       (1 - (type == __SYNC_wmb))
+#else
+# define __SYNC_rpt(type)       1
+#endif
+
+/*
+ * The main event. Here we actually emit a sync instruction of a given type, if
+ * reason is non-zero.
+ *
+ * In future we have the option of emitting entries in a fixups-style table
+ * here that would allow us to opportunistically remove some sync instructions
+ * when we detect at runtime that we're running on a CPU that doesn't need
+ * them.
+ */
+#ifdef CONFIG_CPU_HAS_SYNC
+# define ____SYNC(_type, _reason, _else)                        \
+        .if     (( _type ) != -1) && ( _reason );               \
+        .set    push;                                           \
+        .set    MIPS_ISA_LEVEL_RAW;                             \
+        .rept   __SYNC_rpt(_type);                              \
+        sync    _type;                                          \
+        .endr;                                                  \
+        .set    pop;                                            \
+        .else;                                                  \
+        _else;                                                  \
+        .endif
+#else
+# define ____SYNC(_type, _reason, _else)
+#endif
+
+/*
+ * Preprocessor magic to expand macros used as arguments before we insert them
+ * into assembly code.
+ */
+#ifdef __ASSEMBLY__
+# define ___SYNC(type, reason, else)                            \
+        ____SYNC(type, reason, else)
+#else
+# define ___SYNC(type, reason, else)                            \
+        __stringify(____SYNC(type, reason, else))
+#endif
+
+#define __SYNC(type, reason)                                    \
+        ___SYNC(__SYNC_##type, __SYNC_##reason, )
+#define __SYNC_ELSE(type, reason, else)                         \
+        ___SYNC(__SYNC_##type, __SYNC_##reason, else)
+
+#endif /* __MIPS_ASM_SYNC_H__ */
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
new file mode 100644
index 000000000..25fa651c9
--- /dev/null
+++ b/arch/mips/include/asm/syscall.h
@@ -0,0 +1,160 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ *
+ * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
+ */
+
+#ifndef __ASM_MIPS_SYSCALL_H
+#define __ASM_MIPS_SYSCALL_H
+
+#include <linux/compiler.h>
+#include <uapi/linux/audit.h>
+#include <linux/elf-em.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <asm/ptrace.h>
+#include <asm/unistd.h>
+
+#ifndef __NR_syscall /* Only defined if _MIPS_SIM == _MIPS_SIM_ABI32 */
+#define __NR_syscall 4000
+#endif
+
+static inline bool mips_syscall_is_indirect(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
+        return (IS_ENABLED(CONFIG_32BIT) ||
+                test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
+                (regs->regs[2] == __NR_syscall);
+}
+
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        return current_thread_info()->syscall;
+}
+
+static inline void mips_syscall_update_nr(struct task_struct *task,
+                                          struct pt_regs *regs)
+{
+        /*
+         * v0 is the system call number, except for O32 ABI syscall(), where it
+         * ends up in a0.
+         */
+        if (mips_syscall_is_indirect(task, regs))
+                task_thread_info(task)->syscall = regs->regs[4];
+        else
+                task_thread_info(task)->syscall = regs->regs[2];
+}
+
+static inline void mips_get_syscall_arg(unsigned long *arg,
+        struct task_struct *task, struct pt_regs *regs, unsigned int n)
+{
+        unsigned long usp __maybe_unused = regs->regs[29];
+
+        switch (n) {
+        case 0: case 1: case 2: case 3:
+                *arg = regs->regs[4 + n];
+
+                return;
+
+#ifdef CONFIG_32BIT
+        case 4: case 5: case 6: case 7:
+                get_user(*arg, (int *)usp + n);
+                return;
+#endif
+
+#ifdef CONFIG_64BIT
+        case 4: case 5: case 6: case 7:
+#ifdef CONFIG_MIPS32_O32
+                if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
+                        get_user(*arg, (int *)usp + n);
+                else
+#endif
+                        *arg = regs->regs[4 + n];
+
+                return;
+#endif
+
+        default:
+                BUG();
+        }
+
+        unreachable();
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        return regs->regs[7] ? -regs->regs[2] : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->regs[2];
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        /* Do nothing */
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        if (error) {
+                regs->regs[2] = -error;
+                regs->regs[7] = 1;
+        } else {
+                regs->regs[2] = val;
+                regs->regs[7] = 0;
+        }
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned long *args)
+{
+        unsigned int i = 0;
+        unsigned int n = 6;
+
+        /* O32 ABI syscall() */
+        if (mips_syscall_is_indirect(task, regs))
+                i++;
+
+        while (n--)
+                mips_get_syscall_arg(args++, task, regs, i++);
+}
+
+extern const unsigned long sys_call_table[];
+extern const unsigned long sys32_call_table[];
+extern const unsigned long sysn32_call_table[];
+
+static inline int syscall_get_arch(struct task_struct *task)
+{
+        int arch = AUDIT_ARCH_MIPS;
+#ifdef CONFIG_64BIT
+        if (!test_tsk_thread_flag(task, TIF_32BIT_REGS)) {
+                arch |= __AUDIT_ARCH_64BIT;
+                /* N32 sets only TIF_32BIT_ADDR */
+                if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
+                        arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
+        }
+#endif
+#if defined(__LITTLE_ENDIAN)
+        arch |=  __AUDIT_ARCH_LE;
+#endif
+        return arch;
+}
+
+#endif  /* __ASM_MIPS_SYSCALL_H */
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
new file mode 100644
index 000000000..bc29eeacc
--- /dev/null
+++ b/arch/mips/include/asm/termios.h
@@ -0,0 +1,105 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TERMIOS_H
+#define _ASM_TERMIOS_H
+
+#include <linux/uaccess.h>
+#include <uapi/asm/termios.h>
+
+/*
+ *      intr=^C         quit=^\         erase=del       kill=^U
+ *      vmin=\1         vtime=\0        eol2=\0         swtc=\0
+ *      start=^Q        stop=^S         susp=^Z         vdsusp=
+ *      reprint=^R      discard=^U      werase=^W       lnext=^V
+ *      eof=^D          eol=\0
+ */
+#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0"
+
+#include <linux/string.h>
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+static inline int user_termio_to_kernel_termios(struct ktermios *termios,
+        struct termio __user *termio)
+{
+        unsigned short iflag, oflag, cflag, lflag;
+        unsigned int err;
+
+        if (!access_ok(termio, sizeof(struct termio)))
+                return -EFAULT;
+
+        err = __get_user(iflag, &termio->c_iflag);
+        termios->c_iflag = (termios->c_iflag & 0xffff0000) | iflag;
+        err |=__get_user(oflag, &termio->c_oflag);
+        termios->c_oflag = (termios->c_oflag & 0xffff0000) | oflag;
+        err |=__get_user(cflag, &termio->c_cflag);
+        termios->c_cflag = (termios->c_cflag & 0xffff0000) | cflag;
+        err |=__get_user(lflag, &termio->c_lflag);
+        termios->c_lflag = (termios->c_lflag & 0xffff0000) | lflag;
+        err |=__get_user(termios->c_line, &termio->c_line);
+        if (err)
+                return -EFAULT;
+
+        if (__copy_from_user(termios->c_cc, termio->c_cc, NCC))
+                return -EFAULT;
+
+        return 0;
+}
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+static inline int kernel_termios_to_user_termio(struct termio __user *termio,
+        struct ktermios *termios)
+{
+        int err;
+
+        if (!access_ok(termio, sizeof(struct termio)))
+                return -EFAULT;
+
+        err = __put_user(termios->c_iflag, &termio->c_iflag);
+        err |= __put_user(termios->c_oflag, &termio->c_oflag);
+        err |= __put_user(termios->c_cflag, &termio->c_cflag);
+        err |= __put_user(termios->c_lflag, &termio->c_lflag);
+        err |= __put_user(termios->c_line, &termio->c_line);
+        if (err)
+                return -EFAULT;
+
+        if (__copy_to_user(termio->c_cc, termios->c_cc, NCC))
+                return -EFAULT;
+
+        return 0;
+}
+
+static inline int user_termios_to_kernel_termios(struct ktermios __user *k,
+        struct termios2 *u)
+{
+        return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0;
+}
+
+static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
+        struct ktermios *k)
+{
+        return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0;
+}
+
+static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
+        struct termios __user *u)
+{
+        return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0;
+}
+
+static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
+        struct ktermios *k)
+{
+        return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0;
+}
+
+#endif /* _ASM_TERMIOS_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
new file mode 100644
index 000000000..e2c352da3
--- /dev/null
+++ b/arch/mips/include/asm/thread_info.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* thread_info.h: MIPS low-level thread information
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+
+#ifndef __ASSEMBLY__
+
+#include <asm/processor.h>
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ *   must also be changed
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        unsigned long           flags;          /* low level flags */
+        unsigned long           tp_value;       /* thread pointer */
+        __u32                   cpu;            /* current CPU */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
+        mm_segment_t            addr_limit;     /*
+                                                 * thread address space limit:
+                                                 * 0x7fffffff for user-thead
+                                                 * 0xffffffff for kernel-thread
+                                                 */
+        struct pt_regs          *regs;
+        long                    syscall;        /* syscall number */
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .flags          = _TIF_FIXADE,          \
+        .cpu            = 0,                    \
+        .preempt_count  = INIT_PREEMPT_COUNT,   \
+        .addr_limit     = KERNEL_DS,            \
+}
+
+/*
+ * A pointer to the struct thread_info for the currently executing thread is
+ * held in register $28/$gp.
+ *
+ * We declare __current_thread_info as a global register variable rather than a
+ * local register variable within current_thread_info() because clang doesn't
+ * support explicit local register variables.
+ *
+ * When building the VDSO we take care not to declare the global register
+ * variable because this causes GCC to not preserve the value of $28/$gp in
+ * functions that change its value (which is common in the PIC VDSO when
+ * accessing the GOT). Since the VDSO shouldn't be accessing
+ * __current_thread_info anyway we declare it extern in order to cause a link
+ * failure if it's referenced.
+ */
+#ifdef __VDSO__
+extern struct thread_info *__current_thread_info;
+#else
+register struct thread_info *__current_thread_info __asm__("$28");
+#endif
+
+static inline struct thread_info *current_thread_info(void)
+{
+        return __current_thread_info;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+/* thread information allocation */
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
+#define THREAD_SIZE_ORDER (1)
+#endif
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
+#define THREAD_SIZE_ORDER (2)
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define THREAD_SIZE_ORDER (1)
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+
+#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_MASK (THREAD_SIZE - 1UL)
+
+#define STACK_WARN      (THREAD_SIZE / 8)
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to
+ *   access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SIGPENDING          1       /* signal pending */
+#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
+#define TIF_SYSCALL_AUDIT       3       /* syscall auditing active */
+#define TIF_SECCOMP             4       /* secure computing */
+#define TIF_NOTIFY_RESUME       5       /* callback before returning to user */
+#define TIF_UPROBE              6       /* breakpointed or singlestepping */
+#define TIF_NOTIFY_SIGNAL       7       /* signal notifications exist */
+#define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_MEMDIE              18      /* is terminating due to OOM killer */
+#define TIF_NOHZ                19      /* in adaptive nohz mode */
+#define TIF_FIXADE              20      /* Fix address errors in software */
+#define TIF_LOGADE              21      /* Log address errors to syslog */
+#define TIF_32BIT_REGS          22      /* 32-bit general purpose registers */
+#define TIF_32BIT_ADDR          23      /* 32-bit address space (o32/n32) */
+#define TIF_FPUBOUND            24      /* thread bound to FPU-full CPU set */
+#define TIF_LOAD_WATCH          25      /* If set, load watch registers */
+#define TIF_SYSCALL_TRACEPOINT  26      /* syscall tracepoint instrumentation */
+#define TIF_32BIT_FPREGS        27      /* 32-bit floating point registers */
+#define TIF_HYBRID_FPREGS       28      /* 64b FP registers, odd singles in bits 63:32 of even doubles */
+#define TIF_USEDMSA             29      /* MSA has been used this quantum */
+#define TIF_MSA_CTX_LIVE        30      /* MSA context must be preserved */
+#define TIF_SYSCALL_TRACE       31      /* syscall trace active */
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_UPROBE             (1<<TIF_UPROBE)
+#define _TIF_NOTIFY_SIGNAL      (1<<TIF_NOTIFY_SIGNAL)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_NOHZ               (1<<TIF_NOHZ)
+#define _TIF_FIXADE             (1<<TIF_FIXADE)
+#define _TIF_LOGADE             (1<<TIF_LOGADE)
+#define _TIF_32BIT_REGS         (1<<TIF_32BIT_REGS)
+#define _TIF_32BIT_ADDR         (1<<TIF_32BIT_ADDR)
+#define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
+#define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
+#define _TIF_32BIT_FPREGS       (1<<TIF_32BIT_FPREGS)
+#define _TIF_HYBRID_FPREGS      (1<<TIF_HYBRID_FPREGS)
+#define _TIF_USEDMSA            (1<<TIF_USEDMSA)
+#define _TIF_MSA_CTX_LIVE       (1<<TIF_MSA_CTX_LIVE)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
+
+#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
+                                 _TIF_SYSCALL_AUDIT | \
+                                 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP)
+
+/* work to do in syscall_trace_leave() */
+#define _TIF_WORK_SYSCALL_EXIT  (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
+                                 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
+
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          \
+        (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME |     \
+         _TIF_UPROBE | _TIF_NOTIFY_SIGNAL)
+/* work to do on any return to u-space */
+#define _TIF_ALLWORK_MASK       (_TIF_NOHZ | _TIF_WORK_MASK |           \
+                                 _TIF_WORK_SYSCALL_EXIT |               \
+                                 _TIF_SYSCALL_TRACEPOINT)
+
+/*
+ * We stash processor id into a COP0 register to retrieve it fast
+ * at kernel exception entry.
+ */
+#if   defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define SMP_CPUID_REG           20, 0   /* XCONTEXT */
+#define ASM_SMP_CPUID_REG       $20
+#define SMP_CPUID_PTRSHIFT      48
+#else
+#define SMP_CPUID_REG           4, 0    /* CONTEXT */
+#define ASM_SMP_CPUID_REG       $4
+#define SMP_CPUID_PTRSHIFT      23
+#endif
+
+#ifdef CONFIG_64BIT
+#define SMP_CPUID_REGSHIFT      (SMP_CPUID_PTRSHIFT + 3)
+#else
+#define SMP_CPUID_REGSHIFT      (SMP_CPUID_PTRSHIFT + 2)
+#endif
+
+#define ASM_CPUID_MFC0          MFC0
+#define UASM_i_CPUID_MFC0       UASM_i_MFC0
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
new file mode 100644
index 000000000..e855a3611
--- /dev/null
+++ b/arch/mips/include/asm/time.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2001, 2002, MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (c) 2003  Maciej W. Rozycki
+ *
+ * include/asm-mips/time.h
+ *     header file for the new style time.c file and time services.
+ */
+#ifndef _ASM_TIME_H
+#define _ASM_TIME_H
+
+#include <linux/rtc.h>
+#include <linux/spinlock.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+
+extern spinlock_t rtc_lock;
+
+/*
+ * board specific routines required by time_init().
+ */
+extern void plat_time_init(void);
+
+/*
+ * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
+ * counter as a timer interrupt source.
+ */
+extern unsigned int mips_hpt_frequency;
+
+/*
+ * The performance counter IRQ on MIPS is a close relative to the timer IRQ
+ * so it lives here.
+ */
+extern int (*perf_irq)(void);
+extern int __weak get_c0_perfcount_int(void);
+
+/*
+ * Initialize the calling CPU's compare interrupt as clockevent device
+ */
+extern unsigned int get_c0_compare_int(void);
+extern int r4k_clockevent_init(void);
+
+static inline int mips_clockevent_init(void)
+{
+#ifdef CONFIG_CEVT_R4K
+        return r4k_clockevent_init();
+#else
+        return -ENXIO;
+#endif
+}
+
+/*
+ * Initialize the count register as a clocksource
+ */
+extern int init_r4k_clocksource(void);
+
+static inline int init_mips_clocksource(void)
+{
+#ifdef CONFIG_CSRC_R4K
+        return init_r4k_clocksource();
+#else
+        return 0;
+#endif
+}
+
+static inline void clockevent_set_clock(struct clock_event_device *cd,
+                                        unsigned int clock)
+{
+        clockevents_calc_mult_shift(cd, clock, 4);
+}
+
+#endif /* _ASM_TIME_H */
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
new file mode 100644
index 000000000..2e107886f
--- /dev/null
+++ b/arch/mips/include/asm/timex.h
@@ -0,0 +1,102 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
+ * Copyright (C) 2014 by Maciej W. Rozycki
+ */
+#ifndef _ASM_TIMEX_H
+#define _ASM_TIMEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
+#include <asm/cpu-type.h>
+
+/*
+ * This is the clock rate of the i8253 PIT.  A MIPS system may not have
+ * a PIT by the symbol is used all over the kernel including some APIs.
+ * So keeping it defined to the number for the PIT is the only sane thing
+ * for now.
+ */
+#define CLOCK_TICK_RATE 1193182
+
+/*
+ * Standard way to access the cycle counter.
+ * Currently only used on SMP for scheduling.
+ *
+ * Only the low 32 bits are available as a continuously counting entity.
+ * But this only means we'll force a reschedule every 8 seconds or so,
+ * which isn't an evil thing.
+ *
+ * We know that all SMP capable CPUs have cycle counters.
+ */
+
+typedef unsigned int cycles_t;
+
+/*
+ * On R4000/R4400 an erratum exists such that if the cycle counter is
+ * read in the exact moment that it is matching the compare register,
+ * no interrupt will be generated.
+ *
+ * There is a suggested workaround and also the erratum can't strike if
+ * the compare interrupt isn't being used as the clock source device.
+ * However for now the implementaton of this function doesn't get these
+ * fine details right.
+ */
+static inline int can_use_mips_counter(unsigned int prid)
+{
+        int comp = (prid & PRID_COMP_MASK) != PRID_COMP_LEGACY;
+
+        if (__builtin_constant_p(cpu_has_counter) && !cpu_has_counter)
+                return 0;
+        else if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r)
+                return 1;
+        else if (likely(!__builtin_constant_p(cpu_has_mips_r) && comp))
+                return 1;
+        /* Make sure we don't peek at cpu_data[0].options in the fast path! */
+        if (!__builtin_constant_p(cpu_has_counter))
+                asm volatile("" : "=m" (cpu_data[0].options));
+        if (likely(cpu_has_counter &&
+                   prid > (PRID_IMP_R4000 | PRID_REV_ENCODE_44(15, 15))))
+                return 1;
+        else
+                return 0;
+}
+
+static inline cycles_t get_cycles(void)
+{
+        if (can_use_mips_counter(read_c0_prid()))
+                return read_c0_count();
+        else
+                return 0;       /* no usable counter */
+}
+#define get_cycles get_cycles
+
+/*
+ * Like get_cycles - but where c0_count is not available we desperately
+ * use c0_random in an attempt to get at least a little bit of entropy.
+ */
+static inline unsigned long random_get_entropy(void)
+{
+        unsigned int c0_random;
+
+        if (can_use_mips_counter(read_c0_prid()))
+                return read_c0_count();
+
+        if (cpu_has_3kex)
+                c0_random = (read_c0_random() >> 8) & 0x3f;
+        else
+                c0_random = read_c0_random() & 0x3f;
+        return (random_get_entropy_fallback() << 6) | (0x3f - c0_random);
+}
+#define random_get_entropy random_get_entropy
+
+#endif /* __KERNEL__ */
+
+#endif /*  _ASM_TIMEX_H */
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
new file mode 100644
index 000000000..90f3ad76d
--- /dev/null
+++ b/arch/mips/include/asm/tlb.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
+
+#define _UNIQUE_ENTRYHI(base, idx)                                      \
+                (((base) + ((idx) << (PAGE_SHIFT + 1))) |               \
+                 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
+#define UNIQUE_ENTRYHI(idx)             _UNIQUE_ENTRYHI(CKSEG0, idx)
+#define UNIQUE_GUEST_ENTRYHI(idx)       _UNIQUE_ENTRYHI(CKSEG1, idx)
+
+static inline unsigned int num_wired_entries(void)
+{
+        unsigned int wired = read_c0_wired();
+
+        if (cpu_has_mips_r6)
+                wired &= MIPSR6_WIRED_WIRED;
+
+        return wired;
+}
+
+#include <asm-generic/tlb.h>
+
+#endif /* __ASM_TLB_H */
diff --git a/arch/mips/include/asm/tlbdebug.h b/arch/mips/include/asm/tlbdebug.h
new file mode 100644
index 000000000..3a25a8780
--- /dev/null
+++ b/arch/mips/include/asm/tlbdebug.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 by Ralf Baechle
+ */
+#ifndef __ASM_TLBDEBUG_H
+#define __ASM_TLBDEBUG_H
+
+/*
+ * TLB debugging functions:
+ */
+extern void dump_tlb_regs(void);
+extern void dump_tlb_all(void);
+
+#endif /* __ASM_TLBDEBUG_H */
diff --git a/arch/mips/include/asm/tlbex.h b/arch/mips/include/asm/tlbex.h
new file mode 100644
index 000000000..6d97e23f3
--- /dev/null
+++ b/arch/mips/include/asm/tlbex.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_TLBEX_H
+#define __ASM_TLBEX_H
+
+#include <asm/uasm.h>
+
+/*
+ * Write random or indexed TLB entry, and care about the hazards from
+ * the preceding mtc0 and for the following eret.
+ */
+enum tlb_write_entry {
+        tlb_random,
+        tlb_indexed
+};
+
+extern int pgd_reg;
+
+void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
+                      unsigned int tmp, unsigned int ptr);
+void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr);
+void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr);
+void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep);
+void build_tlb_write_entry(u32 **p, struct uasm_label **l,
+                           struct uasm_reloc **r,
+                           enum tlb_write_entry wmode);
+
+extern void handle_tlbl(void);
+extern char handle_tlbl_end[];
+
+extern void handle_tlbs(void);
+extern char handle_tlbs_end[];
+
+extern void handle_tlbm(void);
+extern char handle_tlbm_end[];
+
+#endif /* __ASM_TLBEX_H */
diff --git a/arch/mips/include/asm/tlbflush.h b/arch/mips/include/asm/tlbflush.h
new file mode 100644
index 000000000..9789e7a32
--- /dev/null
+++ b/arch/mips/include/asm/tlbflush.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_TLBFLUSH_H
+#define __ASM_TLBFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void local_flush_tlb_kernel_range(unsigned long start,
+        unsigned long end);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+        unsigned long page);
+extern void local_flush_tlb_one(unsigned long vaddr);
+
+#include <asm/mmu_context.h>
+
+#ifdef CONFIG_SMP
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long,
+        unsigned long);
+extern void flush_tlb_kernel_range(unsigned long, unsigned long);
+extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void flush_tlb_one(unsigned long vaddr);
+
+#else /* CONFIG_SMP */
+
+#define flush_tlb_all()                 local_flush_tlb_all()
+#define flush_tlb_mm(mm)                drop_mmu_context(mm)
+#define flush_tlb_range(vma, vmaddr, end)       local_flush_tlb_range(vma, vmaddr, end)
+#define flush_tlb_kernel_range(vmaddr,end) \
+        local_flush_tlb_kernel_range(vmaddr, end)
+#define flush_tlb_page(vma, page)       local_flush_tlb_page(vma, page)
+#define flush_tlb_one(vaddr)            local_flush_tlb_one(vaddr)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_TLBFLUSH_H */
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
new file mode 100644
index 000000000..c1a540669
--- /dev/null
+++ b/arch/mips/include/asm/tlbmisc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_TLBMISC_H
+#define __ASM_TLBMISC_H
+
+/*
+ * - add_wired_entry() add a fixed TLB entry, and move wired register
+ */
+extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+        unsigned long entryhi, unsigned long pagemask);
+
+#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
new file mode 100644
index 000000000..0673d2d0f
--- /dev/null
+++ b/arch/mips/include/asm/topology.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_TOPOLOGY_H
+#define __ASM_TOPOLOGY_H
+
+#include <topology.h>
+#include <linux/smp.h>
+
+#ifdef CONFIG_SMP
+#define topology_physical_package_id(cpu)       (cpu_data[cpu].package)
+#define topology_core_id(cpu)                   (cpu_core(&cpu_data[cpu]))
+#define topology_core_cpumask(cpu)              (&cpu_core_map[cpu])
+#define topology_sibling_cpumask(cpu)           (&cpu_sibling_map[cpu])
+#endif
+
+#endif /* __ASM_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
new file mode 100644
index 000000000..6a0864bb6
--- /dev/null
+++ b/arch/mips/include/asm/traps.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *      Trap handling definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+#ifndef _ASM_TRAPS_H
+#define _ASM_TRAPS_H
+
+/*
+ * Possible status responses for a board_be_handler backend.
+ */
+#define MIPS_BE_DISCARD 0               /* return with no action */
+#define MIPS_BE_FIXUP   1               /* return to the fixup code */
+#define MIPS_BE_FATAL   2               /* treat as an unrecoverable error */
+
+extern void (*board_be_init)(void);
+extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+
+extern void (*board_nmi_handler_setup)(void);
+extern void (*board_ejtag_handler_setup)(void);
+extern void (*board_bind_eic_interrupt)(int irq, int regset);
+extern void (*board_ebase_setup)(void);
+extern void (*board_cache_error_setup)(void);
+
+extern int register_nmi_notifier(struct notifier_block *nb);
+
+#define nmi_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_nmi_notifier(&fn##_nb);                                \
+})
+
+#endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h
new file mode 100644
index 000000000..d45237bef
--- /dev/null
+++ b/arch/mips/include/asm/txx9/boards.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifdef CONFIG_TOSHIBA_JMR3927
+BOARD_VEC(jmr3927_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4927
+BOARD_VEC(rbtx4927_vec)
+BOARD_VEC(rbtx4937_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4938
+BOARD_VEC(rbtx4938_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4939
+BOARD_VEC(rbtx4939_vec)
+#endif
diff --git a/arch/mips/include/asm/txx9/dmac.h b/arch/mips/include/asm/txx9/dmac.h
new file mode 100644
index 000000000..b47ef5fe7
--- /dev/null
+++ b/arch/mips/include/asm/txx9/dmac.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * TXx9 SoC DMA Controller
+ */
+
+#ifndef __ASM_TXX9_DMAC_H
+#define __ASM_TXX9_DMAC_H
+
+#include <linux/dmaengine.h>
+
+#define TXX9_DMA_MAX_NR_CHANNELS        4
+
+/**
+ * struct txx9dmac_platform_data - Controller configuration parameters
+ * @memcpy_chan: Channel used for DMA_MEMCPY
+ * @have_64bit_regs: DMAC have 64 bit registers
+ */
+struct txx9dmac_platform_data {
+        int     memcpy_chan;
+        bool    have_64bit_regs;
+};
+
+/**
+ * struct txx9dmac_chan_platform_data - Channel configuration parameters
+ * @dmac_dev: A platform device for DMAC
+ */
+struct txx9dmac_chan_platform_data {
+        struct platform_device *dmac_dev;
+};
+
+/**
+ * struct txx9dmac_slave - Controller-specific information about a slave
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
+ */
+struct txx9dmac_slave {
+        u64             tx_reg;
+        u64             rx_reg;
+        unsigned int    reg_width;
+};
+
+void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
+                    const struct txx9dmac_platform_data *pdata);
+
+#endif /* __ASM_TXX9_DMAC_H */
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
new file mode 100644
index 000000000..9a2c47bf3
--- /dev/null
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -0,0 +1,98 @@
+/*
+ * linux/include/asm-mips/txx9/generic.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_GENERIC_H
+#define __ASM_TXX9_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/ioport.h>       /* for struct resource */
+
+extern struct resource txx9_ce_res[];
+#define TXX9_CE(n)      (unsigned long)(txx9_ce_res[(n)].start)
+extern unsigned int txx9_pcode;
+extern char txx9_pcode_str[8];
+void txx9_reg_res_init(unsigned int pcode, unsigned long base,
+                       unsigned long size);
+
+extern unsigned int txx9_master_clock;
+extern unsigned int txx9_cpu_clock;
+extern unsigned int txx9_gbus_clock;
+#define TXX9_IMCLK      (txx9_gbus_clock / 2)
+
+extern int txx9_ccfg_toeon;
+struct uart_port;
+int early_serial_txx9_setup(struct uart_port *port);
+
+struct pci_dev;
+struct txx9_board_vec {
+        const char *system;
+        void (*prom_init)(void);
+        void (*mem_setup)(void);
+        void (*irq_setup)(void);
+        void (*time_init)(void);
+        void (*arch_init)(void);
+        void (*device_init)(void);
+#ifdef CONFIG_PCI
+        int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+#endif
+};
+extern struct txx9_board_vec *txx9_board_vec;
+extern int (*txx9_irq_dispatch)(int pending);
+const char *prom_getenv(const char *name);
+void txx9_wdt_init(unsigned long base);
+void txx9_wdt_now(unsigned long base);
+void txx9_spi_init(int busid, unsigned long base, int irq);
+void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
+void txx9_sio_init(unsigned long baseaddr, int irq,
+                   unsigned int line, unsigned int sclk, int nocts);
+#ifdef CONFIG_EARLY_PRINTK
+extern void (*txx9_prom_putchar)(char c);
+void txx9_sio_putchar_init(unsigned long baseaddr);
+#else
+static inline void txx9_sio_putchar_init(unsigned long baseaddr)
+{
+}
+#endif
+
+struct physmap_flash_data;
+void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size,
+                             const struct physmap_flash_data *pdata);
+
+/* 8 bit version of __fls(): find first bit set (returns 0..7) */
+static inline unsigned int __fls8(unsigned char x)
+{
+        int r = 7;
+
+        if (!(x & 0xf0)) {
+                r -= 4;
+                x <<= 4;
+        }
+        if (!(x & 0xc0)) {
+                r -= 2;
+                x <<= 2;
+        }
+        if (!(x & 0x80))
+                r -= 1;
+        return r;
+}
+
+void txx9_iocled_init(unsigned long baseaddr,
+                      int basenum, unsigned int num, int lowactive,
+                      const char *color, char **deftriggers);
+
+/* 7SEG LED */
+void txx9_7segled_init(unsigned int num,
+                       void (*putc)(unsigned int pos, unsigned char val));
+int txx9_7segled_putc(unsigned int pos, char c);
+
+void __init txx9_aclc_init(unsigned long baseaddr, int irq,
+                           unsigned int dmac_id,
+                           unsigned int dma_chan_out,
+                           unsigned int dma_chan_in);
+void __init txx9_sramc_init(struct resource *r);
+
+#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
new file mode 100644
index 000000000..aab959dc3
--- /dev/null
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -0,0 +1,179 @@
+/*
+ * Defines for the TJSYS JMR-TX3927
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ */
+#ifndef __ASM_TXX9_JMR3927_H
+#define __ASM_TXX9_JMR3927_H
+
+#include <asm/txx9/tx3927.h>
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+
+/* CS */
+#define JMR3927_ROMCE0  0x1fc00000      /* 4M */
+#define JMR3927_ROMCE1  0x1e000000      /* 4M */
+#define JMR3927_ROMCE2  0x14000000      /* 16M */
+#define JMR3927_ROMCE3  0x10000000      /* 64M */
+#define JMR3927_ROMCE5  0x1d000000      /* 4M */
+#define JMR3927_SDCS0   0x00000000      /* 32M */
+#define JMR3927_SDCS1   0x02000000      /* 32M */
+/* PCI Direct Mappings */
+
+#define JMR3927_PCIMEM  0x08000000
+#define JMR3927_PCIMEM_SIZE     0x08000000      /* 128M */
+#define JMR3927_PCIIO   0x15000000
+#define JMR3927_PCIIO_SIZE      0x01000000      /* 16M */
+
+#define JMR3927_SDRAM_SIZE      0x02000000      /* 32M */
+#define JMR3927_PORT_BASE       KSEG1
+
+/* Address map (virtual address) */
+#define JMR3927_ROM0_BASE       (KSEG1 + JMR3927_ROMCE0)
+#define JMR3927_ROM1_BASE       (KSEG1 + JMR3927_ROMCE1)
+#define JMR3927_IOC_BASE        (KSEG1 + JMR3927_ROMCE2)
+#define JMR3927_PCIMEM_BASE     (KSEG1 + JMR3927_PCIMEM)
+#define JMR3927_PCIIO_BASE      (KSEG1 + JMR3927_PCIIO)
+
+#define JMR3927_IOC_REV_ADDR    (JMR3927_IOC_BASE + 0x00000000)
+#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
+#define JMR3927_IOC_LED_ADDR    (JMR3927_IOC_BASE + 0x00020000)
+#define JMR3927_IOC_DIPSW_ADDR  (JMR3927_IOC_BASE + 0x00030000)
+#define JMR3927_IOC_BREV_ADDR   (JMR3927_IOC_BASE + 0x00040000)
+#define JMR3927_IOC_DTR_ADDR    (JMR3927_IOC_BASE + 0x00050000)
+#define JMR3927_IOC_INTS1_ADDR  (JMR3927_IOC_BASE + 0x00080000)
+#define JMR3927_IOC_INTS2_ADDR  (JMR3927_IOC_BASE + 0x00090000)
+#define JMR3927_IOC_INTM_ADDR   (JMR3927_IOC_BASE + 0x000a0000)
+#define JMR3927_IOC_INTP_ADDR   (JMR3927_IOC_BASE + 0x000b0000)
+#define JMR3927_IOC_RESET_ADDR  (JMR3927_IOC_BASE + 0x000f0000)
+
+/* Flash ROM */
+#define JMR3927_FLASH_BASE      (JMR3927_ROM0_BASE)
+#define JMR3927_FLASH_SIZE      0x00400000
+
+/* bits for IOC_REV/IOC_BREV (high byte) */
+#define JMR3927_IDT_MASK        0xfc
+#define JMR3927_REV_MASK        0x03
+#define JMR3927_IOC_IDT         0xe0
+
+/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
+#define JMR3927_IOC_INTB_PCIA   0
+#define JMR3927_IOC_INTB_PCIB   1
+#define JMR3927_IOC_INTB_PCIC   2
+#define JMR3927_IOC_INTB_PCID   3
+#define JMR3927_IOC_INTB_MODEM  4
+#define JMR3927_IOC_INTB_INT6   5
+#define JMR3927_IOC_INTB_INT7   6
+#define JMR3927_IOC_INTB_SOFT   7
+#define JMR3927_IOC_INTF_PCIA   (1 << JMR3927_IOC_INTF_PCIA)
+#define JMR3927_IOC_INTF_PCIB   (1 << JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IOC_INTF_PCIC   (1 << JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IOC_INTF_PCID   (1 << JMR3927_IOC_INTB_PCID)
+#define JMR3927_IOC_INTF_MODEM  (1 << JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IOC_INTF_INT6   (1 << JMR3927_IOC_INTB_INT6)
+#define JMR3927_IOC_INTF_INT7   (1 << JMR3927_IOC_INTB_INT7)
+#define JMR3927_IOC_INTF_SOFT   (1 << JMR3927_IOC_INTB_SOFT)
+
+/* bits for IOC_RESET (high byte) */
+#define JMR3927_IOC_RESET_CPU   1
+#define JMR3927_IOC_RESET_PCI   2
+
+#if defined(__BIG_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)(a)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)(a))
+#elif defined(__LITTLE_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)((a)^1)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)((a)^1))
+#else
+#error "No Endian"
+#endif
+
+/* LED macro */
+#define jmr3927_led_set(n/*0-16*/)      jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
+
+#define jmr3927_led_and_set(n/*0-16*/)  jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
+
+/* DIPSW4 macro */
+#define jmr3927_dipsw1()        (gpio_get_value(11) == 0)
+#define jmr3927_dipsw2()        (gpio_get_value(10) == 0)
+#define jmr3927_dipsw3()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
+#define jmr3927_dipsw4()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
+
+/*
+ * IRQ mappings
+ */
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an JMR machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
+#define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
+
+#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
+#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
+#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
+
+#define JMR3927_IRQ_IRC_INT0    (JMR3927_IRQ_IRC + TX3927_IR_INT0)
+#define JMR3927_IRQ_IRC_INT1    (JMR3927_IRQ_IRC + TX3927_IR_INT1)
+#define JMR3927_IRQ_IRC_INT2    (JMR3927_IRQ_IRC + TX3927_IR_INT2)
+#define JMR3927_IRQ_IRC_INT3    (JMR3927_IRQ_IRC + TX3927_IR_INT3)
+#define JMR3927_IRQ_IRC_INT4    (JMR3927_IRQ_IRC + TX3927_IR_INT4)
+#define JMR3927_IRQ_IRC_INT5    (JMR3927_IRQ_IRC + TX3927_IR_INT5)
+#define JMR3927_IRQ_IRC_SIO0    (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
+#define JMR3927_IRQ_IRC_SIO1    (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
+#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
+#define JMR3927_IRQ_IRC_DMA     (JMR3927_IRQ_IRC + TX3927_IR_DMA)
+#define JMR3927_IRQ_IRC_PIO     (JMR3927_IRQ_IRC + TX3927_IR_PIO)
+#define JMR3927_IRQ_IRC_PCI     (JMR3927_IRQ_IRC + TX3927_IR_PCI)
+#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
+#define JMR3927_IRQ_IOC_PCIA    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
+#define JMR3927_IRQ_IOC_PCIB    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IRQ_IOC_PCIC    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IRQ_IOC_PCID    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
+#define JMR3927_IRQ_IOC_MODEM   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IRQ_IOC_INT6    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
+#define JMR3927_IRQ_IOC_INT7    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
+#define JMR3927_IRQ_IOC_SOFT    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
+
+/* IOC (PCI, MODEM) */
+#define JMR3927_IRQ_IOCINT      JMR3927_IRQ_IRC_INT1
+/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
+#define JMR3927_IRQ_ETHER0      JMR3927_IRQ_IRC_INT3
+
+/* Clocks */
+#define JMR3927_CORECLK 132710400       /* 132.7MHz */
+
+/*
+ * TX3927 Pin Configuration:
+ *
+ *      PCFG bits               Avail                   Dead
+ *      SELSIO[1:0]:11          RXD[1:0], TXD[1:0]      PIO[6:3]
+ *      SELSIOC[0]:1            CTS[0], RTS[0]          INT[5:4]
+ *      SELSIOC[1]:0,SELDSF:0,  GSDAO[0],GPCST[3]       CTS[1], RTS[1],DSF,
+ *        GDBGE*                                          PIO[2:1]
+ *      SELDMA[2]:1             DMAREQ[2],DMAACK[2]     PIO[13:12]
+ *      SELTMR[2:0]:000                                 TIMER[1:0]
+ *      SELCS:0,SELDMA[1]:0     PIO[11;10]              SDCS_CE[7:6],
+ *                                                        DMAREQ[1],DMAACK[1]
+ *      SELDMA[0]:1             DMAREQ[0],DMAACK[0]     PIO[9:8]
+ *      SELDMA[3]:1             DMAREQ[3],DMAACK[3]     PIO[15:14]
+ *      SELDONE:1               DMADONE                 PIO[7]
+ *
+ * Usable pins are:
+ *      RXD[1;0],TXD[1:0],CTS[0],RTS[0],
+ *      DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
+ *      INT[3:0]
+ */
+
+void jmr3927_prom_init(void);
+void jmr3927_irq_setup(void);
+struct pci_dev;
+int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/arch/mips/include/asm/txx9/pci.h b/arch/mips/include/asm/txx9/pci.h
new file mode 100644
index 000000000..3d3252906
--- /dev/null
+++ b/arch/mips/include/asm/txx9/pci.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_PCI_H
+#define __ASM_TXX9_PCI_H
+
+#include <linux/pci.h>
+
+extern struct pci_controller txx9_primary_pcic;
+struct pci_controller *
+txx9_alloc_pci_controller(struct pci_controller *pcic,
+                          unsigned long mem_base, unsigned long mem_size,
+                          unsigned long io_base, unsigned long io_size);
+
+int txx9_pci66_check(struct pci_controller *hose, int top_bus,
+                        int current_bus);
+extern int txx9_pci_mem_high __initdata;
+
+extern int txx9_pci_option;
+#define TXX9_PCI_OPT_PICMG      0x0002
+#define TXX9_PCI_OPT_CLK_33     0x0008
+#define TXX9_PCI_OPT_CLK_66     0x0010
+#define TXX9_PCI_OPT_CLK_MASK   \
+        (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
+#define TXX9_PCI_OPT_CLK_AUTO   TXX9_PCI_OPT_CLK_MASK
+
+enum txx9_pci_err_action {
+        TXX9_PCI_ERR_REPORT,
+        TXX9_PCI_ERR_IGNORE,
+        TXX9_PCI_ERR_PANIC,
+};
+extern enum txx9_pci_err_action txx9_pci_err_action;
+
+extern char * (*txx9_board_pcibios_setup)(char *str);
+char *txx9_pcibios_setup(char *str);
+
+#endif /* __ASM_TXX9_PCI_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
new file mode 100644
index 000000000..4060ad26c
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -0,0 +1,92 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_RBTX4927_H
+#define __ASM_TXX9_RBTX4927_H
+
+#include <asm/txx9/tx4927.h>
+
+#define RBTX4927_PCIMEM         0x08000000
+#define RBTX4927_PCIMEM_SIZE    0x08000000
+#define RBTX4927_PCIIO          0x16000000
+#define RBTX4927_PCIIO_SIZE     0x01000000
+
+#define RBTX4927_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
+#define RBTX4927_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4927_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4927_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
+#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
+#define RBTX4927_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000f002)
+#define RBTX4927_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x0000f006)
+#define RBTX4927_BRAMRTC_BASE   (IO_BASE + TXX9_CE(2) + 0x00010000)
+#define RBTX4927_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4927_ETHER_ADDR     (RBTX4927_ETHER_BASE + 0x280)
+
+#define rbtx4927_imask_addr     ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
+#define rbtx4927_imstat_addr    ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
+#define rbtx4927_softint_addr   ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
+#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
+#define rbtx4927_softresetlock_addr     \
+                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
+#define rbtx4927_pcireset_addr  ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4927_INTB_PCID      0
+#define RBTX4927_INTB_PCIC      1
+#define RBTX4927_INTB_PCIB      2
+#define RBTX4927_INTB_PCIA      3
+#define RBTX4927_INTF_PCID      (1 << RBTX4927_INTB_PCID)
+#define RBTX4927_INTF_PCIC      (1 << RBTX4927_INTB_PCIC)
+#define RBTX4927_INTF_PCIB      (1 << RBTX4927_INTB_PCIB)
+#define RBTX4927_INTF_PCIA      (1 << RBTX4927_INTB_PCIA)
+
+#define RBTX4927_NR_IRQ_IOC     8       /* IOC */
+
+#define RBTX4927_IRQ_IOC        (TXX9_IRQ_BASE + TX4927_NUM_IR)
+#define RBTX4927_IRQ_IOC_PCID   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
+#define RBTX4927_IRQ_IOC_PCIC   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
+#define RBTX4927_IRQ_IOC_PCIB   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
+#define RBTX4927_IRQ_IOC_PCIA   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
+
+#define RBTX4927_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4927_IR_INT(1))
+
+#ifdef CONFIG_PCI
+#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
+#else
+#define RBTX4927_ISA_IO_OFFSET 0
+#endif
+
+#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
+#define RBTX4927_RTL_8019_IRQ  (TXX9_IRQ_BASE + TX4927_IR_INT(3))
+
+void rbtx4927_prom_init(void);
+void rbtx4927_irq_setup(void);
+struct pci_dev;
+int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
new file mode 100644
index 000000000..9c969dd3c
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
@@ -0,0 +1,145 @@
+/*
+ * Definitions for TX4937/TX4938
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_RBTX4938_H
+#define __ASM_TXX9_RBTX4938_H
+
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4938.h>
+
+/* Address map */
+#define RBTX4938_FPGA_REG_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000000)
+#define RBTX4938_FPGA_REV_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000002)
+#define RBTX4938_CONFIG1_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000004)
+#define RBTX4938_CONFIG2_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000006)
+#define RBTX4938_CONFIG3_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000008)
+#define RBTX4938_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
+#define RBTX4938_DIPSW_ADDR     (IO_BASE + TXX9_CE(2) + 0x00001002)
+#define RBTX4938_BDIPSW_ADDR    (IO_BASE + TXX9_CE(2) + 0x00001004)
+#define RBTX4938_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4938_IMASK2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002002)
+#define RBTX4938_INTPOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002004)
+#define RBTX4938_ISTAT_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4938_ISTAT2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002008)
+#define RBTX4938_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000200a)
+#define RBTX4938_IMSTAT2_ADDR   (IO_BASE + TXX9_CE(2) + 0x0000200c)
+#define RBTX4938_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
+#define RBTX4938_PIOSEL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005000)
+#define RBTX4938_SPICS_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005002)
+#define RBTX4938_SFPWR_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005008)
+#define RBTX4938_SFVOL_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000500a)
+#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
+#define RBTX4938_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00007002)
+#define RBTX4938_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x00007004)
+#define RBTX4938_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
+
+/* Ethernet port address (Jumperless Mode (W12:Open)) */
+#define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4938_INTB_PCID      0
+#define RBTX4938_INTB_PCIC      1
+#define RBTX4938_INTB_PCIB      2
+#define RBTX4938_INTB_PCIA      3
+#define RBTX4938_INTB_RTC       4
+#define RBTX4938_INTB_ATA       5
+#define RBTX4938_INTB_MODEM     6
+#define RBTX4938_INTB_SWINT     7
+#define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
+#define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
+#define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
+#define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
+#define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
+#define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
+#define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
+#define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
+
+#define rbtx4938_fpga_rev_addr  ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
+#define rbtx4938_led_addr       ((__u8 __iomem *)RBTX4938_LED_ADDR)
+#define rbtx4938_dipsw_addr     ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
+#define rbtx4938_bdipsw_addr    ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
+#define rbtx4938_imask_addr     ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
+#define rbtx4938_imask2_addr    ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
+#define rbtx4938_intpol_addr    ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
+#define rbtx4938_istat_addr     ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
+#define rbtx4938_istat2_addr    ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
+#define rbtx4938_imstat_addr    ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
+#define rbtx4938_imstat2_addr   ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
+#define rbtx4938_softint_addr   ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
+#define rbtx4938_piosel_addr    ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
+#define rbtx4938_spics_addr     ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
+#define rbtx4938_sfpwr_addr     ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
+#define rbtx4938_sfvol_addr     ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
+#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softresetlock_addr     \
+                                ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
+#define rbtx4938_pcireset_addr  ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
+
+/*
+ * IRQ mappings
+ */
+
+#define RBTX4938_SOFT_INT0      0       /* not used */
+#define RBTX4938_SOFT_INT1      1       /* not used */
+#define RBTX4938_IRC_INT        2
+#define RBTX4938_TIMER_INT      7
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define RBTX4938_NR_IRQ_IOC     8
+
+#define RBTX4938_IRQ_IRC        TXX9_IRQ_BASE
+#define RBTX4938_IRQ_IOC        (TXX9_IRQ_BASE + TX4938_NUM_IR)
+#define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
+
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_DMA(ch, n)     (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
+#define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
+#define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
+#define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
+#define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
+#define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
+#define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
+#define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
+#define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
+#define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
+#define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
+#define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
+#define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
+#define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
+#define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
+
+
+/* IOC (PCI, etc) */
+#define RBTX4938_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4938_IR_INT(0))
+/* Onboard 10M Ether */
+#define RBTX4938_IRQ_ETHER      (TXX9_IRQ_BASE + TX4938_IR_INT(1))
+
+#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
+#define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
+
+void rbtx4938_prom_init(void);
+void rbtx4938_irq_setup(void);
+struct pci_dev;
+int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
new file mode 100644
index 000000000..6157bfd90
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -0,0 +1,142 @@
+/*
+ * Definitions for RBTX4939
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2006
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_RBTX4939_H
+#define __ASM_TXX9_RBTX4939_H
+
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+/* Address map */
+#define RBTX4939_IOC_REG_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_IOC_REV_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000002)
+#define RBTX4939_CONFIG1_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000004)
+#define RBTX4939_CONFIG2_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000006)
+#define RBTX4939_CONFIG3_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000008)
+#define RBTX4939_CONFIG4_ADDR   (IO_BASE + TXX9_CE(1) + 0x0000000a)
+#define RBTX4939_USTAT_ADDR     (IO_BASE + TXX9_CE(1) + 0x00001000)
+#define RBTX4939_UDIPSW_ADDR    (IO_BASE + TXX9_CE(1) + 0x00001002)
+#define RBTX4939_BDIPSW_ADDR    (IO_BASE + TXX9_CE(1) + 0x00001004)
+#define RBTX4939_IEN_ADDR       (IO_BASE + TXX9_CE(1) + 0x00002000)
+#define RBTX4939_IPOL_ADDR      (IO_BASE + TXX9_CE(1) + 0x00002002)
+#define RBTX4939_IFAC1_ADDR     (IO_BASE + TXX9_CE(1) + 0x00002004)
+#define RBTX4939_IFAC2_ADDR     (IO_BASE + TXX9_CE(1) + 0x00002006)
+#define RBTX4939_SOFTINT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00003000)
+#define RBTX4939_ISASTAT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00004000)
+#define RBTX4939_PCISTAT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00004002)
+#define RBTX4939_ROME_ADDR      (IO_BASE + TXX9_CE(1) + 0x00004004)
+#define RBTX4939_SPICS_ADDR     (IO_BASE + TXX9_CE(1) + 0x00004006)
+#define RBTX4939_AUDI_ADDR      (IO_BASE + TXX9_CE(1) + 0x00004008)
+#define RBTX4939_ISAGPIO_ADDR   (IO_BASE + TXX9_CE(1) + 0x0000400a)
+#define RBTX4939_PE1_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005000)
+#define RBTX4939_PE2_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005002)
+#define RBTX4939_PE3_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005004)
+#define RBTX4939_VP_ADDR        (IO_BASE + TXX9_CE(1) + 0x00005006)
+#define RBTX4939_VPRESET_ADDR   (IO_BASE + TXX9_CE(1) + 0x00005008)
+#define RBTX4939_VPSOUT_ADDR    (IO_BASE + TXX9_CE(1) + 0x0000500a)
+#define RBTX4939_VPSIN_ADDR     (IO_BASE + TXX9_CE(1) + 0x0000500c)
+#define RBTX4939_7SEG_ADDR(s, ch)       \
+        (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
+#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
+#define RBTX4939_RESETEN_ADDR   (IO_BASE + TXX9_CE(1) + 0x00007002)
+#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
+#define RBTX4939_ETHER_BASE     (IO_BASE + TXX9_CE(1) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4939_ETHER_ADDR     (RBTX4939_ETHER_BASE + 0x300)
+
+/* bits for IEN/IPOL/IFAC */
+#define RBTX4938_INTB_ISA0      0
+#define RBTX4938_INTB_ISA11     1
+#define RBTX4938_INTB_ISA12     2
+#define RBTX4938_INTB_ISA15     3
+#define RBTX4938_INTB_I2S       4
+#define RBTX4938_INTB_SW        5
+#define RBTX4938_INTF_ISA0      (1 << RBTX4938_INTB_ISA0)
+#define RBTX4938_INTF_ISA11     (1 << RBTX4938_INTB_ISA11)
+#define RBTX4938_INTF_ISA12     (1 << RBTX4938_INTB_ISA12)
+#define RBTX4938_INTF_ISA15     (1 << RBTX4938_INTB_ISA15)
+#define RBTX4938_INTF_I2S       (1 << RBTX4938_INTB_I2S)
+#define RBTX4938_INTF_SW        (1 << RBTX4938_INTB_SW)
+
+/* bits for PE1,PE2,PE3 */
+#define RBTX4939_PE1_ATA(ch)    (0x01 << (ch))
+#define RBTX4939_PE1_RMII(ch)   (0x04 << (ch))
+#define RBTX4939_PE2_SIO0       0x01
+#define RBTX4939_PE2_SIO2       0x02
+#define RBTX4939_PE2_SIO3       0x04
+#define RBTX4939_PE2_CIR        0x08
+#define RBTX4939_PE2_SPI        0x10
+#define RBTX4939_PE2_GPIO       0x20
+#define RBTX4939_PE3_VP 0x01
+#define RBTX4939_PE3_VP_P       0x02
+#define RBTX4939_PE3_VP_S       0x04
+
+#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
+#define rbtx4939_ioc_rev_addr   ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
+#define rbtx4939_config1_addr   ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
+#define rbtx4939_config2_addr   ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
+#define rbtx4939_config3_addr   ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
+#define rbtx4939_config4_addr   ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
+#define rbtx4939_ustat_addr     ((u8 __iomem *)RBTX4939_USTAT_ADDR)
+#define rbtx4939_udipsw_addr    ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
+#define rbtx4939_bdipsw_addr    ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
+#define rbtx4939_ien_addr       ((u8 __iomem *)RBTX4939_IEN_ADDR)
+#define rbtx4939_ipol_addr      ((u8 __iomem *)RBTX4939_IPOL_ADDR)
+#define rbtx4939_ifac1_addr     ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
+#define rbtx4939_ifac2_addr     ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
+#define rbtx4939_softint_addr   ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
+#define rbtx4939_isastat_addr   ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
+#define rbtx4939_pcistat_addr   ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
+#define rbtx4939_rome_addr      ((u8 __iomem *)RBTX4939_ROME_ADDR)
+#define rbtx4939_spics_addr     ((u8 __iomem *)RBTX4939_SPICS_ADDR)
+#define rbtx4939_audi_addr      ((u8 __iomem *)RBTX4939_AUDI_ADDR)
+#define rbtx4939_isagpio_addr   ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
+#define rbtx4939_pe1_addr       ((u8 __iomem *)RBTX4939_PE1_ADDR)
+#define rbtx4939_pe2_addr       ((u8 __iomem *)RBTX4939_PE2_ADDR)
+#define rbtx4939_pe3_addr       ((u8 __iomem *)RBTX4939_PE3_ADDR)
+#define rbtx4939_vp_addr        ((u8 __iomem *)RBTX4939_VP_ADDR)
+#define rbtx4939_vpreset_addr   ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
+#define rbtx4939_vpsout_addr    ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
+#define rbtx4939_vpsin_addr     ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
+#define rbtx4939_7seg_addr(s, ch) \
+                                ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
+#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
+#define rbtx4939_reseten_addr   ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
+#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
+
+/*
+ * IRQ mappings
+ */
+#define RBTX4939_NR_IRQ_IOC     8
+
+#define RBTX4939_IRQ_IOC        (TXX9_IRQ_BASE + TX4939_NUM_IR)
+#define RBTX4939_IRQ_END        (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
+
+/* IOC (ISA, etc) */
+#define RBTX4939_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4939_IR_INT(0))
+/* Onboard 10M Ether */
+#define RBTX4939_IRQ_ETHER      (TXX9_IRQ_BASE + TX4939_IR_INT(1))
+
+void rbtx4939_prom_init(void);
+void rbtx4939_irq_setup(void);
+
+struct mtd_partition;
+struct map_info;
+struct rbtx4939_flash_data {
+        unsigned int width;
+        unsigned int nr_parts;
+        struct mtd_partition *parts;
+        void (*map_init)(struct map_info *map);
+};
+
+#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
new file mode 100644
index 000000000..926d08f18
--- /dev/null
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -0,0 +1,68 @@
+/*
+ * Interface for smsc fdc48m81x Super IO chip
+ *
+ * Author: MontaVista Software, Inc. source@mvista.com
+ *
+ * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Manish Lachwani, mlachwani@mvista.com
+ */
+
+#ifndef _SMSC_FDC37M81X_H_
+#define _SMSC_FDC37M81X_H_
+
+/* Common Registers */
+#define SMSC_FDC37M81X_CONFIG_INDEX  0x00
+#define SMSC_FDC37M81X_CONFIG_DATA   0x01
+#define SMSC_FDC37M81X_CONF          0x02
+#define SMSC_FDC37M81X_INDEX         0x03
+#define SMSC_FDC37M81X_DNUM          0x07
+#define SMSC_FDC37M81X_DID           0x20
+#define SMSC_FDC37M81X_DREV          0x21
+#define SMSC_FDC37M81X_PCNT          0x22
+#define SMSC_FDC37M81X_PMGT          0x23
+#define SMSC_FDC37M81X_OSC           0x24
+#define SMSC_FDC37M81X_CONFPA0       0x26
+#define SMSC_FDC37M81X_CONFPA1       0x27
+#define SMSC_FDC37M81X_TEST4         0x2B
+#define SMSC_FDC37M81X_TEST5         0x2C
+#define SMSC_FDC37M81X_TEST1         0x2D
+#define SMSC_FDC37M81X_TEST2         0x2E
+#define SMSC_FDC37M81X_TEST3         0x2F
+
+/* Logical device numbers */
+#define SMSC_FDC37M81X_FDD           0x00
+#define SMSC_FDC37M81X_PARALLEL      0x03
+#define SMSC_FDC37M81X_SERIAL1       0x04
+#define SMSC_FDC37M81X_SERIAL2       0x05
+#define SMSC_FDC37M81X_KBD           0x07
+#define SMSC_FDC37M81X_AUXIO         0x08
+#define SMSC_FDC37M81X_NONE          0xff
+
+/* Logical device Config Registers */
+#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_BASEADDR0     0x60
+#define SMSC_FDC37M81X_BASEADDR1     0x61
+#define SMSC_FDC37M81X_INT           0x70
+#define SMSC_FDC37M81X_INT2          0x72
+#define SMSC_FDC37M81X_LDCR_F0       0xF0
+
+/* Chip Config Values */
+#define SMSC_FDC37M81X_CONFIG_ENTER  0x55
+#define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
+#define SMSC_FDC37M81X_CHIP_ID       0x4d
+
+unsigned long smsc_fdc37m81x_init(unsigned long port);
+
+void smsc_fdc37m81x_config_beg(void);
+
+void smsc_fdc37m81x_config_end(void);
+
+u8 smsc_fdc37m81x_config_get(u8 reg);
+void smsc_fdc37m81x_config_set(u8 reg, u8 val);
+
+#endif
diff --git a/arch/mips/include/asm/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h
new file mode 100644
index 000000000..0d727f354
--- /dev/null
+++ b/arch/mips/include/asm/txx9/spi.h
@@ -0,0 +1,34 @@
+/*
+ * Definitions for TX4937/TX4938 SPI
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_SPI_H
+#define __ASM_TXX9_SPI_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_SPI
+int spi_eeprom_register(int busid, int chipid, int size);
+int spi_eeprom_read(int busid, int chipid,
+                    int address, unsigned char *buf, int len);
+#else
+static inline int spi_eeprom_register(int busid, int chipid, int size)
+{
+        return -ENODEV;
+}
+static inline int spi_eeprom_read(int busid, int chipid,
+                                  int address, unsigned char *buf, int len)
+{
+        return -ENODEV;
+}
+#endif
+
+#endif /* __ASM_TXX9_SPI_H */
diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
new file mode 100644
index 000000000..149fab4f8
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -0,0 +1,341 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Toshiba Corporation
+ */
+#ifndef __ASM_TXX9_TX3927_H
+#define __ASM_TXX9_TX3927_H
+
+#define TX3927_REG_BASE 0xfffe0000UL
+#define TX3927_REG_SIZE 0x00010000
+#define TX3927_SDRAMC_REG       (TX3927_REG_BASE + 0x8000)
+#define TX3927_ROMC_REG         (TX3927_REG_BASE + 0x9000)
+#define TX3927_DMA_REG          (TX3927_REG_BASE + 0xb000)
+#define TX3927_IRC_REG          (TX3927_REG_BASE + 0xc000)
+#define TX3927_PCIC_REG         (TX3927_REG_BASE + 0xd000)
+#define TX3927_CCFG_REG         (TX3927_REG_BASE + 0xe000)
+#define TX3927_NR_TMR   3
+#define TX3927_TMR_REG(ch)      (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
+#define TX3927_NR_SIO   2
+#define TX3927_SIO_REG(ch)      (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX3927_PIO_REG          (TX3927_REG_BASE + 0xf500)
+
+struct tx3927_sdramc_reg {
+        volatile unsigned long cr[8];
+        volatile unsigned long tr[3];
+        volatile unsigned long cmd;
+        volatile unsigned long smrs[2];
+};
+
+struct tx3927_romc_reg {
+        volatile unsigned long cr[8];
+};
+
+struct tx3927_dma_reg {
+        struct tx3927_dma_ch_reg {
+                volatile unsigned long cha;
+                volatile unsigned long sar;
+                volatile unsigned long dar;
+                volatile unsigned long cntr;
+                volatile unsigned long sair;
+                volatile unsigned long dair;
+                volatile unsigned long ccr;
+                volatile unsigned long csr;
+        } ch[4];
+        volatile unsigned long dbr[8];
+        volatile unsigned long tdhr;
+        volatile unsigned long mcr;
+        volatile unsigned long unused0;
+};
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e1, e2
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned short e1;volatile unsigned char e2, e3
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned char e1, e2;volatile unsigned short e3
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e1, e2, e3, e4
+#else
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e2, e1
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned char e3, e2;volatile unsigned short e1
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned short e3;volatile unsigned char e2, e1
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e4, e3, e2, e1
+#endif
+
+struct tx3927_pcic_reg {
+        endian_def_s2(did, vid);
+        endian_def_s2(pcistat, pcicmd);
+        endian_def_b4(cc, scc, rpli, rid);
+        endian_def_b4(unused0, ht, mlt, cls);
+        volatile unsigned long ioba;            /* +10 */
+        volatile unsigned long mba;
+        volatile unsigned long unused1[5];
+        endian_def_s2(svid, ssvid);
+        volatile unsigned long unused2;         /* +30 */
+        endian_def_sb2(unused3, unused4, capptr);
+        volatile unsigned long unused5;
+        endian_def_b4(ml, mg, ip, il);
+        volatile unsigned long unused6;         /* +40 */
+        volatile unsigned long istat;
+        volatile unsigned long iim;
+        volatile unsigned long rrt;
+        volatile unsigned long unused7[3];              /* +50 */
+        volatile unsigned long ipbmma;
+        volatile unsigned long ipbioma;         /* +60 */
+        volatile unsigned long ilbmma;
+        volatile unsigned long ilbioma;
+        volatile unsigned long unused8[9];
+        volatile unsigned long tc;              /* +90 */
+        volatile unsigned long tstat;
+        volatile unsigned long tim;
+        volatile unsigned long tccmd;
+        volatile unsigned long pcirrt;          /* +a0 */
+        volatile unsigned long pcirrt_cmd;
+        volatile unsigned long pcirrdt;
+        volatile unsigned long unused9[3];
+        volatile unsigned long tlboap;
+        volatile unsigned long tlbiap;
+        volatile unsigned long tlbmma;          /* +c0 */
+        volatile unsigned long tlbioma;
+        volatile unsigned long sc_msg;
+        volatile unsigned long sc_be;
+        volatile unsigned long tbl;             /* +d0 */
+        volatile unsigned long unused10[3];
+        volatile unsigned long pwmng;           /* +e0 */
+        volatile unsigned long pwmngs;
+        volatile unsigned long unused11[6];
+        volatile unsigned long req_trace;               /* +100 */
+        volatile unsigned long pbapmc;
+        volatile unsigned long pbapms;
+        volatile unsigned long pbapmim;
+        volatile unsigned long bm;              /* +110 */
+        volatile unsigned long cpcibrs;
+        volatile unsigned long cpcibgs;
+        volatile unsigned long pbacs;
+        volatile unsigned long iobas;           /* +120 */
+        volatile unsigned long mbas;
+        volatile unsigned long lbc;
+        volatile unsigned long lbstat;
+        volatile unsigned long lbim;            /* +130 */
+        volatile unsigned long pcistatim;
+        volatile unsigned long ica;
+        volatile unsigned long icd;
+        volatile unsigned long iiadp;           /* +140 */
+        volatile unsigned long iscdp;
+        volatile unsigned long mmas;
+        volatile unsigned long iomas;
+        volatile unsigned long ipciaddr;                /* +150 */
+        volatile unsigned long ipcidata;
+        volatile unsigned long ipcibe;
+};
+
+struct tx3927_ccfg_reg {
+        volatile unsigned long ccfg;
+        volatile unsigned long crir;
+        volatile unsigned long pcfg;
+        volatile unsigned long tear;
+        volatile unsigned long pdcr;
+};
+
+/*
+ * SDRAMC
+ */
+
+/*
+ * ROMC
+ */
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX3927_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX3927_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX3927_DMA_MCR_RSFIF    0x00000080
+#define TX3927_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX3927_DMA_MCR_LE       0x00000004
+#define TX3927_DMA_MCR_RPRT     0x00000002
+#define TX3927_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX3927_DMA_CCR_DBINH    0x04000000
+#define TX3927_DMA_CCR_SBINH    0x02000000
+#define TX3927_DMA_CCR_CHRST    0x01000000
+#define TX3927_DMA_CCR_RVBYTE   0x00800000
+#define TX3927_DMA_CCR_ACKPOL   0x00400000
+#define TX3927_DMA_CCR_REQPL    0x00200000
+#define TX3927_DMA_CCR_EGREQ    0x00100000
+#define TX3927_DMA_CCR_CHDN     0x00080000
+#define TX3927_DMA_CCR_DNCTL    0x00060000
+#define TX3927_DMA_CCR_EXTRQ    0x00010000
+#define TX3927_DMA_CCR_INTRQD   0x0000e000
+#define TX3927_DMA_CCR_INTENE   0x00001000
+#define TX3927_DMA_CCR_INTENC   0x00000800
+#define TX3927_DMA_CCR_INTENT   0x00000400
+#define TX3927_DMA_CCR_CHNEN    0x00000200
+#define TX3927_DMA_CCR_XFACT    0x00000100
+#define TX3927_DMA_CCR_SNOP     0x00000080
+#define TX3927_DMA_CCR_DSTINC   0x00000040
+#define TX3927_DMA_CCR_SRCINC   0x00000020
+#define TX3927_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX3927_DMA_CCR_XFSZ_1W  TX3927_DMA_CCR_XFSZ(2)
+#define TX3927_DMA_CCR_XFSZ_4W  TX3927_DMA_CCR_XFSZ(4)
+#define TX3927_DMA_CCR_XFSZ_8W  TX3927_DMA_CCR_XFSZ(5)
+#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
+#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
+#define TX3927_DMA_CCR_MEMIO    0x00000002
+#define TX3927_DMA_CCR_ONEAD    0x00000001
+
+/* bits for CSRn */
+#define TX3927_DMA_CSR_CHNACT   0x00000100
+#define TX3927_DMA_CSR_ABCHC    0x00000080
+#define TX3927_DMA_CSR_NCHNC    0x00000040
+#define TX3927_DMA_CSR_NTRNFC   0x00000020
+#define TX3927_DMA_CSR_EXTDN    0x00000010
+#define TX3927_DMA_CSR_CFERR    0x00000008
+#define TX3927_DMA_CSR_CHERR    0x00000004
+#define TX3927_DMA_CSR_DESERR   0x00000002
+#define TX3927_DMA_CSR_SORERR   0x00000001
+
+/*
+ * IRC
+ */
+#define TX3927_IR_INT0  0
+#define TX3927_IR_INT1  1
+#define TX3927_IR_INT2  2
+#define TX3927_IR_INT3  3
+#define TX3927_IR_INT4  4
+#define TX3927_IR_INT5  5
+#define TX3927_IR_SIO0  6
+#define TX3927_IR_SIO1  7
+#define TX3927_IR_SIO(ch)       (6 + (ch))
+#define TX3927_IR_DMA   8
+#define TX3927_IR_PIO   9
+#define TX3927_IR_PCI   10
+#define TX3927_IR_TMR(ch)       (13 + (ch))
+#define TX3927_NUM_IR   16
+
+/*
+ * PCIC
+ */
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci.h */
+#define PCI_STATUS_NEW_CAP      0x0010
+
+/* bits for ISTAT/IIM */
+#define TX3927_PCIC_IIM_ALL     0x00001600
+
+/* bits for TC */
+#define TX3927_PCIC_TC_OF16E    0x00000020
+#define TX3927_PCIC_TC_IF8E     0x00000010
+#define TX3927_PCIC_TC_OF8E     0x00000008
+
+/* bits for TSTAT/TIM */
+#define TX3927_PCIC_TIM_ALL     0x0003ffff
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
+
+/* bits for PBAPMC */
+#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
+#define TX3927_PCIC_PBAPMC_PBAEN        0x00000002
+#define TX3927_PCIC_PBAPMC_BMCEN        0x00000001
+
+/* bits for LBSTAT/LBIM */
+#define TX3927_PCIC_LBIM_ALL    0x0000003e
+
+/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX3927_PCIC_PCISTATIM_ALL       0x0000f900
+
+/* bits for LBC */
+#define TX3927_PCIC_LBC_IBSE    0x00004000
+#define TX3927_PCIC_LBC_TIBSE   0x00002000
+#define TX3927_PCIC_LBC_TMFBSE  0x00001000
+#define TX3927_PCIC_LBC_HRST    0x00000800
+#define TX3927_PCIC_LBC_SRST    0x00000400
+#define TX3927_PCIC_LBC_EPCAD   0x00000200
+#define TX3927_PCIC_LBC_MSDSE   0x00000100
+#define TX3927_PCIC_LBC_CRR     0x00000080
+#define TX3927_PCIC_LBC_ILMDE   0x00000040
+#define TX3927_PCIC_LBC_ILIDE   0x00000020
+
+#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX3927_PCIC_MAX_DEVNU   TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX3927_CCFG_TLBOFF      0x00020000
+#define TX3927_CCFG_BEOW        0x00010000
+#define TX3927_CCFG_WR  0x00008000
+#define TX3927_CCFG_TOE 0x00004000
+#define TX3927_CCFG_PCIXARB     0x00002000
+#define TX3927_CCFG_PCI3        0x00001000
+#define TX3927_CCFG_PSNP        0x00000800
+#define TX3927_CCFG_PPRI        0x00000400
+#define TX3927_CCFG_PLLM        0x00000030
+#define TX3927_CCFG_ENDIAN      0x00000004
+#define TX3927_CCFG_HALT        0x00000002
+#define TX3927_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX3927_PCFG_SYSCLKEN    0x08000000
+#define TX3927_PCFG_SDRCLKEN_ALL        0x07c00000
+#define TX3927_PCFG_SDRCLKEN(ch)        (0x00400000<<(ch))
+#define TX3927_PCFG_PCICLKEN_ALL        0x003c0000
+#define TX3927_PCFG_PCICLKEN(ch)        (0x00040000<<(ch))
+#define TX3927_PCFG_SELALL      0x0003ffff
+#define TX3927_PCFG_SELCS       0x00020000
+#define TX3927_PCFG_SELDSF      0x00010000
+#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
+#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
+#define TX3927_PCFG_SELSIO_ALL  0x00003000
+#define TX3927_PCFG_SELSIO(ch)  (0x00001000<<(ch))
+#define TX3927_PCFG_SELTMR_ALL  0x00000e00
+#define TX3927_PCFG_SELTMR(ch)  (0x00000200<<(ch))
+#define TX3927_PCFG_SELDONE     0x00000100
+#define TX3927_PCFG_INTDMA_ALL  0x000000f0
+#define TX3927_PCFG_INTDMA(ch)  (0x00000010<<(ch))
+#define TX3927_PCFG_SELDMA_ALL  0x0000000f
+#define TX3927_PCFG_SELDMA(ch)  (0x00000001<<(ch))
+
+#define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
+#define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
+#define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
+#define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
+#define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
+#define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
+#define tx3927_pioptr           ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
+
+#define TX3927_REV_PCODE()      (tx3927_ccfgptr->crir >> 16)
+#define TX3927_ROMC_BA(ch)      (tx3927_romcptr->cr[(ch)] & 0xfff00000)
+#define TX3927_ROMC_SIZE(ch)    \
+        (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
+#define TX3927_ROMC_WIDTH(ch)   (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
+
+void tx3927_wdt_init(void);
+void tx3927_setup(void);
+void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
+void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
+struct pci_controller;
+void tx3927_pcic_setup(struct pci_controller *channel,
+                       unsigned long sdram_size, int extarb);
+void tx3927_setup_pcierr_irq(void);
+void tx3927_irq_init(void);
+void tx3927_mtd_init(int ch);
+
+#endif /* __ASM_TXX9_TX3927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
new file mode 100644
index 000000000..284eea752
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -0,0 +1,273 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2006 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_TX4927_H
+#define __ASM_TXX9_TX4927_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4927pcic.h>
+
+#ifdef CONFIG_64BIT
+#define TX4927_REG_BASE 0xffffffffff1f0000UL
+#else
+#define TX4927_REG_BASE 0xff1f0000UL
+#endif
+#define TX4927_REG_SIZE 0x00010000
+
+#define TX4927_SDRAMC_REG       (TX4927_REG_BASE + 0x8000)
+#define TX4927_EBUSC_REG        (TX4927_REG_BASE + 0x9000)
+#define TX4927_DMA_REG          (TX4927_REG_BASE + 0xb000)
+#define TX4927_PCIC_REG         (TX4927_REG_BASE + 0xd000)
+#define TX4927_CCFG_REG         (TX4927_REG_BASE + 0xe000)
+#define TX4927_IRC_REG          (TX4927_REG_BASE + 0xf600)
+#define TX4927_NR_TMR   3
+#define TX4927_TMR_REG(ch)      (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
+#define TX4927_NR_SIO   2
+#define TX4927_SIO_REG(ch)      (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX4927_PIO_REG          (TX4927_REG_BASE + 0xf500)
+#define TX4927_ACLC_REG         (TX4927_REG_BASE + 0xf700)
+
+#define TX4927_IR_ECCERR        0
+#define TX4927_IR_WTOERR        1
+#define TX4927_NUM_IR_INT       6
+#define TX4927_IR_INT(n)        (2 + (n))
+#define TX4927_NUM_IR_SIO       2
+#define TX4927_IR_SIO(n)        (8 + (n))
+#define TX4927_NUM_IR_DMA       4
+#define TX4927_IR_DMA(n)        (10 + (n))
+#define TX4927_IR_PIO           14
+#define TX4927_IR_PDMAC         15
+#define TX4927_IR_PCIC          16
+#define TX4927_NUM_IR_TMR       3
+#define TX4927_IR_TMR(n)        (17 + (n))
+#define TX4927_IR_PCIERR        22
+#define TX4927_IR_PCIPME        23
+#define TX4927_IR_ACLC          24
+#define TX4927_IR_ACLCPME       25
+#define TX4927_NUM_IR   32
+
+#define TX4927_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4927_NUM_PIO  16
+
+struct tx4927_sdramc_reg {
+        u64 cr[4];
+        u64 unused0[4];
+        u64 tr;
+        u64 unused1[2];
+        u64 cmd;
+};
+
+struct tx4927_ebusc_reg {
+        u64 cr[8];
+};
+
+struct tx4927_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+};
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_WDRST       0x0000020000000000ULL
+#define TX4927_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4927_CCFG_TINTDIS     0x01000000
+#define TX4927_CCFG_PCI66       0x00800000
+#define TX4927_CCFG_PCIMODE     0x00400000
+#define TX4927_CCFG_DIVMODE_MASK        0x000e0000
+#define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
+#define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
+#define TX4927_CCFG_BEOW        0x00010000
+#define TX4927_CCFG_WR  0x00008000
+#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_PCIARB      0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
+#define TX4927_CCFG_SYSSP_MASK  0x000000c0
+#define TX4927_CCFG_ENDIAN      0x00000004
+#define TX4927_CCFG_HALT        0x00000002
+#define TX4927_CCFG_ACEHOLD     0x00000001
+#define TX4927_CCFG_W1CBITS     (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4927_PCFG_SYSCLKEN    0x08000000
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4927_PCFG_SEL2        0x00000200
+#define TX4927_PCFG_SEL1        0x00000100
+#define TX4927_PCFG_DMASEL_ALL  0x000000ff
+#define TX4927_PCFG_DMASEL0_MASK        0x00000003
+#define TX4927_PCFG_DMASEL1_MASK        0x0000000c
+#define TX4927_PCFG_DMASEL2_MASK        0x00000030
+#define TX4927_PCFG_DMASEL3_MASK        0x000000c0
+#define TX4927_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4927_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4927_PCFG_DMASEL0_ACL0        0x00000002
+#define TX4927_PCFG_DMASEL0_ACL2        0x00000003
+#define TX4927_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4927_PCFG_DMASEL1_SIO1        0x00000004
+#define TX4927_PCFG_DMASEL1_ACL1        0x00000008
+#define TX4927_PCFG_DMASEL1_ACL3        0x0000000c
+#define TX4927_PCFG_DMASEL2_DRQ2        0x00000000      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_SIO0        0x00000010      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_ACL1        0x00000000      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL2        0x00000020      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL0        0x00000030      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4927_PCFG_DMASEL3_SIO0        0x00000040
+#define TX4927_PCFG_DMASEL3_ACL3        0x00000080
+#define TX4927_PCFG_DMASEL3_ACL1        0x000000c0
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_ACLCKD    0x02000000
+#define TX4927_CLKCTR_PIOCKD    0x01000000
+#define TX4927_CLKCTR_DMACKD    0x00800000
+#define TX4927_CLKCTR_PCICKD    0x00400000
+#define TX4927_CLKCTR_TM0CKD    0x00100000
+#define TX4927_CLKCTR_TM1CKD    0x00080000
+#define TX4927_CLKCTR_TM2CKD    0x00040000
+#define TX4927_CLKCTR_SIO0CKD   0x00020000
+#define TX4927_CLKCTR_SIO1CKD   0x00010000
+#define TX4927_CLKCTR_ACLRST    0x00000200
+#define TX4927_CLKCTR_PIORST    0x00000100
+#define TX4927_CLKCTR_DMARST    0x00000080
+#define TX4927_CLKCTR_PCIRST    0x00000040
+#define TX4927_CLKCTR_TM0RST    0x00000010
+#define TX4927_CLKCTR_TM1RST    0x00000008
+#define TX4927_CLKCTR_TM2RST    0x00000004
+#define TX4927_CLKCTR_SIO0RST   0x00000002
+#define TX4927_CLKCTR_SIO1RST   0x00000001
+
+#define tx4927_sdramcptr \
+                ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr \
+                ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr \
+                ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
+#define tx4927_pioptr           ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
+
+#define TX4927_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
+
+#define TX4927_SDRAMC_CR(ch)    __raw_readq(&tx4927_sdramcptr->cr[(ch)])
+#define TX4927_SDRAMC_BA(ch)    ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
+#define TX4927_SDRAMC_SIZE(ch)  \
+        ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
+
+#define TX4927_EBUSC_CR(ch)     __raw_readq(&tx4927_ebuscptr->cr[(ch)])
+#define TX4927_EBUSC_BA(ch)     ((TX4927_EBUSC_CR(ch) >> 48) << 20)
+#define TX4927_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
+#define TX4927_EBUSC_WIDTH(ch)  \
+        (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
+
+/* utilities */
+static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) & ~bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) | bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+
+/* These functions are not interrupt safe. */
+static inline void tx4927_ccfg_clear(__u64 bits)
+{
+        ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
+                       & ~(TX4927_CCFG_W1CBITS | bits),
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_set(__u64 bits)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~TX4927_CCFG_W1CBITS) | bits,
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_change(__u64 change, __u64 new)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~(TX4927_CCFG_W1CBITS | change)) |
+                       new,
+                       &tx4927_ccfgptr->ccfg);
+}
+
+unsigned int tx4927_get_mem_size(void);
+void tx4927_wdt_init(void);
+void tx4927_setup(void);
+void tx4927_time_init(unsigned int tmrnr);
+void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
+int tx4927_report_pciclk(void);
+int tx4927_pciclk66_setup(void);
+void tx4927_setup_pcierr_irq(void);
+void tx4927_irq_init(void);
+void tx4927_mtd_init(int ch);
+void tx4927_dmac_init(int memcpy_chan);
+void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
+
+#endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
new file mode 100644
index 000000000..9eab2698c
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
@@ -0,0 +1,203 @@
+/*
+ * include/asm-mips/txx9/tx4927pcic.h
+ * TX4927 PCI controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_TX4927PCIC_H
+#define __ASM_TXX9_TX4927PCIC_H
+
+#include <linux/pci.h>
+#include <linux/irqreturn.h>
+
+struct tx4927_pcic_reg {
+        u32 pciid;
+        u32 pcistatus;
+        u32 pciccrev;
+        u32 pcicfg1;
+        u32 p2gm0plbase;                /* +10 */
+        u32 p2gm0pubase;
+        u32 p2gm1plbase;
+        u32 p2gm1pubase;
+        u32 p2gm2pbase;         /* +20 */
+        u32 p2giopbase;
+        u32 unused0;
+        u32 pcisid;
+        u32 unused1;            /* +30 */
+        u32 pcicapptr;
+        u32 unused2;
+        u32 pcicfg2;
+        u32 g2ptocnt;           /* +40 */
+        u32 unused3[15];
+        u32 g2pstatus;          /* +80 */
+        u32 g2pmask;
+        u32 pcisstatus;
+        u32 pcimask;
+        u32 p2gcfg;             /* +90 */
+        u32 p2gstatus;
+        u32 p2gmask;
+        u32 p2gccmd;
+        u32 unused4[24];                /* +a0 */
+        u32 pbareqport;         /* +100 */
+        u32 pbacfg;
+        u32 pbastatus;
+        u32 pbamask;
+        u32 pbabm;              /* +110 */
+        u32 pbacreq;
+        u32 pbacgnt;
+        u32 pbacstate;
+        u64 g2pmgbase[3];               /* +120 */
+        u64 g2piogbase;
+        u32 g2pmmask[3];                /* +140 */
+        u32 g2piomask;
+        u64 g2pmpbase[3];               /* +150 */
+        u64 g2piopbase;
+        u32 pciccfg;            /* +170 */
+        u32 pcicstatus;
+        u32 pcicmask;
+        u32 unused5;
+        u64 p2gmgbase[3];               /* +180 */
+        u64 p2giogbase;
+        u32 g2pcfgadrs;         /* +1a0 */
+        u32 g2pcfgdata;
+        u32 unused6[8];
+        u32 g2pintack;
+        u32 g2pspc;
+        u32 unused7[12];                /* +1d0 */
+        u64 pdmca;              /* +200 */
+        u64 pdmga;
+        u64 pdmpa;
+        u64 pdmctr;
+        u64 pdmcfg;             /* +220 */
+        u64 pdmsts;
+};
+
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci_regs.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci_regs.h */
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
+#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for PBASTATUS/PBAMASK */
+#define TX4927_PCIC_PBASTATUS_ALL       0x00000001
+#define TX4927_PCIC_PBASTATUS_BM        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PMnGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PIOGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4927_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4927_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4927_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4927_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4927_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4927_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4927_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4927_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST        0x00000800
+#define TX4927_PCIC_PCICCFG_SRST        0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4927_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4927_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4927_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4927_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4927_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4927_PCIC_PCICCFG_ICAEN       0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/* bits for PDMCFG */
+#define TX4927_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4927_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4927_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4927_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4927_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4927_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4927_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4927_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4927_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4927_PCIC_PDMCFG_CHRST        0x00000001
+
+/* bits for PDMSTS */
+#define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4927_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4927_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4927_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4927_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4927_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4927_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4927_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4927_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4927_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4927_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4927_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4927_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4927_PCIC_PDMSTS_ALL_ERR      0x0000000f
+
+struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
+        struct pci_controller *channel);
+void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
+                       struct pci_controller *channel, int extarb);
+void tx4927_report_pcic_status(void);
+char *tx4927_pcibios_setup(char *str);
+void tx4927_dump_pcic_settings(void);
+irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
+
+#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
new file mode 100644
index 000000000..6ca767ee6
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -0,0 +1,312 @@
+/*
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_TX4938_H
+#define __ASM_TXX9_TX4938_H
+
+/* some controllers are compatible with 4927 */
+#include <asm/txx9/tx4927.h>
+
+#ifdef CONFIG_64BIT
+#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
+#else
+#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
+#endif
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+
+struct tx4938_sramc_reg {
+        u64 cr;
+};
+
+struct tx4938_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+        u64 unused3;
+        u64 jmpadr;
+};
+
+/*
+ * IRC
+ */
+
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+
+#define TX4938_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4938_NUM_PIO  16
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       0x0000020000000000ULL
+#define TX4938_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIARB      0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
+#define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
+#define TX4938_PCFG_ATA_SEL     0x2000000000000000ULL
+#define TX4938_PCFG_ISA_SEL     0x1000000000000000ULL
+#define TX4938_PCFG_SPI_SEL     0x0800000000000000ULL
+#define TX4938_PCFG_NDF_SEL     0x0400000000000000ULL
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
+#define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+
+#define tx4938_sdramcptr        tx4927_sdramcptr
+#define tx4938_ebuscptr         tx4927_ebuscptr
+#define tx4938_pcicptr          tx4927_pcicptr
+#define tx4938_pcic1ptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr \
+                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
+#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
+#define tx4938_sramcptr \
+                ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
+
+
+#define TX4938_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
+
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
+
+#define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
+#define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
+#define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
+
+#define TX4938_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
+#define TX4938_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
+#define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
+#define TX4938_EBUSC_WIDTH(ch)  TX4927_EBUSC_WIDTH(ch)
+
+#define tx4938_get_mem_size() tx4927_get_mem_size()
+void tx4938_wdt_init(void);
+void tx4938_setup(void);
+void tx4938_time_init(unsigned int tmrnr);
+void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
+void tx4938_spi_init(int busid);
+void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
+int tx4938_report_pciclk(void);
+void tx4938_report_pci1clk(void);
+int tx4938_pciclk66_setup(void);
+struct pci_dev;
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+void tx4938_setup_pcierr_irq(void);
+void tx4938_irq_init(void);
+void tx4938_mtd_init(int ch);
+void tx4938_ndfmc_init(unsigned int hold, unsigned int spw);
+
+struct tx4938ide_platform_info {
+        /*
+         * I/O port shift, for platforms with ports that are
+         * constantly spaced and need larger than the 1-byte
+         * spacing used by ata_std_ports().
+         */
+        unsigned int ioport_shift;
+        unsigned int gbus_clock;        /*  0 means no PIO mode tuning. */
+        unsigned int ebus_ch;
+};
+
+void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
+void tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1);
+void tx4938_aclc_init(void);
+void tx4938_sramc_init(void);
+
+#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
new file mode 100644
index 000000000..abf980af9
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -0,0 +1,524 @@
+/*
+ * Definitions for TX4939
+ *
+ * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_TX4939_H
+#define __ASM_TXX9_TX4939_H
+
+/* some controllers are compatible with 4927/4938 */
+#include <asm/txx9/tx4938.h>
+
+#ifdef CONFIG_64BIT
+#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
+#else
+#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
+#endif
+#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
+
+#define TX4939_ATA_REG(ch)      (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
+#define TX4939_NDFMC_REG        (TX4939_REG_BASE + 0x5000)
+#define TX4939_SRAMC_REG        (TX4939_REG_BASE + 0x6000)
+#define TX4939_CRYPTO_REG       (TX4939_REG_BASE + 0x6800)
+#define TX4939_PCIC1_REG        (TX4939_REG_BASE + 0x7000)
+#define TX4939_DDRC_REG         (TX4939_REG_BASE + 0x8000)
+#define TX4939_EBUSC_REG        (TX4939_REG_BASE + 0x9000)
+#define TX4939_VPC_REG          (TX4939_REG_BASE + 0xa000)
+#define TX4939_DMA_REG(ch)      (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4939_PCIC_REG         (TX4939_REG_BASE + 0xd000)
+#define TX4939_CCFG_REG         (TX4939_REG_BASE + 0xe000)
+#define TX4939_IRC_REG          (TX4939_REG_BASE + 0xe800)
+#define TX4939_NR_TMR   6       /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
+#define TX4939_TMR_REG(ch)      \
+        (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
+#define TX4939_NR_SIO   4       /* 0xf300, 0xf400, 0xf380, 0xf480 */
+#define TX4939_SIO_REG(ch)      \
+        (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
+#define TX4939_ACLC_REG         (TX4939_REG_BASE + 0xf700)
+#define TX4939_SPI_REG          (TX4939_REG_BASE + 0xf800)
+#define TX4939_I2C_REG          (TX4939_REG_BASE + 0xf900)
+#define TX4939_I2S_REG          (TX4939_REG_BASE + 0xfa00)
+#define TX4939_RTC_REG          (TX4939_REG_BASE + 0xfb00)
+#define TX4939_CIR_REG          (TX4939_REG_BASE + 0xfc00)
+
+#define TX4939_RNG_REG          (TX4939_CRYPTO_REG + 0xb0)
+
+struct tx4939_le_reg {
+        __u32 r;
+        __u32 unused;
+};
+
+struct tx4939_ddrc_reg {
+        struct tx4939_le_reg ctl[47];
+        __u64 unused0[17];
+        __u64 winen;
+        __u64 win[4];
+};
+
+struct tx4939_ccfg_reg {
+        __u64 ccfg;
+        __u64 crir;
+        __u64 pcfg;
+        __u64 toea;
+        __u64 clkctr;
+        __u64 unused0;
+        __u64 garbc;
+        __u64 unused1[2];
+        __u64 ramp;
+        __u64 unused2[2];
+        __u64 dskwctrl;
+        __u64 mclkosc;
+        __u64 mclkctl;
+        __u64 unused3[17];
+        struct {
+                __u64 mr;
+                __u64 dr;
+        } gpio[2];
+};
+
+struct tx4939_irc_reg {
+        struct tx4939_le_reg den;
+        struct tx4939_le_reg scipb;
+        struct tx4939_le_reg dm[2];
+        struct tx4939_le_reg lvl[16];
+        struct tx4939_le_reg msk;
+        struct tx4939_le_reg edc;
+        struct tx4939_le_reg pnd0;
+        struct tx4939_le_reg cs;
+        struct tx4939_le_reg pnd1;
+        struct tx4939_le_reg dm2[2];
+        struct tx4939_le_reg dbr[2];
+        struct tx4939_le_reg dben;
+        struct tx4939_le_reg unused0[2];
+        struct tx4939_le_reg flag[2];
+        struct tx4939_le_reg pol;
+        struct tx4939_le_reg cnt;
+        struct tx4939_le_reg maskint;
+        struct tx4939_le_reg maskext;
+};
+
+struct tx4939_crypto_reg {
+        struct tx4939_le_reg csr;
+        struct tx4939_le_reg idesptr;
+        struct tx4939_le_reg cdesptr;
+        struct tx4939_le_reg buserr;
+        struct tx4939_le_reg cip_tout;
+        struct tx4939_le_reg cir;
+        union {
+                struct {
+                        struct tx4939_le_reg data[8];
+                        struct tx4939_le_reg ctrl;
+                } gen;
+                struct {
+                        struct {
+                                struct tx4939_le_reg l;
+                                struct tx4939_le_reg u;
+                        } key[3], ini;
+                        struct tx4939_le_reg ctrl;
+                } des;
+                struct {
+                        struct tx4939_le_reg key[4];
+                        struct tx4939_le_reg ini[4];
+                        struct tx4939_le_reg ctrl;
+                } aes;
+                struct {
+                        struct {
+                                struct tx4939_le_reg l;
+                                struct tx4939_le_reg u;
+                        } cnt;
+                        struct tx4939_le_reg ini[5];
+                        struct tx4939_le_reg unused;
+                        struct tx4939_le_reg ctrl;
+                } hash;
+        } cdr;
+        struct tx4939_le_reg unused0[7];
+        struct tx4939_le_reg rcsr;
+        struct tx4939_le_reg rpr;
+        __u64 rdr;
+        __u64 ror[3];
+        struct tx4939_le_reg unused1[2];
+        struct tx4939_le_reg xorslr;
+        struct tx4939_le_reg xorsur;
+};
+
+struct tx4939_crypto_desc {
+        __u32 src;
+        __u32 dst;
+        __u32 next;
+        __u32 ctrl;
+        __u32 index;
+        __u32 xor;
+};
+
+struct tx4939_vpc_reg {
+        struct tx4939_le_reg csr;
+        struct {
+                struct tx4939_le_reg ctrlA;
+                struct tx4939_le_reg ctrlB;
+                struct tx4939_le_reg idesptr;
+                struct tx4939_le_reg cdesptr;
+        } port[3];
+        struct tx4939_le_reg buserr;
+};
+
+struct tx4939_vpc_desc {
+        __u32 src;
+        __u32 next;
+        __u32 ctrl1;
+        __u32 ctrl2;
+};
+
+/*
+ * IRC
+ */
+#define TX4939_IR_NONE  0
+#define TX4939_IR_DDR   1
+#define TX4939_IR_WTOERR        2
+#define TX4939_NUM_IR_INT       3
+#define TX4939_IR_INT(n)        (3 + (n))
+#define TX4939_NUM_IR_ETH       2
+#define TX4939_IR_ETH(n)        ((n) ? 43 : 6)
+#define TX4939_IR_VIDEO 7
+#define TX4939_IR_CIR   8
+#define TX4939_NUM_IR_SIO       4
+#define TX4939_IR_SIO(n)        ((n) ? 43 + (n) : 9)    /* 9,44-46 */
+#define TX4939_NUM_IR_DMA       4
+#define TX4939_IR_DMA(ch, n)    (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
+#define TX4939_IR_IRC   14
+#define TX4939_IR_PDMAC 15
+#define TX4939_NUM_IR_TMR       6
+#define TX4939_IR_TMR(n)        (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
+#define TX4939_NUM_IR_ATA       2
+#define TX4939_IR_ATA(n)        (19 + (n))
+#define TX4939_IR_ACLC  21
+#define TX4939_IR_CIPHER        26
+#define TX4939_IR_INTA  27
+#define TX4939_IR_INTB  28
+#define TX4939_IR_INTC  29
+#define TX4939_IR_INTD  30
+#define TX4939_IR_I2C   33
+#define TX4939_IR_SPI   34
+#define TX4939_IR_PCIC  35
+#define TX4939_IR_PCIC1 36
+#define TX4939_IR_PCIERR        37
+#define TX4939_IR_PCIPME        38
+#define TX4939_IR_NDFMC 39
+#define TX4939_IR_ACLCPME       40
+#define TX4939_IR_RTC   41
+#define TX4939_IR_RND   42
+#define TX4939_IR_I2S   47
+#define TX4939_NUM_IR   64
+
+#define TX4939_IRC_INT  2       /* IP[2] in Status register */
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4939_CCFG_PCIBOOT     0x0000040000000000ULL
+#define TX4939_CCFG_WDRST       0x0000020000000000ULL
+#define TX4939_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4939_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4939_CCFG_GTOT_MASK   0x06000000
+#define TX4939_CCFG_GTOT_4096   0x06000000
+#define TX4939_CCFG_GTOT_2048   0x04000000
+#define TX4939_CCFG_GTOT_1024   0x02000000
+#define TX4939_CCFG_GTOT_512    0x00000000
+#define TX4939_CCFG_TINTDIS     0x01000000
+#define TX4939_CCFG_PCI66       0x00800000
+#define TX4939_CCFG_PCIMODE     0x00400000
+#define TX4939_CCFG_SSCG        0x00100000
+#define TX4939_CCFG_MULCLK_MASK 0x000e0000
+#define TX4939_CCFG_MULCLK_8    (0x7 << 17)
+#define TX4939_CCFG_MULCLK_9    (0x0 << 17)
+#define TX4939_CCFG_MULCLK_10   (0x1 << 17)
+#define TX4939_CCFG_MULCLK_11   (0x2 << 17)
+#define TX4939_CCFG_MULCLK_12   (0x3 << 17)
+#define TX4939_CCFG_MULCLK_13   (0x4 << 17)
+#define TX4939_CCFG_MULCLK_14   (0x5 << 17)
+#define TX4939_CCFG_MULCLK_15   (0x6 << 17)
+#define TX4939_CCFG_BEOW        0x00010000
+#define TX4939_CCFG_WR  0x00008000
+#define TX4939_CCFG_TOE 0x00004000
+#define TX4939_CCFG_PCIARB      0x00002000
+#define TX4939_CCFG_YDIVMODE_MASK       0x00001c00
+#define TX4939_CCFG_YDIVMODE_2  (0x0 << 10)
+#define TX4939_CCFG_YDIVMODE_3  (0x1 << 10)
+#define TX4939_CCFG_YDIVMODE_5  (0x6 << 10)
+#define TX4939_CCFG_YDIVMODE_6  (0x7 << 10)
+#define TX4939_CCFG_PTSEL       0x00000200
+#define TX4939_CCFG_BESEL       0x00000100
+#define TX4939_CCFG_SYSSP_MASK  0x000000c0
+#define TX4939_CCFG_ACKSEL      0x00000020
+#define TX4939_CCFG_ROMW        0x00000010
+#define TX4939_CCFG_ENDIAN      0x00000004
+#define TX4939_CCFG_ARMODE      0x00000002
+#define TX4939_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4939_PCFG_SIO2MODE_MASK       0xc000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_GPIO       0x8000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO2       0x4000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO0       0x0000000000000000ULL
+#define TX4939_PCFG_SPIMODE     0x2000000000000000ULL
+#define TX4939_PCFG_I2CMODE     0x1000000000000000ULL
+#define TX4939_PCFG_I2SMODE_MASK        0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_GPIO        0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S_ALT     0x0400000000000000ULL
+#define TX4939_PCFG_I2SMODE_ACLC        0x0000000000000000ULL
+#define TX4939_PCFG_SIO3MODE    0x0200000000000000ULL
+#define TX4939_PCFG_DMASEL3     0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_SIO0        0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_NDFC        0x0000000000000000ULL
+#define TX4939_PCFG_VSSMODE     0x0000200000000000ULL
+#define TX4939_PCFG_VPSMODE     0x0000100000000000ULL
+#define TX4939_PCFG_ET1MODE     0x0000080000000000ULL
+#define TX4939_PCFG_ET0MODE     0x0000040000000000ULL
+#define TX4939_PCFG_ATA1MODE    0x0000020000000000ULL
+#define TX4939_PCFG_ATA0MODE    0x0000010000000000ULL
+#define TX4939_PCFG_BP_PLL      0x0000000100000000ULL
+
+#define TX4939_PCFG_SYSCLKEN    0x08000000
+#define TX4939_PCFG_PCICLKEN_ALL        0x000f0000
+#define TX4939_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4939_PCFG_SPEED1      0x00002000
+#define TX4939_PCFG_SPEED0      0x00001000
+#define TX4939_PCFG_ITMODE      0x00000300
+#define TX4939_PCFG_DMASEL_ALL  (0x00000007 | TX4939_PCFG_DMASEL3)
+#define TX4939_PCFG_DMASEL2     0x00000004
+#define TX4939_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4939_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4939_PCFG_DMASEL1     0x00000002
+#define TX4939_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4939_PCFG_DMASEL0     0x00000001
+#define TX4939_PCFG_DMASEL0_DRQ0        0x00000000
+
+/* CLKCTR : Clock Control */
+#define TX4939_CLKCTR_IOSCKD    0x8000000000000000ULL
+#define TX4939_CLKCTR_SYSCKD    0x4000000000000000ULL
+#define TX4939_CLKCTR_TM5CKD    0x2000000000000000ULL
+#define TX4939_CLKCTR_TM4CKD    0x1000000000000000ULL
+#define TX4939_CLKCTR_TM3CKD    0x0800000000000000ULL
+#define TX4939_CLKCTR_CIRCKD    0x0400000000000000ULL
+#define TX4939_CLKCTR_SIO3CKD   0x0200000000000000ULL
+#define TX4939_CLKCTR_SIO2CKD   0x0100000000000000ULL
+#define TX4939_CLKCTR_SIO1CKD   0x0080000000000000ULL
+#define TX4939_CLKCTR_VPCCKD    0x0040000000000000ULL
+#define TX4939_CLKCTR_EPCICKD   0x0020000000000000ULL
+#define TX4939_CLKCTR_ETH1CKD   0x0008000000000000ULL
+#define TX4939_CLKCTR_ATA1CKD   0x0004000000000000ULL
+#define TX4939_CLKCTR_BROMCKD   0x0002000000000000ULL
+#define TX4939_CLKCTR_NDCCKD    0x0001000000000000ULL
+#define TX4939_CLKCTR_I2CCKD    0x0000800000000000ULL
+#define TX4939_CLKCTR_ETH0CKD   0x0000400000000000ULL
+#define TX4939_CLKCTR_SPICKD    0x0000200000000000ULL
+#define TX4939_CLKCTR_SRAMCKD   0x0000100000000000ULL
+#define TX4939_CLKCTR_PCI1CKD   0x0000080000000000ULL
+#define TX4939_CLKCTR_DMA1CKD   0x0000040000000000ULL
+#define TX4939_CLKCTR_ACLCKD    0x0000020000000000ULL
+#define TX4939_CLKCTR_ATA0CKD   0x0000010000000000ULL
+#define TX4939_CLKCTR_DMA0CKD   0x0000008000000000ULL
+#define TX4939_CLKCTR_PCICCKD   0x0000004000000000ULL
+#define TX4939_CLKCTR_I2SCKD    0x0000002000000000ULL
+#define TX4939_CLKCTR_TM0CKD    0x0000001000000000ULL
+#define TX4939_CLKCTR_TM1CKD    0x0000000800000000ULL
+#define TX4939_CLKCTR_TM2CKD    0x0000000400000000ULL
+#define TX4939_CLKCTR_SIO0CKD   0x0000000200000000ULL
+#define TX4939_CLKCTR_CYPCKD    0x0000000100000000ULL
+#define TX4939_CLKCTR_IOSRST    0x80000000
+#define TX4939_CLKCTR_SYSRST    0x40000000
+#define TX4939_CLKCTR_TM5RST    0x20000000
+#define TX4939_CLKCTR_TM4RST    0x10000000
+#define TX4939_CLKCTR_TM3RST    0x08000000
+#define TX4939_CLKCTR_CIRRST    0x04000000
+#define TX4939_CLKCTR_SIO3RST   0x02000000
+#define TX4939_CLKCTR_SIO2RST   0x01000000
+#define TX4939_CLKCTR_SIO1RST   0x00800000
+#define TX4939_CLKCTR_VPCRST    0x00400000
+#define TX4939_CLKCTR_EPCIRST   0x00200000
+#define TX4939_CLKCTR_ETH1RST   0x00080000
+#define TX4939_CLKCTR_ATA1RST   0x00040000
+#define TX4939_CLKCTR_BROMRST   0x00020000
+#define TX4939_CLKCTR_NDCRST    0x00010000
+#define TX4939_CLKCTR_I2CRST    0x00008000
+#define TX4939_CLKCTR_ETH0RST   0x00004000
+#define TX4939_CLKCTR_SPIRST    0x00002000
+#define TX4939_CLKCTR_SRAMRST   0x00001000
+#define TX4939_CLKCTR_PCI1RST   0x00000800
+#define TX4939_CLKCTR_DMA1RST   0x00000400
+#define TX4939_CLKCTR_ACLRST    0x00000200
+#define TX4939_CLKCTR_ATA0RST   0x00000100
+#define TX4939_CLKCTR_DMA0RST   0x00000080
+#define TX4939_CLKCTR_PCICRST   0x00000040
+#define TX4939_CLKCTR_I2SRST    0x00000020
+#define TX4939_CLKCTR_TM0RST    0x00000010
+#define TX4939_CLKCTR_TM1RST    0x00000008
+#define TX4939_CLKCTR_TM2RST    0x00000004
+#define TX4939_CLKCTR_SIO0RST   0x00000002
+#define TX4939_CLKCTR_CYPRST    0x00000001
+
+/*
+ * CRYPTO
+ */
+#define TX4939_CRYPTO_CSR_SAESO 0x08000000
+#define TX4939_CRYPTO_CSR_SAESI 0x04000000
+#define TX4939_CRYPTO_CSR_SDESO 0x02000000
+#define TX4939_CRYPTO_CSR_SDESI 0x01000000
+#define TX4939_CRYPTO_CSR_INDXBST_MASK  0x00700000
+#define TX4939_CRYPTO_CSR_INDXBST(n)    ((n) << 20)
+#define TX4939_CRYPTO_CSR_TOINT 0x00080000
+#define TX4939_CRYPTO_CSR_DCINT 0x00040000
+#define TX4939_CRYPTO_CSR_GBINT 0x00010000
+#define TX4939_CRYPTO_CSR_INDXAST_MASK  0x0000e000
+#define TX4939_CRYPTO_CSR_INDXAST(n)    ((n) << 13)
+#define TX4939_CRYPTO_CSR_CSWAP_MASK    0x00001800
+#define TX4939_CRYPTO_CSR_CSWAP_NONE    0x00000000
+#define TX4939_CRYPTO_CSR_CSWAP_IN      0x00000800
+#define TX4939_CRYPTO_CSR_CSWAP_OUT     0x00001000
+#define TX4939_CRYPTO_CSR_CSWAP_BOTH    0x00001800
+#define TX4939_CRYPTO_CSR_CDIV_MASK     0x00000600
+#define TX4939_CRYPTO_CSR_CDIV_DIV2     0x00000000
+#define TX4939_CRYPTO_CSR_CDIV_DIV1     0x00000200
+#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT  0x00000400
+#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT  0x00000600
+#define TX4939_CRYPTO_CSR_PDINT_MASK    0x000000c0
+#define TX4939_CRYPTO_CSR_PDINT_ALL     0x00000000
+#define TX4939_CRYPTO_CSR_PDINT_END     0x00000040
+#define TX4939_CRYPTO_CSR_PDINT_NEXT    0x00000080
+#define TX4939_CRYPTO_CSR_PDINT_NONE    0x000000c0
+#define TX4939_CRYPTO_CSR_GINTE 0x00000008
+#define TX4939_CRYPTO_CSR_RSTD  0x00000004
+#define TX4939_CRYPTO_CSR_RSTC  0x00000002
+#define TX4939_CRYPTO_CSR_ENCR  0x00000001
+
+/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
+#define TX4939_CRYPTO_CTX_ENGINE_MASK   0x00000003
+#define TX4939_CRYPTO_CTX_ENGINE_DES    0x00000000
+#define TX4939_CRYPTO_CTX_ENGINE_AES    0x00000001
+#define TX4939_CRYPTO_CTX_ENGINE_MD5    0x00000002
+#define TX4939_CRYPTO_CTX_ENGINE_SHA1   0x00000003
+#define TX4939_CRYPTO_CTX_TDMS  0x00000010
+#define TX4939_CRYPTO_CTX_CMS   0x00000020
+#define TX4939_CRYPTO_CTX_DMS   0x00000040
+#define TX4939_CRYPTO_CTX_UPDATE        0x00000080
+
+/* bits for tx4939_crypto_desc.ctrl */
+#define TX4939_CRYPTO_DESC_OB_CNT_MASK  0xffe00000
+#define TX4939_CRYPTO_DESC_OB_CNT(cnt)  ((cnt) << 21)
+#define TX4939_CRYPTO_DESC_IB_CNT_MASK  0x001ffc00
+#define TX4939_CRYPTO_DESC_IB_CNT(cnt)  ((cnt) << 10)
+#define TX4939_CRYPTO_DESC_START        0x00000200
+#define TX4939_CRYPTO_DESC_END  0x00000100
+#define TX4939_CRYPTO_DESC_XOR  0x00000010
+#define TX4939_CRYPTO_DESC_LAST 0x00000008
+#define TX4939_CRYPTO_DESC_ERR_MASK     0x00000006
+#define TX4939_CRYPTO_DESC_ERR_NONE     0x00000000
+#define TX4939_CRYPTO_DESC_ERR_TOUT     0x00000002
+#define TX4939_CRYPTO_DESC_ERR_DIGEST   0x00000004
+#define TX4939_CRYPTO_DESC_OWN  0x00000001
+
+/* bits for tx4939_crypto_desc.index */
+#define TX4939_CRYPTO_DESC_HASH_IDX_MASK        0x00000070
+#define TX4939_CRYPTO_DESC_HASH_IDX(idx)        ((idx) << 4)
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK     0x00000007
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx)     ((idx) << 0)
+
+#define TX4939_CRYPTO_NR_SET    6
+
+#define TX4939_CRYPTO_RCSR_INTE 0x00000008
+#define TX4939_CRYPTO_RCSR_RST  0x00000004
+#define TX4939_CRYPTO_RCSR_FIN  0x00000002
+#define TX4939_CRYPTO_RCSR_ST   0x00000001
+
+/*
+ * VPC
+ */
+#define TX4939_VPC_CSR_GBINT    0x00010000
+#define TX4939_VPC_CSR_SWAPO    0x00000020
+#define TX4939_VPC_CSR_SWAPI    0x00000010
+#define TX4939_VPC_CSR_GINTE    0x00000008
+#define TX4939_VPC_CSR_RSTD     0x00000004
+#define TX4939_VPC_CSR_RSTVPC   0x00000002
+
+#define TX4939_VPC_CTRLA_VDPSN  0x00000200
+#define TX4939_VPC_CTRLA_PBUSY  0x00000100
+#define TX4939_VPC_CTRLA_DCINT  0x00000080
+#define TX4939_VPC_CTRLA_UOINT  0x00000040
+#define TX4939_VPC_CTRLA_PDINT_MASK     0x00000030
+#define TX4939_VPC_CTRLA_PDINT_ALL      0x00000000
+#define TX4939_VPC_CTRLA_PDINT_NEXT     0x00000010
+#define TX4939_VPC_CTRLA_PDINT_NONE     0x00000030
+#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
+#define TX4939_VPC_CTRLA_VDMODE 0x00000004
+#define TX4939_VPC_CTRLA_VDFOR  0x00000002
+#define TX4939_VPC_CTRLA_ENVPC  0x00000001
+
+/* bits for tx4939_vpc_desc.ctrl1 */
+#define TX4939_VPC_DESC_CTRL1_ERR_MASK  0x00000006
+#define TX4939_VPC_DESC_CTRL1_OWN       0x00000001
+
+#define tx4939_ddrcptr  ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
+#define tx4939_ebuscptr         tx4938_ebuscptr
+#define tx4939_ircptr \
+                ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
+#define tx4939_pcicptr          tx4938_pcicptr
+#define tx4939_pcic1ptr         tx4938_pcic1ptr
+#define tx4939_ccfgptr \
+                ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
+#define tx4939_sramcptr         tx4938_sramcptr
+#define tx4939_cryptoptr \
+                ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
+#define tx4939_vpcptr   ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
+
+#define TX4939_REV_MAJ_MIN()    \
+        ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
+#define TX4939_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
+#define TX4939_CCFG_BCFG()      \
+        ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
+                 >> 32))
+
+#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
+#define tx4939_ccfg_set(bits)   tx4938_ccfg_set(bits)
+#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
+
+#define TX4939_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
+#define TX4939_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
+#define TX4939_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
+#define TX4939_EBUSC_WIDTH(ch)  \
+        (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
+
+/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2  (14.745MHz for MST 20MHz) */
+#define TX4939_SCLK0(mst)       \
+        ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
+
+void tx4939_wdt_init(void);
+void tx4939_setup(void);
+void tx4939_time_init(unsigned int tmrnr);
+void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
+void tx4939_spi_init(int busid);
+void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
+int tx4939_report_pciclk(void);
+void tx4939_report_pci1clk(void);
+struct pci_dev;
+int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+void tx4939_setup_pcierr_irq(void);
+void tx4939_irq_init(void);
+int tx4939_irq(void);
+void tx4939_mtd_init(int ch);
+void tx4939_ata_init(void);
+void tx4939_rtc_init(void);
+void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
+                       unsigned char ch_mask, unsigned char wide_mask);
+void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
+void tx4939_aclc_init(void);
+void tx4939_sramc_init(void);
+void tx4939_rng_init(void);
+
+#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/include/asm/txx9irq.h b/arch/mips/include/asm/txx9irq.h
new file mode 100644
index 000000000..68a6650a4
--- /dev/null
+++ b/arch/mips/include/asm/txx9irq.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-mips/txx9irq.h
+ * TX39/TX49 interrupt controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9IRQ_H
+#define __ASM_TXX9IRQ_H
+
+#include <irq.h>
+
+#ifdef CONFIG_IRQ_MIPS_CPU
+#define TXX9_IRQ_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#else
+#ifdef CONFIG_I8259
+#define TXX9_IRQ_BASE   (I8259A_IRQ_BASE + 16)
+#else
+#define TXX9_IRQ_BASE   0
+#endif
+#endif
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXx9_MAX_IR 16
+#else
+#define TXx9_MAX_IR 32
+#endif
+
+void txx9_irq_init(unsigned long baseaddr);
+int txx9_irq(void);
+int txx9_irq_set_pri(int irc_irq, int new_pri);
+
+#endif /* __ASM_TXX9IRQ_H */
diff --git a/arch/mips/include/asm/txx9pio.h b/arch/mips/include/asm/txx9pio.h
new file mode 100644
index 000000000..3d6fa9f8d
--- /dev/null
+++ b/arch/mips/include/asm/txx9pio.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-mips/txx9pio.h
+ * TX39/TX49 PIO controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9PIO_H
+#define __ASM_TXX9PIO_H
+
+#include <linux/types.h>
+
+struct txx9_pio_reg {
+        __u32 dout;
+        __u32 din;
+        __u32 dir;
+        __u32 od;
+        __u32 flag[2];
+        __u32 pol;
+        __u32 intc;
+        __u32 maskcpu;
+        __u32 maskext;
+};
+
+int txx9_gpio_init(unsigned long baseaddr,
+                   unsigned int base, unsigned int num);
+
+#endif /* __ASM_TXX9PIO_H */
diff --git a/arch/mips/include/asm/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h
new file mode 100644
index 000000000..466a3def3
--- /dev/null
+++ b/arch/mips/include/asm/txx9tmr.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-mips/txx9tmr.h
+ * TX39/TX49 timer controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9TMR_H
+#define __ASM_TXX9TMR_H
+
+#include <linux/types.h>
+
+struct txx9_tmr_reg {
+        u32 tcr;
+        u32 tisr;
+        u32 cpra;
+        u32 cprb;
+        u32 itmr;
+        u32 unused0[3];
+        u32 ccdr;
+        u32 unused1[3];
+        u32 pgmr;
+        u32 unused2[3];
+        u32 wtmr;
+        u32 unused3[43];
+        u32 trr;
+};
+
+/* TMTCR : Timer Control */
+#define TXx9_TMTCR_TCE          0x00000080
+#define TXx9_TMTCR_CCDE         0x00000040
+#define TXx9_TMTCR_CRE          0x00000020
+#define TXx9_TMTCR_ECES         0x00000008
+#define TXx9_TMTCR_CCS          0x00000004
+#define TXx9_TMTCR_TMODE_MASK   0x00000003
+#define TXx9_TMTCR_TMODE_ITVL   0x00000000
+#define TXx9_TMTCR_TMODE_PGEN   0x00000001
+#define TXx9_TMTCR_TMODE_WDOG   0x00000002
+
+/* TMTISR : Timer Int. Status */
+#define TXx9_TMTISR_TPIBS       0x00000004
+#define TXx9_TMTISR_TPIAS       0x00000002
+#define TXx9_TMTISR_TIIS        0x00000001
+
+/* TMITMR : Interval Timer Mode */
+#define TXx9_TMITMR_TIIE        0x00008000
+#define TXx9_TMITMR_TZCE        0x00000001
+
+/* TMWTMR : Watchdog Timer Mode */
+#define TXx9_TMWTMR_TWIE        0x00008000
+#define TXx9_TMWTMR_WDIS        0x00000080
+#define TXx9_TMWTMR_TWC         0x00000001
+
+void txx9_clocksource_init(unsigned long baseaddr,
+                           unsigned int imbusclk);
+void txx9_clockevent_init(unsigned long baseaddr, int irq,
+                          unsigned int imbusclk);
+void txx9_tmr_init(unsigned long baseaddr);
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXX9_TIMER_BITS 24
+#else
+#define TXX9_TIMER_BITS 32
+#endif
+
+#endif /* __ASM_TXX9TMR_H */
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
new file mode 100644
index 000000000..148d42a17
--- /dev/null
+++ b/arch/mips/include/asm/types.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 2008 Wind River Systems,
+ *   written by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+#include <uapi/asm/types.h>
+
+#endif /* _ASM_TYPES_H */
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
new file mode 100644
index 000000000..61fc01f17
--- /dev/null
+++ b/arch/mips/include/asm/uaccess.h
@@ -0,0 +1,791 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ * Copyright (C) 2014, Imagination Technologies Ltd.
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <asm/asm-eva.h>
+#include <asm/extable.h>
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+#ifdef CONFIG_32BIT
+
+#ifdef CONFIG_KVM_GUEST
+#define __UA_LIMIT 0x40000000UL
+#else
+#define __UA_LIMIT 0x80000000UL
+#endif
+
+#define __UA_ADDR       ".word"
+#define __UA_LA         "la"
+#define __UA_ADDU       "addu"
+#define __UA_t0         "$8"
+#define __UA_t1         "$9"
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+extern u64 __ua_limit;
+
+#define __UA_LIMIT      __ua_limit
+
+#define __UA_ADDR       ".dword"
+#define __UA_LA         "dla"
+#define __UA_ADDU       "daddu"
+#define __UA_t0         "$12"
+#define __UA_t1         "$13"
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * USER_DS is a bitmask that has the bits set that may not be set in a valid
+ * userspace address.  Note that we limit 32-bit userspace to 0x7fff8000 but
+ * the arithmetic we're doing only works if the limit is a power of two, so
+ * we use 0x80000000 here on 32-bit kernels.  If a process passes an invalid
+ * address in this range it's the process's problem, not ours :-)
+ */
+
+#ifdef CONFIG_KVM_GUEST
+#define KERNEL_DS       ((mm_segment_t) { 0x80000000UL })
+#define USER_DS         ((mm_segment_t) { 0xC0000000UL })
+#else
+#define KERNEL_DS       ((mm_segment_t) { 0UL })
+#define USER_DS         ((mm_segment_t) { __UA_LIMIT })
+#endif
+
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#define uaccess_kernel()        (get_fs().seg == KERNEL_DS.seg)
+
+/*
+ * eva_kernel_access() - determine whether kernel memory access on an EVA system
+ *
+ * Determines whether memory accesses should be performed to kernel memory
+ * on a system using Extended Virtual Addressing (EVA).
+ *
+ * Return: true if a kernel memory access on an EVA system, else false.
+ */
+static inline bool eva_kernel_access(void)
+{
+        if (!IS_ENABLED(CONFIG_EVA))
+                return false;
+
+        return uaccess_kernel();
+}
+
+/*
+ * Is a address valid? This does a straightforward calculation rather
+ * than tests.
+ *
+ * Address valid if:
+ *  - "addr" doesn't have any high-bits set
+ *  - AND "size" doesn't have any high-bits set
+ *  - AND "addr+size" doesn't have any high-bits set
+ *  - OR we are in kernel mode.
+ *
+ * __ua_size() is a trick to avoid runtime checking of positive constant
+ * sizes; for those we already know at compile time that the size is ok.
+ */
+#define __ua_size(size)                                                 \
+        ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size))
+
+/*
+ * access_ok: - Checks if a user space pointer is valid
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns true (nonzero) if the memory block may be valid, false (zero)
+ * if it is definitely invalid.
+ *
+ * Note that, depending on architecture, this function probably just
+ * checks that the pointer is in the user space range - after calling
+ * this function, memory access functions may still return -EFAULT.
+ */
+
+static inline int __access_ok(const void __user *p, unsigned long size)
+{
+        unsigned long addr = (unsigned long)p;
+        return (get_fs().seg & (addr | (addr + size) | __ua_size(size))) == 0;
+}
+
+#define access_ok(addr, size)                                   \
+        likely(__access_ok((addr), (size)))
+
+/*
+ * put_user: - Write a simple value into user space.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user(x,ptr) \
+        __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * get_user: - Get a simple variable from user space.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define get_user(x,ptr) \
+        __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * __put_user: - Write a simple value into user space, with less checking.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define __put_user(x,ptr) \
+        __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * __get_user: - Get a simple variable from user space, with less checking.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define __get_user(x,ptr) \
+        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct __user *)(x))
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifndef CONFIG_EVA
+#define __get_kernel_common(val, size, ptr) __get_user_common(val, size, ptr)
+#else
+/*
+ * Kernel specific functions for EVA. We need to use normal load instructions
+ * to read data from kernel when operating in EVA mode. We use these macros to
+ * avoid redefining __get_user_asm for EVA.
+ */
+#undef _loadd
+#undef _loadw
+#undef _loadh
+#undef _loadb
+#ifdef CONFIG_32BIT
+#define _loadd                  _loadw
+#else
+#define _loadd(reg, addr)       "ld " reg ", " addr
+#endif
+#define _loadw(reg, addr)       "lw " reg ", " addr
+#define _loadh(reg, addr)       "lh " reg ", " addr
+#define _loadb(reg, addr)       "lb " reg ", " addr
+
+#define __get_kernel_common(val, size, ptr)                             \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __get_data_asm(val, _loadb, ptr); break;                \
+        case 2: __get_data_asm(val, _loadh, ptr); break;                \
+        case 4: __get_data_asm(val, _loadw, ptr); break;                \
+        case 8: __GET_DW(val, _loadd, ptr); break;                      \
+        default: __get_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
+#endif
+
+#ifdef CONFIG_32BIT
+#define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr)
+#endif
+
+extern void __get_user_unknown(void);
+
+#define __get_user_common(val, size, ptr)                               \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __get_data_asm(val, user_lb, ptr); break;               \
+        case 2: __get_data_asm(val, user_lh, ptr); break;               \
+        case 4: __get_data_asm(val, user_lw, ptr); break;               \
+        case 8: __GET_DW(val, user_ld, ptr); break;                     \
+        default: __get_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
+
+#define __get_user_nocheck(x, ptr, size)                                \
+({                                                                      \
+        int __gu_err;                                                   \
+                                                                        \
+        if (eva_kernel_access()) {                                      \
+                __get_kernel_common((x), size, ptr);                    \
+        } else {                                                        \
+                __chk_user_ptr(ptr);                                    \
+                __get_user_common((x), size, ptr);                      \
+        }                                                               \
+        __gu_err;                                                       \
+})
+
+#define __get_user_check(x, ptr, size)                                  \
+({                                                                      \
+        int __gu_err = -EFAULT;                                         \
+        const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);             \
+                                                                        \
+        might_fault();                                                  \
+        if (likely(access_ok( __gu_ptr, size))) {               \
+                if (eva_kernel_access())                                \
+                        __get_kernel_common((x), size, __gu_ptr);       \
+                else                                                    \
+                        __get_user_common((x), size, __gu_ptr);         \
+        } else                                                          \
+                (x) = 0;                                                \
+                                                                        \
+        __gu_err;                                                       \
+})
+
+#define __get_data_asm(val, insn, addr)                                 \
+{                                                                       \
+        long __gu_tmp;                                                  \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     "insn("%1", "%3")"                              \n"     \
+        "2:                                                     \n"     \
+        "       .insn                                           \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       move    %1, $0                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 3b                            \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=r" (__gu_tmp)                              \
+        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
+                                                                        \
+        (val) = (__typeof__(*(addr))) __gu_tmp;                         \
+}
+
+/*
+ * Get a long long 64 using 32 bit registers.
+ */
+#define __get_data_asm_ll32(val, insn, addr)                            \
+{                                                                       \
+        union {                                                         \
+                unsigned long long      l;                              \
+                __typeof__(*(addr))     t;                              \
+        } __gu_tmp;                                                     \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     " insn("%1", "(%3)")"                           \n"     \
+        "2:     " insn("%D1", "4(%3)")"                         \n"     \
+        "3:                                                     \n"     \
+        "       .insn                                           \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       move    %1, $0                                  \n"     \
+        "       move    %D1, $0                                 \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=&r" (__gu_tmp.l)                           \
+        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
+                                                                        \
+        (val) = __gu_tmp.t;                                             \
+}
+
+#ifndef CONFIG_EVA
+#define __put_kernel_common(ptr, size) __put_user_common(ptr, size)
+#else
+/*
+ * Kernel specific functions for EVA. We need to use normal load instructions
+ * to read data from kernel when operating in EVA mode. We use these macros to
+ * avoid redefining __get_data_asm for EVA.
+ */
+#undef _stored
+#undef _storew
+#undef _storeh
+#undef _storeb
+#ifdef CONFIG_32BIT
+#define _stored                 _storew
+#else
+#define _stored(reg, addr)      "ld " reg ", " addr
+#endif
+
+#define _storew(reg, addr)      "sw " reg ", " addr
+#define _storeh(reg, addr)      "sh " reg ", " addr
+#define _storeb(reg, addr)      "sb " reg ", " addr
+
+#define __put_kernel_common(ptr, size)                                  \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __put_data_asm(_storeb, ptr); break;                    \
+        case 2: __put_data_asm(_storeh, ptr); break;                    \
+        case 4: __put_data_asm(_storew, ptr); break;                    \
+        case 8: __PUT_DW(_stored, ptr); break;                          \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+} while(0)
+#endif
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef CONFIG_32BIT
+#define __PUT_DW(insn, ptr) __put_data_asm_ll32(insn, ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __PUT_DW(insn, ptr) __put_data_asm(insn, ptr)
+#endif
+
+#define __put_user_common(ptr, size)                                    \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __put_data_asm(user_sb, ptr); break;                    \
+        case 2: __put_data_asm(user_sh, ptr); break;                    \
+        case 4: __put_data_asm(user_sw, ptr); break;                    \
+        case 8: __PUT_DW(user_sd, ptr); break;                          \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
+
+#define __put_user_nocheck(x, ptr, size)                                \
+({                                                                      \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        int __pu_err = 0;                                               \
+                                                                        \
+        __pu_val = (x);                                                 \
+        if (eva_kernel_access()) {                                      \
+                __put_kernel_common(ptr, size);                         \
+        } else {                                                        \
+                __chk_user_ptr(ptr);                                    \
+                __put_user_common(ptr, size);                           \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_check(x, ptr, size)                                  \
+({                                                                      \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
+        int __pu_err = -EFAULT;                                         \
+                                                                        \
+        might_fault();                                                  \
+        if (likely(access_ok( __pu_addr, size))) {      \
+                if (eva_kernel_access())                                \
+                        __put_kernel_common(__pu_addr, size);           \
+                else                                                    \
+                        __put_user_common(__pu_addr, size);             \
+        }                                                               \
+                                                                        \
+        __pu_err;                                                       \
+})
+
+#define __put_data_asm(insn, ptr)                                       \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     "insn("%z2", "%3")"     # __put_data_asm        \n"     \
+        "2:                                                     \n"     \
+        "       .insn                                           \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 3b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
+          "i" (-EFAULT));                                               \
+}
+
+#define __put_data_asm_ll32(insn, ptr)                                  \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     "insn("%2", "(%3)")"    # __put_data_asm_ll32   \n"     \
+        "2:     "insn("%D2", "4(%3)")"                          \n"     \
+        "3:                                                     \n"     \
+        "       .insn                                           \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous"                                              \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
+          "i" (-EFAULT));                                               \
+}
+
+extern void __put_user_unknown(void);
+
+/*
+ * We're generating jump to subroutines which will be outside the range of
+ * jump instructions
+ */
+#ifdef MODULE
+#define __MODULE_JAL(destination)                                       \
+        ".set\tnoat\n\t"                                                \
+        __UA_LA "\t$1, " #destination "\n\t"                            \
+        "jalr\t$1\n\t"                                                  \
+        ".set\tat\n\t"
+#else
+#define __MODULE_JAL(destination)                                       \
+        "jal\t" #destination "\n\t"
+#endif
+
+#if defined(CONFIG_CPU_DADDI_WORKAROUNDS) || (defined(CONFIG_EVA) &&    \
+                                              defined(CONFIG_CPU_HAS_PREFETCH))
+#define DADDI_SCRATCH "$3"
+#else
+#define DADDI_SCRATCH "$0"
+#endif
+
+extern size_t __copy_user(void *__to, const void *__from, size_t __n);
+
+#define __invoke_copy_from(func, to, from, n)                           \
+({                                                                      \
+        register void *__cu_to_r __asm__("$4");                         \
+        register const void __user *__cu_from_r __asm__("$5");          \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        ".set\tnoreorder\n\t"                                           \
+        __MODULE_JAL(func)                                              \
+        ".set\tnoat\n\t"                                                \
+        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
+        ".set\tat\n\t"                                                  \
+        ".set\treorder"                                                 \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+
+#define __invoke_copy_to(func, to, from, n)                             \
+({                                                                      \
+        register void __user *__cu_to_r __asm__("$4");                  \
+        register const void *__cu_from_r __asm__("$5");                 \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        __MODULE_JAL(func)                                              \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+
+#define __invoke_copy_from_kernel(to, from, n)                          \
+        __invoke_copy_from(__copy_user, to, from, n)
+
+#define __invoke_copy_to_kernel(to, from, n)                            \
+        __invoke_copy_to(__copy_user, to, from, n)
+
+#define ___invoke_copy_in_kernel(to, from, n)                           \
+        __invoke_copy_from(__copy_user, to, from, n)
+
+#ifndef CONFIG_EVA
+#define __invoke_copy_from_user(to, from, n)                            \
+        __invoke_copy_from(__copy_user, to, from, n)
+
+#define __invoke_copy_to_user(to, from, n)                              \
+        __invoke_copy_to(__copy_user, to, from, n)
+
+#define ___invoke_copy_in_user(to, from, n)                             \
+        __invoke_copy_from(__copy_user, to, from, n)
+
+#else
+
+/* EVA specific functions */
+
+extern size_t __copy_from_user_eva(void *__to, const void *__from,
+                                   size_t __n);
+extern size_t __copy_to_user_eva(void *__to, const void *__from,
+                                 size_t __n);
+extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n);
+
+/*
+ * Source or destination address is in userland. We need to go through
+ * the TLB
+ */
+#define __invoke_copy_from_user(to, from, n)                            \
+        __invoke_copy_from(__copy_from_user_eva, to, from, n)
+
+#define __invoke_copy_to_user(to, from, n)                              \
+        __invoke_copy_to(__copy_to_user_eva, to, from, n)
+
+#define ___invoke_copy_in_user(to, from, n)                             \
+        __invoke_copy_from(__copy_in_user_eva, to, from, n)
+
+#endif /* CONFIG_EVA */
+
+static inline unsigned long
+raw_copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        if (eva_kernel_access())
+                return __invoke_copy_to_kernel(to, from, n);
+        else
+                return __invoke_copy_to_user(to, from, n);
+}
+
+static inline unsigned long
+raw_copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        if (eva_kernel_access())
+                return __invoke_copy_from_kernel(to, from, n);
+        else
+                return __invoke_copy_from_user(to, from, n);
+}
+
+#define INLINE_COPY_FROM_USER
+#define INLINE_COPY_TO_USER
+
+static inline unsigned long
+raw_copy_in_user(void __user*to, const void __user *from, unsigned long n)
+{
+        if (eva_kernel_access())
+                return ___invoke_copy_in_kernel(to, from, n);
+        else
+                return ___invoke_copy_in_user(to, from, n);
+}
+
+extern __kernel_size_t __bzero_kernel(void __user *addr, __kernel_size_t size);
+extern __kernel_size_t __bzero(void __user *addr, __kernel_size_t size);
+
+/*
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+static inline __kernel_size_t
+__clear_user(void __user *addr, __kernel_size_t size)
+{
+        __kernel_size_t res;
+
+#ifdef CONFIG_CPU_MICROMIPS
+/* micromips memset / bzero also clobbers t7 & t8 */
+#define bzero_clobbers "$4", "$5", "$6", __UA_t0, __UA_t1, "$15", "$24", "$31"
+#else
+#define bzero_clobbers "$4", "$5", "$6", __UA_t0, __UA_t1, "$31"
+#endif /* CONFIG_CPU_MICROMIPS */
+
+        if (eva_kernel_access()) {
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, $0\n\t"
+                        "move\t$6, %2\n\t"
+                        __MODULE_JAL(__bzero_kernel)
+                        "move\t%0, $6"
+                        : "=r" (res)
+                        : "r" (addr), "r" (size)
+                        : bzero_clobbers);
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, $0\n\t"
+                        "move\t$6, %2\n\t"
+                        __MODULE_JAL(__bzero)
+                        "move\t%0, $6"
+                        : "=r" (res)
+                        : "r" (addr), "r" (size)
+                        : bzero_clobbers);
+        }
+
+        return res;
+}
+
+#define clear_user(addr,n)                                              \
+({                                                                      \
+        void __user * __cl_addr = (addr);                               \
+        unsigned long __cl_size = (n);                                  \
+        if (__cl_size && access_ok(__cl_addr, __cl_size))               \
+                __cl_size = __clear_user(__cl_addr, __cl_size);         \
+        __cl_size;                                                      \
+})
+
+extern long __strncpy_from_kernel_asm(char *__to, const char __user *__from, long __len);
+extern long __strncpy_from_user_asm(char *__to, const char __user *__from, long __len);
+
+/*
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+static inline long
+strncpy_from_user(char *__to, const char __user *__from, long __len)
+{
+        long res;
+
+        if (eva_kernel_access()) {
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        "move\t$6, %3\n\t"
+                        __MODULE_JAL(__strncpy_from_kernel_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (__to), "r" (__from), "r" (__len)
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        "move\t$6, %3\n\t"
+                        __MODULE_JAL(__strncpy_from_user_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (__to), "r" (__from), "r" (__len)
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        }
+
+        return res;
+}
+
+extern long __strnlen_kernel_asm(const char __user *s, long n);
+extern long __strnlen_user_asm(const char __user *s, long n);
+
+/*
+ * strnlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only. This function may sleep if pagefaults are
+ *          enabled.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ * If the string is too long, returns a value greater than @n.
+ */
+static inline long strnlen_user(const char __user *s, long n)
+{
+        long res;
+
+        might_fault();
+        if (eva_kernel_access()) {
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        __MODULE_JAL(__strnlen_kernel_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s), "r" (n)
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        } else {
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        __MODULE_JAL(__strnlen_user_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s), "r" (n)
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        }
+
+        return res;
+}
+
+#endif /* _ASM_UACCESS_H */
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
new file mode 100644
index 000000000..f7effca79
--- /dev/null
+++ b/arch/mips/include/asm/uasm.h
@@ -0,0 +1,325 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
+ * Copyright (C) 2005  Maciej W. Rozycki
+ * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
+ */
+
+#ifndef __ASM_UASM_H
+#define __ASM_UASM_H
+
+#include <linux/types.h>
+
+#ifdef CONFIG_EXPORT_UASM
+#include <linux/export.h>
+#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
+#else
+#define UASM_EXPORT_SYMBOL(sym)
+#endif
+
+#define Ip_u1u2u3(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+
+#define Ip_u2u1u3(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+
+#define Ip_u3u2u1(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+
+#define Ip_u3u1u2(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
+
+#define Ip_u1u2s3(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
+
+#define Ip_u2s3u1(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
+
+#define Ip_s3s1s2(op)                                                   \
+void uasm_i##op(u32 **buf, int a, int b, int c)
+
+#define Ip_u2u1s3(op)                                                   \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
+
+#define Ip_u2u1msbu3(op)                                                \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
+           unsigned int d)
+
+#define Ip_u1u2(op)                                                     \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+
+#define Ip_u2u1(op)                                                     \
+void uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+
+#define Ip_u1s2(op)                                                     \
+void uasm_i##op(u32 **buf, unsigned int a, signed int b)
+
+#define Ip_u1(op) void uasm_i##op(u32 **buf, unsigned int a)
+
+#define Ip_0(op) void uasm_i##op(u32 **buf)
+
+Ip_u2u1s3(_addiu);
+Ip_u3u1u2(_addu);
+Ip_u3u1u2(_and);
+Ip_u2u1u3(_andi);
+Ip_u1u2s3(_bbit0);
+Ip_u1u2s3(_bbit1);
+Ip_u1u2s3(_beq);
+Ip_u1u2s3(_beql);
+Ip_u1s2(_bgez);
+Ip_u1s2(_bgezl);
+Ip_u1s2(_bgtz);
+Ip_u1s2(_blez);
+Ip_u1s2(_bltz);
+Ip_u1s2(_bltzl);
+Ip_u1u2s3(_bne);
+Ip_u1(_break);
+Ip_u2s3u1(_cache);
+Ip_u1u2(_cfc1);
+Ip_u2u1(_cfcmsa);
+Ip_u1u2(_ctc1);
+Ip_u2u1(_ctcmsa);
+Ip_u2u1s3(_daddiu);
+Ip_u3u1u2(_daddu);
+Ip_u1u2(_ddivu);
+Ip_u3u1u2(_ddivu_r6);
+Ip_u1(_di);
+Ip_u2u1msbu3(_dins);
+Ip_u2u1msbu3(_dinsm);
+Ip_u2u1msbu3(_dinsu);
+Ip_u1u2(_divu);
+Ip_u3u1u2(_divu_r6);
+Ip_u1u2u3(_dmfc0);
+Ip_u3u1u2(_dmodu);
+Ip_u1u2u3(_dmtc0);
+Ip_u1u2(_dmultu);
+Ip_u3u1u2(_dmulu);
+Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
+Ip_u2u1(_dsbh);
+Ip_u2u1(_dshd);
+Ip_u2u1u3(_dsll);
+Ip_u2u1u3(_dsll32);
+Ip_u3u2u1(_dsllv);
+Ip_u2u1u3(_dsra);
+Ip_u2u1u3(_dsra32);
+Ip_u3u2u1(_dsrav);
+Ip_u2u1u3(_dsrl);
+Ip_u2u1u3(_dsrl32);
+Ip_u3u2u1(_dsrlv);
+Ip_u3u1u2(_dsubu);
+Ip_0(_eret);
+Ip_u2u1msbu3(_ext);
+Ip_u2u1msbu3(_ins);
+Ip_u1(_j);
+Ip_u1(_jal);
+Ip_u2u1(_jalr);
+Ip_u1(_jr);
+Ip_u2s3u1(_lb);
+Ip_u2s3u1(_lbu);
+Ip_u2s3u1(_ld);
+Ip_u3u1u2(_ldx);
+Ip_u2s3u1(_lh);
+Ip_u2s3u1(_lhu);
+Ip_u2s3u1(_ll);
+Ip_u2s3u1(_lld);
+Ip_u1s2(_lui);
+Ip_u2s3u1(_lw);
+Ip_u2s3u1(_lwu);
+Ip_u3u1u2(_lwx);
+Ip_u1u2u3(_mfc0);
+Ip_u1u2u3(_mfhc0);
+Ip_u1(_mfhi);
+Ip_u1(_mflo);
+Ip_u3u1u2(_modu);
+Ip_u3u1u2(_movn);
+Ip_u3u1u2(_movz);
+Ip_u1u2u3(_mtc0);
+Ip_u1u2u3(_mthc0);
+Ip_u1(_mthi);
+Ip_u1(_mtlo);
+Ip_u3u1u2(_mul);
+Ip_u1u2(_multu);
+Ip_u3u1u2(_mulu);
+Ip_u3u1u2(_nor);
+Ip_u3u1u2(_or);
+Ip_u2u1u3(_ori);
+Ip_u2s3u1(_pref);
+Ip_0(_rfe);
+Ip_u2u1u3(_rotr);
+Ip_u2s3u1(_sb);
+Ip_u2s3u1(_sc);
+Ip_u2s3u1(_scd);
+Ip_u2s3u1(_sd);
+Ip_u3u1u2(_seleqz);
+Ip_u3u1u2(_selnez);
+Ip_u2s3u1(_sh);
+Ip_u2u1u3(_sll);
+Ip_u3u2u1(_sllv);
+Ip_s3s1s2(_slt);
+Ip_u2u1s3(_slti);
+Ip_u2u1s3(_sltiu);
+Ip_u3u1u2(_sltu);
+Ip_u2u1u3(_sra);
+Ip_u3u2u1(_srav);
+Ip_u2u1u3(_srl);
+Ip_u3u2u1(_srlv);
+Ip_u3u1u2(_subu);
+Ip_u2s3u1(_sw);
+Ip_u1(_sync);
+Ip_u1(_syscall);
+Ip_0(_tlbp);
+Ip_0(_tlbr);
+Ip_0(_tlbwi);
+Ip_0(_tlbwr);
+Ip_u1(_wait);
+Ip_u2u1(_wsbh);
+Ip_u3u1u2(_xor);
+Ip_u2u1u3(_xori);
+Ip_u2u1(_yield);
+Ip_u1u2(_ldpte);
+Ip_u2u1u3(_lddir);
+
+/* Handle labels. */
+struct uasm_label {
+        u32 *addr;
+        int lab;
+};
+
+void uasm_build_label(struct uasm_label **lab, u32 *addr,
+                        int lid);
+#ifdef CONFIG_64BIT
+int uasm_in_compat_space_p(long addr);
+#endif
+int uasm_rel_hi(long val);
+int uasm_rel_lo(long val);
+void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
+void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
+
+#define UASM_L_LA(lb)                                                   \
+static inline void uasm_l##lb(struct uasm_label **lab, u32 *addr)       \
+{                                                                       \
+        uasm_build_label(lab, addr, label##lb);                         \
+}
+
+/* convenience macros for instructions */
+#ifdef CONFIG_64BIT
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
+# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
+# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
+# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
+# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
+# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
+# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
+#else
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
+# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
+# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
+# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
+# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
+# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
+# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
+#endif
+
+#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
+#define uasm_i_beqz(buf, rs, off) uasm_i_beq(buf, rs, 0, off)
+#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
+#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
+#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
+#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
+#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
+#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
+#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
+
+static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
+                                     unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_drotr(p, a1, a2, a3);
+        else
+                uasm_i_drotr32(p, a1, a2, a3 - 32);
+}
+
+static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsll(p, a1, a2, a3);
+        else
+                uasm_i_dsll32(p, a1, a2, a3 - 32);
+}
+
+static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsrl(p, a1, a2, a3);
+        else
+                uasm_i_dsrl32(p, a1, a2, a3 - 32);
+}
+
+static inline void uasm_i_dsra_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsra(p, a1, a2, a3);
+        else
+                uasm_i_dsra32(p, a1, a2, a3 - 32);
+}
+
+/* Handle relocations. */
+struct uasm_reloc {
+        u32 *addr;
+        unsigned int type;
+        int lab;
+};
+
+/* This is zero so we can use zeroed label arrays. */
+#define UASM_LABEL_INVALID 0
+
+void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid);
+void uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
+void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off);
+void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off);
+void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
+        u32 *first, u32 *end, u32 *target);
+int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
+
+/* Convenience functions for labeled branches. */
+void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
+                 unsigned int r2, int lid);
+void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
+                 unsigned int reg2, int lid);
+void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+
+#endif /* __ASM_UASM_H */
diff --git a/arch/mips/include/asm/unaligned-emul.h b/arch/mips/include/asm/unaligned-emul.h
new file mode 100644
index 000000000..2022b1894
--- /dev/null
+++ b/arch/mips/include/asm/unaligned-emul.h
@@ -0,0 +1,779 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef _ASM_MIPS_UNALIGNED_EMUL_H
+#define _ASM_MIPS_UNALIGNED_EMUL_H
+
+#include <asm/asm.h>
+
+#ifdef __BIG_ENDIAN
+#define  _LoadHW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (".set\tnoat\n"        \
+                "1:\t"type##_lb("%0", "0(%2)")"\n"  \
+                "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                "3:\t.set\tat\n\t"                  \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadW(addr, value, res, type)   \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_lwl("%0", "(%2)")"\n"   \
+                "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl instruction */
+#define  _LoadW(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n"                      \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_lb("%0", "0(%2)")"\n\t"  \
+                "2:"type##_lbu("$1", "1(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "3:"type##_lbu("$1", "2(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "4:"type##_lbu("$1", "3(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#define  _LoadHWU(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tnoat\n"                      \
+                "1:\t"type##_lbu("%0", "0(%2)")"\n" \
+                "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".set\tat\n\t"                      \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadWU(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_lwl("%0", "(%2)")"\n"  \
+                "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
+                "dsll\t%0, %0, 32\n\t"              \
+                "dsrl\t%0, %0, 32\n\t"              \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                "\t.section\t.fixup,\"ax\"\n\t"     \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\tldl\t%0, (%2)\n"               \
+                "2:\tldr\t%0, 7(%2)\n\t"            \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                "\t.section\t.fixup,\"ax\"\n\t"     \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl and ldl instructions */
+#define  _LoadWU(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_lbu("%0", "0(%2)")"\n\t" \
+                "2:"type##_lbu("$1", "1(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "3:"type##_lbu("$1", "2(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "4:"type##_lbu("$1", "3(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:lb\t%0, 0(%2)\n\t"               \
+                "2:lbu\t $1, 1(%2)\n\t"             \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "3:lbu\t$1, 2(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "4:lbu\t$1, 3(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "5:lbu\t$1, 4(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "6:lbu\t$1, 5(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "7:lbu\t$1, 6(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "8:lbu\t$1, 7(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n\t"                     \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                STR(PTR)"\t5b, 11b\n\t"             \
+                STR(PTR)"\t6b, 11b\n\t"             \
+                STR(PTR)"\t7b, 11b\n\t"             \
+                STR(PTR)"\t8b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+
+#define  _StoreHW(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tnoat\n"                      \
+                "1:\t"type##_sb("%1", "1(%2)")"\n"  \
+                "srl\t$1, %1, 0x8\n"                \
+                "2:\t"type##_sb("$1", "0(%2)")"\n"  \
+                ".set\tat\n\t"                      \
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"              \
+                STR(PTR)"\t2b, 4b\n\t"              \
+                ".previous"                         \
+                : "=r" (res)                        \
+                : "r" (value), "r" (addr), "i" (-EFAULT));\
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_swl("%1", "(%2)")"\n"  \
+                "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=r" (res)                                \
+                : "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\tsdl\t%1,(%2)\n"                \
+                "2:\tsdr\t%1, 7(%2)\n\t"            \
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=r" (res)                                \
+                : "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_sb("%1", "3(%2)")"\n\t"  \
+                "srl\t$1, %1, 0x8\n\t"              \
+                "2:"type##_sb("$1", "2(%2)")"\n\t"  \
+                "srl\t$1, $1,  0x8\n\t"             \
+                "3:"type##_sb("$1", "1(%2)")"\n\t"  \
+                "srl\t$1, $1, 0x8\n\t"              \
+                "4:"type##_sb("$1", "0(%2)")"\n\t"  \
+                ".set\tpop\n\t"                     \
+                "li\t%0, 0\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%0, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (res)                               \
+                : "r" (value), "r" (addr), "i" (-EFAULT)    \
+                : "memory");                                \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:sb\t%1, 7(%2)\n\t"               \
+                "dsrl\t$1, %1, 0x8\n\t"             \
+                "2:sb\t$1, 6(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "3:sb\t$1, 5(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "4:sb\t$1, 4(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "5:sb\t$1, 3(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "6:sb\t$1, 2(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "7:sb\t$1, 1(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "8:sb\t$1, 0(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                ".set\tpop\n\t"                     \
+                "li\t%0, 0\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%0, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                STR(PTR)"\t5b, 11b\n\t"             \
+                STR(PTR)"\t6b, 11b\n\t"             \
+                STR(PTR)"\t7b, 11b\n\t"             \
+                STR(PTR)"\t8b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (res)                               \
+                : "r" (value), "r" (addr), "i" (-EFAULT)    \
+                : "memory");                                \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#else /* __BIG_ENDIAN */
+
+#define  _LoadHW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (".set\tnoat\n"        \
+                "1:\t"type##_lb("%0", "1(%2)")"\n"  \
+                "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                "3:\t.set\tat\n\t"                  \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadW(addr, value, res, type)   \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_lwl("%0", "3(%2)")"\n" \
+                "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl instruction */
+#define  _LoadW(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n"                      \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_lb("%0", "3(%2)")"\n\t"  \
+                "2:"type##_lbu("$1", "2(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "3:"type##_lbu("$1", "1(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "4:"type##_lbu("$1", "0(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+
+#define  _LoadHWU(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tnoat\n"                      \
+                "1:\t"type##_lbu("%0", "1(%2)")"\n" \
+                "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".set\tat\n\t"                      \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadWU(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_lwl("%0", "3(%2)")"\n" \
+                "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
+                "dsll\t%0, %0, 32\n\t"              \
+                "dsrl\t%0, %0, 32\n\t"              \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                "\t.section\t.fixup,\"ax\"\n\t"     \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\tldl\t%0, 7(%2)\n"              \
+                "2:\tldr\t%0, (%2)\n\t"             \
+                "li\t%1, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                "\t.section\t.fixup,\"ax\"\n\t"     \
+                "4:\tli\t%1, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl and ldl instructions */
+#define  _LoadWU(addr, value, res, type) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_lbu("%0", "3(%2)")"\n\t" \
+                "2:"type##_lbu("$1", "2(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "3:"type##_lbu("$1", "1(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "4:"type##_lbu("$1", "0(%2)")"\n\t" \
+                "sll\t%0, 0x8\n\t"                  \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:lb\t%0, 7(%2)\n\t"               \
+                "2:lbu\t$1, 6(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "3:lbu\t$1, 5(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "4:lbu\t$1, 4(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "5:lbu\t$1, 3(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "6:lbu\t$1, 2(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "7:lbu\t$1, 1(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "8:lbu\t$1, 0(%2)\n\t"              \
+                "dsll\t%0, 0x8\n\t"                 \
+                "or\t%0, $1\n\t"                    \
+                "li\t%1, 0\n"                       \
+                ".set\tpop\n\t"                     \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%1, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                STR(PTR)"\t5b, 11b\n\t"             \
+                STR(PTR)"\t6b, 11b\n\t"             \
+                STR(PTR)"\t7b, 11b\n\t"             \
+                STR(PTR)"\t8b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (value), "=r" (res)         \
+                : "r" (addr), "i" (-EFAULT));       \
+} while (0)
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#define  _StoreHW(addr, value, res, type) \
+do {                                                 \
+        __asm__ __volatile__ (                      \
+                ".set\tnoat\n"                      \
+                "1:\t"type##_sb("%1", "0(%2)")"\n"  \
+                "srl\t$1,%1, 0x8\n"                 \
+                "2:\t"type##_sb("$1", "1(%2)")"\n"  \
+                ".set\tat\n\t"                      \
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=r" (res)                        \
+                : "r" (value), "r" (addr), "i" (-EFAULT));\
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\t"type##_swl("%1", "3(%2)")"\n" \
+                "2:\t"type##_swr("%1", "(%2)")"\n\t"\
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=r" (res)                                \
+                : "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                "1:\tsdl\t%1, 7(%2)\n"              \
+                "2:\tsdr\t%1, (%2)\n\t"             \
+                "li\t%0, 0\n"                       \
+                "3:\n\t"                            \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "4:\tli\t%0, %3\n\t"                \
+                "j\t3b\n\t"                         \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 4b\n\t"               \
+                STR(PTR)"\t2b, 4b\n\t"               \
+                ".previous"                         \
+                : "=r" (res)                                \
+                : "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without swl and sdl instructions */
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:"type##_sb("%1", "0(%2)")"\n\t"  \
+                "srl\t$1, %1, 0x8\n\t"              \
+                "2:"type##_sb("$1", "1(%2)")"\n\t"  \
+                "srl\t$1, $1,  0x8\n\t"             \
+                "3:"type##_sb("$1", "2(%2)")"\n\t"  \
+                "srl\t$1, $1, 0x8\n\t"              \
+                "4:"type##_sb("$1", "3(%2)")"\n\t"  \
+                ".set\tpop\n\t"                     \
+                "li\t%0, 0\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%0, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (res)                               \
+                : "r" (value), "r" (addr), "i" (-EFAULT)    \
+                : "memory");                                \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+        __asm__ __volatile__ (                      \
+                ".set\tpush\n\t"                    \
+                ".set\tnoat\n\t"                    \
+                "1:sb\t%1, 0(%2)\n\t"               \
+                "dsrl\t$1, %1, 0x8\n\t"             \
+                "2:sb\t$1, 1(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "3:sb\t$1, 2(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "4:sb\t$1, 3(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "5:sb\t$1, 4(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "6:sb\t$1, 5(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "7:sb\t$1, 6(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                "8:sb\t$1, 7(%2)\n\t"               \
+                "dsrl\t$1, $1, 0x8\n\t"             \
+                ".set\tpop\n\t"                     \
+                "li\t%0, 0\n"                       \
+                "10:\n\t"                           \
+                ".insn\n\t"                         \
+                ".section\t.fixup,\"ax\"\n\t"       \
+                "11:\tli\t%0, %3\n\t"               \
+                "j\t10b\n\t"                        \
+                ".previous\n\t"                     \
+                ".section\t__ex_table,\"a\"\n\t"    \
+                STR(PTR)"\t1b, 11b\n\t"             \
+                STR(PTR)"\t2b, 11b\n\t"             \
+                STR(PTR)"\t3b, 11b\n\t"             \
+                STR(PTR)"\t4b, 11b\n\t"             \
+                STR(PTR)"\t5b, 11b\n\t"             \
+                STR(PTR)"\t6b, 11b\n\t"             \
+                STR(PTR)"\t7b, 11b\n\t"             \
+                STR(PTR)"\t8b, 11b\n\t"             \
+                ".previous"                         \
+                : "=&r" (res)                               \
+                : "r" (value), "r" (addr), "i" (-EFAULT)    \
+                : "memory");                                \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+#endif
+
+#define LoadHWU(addr, value, res)       _LoadHWU(addr, value, res, kernel)
+#define LoadHWUE(addr, value, res)      _LoadHWU(addr, value, res, user)
+#define LoadWU(addr, value, res)        _LoadWU(addr, value, res, kernel)
+#define LoadWUE(addr, value, res)       _LoadWU(addr, value, res, user)
+#define LoadHW(addr, value, res)        _LoadHW(addr, value, res, kernel)
+#define LoadHWE(addr, value, res)       _LoadHW(addr, value, res, user)
+#define LoadW(addr, value, res)         _LoadW(addr, value, res, kernel)
+#define LoadWE(addr, value, res)        _LoadW(addr, value, res, user)
+#define LoadDW(addr, value, res)        _LoadDW(addr, value, res)
+
+#define StoreHW(addr, value, res)       _StoreHW(addr, value, res, kernel)
+#define StoreHWE(addr, value, res)      _StoreHW(addr, value, res, user)
+#define StoreW(addr, value, res)        _StoreW(addr, value, res, kernel)
+#define StoreWE(addr, value, res)       _StoreW(addr, value, res, user)
+#define StoreDW(addr, value, res)       _StoreDW(addr, value, res)
+
+#endif /* _ASM_MIPS_UNALIGNED_EMUL_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
new file mode 100644
index 000000000..5d70babfc
--- /dev/null
+++ b/arch/mips/include/asm/unistd.h
@@ -0,0 +1,62 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
+ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
+ */
+#ifndef _ASM_UNISTD_H
+#define _ASM_UNISTD_H
+
+#include <uapi/asm/unistd.h>
+#include <asm/unistd_nr_n32.h>
+#include <asm/unistd_nr_n64.h>
+#include <asm/unistd_nr_o32.h>
+
+#ifdef CONFIG_MIPS32_N32
+#define NR_syscalls  (__NR_N32_Linux + __NR_N32_Linux_syscalls)
+#elif defined(CONFIG_64BIT)
+#define NR_syscalls  (__NR_64_Linux + __NR_64_Linux_syscalls)
+#else
+#define NR_syscalls  (__NR_O32_Linux + __NR_O32_Linux_syscalls)
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define __ARCH_WANT_NEW_STAT
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_IPC
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_UTIME32
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_UNAME
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+# ifdef CONFIG_32BIT
+#  define __ARCH_WANT_STAT64
+#  define __ARCH_WANT_SYS_TIME32
+# endif
+# ifdef CONFIG_MIPS32_O32
+#  define __ARCH_WANT_SYS_TIME32
+# endif
+#define __ARCH_WANT_SYS_FORK
+#define __ARCH_WANT_SYS_CLONE
+#define __ARCH_WANT_SYS_CLONE3
+
+/* whitelists for checksyscalls */
+#define __IGNORE_fadvise64_64
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNISTD_H */
diff --git a/arch/mips/include/asm/unroll.h b/arch/mips/include/asm/unroll.h
new file mode 100644
index 000000000..6f4ac854b
--- /dev/null
+++ b/arch/mips/include/asm/unroll.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_UNROLL_H__
+#define __ASM_UNROLL_H__
+
+/*
+ * Explicitly unroll a loop, for use in cases where doing so is performance
+ * critical.
+ *
+ * Ideally we'd rely upon the compiler to provide this but there's no commonly
+ * available means to do so. For example GCC's "#pragma GCC unroll"
+ * functionality would be ideal but is only available from GCC 8 onwards. Using
+ * -funroll-loops is an option but GCC tends to make poor choices when
+ * compiling our string functions. -funroll-all-loops leads to massive code
+ * bloat, even if only applied to the string functions.
+ */
+#define unroll(times, fn, ...) do {                             \
+        extern void bad_unroll(void)                            \
+                __compiletime_error("Unsupported unroll");      \
+                                                                \
+        /*                                                      \
+         * We can't unroll if the number of iterations isn't    \
+         * compile-time constant. Unfortunately clang versions  \
+         * up until 8.0 tend to miss obvious constants & cause  \
+         * this check to fail, even though they go on to        \
+         * generate reasonable code for the switch statement,   \
+         * so we skip the sanity check for those compilers.     \
+         */                                                     \
+        BUILD_BUG_ON(!__builtin_constant_p(times));             \
+                                                                \
+        switch (times) {                                        \
+        case 32: fn(__VA_ARGS__); fallthrough;                  \
+        case 31: fn(__VA_ARGS__); fallthrough;                  \
+        case 30: fn(__VA_ARGS__); fallthrough;                  \
+        case 29: fn(__VA_ARGS__); fallthrough;                  \
+        case 28: fn(__VA_ARGS__); fallthrough;                  \
+        case 27: fn(__VA_ARGS__); fallthrough;                  \
+        case 26: fn(__VA_ARGS__); fallthrough;                  \
+        case 25: fn(__VA_ARGS__); fallthrough;                  \
+        case 24: fn(__VA_ARGS__); fallthrough;                  \
+        case 23: fn(__VA_ARGS__); fallthrough;                  \
+        case 22: fn(__VA_ARGS__); fallthrough;                  \
+        case 21: fn(__VA_ARGS__); fallthrough;                  \
+        case 20: fn(__VA_ARGS__); fallthrough;                  \
+        case 19: fn(__VA_ARGS__); fallthrough;                  \
+        case 18: fn(__VA_ARGS__); fallthrough;                  \
+        case 17: fn(__VA_ARGS__); fallthrough;                  \
+        case 16: fn(__VA_ARGS__); fallthrough;                  \
+        case 15: fn(__VA_ARGS__); fallthrough;                  \
+        case 14: fn(__VA_ARGS__); fallthrough;                  \
+        case 13: fn(__VA_ARGS__); fallthrough;                  \
+        case 12: fn(__VA_ARGS__); fallthrough;                  \
+        case 11: fn(__VA_ARGS__); fallthrough;                  \
+        case 10: fn(__VA_ARGS__); fallthrough;                  \
+        case 9: fn(__VA_ARGS__); fallthrough;                   \
+        case 8: fn(__VA_ARGS__); fallthrough;                   \
+        case 7: fn(__VA_ARGS__); fallthrough;                   \
+        case 6: fn(__VA_ARGS__); fallthrough;                   \
+        case 5: fn(__VA_ARGS__); fallthrough;                   \
+        case 4: fn(__VA_ARGS__); fallthrough;                   \
+        case 3: fn(__VA_ARGS__); fallthrough;                   \
+        case 2: fn(__VA_ARGS__); fallthrough;                   \
+        case 1: fn(__VA_ARGS__); fallthrough;                   \
+        case 0: break;                                          \
+                                                                \
+        default:                                                \
+                /*                                              \
+                 * Either the iteration count is unreasonable   \
+                 * or we need to add more cases above.          \
+                 */                                             \
+                bad_unroll();                                   \
+                break;                                          \
+        }                                                       \
+} while (0)
+
+#endif /* __ASM_UNROLL_H__ */
diff --git a/arch/mips/include/asm/uprobes.h b/arch/mips/include/asm/uprobes.h
new file mode 100644
index 000000000..b86d1ae07
--- /dev/null
+++ b/arch/mips/include/asm/uprobes.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_UPROBES_H
+#define __ASM_UPROBES_H
+
+#include <linux/notifier.h>
+#include <linux/types.h>
+
+#include <asm/break.h>
+#include <asm/inst.h>
+
+/*
+ * We want this to be defined as union mips_instruction but that makes the
+ * generic code blow up.
+ */
+typedef u32 uprobe_opcode_t;
+
+/*
+ * Classic MIPS (note this implementation doesn't consider microMIPS yet)
+ * instructions are always 4 bytes but in order to deal with branches and
+ * their delay slots, we treat instructions as having 8 bytes maximum.
+ */
+#define MAX_UINSN_BYTES                 8
+#define UPROBE_XOL_SLOT_BYTES           128     /* Max. cache line size */
+
+#define UPROBE_BRK_UPROBE               0x000d000d      /* break 13 */
+#define UPROBE_BRK_UPROBE_XOL           0x000e000d      /* break 14 */
+
+#define UPROBE_SWBP_INSN                UPROBE_BRK_UPROBE
+#define UPROBE_SWBP_INSN_SIZE           4
+
+struct arch_uprobe {
+        unsigned long   resume_epc;
+        u32     insn[2];
+        u32     ixol[2];
+};
+
+struct arch_uprobe_task {
+        unsigned long saved_trap_nr;
+};
+
+#endif /* __ASM_UPROBES_H */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
new file mode 100644
index 000000000..cc7b51612
--- /dev/null
+++ b/arch/mips/include/asm/vdso.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ */
+
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#include <linux/mm_types.h>
+#include <vdso/datapage.h>
+
+#include <asm/barrier.h>
+
+/**
+ * struct mips_vdso_image - Details of a VDSO image.
+ * @data: Pointer to VDSO image data (page-aligned).
+ * @size: Size of the VDSO image data (page-aligned).
+ * @off_sigreturn: Offset of the sigreturn() trampoline.
+ * @off_rt_sigreturn: Offset of the rt_sigreturn() trampoline.
+ * @mapping: Special mapping structure.
+ *
+ * This structure contains details of a VDSO image, including the image data
+ * and offsets of certain symbols required by the kernel. It is generated as
+ * part of the VDSO build process, aside from the mapping page array, which is
+ * populated at runtime.
+ */
+struct mips_vdso_image {
+        void *data;
+        unsigned long size;
+
+        unsigned long off_sigreturn;
+        unsigned long off_rt_sigreturn;
+
+        struct vm_special_mapping mapping;
+};
+
+/*
+ * The following structures are auto-generated as part of the build for each
+ * ABI by genvdso, see arch/mips/vdso/Makefile.
+ */
+
+extern struct mips_vdso_image vdso_image;
+
+#ifdef CONFIG_MIPS32_O32
+extern struct mips_vdso_image vdso_image_o32;
+#endif
+
+#ifdef CONFIG_MIPS32_N32
+extern struct mips_vdso_image vdso_image_n32;
+#endif
+
+union mips_vdso_data {
+        struct vdso_data data[CS_BASES];
+        u8 page[PAGE_SIZE];
+};
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/mips/include/asm/vdso/clocksource.h b/arch/mips/include/asm/vdso/clocksource.h
new file mode 100644
index 000000000..510e1671d
--- /dev/null
+++ b/arch/mips/include/asm/vdso/clocksource.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __ASM_VDSOCLOCKSOURCE_H
+#define __ASM_VDSOCLOCKSOURCE_H
+
+#define VDSO_ARCH_CLOCKMODES    \
+        VDSO_CLOCKMODE_R4K,     \
+        VDSO_CLOCKMODE_GIC
+
+#endif /* __ASM_VDSOCLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
new file mode 100644
index 000000000..44a45f3fa
--- /dev/null
+++ b/arch/mips/include/asm/vdso/gettimeofday.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2018 ARM Limited
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_VDSO_GETTIMEOFDAY_H
+#define __ASM_VDSO_GETTIMEOFDAY_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/vdso/vdso.h>
+#include <asm/clocksource.h>
+#include <asm/unistd.h>
+#include <asm/vdso.h>
+
+#define VDSO_HAS_CLOCK_GETRES           1
+
+#if MIPS_ISA_REV < 6
+#define VDSO_SYSCALL_CLOBBERS "hi", "lo",
+#else
+#define VDSO_SYSCALL_CLOBBERS
+#endif
+
+static __always_inline long gettimeofday_fallback(
+                                struct __kernel_old_timeval *_tv,
+                                struct timezone *_tz)
+{
+        register struct timezone *tz asm("a1") = _tz;
+        register struct __kernel_old_timeval *tv asm("a0") = _tv;
+        register long ret asm("v0");
+        register long nr asm("v0") = __NR_gettimeofday;
+        register long error asm("a3");
+
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (tv), "r" (tz), "r" (nr)
+        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+          "$14", "$15", "$24", "$25",
+          VDSO_SYSCALL_CLOBBERS
+          "memory");
+
+        return error ? -ret : ret;
+}
+
+static __always_inline long clock_gettime_fallback(
+                                        clockid_t _clkid,
+                                        struct __kernel_timespec *_ts)
+{
+        register struct __kernel_timespec *ts asm("a1") = _ts;
+        register clockid_t clkid asm("a0") = _clkid;
+        register long ret asm("v0");
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+        register long nr asm("v0") = __NR_clock_gettime;
+#else
+        register long nr asm("v0") = __NR_clock_gettime64;
+#endif
+        register long error asm("a3");
+
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (clkid), "r" (ts), "r" (nr)
+        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+          "$14", "$15", "$24", "$25",
+          VDSO_SYSCALL_CLOBBERS
+          "memory");
+
+        return error ? -ret : ret;
+}
+
+static __always_inline int clock_getres_fallback(
+                                        clockid_t _clkid,
+                                        struct __kernel_timespec *_ts)
+{
+        register struct __kernel_timespec *ts asm("a1") = _ts;
+        register clockid_t clkid asm("a0") = _clkid;
+        register long ret asm("v0");
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+        register long nr asm("v0") = __NR_clock_getres;
+#else
+        register long nr asm("v0") = __NR_clock_getres_time64;
+#endif
+        register long error asm("a3");
+
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (clkid), "r" (ts), "r" (nr)
+        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+          "$14", "$15", "$24", "$25",
+          VDSO_SYSCALL_CLOBBERS
+          "memory");
+
+        return error ? -ret : ret;
+}
+
+#if _MIPS_SIM != _MIPS_SIM_ABI64
+
+static __always_inline long clock_gettime32_fallback(
+                                        clockid_t _clkid,
+                                        struct old_timespec32 *_ts)
+{
+        register struct old_timespec32 *ts asm("a1") = _ts;
+        register clockid_t clkid asm("a0") = _clkid;
+        register long ret asm("v0");
+        register long nr asm("v0") = __NR_clock_gettime;
+        register long error asm("a3");
+
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (clkid), "r" (ts), "r" (nr)
+        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+          "$14", "$15", "$24", "$25",
+          VDSO_SYSCALL_CLOBBERS
+          "memory");
+
+        return error ? -ret : ret;
+}
+
+static __always_inline int clock_getres32_fallback(
+                                        clockid_t _clkid,
+                                        struct old_timespec32 *_ts)
+{
+        register struct old_timespec32 *ts asm("a1") = _ts;
+        register clockid_t clkid asm("a0") = _clkid;
+        register long ret asm("v0");
+        register long nr asm("v0") = __NR_clock_getres;
+        register long error asm("a3");
+
+        asm volatile(
+        "       syscall\n"
+        : "=r" (ret), "=r" (error)
+        : "r" (clkid), "r" (ts), "r" (nr)
+        : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+          "$14", "$15", "$24", "$25",
+          VDSO_SYSCALL_CLOBBERS
+          "memory");
+
+        return error ? -ret : ret;
+}
+#endif
+
+#ifdef CONFIG_CSRC_R4K
+
+static __always_inline u64 read_r4k_count(void)
+{
+        unsigned int count;
+
+        __asm__ __volatile__(
+        "       .set push\n"
+        "       .set mips32r2\n"
+        "       rdhwr   %0, $2\n"
+        "       .set pop\n"
+        : "=r" (count));
+
+        return count;
+}
+
+#endif
+
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+
+static __always_inline u64 read_gic_count(const struct vdso_data *data)
+{
+        void __iomem *gic = get_gic(data);
+        u32 hi, hi2, lo;
+
+        do {
+                hi = __raw_readl(gic + sizeof(lo));
+                lo = __raw_readl(gic);
+                hi2 = __raw_readl(gic + sizeof(lo));
+        } while (hi2 != hi);
+
+        return (((u64)hi) << 32) + lo;
+}
+
+#endif
+
+static __always_inline u64 __arch_get_hw_counter(s32 clock_mode,
+                                                 const struct vdso_data *vd)
+{
+#ifdef CONFIG_CSRC_R4K
+        if (clock_mode == VDSO_CLOCKMODE_R4K)
+                return read_r4k_count();
+#endif
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+        if (clock_mode == VDSO_CLOCKMODE_GIC)
+                return read_gic_count(vd);
+#endif
+        /*
+         * Core checks mode already. So this raced against a concurrent
+         * update. Return something. Core will do another round see the
+         * change and fallback to syscall.
+         */
+        return 0;
+}
+
+static inline bool mips_vdso_hres_capable(void)
+{
+        return IS_ENABLED(CONFIG_CSRC_R4K) ||
+               IS_ENABLED(CONFIG_CLKSRC_MIPS_GIC);
+}
+#define __arch_vdso_hres_capable mips_vdso_hres_capable
+
+static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
+{
+        return get_vdso_data();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_GETTIMEOFDAY_H */
diff --git a/arch/mips/include/asm/vdso/processor.h b/arch/mips/include/asm/vdso/processor.h
new file mode 100644
index 000000000..511c95d73
--- /dev/null
+++ b/arch/mips/include/asm/vdso/processor.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 ARM Ltd.
+ */
+#ifndef __ASM_VDSO_PROCESSOR_H
+#define __ASM_VDSO_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_CPU_LOONGSON64
+/*
+ * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
+ * tight read loop is executed, because reads take priority over writes & the
+ * hardware (incorrectly) doesn't ensure that writes will eventually occur.
+ *
+ * Since spin loops of any kind should have a cpu_relax() in them, force an SFB
+ * flush from cpu_relax() such that any pending writes will become visible as
+ * expected.
+ */
+#define cpu_relax()     smp_mb()
+#else
+#define cpu_relax()     barrier()
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_PROCESSOR_H */
diff --git a/arch/mips/include/asm/vdso/vdso.h b/arch/mips/include/asm/vdso/vdso.h
new file mode 100644
index 000000000..a327ca212
--- /dev/null
+++ b/arch/mips/include/asm/vdso/vdso.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ */
+
+#include <asm/sgidefs.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/asm.h>
+#include <asm/page.h>
+#include <asm/vdso.h>
+
+static inline unsigned long get_vdso_base(void)
+{
+        unsigned long addr;
+
+        /*
+         * We can't use cpu_has_mips_r6 since it needs the cpu_data[]
+         * kernel symbol.
+         */
+#ifdef CONFIG_CPU_MIPSR6
+        /*
+         * lapc <symbol> is an alias to addiupc reg, <symbol> - .
+         *
+         * We can't use addiupc because there is no label-label
+         * support for the addiupc reloc
+         */
+        __asm__("lapc   %0, _start                      \n"
+                : "=r" (addr) : :);
+#else
+        /*
+         * Get the base load address of the VDSO. We have to avoid generating
+         * relocations and references to the GOT because ld.so does not peform
+         * relocations on the VDSO. We use the current offset from the VDSO base
+         * and perform a PC-relative branch which gives the absolute address in
+         * ra, and take the difference. The assembler chokes on
+         * "li %0, _start - .", so embed the offset as a word and branch over
+         * it.
+         *
+         */
+
+        __asm__(
+        "       .set push                               \n"
+        "       .set noreorder                          \n"
+        "       bal     1f                              \n"
+        "        nop                                    \n"
+        "       .word   _start - .                      \n"
+        "1:     lw      %0, 0($31)                      \n"
+        "       " STR(PTR_ADDU) " %0, $31, %0           \n"
+        "       .set pop                                \n"
+        : "=r" (addr)
+        :
+        : "$31");
+#endif /* CONFIG_CPU_MIPSR6 */
+
+        return addr;
+}
+
+static inline const struct vdso_data *get_vdso_data(void)
+{
+        return (const struct vdso_data *)(get_vdso_base() - PAGE_SIZE);
+}
+
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+
+static inline void __iomem *get_gic(const struct vdso_data *data)
+{
+        return (void __iomem *)((unsigned long)data & PAGE_MASK) - PAGE_SIZE;
+}
+
+#endif /* CONFIG_CLKSRC_MIPS_GIC */
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/vdso/vsyscall.h b/arch/mips/include/asm/vdso/vsyscall.h
new file mode 100644
index 000000000..47168aaf1
--- /dev/null
+++ b/arch/mips/include/asm/vdso/vsyscall.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_VDSO_VSYSCALL_H
+#define __ASM_VDSO_VSYSCALL_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/timekeeper_internal.h>
+#include <vdso/datapage.h>
+
+extern struct vdso_data *vdso_data;
+
+/*
+ * Update the vDSO data page to keep in sync with kernel timekeeping.
+ */
+static __always_inline
+struct vdso_data *__mips_get_k_vdso_data(void)
+{
+        return vdso_data;
+}
+#define __arch_get_k_vdso_data __mips_get_k_vdso_data
+
+/* The asm-generic header needs to be included after the definitions above */
+#include <asm-generic/vdso/vsyscall.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_VSYSCALL_H */
diff --git a/arch/mips/include/asm/vermagic.h b/arch/mips/include/asm/vermagic.h
new file mode 100644
index 000000000..4d2dae0c7
--- /dev/null
+++ b/arch/mips/include/asm/vermagic.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_VERMAGIC_H
+#define _ASM_VERMAGIC_H
+
+#ifdef CONFIG_CPU_BMIPS
+#define MODULE_PROC_FAMILY "BMIPS "
+#elif defined CONFIG_CPU_MIPS32_R1
+#define MODULE_PROC_FAMILY "MIPS32_R1 "
+#elif defined CONFIG_CPU_MIPS32_R2
+#define MODULE_PROC_FAMILY "MIPS32_R2 "
+#elif defined CONFIG_CPU_MIPS32_R5
+#define MODULE_PROC_FAMILY "MIPS32_R5 "
+#elif defined CONFIG_CPU_MIPS32_R6
+#define MODULE_PROC_FAMILY "MIPS32_R6 "
+#elif defined CONFIG_CPU_MIPS64_R1
+#define MODULE_PROC_FAMILY "MIPS64_R1 "
+#elif defined CONFIG_CPU_MIPS64_R2
+#define MODULE_PROC_FAMILY "MIPS64_R2 "
+#elif defined CONFIG_CPU_MIPS64_R5
+#define MODULE_PROC_FAMILY "MIPS64_R5 "
+#elif defined CONFIG_CPU_MIPS64_R6
+#define MODULE_PROC_FAMILY "MIPS64_R6 "
+#elif defined CONFIG_CPU_R3000
+#define MODULE_PROC_FAMILY "R3000 "
+#elif defined CONFIG_CPU_TX39XX
+#define MODULE_PROC_FAMILY "TX39XX "
+#elif defined CONFIG_CPU_VR41XX
+#define MODULE_PROC_FAMILY "VR41XX "
+#elif defined CONFIG_CPU_R4X00
+#define MODULE_PROC_FAMILY "R4X00 "
+#elif defined CONFIG_CPU_TX49XX
+#define MODULE_PROC_FAMILY "TX49XX "
+#elif defined CONFIG_CPU_R5000
+#define MODULE_PROC_FAMILY "R5000 "
+#elif defined CONFIG_CPU_R5500
+#define MODULE_PROC_FAMILY "R5500 "
+#elif defined CONFIG_CPU_NEVADA
+#define MODULE_PROC_FAMILY "NEVADA "
+#elif defined CONFIG_CPU_R10000
+#define MODULE_PROC_FAMILY "R10000 "
+#elif defined CONFIG_CPU_RM7000
+#define MODULE_PROC_FAMILY "RM7000 "
+#elif defined CONFIG_CPU_SB1
+#define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON32
+#define MODULE_PROC_FAMILY "LOONGSON32 "
+#elif defined CONFIG_CPU_LOONGSON2EF
+#define MODULE_PROC_FAMILY "LOONGSON2EF "
+#elif defined CONFIG_CPU_LOONGSON64
+#define MODULE_PROC_FAMILY "LOONGSON64 "
+#elif defined CONFIG_CPU_CAVIUM_OCTEON
+#define MODULE_PROC_FAMILY "OCTEON "
+#elif defined CONFIG_CPU_P5600
+#define MODULE_PROC_FAMILY "P5600 "
+#elif defined CONFIG_CPU_XLR
+#define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
+#else
+#error MODULE_PROC_FAMILY undefined for your processor configuration
+#endif
+
+#ifdef CONFIG_32BIT
+#define MODULE_KERNEL_TYPE "32BIT "
+#elif defined CONFIG_64BIT
+#define MODULE_KERNEL_TYPE "64BIT "
+#endif
+
+#define MODULE_ARCH_VERMAGIC \
+        MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
+
+#endif /* _ASM_VERMAGIC_H */
diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
new file mode 100644
index 000000000..0136e0366
--- /dev/null
+++ b/arch/mips/include/asm/vga.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+#ifndef _ASM_VGA_H
+#define _ASM_VGA_H
+
+#include <linux/string.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+/*
+ *      On the PC, we can just recalculate addresses and then
+ *      access the videoram directly without any black magic.
+ */
+
+#define VGA_MAP_MEM(x, s)       CKSEG1ADDR(0x10000000L + (unsigned long)(x))
+
+#define vga_readb(x)    (*(x))
+#define vga_writeb(x, y)        (*(y) = (x))
+
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+#undef scr_writew
+#undef scr_readw
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+        *addr = cpu_to_le16(val);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+        return le16_to_cpu(*addr);
+}
+
+static inline void scr_memsetw(u16 *s, u16 v, unsigned int count)
+{
+        memset16(s, cpu_to_le16(v), count / 2);
+}
+
+#define scr_memcpyw(d, s, c) memcpy(d, s, c)
+#define scr_memmovew(d, s, c) memmove(d, s, c)
+#define VT_BUF_HAVE_MEMCPYW
+#define VT_BUF_HAVE_MEMMOVEW
+#define VT_BUF_HAVE_MEMSETW
+
+#endif /* _ASM_VGA_H */
diff --git a/arch/mips/include/asm/vmalloc.h b/arch/mips/include/asm/vmalloc.h
new file mode 100644
index 000000000..25dc09b25
--- /dev/null
+++ b/arch/mips/include/asm/vmalloc.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_MIPS_VMALLOC_H
+#define _ASM_MIPS_VMALLOC_H
+
+#endif /* _ASM_MIPS_VMALLOC_H */
diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h
new file mode 100644
index 000000000..80e70dbd1
--- /dev/null
+++ b/arch/mips/include/asm/vpe.h
@@ -0,0 +1,130 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#ifndef _ASM_VPE_H
+#define _ASM_VPE_H
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+
+#define VPE_MODULE_NAME "vpe"
+#define VPE_MODULE_MINOR 1
+
+/* grab the likely amount of memory we will need. */
+#ifdef CONFIG_MIPS_VPE_LOADER_TOM
+#define P_SIZE (2 * 1024 * 1024)
+#else
+/* add an overhead to the max kmalloc size for non-striped symbols/etc */
+#define P_SIZE (256 * 1024)
+#endif
+
+#define MAX_VPES 16
+#define VPE_PATH_MAX 256
+
+static inline int aprp_cpu_index(void)
+{
+#ifdef CONFIG_MIPS_CMP
+        return setup_max_cpus;
+#else
+        extern int tclimit;
+        return tclimit;
+#endif
+}
+
+enum vpe_state {
+        VPE_STATE_UNUSED = 0,
+        VPE_STATE_INUSE,
+        VPE_STATE_RUNNING
+};
+
+enum tc_state {
+        TC_STATE_UNUSED = 0,
+        TC_STATE_INUSE,
+        TC_STATE_RUNNING,
+        TC_STATE_DYNAMIC
+};
+
+struct vpe {
+        enum vpe_state state;
+
+        /* (device) minor associated with this vpe */
+        int minor;
+
+        /* elfloader stuff */
+        void *load_addr;
+        unsigned long len;
+        char *pbuffer;
+        unsigned long plen;
+        char cwd[VPE_PATH_MAX];
+
+        unsigned long __start;
+
+        /* tc's associated with this vpe */
+        struct list_head tc;
+
+        /* The list of vpe's */
+        struct list_head list;
+
+        /* shared symbol address */
+        void *shared_ptr;
+
+        /* the list of who wants to know when something major happens */
+        struct list_head notify;
+
+        unsigned int ntcs;
+};
+
+struct tc {
+        enum tc_state state;
+        int index;
+
+        struct vpe *pvpe;       /* parent VPE */
+        struct list_head tc;    /* The list of TC's with this VPE */
+        struct list_head list;  /* The global list of tc's */
+};
+
+struct vpe_notifications {
+        void (*start)(int vpe);
+        void (*stop)(int vpe);
+
+        struct list_head list;
+};
+
+struct vpe_control {
+        spinlock_t vpe_list_lock;
+        struct list_head vpe_list;      /* Virtual processing elements */
+        spinlock_t tc_list_lock;
+        struct list_head tc_list;       /* Thread contexts */
+};
+
+extern unsigned long physical_memsize;
+extern struct vpe_control vpecontrol;
+extern const struct file_operations vpe_fops;
+
+int vpe_notify(int index, struct vpe_notifications *notify);
+
+void *vpe_get_shared(int index);
+char *vpe_getcwd(int index);
+
+struct vpe *get_vpe(int minor);
+struct tc *get_tc(int index);
+struct vpe *alloc_vpe(int minor);
+struct tc *alloc_tc(int index);
+void release_vpe(struct vpe *v);
+
+void *alloc_progmem(unsigned long len);
+void release_progmem(void *ptr);
+
+int vpe_run(struct vpe *v);
+void cleanup_tc(struct tc *tc);
+
+int __init vpe_module_init(void);
+void __exit vpe_module_exit(void);
+#endif /* _ASM_VPE_H */
diff --git a/arch/mips/include/asm/vr41xx/capcella.h b/arch/mips/include/asm/vr41xx/capcella.h
new file mode 100644
index 000000000..d45a33969
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/capcella.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  capcella.h, Include file for ZAO Networks Capcella.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __ZAO_CAPCELLA_H
+#define __ZAO_CAPCELLA_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define PC104PLUS_INTA_PIN              2
+#define PC104PLUS_INTB_PIN              3
+#define PC104PLUS_INTC_PIN              4
+#define PC104PLUS_INTD_PIN              5
+
+/*
+ * Interrupt Number
+ */
+#define RTL8139_1_IRQ                   GIU_IRQ(PC104PLUS_INTC_PIN)
+#define RTL8139_2_IRQ                   GIU_IRQ(PC104PLUS_INTD_PIN)
+#define PC104PLUS_INTA_IRQ              GIU_IRQ(PC104PLUS_INTA_PIN)
+#define PC104PLUS_INTB_IRQ              GIU_IRQ(PC104PLUS_INTB_PIN)
+#define PC104PLUS_INTC_IRQ              GIU_IRQ(PC104PLUS_INTC_PIN)
+#define PC104PLUS_INTD_IRQ              GIU_IRQ(PC104PLUS_INTD_PIN)
+
+#endif /* __ZAO_CAPCELLA_H */
diff --git a/arch/mips/include/asm/vr41xx/giu.h b/arch/mips/include/asm/vr41xx/giu.h
new file mode 100644
index 000000000..0211fa898
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/giu.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Include file for NEC VR4100 series General-purpose I/O Unit.
+ *
+ *  Copyright (C) 2005-2009  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __NEC_VR41XX_GIU_H
+#define __NEC_VR41XX_GIU_H
+
+/*
+ * NEC VR4100 series GIU platform device IDs.
+ */
+enum {
+        GPIO_50PINS_PULLUPDOWN,
+        GPIO_36PINS,
+        GPIO_48PINS_EDGE_SELECT,
+};
+
+typedef enum {
+        IRQ_TRIGGER_LEVEL,
+        IRQ_TRIGGER_EDGE,
+        IRQ_TRIGGER_EDGE_FALLING,
+        IRQ_TRIGGER_EDGE_RISING,
+} irq_trigger_t;
+
+typedef enum {
+        IRQ_SIGNAL_THROUGH,
+        IRQ_SIGNAL_HOLD,
+} irq_signal_t;
+
+extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
+                                   irq_signal_t signal);
+
+typedef enum {
+        IRQ_LEVEL_LOW,
+        IRQ_LEVEL_HIGH,
+} irq_level_t;
+
+extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
+
+#endif /* __NEC_VR41XX_GIU_H */
diff --git a/arch/mips/include/asm/vr41xx/irq.h b/arch/mips/include/asm/vr41xx/irq.h
new file mode 100644
index 000000000..2f3d552f9
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/irq.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * include/asm-mips/vr41xx/irq.h
+ *
+ * Interrupt numbers for NEC VR4100 series.
+ *
+ * Copyright (C) 1999 Michael Klar
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+ * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __NEC_VR41XX_IRQ_H
+#define __NEC_VR41XX_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE       0
+#define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
+#define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
+#define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
+#define INT0_IRQ                MIPS_CPU_IRQ(2)
+#define INT1_IRQ                MIPS_CPU_IRQ(3)
+#define INT2_IRQ                MIPS_CPU_IRQ(4)
+#define INT3_IRQ                MIPS_CPU_IRQ(5)
+#define INT4_IRQ                MIPS_CPU_IRQ(6)
+#define TIMER_IRQ               MIPS_CPU_IRQ(7)
+
+/*
+ * SYINT1 Interrupt Numbers
+ */
+#define SYSINT1_IRQ_BASE        8
+#define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
+#define BATTRY_IRQ              SYSINT1_IRQ(0)
+#define POWER_IRQ               SYSINT1_IRQ(1)
+#define RTCLONG1_IRQ            SYSINT1_IRQ(2)
+#define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
+/* RFU */
+#define PIU_IRQ                 SYSINT1_IRQ(5)
+#define AIU_IRQ                 SYSINT1_IRQ(6)
+#define KIU_IRQ                 SYSINT1_IRQ(7)
+#define GIUINT_IRQ              SYSINT1_IRQ(8)
+#define SIU_IRQ                 SYSINT1_IRQ(9)
+#define BUSERR_IRQ              SYSINT1_IRQ(10)
+#define SOFTINT_IRQ             SYSINT1_IRQ(11)
+#define CLKRUN_IRQ              SYSINT1_IRQ(12)
+#define DOZEPIU_IRQ             SYSINT1_IRQ(13)
+#define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
+
+/*
+ * SYSINT2 Interrupt Numbers
+ */
+#define SYSINT2_IRQ_BASE        24
+#define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
+#define RTCLONG2_IRQ            SYSINT2_IRQ(0)
+#define LED_IRQ                 SYSINT2_IRQ(1)
+#define HSP_IRQ                 SYSINT2_IRQ(2)
+#define TCLOCK_IRQ              SYSINT2_IRQ(3)
+#define FIR_IRQ                 SYSINT2_IRQ(4)
+#define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
+#define DSIU_IRQ                SYSINT2_IRQ(5)
+#define PCI_IRQ                 SYSINT2_IRQ(6)
+#define SCU_IRQ                 SYSINT2_IRQ(7)
+#define CSI_IRQ                 SYSINT2_IRQ(8)
+#define BCU_IRQ                 SYSINT2_IRQ(9)
+#define ETHERNET_IRQ            SYSINT2_IRQ(10)
+#define SYSINT2_IRQ_LAST        ETHERNET_IRQ
+
+/*
+ * GIU Interrupt Numbers
+ */
+#define GIU_IRQ_BASE            40
+#define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
+#define GIU_IRQ_LAST            GIU_IRQ(31)
+
+/*
+ * VRC4173 Interrupt Numbers
+ */
+#define VRC4173_IRQ_BASE        72
+#define VRC4173_IRQ(x)          (VRC4173_IRQ_BASE + (x))
+#define VRC4173_USB_IRQ         VRC4173_IRQ(0)
+#define VRC4173_PCMCIA2_IRQ     VRC4173_IRQ(1)
+#define VRC4173_PCMCIA1_IRQ     VRC4173_IRQ(2)
+#define VRC4173_PS2CH2_IRQ      VRC4173_IRQ(3)
+#define VRC4173_PS2CH1_IRQ      VRC4173_IRQ(4)
+#define VRC4173_PIU_IRQ         VRC4173_IRQ(5)
+#define VRC4173_AIU_IRQ         VRC4173_IRQ(6)
+#define VRC4173_KIU_IRQ         VRC4173_IRQ(7)
+#define VRC4173_GIU_IRQ         VRC4173_IRQ(8)
+#define VRC4173_AC97_IRQ        VRC4173_IRQ(9)
+#define VRC4173_AC97INT1_IRQ    VRC4173_IRQ(10)
+/* RFU */
+#define VRC4173_DOZEPIU_IRQ     VRC4173_IRQ(13)
+#define VRC4173_IRQ_LAST        VRC4173_DOZEPIU_IRQ
+
+#endif /* __NEC_VR41XX_IRQ_H */
diff --git a/arch/mips/include/asm/vr41xx/mpc30x.h b/arch/mips/include/asm/vr41xx/mpc30x.h
new file mode 100644
index 000000000..9f977e18d
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/mpc30x.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  mpc30x.h, Include file for Victor MP-C303/304.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __VICTOR_MPC30X_H
+#define __VICTOR_MPC30X_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define VRC4173_PIN                     1
+#define MQ200_PIN                       4
+
+/*
+ * Interrupt Number
+ */
+#define VRC4173_CASCADE_IRQ             GIU_IRQ(VRC4173_PIN)
+#define MQ200_IRQ                       GIU_IRQ(MQ200_PIN)
+
+#endif /* __VICTOR_MPC30X_H */
diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h
new file mode 100644
index 000000000..ad93b5e89
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/pci.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Include file for NEC VR4100 series PCI Control Unit.
+ *
+ *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __NEC_VR41XX_PCI_H
+#define __NEC_VR41XX_PCI_H
+
+#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
+
+struct pci_master_address_conversion {
+        uint32_t bus_base_address;
+        uint32_t address_mask;
+        uint32_t pci_base_address;
+};
+
+struct pci_target_address_conversion {
+        uint32_t address_mask;
+        uint32_t bus_base_address;
+};
+
+typedef enum {
+        CANNOT_LOCK_FROM_DEVICE,
+        CAN_LOCK_FROM_DEVICE,
+} pci_exclusive_access_t;
+
+struct pci_mailbox_address {
+        uint32_t base_address;
+};
+
+struct pci_target_address_window {
+        uint32_t base_address;
+};
+
+typedef enum {
+        PCI_ARBITRATION_MODE_FAIR,
+        PCI_ARBITRATION_MODE_ALTERNATE_0,
+        PCI_ARBITRATION_MODE_ALTERNATE_B,
+} pci_arbiter_priority_control_t;
+
+typedef enum {
+        PCI_TAKE_AWAY_GNT_DISABLE,
+        PCI_TAKE_AWAY_GNT_ENABLE,
+} pci_take_away_gnt_mode_t;
+
+struct pci_controller_unit_setup {
+        struct pci_master_address_conversion *master_memory1;
+        struct pci_master_address_conversion *master_memory2;
+
+        struct pci_target_address_conversion *target_memory1;
+        struct pci_target_address_conversion *target_memory2;
+
+        struct pci_master_address_conversion *master_io;
+
+        pci_exclusive_access_t exclusive_access;
+
+        uint32_t pci_clock_max;
+        uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
+
+        struct pci_mailbox_address *mailbox;
+        struct pci_target_address_window *target_window1;
+        struct pci_target_address_window *target_window2;
+
+        uint8_t master_latency_timer;
+        uint8_t retry_limit;
+
+        pci_arbiter_priority_control_t arbiter_priority_control;
+        pci_take_away_gnt_mode_t take_away_gnt_mode;
+
+        struct resource *mem_resource;
+        struct resource *io_resource;
+};
+
+extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
+
+#endif /* __NEC_VR41XX_PCI_H */
diff --git a/arch/mips/include/asm/vr41xx/siu.h b/arch/mips/include/asm/vr41xx/siu.h
new file mode 100644
index 000000000..e920cd2cf
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/siu.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Include file for NEC VR4100 series Serial Interface Unit.
+ *
+ *  Copyright (C) 2005-2008  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __NEC_VR41XX_SIU_H
+#define __NEC_VR41XX_SIU_H
+
+#define SIU_PORTS_MAX 2
+
+typedef enum {
+        SIU_INTERFACE_RS232C,
+        SIU_INTERFACE_IRDA,
+} siu_interface_t;
+
+extern void vr41xx_select_siu_interface(siu_interface_t interface);
+
+typedef enum {
+        SIU_USE_IRDA,
+        FIR_USE_IRDA,
+} irda_use_t;
+
+extern void vr41xx_use_irda(irda_use_t use);
+
+typedef enum {
+        SHARP_IRDA,
+        TEMIC_IRDA,
+        HP_IRDA,
+} irda_module_t;
+
+typedef enum {
+        IRDA_TX_1_5MBPS,
+        IRDA_TX_4MBPS,
+} irda_speed_t;
+
+extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
+
+#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
+extern void vr41xx_siu_early_setup(struct uart_port *port);
+#else
+static inline void vr41xx_siu_early_setup(struct uart_port *port) {}
+#endif
+
+#endif /* __NEC_VR41XX_SIU_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0219.h b/arch/mips/include/asm/vr41xx/tb0219.h
new file mode 100644
index 000000000..01e96d6c2
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0219.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  tb0219.h, Include file for TANBAC TB0219.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@linux-mips.org>
+ *
+ *  Modified for TANBAC TB0219:
+ *  Copyright (C) 2003 Megasolution Inc.  <matsu@megasolution.jp>
+ */
+#ifndef __TANBAC_TB0219_H
+#define __TANBAC_TB0219_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define TB0219_PCI_SLOT1_PIN            2
+#define TB0219_PCI_SLOT2_PIN            3
+#define TB0219_PCI_SLOT3_PIN            4
+
+/*
+ * Interrupt Number
+ */
+#define TB0219_PCI_SLOT1_IRQ            GIU_IRQ(TB0219_PCI_SLOT1_PIN)
+#define TB0219_PCI_SLOT2_IRQ            GIU_IRQ(TB0219_PCI_SLOT2_PIN)
+#define TB0219_PCI_SLOT3_IRQ            GIU_IRQ(TB0219_PCI_SLOT3_PIN)
+
+#endif /* __TANBAC_TB0219_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0226.h b/arch/mips/include/asm/vr41xx/tb0226.h
new file mode 100644
index 000000000..64993d149
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0226.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  tb0226.h, Include file for TANBAC TB0226.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __TANBAC_TB0226_H
+#define __TANBAC_TB0226_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define GD82559_1_PIN                   2
+#define GD82559_2_PIN                   3
+#define UPD720100_INTA_PIN              4
+#define UPD720100_INTB_PIN              8
+#define UPD720100_INTC_PIN              13
+
+/*
+ * Interrupt Number
+ */
+#define GD82559_1_IRQ                   GIU_IRQ(GD82559_1_PIN)
+#define GD82559_2_IRQ                   GIU_IRQ(GD82559_2_PIN)
+#define UPD720100_INTA_IRQ              GIU_IRQ(UPD720100_INTA_PIN)
+#define UPD720100_INTB_IRQ              GIU_IRQ(UPD720100_INTB_PIN)
+#define UPD720100_INTC_IRQ              GIU_IRQ(UPD720100_INTC_PIN)
+
+#endif /* __TANBAC_TB0226_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h
new file mode 100644
index 000000000..3ddc91386
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0287.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
+ *
+ *  Copyright (C) 2005  Media Lab Inc. <ito@mlb.co.jp>
+ *
+ *  This code is largely based on tb0219.h.
+ */
+#ifndef __TANBAC_TB0287_H
+#define __TANBAC_TB0287_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define TB0287_PCI_SLOT_PIN             2
+#define TB0287_SM501_PIN                3
+#define TB0287_SIL680A_PIN              8
+#define TB0287_RTL8110_PIN              13
+
+/*
+ * Interrupt Number
+ */
+#define TB0287_PCI_SLOT_IRQ             GIU_IRQ(TB0287_PCI_SLOT_PIN)
+#define TB0287_SM501_IRQ                GIU_IRQ(TB0287_SM501_PIN)
+#define TB0287_SIL680A_IRQ              GIU_IRQ(TB0287_SIL680A_PIN)
+#define TB0287_RTL8110_IRQ              GIU_IRQ(TB0287_RTL8110_PIN)
+
+#endif /* __TANBAC_TB0287_H */
diff --git a/arch/mips/include/asm/vr41xx/vr41xx.h b/arch/mips/include/asm/vr41xx/vr41xx.h
new file mode 100644
index 000000000..9a4b36b75
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/vr41xx.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * include/asm-mips/vr41xx/vr41xx.h
+ *
+ * Include file for NEC VR4100 series.
+ *
+ * Copyright (C) 1999 Michael Klar
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+ * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#ifndef __NEC_VR41XX_H
+#define __NEC_VR41XX_H
+
+#include <linux/interrupt.h>
+
+/*
+ * CPU Revision
+ */
+/* VR4122 0x00000c70-0x00000c72 */
+#define PRID_VR4122_REV1_0      0x00000c70
+#define PRID_VR4122_REV2_0      0x00000c70
+#define PRID_VR4122_REV2_1      0x00000c70
+#define PRID_VR4122_REV3_0      0x00000c71
+#define PRID_VR4122_REV3_1      0x00000c72
+
+/* VR4181A 0x00000c73-0x00000c7f */
+#define PRID_VR4181A_REV1_0     0x00000c73
+#define PRID_VR4181A_REV1_1     0x00000c74
+
+/* VR4131 0x00000c80-0x00000c83 */
+#define PRID_VR4131_REV1_2      0x00000c80
+#define PRID_VR4131_REV2_0      0x00000c81
+#define PRID_VR4131_REV2_1      0x00000c82
+#define PRID_VR4131_REV2_2      0x00000c83
+
+/* VR4133 0x00000c84- */
+#define PRID_VR4133             0x00000c84
+
+/*
+ * Bus Control Uint
+ */
+extern unsigned long vr41xx_calculate_clock_frequency(void);
+extern unsigned long vr41xx_get_vtclock_frequency(void);
+extern unsigned long vr41xx_get_tclock_frequency(void);
+
+/*
+ * Clock Mask Unit
+ */
+typedef enum {
+        PIU_CLOCK,
+        SIU_CLOCK,
+        AIU_CLOCK,
+        KIU_CLOCK,
+        FIR_CLOCK,
+        DSIU_CLOCK,
+        CSI_CLOCK,
+        PCIU_CLOCK,
+        HSP_CLOCK,
+        PCI_CLOCK,
+        CEU_CLOCK,
+        ETHER0_CLOCK,
+        ETHER1_CLOCK
+} vr41xx_clock_t;
+
+extern void vr41xx_supply_clock(vr41xx_clock_t clock);
+extern void vr41xx_mask_clock(vr41xx_clock_t clock);
+
+/*
+ * Interrupt Control Unit
+ */
+extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
+extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
+
+#define PIUINT_COMMAND          0x0040
+#define PIUINT_DATA             0x0020
+#define PIUINT_PAGE1            0x0010
+#define PIUINT_PAGE0            0x0008
+#define PIUINT_DATALOST         0x0004
+#define PIUINT_STATUSCHANGE     0x0001
+
+extern void vr41xx_enable_piuint(uint16_t mask);
+extern void vr41xx_disable_piuint(uint16_t mask);
+
+#define AIUINT_INPUT_DMAEND     0x0800
+#define AIUINT_INPUT_DMAHALT    0x0400
+#define AIUINT_INPUT_DATALOST   0x0200
+#define AIUINT_INPUT_DATA       0x0100
+#define AIUINT_OUTPUT_DMAEND    0x0008
+#define AIUINT_OUTPUT_DMAHALT   0x0004
+#define AIUINT_OUTPUT_NODATA    0x0002
+
+extern void vr41xx_enable_aiuint(uint16_t mask);
+extern void vr41xx_disable_aiuint(uint16_t mask);
+
+#define KIUINT_DATALOST         0x0004
+#define KIUINT_DATAREADY        0x0002
+#define KIUINT_SCAN             0x0001
+
+extern void vr41xx_enable_kiuint(uint16_t mask);
+extern void vr41xx_disable_kiuint(uint16_t mask);
+
+#define DSIUINT_CTS             0x0800
+#define DSIUINT_RXERR           0x0400
+#define DSIUINT_RX              0x0200
+#define DSIUINT_TX              0x0100
+#define DSIUINT_ALL             0x0f00
+
+extern void vr41xx_enable_dsiuint(uint16_t mask);
+extern void vr41xx_disable_dsiuint(uint16_t mask);
+
+#define FIRINT_UNIT             0x0010
+#define FIRINT_RX_DMAEND        0x0008
+#define FIRINT_RX_DMAHALT       0x0004
+#define FIRINT_TX_DMAEND        0x0002
+#define FIRINT_TX_DMAHALT       0x0001
+
+extern void vr41xx_enable_firint(uint16_t mask);
+extern void vr41xx_disable_firint(uint16_t mask);
+
+extern void vr41xx_enable_pciint(void);
+extern void vr41xx_disable_pciint(void);
+
+extern void vr41xx_enable_scuint(void);
+extern void vr41xx_disable_scuint(void);
+
+#define CSIINT_TX_DMAEND        0x0040
+#define CSIINT_TX_DMAHALT       0x0020
+#define CSIINT_TX_DATA          0x0010
+#define CSIINT_TX_FIFOEMPTY     0x0008
+#define CSIINT_RX_DMAEND        0x0004
+#define CSIINT_RX_DMAHALT       0x0002
+#define CSIINT_RX_FIFOEMPTY     0x0001
+
+extern void vr41xx_enable_csiint(uint16_t mask);
+extern void vr41xx_disable_csiint(uint16_t mask);
+
+extern void vr41xx_enable_bcuint(void);
+extern void vr41xx_disable_bcuint(void);
+
+#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
+extern void vr41xx_siu_setup(void);
+#else
+static inline void vr41xx_siu_setup(void) {}
+#endif
+
+#endif /* __NEC_VR41XX_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
new file mode 100644
index 000000000..21443f096
--- /dev/null
+++ b/arch/mips/include/asm/war.h
@@ -0,0 +1,73 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_WAR_H
+#define _ASM_WAR_H
+
+/*
+ * Work around certain R4000 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #28
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #19
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed while an integer multiplication is in progress:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   errata #16 & #28
+ *
+ * - An integer division may give an incorrect result if started in
+ *   a delay slot of a taken branch or a jump:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #52
+ */
+#ifdef CONFIG_CPU_R4000_WORKAROUNDS
+#define R4000_WAR 1
+#else
+#define R4000_WAR 0
+#endif
+
+/*
+ * Work around certain R4400 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
+ *   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
+ */
+#ifdef CONFIG_CPU_R4400_WORKAROUNDS
+#define R4400_WAR 1
+#else
+#define R4400_WAR 0
+#endif
+
+/*
+ * Work around the "daddi" and "daddiu" CPU errata:
+ *
+ * - The `daddi' instruction fails to trap on overflow.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #23
+ *
+ * - The `daddiu' instruction can produce an incorrect result.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #41
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #15
+ *   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
+ */
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+#define DADDI_WAR 1
+#else
+#define DADDI_WAR 0
+#endif
+
+#endif /* _ASM_WAR_H */
diff --git a/arch/mips/include/asm/watch.h b/arch/mips/include/asm/watch.h
new file mode 100644
index 000000000..6ffe3eadf
--- /dev/null
+++ b/arch/mips/include/asm/watch.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 David Daney
+ */
+#ifndef _ASM_WATCH_H
+#define _ASM_WATCH_H
+
+#include <linux/bitops.h>
+
+#include <asm/mipsregs.h>
+
+void mips_install_watch_registers(struct task_struct *t);
+void mips_read_watch_registers(void);
+void mips_clear_watch_registers(void);
+void mips_probe_watch_registers(struct cpuinfo_mips *c);
+
+#ifdef CONFIG_HARDWARE_WATCHPOINTS
+#define __restore_watch(task) do {                                      \
+        if (unlikely(test_bit(TIF_LOAD_WATCH,                           \
+                              &task_thread_info(task)->flags))) {       \
+                mips_install_watch_registers(task);                     \
+        }                                                               \
+} while (0)
+
+#else
+#define __restore_watch(task) do {} while (0)
+#endif
+
+#endif /* _ASM_WATCH_H */
diff --git a/arch/mips/include/asm/wbflush.h b/arch/mips/include/asm/wbflush.h
new file mode 100644
index 000000000..eadc0ac47
--- /dev/null
+++ b/arch/mips/include/asm/wbflush.h
@@ -0,0 +1,34 @@
+/*
+ * Header file for using the wbflush routine
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef _ASM_WBFLUSH_H
+#define _ASM_WBFLUSH_H
+
+
+#ifdef CONFIG_CPU_HAS_WB
+
+extern void (*__wbflush)(void);
+extern void wbflush_setup(void);
+
+#define wbflush()                       \
+        do {                            \
+                __sync();               \
+                __wbflush();            \
+        } while (0)
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wbflush_setup() do { } while (0)
+
+#define wbflush() fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#endif /* _ASM_WBFLUSH_H */
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
new file mode 100644
index 000000000..680e7efeb
--- /dev/null
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xtalk.h -- platform-independent crosstalk interface, derived from
+ * IRIX <sys/PCI/bridge.h>, revision 1.38.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XTALK_H
+#define _ASM_XTALK_XTALK_H
+
+#ifndef __ASSEMBLY__
+/*
+ * User-level device driver visible types
+ */
+typedef char            xwidgetnum_t;   /* xtalk widget number  (0..15) */
+
+#define XWIDGET_NONE            -1
+
+typedef int xwidget_part_num_t; /* xtalk widget part number */
+
+#define XWIDGET_PART_NUM_NONE   -1
+
+typedef int             xwidget_rev_num_t;      /* xtalk widget revision number */
+
+#define XWIDGET_REV_NUM_NONE    -1
+
+typedef int xwidget_mfg_num_t;  /* xtalk widget manufacturing ID */
+
+#define XWIDGET_MFG_NUM_NONE    -1
+
+typedef struct xtalk_piomap_s *xtalk_piomap_t;
+
+/* It is often convenient to fold the XIO target port
+ * number into the XIO address.
+ */
+#define XIO_NOWHERE     (0xFFFFFFFFFFFFFFFFull)
+#define XIO_ADDR_BITS   (0x0000FFFFFFFFFFFFull)
+#define XIO_PORT_BITS   (0xF000000000000000ull)
+#define XIO_PORT_SHIFT  (60)
+
+#define XIO_PACKED(x)   (((x)&XIO_PORT_BITS) != 0)
+#define XIO_ADDR(x)     ((x)&XIO_ADDR_BITS)
+#define XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
+#define XIO_PACK(p, o)  ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/asm/xtalk/xwidget.h b/arch/mips/include/asm/xtalk/xwidget.h
new file mode 100644
index 000000000..24f121da6
--- /dev/null
+++ b/arch/mips/include/asm/xtalk/xwidget.h
@@ -0,0 +1,279 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xwidget.h - generic crosstalk widget header file, derived from IRIX
+ * <sys/xtalk/xtalkwidget.h>, revision 1.32.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XWIDGET_H
+#define _ASM_XTALK_XWIDGET_H
+
+#include <linux/types.h>
+#include <asm/xtalk/xtalk.h>
+
+#define WIDGET_ID                       0x04
+#define WIDGET_STATUS                   0x0c
+#define WIDGET_ERR_UPPER_ADDR           0x14
+#define WIDGET_ERR_LOWER_ADDR           0x1c
+#define WIDGET_CONTROL                  0x24
+#define WIDGET_REQ_TIMEOUT              0x2c
+#define WIDGET_INTDEST_UPPER_ADDR       0x34
+#define WIDGET_INTDEST_LOWER_ADDR       0x3c
+#define WIDGET_ERR_CMD_WORD             0x44
+#define WIDGET_LLP_CFG                  0x4c
+#define WIDGET_TFLUSH                   0x54
+
+/* WIDGET_ID */
+#define WIDGET_REV_NUM                  0xf0000000
+#define WIDGET_PART_NUM                 0x0ffff000
+#define WIDGET_MFG_NUM                  0x00000ffe
+#define WIDGET_REV_NUM_SHFT             28
+#define WIDGET_PART_NUM_SHFT            12
+#define WIDGET_MFG_NUM_SHFT             1
+
+#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
+#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
+#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
+
+/* WIDGET_STATUS */
+#define WIDGET_LLP_REC_CNT              0xff000000
+#define WIDGET_LLP_TX_CNT               0x00ff0000
+#define WIDGET_PENDING                  0x0000001f
+
+/* WIDGET_ERR_UPPER_ADDR */
+#define WIDGET_ERR_UPPER_ADDR_ONLY      0x0000ffff
+
+/* WIDGET_CONTROL */
+#define WIDGET_F_BAD_PKT                0x00010000
+#define WIDGET_LLP_XBAR_CRD             0x0000f000
+#define WIDGET_LLP_XBAR_CRD_SHFT        12
+#define WIDGET_CLR_RLLP_CNT             0x00000800
+#define WIDGET_CLR_TLLP_CNT             0x00000400
+#define WIDGET_SYS_END                  0x00000200
+#define WIDGET_MAX_TRANS                0x000001f0
+#define WIDGET_WIDGET_ID                0x0000000f
+
+/* WIDGET_INTDEST_UPPER_ADDR */
+#define WIDGET_INT_VECTOR               0xff000000
+#define WIDGET_INT_VECTOR_SHFT          24
+#define WIDGET_TARGET_ID                0x000f0000
+#define WIDGET_TARGET_ID_SHFT           16
+#define WIDGET_UPP_ADDR                 0x0000ffff
+
+/* WIDGET_ERR_CMD_WORD */
+#define WIDGET_DIDN                     0xf0000000
+#define WIDGET_SIDN                     0x0f000000
+#define WIDGET_PACTYP                   0x00f00000
+#define WIDGET_TNUM                     0x000f8000
+#define WIDGET_COHERENT                 0x00004000
+#define WIDGET_DS                       0x00003000
+#define WIDGET_GBR                      0x00000800
+#define WIDGET_VBPM                     0x00000400
+#define WIDGET_ERROR                    0x00000200
+#define WIDGET_BARRIER                  0x00000100
+
+/* WIDGET_LLP_CFG */
+#define WIDGET_LLP_MAXRETRY             0x03ff0000
+#define WIDGET_LLP_MAXRETRY_SHFT        16
+#define WIDGET_LLP_NULLTIMEOUT          0x0000fc00
+#define WIDGET_LLP_NULLTIMEOUT_SHFT     10
+#define WIDGET_LLP_MAXBURST             0x000003ff
+#define WIDGET_LLP_MAXBURST_SHFT        0
+
+/* Xtalk Widget Device Mfgr Nums */
+#define WIDGET_XBOW_MFGR_NUM    0x0      /* IP30 XBow Chip */
+#define WIDGET_XXBOW_MFGR_NUM   0x0      /* IP35 Xbow + XBridge Chip */
+#define WIDGET_ODYS_MFGR_NUM    0x023    /* Odyssey / VPro GFX */
+#define WIDGET_TPU_MFGR_NUM     0x024    /* Tensor Processor Unit */
+#define WIDGET_XBRDG_MFGR_NUM   0x024    /* IP35 XBridge Chip */
+#define WIDGET_HEART_MFGR_NUM   0x036    /* IP30 HEART Chip */
+#define WIDGET_BRIDG_MFGR_NUM   0x036    /* PCI Bridge */
+#define WIDGET_HUB_MFGR_NUM     0x036    /* IP27 Hub Chip */
+#define WIDGET_BDRCK_MFGR_NUM   0x036    /* IP35 Bedrock Chip */
+#define WIDGET_IMPCT_MFGR_NUM   0x2aa    /* HQ4 / Impact GFX */
+#define WIDGET_KONA_MFGR_NUM    0x2aa    /* InfiniteReality3 / Kona GFX */
+#define WIDGET_NULL_MFGR_NUM    -1       /* NULL */
+
+/* Xtalk Widget Device Part Nums */
+#define WIDGET_XBOW_PART_NUM    0x0000
+#define WIDGET_HEART_PART_NUM   0xc001
+#define WIDGET_BRIDG_PART_NUM   0xc002
+#define WIDGET_IMPCT_PART_NUM   0xc003
+#define WIDGET_ODYS_PART_NUM    0xc013
+#define WIDGET_HUB_PART_NUM     0xc101
+#define WIDGET_KONA_PART_NUM    0xc102
+#define WIDGET_BDRCK_PART_NUM   0xc110
+#define WIDGET_TPU_PART_NUM     0xc202
+#define WIDGET_XXBOW_PART_NUM   0xd000
+#define WIDGET_XBRDG_PART_NUM   0xd002
+#define WIDGET_NULL_PART_NUM    -1
+
+/* For Xtalk Widget identification */
+struct widget_ident {
+        u32 mfgr;
+        u32 part;
+        char *name;
+        char *revs[16];
+};
+
+/* Known Xtalk Widgets */
+static const struct widget_ident __initconst widget_idents[] = {
+        {
+                WIDGET_XBOW_MFGR_NUM,
+                WIDGET_XBOW_PART_NUM,
+                "xbow",
+                {NULL, "1.0", "1.1", "1.2", "1.3", "2.0", NULL},
+        },
+        {
+                WIDGET_HEART_MFGR_NUM,
+                WIDGET_HEART_PART_NUM,
+                "heart",
+                {NULL, "A", "B", "C", "D", "E", "F", NULL},
+        },
+        {
+                WIDGET_BRIDG_MFGR_NUM,
+                WIDGET_BRIDG_PART_NUM,
+                "bridge",
+                {NULL, "A", "B", "C", "D", NULL},
+        },
+        {
+                WIDGET_IMPCT_MFGR_NUM,
+                WIDGET_IMPCT_PART_NUM,
+                "impact",
+                {NULL, "A", "B", NULL},
+        },
+        {
+                WIDGET_ODYS_MFGR_NUM,
+                WIDGET_ODYS_PART_NUM,
+                "odyssey",
+                {NULL, "A", "B", NULL},
+        },
+        {
+                WIDGET_HUB_MFGR_NUM,
+                WIDGET_HUB_PART_NUM,
+                "hub",
+                {NULL, "1.0", "2.0", "2.1", "2.2", "2.3", "2.4", NULL},
+        },
+        {
+                WIDGET_KONA_MFGR_NUM,
+                WIDGET_KONA_PART_NUM,
+                "kona",
+                {NULL},
+        },
+        {
+                WIDGET_BDRCK_MFGR_NUM,
+                WIDGET_BDRCK_PART_NUM,
+                "bedrock",
+                {NULL, "1.0", "1.1", NULL},
+        },
+        {
+                WIDGET_TPU_MFGR_NUM,
+                WIDGET_TPU_PART_NUM,
+                "tpu",
+                {"0", NULL},
+        },
+        {
+                WIDGET_XXBOW_MFGR_NUM,
+                WIDGET_XXBOW_PART_NUM,
+                "xxbow",
+                {NULL, "1.0", "2.0", NULL},
+        },
+        {
+                WIDGET_XBRDG_MFGR_NUM,
+                WIDGET_XBRDG_PART_NUM,
+                "xbridge",
+                {NULL, "A", "B", NULL},
+        },
+        {
+                WIDGET_NULL_MFGR_NUM,
+                WIDGET_NULL_PART_NUM,
+                NULL,
+                {NULL},
+        }
+};
+
+/*
+ * according to the crosstalk spec, only 32-bits access to the widget
+ * configuration registers is allowed.  some widgets may allow 64-bits
+ * access but software should not depend on it.  registers beyond the
+ * widget target flush register are widget dependent thus will not be
+ * defined here
+ */
+#ifndef __ASSEMBLY__
+typedef u32 widgetreg_t;
+
+/* widget configuration registers */
+typedef volatile struct widget_cfg {
+        widgetreg_t             w_pad_0;                /* 0x00 */
+        widgetreg_t             w_id;                   /* 0x04 */
+        widgetreg_t             w_pad_1;                /* 0x08 */
+        widgetreg_t             w_status;               /* 0x0c */
+        widgetreg_t             w_pad_2;                /* 0x10 */
+        widgetreg_t             w_err_upper_addr;       /* 0x14 */
+        widgetreg_t             w_pad_3;                /* 0x18 */
+        widgetreg_t             w_err_lower_addr;       /* 0x1c */
+        widgetreg_t             w_pad_4;                /* 0x20 */
+        widgetreg_t             w_control;              /* 0x24 */
+        widgetreg_t             w_pad_5;                /* 0x28 */
+        widgetreg_t             w_req_timeout;          /* 0x2c */
+        widgetreg_t             w_pad_6;                /* 0x30 */
+        widgetreg_t             w_intdest_upper_addr;   /* 0x34 */
+        widgetreg_t             w_pad_7;                /* 0x38 */
+        widgetreg_t             w_intdest_lower_addr;   /* 0x3c */
+        widgetreg_t             w_pad_8;                /* 0x40 */
+        widgetreg_t             w_err_cmd_word;         /* 0x44 */
+        widgetreg_t             w_pad_9;                /* 0x48 */
+        widgetreg_t             w_llp_cfg;              /* 0x4c */
+        widgetreg_t             w_pad_10;               /* 0x50 */
+        widgetreg_t             w_tflush;               /* 0x54 */
+} widget_cfg_t;
+
+typedef struct {
+        unsigned        didn:4;
+        unsigned        sidn:4;
+        unsigned        pactyp:4;
+        unsigned        tnum:5;
+        unsigned        ct:1;
+        unsigned        ds:2;
+        unsigned        gbr:1;
+        unsigned        vbpm:1;
+        unsigned        error:1;
+        unsigned        bo:1;
+        unsigned        other:8;
+} w_err_cmd_word_f;
+
+typedef union {
+        widgetreg_t             r;
+        w_err_cmd_word_f        f;
+} w_err_cmd_word_u;
+
+typedef struct xwidget_info_s *xwidget_info_t;
+
+/*
+ * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
+ */
+typedef struct xwidget_hwid_s {
+        xwidget_part_num_t      part_num;
+        xwidget_rev_num_t       rev_num;
+        xwidget_mfg_num_t       mfg_num;
+} *xwidget_hwid_t;
+
+
+/*
+ * Returns 1 if a driver that handles devices described by hwid1 is able
+ * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
+ * numbers at all.
+ */
+#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
+        (((hwid1)->part_num == (hwid2)->part_num) && \
+        (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid1)->mfg_num == (hwid2)->mfg_num)))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XWIDGET_H */
diff --git a/arch/mips/include/asm/yamon-dt.h b/arch/mips/include/asm/yamon-dt.h
new file mode 100644
index 000000000..e20475540
--- /dev/null
+++ b/arch/mips/include/asm/yamon-dt.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MIPS_ASM_YAMON_DT_H__
+#define __MIPS_ASM_YAMON_DT_H__
+
+#include <linux/types.h>
+
+/**
+ * struct yamon_mem_region - Represents a contiguous range of physical RAM.
+ * @start:      Start physical address.
+ * @size:       Maximum size of region.
+ * @discard:    Length of additional memory to discard after the region.
+ */
+struct yamon_mem_region {
+        phys_addr_t     start;
+        phys_addr_t     size;
+        phys_addr_t     discard;
+};
+
+/**
+ * yamon_dt_append_cmdline() - Append YAMON-provided command line to /chosen
+ * @fdt: the FDT blob
+ *
+ * Write the YAMON-provided command line to the bootargs property of the
+ * /chosen node in @fdt.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_append_cmdline(void *fdt);
+
+/**
+ * yamon_dt_append_memory() - Append YAMON-provided memory info to /memory
+ * @fdt:        the FDT blob
+ * @regions:    zero size terminated array of physical memory regions
+ *
+ * Generate a /memory node in @fdt based upon memory size information provided
+ * by YAMON in its environment and the @regions array.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_append_memory(void *fdt,
+                                        const struct yamon_mem_region *regions);
+
+/**
+ * yamon_dt_serial_config() - Append YAMON-provided serial config to /chosen
+ * @fdt: the FDT blob
+ *
+ * Generate a stdout-path property in the /chosen node of @fdt, based upon
+ * information provided in the YAMON environment about the UART configuration
+ * of the system.
+ *
+ * Return: 0 on success, else -errno
+ */
+extern __init int yamon_dt_serial_config(void *fdt);
+
+#endif /* __MIPS_ASM_YAMON_DT_H__ */
diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
new file mode 100644
index 000000000..6db08385d
--- /dev/null
+++ b/arch/mips/include/uapi/asm/Kbuild
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+generated-y += unistd_n32.h
+generated-y += unistd_n64.h
+generated-y += unistd_o32.h
+generated-y += unistd_nr_n32.h
+generated-y += unistd_nr_n64.h
+generated-y += unistd_nr_o32.h
+
+generic-y += kvm_para.h
diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h
new file mode 100644
index 000000000..612c2c41f
--- /dev/null
+++ b/arch/mips/include/uapi/asm/auxvec.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_AUXVEC_H
+#define __ASM_AUXVEC_H
+
+/* Location of VDSO image. */
+#define AT_SYSINFO_EHDR         33
+
+#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
+
+#endif /* __ASM_AUXVEC_H */
diff --git a/arch/mips/include/uapi/asm/bitfield.h b/arch/mips/include/uapi/asm/bitfield.h
new file mode 100644
index 000000000..b11713d87
--- /dev/null
+++ b/arch/mips/include/uapi/asm/bitfield.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __UAPI_ASM_BITFIELD_H
+#define __UAPI_ASM_BITFIELD_H
+
+/*
+ *  * Damn ...  bitfields depend from byteorder :-(
+ *   */
+#ifdef __MIPSEB__
+#define __BITFIELD_FIELD(field, more)                                   \
+        field;                                                          \
+        more
+
+#elif defined(__MIPSEL__)
+
+#define __BITFIELD_FIELD(field, more)                                   \
+        more                                                            \
+        field;
+
+#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
+#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
+#endif
+
+#endif /* __UAPI_ASM_BITFIELD_H */
diff --git a/arch/mips/include/uapi/asm/bitsperlong.h b/arch/mips/include/uapi/asm/bitsperlong.h
new file mode 100644
index 000000000..7268380d8
--- /dev/null
+++ b/arch/mips/include/uapi/asm/bitsperlong.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __ASM_MIPS_BITSPERLONG_H
+#define __ASM_MIPS_BITSPERLONG_H
+
+#define __BITS_PER_LONG _MIPS_SZLONG
+
+#include <asm-generic/bitsperlong.h>
+
+#endif /* __ASM_MIPS_BITSPERLONG_H */
diff --git a/arch/mips/include/uapi/asm/break.h b/arch/mips/include/uapi/asm/break.h
new file mode 100644
index 000000000..10380b1bc
--- /dev/null
+++ b/arch/mips/include/uapi/asm/break.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef __UAPI_ASM_BREAK_H
+#define __UAPI_ASM_BREAK_H
+
+/*
+ * The following break codes are or were in use for specific purposes in
+ * other MIPS operating systems.  Linux/MIPS doesn't use all of them.  The
+ * unused ones are here as placeholders; we might encounter them in
+ * non-Linux/MIPS object files or make use of them in the future.
+ */
+#define BRK_USERBP      0       /* User bp (used by debuggers) */
+#define BRK_SSTEPBP     5       /* User bp (used by debuggers) */
+#define BRK_OVERFLOW    6       /* Overflow check */
+#define BRK_DIVZERO     7       /* Divide by zero check */
+#define BRK_RANGE       8       /* Range error check */
+#define BRK_BUG         12      /* Used by BUG() */
+#define BRK_UPROBE      13      /* See <asm/uprobes.h> */
+#define BRK_UPROBE_XOL  14      /* See <asm/uprobes.h> */
+#define BRK_MEMU        514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP   515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516  /* Kprobe single step software implementation */
+#define BRK_MULOVF      1023    /* Multiply overflow */
+
+#endif /* __UAPI_ASM_BREAK_H */
diff --git a/arch/mips/include/uapi/asm/byteorder.h b/arch/mips/include/uapi/asm/byteorder.h
new file mode 100644
index 000000000..b4edc85f9
--- /dev/null
+++ b/arch/mips/include/uapi/asm/byteorder.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#if defined(__MIPSEB__)
+#include <linux/byteorder/big_endian.h>
+#elif defined(__MIPSEL__)
+#include <linux/byteorder/little_endian.h>
+#else
+# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/uapi/asm/cachectl.h b/arch/mips/include/uapi/asm/cachectl.h
new file mode 100644
index 000000000..af7639ff4
--- /dev/null
+++ b/arch/mips/include/uapi/asm/cachectl.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE  (1<<0)          /* flush instruction cache        */
+#define DCACHE  (1<<1)          /* writeback and flush data cache */
+#define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE       0       /* make pages cacheable */
+#define UNCACHEABLE     1       /* make pages uncacheable */
+
+#endif  /* _ASM_CACHECTL */
diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h
new file mode 100644
index 000000000..2fb714e2d
--- /dev/null
+++ b/arch/mips/include/uapi/asm/errno.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
+ */
+#ifndef _UAPI_ASM_ERRNO_H
+#define _UAPI_ASM_ERRNO_H
+
+/*
+ * These error numbers are intended to be MIPS ABI compatible
+ */
+
+#include <asm-generic/errno-base.h>
+
+#define ENOMSG          35      /* No message of desired type */
+#define EIDRM           36      /* Identifier removed */
+#define ECHRNG          37      /* Channel number out of range */
+#define EL2NSYNC        38      /* Level 2 not synchronized */
+#define EL3HLT          39      /* Level 3 halted */
+#define EL3RST          40      /* Level 3 reset */
+#define ELNRNG          41      /* Link number out of range */
+#define EUNATCH         42      /* Protocol driver not attached */
+#define ENOCSI          43      /* No CSI structure available */
+#define EL2HLT          44      /* Level 2 halted */
+#define EDEADLK         45      /* Resource deadlock would occur */
+#define ENOLCK          46      /* No record locks available */
+#define EBADE           50      /* Invalid exchange */
+#define EBADR           51      /* Invalid request descriptor */
+#define EXFULL          52      /* Exchange full */
+#define ENOANO          53      /* No anode */
+#define EBADRQC         54      /* Invalid request code */
+#define EBADSLT         55      /* Invalid slot */
+#define EDEADLOCK       56      /* File locking deadlock error */
+#define EBFONT          59      /* Bad font file format */
+#define ENOSTR          60      /* Device not a stream */
+#define ENODATA         61      /* No data available */
+#define ETIME           62      /* Timer expired */
+#define ENOSR           63      /* Out of streams resources */
+#define ENONET          64      /* Machine is not on the network */
+#define ENOPKG          65      /* Package not installed */
+#define EREMOTE         66      /* Object is remote */
+#define ENOLINK         67      /* Link has been severed */
+#define EADV            68      /* Advertise error */
+#define ESRMNT          69      /* Srmount error */
+#define ECOMM           70      /* Communication error on send */
+#define EPROTO          71      /* Protocol error */
+#define EDOTDOT         73      /* RFS specific error */
+#define EMULTIHOP       74      /* Multihop attempted */
+#define EBADMSG         77      /* Not a data message */
+#define ENAMETOOLONG    78      /* File name too long */
+#define EOVERFLOW       79      /* Value too large for defined data type */
+#define ENOTUNIQ        80      /* Name not unique on network */
+#define EBADFD          81      /* File descriptor in bad state */
+#define EREMCHG         82      /* Remote address changed */
+#define ELIBACC         83      /* Can not access a needed shared library */
+#define ELIBBAD         84      /* Accessing a corrupted shared library */
+#define ELIBSCN         85      /* .lib section in a.out corrupted */
+#define ELIBMAX         86      /* Attempting to link in too many shared libraries */
+#define ELIBEXEC        87      /* Cannot exec a shared library directly */
+#define EILSEQ          88      /* Illegal byte sequence */
+#define ENOSYS          89      /* Function not implemented */
+#define ELOOP           90      /* Too many symbolic links encountered */
+#define ERESTART        91      /* Interrupted system call should be restarted */
+#define ESTRPIPE        92      /* Streams pipe error */
+#define ENOTEMPTY       93      /* Directory not empty */
+#define EUSERS          94      /* Too many users */
+#define ENOTSOCK        95      /* Socket operation on non-socket */
+#define EDESTADDRREQ    96      /* Destination address required */
+#define EMSGSIZE        97      /* Message too long */
+#define EPROTOTYPE      98      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     99      /* Protocol not available */
+#define EPROTONOSUPPORT 120     /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121     /* Socket type not supported */
+#define EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT    123     /* Protocol family not supported */
+#define EAFNOSUPPORT    124     /* Address family not supported by protocol */
+#define EADDRINUSE      125     /* Address already in use */
+#define EADDRNOTAVAIL   126     /* Cannot assign requested address */
+#define ENETDOWN        127     /* Network is down */
+#define ENETUNREACH     128     /* Network is unreachable */
+#define ENETRESET       129     /* Network dropped connection because of reset */
+#define ECONNABORTED    130     /* Software caused connection abort */
+#define ECONNRESET      131     /* Connection reset by peer */
+#define ENOBUFS         132     /* No buffer space available */
+#define EISCONN         133     /* Transport endpoint is already connected */
+#define ENOTCONN        134     /* Transport endpoint is not connected */
+#define EUCLEAN         135     /* Structure needs cleaning */
+#define ENOTNAM         137     /* Not a XENIX named type file */
+#define ENAVAIL         138     /* No XENIX semaphores available */
+#define EISNAM          139     /* Is a named type file */
+#define EREMOTEIO       140     /* Remote I/O error */
+#define EINIT           141     /* Reserved */
+#define EREMDEV         142     /* Error 142 */
+#define ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS    144     /* Too many references: cannot splice */
+#define ETIMEDOUT       145     /* Connection timed out */
+#define ECONNREFUSED    146     /* Connection refused */
+#define EHOSTDOWN       147     /* Host is down */
+#define EHOSTUNREACH    148     /* No route to host */
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EALREADY        149     /* Operation already in progress */
+#define EINPROGRESS     150     /* Operation now in progress */
+#define ESTALE          151     /* Stale file handle */
+#define ECANCELED       158     /* AIO operation canceled */
+
+/*
+ * These error are Linux extensions.
+ */
+#define ENOMEDIUM       159     /* No medium found */
+#define EMEDIUMTYPE     160     /* Wrong medium type */
+#define ENOKEY          161     /* Required key not available */
+#define EKEYEXPIRED     162     /* Key has expired */
+#define EKEYREVOKED     163     /* Key has been revoked */
+#define EKEYREJECTED    164     /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD      165     /* Owner died */
+#define ENOTRECOVERABLE 166     /* State not recoverable */
+
+#define ERFKILL         167     /* Operation not possible due to RF-kill */
+
+#define EHWPOISON       168     /* Memory page has hardware error */
+
+#define EDQUOT          1133    /* Quota exceeded */
+
+
+#endif /* _UAPI_ASM_ERRNO_H */
diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h
new file mode 100644
index 000000000..42e13dead
--- /dev/null
+++ b/arch/mips/include/uapi/asm/fcntl.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
+ */
+#ifndef _UAPI_ASM_FCNTL_H
+#define _UAPI_ASM_FCNTL_H
+
+#include <asm/sgidefs.h>
+
+#define O_APPEND        0x0008
+#define O_DSYNC         0x0010  /* used to be O_SYNC, see below */
+#define O_NONBLOCK      0x0080
+#define O_CREAT         0x0100  /* not fcntl */
+#define O_TRUNC         0x0200  /* not fcntl */
+#define O_EXCL          0x0400  /* not fcntl */
+#define O_NOCTTY        0x0800  /* not fcntl */
+#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
+#define O_LARGEFILE     0x2000  /* allow large file opens */
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        0x4000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
+#define O_DIRECT        0x8000  /* direct disk access hint */
+
+#define F_GETLK         14
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        24      /*  for sockets. */
+#define F_GETOWN        23      /*  for sockets. */
+
+#ifndef __mips64
+#define F_GETLK64       33      /*  using 'struct flock64' */
+#define F_SETLK64       34
+#define F_SETLKW64      35
+#endif
+
+/*
+ * The flavours of struct flock.  "struct flock" is the ABI compliant
+ * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
+ * a historic accident and inconsistence with the ABI definition it doesn't
+ * contain all the same fields as struct flock.
+ */
+
+#if _MIPS_SIM != _MIPS_SIM_ABI64
+
+#include <linux/types.h>
+
+struct flock {
+        short   l_type;
+        short   l_whence;
+        __kernel_off_t  l_start;
+        __kernel_off_t  l_len;
+        long    l_sysid;
+        __kernel_pid_t l_pid;
+        long    pad[4];
+};
+
+#define HAVE_ARCH_STRUCT_FLOCK
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _UAPI_ASM_FCNTL_H */
diff --git a/arch/mips/include/uapi/asm/hwcap.h b/arch/mips/include/uapi/asm/hwcap.h
new file mode 100644
index 000000000..b7e02bdc1
--- /dev/null
+++ b/arch/mips/include/uapi/asm/hwcap.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_ASM_HWCAP_H
+#define _UAPI_ASM_HWCAP_H
+
+/* HWCAP flags */
+#define HWCAP_MIPS_R6           (1 << 0)
+#define HWCAP_MIPS_MSA          (1 << 1)
+#define HWCAP_MIPS_CRC32        (1 << 2)
+#define HWCAP_MIPS_MIPS16       (1 << 3)
+#define HWCAP_MIPS_MDMX     (1 << 4)
+#define HWCAP_MIPS_MIPS3D   (1 << 5)
+#define HWCAP_MIPS_SMARTMIPS (1 << 6)
+#define HWCAP_MIPS_DSP      (1 << 7)
+#define HWCAP_MIPS_DSP2     (1 << 8)
+#define HWCAP_MIPS_DSP3     (1 << 9)
+#define HWCAP_MIPS_MIPS16E2 (1 << 10)
+#define HWCAP_LOONGSON_MMI  (1 << 11)
+#define HWCAP_LOONGSON_EXT  (1 << 12)
+#define HWCAP_LOONGSON_EXT2 (1 << 13)
+#define HWCAP_LOONGSON_CPUCFG (1 << 14)
+
+#endif /* _UAPI_ASM_HWCAP_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
new file mode 100644
index 000000000..43d1faa02
--- /dev/null
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -0,0 +1,1141 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Format of an instruction in memory.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2000 by Ralf Baechle
+ * Copyright (C) 2006 by Thiemo Seufer
+ * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef _UAPI_ASM_INST_H
+#define _UAPI_ASM_INST_H
+
+#include <asm/bitfield.h>
+
+/*
+ * Major opcodes; before MIPS IV cop1x was called cop3.
+ */
+enum major_op {
+        spec_op, bcond_op, j_op, jal_op,
+        beq_op, bne_op, blez_op, bgtz_op,
+        addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
+        andi_op, ori_op, xori_op, lui_op,
+        cop0_op, cop1_op, cop2_op, cop1x_op,
+        beql_op, bnel_op, blezl_op, bgtzl_op,
+        daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
+        spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
+        lb_op, lh_op, lwl_op, lw_op,
+        lbu_op, lhu_op, lwr_op, lwu_op,
+        sb_op, sh_op, swl_op, sw_op,
+        sdl_op, sdr_op, swr_op, cache_op,
+        ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
+        lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
+        sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
+        scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
+};
+
+/*
+ * func field of spec opcode.
+ */
+enum spec_op {
+        sll_op, movc_op, srl_op, sra_op,
+        sllv_op, pmon_op, srlv_op, srav_op,
+        jr_op, jalr_op, movz_op, movn_op,
+        syscall_op, break_op, spim_op, sync_op,
+        mfhi_op, mthi_op, mflo_op, mtlo_op,
+        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
+        mult_op, multu_op, div_op, divu_op,
+        dmult_op, dmultu_op, ddiv_op, ddivu_op,
+        add_op, addu_op, sub_op, subu_op,
+        and_op, or_op, xor_op, nor_op,
+        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
+        dadd_op, daddu_op, dsub_op, dsubu_op,
+        tge_op, tgeu_op, tlt_op, tltu_op,
+        teq_op, seleqz_op, tne_op, selnez_op,
+        dsll_op, spec5_unused_op, dsrl_op, dsra_op,
+        dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op
+};
+
+/*
+ * func field of spec2 opcode.
+ */
+enum spec2_op {
+        madd_op, maddu_op, mul_op, spec2_3_unused_op,
+        msub_op, msubu_op, /* more unused ops */
+        clz_op = 0x20, clo_op,
+        dclz_op = 0x24, dclo_op,
+        sdbpp_op = 0x3f
+};
+
+/*
+ * func field of spec3 opcode.
+ */
+enum spec3_op {
+        ext_op, dextm_op, dextu_op, dext_op,
+        ins_op, dinsm_op, dinsu_op, dins_op,
+        yield_op  = 0x09, lx_op     = 0x0a,
+        lwle_op   = 0x19, lwre_op   = 0x1a,
+        cachee_op = 0x1b, sbe_op    = 0x1c,
+        she_op    = 0x1d, sce_op    = 0x1e,
+        swe_op    = 0x1f, bshfl_op  = 0x20,
+        swle_op   = 0x21, swre_op   = 0x22,
+        prefe_op  = 0x23, dbshfl_op = 0x24,
+        cache6_op = 0x25, sc6_op    = 0x26,
+        scd6_op   = 0x27, lbue_op   = 0x28,
+        lhue_op   = 0x29, lbe_op    = 0x2c,
+        lhe_op    = 0x2d, lle_op    = 0x2e,
+        lwe_op    = 0x2f, pref6_op  = 0x35,
+        ll6_op    = 0x36, lld6_op   = 0x37,
+        rdhwr_op  = 0x3b
+};
+
+/*
+ * Bits 10-6 minor opcode for r6 spec mult/div encodings
+ */
+enum mult_op {
+        mult_mult_op = 0x0,
+        mult_mul_op = 0x2,
+        mult_muh_op = 0x3,
+};
+enum multu_op {
+        multu_multu_op = 0x0,
+        multu_mulu_op = 0x2,
+        multu_muhu_op = 0x3,
+};
+enum div_op {
+        div_div_op = 0x0,
+        div_div6_op = 0x2,
+        div_mod_op = 0x3,
+};
+enum divu_op {
+        divu_divu_op = 0x0,
+        divu_divu6_op = 0x2,
+        divu_modu_op = 0x3,
+};
+enum dmult_op {
+        dmult_dmult_op = 0x0,
+        dmult_dmul_op = 0x2,
+        dmult_dmuh_op = 0x3,
+};
+enum dmultu_op {
+        dmultu_dmultu_op = 0x0,
+        dmultu_dmulu_op = 0x2,
+        dmultu_dmuhu_op = 0x3,
+};
+enum ddiv_op {
+        ddiv_ddiv_op = 0x0,
+        ddiv_ddiv6_op = 0x2,
+        ddiv_dmod_op = 0x3,
+};
+enum ddivu_op {
+        ddivu_ddivu_op = 0x0,
+        ddivu_ddivu6_op = 0x2,
+        ddivu_dmodu_op = 0x3,
+};
+
+/*
+ * rt field of bcond opcodes.
+ */
+enum rt_op {
+        bltz_op, bgez_op, bltzl_op, bgezl_op,
+        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
+        tgei_op, tgeiu_op, tlti_op, tltiu_op,
+        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
+        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
+        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
+        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
+        bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
+};
+
+/*
+ * rs field of cop opcodes.
+ */
+enum cop_op {
+        mfc_op        = 0x00, dmfc_op       = 0x01,
+        cfc_op        = 0x02, mfhc0_op      = 0x02,
+        mfhc_op       = 0x03, mtc_op        = 0x04,
+        dmtc_op       = 0x05, ctc_op        = 0x06,
+        mthc0_op      = 0x06, mthc_op       = 0x07,
+        bc_op         = 0x08, bc1eqz_op     = 0x09,
+        mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
+        wrpgpr_op     = 0x0e, cop_op        = 0x10,
+        copm_op       = 0x18
+};
+
+/*
+ * rt field of cop.bc_op opcodes
+ */
+enum bcop_op {
+        bcf_op, bct_op, bcfl_op, bctl_op
+};
+
+/*
+ * func field of cop0 coi opcodes.
+ */
+enum cop0_coi_func {
+        tlbr_op       = 0x01, tlbwi_op      = 0x02,
+        tlbwr_op      = 0x06, tlbp_op       = 0x08,
+        rfe_op        = 0x10, eret_op       = 0x18,
+        wait_op       = 0x20, hypcall_op    = 0x28
+};
+
+/*
+ * func field of cop0 com opcodes.
+ */
+enum cop0_com_func {
+        tlbr1_op      = 0x01, tlbw_op       = 0x02,
+        tlbp1_op      = 0x08, dctr_op       = 0x09,
+        dctw_op       = 0x0a
+};
+
+/*
+ * fmt field of cop1 opcodes.
+ */
+enum cop1_fmt {
+        s_fmt, d_fmt, e_fmt, q_fmt,
+        w_fmt, l_fmt
+};
+
+/*
+ * func field of cop1 instructions using d, s or w format.
+ */
+enum cop1_sdw_func {
+        fadd_op      =  0x00, fsub_op      =  0x01,
+        fmul_op      =  0x02, fdiv_op      =  0x03,
+        fsqrt_op     =  0x04, fabs_op      =  0x05,
+        fmov_op      =  0x06, fneg_op      =  0x07,
+        froundl_op   =  0x08, ftruncl_op   =  0x09,
+        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
+        fround_op    =  0x0c, ftrunc_op    =  0x0d,
+        fceil_op     =  0x0e, ffloor_op    =  0x0f,
+        fsel_op      =  0x10,
+        fmovc_op     =  0x11, fmovz_op     =  0x12,
+        fmovn_op     =  0x13, fseleqz_op   =  0x14,
+        frecip_op    =  0x15, frsqrt_op    =  0x16,
+        fselnez_op   =  0x17, fmaddf_op    =  0x18,
+        fmsubf_op    =  0x19, frint_op     =  0x1a,
+        fclass_op    =  0x1b, fmin_op      =  0x1c,
+        fmina_op     =  0x1d, fmax_op      =  0x1e,
+        fmaxa_op     =  0x1f, fcvts_op     =  0x20,
+        fcvtd_op     =  0x21, fcvte_op     =  0x22,
+        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
+        fcmp_op      =  0x30
+};
+
+/*
+ * func field of cop1x opcodes (MIPS IV).
+ */
+enum cop1x_func {
+        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
+        swxc1_op     =  0x08, sdxc1_op     =  0x09,
+        pfetch_op    =  0x0f, madd_s_op    =  0x20,
+        madd_d_op    =  0x21, madd_e_op    =  0x22,
+        msub_s_op    =  0x28, msub_d_op    =  0x29,
+        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
+        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
+        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
+        nmsub_e_op   =  0x3a
+};
+
+/*
+ * func field for mad opcodes (MIPS IV).
+ */
+enum mad_func {
+        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
+        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
+};
+
+/*
+ * func field for page table walker (Loongson-3).
+ */
+enum ptw_func {
+        lwdir_op = 0x00,
+        lwpte_op = 0x01,
+        lddir_op = 0x02,
+        ldpte_op = 0x03,
+};
+
+/*
+ * func field for special3 lx opcodes (Cavium Octeon).
+ */
+enum lx_func {
+        lwx_op  = 0x00,
+        lhx_op  = 0x04,
+        lbux_op = 0x06,
+        ldx_op  = 0x08,
+        lwux_op = 0x10,
+        lhux_op = 0x14,
+        lbx_op  = 0x16,
+};
+
+/*
+ * BSHFL opcodes
+ */
+enum bshfl_func {
+        wsbh_op = 0x2,
+        seb_op  = 0x10,
+        seh_op  = 0x18,
+};
+
+/*
+ * DBSHFL opcodes
+ */
+enum dbshfl_func {
+        dsbh_op = 0x2,
+        dshd_op = 0x5,
+};
+
+/*
+ * MSA minor opcodes.
+ */
+enum msa_func {
+        msa_elm_op = 0x19,
+};
+
+/*
+ * MSA ELM opcodes.
+ */
+enum msa_elm {
+        msa_ctc_op = 0x3e,
+        msa_cfc_op = 0x7e,
+};
+
+/*
+ * func field for MSA MI10 format.
+ */
+enum msa_mi10_func {
+        msa_ld_op = 8,
+        msa_st_op = 9,
+};
+
+/*
+ * MSA 2 bit format fields.
+ */
+enum msa_2b_fmt {
+        msa_fmt_b = 0,
+        msa_fmt_h = 1,
+        msa_fmt_w = 2,
+        msa_fmt_d = 3,
+};
+
+/*
+ * (microMIPS) Major opcodes.
+ */
+enum mm_major_op {
+        mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
+        mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
+        mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
+        mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
+        mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
+        mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
+        mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
+        mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
+        mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
+        mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
+        mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
+        mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
+        mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
+        mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
+        mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
+        mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
+};
+
+/*
+ * (microMIPS) POOL32I minor opcodes.
+ */
+enum mm_32i_minor_op {
+        mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
+        mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
+        mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
+        mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
+        mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
+        mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
+        mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
+        mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
+        mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
+};
+
+/*
+ * (microMIPS) POOL32A minor opcodes.
+ */
+enum mm_32a_minor_op {
+        mm_sll32_op = 0x000,
+        mm_ins_op = 0x00c,
+        mm_sllv32_op = 0x010,
+        mm_ext_op = 0x02c,
+        mm_pool32axf_op = 0x03c,
+        mm_srl32_op = 0x040,
+        mm_srlv32_op = 0x050,
+        mm_sra_op = 0x080,
+        mm_srav_op = 0x090,
+        mm_rotr_op = 0x0c0,
+        mm_lwxs_op = 0x118,
+        mm_addu32_op = 0x150,
+        mm_subu32_op = 0x1d0,
+        mm_wsbh_op = 0x1ec,
+        mm_mul_op = 0x210,
+        mm_and_op = 0x250,
+        mm_or32_op = 0x290,
+        mm_xor32_op = 0x310,
+        mm_slt_op = 0x350,
+        mm_sltu_op = 0x390,
+};
+
+/*
+ * (microMIPS) POOL32B functions.
+ */
+enum mm_32b_func {
+        mm_lwc2_func = 0x0,
+        mm_lwp_func = 0x1,
+        mm_ldc2_func = 0x2,
+        mm_ldp_func = 0x4,
+        mm_lwm32_func = 0x5,
+        mm_cache_func = 0x6,
+        mm_ldm_func = 0x7,
+        mm_swc2_func = 0x8,
+        mm_swp_func = 0x9,
+        mm_sdc2_func = 0xa,
+        mm_sdp_func = 0xc,
+        mm_swm32_func = 0xd,
+        mm_sdm_func = 0xf,
+};
+
+/*
+ * (microMIPS) POOL32C functions.
+ */
+enum mm_32c_func {
+        mm_pref_func = 0x2,
+        mm_ll_func = 0x3,
+        mm_swr_func = 0x9,
+        mm_sc_func = 0xb,
+        mm_lwu_func = 0xe,
+};
+
+/*
+ * (microMIPS) POOL32AXF minor opcodes.
+ */
+enum mm_32axf_minor_op {
+        mm_mfc0_op = 0x003,
+        mm_mtc0_op = 0x00b,
+        mm_tlbp_op = 0x00d,
+        mm_mfhi32_op = 0x035,
+        mm_jalr_op = 0x03c,
+        mm_tlbr_op = 0x04d,
+        mm_mflo32_op = 0x075,
+        mm_jalrhb_op = 0x07c,
+        mm_tlbwi_op = 0x08d,
+        mm_mthi32_op = 0x0b5,
+        mm_tlbwr_op = 0x0cd,
+        mm_mtlo32_op = 0x0f5,
+        mm_di_op = 0x11d,
+        mm_jalrs_op = 0x13c,
+        mm_jalrshb_op = 0x17c,
+        mm_sync_op = 0x1ad,
+        mm_syscall_op = 0x22d,
+        mm_wait_op = 0x24d,
+        mm_eret_op = 0x3cd,
+        mm_divu_op = 0x5dc,
+};
+
+/*
+ * (microMIPS) POOL32F minor opcodes.
+ */
+enum mm_32f_minor_op {
+        mm_32f_00_op = 0x00,
+        mm_32f_01_op = 0x01,
+        mm_32f_02_op = 0x02,
+        mm_32f_10_op = 0x08,
+        mm_32f_11_op = 0x09,
+        mm_32f_12_op = 0x0a,
+        mm_32f_20_op = 0x10,
+        mm_32f_30_op = 0x18,
+        mm_32f_40_op = 0x20,
+        mm_32f_41_op = 0x21,
+        mm_32f_42_op = 0x22,
+        mm_32f_50_op = 0x28,
+        mm_32f_51_op = 0x29,
+        mm_32f_52_op = 0x2a,
+        mm_32f_60_op = 0x30,
+        mm_32f_70_op = 0x38,
+        mm_32f_73_op = 0x3b,
+        mm_32f_74_op = 0x3c,
+};
+
+/*
+ * (microMIPS) POOL32F secondary minor opcodes.
+ */
+enum mm_32f_10_minor_op {
+        mm_lwxc1_op = 0x1,
+        mm_swxc1_op,
+        mm_ldxc1_op,
+        mm_sdxc1_op,
+        mm_luxc1_op,
+        mm_suxc1_op,
+};
+
+enum mm_32f_func {
+        mm_lwxc1_func = 0x048,
+        mm_swxc1_func = 0x088,
+        mm_ldxc1_func = 0x0c8,
+        mm_sdxc1_func = 0x108,
+};
+
+/*
+ * (microMIPS) POOL32F secondary minor opcodes.
+ */
+enum mm_32f_40_minor_op {
+        mm_fmovf_op,
+        mm_fmovt_op,
+};
+
+/*
+ * (microMIPS) POOL32F secondary minor opcodes.
+ */
+enum mm_32f_60_minor_op {
+        mm_fadd_op,
+        mm_fsub_op,
+        mm_fmul_op,
+        mm_fdiv_op,
+};
+
+/*
+ * (microMIPS) POOL32F secondary minor opcodes.
+ */
+enum mm_32f_70_minor_op {
+        mm_fmovn_op,
+        mm_fmovz_op,
+};
+
+/*
+ * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
+ */
+enum mm_32f_73_minor_op {
+        mm_fmov0_op = 0x01,
+        mm_fcvtl_op = 0x04,
+        mm_movf0_op = 0x05,
+        mm_frsqrt_op = 0x08,
+        mm_ffloorl_op = 0x0c,
+        mm_fabs0_op = 0x0d,
+        mm_fcvtw_op = 0x24,
+        mm_movt0_op = 0x25,
+        mm_fsqrt_op = 0x28,
+        mm_ffloorw_op = 0x2c,
+        mm_fneg0_op = 0x2d,
+        mm_cfc1_op = 0x40,
+        mm_frecip_op = 0x48,
+        mm_fceill_op = 0x4c,
+        mm_fcvtd0_op = 0x4d,
+        mm_ctc1_op = 0x60,
+        mm_fceilw_op = 0x6c,
+        mm_fcvts0_op = 0x6d,
+        mm_mfc1_op = 0x80,
+        mm_fmov1_op = 0x81,
+        mm_movf1_op = 0x85,
+        mm_ftruncl_op = 0x8c,
+        mm_fabs1_op = 0x8d,
+        mm_mtc1_op = 0xa0,
+        mm_movt1_op = 0xa5,
+        mm_ftruncw_op = 0xac,
+        mm_fneg1_op = 0xad,
+        mm_mfhc1_op = 0xc0,
+        mm_froundl_op = 0xcc,
+        mm_fcvtd1_op = 0xcd,
+        mm_mthc1_op = 0xe0,
+        mm_froundw_op = 0xec,
+        mm_fcvts1_op = 0xed,
+};
+
+/*
+ * (microMIPS) POOL32S minor opcodes.
+ */
+enum mm_32s_minor_op {
+        mm_32s_elm_op = 0x16,
+};
+
+/*
+ * (microMIPS) POOL16C minor opcodes.
+ */
+enum mm_16c_minor_op {
+        mm_lwm16_op = 0x04,
+        mm_swm16_op = 0x05,
+        mm_jr16_op = 0x0c,
+        mm_jrc_op = 0x0d,
+        mm_jalr16_op = 0x0e,
+        mm_jalrs16_op = 0x0f,
+        mm_jraddiusp_op = 0x18,
+};
+
+/*
+ * (microMIPS) POOL16D minor opcodes.
+ */
+enum mm_16d_minor_op {
+        mm_addius5_func,
+        mm_addiusp_func,
+};
+
+/*
+ * (MIPS16e) opcodes.
+ */
+enum MIPS16e_ops {
+        MIPS16e_jal_op = 003,
+        MIPS16e_ld_op = 007,
+        MIPS16e_i8_op = 014,
+        MIPS16e_sd_op = 017,
+        MIPS16e_lb_op = 020,
+        MIPS16e_lh_op = 021,
+        MIPS16e_lwsp_op = 022,
+        MIPS16e_lw_op = 023,
+        MIPS16e_lbu_op = 024,
+        MIPS16e_lhu_op = 025,
+        MIPS16e_lwpc_op = 026,
+        MIPS16e_lwu_op = 027,
+        MIPS16e_sb_op = 030,
+        MIPS16e_sh_op = 031,
+        MIPS16e_swsp_op = 032,
+        MIPS16e_sw_op = 033,
+        MIPS16e_rr_op = 035,
+        MIPS16e_extend_op = 036,
+        MIPS16e_i64_op = 037,
+};
+
+enum MIPS16e_i64_func {
+        MIPS16e_ldsp_func,
+        MIPS16e_sdsp_func,
+        MIPS16e_sdrasp_func,
+        MIPS16e_dadjsp_func,
+        MIPS16e_ldpc_func,
+};
+
+enum MIPS16e_rr_func {
+        MIPS16e_jr_func,
+};
+
+enum MIPS6e_i8_func {
+        MIPS16e_swrasp_func = 02,
+};
+
+/*
+ * (microMIPS) NOP instruction.
+ */
+#define MM_NOP16        0x0c00
+
+struct j_format {
+        __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
+        __BITFIELD_FIELD(unsigned int target : 26,
+        ;))
+};
+
+struct i_format {                       /* signed immediate format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(signed int simmediate : 16,
+        ;))))
+};
+
+struct u_format {                       /* unsigned immediate format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int uimmediate : 16,
+        ;))))
+};
+
+struct c_format {                       /* Cache (>= R6000) format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int c_op : 3,
+        __BITFIELD_FIELD(unsigned int cache : 2,
+        __BITFIELD_FIELD(unsigned int simmediate : 16,
+        ;)))))
+};
+
+struct r_format {                       /* Register format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int re : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct c0r_format {                     /* C0 register format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int z: 8,
+        __BITFIELD_FIELD(unsigned int sel : 3,
+        ;))))))
+};
+
+struct mfmc0_format {                   /* MFMC0 register format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int re : 5,
+        __BITFIELD_FIELD(unsigned int sc : 1,
+        __BITFIELD_FIELD(unsigned int : 2,
+        __BITFIELD_FIELD(unsigned int sel : 3,
+        ;))))))))
+};
+
+struct co_format {                      /* C0 CO format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int co : 1,
+        __BITFIELD_FIELD(unsigned int code : 19,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))
+};
+
+struct p_format {               /* Performance counter format (R10000) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int re : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct f_format {                       /* FPU register format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int : 1,
+        __BITFIELD_FIELD(unsigned int fmt : 4,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int re : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;)))))))
+};
+
+struct ma_format {              /* FPU multiply and add format (MIPS IV) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int fr : 5,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 4,
+        __BITFIELD_FIELD(unsigned int fmt : 2,
+        ;)))))))
+};
+
+struct b_format {                       /* BREAK and SYSCALL */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int code : 20,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;)))
+};
+
+struct ps_format {                      /* MIPS-3D / paired single format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct v_format {                               /* MDMX vector format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int sel : 4,
+        __BITFIELD_FIELD(unsigned int fmt : 1,
+        __BITFIELD_FIELD(unsigned int vt : 5,
+        __BITFIELD_FIELD(unsigned int vs : 5,
+        __BITFIELD_FIELD(unsigned int vd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;)))))))
+};
+
+struct msa_mi10_format {                /* MSA MI10 */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(signed int s10 : 10,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int wd : 5,
+        __BITFIELD_FIELD(unsigned int func : 4,
+        __BITFIELD_FIELD(unsigned int df : 2,
+        ;))))))
+};
+
+struct dsp_format {             /* SPEC3 DSP format instructions */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int index : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int op : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct spec3_format {   /* SPEC3 */
+        __BITFIELD_FIELD(unsigned int opcode:6,
+        __BITFIELD_FIELD(unsigned int rs:5,
+        __BITFIELD_FIELD(unsigned int rt:5,
+        __BITFIELD_FIELD(signed int simmediate:9,
+        __BITFIELD_FIELD(unsigned int func:7,
+        ;)))))
+};
+
+/*
+ * microMIPS instruction formats (32-bit length)
+ *
+ * NOTE:
+ *      Parenthesis denote whether the format is a microMIPS instruction or
+ *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
+ */
+struct fb_format {              /* FPU branch format (MIPS32) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int bc : 5,
+        __BITFIELD_FIELD(unsigned int cc : 3,
+        __BITFIELD_FIELD(unsigned int flag : 2,
+        __BITFIELD_FIELD(signed int simmediate : 16,
+        ;)))))
+};
+
+struct fp0_format {             /* FPU multiply and add format (MIPS32) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int fmt : 5,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_fp0_format {          /* FPU multiply and add format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int fmt : 3,
+        __BITFIELD_FIELD(unsigned int op : 2,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;)))))))
+};
+
+struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int op : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fmt : 2,
+        __BITFIELD_FIELD(unsigned int op : 8,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int cc : 3,
+        __BITFIELD_FIELD(unsigned int zero : 2,
+        __BITFIELD_FIELD(unsigned int fmt : 2,
+        __BITFIELD_FIELD(unsigned int op : 3,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))))
+};
+
+struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fmt : 3,
+        __BITFIELD_FIELD(unsigned int op : 7,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int cc : 3,
+        __BITFIELD_FIELD(unsigned int fmt : 3,
+        __BITFIELD_FIELD(unsigned int cond : 4,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;)))))))
+};
+
+struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int index : 5,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int op : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int fr : 5,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int ft : 5,
+        __BITFIELD_FIELD(unsigned int fs : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int fr : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+struct mm_i_format {            /* Immediate format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(signed int simmediate : 16,
+        ;))))
+};
+
+struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int func : 4,
+        __BITFIELD_FIELD(signed int simmediate : 12,
+        ;)))))
+};
+
+struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int index : 5,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int func : 11,
+        ;)))))
+};
+
+struct mm_a_format {            /* ADDIUPC format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 3,
+        __BITFIELD_FIELD(signed int simmediate : 23,
+        ;)))
+};
+
+/*
+ * microMIPS instruction formats (16-bit length)
+ */
+struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(signed int simmediate : 10,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;)))
+};
+
+struct mm_b1_format {           /* Conditional branch format (microMIPS) */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 3,
+        __BITFIELD_FIELD(signed int simmediate : 7,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;))))
+};
+
+struct mm16_m_format {          /* Multi-word load/store format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int func : 4,
+        __BITFIELD_FIELD(unsigned int rlist : 2,
+        __BITFIELD_FIELD(unsigned int imm : 4,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;)))))
+};
+
+struct mm16_rb_format {         /* Signed immediate format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 3,
+        __BITFIELD_FIELD(unsigned int base : 3,
+        __BITFIELD_FIELD(signed int simmediate : 4,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;)))))
+};
+
+struct mm16_r3_format {         /* Load from global pointer format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 3,
+        __BITFIELD_FIELD(signed int simmediate : 7,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;))))
+};
+
+struct mm16_r5_format {         /* Load/store from stack pointer format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int imm : 5,
+        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
+        ;))))
+};
+
+/*
+ * Loongson-3 overridden COP2 instruction formats (32-bit length)
+ */
+struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int fr : 1,
+        __BITFIELD_FIELD(unsigned int offset : 9,
+        __BITFIELD_FIELD(unsigned int ls : 1,
+        __BITFIELD_FIELD(unsigned int rq : 5,
+        ;)))))))
+};
+
+struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int base : 5,
+        __BITFIELD_FIELD(unsigned int rt : 5,
+        __BITFIELD_FIELD(unsigned int index : 5,
+        __BITFIELD_FIELD(unsigned int offset : 8,
+        __BITFIELD_FIELD(unsigned int opcode1 : 3,
+        ;))))))
+};
+
+struct loongson3_lscsr_format { /* Loongson-3 CPUCFG&CSR read/write format */
+        __BITFIELD_FIELD(unsigned int opcode : 6,
+        __BITFIELD_FIELD(unsigned int rs : 5,
+        __BITFIELD_FIELD(unsigned int fr : 5,
+        __BITFIELD_FIELD(unsigned int rd : 5,
+        __BITFIELD_FIELD(unsigned int fd : 5,
+        __BITFIELD_FIELD(unsigned int func : 6,
+        ;))))))
+};
+
+/*
+ * MIPS16e instruction formats (16-bit length)
+ */
+struct m16e_rr {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int rx : 3,
+        __BITFIELD_FIELD(unsigned int nd : 1,
+        __BITFIELD_FIELD(unsigned int l : 1,
+        __BITFIELD_FIELD(unsigned int ra : 1,
+        __BITFIELD_FIELD(unsigned int func : 5,
+        ;))))))
+};
+
+struct m16e_jal {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int x : 1,
+        __BITFIELD_FIELD(unsigned int imm20_16 : 5,
+        __BITFIELD_FIELD(signed int imm25_21 : 5,
+        ;))))
+};
+
+struct m16e_i64 {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int func : 3,
+        __BITFIELD_FIELD(unsigned int imm : 8,
+        ;)))
+};
+
+struct m16e_ri64 {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int func : 3,
+        __BITFIELD_FIELD(unsigned int ry : 3,
+        __BITFIELD_FIELD(unsigned int imm : 5,
+        ;))))
+};
+
+struct m16e_ri {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int rx : 3,
+        __BITFIELD_FIELD(unsigned int imm : 8,
+        ;)))
+};
+
+struct m16e_rri {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int rx : 3,
+        __BITFIELD_FIELD(unsigned int ry : 3,
+        __BITFIELD_FIELD(unsigned int imm : 5,
+        ;))))
+};
+
+struct m16e_i8 {
+        __BITFIELD_FIELD(unsigned int opcode : 5,
+        __BITFIELD_FIELD(unsigned int func : 3,
+        __BITFIELD_FIELD(unsigned int imm : 8,
+        ;)))
+};
+
+union mips_instruction {
+        unsigned int word;
+        unsigned short halfword[2];
+        unsigned char byte[4];
+        struct j_format j_format;
+        struct i_format i_format;
+        struct u_format u_format;
+        struct c_format c_format;
+        struct r_format r_format;
+        struct c0r_format c0r_format;
+        struct mfmc0_format mfmc0_format;
+        struct co_format co_format;
+        struct p_format p_format;
+        struct f_format f_format;
+        struct ma_format ma_format;
+        struct msa_mi10_format msa_mi10_format;
+        struct b_format b_format;
+        struct ps_format ps_format;
+        struct v_format v_format;
+        struct dsp_format dsp_format;
+        struct spec3_format spec3_format;
+        struct fb_format fb_format;
+        struct fp0_format fp0_format;
+        struct mm_fp0_format mm_fp0_format;
+        struct fp1_format fp1_format;
+        struct mm_fp1_format mm_fp1_format;
+        struct mm_fp2_format mm_fp2_format;
+        struct mm_fp3_format mm_fp3_format;
+        struct mm_fp4_format mm_fp4_format;
+        struct mm_fp5_format mm_fp5_format;
+        struct fp6_format fp6_format;
+        struct mm_fp6_format mm_fp6_format;
+        struct mm_i_format mm_i_format;
+        struct mm_m_format mm_m_format;
+        struct mm_x_format mm_x_format;
+        struct mm_a_format mm_a_format;
+        struct mm_b0_format mm_b0_format;
+        struct mm_b1_format mm_b1_format;
+        struct mm16_m_format mm16_m_format ;
+        struct mm16_rb_format mm16_rb_format;
+        struct mm16_r3_format mm16_r3_format;
+        struct mm16_r5_format mm16_r5_format;
+        struct loongson3_lswc2_format loongson3_lswc2_format;
+        struct loongson3_lsdc2_format loongson3_lsdc2_format;
+        struct loongson3_lscsr_format loongson3_lscsr_format;
+};
+
+union mips16e_instruction {
+        unsigned int full : 16;
+        struct m16e_rr rr;
+        struct m16e_jal jal;
+        struct m16e_i64 i64;
+        struct m16e_ri64 ri64;
+        struct m16e_ri ri;
+        struct m16e_rri rri;
+        struct m16e_i8 i8;
+};
+
+#endif /* _UAPI_ASM_INST_H */
diff --git a/arch/mips/include/uapi/asm/ioctl.h b/arch/mips/include/uapi/asm/ioctl.h
new file mode 100644
index 000000000..1050a6ea2
--- /dev/null
+++ b/arch/mips/include/uapi/asm/ioctl.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Wind River Systems
+ * Written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_IOCTL_H
+#define __ASM_IOCTL_H
+
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+/*
+ * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
+ * And this turns out useful to catch old ioctl numbers in header
+ * files for us.
+ */
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+#include <asm-generic/ioctl.h>
+
+#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/uapi/asm/ioctls.h b/arch/mips/include/uapi/asm/ioctls.h
new file mode 100644
index 000000000..16aa8a766
--- /dev/null
+++ b/arch/mips/include/uapi/asm/ioctls.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_IOCTLS_H
+#define __ASM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define TCGETA          0x5401
+#define TCSETA          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETAW         0x5403
+#define TCSETAF         0x5404
+
+#define TCSBRK          0x5405
+#define TCXONC          0x5406
+#define TCFLSH          0x5407
+
+#define TCGETS          0x540d
+#define TCSETS          0x540e
+#define TCSETSW         0x540f
+#define TCSETSF         0x5410
+
+#define TIOCEXCL        0x740d          /* set exclusive use of tty */
+#define TIOCNXCL        0x740e          /* reset exclusive use of tty */
+#define TIOCOUTQ        0x7472          /* output queue size */
+#define TIOCSTI         0x5472          /* simulate terminal input */
+#define TIOCMGET        0x741d          /* get all modem bits */
+#define TIOCMBIS        0x741b          /* bis modem bits */
+#define TIOCMBIC        0x741c          /* bic modem bits */
+#define TIOCMSET        0x741a          /* set all modem bits */
+#define TIOCPKT         0x5470          /* pty: set/clear packet mode */
+#define  TIOCPKT_DATA           0x00    /* data packet */
+#define  TIOCPKT_FLUSHREAD      0x01    /* flush packet */
+#define  TIOCPKT_FLUSHWRITE     0x02    /* flush packet */
+#define  TIOCPKT_STOP           0x04    /* stop output */
+#define  TIOCPKT_START          0x08    /* start output */
+#define  TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
+#define  TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
+#define  TIOCPKT_IOCTL          0x40    /* state change of pty driver */
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */
+#define TIOCNOTTY       0x5471          /* void tty association */
+#define TIOCSETD        0x7401
+#define TIOCGETD        0x7400
+
+#define FIOCLEX         0x6601
+#define FIONCLEX        0x6602
+#define FIOASYNC        0x667d
+#define FIONBIO         0x667e
+#define FIOQSIZE        0x667f
+
+#define TIOCGLTC        0x7474                  /* get special local chars */
+#define TIOCSLTC        0x7475                  /* set special local chars */
+#define TIOCSPGRP       _IOW('t', 118, int)     /* set pgrp of tty */
+#define TIOCGPGRP       _IOR('t', 119, int)     /* get pgrp of tty */
+#define TIOCCONS        _IOW('t', 120, int)     /* become virtual console */
+
+#define FIONREAD        0x467f
+#define TIOCINQ         FIONREAD
+
+#define TIOCGETP        0x7408
+#define TIOCSETP        0x7409
+#define TIOCSETN        0x740a                  /* TIOCSETP wo flush */
+
+/* #define TIOCSETA     _IOW('t', 20, struct termios) set termios struct */
+/* #define TIOCSETAW    _IOW('t', 21, struct termios) drain output, set */
+/* #define TIOCSETAF    _IOW('t', 22, struct termios) drn out, fls in, set */
+/* #define TIOCGETD     _IOR('t', 26, int)      get line discipline */
+/* #define TIOCSETD     _IOW('t', 27, int)      set line discipline */
+                                                /* 127-124 compat */
+
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x7416  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T', 0x2A, struct termios2)
+#define TCSETS2         _IOW('T', 0x2B, struct termios2)
+#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
+#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+#define TIOCGRS485      _IOR('T', 0x2E, struct serial_rs485)
+#define TIOCSRS485      _IOWR('T', 0x2F, struct serial_rs485)
+#define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
+#define TIOCSIG         _IOW('T', 0x36, int)  /* Generate signal on Pty slave */
+#define TIOCVHANGUP     0x5437
+#define TIOCGPKT        _IOR('T', 0x38, int) /* Get packet mode state */
+#define TIOCGPTLCK      _IOR('T', 0x39, int) /* Get Pty lock state */
+#define TIOCGEXCL       _IOR('T', 0x40, int) /* Get exclusive mode state */
+#define TIOCGPTPEER     _IO('T', 0x41) /* Safely open the slave */
+#define TIOCGISO7816    _IOR('T', 0x42, struct serial_iso7816)
+#define TIOCSISO7816    _IOWR('T', 0x43, struct serial_iso7816)
+
+/* I hope the range from 0x5480 on is free ... */
+#define TIOCSCTTY       0x5480          /* become controlling tty */
+#define TIOCGSOFTCAR    0x5481
+#define TIOCSSOFTCAR    0x5482
+#define TIOCLINUX       0x5483
+#define TIOCGSERIAL     0x5484
+#define TIOCSSERIAL     0x5485
+#define TCSBRKP         0x5486  /* Needed for POSIX tcsendbreak() */
+#define TIOCSERCONFIG   0x5488
+#define TIOCSERGWILD    0x5489
+#define TIOCSERSWILD    0x548a
+#define TIOCGLCKTRMIOS  0x548b
+#define TIOCSLCKTRMIOS  0x548c
+#define TIOCSERGSTRUCT  0x548d /* For debugging only */
+#define TIOCSERGETLSR   0x548e /* Get line status register */
+#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
+#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
+#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+
+#endif /* __ASM_IOCTLS_H */
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
new file mode 100644
index 000000000..edcf717c4
--- /dev/null
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Cavium, Inc.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
+
+#ifndef __LINUX_KVM_MIPS_H
+#define __LINUX_KVM_MIPS_H
+
+#include <linux/types.h>
+
+/*
+ * KVM MIPS specific structures and definitions.
+ *
+ * Some parts derived from the x86 version of this file.
+ */
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+/*
+ * for KVM_GET_REGS and KVM_SET_REGS
+ *
+ * If Config[AT] is zero (32-bit CPU), the register contents are
+ * stored in the lower 32-bits of the struct kvm_regs fields and sign
+ * extended to 64-bits.
+ */
+struct kvm_regs {
+        /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
+        __u64 gpr[32];
+        __u64 hi;
+        __u64 lo;
+        __u64 pc;
+};
+
+/*
+ * for KVM_GET_FPU and KVM_SET_FPU
+ */
+struct kvm_fpu {
+};
+
+
+/*
+ * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
+ * registers.  The id field is broken down as follows:
+ *
+ *  bits[63..52] - As per linux/kvm.h
+ *  bits[51..32] - Must be zero.
+ *  bits[31..16] - Register set.
+ *
+ * Register set = 0: GP registers from kvm_regs (see definitions below).
+ *
+ * Register set = 1: CP0 registers.
+ *  bits[15..8]  - COP0 register set.
+ *
+ *  COP0 register set = 0: Main CP0 registers.
+ *   bits[7..3]   - Register 'rd'  index.
+ *   bits[2..0]   - Register 'sel' index.
+ *
+ *  COP0 register set = 1: MAARs.
+ *   bits[7..0]   - MAAR index.
+ *
+ * Register set = 2: KVM specific registers (see definitions below).
+ *
+ * Register set = 3: FPU / MSA registers (see definitions below).
+ *
+ * Other sets registers may be added in the future.  Each set would
+ * have its own identifier in bits[31..16].
+ */
+
+#define KVM_REG_MIPS_GP         (KVM_REG_MIPS | 0x0000000000000000ULL)
+#define KVM_REG_MIPS_CP0        (KVM_REG_MIPS | 0x0000000000010000ULL)
+#define KVM_REG_MIPS_KVM        (KVM_REG_MIPS | 0x0000000000020000ULL)
+#define KVM_REG_MIPS_FPU        (KVM_REG_MIPS | 0x0000000000030000ULL)
+
+
+/*
+ * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
+ */
+
+#define KVM_REG_MIPS_R0         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  0)
+#define KVM_REG_MIPS_R1         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  1)
+#define KVM_REG_MIPS_R2         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  2)
+#define KVM_REG_MIPS_R3         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  3)
+#define KVM_REG_MIPS_R4         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  4)
+#define KVM_REG_MIPS_R5         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  5)
+#define KVM_REG_MIPS_R6         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  6)
+#define KVM_REG_MIPS_R7         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  7)
+#define KVM_REG_MIPS_R8         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  8)
+#define KVM_REG_MIPS_R9         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  9)
+#define KVM_REG_MIPS_R10        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
+#define KVM_REG_MIPS_R11        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
+#define KVM_REG_MIPS_R12        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
+#define KVM_REG_MIPS_R13        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
+#define KVM_REG_MIPS_R14        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
+#define KVM_REG_MIPS_R15        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
+#define KVM_REG_MIPS_R16        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
+#define KVM_REG_MIPS_R17        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
+#define KVM_REG_MIPS_R18        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
+#define KVM_REG_MIPS_R19        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
+#define KVM_REG_MIPS_R20        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
+#define KVM_REG_MIPS_R21        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
+#define KVM_REG_MIPS_R22        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
+#define KVM_REG_MIPS_R23        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
+#define KVM_REG_MIPS_R24        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
+#define KVM_REG_MIPS_R25        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
+#define KVM_REG_MIPS_R26        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
+#define KVM_REG_MIPS_R27        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
+#define KVM_REG_MIPS_R28        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
+#define KVM_REG_MIPS_R29        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
+#define KVM_REG_MIPS_R30        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
+#define KVM_REG_MIPS_R31        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
+
+#define KVM_REG_MIPS_HI         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
+#define KVM_REG_MIPS_LO         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
+#define KVM_REG_MIPS_PC         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
+
+
+/*
+ * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
+ */
+
+#define KVM_REG_MIPS_MAAR       (KVM_REG_MIPS_CP0 | (1 << 8))
+#define KVM_REG_MIPS_CP0_MAAR(n)        (KVM_REG_MIPS_MAAR | \
+                                         KVM_REG_SIZE_U64 | (n))
+
+
+/*
+ * KVM_REG_MIPS_KVM - KVM specific control registers.
+ */
+
+/*
+ * CP0_Count control
+ * DC:    Set 0: Master disable CP0_Count and set COUNT_RESUME to now
+ *        Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
+ *               interrupts since COUNT_RESUME
+ *        This can be used to freeze the timer to get a consistent snapshot of
+ *        the CP0_Count and timer interrupt pending state, while also resuming
+ *        safely without losing time or guest timer interrupts.
+ * Other: Reserved, do not change.
+ */
+#define KVM_REG_MIPS_COUNT_CTL      (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
+#define KVM_REG_MIPS_COUNT_CTL_DC       0x00000001
+
+/*
+ * CP0_Count resume monotonic nanoseconds
+ * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
+ * disable). Any reads and writes of Count related registers while
+ * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
+ * cleared again (master enable) any timer interrupts since this time will be
+ * emulated.
+ * Modifications to times in the future are rejected.
+ */
+#define KVM_REG_MIPS_COUNT_RESUME   (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
+/*
+ * CP0_Count rate in Hz
+ * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
+ * discontinuities in CP0_Count.
+ */
+#define KVM_REG_MIPS_COUNT_HZ       (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
+
+
+/*
+ * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
+ *
+ *  bits[15..8]  - Register subset (see definitions below).
+ *  bits[7..5]   - Must be zero.
+ *  bits[4..0]   - Register number within register subset.
+ */
+
+#define KVM_REG_MIPS_FPR        (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
+#define KVM_REG_MIPS_FCR        (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
+#define KVM_REG_MIPS_MSACR      (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
+
+/*
+ * KVM_REG_MIPS_FPR - Floating point / Vector registers.
+ */
+#define KVM_REG_MIPS_FPR_32(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32  | (n))
+#define KVM_REG_MIPS_FPR_64(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64  | (n))
+#define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
+
+/*
+ * KVM_REG_MIPS_FCR - Floating point control registers.
+ */
+#define KVM_REG_MIPS_FCR_IR     (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 |  0)
+#define KVM_REG_MIPS_FCR_CSR    (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
+
+/*
+ * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
+ */
+#define KVM_REG_MIPS_MSA_IR      (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  0)
+#define KVM_REG_MIPS_MSA_CSR     (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  1)
+
+
+/*
+ * KVM MIPS specific structures and definitions
+ *
+ */
+struct kvm_debug_exit_arch {
+        __u64 epc;
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* dummy definition */
+struct kvm_sregs {
+};
+
+struct kvm_mips_interrupt {
+        /* in */
+        __u32 cpu;
+        __u32 irq;
+};
+
+#endif /* __LINUX_KVM_MIPS_H */
diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h
new file mode 100644
index 000000000..57dc2ac4f
--- /dev/null
+++ b/arch/mips/include/uapi/asm/mman.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+#define PROT_NONE       0x00            /* page can not be accessed */
+#define PROT_READ       0x01            /* page can be read */
+#define PROT_WRITE      0x02            /* page can be written */
+#define PROT_EXEC       0x04            /* page can be executed */
+/*                      0x08               reserved for PROT_EXEC_NOFLUSH */
+#define PROT_SEM        0x10            /* page may be used for atomic ops */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+/*
+ * Flags for mmap
+ */
+/* 0x01 - 0x03 are defined in linux/mman.h */
+#define MAP_TYPE        0x00f           /* Mask for type of mapping */
+#define MAP_FIXED       0x010           /* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME      0x020           /* Assign page to file */
+#define MAP_AUTOGROW    0x040           /* File may grow by writing */
+#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
+#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE   0x0400          /* don't check for reservations */
+#define MAP_ANONYMOUS   0x0800          /* don't use a file */
+#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
+#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
+#define MAP_LOCKED      0x8000          /* pages are locked */
+#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x20000         /* do not block on IO */
+#define MAP_STACK       0x40000         /* give out an address that is best suited for process/thread stacks */
+#define MAP_HUGETLB     0x80000         /* create a huge page mapping */
+#define MAP_FIXED_NOREPLACE 0x100000    /* MAP_FIXED which doesn't unmap underlying mapping */
+
+/*
+ * Flags for msync
+ */
+#define MS_ASYNC        0x0001          /* sync memory asynchronously */
+#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
+#define MS_SYNC         0x0004          /* synchronous memory sync */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+#define MCL_ONFAULT     4               /* lock all pages that are faulted in */
+
+/*
+ * Flags for mlock
+ */
+#define MLOCK_ONFAULT   0x01            /* Lock pages in range after they are faulted in, do not prefault */
+
+#define MADV_NORMAL     0               /* no further special treatment */
+#define MADV_RANDOM     1               /* expect random page references */
+#define MADV_SEQUENTIAL 2               /* expect sequential page references */
+#define MADV_WILLNEED   3               /* will need these pages */
+#define MADV_DONTNEED   4               /* don't need these pages */
+
+/* common parameters: try to keep these consistent across architectures */
+#define MADV_FREE       8               /* free pages only if memory pressure */
+#define MADV_REMOVE     9               /* remove these pages & resources */
+#define MADV_DONTFORK   10              /* don't inherit across fork */
+#define MADV_DOFORK     11              /* do inherit across fork */
+
+#define MADV_MERGEABLE   12             /* KSM may merge identical pages */
+#define MADV_UNMERGEABLE 13             /* KSM may not merge identical pages */
+#define MADV_HWPOISON    100            /* poison a page for testing */
+
+#define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
+#define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
+
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
+#define MADV_WIPEONFORK 18              /* Zero memory on fork, child only */
+#define MADV_KEEPONFORK 19              /* Undo MADV_WIPEONFORK */
+
+#define MADV_COLD       20              /* deactivate these pages */
+#define MADV_PAGEOUT    21              /* reclaim these pages */
+
+/* compatibility flags */
+#define MAP_FILE        0
+
+#define PKEY_DISABLE_ACCESS     0x1
+#define PKEY_DISABLE_WRITE      0x2
+#define PKEY_ACCESS_MASK        (PKEY_DISABLE_ACCESS |\
+                                 PKEY_DISABLE_WRITE)
+
+#endif /* _ASM_MMAN_H */
diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h
new file mode 100644
index 000000000..128af72f2
--- /dev/null
+++ b/arch/mips/include/uapi/asm/msgbuf.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_MSGBUF_H
+#define _ASM_MSGBUF_H
+
+#include <asm/ipcbuf.h>
+
+/*
+ * The msqid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous unsigned long values
+ */
+
+#if defined(__mips64)
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        long msg_stime;                 /* last msgsnd time */
+        long msg_rtime;                 /* last msgrcv time */
+        long msg_ctime;                 /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+#elif defined (__MIPSEB__)
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        unsigned long  msg_stime_high;
+        unsigned long  msg_stime;       /* last msgsnd time */
+        unsigned long  msg_rtime_high;
+        unsigned long  msg_rtime;       /* last msgrcv time */
+        unsigned long  msg_ctime_high;
+        unsigned long  msg_ctime;       /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+#elif defined (__MIPSEL__)
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        unsigned long  msg_stime;       /* last msgsnd time */
+        unsigned long  msg_stime_high;
+        unsigned long  msg_rtime;       /* last msgrcv time */
+        unsigned long  msg_rtime_high;
+        unsigned long  msg_ctime;       /* last change time */
+        unsigned long  msg_ctime_high;
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+#else
+#warning no endianess set
+#endif
+
+#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mips/include/uapi/asm/param.h b/arch/mips/include/uapi/asm/param.h
new file mode 100644
index 000000000..3f337ed66
--- /dev/null
+++ b/arch/mips/include/uapi/asm/param.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PARAM_H
+#define _ASM_PARAM_H
+
+#define EXEC_PAGESIZE   65536
+
+#include <asm-generic/param.h>
+
+#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/uapi/asm/poll.h b/arch/mips/include/uapi/asm/poll.h
new file mode 100644
index 000000000..ad289d7b7
--- /dev/null
+++ b/arch/mips/include/uapi/asm/poll.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __ASM_POLL_H
+#define __ASM_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      0x0100
+
+#include <asm-generic/poll.h>
+
+#endif /* __ASM_POLL_H */
diff --git a/arch/mips/include/uapi/asm/posix_types.h b/arch/mips/include/uapi/asm/posix_types.h
new file mode 100644
index 000000000..f0ccb5b90
--- /dev/null
+++ b/arch/mips/include/uapi/asm/posix_types.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+#include <asm/sgidefs.h>
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef long            __kernel_daddr_t;
+#define __kernel_daddr_t __kernel_daddr_t
+
+#include <asm-generic/posix_types.h>
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000..f3c025445
--- /dev/null
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_PTRACE_H
+#define _UAPI_ASM_PTRACE_H
+
+#include <linux/types.h>
+
+/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
+#define FPR_BASE        32
+#define PC              64
+#define CAUSE           65
+#define BADVADDR        66
+#define MMHI            67
+#define MMLO            68
+#define FPC_CSR         69
+#define FPC_EIR         70
+#define DSP_BASE        71              /* 3 more hi / lo register pairs */
+#define DSP_CONTROL     77
+#define ACX             78
+
+/*
+ * This struct defines the registers as used by PTRACE_{GET,SET}REGS. The
+ * format is the same for both 32- and 64-bit processes. Registers for 32-bit
+ * processes are sign extended.
+ */
+#ifdef __KERNEL__
+struct user_pt_regs {
+#else
+struct pt_regs {
+#endif
+        /* Saved main processor registers. */
+        __u64 regs[32];
+
+        /* Saved special registers. */
+        __u64 lo;
+        __u64 hi;
+        __u64 cp0_epc;
+        __u64 cp0_badvaddr;
+        __u64 cp0_status;
+        __u64 cp0_cause;
+} __attribute__ ((aligned (8)));
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+#define PTRACE_GETFPREGS                14
+#define PTRACE_SETFPREGS                15
+/* #define PTRACE_GETFPXREGS            18 */
+/* #define PTRACE_SETFPXREGS            19 */
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#define PTRACE_GET_THREAD_AREA  25
+#define PTRACE_SET_THREAD_AREA  26
+
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264    0xc0
+#define PTRACE_PEEKDATA_3264    0xc1
+#define PTRACE_POKETEXT_3264    0xc2
+#define PTRACE_POKEDATA_3264    0xc3
+#define PTRACE_GET_THREAD_AREA_3264     0xc4
+
+/* Read and write watchpoint registers.  */
+enum pt_watch_style {
+        pt_watch_style_mips32,
+        pt_watch_style_mips64
+};
+struct mips32_watch_regs {
+        unsigned int watchlo[8];
+        /* Lower 16 bits of watchhi. */
+        unsigned short watchhi[8];
+        /* Valid mask and I R W bits.
+         * bit 0 -- 1 if W bit is usable.
+         * bit 1 -- 1 if R bit is usable.
+         * bit 2 -- 1 if I bit is usable.
+         * bits 3 - 11 -- Valid watchhi mask bits.
+         */
+        unsigned short watch_masks[8];
+        /* The number of valid watch register pairs.  */
+        unsigned int num_valid;
+} __attribute__((aligned(8)));
+
+struct mips64_watch_regs {
+        unsigned long long watchlo[8];
+        unsigned short watchhi[8];
+        unsigned short watch_masks[8];
+        unsigned int num_valid;
+} __attribute__((aligned(8)));
+
+struct pt_watch_regs {
+        enum pt_watch_style style;
+        union {
+                struct mips32_watch_regs mips32;
+                struct mips64_watch_regs mips64;
+        };
+};
+
+#define PTRACE_GET_WATCH_REGS   0xd0
+#define PTRACE_SET_WATCH_REGS   0xd1
+
+
+#endif /* _UAPI_ASM_PTRACE_H */
diff --git a/arch/mips/include/uapi/asm/reg.h b/arch/mips/include/uapi/asm/reg.h
new file mode 100644
index 000000000..56d15cb81
--- /dev/null
+++ b/arch/mips/include/uapi/asm/reg.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Various register offset definitions for debuggers, core file
+ * examiners and whatnot.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1995, 1999 Silicon Graphics
+ */
+#ifndef __UAPI_ASM_MIPS_REG_H
+#define __UAPI_ASM_MIPS_REG_H
+
+#define MIPS32_EF_R0            6
+#define MIPS32_EF_R1            7
+#define MIPS32_EF_R2            8
+#define MIPS32_EF_R3            9
+#define MIPS32_EF_R4            10
+#define MIPS32_EF_R5            11
+#define MIPS32_EF_R6            12
+#define MIPS32_EF_R7            13
+#define MIPS32_EF_R8            14
+#define MIPS32_EF_R9            15
+#define MIPS32_EF_R10           16
+#define MIPS32_EF_R11           17
+#define MIPS32_EF_R12           18
+#define MIPS32_EF_R13           19
+#define MIPS32_EF_R14           20
+#define MIPS32_EF_R15           21
+#define MIPS32_EF_R16           22
+#define MIPS32_EF_R17           23
+#define MIPS32_EF_R18           24
+#define MIPS32_EF_R19           25
+#define MIPS32_EF_R20           26
+#define MIPS32_EF_R21           27
+#define MIPS32_EF_R22           28
+#define MIPS32_EF_R23           29
+#define MIPS32_EF_R24           30
+#define MIPS32_EF_R25           31
+
+/*
+ * k0/k1 unsaved
+ */
+#define MIPS32_EF_R26           32
+#define MIPS32_EF_R27           33
+
+#define MIPS32_EF_R28           34
+#define MIPS32_EF_R29           35
+#define MIPS32_EF_R30           36
+#define MIPS32_EF_R31           37
+
+/*
+ * Saved special registers
+ */
+#define MIPS32_EF_LO            38
+#define MIPS32_EF_HI            39
+
+#define MIPS32_EF_CP0_EPC       40
+#define MIPS32_EF_CP0_BADVADDR  41
+#define MIPS32_EF_CP0_STATUS    42
+#define MIPS32_EF_CP0_CAUSE     43
+#define MIPS32_EF_UNUSED0       44
+
+#define MIPS32_EF_SIZE          180
+
+#define MIPS64_EF_R0            0
+#define MIPS64_EF_R1            1
+#define MIPS64_EF_R2            2
+#define MIPS64_EF_R3            3
+#define MIPS64_EF_R4            4
+#define MIPS64_EF_R5            5
+#define MIPS64_EF_R6            6
+#define MIPS64_EF_R7            7
+#define MIPS64_EF_R8            8
+#define MIPS64_EF_R9            9
+#define MIPS64_EF_R10           10
+#define MIPS64_EF_R11           11
+#define MIPS64_EF_R12           12
+#define MIPS64_EF_R13           13
+#define MIPS64_EF_R14           14
+#define MIPS64_EF_R15           15
+#define MIPS64_EF_R16           16
+#define MIPS64_EF_R17           17
+#define MIPS64_EF_R18           18
+#define MIPS64_EF_R19           19
+#define MIPS64_EF_R20           20
+#define MIPS64_EF_R21           21
+#define MIPS64_EF_R22           22
+#define MIPS64_EF_R23           23
+#define MIPS64_EF_R24           24
+#define MIPS64_EF_R25           25
+
+/*
+ * k0/k1 unsaved
+ */
+#define MIPS64_EF_R26           26
+#define MIPS64_EF_R27           27
+
+
+#define MIPS64_EF_R28           28
+#define MIPS64_EF_R29           29
+#define MIPS64_EF_R30           30
+#define MIPS64_EF_R31           31
+
+/*
+ * Saved special registers
+ */
+#define MIPS64_EF_LO            32
+#define MIPS64_EF_HI            33
+
+#define MIPS64_EF_CP0_EPC       34
+#define MIPS64_EF_CP0_BADVADDR  35
+#define MIPS64_EF_CP0_STATUS    36
+#define MIPS64_EF_CP0_CAUSE     37
+
+#define MIPS64_EF_SIZE          304     /* size in bytes */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+#define EF_R0                   MIPS32_EF_R0
+#define EF_R1                   MIPS32_EF_R1
+#define EF_R2                   MIPS32_EF_R2
+#define EF_R3                   MIPS32_EF_R3
+#define EF_R4                   MIPS32_EF_R4
+#define EF_R5                   MIPS32_EF_R5
+#define EF_R6                   MIPS32_EF_R6
+#define EF_R7                   MIPS32_EF_R7
+#define EF_R8                   MIPS32_EF_R8
+#define EF_R9                   MIPS32_EF_R9
+#define EF_R10                  MIPS32_EF_R10
+#define EF_R11                  MIPS32_EF_R11
+#define EF_R12                  MIPS32_EF_R12
+#define EF_R13                  MIPS32_EF_R13
+#define EF_R14                  MIPS32_EF_R14
+#define EF_R15                  MIPS32_EF_R15
+#define EF_R16                  MIPS32_EF_R16
+#define EF_R17                  MIPS32_EF_R17
+#define EF_R18                  MIPS32_EF_R18
+#define EF_R19                  MIPS32_EF_R19
+#define EF_R20                  MIPS32_EF_R20
+#define EF_R21                  MIPS32_EF_R21
+#define EF_R22                  MIPS32_EF_R22
+#define EF_R23                  MIPS32_EF_R23
+#define EF_R24                  MIPS32_EF_R24
+#define EF_R25                  MIPS32_EF_R25
+#define EF_R26                  MIPS32_EF_R26
+#define EF_R27                  MIPS32_EF_R27
+#define EF_R28                  MIPS32_EF_R28
+#define EF_R29                  MIPS32_EF_R29
+#define EF_R30                  MIPS32_EF_R30
+#define EF_R31                  MIPS32_EF_R31
+#define EF_LO                   MIPS32_EF_LO
+#define EF_HI                   MIPS32_EF_HI
+#define EF_CP0_EPC              MIPS32_EF_CP0_EPC
+#define EF_CP0_BADVADDR         MIPS32_EF_CP0_BADVADDR
+#define EF_CP0_STATUS           MIPS32_EF_CP0_STATUS
+#define EF_CP0_CAUSE            MIPS32_EF_CP0_CAUSE
+#define EF_UNUSED0              MIPS32_EF_UNUSED0
+#define EF_SIZE                 MIPS32_EF_SIZE
+
+#elif _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define EF_R0                   MIPS64_EF_R0
+#define EF_R1                   MIPS64_EF_R1
+#define EF_R2                   MIPS64_EF_R2
+#define EF_R3                   MIPS64_EF_R3
+#define EF_R4                   MIPS64_EF_R4
+#define EF_R5                   MIPS64_EF_R5
+#define EF_R6                   MIPS64_EF_R6
+#define EF_R7                   MIPS64_EF_R7
+#define EF_R8                   MIPS64_EF_R8
+#define EF_R9                   MIPS64_EF_R9
+#define EF_R10                  MIPS64_EF_R10
+#define EF_R11                  MIPS64_EF_R11
+#define EF_R12                  MIPS64_EF_R12
+#define EF_R13                  MIPS64_EF_R13
+#define EF_R14                  MIPS64_EF_R14
+#define EF_R15                  MIPS64_EF_R15
+#define EF_R16                  MIPS64_EF_R16
+#define EF_R17                  MIPS64_EF_R17
+#define EF_R18                  MIPS64_EF_R18
+#define EF_R19                  MIPS64_EF_R19
+#define EF_R20                  MIPS64_EF_R20
+#define EF_R21                  MIPS64_EF_R21
+#define EF_R22                  MIPS64_EF_R22
+#define EF_R23                  MIPS64_EF_R23
+#define EF_R24                  MIPS64_EF_R24
+#define EF_R25                  MIPS64_EF_R25
+#define EF_R26                  MIPS64_EF_R26
+#define EF_R27                  MIPS64_EF_R27
+#define EF_R28                  MIPS64_EF_R28
+#define EF_R29                  MIPS64_EF_R29
+#define EF_R30                  MIPS64_EF_R30
+#define EF_R31                  MIPS64_EF_R31
+#define EF_LO                   MIPS64_EF_LO
+#define EF_HI                   MIPS64_EF_HI
+#define EF_CP0_EPC              MIPS64_EF_CP0_EPC
+#define EF_CP0_BADVADDR         MIPS64_EF_CP0_BADVADDR
+#define EF_CP0_STATUS           MIPS64_EF_CP0_STATUS
+#define EF_CP0_CAUSE            MIPS64_EF_CP0_CAUSE
+#define EF_SIZE                 MIPS64_EF_SIZE
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* __UAPI_ASM_MIPS_REG_H */
diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h
new file mode 100644
index 000000000..372ff8f4b
--- /dev/null
+++ b/arch/mips/include/uapi/asm/resource.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_RESOURCE_H
+#define _ASM_RESOURCE_H
+
+
+/*
+ * These five resource limit IDs have a MIPS/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           5       /* max number of open files */
+#define RLIMIT_AS               6       /* address space limit */
+#define RLIMIT_RSS              7       /* max resident set size */
+#define RLIMIT_NPROC            8       /* max number of processes */
+#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
+
+/*
+ * SuS says limits have to be unsigned.
+ * Which makes a ton more sense anyway,
+ * but we keep the old value on MIPS32,
+ * for compatibility:
+ */
+#ifndef __mips64
+# define RLIM_INFINITY          0x7fffffffUL
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* _ASM_RESOURCE_H */
diff --git a/arch/mips/include/uapi/asm/sembuf.h b/arch/mips/include/uapi/asm/sembuf.h
new file mode 100644
index 000000000..ba7fe0c89
--- /dev/null
+++ b/arch/mips/include/uapi/asm/sembuf.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_SEMBUF_H
+#define _ASM_SEMBUF_H
+
+#include <asm/ipcbuf.h>
+
+/*
+ * The semid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for 2 miscellaneous 64-bit values on mips64,
+ * but used for the upper 32 bit of the time values on mips32.
+ */
+
+#ifdef __mips64
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        long             sem_otime;             /* last semop time */
+        long             sem_ctime;             /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+#else
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        unsigned long   sem_otime;              /* last semop time */
+        unsigned long   sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   sem_otime_high;
+        unsigned long   sem_ctime_high;
+};
+#endif
+
+#endif /* _ASM_SEMBUF_H */
diff --git a/arch/mips/include/uapi/asm/setup.h b/arch/mips/include/uapi/asm/setup.h
new file mode 100644
index 000000000..7d48c433b
--- /dev/null
+++ b/arch/mips/include/uapi/asm/setup.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_MIPS_SETUP_H
+#define _UAPI_MIPS_SETUP_H
+
+#define COMMAND_LINE_SIZE       4096
+
+
+#endif /* _UAPI_MIPS_SETUP_H */
diff --git a/arch/mips/include/uapi/asm/sgidefs.h b/arch/mips/include/uapi/asm/sgidefs.h
new file mode 100644
index 000000000..69c3de90c
--- /dev/null
+++ b/arch/mips/include/uapi/asm/sgidefs.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1         1
+#define _MIPS_ISA_MIPS2         2
+#define _MIPS_ISA_MIPS3         3
+#define _MIPS_ISA_MIPS4         4
+#define _MIPS_ISA_MIPS5         5
+#define _MIPS_ISA_MIPS32        6
+#define _MIPS_ISA_MIPS64        7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32         1
+#define _MIPS_SIM_NABI32        2
+#define _MIPS_SIM_ABI64         3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/arch/mips/include/uapi/asm/shmbuf.h b/arch/mips/include/uapi/asm/shmbuf.h
new file mode 100644
index 000000000..680bb95b2
--- /dev/null
+++ b/arch/mips/include/uapi/asm/shmbuf.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_SHMBUF_H
+#define _ASM_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * As MIPS was lacking proper padding after shm_?time, we use 48 bits
+ * of the padding at the end to store a few additional bits of the time.
+ * libc implementations need to take care to convert this into a proper
+ * data structure when moving to 64-bit time_t.
+ */
+
+#ifdef __mips64
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        long                    shm_atime;      /* last attach time */
+        long                    shm_dtime;      /* last detach time */
+        long                    shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+#else
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        unsigned long           shm_atime;      /* last attach time */
+        unsigned long           shm_dtime;      /* last detach time */
+        unsigned long           shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned short          shm_atime_high;
+        unsigned short          shm_dtime_high;
+        unsigned short          shm_ctime_high;
+        unsigned short          __unused1;
+};
+#endif
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASM_SHMBUF_H */
diff --git a/arch/mips/include/uapi/asm/sigcontext.h b/arch/mips/include/uapi/asm/sigcontext.h
new file mode 100644
index 000000000..d0a540e88
--- /dev/null
+++ b/arch/mips/include/uapi/asm/sigcontext.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_SIGCONTEXT_H
+#define _UAPI_ASM_SIGCONTEXT_H
+
+#include <linux/types.h>
+#include <asm/sgidefs.h>
+
+/* scalar FP context was used */
+#define USED_FP                 (1 << 0)
+
+/* the value of Status.FR when context was saved */
+#define USED_FR1                (1 << 1)
+
+/* FR=1, but with odd singles in bits 63:32 of preceding even double */
+#define USED_HYBRID_FPRS        (1 << 2)
+
+/* extended context was used, see struct extcontext for details */
+#define USED_EXTCONTEXT         (1 << 3)
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/kernel/asm-offsets.c
+ */
+struct sigcontext {
+        unsigned int            sc_regmask;     /* Unused */
+        unsigned int            sc_status;      /* Unused */
+        unsigned long long      sc_pc;
+        unsigned long long      sc_regs[32];
+        unsigned long long      sc_fpregs[32];
+        unsigned int            sc_acx;         /* Was sc_ownedfp */
+        unsigned int            sc_fpc_csr;
+        unsigned int            sc_fpc_eir;     /* Unused */
+        unsigned int            sc_used_math;
+        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
+        unsigned long long      sc_mdhi;
+        unsigned long long      sc_mdlo;
+        unsigned long           sc_hi1;         /* Was sc_cause */
+        unsigned long           sc_lo1;         /* Was sc_badvaddr */
+        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
+        unsigned long           sc_lo2;
+        unsigned long           sc_hi3;
+        unsigned long           sc_lo3;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#include <linux/posix_types.h>
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/kernel/asm-offsets.c
+ *
+ * Warning: this structure illdefined with sc_badvaddr being just an unsigned
+ * int so it was changed to unsigned long in 2.6.0-test1.  This may break
+ * binary compatibility - no prisoners.
+ * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
+ * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
+ */
+struct sigcontext {
+        __u64   sc_regs[32];
+        __u64   sc_fpregs[32];
+        __u64   sc_mdhi;
+        __u64   sc_hi1;
+        __u64   sc_hi2;
+        __u64   sc_hi3;
+        __u64   sc_mdlo;
+        __u64   sc_lo1;
+        __u64   sc_lo2;
+        __u64   sc_lo3;
+        __u64   sc_pc;
+        __u32   sc_fpc_csr;
+        __u32   sc_used_math;
+        __u32   sc_dsp;
+        __u32   sc_reserved;
+};
+
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _UAPI_ASM_SIGCONTEXT_H */
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
new file mode 100644
index 000000000..c34c7eef0
--- /dev/null
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_SIGINFO_H
+#define _UAPI_ASM_SIGINFO_H
+
+
+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
+#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
+
+#define __ARCH_HAS_SWAPPED_SIGINFO
+
+#include <asm-generic/siginfo.h>
+
+/*
+ * si_code values
+ * Again these have been chosen to be IRIX compatible.
+ */
+#undef SI_ASYNCIO
+#undef SI_TIMER
+#undef SI_MESGQ
+#define SI_ASYNCIO      -2      /* sent by AIO completion */
+#define SI_TIMER        -3      /* sent by timer expiration */
+#define SI_MESGQ        -4      /* sent by real time mesq state change */
+
+#endif /* _UAPI_ASM_SIGINFO_H */
diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
new file mode 100644
index 000000000..53104b10a
--- /dev/null
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_SIGNAL_H
+#define _UAPI_ASM_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG           128
+#define _NSIG_BPW       (sizeof(unsigned long) * 8)
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+#define SIGHUP           1      /* Hangup (POSIX).  */
+#define SIGINT           2      /* Interrupt (ANSI).  */
+#define SIGQUIT          3      /* Quit (POSIX).  */
+#define SIGILL           4      /* Illegal instruction (ANSI).  */
+#define SIGTRAP          5      /* Trace trap (POSIX).  */
+#define SIGIOT           6      /* IOT trap (4.2 BSD).  */
+#define SIGABRT          SIGIOT /* Abort (ANSI).  */
+#define SIGEMT           7
+#define SIGFPE           8      /* Floating-point exception (ANSI).  */
+#define SIGKILL          9      /* Kill, unblockable (POSIX).  */
+#define SIGBUS          10      /* BUS error (4.2 BSD).  */
+#define SIGSEGV         11      /* Segmentation violation (ANSI).  */
+#define SIGSYS          12
+#define SIGPIPE         13      /* Broken pipe (POSIX).  */
+#define SIGALRM         14      /* Alarm clock (POSIX).  */
+#define SIGTERM         15      /* Termination (ANSI).  */
+#define SIGUSR1         16      /* User-defined signal 1 (POSIX).  */
+#define SIGUSR2         17      /* User-defined signal 2 (POSIX).  */
+#define SIGCHLD         18      /* Child status has changed (POSIX).  */
+#define SIGCLD          SIGCHLD /* Same as SIGCHLD (System V).  */
+#define SIGPWR          19      /* Power failure restart (System V).  */
+#define SIGWINCH        20      /* Window size change (4.3 BSD, Sun).  */
+#define SIGURG          21      /* Urgent condition on socket (4.2 BSD).  */
+#define SIGIO           22      /* I/O now possible (4.2 BSD).  */
+#define SIGPOLL         SIGIO   /* Pollable event occurred (System V).  */
+#define SIGSTOP         23      /* Stop, unblockable (POSIX).  */
+#define SIGTSTP         24      /* Keyboard stop (POSIX).  */
+#define SIGCONT         25      /* Continue (POSIX).  */
+#define SIGTTIN         26      /* Background read from tty (POSIX).  */
+#define SIGTTOU         27      /* Background write to tty (POSIX).  */
+#define SIGVTALRM       28      /* Virtual alarm clock (4.2 BSD).  */
+#define SIGPROF         29      /* Profiling alarm clock (4.2 BSD).  */
+#define SIGXCPU         30      /* CPU limit exceeded (4.2 BSD).  */
+#define SIGXFSZ         31      /* File size limit exceeded (4.2 BSD).  */
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ *
+ * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
+ * supported its use and no libc was using it, so the entire sa-restorer
+ * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
+ * retaining only the SA_RESTORER definition as a reminder to avoid
+ * accidental reuse of the mask bit.
+ */
+#define SA_ONSTACK      0x08000000
+#define SA_RESETHAND    0x80000000
+#define SA_RESTART      0x10000000
+#define SA_SIGINFO      0x00000008
+#define SA_NODEFER      0x40000000
+#define SA_NOCLDWAIT    0x00010000
+#define SA_NOCLDSTOP    0x00000001
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define MINSIGSTKSZ    2048
+#define SIGSTKSZ       8192
+
+
+#define SIG_BLOCK       1       /* for blocking signals */
+#define SIG_UNBLOCK     2       /* for unblocking signals */
+#define SIG_SETMASK     3       /* for setting the signal mask */
+
+#include <asm-generic/signal-defs.h>
+
+#ifndef __KERNEL__
+struct sigaction {
+        unsigned int    sa_flags;
+        __sighandler_t  sa_handler;
+        sigset_t        sa_mask;
+};
+#endif
+
+/* IRIX compatible stack_t  */
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        size_t ss_size;
+        int ss_flags;
+} stack_t;
+
+
+#endif /* _UAPI_ASM_SIGNAL_H */
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
new file mode 100644
index 000000000..d0a9ed2ca
--- /dev/null
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_SOCKET_H
+#define _UAPI_ASM_SOCKET_H
+
+#include <linux/posix_types.h>
+#include <asm/sockios.h>
+
+/*
+ * For setsockopt(2)
+ *
+ * This defines are ABI conformant as far as Linux supports these ...
+ */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001  /* Record debugging information.  */
+#define SO_REUSEADDR    0x0004  /* Allow reuse of local addresses.  */
+#define SO_KEEPALIVE    0x0008  /* Keep connections alive and send
+                                   SIGPIPE when they die.  */
+#define SO_DONTROUTE    0x0010  /* Don't do local routing.  */
+#define SO_BROADCAST    0x0020  /* Allow transmission of
+                                   broadcast messages.  */
+#define SO_LINGER       0x0080  /* Block on close of a reliable
+                                   socket to transmit pending data.  */
+#define SO_OOBINLINE 0x0100     /* Receive out-of-band data in-band.  */
+#define SO_REUSEPORT 0x0200     /* Allow local address and port reuse.  */
+
+#define SO_TYPE         0x1008  /* Compatible name for SO_STYLE.  */
+#define SO_STYLE        SO_TYPE /* Synonym */
+#define SO_ERROR        0x1007  /* get error status and clear */
+#define SO_SNDBUF       0x1001  /* Send buffer size. */
+#define SO_RCVBUF       0x1002  /* Receive buffer. */
+#define SO_SNDLOWAT     0x1003  /* send low-water mark */
+#define SO_RCVLOWAT     0x1004  /* receive low-water mark */
+#define SO_SNDTIMEO_OLD 0x1005  /* send timeout */
+#define SO_RCVTIMEO_OLD 0x1006  /* receive timeout */
+#define SO_ACCEPTCONN   0x1009
+#define SO_PROTOCOL     0x1028  /* protocol type */
+#define SO_DOMAIN       0x1029  /* domain/socket family */
+
+/* linux-specific, might as well be the same as on i386 */
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_BSDCOMPAT    14
+
+#define SO_PASSCRED     17
+#define SO_PEERCRED     18
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE         25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+#define SO_GET_FILTER           SO_ATTACH_FILTER
+
+#define SO_PEERNAME             28
+
+#define SO_PEERSEC              30
+#define SO_SNDBUFFORCE          31
+#define SO_RCVBUFFORCE          33
+#define SO_PASSSEC              34
+
+#define SO_MARK                 36
+
+#define SO_RXQ_OVFL             40
+
+#define SO_WIFI_STATUS          41
+#define SCM_WIFI_STATUS         SO_WIFI_STATUS
+#define SO_PEEK_OFF             42
+
+/* Instruct lower device to use last 4-bytes of skb data as FCS */
+#define SO_NOFCS                43
+
+#define SO_LOCK_FILTER          44
+
+#define SO_SELECT_ERR_QUEUE     45
+
+#define SO_BUSY_POLL            46
+
+#define SO_MAX_PACING_RATE      47
+
+#define SO_BPF_EXTENSIONS       48
+
+#define SO_INCOMING_CPU         49
+
+#define SO_ATTACH_BPF           50
+#define SO_DETACH_BPF           SO_DETACH_FILTER
+
+#define SO_ATTACH_REUSEPORT_CBPF        51
+#define SO_ATTACH_REUSEPORT_EBPF        52
+
+#define SO_CNX_ADVICE           53
+
+#define SCM_TIMESTAMPING_OPT_STATS      54
+
+#define SO_MEMINFO              55
+
+#define SO_INCOMING_NAPI_ID     56
+
+#define SO_COOKIE               57
+
+#define SCM_TIMESTAMPING_PKTINFO        58
+
+#define SO_PEERGROUPS           59
+
+#define SO_ZEROCOPY             60
+
+#define SO_TXTIME               61
+#define SCM_TXTIME              SO_TXTIME
+
+#define SO_BINDTOIFINDEX        62
+
+#define SO_TIMESTAMP_OLD        29
+#define SO_TIMESTAMPNS_OLD      35
+#define SO_TIMESTAMPING_OLD     37
+
+#define SO_TIMESTAMP_NEW        63
+#define SO_TIMESTAMPNS_NEW      64
+#define SO_TIMESTAMPING_NEW     65
+
+#define SO_RCVTIMEO_NEW         66
+#define SO_SNDTIMEO_NEW         67
+
+#define SO_DETACH_REUSEPORT_BPF 68
+
+#if !defined(__KERNEL__)
+
+#if __BITS_PER_LONG == 64
+#define SO_TIMESTAMP            SO_TIMESTAMP_OLD
+#define SO_TIMESTAMPNS          SO_TIMESTAMPNS_OLD
+#define SO_TIMESTAMPING         SO_TIMESTAMPING_OLD
+
+#define SO_RCVTIMEO             SO_RCVTIMEO_OLD
+#define SO_SNDTIMEO             SO_SNDTIMEO_OLD
+#else
+#define SO_TIMESTAMP (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_TIMESTAMP_OLD : SO_TIMESTAMP_NEW)
+#define SO_TIMESTAMPNS (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_TIMESTAMPNS_OLD : SO_TIMESTAMPNS_NEW)
+#define SO_TIMESTAMPING (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_TIMESTAMPING_OLD : SO_TIMESTAMPING_NEW)
+
+#define SO_RCVTIMEO (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_RCVTIMEO_OLD : SO_RCVTIMEO_NEW)
+#define SO_SNDTIMEO (sizeof(time_t) == sizeof(__kernel_long_t) ? SO_SNDTIMEO_OLD : SO_SNDTIMEO_NEW)
+#endif
+
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+#define SCM_TIMESTAMPING        SO_TIMESTAMPING
+
+#endif
+
+#endif /* _UAPI_ASM_SOCKET_H */
diff --git a/arch/mips/include/uapi/asm/sockios.h b/arch/mips/include/uapi/asm/sockios.h
new file mode 100644
index 000000000..66f60234f
--- /dev/null
+++ b/arch/mips/include/uapi/asm/sockios.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Socket-level I/O control calls.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SOCKIOS_H
+#define _ASM_SOCKIOS_H
+
+#include <asm/ioctl.h>
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP_OLD  0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS_OLD 0x8907         /* Get stamp (timespec) */
+
+#endif /* _ASM_SOCKIOS_H */
diff --git a/arch/mips/include/uapi/asm/stat.h b/arch/mips/include/uapi/asm/stat.h
new file mode 100644
index 000000000..3d2a3b718
--- /dev/null
+++ b/arch/mips/include/uapi/asm/stat.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_STAT_H
+#define _ASM_STAT_H
+
+#include <linux/types.h>
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+struct stat {
+        unsigned        st_dev;
+        long            st_pad1[3];             /* Reserved for network id */
+        ino_t           st_ino;
+        mode_t          st_mode;
+        __u32           st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned        st_rdev;
+        long            st_pad2[2];
+        long            st_size;
+        long            st_pad3;
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        long            st_atime;
+        long            st_atime_nsec;
+        long            st_mtime;
+        long            st_mtime_nsec;
+        long            st_ctime;
+        long            st_ctime_nsec;
+        long            st_blksize;
+        long            st_blocks;
+        long            st_pad4[14];
+};
+
+/*
+ * This matches struct stat64 in glibc2.1, hence the absolutely insane
+ * amounts of padding around dev_t's.  The memory layout is the same as of
+ * struct stat of the 64-bit kernel.
+ */
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_pad0[3];     /* Reserved for st_dev expansion  */
+
+        unsigned long long      st_ino;
+
+        mode_t          st_mode;
+        __u32           st_nlink;
+
+        uid_t           st_uid;
+        gid_t           st_gid;
+
+        unsigned long   st_rdev;
+        unsigned long   st_pad1[3];     /* Reserved for st_rdev expansion  */
+
+        long long       st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        long            st_atime;
+        unsigned long   st_atime_nsec;  /* Reserved for st_atime expansion  */
+
+        long            st_mtime;
+        unsigned long   st_mtime_nsec;  /* Reserved for st_mtime expansion  */
+
+        long            st_ctime;
+        unsigned long   st_ctime_nsec;  /* Reserved for st_ctime expansion  */
+
+        unsigned long   st_blksize;
+        unsigned long   st_pad2;
+
+        long long       st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/* The memory layout is the same as of struct stat64 of the 32-bit kernel.  */
+struct stat {
+        unsigned int            st_dev;
+        unsigned int            st_pad0[3]; /* Reserved for st_dev expansion */
+
+        unsigned long           st_ino;
+
+        mode_t                  st_mode;
+        __u32                   st_nlink;
+
+        uid_t                   st_uid;
+        gid_t                   st_gid;
+
+        unsigned int            st_rdev;
+        unsigned int            st_pad1[3]; /* Reserved for st_rdev expansion */
+
+        long                    st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        unsigned int            st_atime;
+        unsigned int            st_atime_nsec;
+
+        unsigned int            st_mtime;
+        unsigned int            st_mtime_nsec;
+
+        unsigned int            st_ctime;
+        unsigned int            st_ctime_nsec;
+
+        unsigned int            st_blksize;
+        unsigned int            st_pad2;
+
+        unsigned long           st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define STAT_HAVE_NSEC 1
+
+#endif /* _ASM_STAT_H */
diff --git a/arch/mips/include/uapi/asm/statfs.h b/arch/mips/include/uapi/asm/statfs.h
new file mode 100644
index 000000000..f4174dcae
--- /dev/null
+++ b/arch/mips/include/uapi/asm/statfs.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_STATFS_H
+#define _ASM_STATFS_H
+
+#include <linux/posix_types.h>
+#include <asm/sgidefs.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t        fsid_t;
+
+#endif
+
+struct statfs {
+        long            f_type;
+#define f_fstyp f_type
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_flags;
+        long            f_spare[5];
+};
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+/*
+ * Unlike the traditional version the LFAPI version has none of the ABI junk
+ */
+struct statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_flags;
+        __u32   f_spare[5];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+struct statfs64 {                       /* Same as struct statfs */
+        long            f_type;
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_flags;
+        long            f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_flags;
+        __u32   f_spare[5];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#endif /* _ASM_STATFS_H */
diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h
new file mode 100644
index 000000000..d6795fe4e
--- /dev/null
+++ b/arch/mips/include/uapi/asm/swab.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_SWAB_H
+#define _ASM_SWAB_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define __SWAB_64_THRU_32__
+
+#if !defined(__mips16) &&                                       \
+        ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) ||  \
+         defined(_MIPS_ARCH_LOONGSON3A))
+
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
+{
+        __asm__(
+        "       .set    push                    \n"
+        "       .set    arch=mips32r2           \n"
+        "       wsbh    %0, %1                  \n"
+        "       .set    pop                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab16 __arch_swab16
+
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
+{
+        __asm__(
+        "       .set    push                    \n"
+        "       .set    arch=mips32r2           \n"
+        "       wsbh    %0, %1                  \n"
+        "       rotr    %0, %0, 16              \n"
+        "       .set    pop                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab32 __arch_swab32
+
+/*
+ * Having already checked for MIPS R2, enable the optimized version for
+ * 64-bit kernel on r2 CPUs.
+ */
+#ifdef __mips64
+static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
+{
+        __asm__(
+        "       .set    push                    \n"
+        "       .set    arch=mips64r2           \n"
+        "       dsbh    %0, %1                  \n"
+        "       dshd    %0, %0                  \n"
+        "       .set    pop                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab64 __arch_swab64
+#endif /* __mips64 */
+#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */
+#endif /* _ASM_SWAB_H */
diff --git a/arch/mips/include/uapi/asm/sysmips.h b/arch/mips/include/uapi/asm/sysmips.h
new file mode 100644
index 000000000..4c009e10d
--- /dev/null
+++ b/arch/mips/include/uapi/asm/sysmips.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Definitions for the MIPS sysmips(2) call
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SYSMIPS_H
+#define _ASM_SYSMIPS_H
+
+/*
+ * Commands for the sysmips(2) call
+ *
+ * sysmips(2) is deprecated - though some existing software uses it.
+ * We only support the following commands.
+ */
+#define SETNAME                    1    /* set hostname                  */
+#define FLUSH_CACHE                3    /* writeback and invalidate caches */
+#define MIPS_FIXADE                7    /* control address error fixing  */
+#define MIPS_RDNVRAM              10    /* read NVRAM */
+#define MIPS_ATOMIC_SET         2001    /* atomically set variable       */
+
+#endif /* _ASM_SYSMIPS_H */
diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h
new file mode 100644
index 000000000..dfeffba72
--- /dev/null
+++ b/arch/mips/include/uapi/asm/termbits.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_TERMBITS_H
+#define _ASM_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+/*
+ * The ABI says nothing about NCC but seems to use NCCS as
+ * replacement for it in struct termio
+ */
+#define NCCS    23
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR            0              /* Interrupt character [ISIG].  */
+#define VQUIT            1              /* Quit character [ISIG].  */
+#define VERASE           2              /* Erase character [ICANON].  */
+#define VKILL            3              /* Kill-line character [ICANON].  */
+#define VMIN             4              /* Minimum number of bytes read at once [!ICANON].  */
+#define VTIME            5              /* Time-out value (tenths of a second) [!ICANON].  */
+#define VEOL2            6              /* Second EOL character [ICANON].  */
+#define VSWTC            7              /* ??? */
+#define VSWTCH          VSWTC
+#define VSTART           8              /* Start (X-ON) character [IXON, IXOFF].  */
+#define VSTOP            9              /* Stop (X-OFF) character [IXON, IXOFF].  */
+#define VSUSP           10              /* Suspend character [ISIG].  */
+#if 0
+/*
+ * VDSUSP is not supported
+ */
+#define VDSUSP          11              /* Delayed suspend character [ISIG].  */
+#endif
+#define VREPRINT        12              /* Reprint-line character [ICANON].  */
+#define VDISCARD        13              /* Discard character [IEXTEN].  */
+#define VWERASE         14              /* Word-erase character [ICANON].  */
+#define VLNEXT          15              /* Literal-next character [IEXTEN].  */
+#define VEOF            16              /* End-of-file character [ICANON].  */
+#define VEOL            17              /* End-of-line character [ICANON].  */
+
+/* c_iflag bits */
+#define IGNBRK  0000001         /* Ignore break condition.  */
+#define BRKINT  0000002         /* Signal interrupt on break.  */
+#define IGNPAR  0000004         /* Ignore characters with parity errors.  */
+#define PARMRK  0000010         /* Mark parity and framing errors.  */
+#define INPCK   0000020         /* Enable input parity check.  */
+#define ISTRIP  0000040         /* Strip 8th bit off characters.  */
+#define INLCR   0000100         /* Map NL to CR on input.  */
+#define IGNCR   0000200         /* Ignore CR.  */
+#define ICRNL   0000400         /* Map CR to NL on input.  */
+#define IUCLC   0001000         /* Map upper case to lower case on input.  */
+#define IXON    0002000         /* Enable start/stop output control.  */
+#define IXANY   0004000         /* Any character will restart after stop.  */
+#define IXOFF   0010000         /* Enable start/stop input control.  */
+#define IMAXBEL 0020000         /* Ring bell when input queue is full.  */
+#define IUTF8   0040000         /* Input is UTF-8 */
+
+/* c_oflag bits */
+#define OPOST   0000001         /* Perform output processing.  */
+#define OLCUC   0000002         /* Map lower case to upper case on output.  */
+#define ONLCR   0000004         /* Map NL to CR-NL on output.  */
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+/*
+#define PAGEOUT ???
+#define WRAP    ???
+ */
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060         /* Number of bits per byte (mask).  */
+#define   CS5   0000000         /* 5 bits per byte.  */
+#define   CS6   0000020         /* 6 bits per byte.  */
+#define   CS7   0000040         /* 7 bits per byte.  */
+#define   CS8   0000060         /* 8 bits per byte.  */
+#define CSTOPB  0000100         /* Two stop bits instead of one.  */
+#define CREAD   0000200         /* Enable receiver.  */
+#define PARENB  0000400         /* Parity enable.  */
+#define PARODD  0001000         /* Odd parity instead of even.  */
+#define HUPCL   0002000         /* Hang up on last close.  */
+#define CLOCAL  0004000         /* Ignore modem status lines.  */
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate */
+#define CMSPAR    010000000000  /* mark or space (stick) parity */
+#define CRTSCTS   020000000000  /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001         /* Enable signals.  */
+#define ICANON  0000002         /* Do erase and kill processing.  */
+#define XCASE   0000004
+#define ECHO    0000010         /* Enable echo.  */
+#define ECHOE   0000020         /* Visual erase for ERASE.  */
+#define ECHOK   0000040         /* Echo NL after KILL.  */
+#define ECHONL  0000100         /* Echo NL even if ECHO is off.  */
+#define NOFLSH  0000200         /* Disable flush after interrupt.  */
+#define IEXTEN  0000400         /* Enable DISCARD and LNEXT.  */
+#define ECHOCTL 0001000         /* Echo control characters as ^X.  */
+#define ECHOPRT 0002000         /* Hardcopy visual erase.  */
+#define ECHOKE  0004000         /* Visual erase for KILL.  */
+#define FLUSHO  0020000
+#define PENDIN  0040000         /* Retype pending input (state).  */
+#define TOSTOP  0100000         /* Send SIGTTOU for background output.  */
+#define ITOSTOP TOSTOP
+#define EXTPROC 0200000         /* External processing on pty */
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0       /* Suspend output.  */
+#define TCOON           1       /* Restart suspended output.  */
+#define TCIOFF          2       /* Send a STOP character.  */
+#define TCION           3       /* Send a START character.  */
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0       /* Discard data received but not yet read.  */
+#define TCOFLUSH        1       /* Discard data written but not yet sent.  */
+#define TCIOFLUSH       2       /* Discard all pending data.  */
+
+/* tcsetattr uses these */
+#define TCSANOW         TCSETS  /* Change immediately.  */
+#define TCSADRAIN       TCSETSW /* Change when pending output is written.  */
+#define TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
+
+#endif /* _ASM_TERMBITS_H */
diff --git a/arch/mips/include/uapi/asm/termios.h b/arch/mips/include/uapi/asm/termios.h
new file mode 100644
index 000000000..d6c576794
--- /dev/null
+++ b/arch/mips/include/uapi/asm/termios.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_TERMIOS_H
+#define _UAPI_ASM_TERMIOS_H
+
+#include <linux/errno.h>
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        int     sg_flags;       /* SGI special - int, not short */
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;        /* stop process signal */
+        char    t_dsuspc;       /* delayed stop process signal */
+        char    t_rprntc;       /* reprint line */
+        char    t_flushc;       /* flush output (toggles) */
+        char    t_werasc;       /* word erase */
+        char    t_lnextc;       /* literal next character */
+};
+
+/* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
+   compatibility anyway ... */
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC     8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        char c_line;                    /* line discipline */
+        unsigned char c_cc[NCCS];       /* control characters */
+};
+
+
+/* modem lines */
+#define TIOCM_LE        0x001           /* line enable */
+#define TIOCM_DTR       0x002           /* data terminal ready */
+#define TIOCM_RTS       0x004           /* request to send */
+#define TIOCM_ST        0x010           /* secondary transmit */
+#define TIOCM_SR        0x020           /* secondary receive */
+#define TIOCM_CTS       0x040           /* clear to send */
+#define TIOCM_CAR       0x100           /* carrier detect */
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RNG       0x200           /* ring */
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_DSR       0x400           /* data set ready */
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+
+#endif /* _UAPI_ASM_TERMIOS_H */
diff --git a/arch/mips/include/uapi/asm/types.h b/arch/mips/include/uapi/asm/types.h
new file mode 100644
index 000000000..6b2150484
--- /dev/null
+++ b/arch/mips/include/uapi/asm/types.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 2008 Wind River Systems,
+ *   written by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _UAPI_ASM_TYPES_H
+#define _UAPI_ASM_TYPES_H
+
+/*
+ * We don't use int-l64.h for the kernel anymore but still use it for
+ * userspace to avoid code changes.
+ *
+ * However, some user programs (e.g. perf) may not want this. They can
+ * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
+ */
+#ifndef __KERNEL__
+# if _MIPS_SZLONG == 64 && !defined(__SANE_USERSPACE_TYPES__)
+#  include <asm-generic/int-l64.h>
+# else
+#  include <asm-generic/int-ll64.h>
+# endif
+#endif
+
+
+#endif /* _UAPI_ASM_TYPES_H */
diff --git a/arch/mips/include/uapi/asm/ucontext.h b/arch/mips/include/uapi/asm/ucontext.h
new file mode 100644
index 000000000..2d3bf8eeb
--- /dev/null
+++ b/arch/mips/include/uapi/asm/ucontext.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __MIPS_UAPI_ASM_UCONTEXT_H
+#define __MIPS_UAPI_ASM_UCONTEXT_H
+
+/**
+ * struct extcontext - extended context header structure
+ * @magic:      magic value identifying the type of extended context
+ * @size:       the size in bytes of the enclosing structure
+ *
+ * Extended context structures provide context which does not fit within struct
+ * sigcontext. They are placed sequentially in memory at the end of struct
+ * ucontext and struct sigframe, with each extended context structure beginning
+ * with a header defined by this struct. The type of context represented is
+ * indicated by the magic field. Userland may check each extended context
+ * structure against magic values that it recognises. The size field allows any
+ * unrecognised context to be skipped, allowing for future expansion. The end
+ * of the extended context data is indicated by the magic value
+ * END_EXTCONTEXT_MAGIC.
+ */
+struct extcontext {
+        unsigned int            magic;
+        unsigned int            size;
+};
+
+/**
+ * struct msa_extcontext - MSA extended context structure
+ * @ext:        the extended context header, with magic == MSA_EXTCONTEXT_MAGIC
+ * @wr:         the most significant 64 bits of each MSA vector register
+ * @csr:        the value of the MSA control & status register
+ *
+ * If MSA context is live for a task at the time a signal is delivered to it,
+ * this structure will hold the MSA context of the task as it was prior to the
+ * signal delivery.
+ */
+struct msa_extcontext {
+        struct extcontext       ext;
+#define MSA_EXTCONTEXT_MAGIC    0x784d5341      /* xMSA */
+
+        unsigned long long      wr[32];
+        unsigned int            csr;
+};
+
+#define END_EXTCONTEXT_MAGIC    0x78454e44      /* xEND */
+
+/**
+ * struct ucontext - user context structure
+ * @uc_flags:
+ * @uc_link:
+ * @uc_stack:
+ * @uc_mcontext:        holds basic processor state
+ * @uc_sigmask:
+ * @uc_extcontext:      holds extended processor state
+ */
+struct ucontext {
+        /* Historic fields matching asm-generic */
+        unsigned long           uc_flags;
+        struct ucontext         *uc_link;
+        stack_t                 uc_stack;
+        struct sigcontext       uc_mcontext;
+        sigset_t                uc_sigmask;
+
+        /* Extended context structures may follow ucontext */
+        unsigned long long      uc_extcontext[0];
+};
+
+#endif /* __MIPS_UAPI_ASM_UCONTEXT_H */
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
new file mode 100644
index 000000000..4abe38754
--- /dev/null
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
+ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
+ */
+#ifndef _UAPI_ASM_UNISTD_H
+#define _UAPI_ASM_UNISTD_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+#define __NR_Linux      4000
+#include <asm/unistd_o32.h>
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+#define __NR_Linux      5000
+#include <asm/unistd_n64.h>
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define __NR_Linux      6000
+#include <asm/unistd_n32.h>
+
+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _UAPI_ASM_UNISTD_H */