Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release

1 files changed, 65 insertions, 0 deletions

diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
new file mode 100644
index 000000000..bad740ad3
--- /dev/null
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  DEC I/O ASIC's counter clocksource
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#include <linux/clocksource.h>
+#include <linux/sched_clock.h>
+#include <linux/init.h>
+
+#include <asm/ds1287.h>
+#include <asm/time.h>
+#include <asm/dec/ioasic.h>
+#include <asm/dec/ioasic_addrs.h>
+
+static u64 dec_ioasic_hpt_read(struct clocksource *cs)
+{
+        return ioasic_read(IO_REG_FCTR);
+}
+
+static struct clocksource clocksource_dec = {
+        .name           = "dec-ioasic",
+        .read           = dec_ioasic_hpt_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static u64 notrace dec_ioasic_read_sched_clock(void)
+{
+        return ioasic_read(IO_REG_FCTR);
+}
+
+int __init dec_ioasic_clocksource_init(void)
+{
+        unsigned int freq;
+        u32 start, end;
+        int i = HZ / 8;
+
+        ds1287_timer_state();
+        while (!ds1287_timer_state())
+                ;
+
+        start = dec_ioasic_hpt_read(&clocksource_dec);
+
+        while (i--)
+                while (!ds1287_timer_state())
+                        ;
+
+        end = dec_ioasic_hpt_read(&clocksource_dec);
+
+        freq = (end - start) * 8;
+
+        /* An early revision of the I/O ASIC didn't have the counter.  */
+        if (!freq)
+                return -ENXIO;
+
+        printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
+
+        clocksource_dec.rating = 200 + freq / 10000000;
+        clocksource_register_hz(&clocksource_dec, freq);
+
+        sched_clock_register(dec_ioasic_read_sched_clock, 32, freq);
+
+        return 0;
+}