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authorWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
committerWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
commita07bb8fd1299070229f0e8f3dcb57ffd5ef9870a (patch)
tree84f21bd0bf7071bc5fc7dd989e77d7ceb5476682 /arch/mips/ralink
downloadohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.tar.gz
ohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.zip
Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release
Diffstat (limited to 'arch/mips/ralink')
-rw-r--r--arch/mips/ralink/Kconfig103
-rw-r--r--arch/mips/ralink/Makefile28
-rw-r--r--arch/mips/ralink/Platform33
-rw-r--r--arch/mips/ralink/bootrom.c40
-rw-r--r--arch/mips/ralink/cevt-rt3352.c153
-rw-r--r--arch/mips/ralink/clk.c87
-rw-r--r--arch/mips/ralink/common.h34
-rw-r--r--arch/mips/ralink/early_printk.c88
-rw-r--r--arch/mips/ralink/ill_acc.c88
-rw-r--r--arch/mips/ralink/irq-gic.c23
-rw-r--r--arch/mips/ralink/irq.c204
-rw-r--r--arch/mips/ralink/mt7620.c718
-rw-r--r--arch/mips/ralink/mt7621.c211
-rw-r--r--arch/mips/ralink/of.c106
-rw-r--r--arch/mips/ralink/prom.c72
-rw-r--r--arch/mips/ralink/reset.c104
-rw-r--r--arch/mips/ralink/rt288x.c111
-rw-r--r--arch/mips/ralink/rt305x.c278
-rw-r--r--arch/mips/ralink/rt3883.c148
-rw-r--r--arch/mips/ralink/timer-gic.c22
-rw-r--r--arch/mips/ralink/timer.c151
21 files changed, 2802 insertions, 0 deletions
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
new file mode 100644
index 000000000..c10d8b233
--- /dev/null
+++ b/arch/mips/ralink/Kconfig
@@ -0,0 +1,103 @@
1# SPDX-License-Identifier: GPL-2.0
2if RALINK
3
4config CLKEVT_RT3352
5 bool
6 depends on SOC_RT305X || SOC_MT7620
7 default y
8 select TIMER_OF
9 select CLKSRC_MMIO
10
11config RALINK_ILL_ACC
12 bool
13 depends on SOC_RT305X
14 default y
15
16config IRQ_INTC
17 bool
18 default y
19 depends on !SOC_MT7621
20
21choice
22 prompt "Ralink SoC selection"
23 default SOC_RT305X
24 help
25 Select Ralink MIPS SoC type.
26
27 config SOC_RT288X
28 bool "RT288x"
29 select MIPS_L1_CACHE_SHIFT_4
30 select HAVE_LEGACY_CLK
31 select HAVE_PCI
32
33 config SOC_RT305X
34 bool "RT305x"
35 select HAVE_LEGACY_CLK
36
37 config SOC_RT3883
38 bool "RT3883"
39 select HAVE_LEGACY_CLK
40 select HAVE_PCI
41
42 config SOC_MT7620
43 bool "MT7620/8"
44 select CPU_MIPSR2_IRQ_VI
45 select HAVE_LEGACY_CLK
46 select HAVE_PCI
47
48 config SOC_MT7621
49 bool "MT7621"
50 select MIPS_CPU_SCACHE
51 select SYS_SUPPORTS_MULTITHREADING
52 select SYS_SUPPORTS_SMP
53 select SYS_SUPPORTS_MIPS_CPS
54 select SYS_SUPPORTS_HIGHMEM
55 select MIPS_GIC
56 select COMMON_CLK
57 select CLKSRC_MIPS_GIC
58 select HAVE_PCI if PCI_MT7621
59 select SOC_BUS
60endchoice
61
62choice
63 prompt "Devicetree selection"
64 default DTB_RT_NONE
65 help
66 Select the devicetree.
67
68 config DTB_RT_NONE
69 bool "None"
70
71 config DTB_RT2880_EVAL
72 bool "RT2880 eval kit"
73 depends on SOC_RT288X
74 select BUILTIN_DTB
75
76 config DTB_RT305X_EVAL
77 bool "RT305x eval kit"
78 depends on SOC_RT305X
79 select BUILTIN_DTB
80
81 config DTB_RT3883_EVAL
82 bool "RT3883 eval kit"
83 depends on SOC_RT3883
84 select BUILTIN_DTB
85
86 config DTB_MT7620A_EVAL
87 bool "MT7620A eval kit"
88 depends on SOC_MT7620
89 select BUILTIN_DTB
90
91 config DTB_OMEGA2P
92 bool "Onion Omega2+"
93 depends on SOC_MT7620
94 select BUILTIN_DTB
95
96 config DTB_VOCORE2
97 bool "VoCore2"
98 depends on SOC_MT7620
99 select BUILTIN_DTB
100
101endchoice
102
103endif
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
new file mode 100644
index 000000000..26fabbdea
--- /dev/null
+++ b/arch/mips/ralink/Makefile
@@ -0,0 +1,28 @@
1# SPDX-License-Identifier: GPL-2.0-only
2# Makefile for the Ralink common stuff
3#
4# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5# Copyright (C) 2013 John Crispin <john@phrozen.org>
6
7obj-y := prom.o of.o reset.o
8
9ifndef CONFIG_MIPS_GIC
10 obj-y += clk.o timer.o
11endif
12
13obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
14
15obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
16
17obj-$(CONFIG_IRQ_INTC) += irq.o
18obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
19
20obj-$(CONFIG_SOC_RT288X) += rt288x.o
21obj-$(CONFIG_SOC_RT305X) += rt305x.o
22obj-$(CONFIG_SOC_RT3883) += rt3883.o
23obj-$(CONFIG_SOC_MT7620) += mt7620.o
24obj-$(CONFIG_SOC_MT7621) += mt7621.o
25
26obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
27
28obj-$(CONFIG_DEBUG_FS) += bootrom.o
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
new file mode 100644
index 000000000..02ee07914
--- /dev/null
+++ b/arch/mips/ralink/Platform
@@ -0,0 +1,33 @@
1#
2# Ralink SoC common stuff
3#
4cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
5
6#
7# Ralink RT288x
8#
9load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
10cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
11
12#
13# Ralink RT305x
14#
15load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
16cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
17
18#
19# Ralink RT3883
20#
21load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
22cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
23
24#
25# Ralink MT7620
26#
27load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
28cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
29
30# Ralink MT7621
31#
32load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
33cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
diff --git a/arch/mips/ralink/bootrom.c b/arch/mips/ralink/bootrom.c
new file mode 100644
index 000000000..94ca8379b
--- /dev/null
+++ b/arch/mips/ralink/bootrom.c
@@ -0,0 +1,40 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2013 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/debugfs.h>
8#include <linux/seq_file.h>
9
10#define BOOTROM_OFFSET 0x10118000
11#define BOOTROM_SIZE 0x8000
12
13static void __iomem *membase = (void __iomem *) KSEG1ADDR(BOOTROM_OFFSET);
14
15static int bootrom_show(struct seq_file *s, void *unused)
16{
17 seq_write(s, membase, BOOTROM_SIZE);
18
19 return 0;
20}
21
22static int bootrom_open(struct inode *inode, struct file *file)
23{
24 return single_open(file, bootrom_show, NULL);
25}
26
27static const struct file_operations bootrom_file_ops = {
28 .open = bootrom_open,
29 .read = seq_read,
30 .llseek = seq_lseek,
31 .release = single_release,
32};
33
34static int __init bootrom_setup(void)
35{
36 debugfs_create_file("bootrom", 0444, NULL, NULL, &bootrom_file_ops);
37 return 0;
38}
39
40postcore_initcall(bootrom_setup);
diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c
new file mode 100644
index 000000000..269d4877d
--- /dev/null
+++ b/arch/mips/ralink/cevt-rt3352.c
@@ -0,0 +1,153 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 by John Crispin <john@phrozen.org>
7 */
8
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/interrupt.h>
12#include <linux/reset.h>
13#include <linux/init.h>
14#include <linux/time.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18
19#include <asm/mach-ralink/ralink_regs.h>
20
21#define SYSTICK_FREQ (50 * 1000)
22
23#define SYSTICK_CONFIG 0x00
24#define SYSTICK_COMPARE 0x04
25#define SYSTICK_COUNT 0x08
26
27/* route systick irq to mips irq 7 instead of the r4k-timer */
28#define CFG_EXT_STK_EN 0x2
29/* enable the counter */
30#define CFG_CNT_EN 0x1
31
32struct systick_device {
33 void __iomem *membase;
34 struct clock_event_device dev;
35 int irq_requested;
36 int freq_scale;
37};
38
39static int systick_set_oneshot(struct clock_event_device *evt);
40static int systick_shutdown(struct clock_event_device *evt);
41
42static int systick_next_event(unsigned long delta,
43 struct clock_event_device *evt)
44{
45 struct systick_device *sdev;
46 u32 count;
47
48 sdev = container_of(evt, struct systick_device, dev);
49 count = ioread32(sdev->membase + SYSTICK_COUNT);
50 count = (count + delta) % SYSTICK_FREQ;
51 iowrite32(count, sdev->membase + SYSTICK_COMPARE);
52
53 return 0;
54}
55
56static void systick_event_handler(struct clock_event_device *dev)
57{
58 /* noting to do here */
59}
60
61static irqreturn_t systick_interrupt(int irq, void *dev_id)
62{
63 struct clock_event_device *dev = (struct clock_event_device *) dev_id;
64
65 dev->event_handler(dev);
66
67 return IRQ_HANDLED;
68}
69
70static struct systick_device systick = {
71 .dev = {
72 /*
73 * cevt-r4k uses 300, make sure systick
74 * gets used if available
75 */
76 .rating = 310,
77 .features = CLOCK_EVT_FEAT_ONESHOT,
78 .set_next_event = systick_next_event,
79 .set_state_shutdown = systick_shutdown,
80 .set_state_oneshot = systick_set_oneshot,
81 .event_handler = systick_event_handler,
82 },
83};
84
85static int systick_shutdown(struct clock_event_device *evt)
86{
87 struct systick_device *sdev;
88
89 sdev = container_of(evt, struct systick_device, dev);
90
91 if (sdev->irq_requested)
92 free_irq(systick.dev.irq, &systick.dev);
93 sdev->irq_requested = 0;
94 iowrite32(0, systick.membase + SYSTICK_CONFIG);
95
96 return 0;
97}
98
99static int systick_set_oneshot(struct clock_event_device *evt)
100{
101 const char *name = systick.dev.name;
102 struct systick_device *sdev;
103 int irq = systick.dev.irq;
104
105 sdev = container_of(evt, struct systick_device, dev);
106
107 if (!sdev->irq_requested) {
108 if (request_irq(irq, systick_interrupt,
109 IRQF_PERCPU | IRQF_TIMER, name, &systick.dev))
110 pr_err("Failed to request irq %d (%s)\n", irq, name);
111 }
112 sdev->irq_requested = 1;
113 iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
114 systick.membase + SYSTICK_CONFIG);
115
116 return 0;
117}
118
119static int __init ralink_systick_init(struct device_node *np)
120{
121 int ret;
122
123 systick.membase = of_iomap(np, 0);
124 if (!systick.membase)
125 return -ENXIO;
126
127 systick.dev.name = np->name;
128 clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
129 systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
130 systick.dev.max_delta_ticks = 0x7fff;
131 systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
132 systick.dev.min_delta_ticks = 0x3;
133 systick.dev.irq = irq_of_parse_and_map(np, 0);
134 if (!systick.dev.irq) {
135 pr_err("%pOFn: request_irq failed", np);
136 return -EINVAL;
137 }
138
139 ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
140 SYSTICK_FREQ, 301, 16,
141 clocksource_mmio_readl_up);
142 if (ret)
143 return ret;
144
145 clockevents_register_device(&systick.dev);
146
147 pr_info("%pOFn: running - mult: %d, shift: %d\n",
148 np, systick.dev.mult, systick.dev.shift);
149
150 return 0;
151}
152
153TIMER_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
new file mode 100644
index 000000000..2f9d5acb3
--- /dev/null
+++ b/arch/mips/ralink/clk.c
@@ -0,0 +1,87 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/clkdev.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15
16#include "common.h"
17
18struct clk {
19 struct clk_lookup cl;
20 unsigned long rate;
21};
22
23void ralink_clk_add(const char *dev, unsigned long rate)
24{
25 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
26
27 if (!clk)
28 panic("failed to add clock");
29
30 clk->cl.dev_id = dev;
31 clk->cl.clk = clk;
32
33 clk->rate = rate;
34
35 clkdev_add(&clk->cl);
36}
37
38/*
39 * Linux clock API
40 */
41int clk_enable(struct clk *clk)
42{
43 return 0;
44}
45EXPORT_SYMBOL_GPL(clk_enable);
46
47void clk_disable(struct clk *clk)
48{
49}
50EXPORT_SYMBOL_GPL(clk_disable);
51
52unsigned long clk_get_rate(struct clk *clk)
53{
54 if (!clk)
55 return 0;
56
57 return clk->rate;
58}
59EXPORT_SYMBOL_GPL(clk_get_rate);
60
61int clk_set_rate(struct clk *clk, unsigned long rate)
62{
63 return -1;
64}
65EXPORT_SYMBOL_GPL(clk_set_rate);
66
67long clk_round_rate(struct clk *clk, unsigned long rate)
68{
69 return -1;
70}
71EXPORT_SYMBOL_GPL(clk_round_rate);
72
73void __init plat_time_init(void)
74{
75 struct clk *clk;
76
77 ralink_of_remap();
78
79 ralink_clk_init();
80 clk = clk_get_sys("cpu", NULL);
81 if (IS_ERR(clk))
82 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
83 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
84 mips_hpt_frequency = clk_get_rate(clk) / 2;
85 clk_put(clk);
86 timer_probe();
87}
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
new file mode 100644
index 000000000..4bc65b7a3
--- /dev/null
+++ b/arch/mips/ralink/common.h
@@ -0,0 +1,34 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2013 John Crispin <john@phrozen.org>
5 */
6
7#ifndef _RALINK_COMMON_H__
8#define _RALINK_COMMON_H__
9
10#define RAMIPS_SYS_TYPE_LEN 32
11
12struct ralink_soc_info {
13 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
14 unsigned char *compatible;
15
16 unsigned long mem_base;
17 unsigned long mem_size;
18 unsigned long mem_size_min;
19 unsigned long mem_size_max;
20};
21extern struct ralink_soc_info soc_info;
22
23extern void ralink_of_remap(void);
24
25extern void ralink_clk_init(void);
26extern void ralink_clk_add(const char *dev, unsigned long rate);
27
28extern void ralink_rst_init(void);
29
30extern void prom_soc_init(struct ralink_soc_info *soc_info);
31
32__iomem void *plat_of_remap_node(const char *node);
33
34#endif /* _RALINK_COMMON_H__ */
diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
new file mode 100644
index 000000000..eb4fac25e
--- /dev/null
+++ b/arch/mips/ralink/early_printk.c
@@ -0,0 +1,88 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 */
6
7#include <linux/io.h>
8#include <linux/serial_reg.h>
9
10#include <asm/addrspace.h>
11#include <asm/setup.h>
12
13#ifdef CONFIG_SOC_RT288X
14#define EARLY_UART_BASE 0x300c00
15#define CHIPID_BASE 0x300004
16#elif defined(CONFIG_SOC_MT7621)
17#define EARLY_UART_BASE 0x1E000c00
18#define CHIPID_BASE 0x1E000004
19#else
20#define EARLY_UART_BASE 0x10000c00
21#define CHIPID_BASE 0x10000004
22#endif
23
24#define MT7628_CHIP_NAME1 0x20203832
25
26#define UART_REG_TX 0x04
27#define UART_REG_LCR 0x0c
28#define UART_REG_LSR 0x14
29#define UART_REG_LSR_RT2880 0x1c
30
31static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
32static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
33static int init_complete;
34
35static inline void uart_w32(u32 val, unsigned reg)
36{
37 __raw_writel(val, uart_membase + reg);
38}
39
40static inline u32 uart_r32(unsigned reg)
41{
42 return __raw_readl(uart_membase + reg);
43}
44
45static inline int soc_is_mt7628(void)
46{
47 return IS_ENABLED(CONFIG_SOC_MT7620) &&
48 (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
49}
50
51static void find_uart_base(void)
52{
53 int i;
54
55 if (!soc_is_mt7628())
56 return;
57
58 for (i = 0; i < 3; i++) {
59 u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
60
61 if (!reg)
62 continue;
63
64 uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE +
65 (0x100 * i));
66 break;
67 }
68}
69
70void prom_putchar(char ch)
71{
72 if (!init_complete) {
73 find_uart_base();
74 init_complete = 1;
75 }
76
77 if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
78 uart_w32((unsigned char)ch, UART_TX);
79 while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
80 ;
81 } else {
82 while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
83 ;
84 uart_w32((unsigned char)ch, UART_REG_TX);
85 while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
86 ;
87 }
88}
diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
new file mode 100644
index 000000000..bea857c9d
--- /dev/null
+++ b/arch/mips/ralink/ill_acc.c
@@ -0,0 +1,88 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2013 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/interrupt.h>
8#include <linux/of_platform.h>
9#include <linux/of_irq.h>
10
11#include <asm/mach-ralink/ralink_regs.h>
12
13#define REG_ILL_ACC_ADDR 0x10
14#define REG_ILL_ACC_TYPE 0x14
15
16#define ILL_INT_STATUS BIT(31)
17#define ILL_ACC_WRITE BIT(30)
18#define ILL_ACC_LEN_M 0xff
19#define ILL_ACC_OFF_M 0xf
20#define ILL_ACC_OFF_S 16
21#define ILL_ACC_ID_M 0x7
22#define ILL_ACC_ID_S 8
23
24#define DRV_NAME "ill_acc"
25
26static const char * const ill_acc_ids[] = {
27 "cpu", "dma", "ppe", "pdma rx", "pdma tx", "pci/e", "wmac", "usb",
28};
29
30static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
31{
32 struct device *dev = (struct device *) _priv;
33 u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
34 u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
35
36 dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
37 (type & ILL_ACC_WRITE) ? ("write") : ("read"),
38 ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
39 addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
40 type & ILL_ACC_LEN_M);
41
42 rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
43
44 return IRQ_HANDLED;
45}
46
47static int __init ill_acc_of_setup(void)
48{
49 struct platform_device *pdev;
50 struct device_node *np;
51 int irq;
52
53 /* somehow this driver breaks on RT5350 */
54 if (of_machine_is_compatible("ralink,rt5350-soc"))
55 return -EINVAL;
56
57 np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
58 if (!np)
59 return -EINVAL;
60
61 pdev = of_find_device_by_node(np);
62 if (!pdev) {
63 pr_err("%pOFn: failed to lookup pdev\n", np);
64 of_node_put(np);
65 return -EINVAL;
66 }
67
68 irq = irq_of_parse_and_map(np, 0);
69 if (!irq) {
70 dev_err(&pdev->dev, "failed to get irq\n");
71 put_device(&pdev->dev);
72 return -EINVAL;
73 }
74
75 if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
76 dev_err(&pdev->dev, "failed to request irq\n");
77 put_device(&pdev->dev);
78 return -EINVAL;
79 }
80
81 rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
82
83 dev_info(&pdev->dev, "irq registered\n");
84
85 return 0;
86}
87
88arch_initcall(ill_acc_of_setup);
diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
new file mode 100644
index 000000000..3bab51a5f
--- /dev/null
+++ b/arch/mips/ralink/irq-gic.c
@@ -0,0 +1,23 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/init.h>
9
10#include <linux/of.h>
11#include <linux/irqchip.h>
12#include <asm/mips-cps.h>
13
14int get_c0_perfcount_int(void)
15{
16 return gic_get_c0_perfcount_int();
17}
18EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
19
20void __init arch_init_irq(void)
21{
22 irqchip_init();
23}
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
new file mode 100644
index 000000000..220ca0cd7
--- /dev/null
+++ b/arch/mips/ralink/irq.c
@@ -0,0 +1,204 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/io.h>
9#include <linux/bitops.h>
10#include <linux/of_platform.h>
11#include <linux/of_address.h>
12#include <linux/of_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/interrupt.h>
15
16#include <asm/irq_cpu.h>
17#include <asm/mipsregs.h>
18
19#include "common.h"
20
21#define INTC_INT_GLOBAL BIT(31)
22
23#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
24#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
25#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
26#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
27#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
28
29/* we have a cascade of 8 irqs */
30#define RALINK_INTC_IRQ_BASE 8
31
32/* we have 32 SoC irqs */
33#define RALINK_INTC_IRQ_COUNT 32
34
35#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
36
37enum rt_intc_regs_enum {
38 INTC_REG_STATUS0 = 0,
39 INTC_REG_STATUS1,
40 INTC_REG_TYPE,
41 INTC_REG_RAW_STATUS,
42 INTC_REG_ENABLE,
43 INTC_REG_DISABLE,
44};
45
46static u32 rt_intc_regs[] = {
47 [INTC_REG_STATUS0] = 0x00,
48 [INTC_REG_STATUS1] = 0x04,
49 [INTC_REG_TYPE] = 0x20,
50 [INTC_REG_RAW_STATUS] = 0x30,
51 [INTC_REG_ENABLE] = 0x34,
52 [INTC_REG_DISABLE] = 0x38,
53};
54
55static void __iomem *rt_intc_membase;
56
57static int rt_perfcount_irq;
58
59static inline void rt_intc_w32(u32 val, unsigned reg)
60{
61 __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
62}
63
64static inline u32 rt_intc_r32(unsigned reg)
65{
66 return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
67}
68
69static void ralink_intc_irq_unmask(struct irq_data *d)
70{
71 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
72}
73
74static void ralink_intc_irq_mask(struct irq_data *d)
75{
76 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
77}
78
79static struct irq_chip ralink_intc_irq_chip = {
80 .name = "INTC",
81 .irq_unmask = ralink_intc_irq_unmask,
82 .irq_mask = ralink_intc_irq_mask,
83 .irq_mask_ack = ralink_intc_irq_mask,
84};
85
86int get_c0_perfcount_int(void)
87{
88 return rt_perfcount_irq;
89}
90EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
91
92unsigned int get_c0_compare_int(void)
93{
94 return CP0_LEGACY_COMPARE_IRQ;
95}
96
97static void ralink_intc_irq_handler(struct irq_desc *desc)
98{
99 u32 pending = rt_intc_r32(INTC_REG_STATUS0);
100
101 if (pending) {
102 struct irq_domain *domain = irq_desc_get_handler_data(desc);
103 generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
104 } else {
105 spurious_interrupt();
106 }
107}
108
109asmlinkage void plat_irq_dispatch(void)
110{
111 unsigned long pending;
112
113 pending = read_c0_status() & read_c0_cause() & ST0_IM;
114
115 if (pending & STATUSF_IP7)
116 do_IRQ(RALINK_CPU_IRQ_COUNTER);
117
118 else if (pending & STATUSF_IP5)
119 do_IRQ(RALINK_CPU_IRQ_FE);
120
121 else if (pending & STATUSF_IP6)
122 do_IRQ(RALINK_CPU_IRQ_WIFI);
123
124 else if (pending & STATUSF_IP4)
125 do_IRQ(RALINK_CPU_IRQ_PCI);
126
127 else if (pending & STATUSF_IP2)
128 do_IRQ(RALINK_CPU_IRQ_INTC);
129
130 else
131 spurious_interrupt();
132}
133
134static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
135{
136 irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
137
138 return 0;
139}
140
141static const struct irq_domain_ops irq_domain_ops = {
142 .xlate = irq_domain_xlate_onecell,
143 .map = intc_map,
144};
145
146static int __init intc_of_init(struct device_node *node,
147 struct device_node *parent)
148{
149 struct resource res;
150 struct irq_domain *domain;
151 int irq;
152
153 if (!of_property_read_u32_array(node, "ralink,intc-registers",
154 rt_intc_regs, 6))
155 pr_info("intc: using register map from devicetree\n");
156
157 irq = irq_of_parse_and_map(node, 0);
158 if (!irq)
159 panic("Failed to get INTC IRQ");
160
161 if (of_address_to_resource(node, 0, &res))
162 panic("Failed to get intc memory range");
163
164 if (!request_mem_region(res.start, resource_size(&res),
165 res.name))
166 pr_err("Failed to request intc memory");
167
168 rt_intc_membase = ioremap(res.start,
169 resource_size(&res));
170 if (!rt_intc_membase)
171 panic("Failed to remap intc memory");
172
173 /* disable all interrupts */
174 rt_intc_w32(~0, INTC_REG_DISABLE);
175
176 /* route all INTC interrupts to MIPS HW0 interrupt */
177 rt_intc_w32(0, INTC_REG_TYPE);
178
179 domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
180 RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
181 if (!domain)
182 panic("Failed to add irqdomain");
183
184 rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
185
186 irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain);
187
188 /* tell the kernel which irq is used for performance monitoring */
189 rt_perfcount_irq = irq_create_mapping(domain, 9);
190
191 return 0;
192}
193
194static struct of_device_id __initdata of_irq_ids[] = {
195 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
196 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
197 {},
198};
199
200void __init arch_init_irq(void)
201{
202 of_irq_init(of_irq_ids);
203}
204
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
new file mode 100644
index 000000000..fcf010038
--- /dev/null
+++ b/arch/mips/ralink/mt7620.c
@@ -0,0 +1,718 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/bug.h>
14
15#include <asm/mipsregs.h>
16#include <asm/mach-ralink/ralink_regs.h>
17#include <asm/mach-ralink/mt7620.h>
18#include <asm/mach-ralink/pinmux.h>
19
20#include "common.h"
21
22/* analog */
23#define PMU0_CFG 0x88
24#define PMU_SW_SET BIT(28)
25#define A_DCDC_EN BIT(24)
26#define A_SSC_PERI BIT(19)
27#define A_SSC_GEN BIT(18)
28#define A_SSC_M 0x3
29#define A_SSC_S 16
30#define A_DLY_M 0x7
31#define A_DLY_S 8
32#define A_VTUNE_M 0xff
33
34/* digital */
35#define PMU1_CFG 0x8C
36#define DIG_SW_SEL BIT(25)
37
38/* clock scaling */
39#define CLKCFG_FDIV_MASK 0x1f00
40#define CLKCFG_FDIV_USB_VAL 0x0300
41#define CLKCFG_FFRAC_MASK 0x001f
42#define CLKCFG_FFRAC_USB_VAL 0x0003
43
44/* EFUSE bits */
45#define EFUSE_MT7688 0x100000
46
47/* DRAM type bit */
48#define DRAM_TYPE_MT7628_MASK 0x1
49
50/* does the board have sdram or ddram */
51static int dram_type;
52
53static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
54static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
55static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
56static struct rt2880_pmx_func mdio_grp[] = {
57 FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
58 FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
59};
60static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
61static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
62static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
63static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
64static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
65static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
66static struct rt2880_pmx_func uartf_grp[] = {
67 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
68 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
69 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
70 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
71 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
72 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
73 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
74};
75static struct rt2880_pmx_func wdt_grp[] = {
76 FUNC("wdt rst", 0, 17, 1),
77 FUNC("wdt refclk", 0, 17, 1),
78 };
79static struct rt2880_pmx_func pcie_rst_grp[] = {
80 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
81 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
82};
83static struct rt2880_pmx_func nd_sd_grp[] = {
84 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
85 FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13)
86};
87
88static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
89 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
90 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
91 MT7620_GPIO_MODE_UART0_SHIFT),
92 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
93 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
94 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
95 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
96 GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
97 MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
98 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
99 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
100 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
101 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
102 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
103 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
104 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
105 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
106 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
107 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
108 { 0 }
109};
110
111static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
112 FUNC("sdxc d6", 3, 19, 1),
113 FUNC("utif", 2, 19, 1),
114 FUNC("gpio", 1, 19, 1),
115 FUNC("pwm1", 0, 19, 1),
116};
117
118static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
119 FUNC("sdxc d7", 3, 18, 1),
120 FUNC("utif", 2, 18, 1),
121 FUNC("gpio", 1, 18, 1),
122 FUNC("pwm0", 0, 18, 1),
123};
124
125static struct rt2880_pmx_func uart2_grp_mt7628[] = {
126 FUNC("sdxc d5 d4", 3, 20, 2),
127 FUNC("pwm", 2, 20, 2),
128 FUNC("gpio", 1, 20, 2),
129 FUNC("uart2", 0, 20, 2),
130};
131
132static struct rt2880_pmx_func uart1_grp_mt7628[] = {
133 FUNC("sw_r", 3, 45, 2),
134 FUNC("pwm", 2, 45, 2),
135 FUNC("gpio", 1, 45, 2),
136 FUNC("uart1", 0, 45, 2),
137};
138
139static struct rt2880_pmx_func i2c_grp_mt7628[] = {
140 FUNC("-", 3, 4, 2),
141 FUNC("debug", 2, 4, 2),
142 FUNC("gpio", 1, 4, 2),
143 FUNC("i2c", 0, 4, 2),
144};
145
146static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) };
147static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) };
148static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
149static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
150
151static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
152 FUNC("jtag", 3, 22, 8),
153 FUNC("utif", 2, 22, 8),
154 FUNC("gpio", 1, 22, 8),
155 FUNC("sdxc", 0, 22, 8),
156};
157
158static struct rt2880_pmx_func uart0_grp_mt7628[] = {
159 FUNC("-", 3, 12, 2),
160 FUNC("-", 2, 12, 2),
161 FUNC("gpio", 1, 12, 2),
162 FUNC("uart0", 0, 12, 2),
163};
164
165static struct rt2880_pmx_func i2s_grp_mt7628[] = {
166 FUNC("antenna", 3, 0, 4),
167 FUNC("pcm", 2, 0, 4),
168 FUNC("gpio", 1, 0, 4),
169 FUNC("i2s", 0, 0, 4),
170};
171
172static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
173 FUNC("-", 3, 6, 1),
174 FUNC("refclk", 2, 6, 1),
175 FUNC("gpio", 1, 6, 1),
176 FUNC("spi cs1", 0, 6, 1),
177};
178
179static struct rt2880_pmx_func spis_grp_mt7628[] = {
180 FUNC("pwm_uart2", 3, 14, 4),
181 FUNC("utif", 2, 14, 4),
182 FUNC("gpio", 1, 14, 4),
183 FUNC("spis", 0, 14, 4),
184};
185
186static struct rt2880_pmx_func gpio_grp_mt7628[] = {
187 FUNC("pcie", 3, 11, 1),
188 FUNC("refclk", 2, 11, 1),
189 FUNC("gpio", 1, 11, 1),
190 FUNC("gpio", 0, 11, 1),
191};
192
193static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
194 FUNC("jtag", 3, 30, 1),
195 FUNC("utif", 2, 30, 1),
196 FUNC("gpio", 1, 30, 1),
197 FUNC("p4led_kn", 0, 30, 1),
198};
199
200static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
201 FUNC("jtag", 3, 31, 1),
202 FUNC("utif", 2, 31, 1),
203 FUNC("gpio", 1, 31, 1),
204 FUNC("p3led_kn", 0, 31, 1),
205};
206
207static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
208 FUNC("jtag", 3, 32, 1),
209 FUNC("utif", 2, 32, 1),
210 FUNC("gpio", 1, 32, 1),
211 FUNC("p2led_kn", 0, 32, 1),
212};
213
214static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
215 FUNC("jtag", 3, 33, 1),
216 FUNC("utif", 2, 33, 1),
217 FUNC("gpio", 1, 33, 1),
218 FUNC("p1led_kn", 0, 33, 1),
219};
220
221static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
222 FUNC("jtag", 3, 34, 1),
223 FUNC("rsvd", 2, 34, 1),
224 FUNC("gpio", 1, 34, 1),
225 FUNC("p0led_kn", 0, 34, 1),
226};
227
228static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
229 FUNC("rsvd", 3, 35, 1),
230 FUNC("rsvd", 2, 35, 1),
231 FUNC("gpio", 1, 35, 1),
232 FUNC("wled_kn", 0, 35, 1),
233};
234
235static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
236 FUNC("jtag", 3, 39, 1),
237 FUNC("utif", 2, 39, 1),
238 FUNC("gpio", 1, 39, 1),
239 FUNC("p4led_an", 0, 39, 1),
240};
241
242static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
243 FUNC("jtag", 3, 40, 1),
244 FUNC("utif", 2, 40, 1),
245 FUNC("gpio", 1, 40, 1),
246 FUNC("p3led_an", 0, 40, 1),
247};
248
249static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
250 FUNC("jtag", 3, 41, 1),
251 FUNC("utif", 2, 41, 1),
252 FUNC("gpio", 1, 41, 1),
253 FUNC("p2led_an", 0, 41, 1),
254};
255
256static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
257 FUNC("jtag", 3, 42, 1),
258 FUNC("utif", 2, 42, 1),
259 FUNC("gpio", 1, 42, 1),
260 FUNC("p1led_an", 0, 42, 1),
261};
262
263static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
264 FUNC("jtag", 3, 43, 1),
265 FUNC("rsvd", 2, 43, 1),
266 FUNC("gpio", 1, 43, 1),
267 FUNC("p0led_an", 0, 43, 1),
268};
269
270static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
271 FUNC("rsvd", 3, 44, 1),
272 FUNC("rsvd", 2, 44, 1),
273 FUNC("gpio", 1, 44, 1),
274 FUNC("wled_an", 0, 44, 1),
275};
276
277#define MT7628_GPIO_MODE_MASK 0x3
278
279#define MT7628_GPIO_MODE_P4LED_KN 58
280#define MT7628_GPIO_MODE_P3LED_KN 56
281#define MT7628_GPIO_MODE_P2LED_KN 54
282#define MT7628_GPIO_MODE_P1LED_KN 52
283#define MT7628_GPIO_MODE_P0LED_KN 50
284#define MT7628_GPIO_MODE_WLED_KN 48
285#define MT7628_GPIO_MODE_P4LED_AN 42
286#define MT7628_GPIO_MODE_P3LED_AN 40
287#define MT7628_GPIO_MODE_P2LED_AN 38
288#define MT7628_GPIO_MODE_P1LED_AN 36
289#define MT7628_GPIO_MODE_P0LED_AN 34
290#define MT7628_GPIO_MODE_WLED_AN 32
291#define MT7628_GPIO_MODE_PWM1 30
292#define MT7628_GPIO_MODE_PWM0 28
293#define MT7628_GPIO_MODE_UART2 26
294#define MT7628_GPIO_MODE_UART1 24
295#define MT7628_GPIO_MODE_I2C 20
296#define MT7628_GPIO_MODE_REFCLK 18
297#define MT7628_GPIO_MODE_PERST 16
298#define MT7628_GPIO_MODE_WDT 14
299#define MT7628_GPIO_MODE_SPI 12
300#define MT7628_GPIO_MODE_SDMODE 10
301#define MT7628_GPIO_MODE_UART0 8
302#define MT7628_GPIO_MODE_I2S 6
303#define MT7628_GPIO_MODE_CS1 4
304#define MT7628_GPIO_MODE_SPIS 2
305#define MT7628_GPIO_MODE_GPIO 0
306
307static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
308 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
309 1, MT7628_GPIO_MODE_PWM1),
310 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
311 1, MT7628_GPIO_MODE_PWM0),
312 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
313 1, MT7628_GPIO_MODE_UART2),
314 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
315 1, MT7628_GPIO_MODE_UART1),
316 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
317 1, MT7628_GPIO_MODE_I2C),
318 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
319 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
320 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
321 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
322 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
323 1, MT7628_GPIO_MODE_SDMODE),
324 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
325 1, MT7628_GPIO_MODE_UART0),
326 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
327 1, MT7628_GPIO_MODE_I2S),
328 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
329 1, MT7628_GPIO_MODE_CS1),
330 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
331 1, MT7628_GPIO_MODE_SPIS),
332 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
333 1, MT7628_GPIO_MODE_GPIO),
334 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
335 1, MT7628_GPIO_MODE_WLED_AN),
336 GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
337 1, MT7628_GPIO_MODE_P0LED_AN),
338 GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
339 1, MT7628_GPIO_MODE_P1LED_AN),
340 GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
341 1, MT7628_GPIO_MODE_P2LED_AN),
342 GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
343 1, MT7628_GPIO_MODE_P3LED_AN),
344 GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
345 1, MT7628_GPIO_MODE_P4LED_AN),
346 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
347 1, MT7628_GPIO_MODE_WLED_KN),
348 GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
349 1, MT7628_GPIO_MODE_P0LED_KN),
350 GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
351 1, MT7628_GPIO_MODE_P1LED_KN),
352 GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
353 1, MT7628_GPIO_MODE_P2LED_KN),
354 GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
355 1, MT7628_GPIO_MODE_P3LED_KN),
356 GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
357 1, MT7628_GPIO_MODE_P4LED_KN),
358 { 0 }
359};
360
361static inline int is_mt76x8(void)
362{
363 return ralink_soc == MT762X_SOC_MT7628AN ||
364 ralink_soc == MT762X_SOC_MT7688;
365}
366
367static __init u32
368mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
369{
370 u64 t;
371
372 t = ref_rate;
373 t *= mul;
374 do_div(t, div);
375
376 return t;
377}
378
379#define MHZ(x) ((x) * 1000 * 1000)
380
381static __init unsigned long
382mt7620_get_xtal_rate(void)
383{
384 u32 reg;
385
386 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
387 if (reg & SYSCFG0_XTAL_FREQ_SEL)
388 return MHZ(40);
389
390 return MHZ(20);
391}
392
393static __init unsigned long
394mt7620_get_periph_rate(unsigned long xtal_rate)
395{
396 u32 reg;
397
398 reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
399 if (reg & CLKCFG0_PERI_CLK_SEL)
400 return xtal_rate;
401
402 return MHZ(40);
403}
404
405static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
406
407static __init unsigned long
408mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
409{
410 u32 reg;
411 u32 mul;
412 u32 div;
413
414 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
415 if (reg & CPLL_CFG0_BYPASS_REF_CLK)
416 return xtal_rate;
417
418 if ((reg & CPLL_CFG0_SW_CFG) == 0)
419 return MHZ(600);
420
421 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
422 CPLL_CFG0_PLL_MULT_RATIO_MASK;
423 mul += 24;
424 if (reg & CPLL_CFG0_LC_CURFCK)
425 mul *= 2;
426
427 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
428 CPLL_CFG0_PLL_DIV_RATIO_MASK;
429
430 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
431
432 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
433}
434
435static __init unsigned long
436mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
437{
438 u32 reg;
439
440 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
441 if (reg & CPLL_CFG1_CPU_AUX1)
442 return xtal_rate;
443
444 if (reg & CPLL_CFG1_CPU_AUX0)
445 return MHZ(480);
446
447 return cpu_pll_rate;
448}
449
450static __init unsigned long
451mt7620_get_cpu_rate(unsigned long pll_rate)
452{
453 u32 reg;
454 u32 mul;
455 u32 div;
456
457 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
458
459 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
460 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
461 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
462
463 return mt7620_calc_rate(pll_rate, mul, div);
464}
465
466static const u32 mt7620_ocp_dividers[16] __initconst = {
467 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
468 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
469 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
470 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
471 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
472};
473
474static __init unsigned long
475mt7620_get_dram_rate(unsigned long pll_rate)
476{
477 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
478 return pll_rate / 4;
479
480 return pll_rate / 3;
481}
482
483static __init unsigned long
484mt7620_get_sys_rate(unsigned long cpu_rate)
485{
486 u32 reg;
487 u32 ocp_ratio;
488 u32 div;
489
490 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
491
492 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
493 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
494
495 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
496 return cpu_rate;
497
498 div = mt7620_ocp_dividers[ocp_ratio];
499 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
500 return cpu_rate;
501
502 return cpu_rate / div;
503}
504
505void __init ralink_clk_init(void)
506{
507 unsigned long xtal_rate;
508 unsigned long cpu_pll_rate;
509 unsigned long pll_rate;
510 unsigned long cpu_rate;
511 unsigned long sys_rate;
512 unsigned long dram_rate;
513 unsigned long periph_rate;
514 unsigned long pcmi2s_rate;
515
516 xtal_rate = mt7620_get_xtal_rate();
517
518#define RFMT(label) label ":%lu.%03luMHz "
519#define RINT(x) ((x) / 1000000)
520#define RFRAC(x) (((x) / 1000) % 1000)
521
522 if (is_mt76x8()) {
523 if (xtal_rate == MHZ(40))
524 cpu_rate = MHZ(580);
525 else
526 cpu_rate = MHZ(575);
527 dram_rate = sys_rate = cpu_rate / 3;
528 periph_rate = MHZ(40);
529 pcmi2s_rate = MHZ(480);
530
531 ralink_clk_add("10000d00.uartlite", periph_rate);
532 ralink_clk_add("10000e00.uartlite", periph_rate);
533 } else {
534 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
535 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
536
537 cpu_rate = mt7620_get_cpu_rate(pll_rate);
538 dram_rate = mt7620_get_dram_rate(pll_rate);
539 sys_rate = mt7620_get_sys_rate(cpu_rate);
540 periph_rate = mt7620_get_periph_rate(xtal_rate);
541 pcmi2s_rate = periph_rate;
542
543 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
544 RINT(xtal_rate), RFRAC(xtal_rate),
545 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
546 RINT(pll_rate), RFRAC(pll_rate));
547
548 ralink_clk_add("10000500.uart", periph_rate);
549 }
550
551 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
552 RINT(cpu_rate), RFRAC(cpu_rate),
553 RINT(dram_rate), RFRAC(dram_rate),
554 RINT(sys_rate), RFRAC(sys_rate),
555 RINT(periph_rate), RFRAC(periph_rate));
556#undef RFRAC
557#undef RINT
558#undef RFMT
559
560 ralink_clk_add("cpu", cpu_rate);
561 ralink_clk_add("10000100.timer", periph_rate);
562 ralink_clk_add("10000120.watchdog", periph_rate);
563 ralink_clk_add("10000900.i2c", periph_rate);
564 ralink_clk_add("10000a00.i2s", pcmi2s_rate);
565 ralink_clk_add("10000b00.spi", sys_rate);
566 ralink_clk_add("10000b40.spi", sys_rate);
567 ralink_clk_add("10000c00.uartlite", periph_rate);
568 ralink_clk_add("10000d00.uart1", periph_rate);
569 ralink_clk_add("10000e00.uart2", periph_rate);
570 ralink_clk_add("10180000.wmac", xtal_rate);
571
572 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
573 /*
574 * When the CPU goes into sleep mode, the BUS clock will be
575 * too low for USB to function properly. Adjust the busses
576 * fractional divider to fix this
577 */
578 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
579
580 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
581 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
582
583 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
584 }
585}
586
587void __init ralink_of_remap(void)
588{
589 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
590 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
591
592 if (!rt_sysc_membase || !rt_memc_membase)
593 panic("Failed to remap core resources");
594}
595
596static __init void
597mt7620_dram_init(struct ralink_soc_info *soc_info)
598{
599 switch (dram_type) {
600 case SYSCFG0_DRAM_TYPE_SDRAM:
601 pr_info("Board has SDRAM\n");
602 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
603 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
604 break;
605
606 case SYSCFG0_DRAM_TYPE_DDR1:
607 pr_info("Board has DDR1\n");
608 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
609 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
610 break;
611
612 case SYSCFG0_DRAM_TYPE_DDR2:
613 pr_info("Board has DDR2\n");
614 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
615 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
616 break;
617 default:
618 BUG();
619 }
620}
621
622static __init void
623mt7628_dram_init(struct ralink_soc_info *soc_info)
624{
625 switch (dram_type) {
626 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
627 pr_info("Board has DDR1\n");
628 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
629 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
630 break;
631
632 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
633 pr_info("Board has DDR2\n");
634 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
635 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
636 break;
637 default:
638 BUG();
639 }
640}
641
642void prom_soc_init(struct ralink_soc_info *soc_info)
643{
644 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
645 unsigned char *name = NULL;
646 u32 n0;
647 u32 n1;
648 u32 rev;
649 u32 cfg0;
650 u32 pmu0;
651 u32 pmu1;
652 u32 bga;
653
654 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
655 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
656 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
657 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
658
659 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
660 if (bga) {
661 ralink_soc = MT762X_SOC_MT7620A;
662 name = "MT7620A";
663 soc_info->compatible = "ralink,mt7620a-soc";
664 } else {
665 ralink_soc = MT762X_SOC_MT7620N;
666 name = "MT7620N";
667 soc_info->compatible = "ralink,mt7620n-soc";
668 }
669 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
670 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
671
672 if (efuse & EFUSE_MT7688) {
673 ralink_soc = MT762X_SOC_MT7688;
674 name = "MT7688";
675 } else {
676 ralink_soc = MT762X_SOC_MT7628AN;
677 name = "MT7628AN";
678 }
679 soc_info->compatible = "ralink,mt7628an-soc";
680 } else {
681 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
682 }
683
684 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
685 "MediaTek %s ver:%u eco:%u",
686 name,
687 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
688 (rev & CHIP_REV_ECO_MASK));
689
690 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
691 if (is_mt76x8()) {
692 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
693 } else {
694 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
695 SYSCFG0_DRAM_TYPE_MASK;
696 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
697 dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
698 }
699
700 soc_info->mem_base = MT7620_DRAM_BASE;
701 if (is_mt76x8())
702 mt7628_dram_init(soc_info);
703 else
704 mt7620_dram_init(soc_info);
705
706 pmu0 = __raw_readl(sysc + PMU0_CFG);
707 pmu1 = __raw_readl(sysc + PMU1_CFG);
708
709 pr_info("Analog PMU set to %s control\n",
710 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
711 pr_info("Digital PMU set to %s control\n",
712 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
713
714 if (is_mt76x8())
715 rt2880_pinmux_data = mt7628an_pinmux_data;
716 else
717 rt2880_pinmux_data = mt7620a_pinmux_data;
718}
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
new file mode 100644
index 000000000..ca0ac607b
--- /dev/null
+++ b/arch/mips/ralink/mt7621.c
@@ -0,0 +1,211 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/sys_soc.h>
12
13#include <asm/mipsregs.h>
14#include <asm/smp-ops.h>
15#include <asm/mips-cps.h>
16#include <asm/mach-ralink/ralink_regs.h>
17#include <asm/mach-ralink/mt7621.h>
18
19#include <pinmux.h>
20
21#include "common.h"
22
23#define MT7621_GPIO_MODE_UART1 1
24#define MT7621_GPIO_MODE_I2C 2
25#define MT7621_GPIO_MODE_UART3_MASK 0x3
26#define MT7621_GPIO_MODE_UART3_SHIFT 3
27#define MT7621_GPIO_MODE_UART3_GPIO 1
28#define MT7621_GPIO_MODE_UART2_MASK 0x3
29#define MT7621_GPIO_MODE_UART2_SHIFT 5
30#define MT7621_GPIO_MODE_UART2_GPIO 1
31#define MT7621_GPIO_MODE_JTAG 7
32#define MT7621_GPIO_MODE_WDT_MASK 0x3
33#define MT7621_GPIO_MODE_WDT_SHIFT 8
34#define MT7621_GPIO_MODE_WDT_GPIO 1
35#define MT7621_GPIO_MODE_PCIE_RST 0
36#define MT7621_GPIO_MODE_PCIE_REF 2
37#define MT7621_GPIO_MODE_PCIE_MASK 0x3
38#define MT7621_GPIO_MODE_PCIE_SHIFT 10
39#define MT7621_GPIO_MODE_PCIE_GPIO 1
40#define MT7621_GPIO_MODE_MDIO_MASK 0x3
41#define MT7621_GPIO_MODE_MDIO_SHIFT 12
42#define MT7621_GPIO_MODE_MDIO_GPIO 1
43#define MT7621_GPIO_MODE_RGMII1 14
44#define MT7621_GPIO_MODE_RGMII2 15
45#define MT7621_GPIO_MODE_SPI_MASK 0x3
46#define MT7621_GPIO_MODE_SPI_SHIFT 16
47#define MT7621_GPIO_MODE_SPI_GPIO 1
48#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
49#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
50#define MT7621_GPIO_MODE_SDHCI_GPIO 1
51
52static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
53static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
54static struct rt2880_pmx_func uart3_grp[] = {
55 FUNC("uart3", 0, 5, 4),
56 FUNC("i2s", 2, 5, 4),
57 FUNC("spdif3", 3, 5, 4),
58};
59static struct rt2880_pmx_func uart2_grp[] = {
60 FUNC("uart2", 0, 9, 4),
61 FUNC("pcm", 2, 9, 4),
62 FUNC("spdif2", 3, 9, 4),
63};
64static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
65static struct rt2880_pmx_func wdt_grp[] = {
66 FUNC("wdt rst", 0, 18, 1),
67 FUNC("wdt refclk", 2, 18, 1),
68};
69static struct rt2880_pmx_func pcie_rst_grp[] = {
70 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
71 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
72};
73static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
74static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
75static struct rt2880_pmx_func spi_grp[] = {
76 FUNC("spi", 0, 34, 7),
77 FUNC("nand1", 2, 34, 7),
78};
79static struct rt2880_pmx_func sdhci_grp[] = {
80 FUNC("sdhci", 0, 41, 8),
81 FUNC("nand2", 2, 41, 8),
82};
83static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
84
85static struct rt2880_pmx_group mt7621_pinmux_data[] = {
86 GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
87 GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
88 GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
89 MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
90 GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
91 MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
92 GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
93 GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
94 MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
95 GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
96 MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
97 GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
98 MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
99 GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
100 GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
101 MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
102 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
103 MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
104 GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
105 { 0 }
106};
107
108phys_addr_t mips_cpc_default_phys_base(void)
109{
110 panic("Cannot detect cpc address");
111}
112
113void __init ralink_of_remap(void)
114{
115 rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
116 rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
117
118 if (!rt_sysc_membase || !rt_memc_membase)
119 panic("Failed to remap core resources");
120}
121
122static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
123{
124 struct soc_device *soc_dev;
125 struct soc_device_attribute *soc_dev_attr;
126
127 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
128 if (!soc_dev_attr)
129 return;
130
131 soc_dev_attr->soc_id = "mt7621";
132 soc_dev_attr->family = "Ralink";
133
134 if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
135 (rev & CHIP_REV_ECO_MASK) == 1)
136 soc_dev_attr->revision = "E2";
137 else
138 soc_dev_attr->revision = "E1";
139
140 soc_dev_attr->data = soc_info;
141
142 soc_dev = soc_device_register(soc_dev_attr);
143 if (IS_ERR(soc_dev)) {
144 kfree(soc_dev_attr);
145 return;
146 }
147}
148
149void prom_soc_init(struct ralink_soc_info *soc_info)
150{
151 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
152 unsigned char *name = NULL;
153 u32 n0;
154 u32 n1;
155 u32 rev;
156
157 /* Early detection of CMP support */
158 mips_cm_probe();
159 mips_cpc_probe();
160
161 if (mips_cps_numiocu(0)) {
162 /*
163 * mips_cm_probe() wipes out bootloader
164 * config for CM regions and we have to configure them
165 * again. This SoC cannot talk to pamlbus devices
166 * witout proper iocu region set up.
167 *
168 * FIXME: it would be better to do this with values
169 * from DT, but we need this very early because
170 * without this we cannot talk to pretty much anything
171 * including serial.
172 */
173 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
174 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
175 CM_GCR_REGn_MASK_CMTGT_IOCU0);
176 __sync();
177 }
178
179 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
180 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
181
182 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
183 name = "MT7621";
184 soc_info->compatible = "mtk,mt7621-soc";
185 } else {
186 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
187 }
188 ralink_soc = MT762X_SOC_MT7621AT;
189 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
190
191 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
192 "MediaTek %s ver:%u eco:%u",
193 name,
194 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
195 (rev & CHIP_REV_ECO_MASK));
196
197 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
198 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
199 soc_info->mem_base = MT7621_DRAM_BASE;
200
201 rt2880_pinmux_data = mt7621_pinmux_data;
202
203 soc_dev_init(soc_info, rev);
204
205 if (!register_cps_smp_ops())
206 return;
207 if (!register_cmp_smp_ops())
208 return;
209 if (!register_vsmp_smp_ops())
210 return;
211}
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
new file mode 100644
index 000000000..3017263ac
--- /dev/null
+++ b/arch/mips/ralink/of.c
@@ -0,0 +1,106 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2013 John Crispin <john@phrozen.org>
7 */
8
9#include <linux/io.h>
10#include <linux/clk.h>
11#include <linux/export.h>
12#include <linux/init.h>
13#include <linux/sizes.h>
14#include <linux/of_fdt.h>
15#include <linux/kernel.h>
16#include <linux/memblock.h>
17#include <linux/of_platform.h>
18#include <linux/of_address.h>
19
20#include <asm/reboot.h>
21#include <asm/bootinfo.h>
22#include <asm/addrspace.h>
23#include <asm/prom.h>
24
25#include "common.h"
26
27__iomem void *rt_sysc_membase;
28__iomem void *rt_memc_membase;
29EXPORT_SYMBOL_GPL(rt_sysc_membase);
30
31__iomem void *plat_of_remap_node(const char *node)
32{
33 struct resource res;
34 struct device_node *np;
35
36 np = of_find_compatible_node(NULL, NULL, node);
37 if (!np)
38 panic("Failed to find %s node", node);
39
40 if (of_address_to_resource(np, 0, &res))
41 panic("Failed to get resource for %s", node);
42
43 if (!request_mem_region(res.start,
44 resource_size(&res),
45 res.name))
46 panic("Failed to request resources for %s", node);
47
48 return ioremap(res.start, resource_size(&res));
49}
50
51void __init device_tree_init(void)
52{
53 unflatten_and_copy_device_tree();
54}
55
56static int memory_dtb;
57
58static int __init early_init_dt_find_memory(unsigned long node,
59 const char *uname, int depth, void *data)
60{
61 if (depth == 1 && !strcmp(uname, "memory@0"))
62 memory_dtb = 1;
63
64 return 0;
65}
66
67void __init plat_mem_setup(void)
68{
69 void *dtb = NULL;
70
71 set_io_port_base(KSEG1);
72
73 /*
74 * Load the builtin devicetree. This causes the chosen node to be
75 * parsed resulting in our memory appearing. fw_passed_dtb is used
76 * by CONFIG_MIPS_APPENDED_RAW_DTB as well.
77 */
78 if (fw_passed_dtb)
79 dtb = (void *)fw_passed_dtb;
80 else if (&__dtb_start != &__dtb_end)
81 dtb = (void *)__dtb_start;
82
83 __dt_setup_arch(dtb);
84
85 of_scan_flat_dt(early_init_dt_find_memory, NULL);
86 if (memory_dtb)
87 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
88 else if (soc_info.mem_size)
89 memblock_add(soc_info.mem_base, soc_info.mem_size * SZ_1M);
90 else
91 detect_memory_region(soc_info.mem_base,
92 soc_info.mem_size_min * SZ_1M,
93 soc_info.mem_size_max * SZ_1M);
94}
95
96static int __init plat_of_setup(void)
97{
98 __dt_register_buses(soc_info.compatible, "palmbus");
99
100 /* make sure that the reset controller is setup early */
101 ralink_rst_init();
102
103 return 0;
104}
105
106arch_initcall(plat_of_setup);
diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
new file mode 100644
index 000000000..02e7878dc
--- /dev/null
+++ b/arch/mips/ralink/prom.c
@@ -0,0 +1,72 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
6 * Copyright (C) 2013 John Crispin <john@phrozen.org>
7 */
8
9#include <linux/string.h>
10#include <linux/of_fdt.h>
11#include <linux/of_platform.h>
12
13#include <asm/bootinfo.h>
14#include <asm/addrspace.h>
15
16#include <asm/mach-ralink/ralink_regs.h>
17
18#include "common.h"
19
20struct ralink_soc_info soc_info;
21struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
22
23enum ralink_soc_type ralink_soc;
24EXPORT_SYMBOL_GPL(ralink_soc);
25
26const char *get_system_type(void)
27{
28 return soc_info.sys_type;
29}
30
31static __init void prom_init_cmdline(void)
32{
33 int argc;
34 char **argv;
35 int i;
36
37 pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n",
38 (unsigned int)fw_arg0, (unsigned int)fw_arg1,
39 (unsigned int)fw_arg2, (unsigned int)fw_arg3);
40
41 argc = fw_arg0;
42 argv = (char **) KSEG1ADDR(fw_arg1);
43
44 if (!argv) {
45 pr_debug("argv=%p is invalid, skipping\n",
46 argv);
47 return;
48 }
49
50 for (i = 0; i < argc; i++) {
51 char *p = (char *) KSEG1ADDR(argv[i]);
52
53 if (CPHYSADDR(p) && *p) {
54 pr_debug("argv[%d]: %s\n", i, p);
55 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
56 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
57 }
58 }
59}
60
61void __init prom_init(void)
62{
63 prom_soc_init(&soc_info);
64
65 pr_info("SoC Type: %s\n", get_system_type());
66
67 prom_init_cmdline();
68}
69
70void __init prom_free_prom_memory(void)
71{
72}
diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
new file mode 100644
index 000000000..8126f1260
--- /dev/null
+++ b/arch/mips/ralink/reset.c
@@ -0,0 +1,104 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 * Copyright (C) 2013 John Crispin <john@phrozen.org>
7 */
8
9#include <linux/pm.h>
10#include <linux/io.h>
11#include <linux/of.h>
12#include <linux/delay.h>
13#include <linux/reset-controller.h>
14
15#include <asm/reboot.h>
16
17#include <asm/mach-ralink/ralink_regs.h>
18
19/* Reset Control */
20#define SYSC_REG_RESET_CTRL 0x034
21
22#define RSTCTL_RESET_PCI BIT(26)
23#define RSTCTL_RESET_SYSTEM BIT(0)
24
25static int ralink_assert_device(struct reset_controller_dev *rcdev,
26 unsigned long id)
27{
28 u32 val;
29
30 if (id < 8)
31 return -1;
32
33 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
34 val |= BIT(id);
35 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
36
37 return 0;
38}
39
40static int ralink_deassert_device(struct reset_controller_dev *rcdev,
41 unsigned long id)
42{
43 u32 val;
44
45 if (id < 8)
46 return -1;
47
48 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
49 val &= ~BIT(id);
50 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
51
52 return 0;
53}
54
55static int ralink_reset_device(struct reset_controller_dev *rcdev,
56 unsigned long id)
57{
58 ralink_assert_device(rcdev, id);
59 return ralink_deassert_device(rcdev, id);
60}
61
62static const struct reset_control_ops reset_ops = {
63 .reset = ralink_reset_device,
64 .assert = ralink_assert_device,
65 .deassert = ralink_deassert_device,
66};
67
68static struct reset_controller_dev reset_dev = {
69 .ops = &reset_ops,
70 .owner = THIS_MODULE,
71 .nr_resets = 32,
72 .of_reset_n_cells = 1,
73};
74
75void ralink_rst_init(void)
76{
77 reset_dev.of_node = of_find_compatible_node(NULL, NULL,
78 "ralink,rt2880-reset");
79 if (!reset_dev.of_node)
80 pr_err("Failed to find reset controller node");
81 else
82 reset_controller_register(&reset_dev);
83}
84
85static void ralink_restart(char *command)
86{
87 if (IS_ENABLED(CONFIG_PCI)) {
88 rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
89 mdelay(50);
90 }
91
92 local_irq_disable();
93 rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
94 unreachable();
95}
96
97static int __init mips_reboot_setup(void)
98{
99 _machine_restart = ralink_restart;
100
101 return 0;
102}
103
104arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
new file mode 100644
index 000000000..3f0968978
--- /dev/null
+++ b/arch/mips/ralink/rt288x.c
@@ -0,0 +1,111 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/mipsregs.h>
15#include <asm/mach-ralink/ralink_regs.h>
16#include <asm/mach-ralink/rt288x.h>
17#include <asm/mach-ralink/pinmux.h>
18
19#include "common.h"
20
21static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
22static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
23static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
24static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
25static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
26static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
27static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
28
29static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
30 GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
31 GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
32 GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
33 GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
34 GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
35 GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
36 GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
37 { 0 }
38};
39
40void __init ralink_clk_init(void)
41{
42 unsigned long cpu_rate, wmac_rate = 40000000;
43 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
44 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
45
46 switch (t) {
47 case SYSTEM_CONFIG_CPUCLK_250:
48 cpu_rate = 250000000;
49 break;
50 case SYSTEM_CONFIG_CPUCLK_266:
51 cpu_rate = 266666667;
52 break;
53 case SYSTEM_CONFIG_CPUCLK_280:
54 cpu_rate = 280000000;
55 break;
56 case SYSTEM_CONFIG_CPUCLK_300:
57 cpu_rate = 300000000;
58 break;
59 }
60
61 ralink_clk_add("cpu", cpu_rate);
62 ralink_clk_add("300100.timer", cpu_rate / 2);
63 ralink_clk_add("300120.watchdog", cpu_rate / 2);
64 ralink_clk_add("300500.uart", cpu_rate / 2);
65 ralink_clk_add("300900.i2c", cpu_rate / 2);
66 ralink_clk_add("300c00.uartlite", cpu_rate / 2);
67 ralink_clk_add("400000.ethernet", cpu_rate / 2);
68 ralink_clk_add("480000.wmac", wmac_rate);
69}
70
71void __init ralink_of_remap(void)
72{
73 rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
74 rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
75
76 if (!rt_sysc_membase || !rt_memc_membase)
77 panic("Failed to remap core resources");
78}
79
80void prom_soc_init(struct ralink_soc_info *soc_info)
81{
82 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
83 const char *name;
84 u32 n0;
85 u32 n1;
86 u32 id;
87
88 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
89 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
90 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
91
92 if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
93 soc_info->compatible = "ralink,r2880-soc";
94 name = "RT2880";
95 } else {
96 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
97 }
98
99 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
100 "Ralink %s id:%u rev:%u",
101 name,
102 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
103 (id & CHIP_ID_REV_MASK));
104
105 soc_info->mem_base = RT2880_SDRAM_BASE;
106 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
107 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
108
109 rt2880_pinmux_data = rt2880_pinmux_data_act;
110 ralink_soc = RT2880_SOC;
111}
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
new file mode 100644
index 000000000..496f966c0
--- /dev/null
+++ b/arch/mips/ralink/rt305x.c
@@ -0,0 +1,278 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/bug.h>
14
15#include <asm/io.h>
16#include <asm/mipsregs.h>
17#include <asm/mach-ralink/ralink_regs.h>
18#include <asm/mach-ralink/rt305x.h>
19#include <asm/mach-ralink/pinmux.h>
20
21#include "common.h"
22
23static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
24static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
25static struct rt2880_pmx_func uartf_func[] = {
26 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
27 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
28 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
29 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
30 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
31 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
32 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
33};
34static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
35static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
36static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
37static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
38static struct rt2880_pmx_func rt5350_cs1_func[] = {
39 FUNC("spi_cs1", 0, 27, 1),
40 FUNC("wdg_cs1", 1, 27, 1),
41};
42static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
43static struct rt2880_pmx_func rt3352_rgmii_func[] = {
44 FUNC("rgmii", 0, 24, 12)
45};
46static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
47static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
48static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
49static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
50static struct rt2880_pmx_func rt3352_cs1_func[] = {
51 FUNC("spi_cs1", 0, 45, 1),
52 FUNC("wdg_cs1", 1, 45, 1),
53};
54
55static struct rt2880_pmx_group rt3050_pinmux_data[] = {
56 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
57 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
58 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
59 RT305X_GPIO_MODE_UART0_SHIFT),
60 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
61 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
62 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
63 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
64 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
65 { 0 }
66};
67
68static struct rt2880_pmx_group rt3352_pinmux_data[] = {
69 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
70 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
71 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
72 RT305X_GPIO_MODE_UART0_SHIFT),
73 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
74 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
75 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
76 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
77 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
78 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
79 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
80 GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
81 { 0 }
82};
83
84static struct rt2880_pmx_group rt5350_pinmux_data[] = {
85 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
86 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
87 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
88 RT305X_GPIO_MODE_UART0_SHIFT),
89 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
90 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
91 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
92 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
93 { 0 }
94};
95
96static unsigned long rt5350_get_mem_size(void)
97{
98 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
99 unsigned long ret;
100 u32 t;
101
102 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
103 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
104 RT5350_SYSCFG0_DRAM_SIZE_MASK;
105
106 switch (t) {
107 case RT5350_SYSCFG0_DRAM_SIZE_2M:
108 ret = 2;
109 break;
110 case RT5350_SYSCFG0_DRAM_SIZE_8M:
111 ret = 8;
112 break;
113 case RT5350_SYSCFG0_DRAM_SIZE_16M:
114 ret = 16;
115 break;
116 case RT5350_SYSCFG0_DRAM_SIZE_32M:
117 ret = 32;
118 break;
119 case RT5350_SYSCFG0_DRAM_SIZE_64M:
120 ret = 64;
121 break;
122 default:
123 panic("rt5350: invalid DRAM size: %u", t);
124 break;
125 }
126
127 return ret;
128}
129
130void __init ralink_clk_init(void)
131{
132 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
133 unsigned long wmac_rate = 40000000;
134
135 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
136
137 if (soc_is_rt305x() || soc_is_rt3350()) {
138 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
139 RT305X_SYSCFG_CPUCLK_MASK;
140 switch (t) {
141 case RT305X_SYSCFG_CPUCLK_LOW:
142 cpu_rate = 320000000;
143 break;
144 case RT305X_SYSCFG_CPUCLK_HIGH:
145 cpu_rate = 384000000;
146 break;
147 }
148 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
149 } else if (soc_is_rt3352()) {
150 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
151 RT3352_SYSCFG0_CPUCLK_MASK;
152 switch (t) {
153 case RT3352_SYSCFG0_CPUCLK_LOW:
154 cpu_rate = 384000000;
155 break;
156 case RT3352_SYSCFG0_CPUCLK_HIGH:
157 cpu_rate = 400000000;
158 break;
159 }
160 sys_rate = wdt_rate = cpu_rate / 3;
161 uart_rate = 40000000;
162 } else if (soc_is_rt5350()) {
163 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
164 RT5350_SYSCFG0_CPUCLK_MASK;
165 switch (t) {
166 case RT5350_SYSCFG0_CPUCLK_360:
167 cpu_rate = 360000000;
168 sys_rate = cpu_rate / 3;
169 break;
170 case RT5350_SYSCFG0_CPUCLK_320:
171 cpu_rate = 320000000;
172 sys_rate = cpu_rate / 4;
173 break;
174 case RT5350_SYSCFG0_CPUCLK_300:
175 cpu_rate = 300000000;
176 sys_rate = cpu_rate / 3;
177 break;
178 default:
179 BUG();
180 }
181 uart_rate = 40000000;
182 wdt_rate = sys_rate;
183 } else {
184 BUG();
185 }
186
187 if (soc_is_rt3352() || soc_is_rt5350()) {
188 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
189
190 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
191 wmac_rate = 20000000;
192 }
193
194 ralink_clk_add("cpu", cpu_rate);
195 ralink_clk_add("sys", sys_rate);
196 ralink_clk_add("10000900.i2c", uart_rate);
197 ralink_clk_add("10000a00.i2s", uart_rate);
198 ralink_clk_add("10000b00.spi", sys_rate);
199 ralink_clk_add("10000b40.spi", sys_rate);
200 ralink_clk_add("10000100.timer", wdt_rate);
201 ralink_clk_add("10000120.watchdog", wdt_rate);
202 ralink_clk_add("10000500.uart", uart_rate);
203 ralink_clk_add("10000c00.uartlite", uart_rate);
204 ralink_clk_add("10100000.ethernet", sys_rate);
205 ralink_clk_add("10180000.wmac", wmac_rate);
206}
207
208void __init ralink_of_remap(void)
209{
210 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
211 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
212
213 if (!rt_sysc_membase || !rt_memc_membase)
214 panic("Failed to remap core resources");
215}
216
217void prom_soc_init(struct ralink_soc_info *soc_info)
218{
219 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
220 unsigned char *name;
221 u32 n0;
222 u32 n1;
223 u32 id;
224
225 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
226 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
227
228 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
229 unsigned long icache_sets;
230
231 icache_sets = (read_c0_config1() >> 22) & 7;
232 if (icache_sets == 1) {
233 ralink_soc = RT305X_SOC_RT3050;
234 name = "RT3050";
235 soc_info->compatible = "ralink,rt3050-soc";
236 } else {
237 ralink_soc = RT305X_SOC_RT3052;
238 name = "RT3052";
239 soc_info->compatible = "ralink,rt3052-soc";
240 }
241 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
242 ralink_soc = RT305X_SOC_RT3350;
243 name = "RT3350";
244 soc_info->compatible = "ralink,rt3350-soc";
245 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
246 ralink_soc = RT305X_SOC_RT3352;
247 name = "RT3352";
248 soc_info->compatible = "ralink,rt3352-soc";
249 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
250 ralink_soc = RT305X_SOC_RT5350;
251 name = "RT5350";
252 soc_info->compatible = "ralink,rt5350-soc";
253 } else {
254 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
255 }
256
257 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
258
259 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
260 "Ralink %s id:%u rev:%u",
261 name,
262 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
263 (id & CHIP_ID_REV_MASK));
264
265 soc_info->mem_base = RT305X_SDRAM_BASE;
266 if (soc_is_rt5350()) {
267 soc_info->mem_size = rt5350_get_mem_size();
268 rt2880_pinmux_data = rt5350_pinmux_data;
269 } else if (soc_is_rt305x() || soc_is_rt3350()) {
270 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
271 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
272 rt2880_pinmux_data = rt3050_pinmux_data;
273 } else if (soc_is_rt3352()) {
274 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
275 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
276 rt2880_pinmux_data = rt3352_pinmux_data;
277 }
278}
diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
new file mode 100644
index 000000000..8f3fe3106
--- /dev/null
+++ b/arch/mips/ralink/rt3883.c
@@ -0,0 +1,148 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/mipsregs.h>
15#include <asm/mach-ralink/ralink_regs.h>
16#include <asm/mach-ralink/rt3883.h>
17#include <asm/mach-ralink/pinmux.h>
18
19#include "common.h"
20
21static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
22static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
23static struct rt2880_pmx_func uartf_func[] = {
24 FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
25 FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
26 FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
27 FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
28 FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
29 FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
30 FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
31};
32static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
33static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
34static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
35static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
36static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
37static struct rt2880_pmx_func pci_func[] = {
38 FUNC("pci-dev", 0, 40, 32),
39 FUNC("pci-host2", 1, 40, 32),
40 FUNC("pci-host1", 2, 40, 32),
41 FUNC("pci-fnc", 3, 40, 32)
42};
43static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
44static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
45
46static struct rt2880_pmx_group rt3883_pinmux_data[] = {
47 GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
48 GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
49 GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
50 RT3883_GPIO_MODE_UART0_SHIFT),
51 GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
52 GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
53 GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
54 GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
55 GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
56 GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
57 RT3883_GPIO_MODE_PCI_SHIFT),
58 GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
59 GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
60 { 0 }
61};
62
63void __init ralink_clk_init(void)
64{
65 unsigned long cpu_rate, sys_rate;
66 u32 syscfg0;
67 u32 clksel;
68 u32 ddr2;
69
70 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
71 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
72 RT3883_SYSCFG0_CPUCLK_MASK);
73 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
74
75 switch (clksel) {
76 case RT3883_SYSCFG0_CPUCLK_250:
77 cpu_rate = 250000000;
78 sys_rate = (ddr2) ? 125000000 : 83000000;
79 break;
80 case RT3883_SYSCFG0_CPUCLK_384:
81 cpu_rate = 384000000;
82 sys_rate = (ddr2) ? 128000000 : 96000000;
83 break;
84 case RT3883_SYSCFG0_CPUCLK_480:
85 cpu_rate = 480000000;
86 sys_rate = (ddr2) ? 160000000 : 120000000;
87 break;
88 case RT3883_SYSCFG0_CPUCLK_500:
89 cpu_rate = 500000000;
90 sys_rate = (ddr2) ? 166000000 : 125000000;
91 break;
92 }
93
94 ralink_clk_add("cpu", cpu_rate);
95 ralink_clk_add("10000100.timer", sys_rate);
96 ralink_clk_add("10000120.watchdog", sys_rate);
97 ralink_clk_add("10000500.uart", 40000000);
98 ralink_clk_add("10000900.i2c", 40000000);
99 ralink_clk_add("10000a00.i2s", 40000000);
100 ralink_clk_add("10000b00.spi", sys_rate);
101 ralink_clk_add("10000b40.spi", sys_rate);
102 ralink_clk_add("10000c00.uartlite", 40000000);
103 ralink_clk_add("10100000.ethernet", sys_rate);
104 ralink_clk_add("10180000.wmac", 40000000);
105}
106
107void __init ralink_of_remap(void)
108{
109 rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
110 rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
111
112 if (!rt_sysc_membase || !rt_memc_membase)
113 panic("Failed to remap core resources");
114}
115
116void prom_soc_init(struct ralink_soc_info *soc_info)
117{
118 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
119 const char *name;
120 u32 n0;
121 u32 n1;
122 u32 id;
123
124 n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
125 n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
126 id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
127
128 if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
129 soc_info->compatible = "ralink,rt3883-soc";
130 name = "RT3883";
131 } else {
132 panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
133 }
134
135 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
136 "Ralink %s ver:%u eco:%u",
137 name,
138 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
139 (id & RT3883_REVID_ECO_ID_MASK));
140
141 soc_info->mem_base = RT3883_SDRAM_BASE;
142 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
143 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
144
145 rt2880_pinmux_data = rt3883_pinmux_data;
146
147 ralink_soc = RT3883_SOC;
148}
diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c
new file mode 100644
index 000000000..dcf2a44ac
--- /dev/null
+++ b/arch/mips/ralink/timer-gic.c
@@ -0,0 +1,22 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/init.h>
9
10#include <linux/of.h>
11#include <linux/of_clk.h>
12#include <linux/clocksource.h>
13
14#include "common.h"
15
16void __init plat_time_init(void)
17{
18 ralink_of_remap();
19
20 of_clk_init(NULL);
21 timer_probe();
22}
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
new file mode 100644
index 000000000..652424d8e
--- /dev/null
+++ b/arch/mips/ralink/timer.c
@@ -0,0 +1,151 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Ralink RT2880 timer
4 * Author: John Crispin
5 *
6 * Copyright (C) 2013 John Crispin <john@phrozen.org>
7*/
8
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/timer.h>
12#include <linux/of_gpio.h>
13#include <linux/clk.h>
14
15#include <asm/mach-ralink/ralink_regs.h>
16
17#define TIMER_REG_TMRSTAT 0x00
18#define TIMER_REG_TMR0LOAD 0x10
19#define TIMER_REG_TMR0CTL 0x18
20
21#define TMRSTAT_TMR0INT BIT(0)
22
23#define TMR0CTL_ENABLE BIT(7)
24#define TMR0CTL_MODE_PERIODIC BIT(4)
25#define TMR0CTL_PRESCALER 1
26#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
27#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
28
29struct rt_timer {
30 struct device *dev;
31 void __iomem *membase;
32 int irq;
33 unsigned long timer_freq;
34 unsigned long timer_div;
35};
36
37static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
38{
39 __raw_writel(val, rt->membase + reg);
40}
41
42static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
43{
44 return __raw_readl(rt->membase + reg);
45}
46
47static irqreturn_t rt_timer_irq(int irq, void *_rt)
48{
49 struct rt_timer *rt = (struct rt_timer *) _rt;
50
51 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
52 rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
53
54 return IRQ_HANDLED;
55}
56
57
58static int rt_timer_request(struct rt_timer *rt)
59{
60 int err = request_irq(rt->irq, rt_timer_irq, 0,
61 dev_name(rt->dev), rt);
62 if (err) {
63 dev_err(rt->dev, "failed to request irq\n");
64 } else {
65 u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
66 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
67 }
68 return err;
69}
70
71static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
72{
73 if (rt->timer_freq < divisor)
74 rt->timer_div = rt->timer_freq;
75 else
76 rt->timer_div = divisor;
77
78 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
79
80 return 0;
81}
82
83static int rt_timer_enable(struct rt_timer *rt)
84{
85 u32 t;
86
87 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
88
89 t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
90 t |= TMR0CTL_ENABLE;
91 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
92
93 return 0;
94}
95
96static int rt_timer_probe(struct platform_device *pdev)
97{
98 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
99 struct rt_timer *rt;
100 struct clk *clk;
101
102 rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
103 if (!rt) {
104 dev_err(&pdev->dev, "failed to allocate memory\n");
105 return -ENOMEM;
106 }
107
108 rt->irq = platform_get_irq(pdev, 0);
109 if (rt->irq < 0)
110 return rt->irq;
111
112 rt->membase = devm_ioremap_resource(&pdev->dev, res);
113 if (IS_ERR(rt->membase))
114 return PTR_ERR(rt->membase);
115
116 clk = devm_clk_get(&pdev->dev, NULL);
117 if (IS_ERR(clk)) {
118 dev_err(&pdev->dev, "failed get clock rate\n");
119 return PTR_ERR(clk);
120 }
121
122 rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
123 if (!rt->timer_freq)
124 return -EINVAL;
125
126 rt->dev = &pdev->dev;
127 platform_set_drvdata(pdev, rt);
128
129 rt_timer_request(rt);
130 rt_timer_config(rt, 2);
131 rt_timer_enable(rt);
132
133 dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
134
135 return 0;
136}
137
138static const struct of_device_id rt_timer_match[] = {
139 { .compatible = "ralink,rt2880-timer" },
140 {},
141};
142
143static struct platform_driver rt_timer_driver = {
144 .probe = rt_timer_probe,
145 .driver = {
146 .name = "rt-timer",
147 .of_match_table = rt_timer_match,
148 .suppress_bind_attrs = true,
149 },
150};
151builtin_platform_driver(rt_timer_driver);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-04-16 09:33:51 +0800