aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/rb532
diff options
context:
space:
mode:
authorWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
committerWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
commita07bb8fd1299070229f0e8f3dcb57ffd5ef9870a (patch)
tree84f21bd0bf7071bc5fc7dd989e77d7ceb5476682 /arch/mips/rb532
downloadohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.tar.gz
ohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.zip
Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release
Diffstat (limited to 'arch/mips/rb532')
-rw-r--r--arch/mips/rb532/Makefile8
-rw-r--r--arch/mips/rb532/Platform6
-rw-r--r--arch/mips/rb532/devices.c322
-rw-r--r--arch/mips/rb532/gpio.c207
-rw-r--r--arch/mips/rb532/irq.c234
-rw-r--r--arch/mips/rb532/prom.c130
-rw-r--r--arch/mips/rb532/serial.c54
-rw-r--r--arch/mips/rb532/setup.c81
-rw-r--r--arch/mips/rb532/time.c54
9 files changed, 1096 insertions, 0 deletions
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
new file mode 100644
index 000000000..fb4b4bf83
--- /dev/null
+++ b/arch/mips/rb532/Makefile
@@ -0,0 +1,8 @@
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Makefile for the RB532 board specific parts of the kernel
4#
5
6obj-$(CONFIG_SERIAL_8250_CONSOLE) += serial.o
7
8obj-y += irq.o time.o setup.o prom.o gpio.o devices.o
diff --git a/arch/mips/rb532/Platform b/arch/mips/rb532/Platform
new file mode 100644
index 000000000..12eaa8790
--- /dev/null
+++ b/arch/mips/rb532/Platform
@@ -0,0 +1,6 @@
1#
2# Routerboard 532
3#
4cflags-$(CONFIG_MIKROTIK_RB532) += \
5 -I$(srctree)/arch/mips/include/asm/mach-rc32434
6load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
new file mode 100644
index 000000000..0e3c8d761
--- /dev/null
+++ b/arch/mips/rb532/devices.c
@@ -0,0 +1,322 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * RouterBoard 500 Platform devices
4 *
5 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
7 */
8#include <linux/kernel.h>
9#include <linux/export.h>
10#include <linux/init.h>
11#include <linux/ctype.h>
12#include <linux/string.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/platnand.h>
15#include <linux/mtd/mtd.h>
16#include <linux/gpio.h>
17#include <linux/gpio/machine.h>
18#include <linux/gpio_keys.h>
19#include <linux/input.h>
20#include <linux/serial_8250.h>
21
22#include <asm/bootinfo.h>
23
24#include <asm/mach-rc32434/rc32434.h>
25#include <asm/mach-rc32434/dma.h>
26#include <asm/mach-rc32434/dma_v.h>
27#include <asm/mach-rc32434/eth.h>
28#include <asm/mach-rc32434/rb.h>
29#include <asm/mach-rc32434/integ.h>
30#include <asm/mach-rc32434/gpio.h>
31#include <asm/mach-rc32434/irq.h>
32
33#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
34#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
35
36extern unsigned int idt_cpu_freq;
37
38static struct mpmc_device dev3;
39
40void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
41{
42 unsigned long flags;
43
44 spin_lock_irqsave(&dev3.lock, flags);
45
46 dev3.state = (dev3.state | or_mask) & ~nand_mask;
47 writeb(dev3.state, dev3.base);
48
49 spin_unlock_irqrestore(&dev3.lock, flags);
50}
51EXPORT_SYMBOL(set_latch_u5);
52
53unsigned char get_latch_u5(void)
54{
55 return dev3.state;
56}
57EXPORT_SYMBOL(get_latch_u5);
58
59static struct resource korina_dev0_res[] = {
60 {
61 .name = "korina_regs",
62 .start = ETH0_BASE_ADDR,
63 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
64 .flags = IORESOURCE_MEM,
65 }, {
66 .name = "korina_rx",
67 .start = ETH0_DMA_RX_IRQ,
68 .end = ETH0_DMA_RX_IRQ,
69 .flags = IORESOURCE_IRQ
70 }, {
71 .name = "korina_tx",
72 .start = ETH0_DMA_TX_IRQ,
73 .end = ETH0_DMA_TX_IRQ,
74 .flags = IORESOURCE_IRQ
75 }, {
76 .name = "korina_ovr",
77 .start = ETH0_RX_OVR_IRQ,
78 .end = ETH0_RX_OVR_IRQ,
79 .flags = IORESOURCE_IRQ
80 }, {
81 .name = "korina_und",
82 .start = ETH0_TX_UND_IRQ,
83 .end = ETH0_TX_UND_IRQ,
84 .flags = IORESOURCE_IRQ
85 }, {
86 .name = "korina_dma_rx",
87 .start = ETH0_RX_DMA_ADDR,
88 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .name = "korina_dma_tx",
92 .start = ETH0_TX_DMA_ADDR,
93 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
94 .flags = IORESOURCE_MEM,
95 }
96};
97
98static struct korina_device korina_dev0_data = {
99 .name = "korina0",
100 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
101};
102
103static struct platform_device korina_dev0 = {
104 .id = -1,
105 .name = "korina",
106 .resource = korina_dev0_res,
107 .num_resources = ARRAY_SIZE(korina_dev0_res),
108};
109
110static struct resource cf_slot0_res[] = {
111 {
112 .name = "cf_membase",
113 .flags = IORESOURCE_MEM
114 }, {
115 .name = "cf_irq",
116 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
117 .end = (8 + 4 * 32 + CF_GPIO_NUM),
118 .flags = IORESOURCE_IRQ
119 }
120};
121
122static struct gpiod_lookup_table cf_slot0_gpio_table = {
123 .dev_id = "pata-rb532-cf",
124 .table = {
125 GPIO_LOOKUP("gpio0", CF_GPIO_NUM,
126 NULL, GPIO_ACTIVE_HIGH),
127 { },
128 },
129};
130
131static struct platform_device cf_slot0 = {
132 .id = -1,
133 .name = "pata-rb532-cf",
134 .resource = cf_slot0_res,
135 .num_resources = ARRAY_SIZE(cf_slot0_res),
136};
137
138/* Resources and device for NAND */
139static int rb532_dev_ready(struct nand_chip *chip)
140{
141 return gpio_get_value(GPIO_RDY);
142}
143
144static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
145{
146 unsigned char orbits, nandbits;
147
148 if (ctrl & NAND_CTRL_CHANGE) {
149 orbits = (ctrl & NAND_CLE) << 1;
150 orbits |= (ctrl & NAND_ALE) >> 1;
151
152 nandbits = (~ctrl & NAND_CLE) << 1;
153 nandbits |= (~ctrl & NAND_ALE) >> 1;
154
155 set_latch_u5(orbits, nandbits);
156 }
157 if (cmd != NAND_CMD_NONE)
158 writeb(cmd, chip->legacy.IO_ADDR_W);
159}
160
161static struct resource nand_slot0_res[] = {
162 [0] = {
163 .name = "nand_membase",
164 .flags = IORESOURCE_MEM
165 }
166};
167
168static struct platform_nand_data rb532_nand_data = {
169 .ctrl.dev_ready = rb532_dev_ready,
170 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
171};
172
173static struct platform_device nand_slot0 = {
174 .name = "gen_nand",
175 .id = -1,
176 .resource = nand_slot0_res,
177 .num_resources = ARRAY_SIZE(nand_slot0_res),
178 .dev.platform_data = &rb532_nand_data,
179};
180
181static struct mtd_partition rb532_partition_info[] = {
182 {
183 .name = "Routerboard NAND boot",
184 .offset = 0,
185 .size = 4 * 1024 * 1024,
186 }, {
187 .name = "rootfs",
188 .offset = MTDPART_OFS_NXTBLK,
189 .size = MTDPART_SIZ_FULL,
190 }
191};
192
193static struct platform_device rb532_led = {
194 .name = "rb532-led",
195 .id = -1,
196};
197
198static struct platform_device rb532_button = {
199 .name = "rb532-button",
200 .id = -1,
201};
202
203static struct resource rb532_wdt_res[] = {
204 {
205 .name = "rb532_wdt_res",
206 .start = INTEG0_BASE_ADDR,
207 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
208 .flags = IORESOURCE_MEM,
209 }
210};
211
212static struct platform_device rb532_wdt = {
213 .name = "rc32434_wdt",
214 .id = -1,
215 .resource = rb532_wdt_res,
216 .num_resources = ARRAY_SIZE(rb532_wdt_res),
217};
218
219static struct plat_serial8250_port rb532_uart_res[] = {
220 {
221 .type = PORT_16550A,
222 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
223 .irq = UART0_IRQ,
224 .regshift = 2,
225 .iotype = UPIO_MEM,
226 .flags = UPF_BOOT_AUTOCONF,
227 },
228 {
229 .flags = 0,
230 }
231};
232
233static struct platform_device rb532_uart = {
234 .name = "serial8250",
235 .id = PLAT8250_DEV_PLATFORM,
236 .dev.platform_data = &rb532_uart_res,
237};
238
239static struct platform_device *rb532_devs[] = {
240 &korina_dev0,
241 &nand_slot0,
242 &cf_slot0,
243 &rb532_led,
244 &rb532_button,
245 &rb532_uart,
246 &rb532_wdt
247};
248
249/* NAND definitions */
250#define NAND_CHIP_DELAY 25
251
252static void __init rb532_nand_setup(void)
253{
254 switch (mips_machtype) {
255 case MACH_MIKROTIK_RB532A:
256 set_latch_u5(LO_FOFF | LO_CEX,
257 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
258 break;
259 default:
260 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
261 LO_ULED | LO_ALE | LO_CLE);
262 break;
263 }
264
265 /* Setup NAND specific settings */
266 rb532_nand_data.chip.nr_chips = 1;
267 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
268 rb532_nand_data.chip.partitions = rb532_partition_info;
269 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
270}
271
272
273static int __init plat_setup_devices(void)
274{
275 /* Look for the CF card reader */
276 if (!readl(IDT434_REG_BASE + DEV1MASK))
277 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
278 else {
279 cf_slot0_res[0].start =
280 readl(IDT434_REG_BASE + DEV1BASE);
281 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
282 }
283
284 /* Read the NAND resources from the device controller */
285 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
286 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
287
288 /* Read and map device controller 3 */
289 dev3.base = ioremap(readl(IDT434_REG_BASE + DEV3BASE), 1);
290
291 if (!dev3.base) {
292 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
293 return -ENXIO;
294 }
295
296 /* Initialise the NAND device */
297 rb532_nand_setup();
298
299 /* set the uart clock to the current cpu frequency */
300 rb532_uart_res[0].uartclk = idt_cpu_freq;
301
302 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
303
304 gpiod_add_lookup_table(&cf_slot0_gpio_table);
305 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
306}
307
308#ifdef CONFIG_NET
309
310static int __init setup_kmac(char *s)
311{
312 printk(KERN_INFO "korina mac = %s\n", s);
313 if (!mac_pton(s, korina_dev0_data.mac))
314 printk(KERN_ERR "Invalid mac\n");
315 return 1;
316}
317
318__setup("kmac=", setup_kmac);
319
320#endif /* CONFIG_NET */
321
322arch_initcall(plat_setup_devices);
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
new file mode 100644
index 000000000..94f02ada4
--- /dev/null
+++ b/arch/mips/rb532/gpio.c
@@ -0,0 +1,207 @@
1/*
2 * Miscellaneous functions for IDT EB434 board
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
6 * Copyright 2007 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/init.h>
31#include <linux/types.h>
32#include <linux/export.h>
33#include <linux/spinlock.h>
34#include <linux/platform_device.h>
35#include <linux/gpio/driver.h>
36
37#include <asm/mach-rc32434/rb.h>
38#include <asm/mach-rc32434/gpio.h>
39
40struct rb532_gpio_chip {
41 struct gpio_chip chip;
42 void __iomem *regbase;
43};
44
45static struct resource rb532_gpio_reg0_res[] = {
46 {
47 .name = "gpio_reg0",
48 .start = REGBASE + GPIOBASE,
49 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
50 .flags = IORESOURCE_MEM,
51 }
52};
53
54/* rb532_set_bit - sanely set a bit
55 *
56 * bitval: new value for the bit
57 * offset: bit index in the 4 byte address range
58 * ioaddr: 4 byte aligned address being altered
59 */
60static inline void rb532_set_bit(unsigned bitval,
61 unsigned offset, void __iomem *ioaddr)
62{
63 unsigned long flags;
64 u32 val;
65
66 local_irq_save(flags);
67
68 val = readl(ioaddr);
69 val &= ~(!bitval << offset); /* unset bit if bitval == 0 */
70 val |= (!!bitval << offset); /* set bit if bitval == 1 */
71 writel(val, ioaddr);
72
73 local_irq_restore(flags);
74}
75
76/* rb532_get_bit - read a bit
77 *
78 * returns the boolean state of the bit, which may be > 1
79 */
80static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
81{
82 return readl(ioaddr) & (1 << offset);
83}
84
85/*
86 * Return GPIO level */
87static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
88{
89 struct rb532_gpio_chip *gpch;
90
91 gpch = gpiochip_get_data(chip);
92 return !!rb532_get_bit(offset, gpch->regbase + GPIOD);
93}
94
95/*
96 * Set output GPIO level
97 */
98static void rb532_gpio_set(struct gpio_chip *chip,
99 unsigned offset, int value)
100{
101 struct rb532_gpio_chip *gpch;
102
103 gpch = gpiochip_get_data(chip);
104 rb532_set_bit(value, offset, gpch->regbase + GPIOD);
105}
106
107/*
108 * Set GPIO direction to input
109 */
110static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
111{
112 struct rb532_gpio_chip *gpch;
113
114 gpch = gpiochip_get_data(chip);
115
116 /* disable alternate function in case it's set */
117 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
118
119 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
120 return 0;
121}
122
123/*
124 * Set GPIO direction to output
125 */
126static int rb532_gpio_direction_output(struct gpio_chip *chip,
127 unsigned offset, int value)
128{
129 struct rb532_gpio_chip *gpch;
130
131 gpch = gpiochip_get_data(chip);
132
133 /* disable alternate function in case it's set */
134 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
135
136 /* set the initial output value */
137 rb532_set_bit(value, offset, gpch->regbase + GPIOD);
138
139 rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
140 return 0;
141}
142
143static int rb532_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
144{
145 return 8 + 4 * 32 + gpio;
146}
147
148static struct rb532_gpio_chip rb532_gpio_chip[] = {
149 [0] = {
150 .chip = {
151 .label = "gpio0",
152 .direction_input = rb532_gpio_direction_input,
153 .direction_output = rb532_gpio_direction_output,
154 .get = rb532_gpio_get,
155 .set = rb532_gpio_set,
156 .to_irq = rb532_gpio_to_irq,
157 .base = 0,
158 .ngpio = 32,
159 },
160 },
161};
162
163/*
164 * Set GPIO interrupt level
165 */
166void rb532_gpio_set_ilevel(int bit, unsigned gpio)
167{
168 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
169}
170EXPORT_SYMBOL(rb532_gpio_set_ilevel);
171
172/*
173 * Set GPIO interrupt status
174 */
175void rb532_gpio_set_istat(int bit, unsigned gpio)
176{
177 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
178}
179EXPORT_SYMBOL(rb532_gpio_set_istat);
180
181/*
182 * Configure GPIO alternate function
183 */
184void rb532_gpio_set_func(unsigned gpio)
185{
186 rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
187}
188EXPORT_SYMBOL(rb532_gpio_set_func);
189
190int __init rb532_gpio_init(void)
191{
192 struct resource *r;
193
194 r = rb532_gpio_reg0_res;
195 rb532_gpio_chip->regbase = ioremap(r->start, resource_size(r));
196
197 if (!rb532_gpio_chip->regbase) {
198 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
199 return -ENXIO;
200 }
201
202 /* Register our GPIO chip */
203 gpiochip_add_data(&rb532_gpio_chip->chip, rb532_gpio_chip);
204
205 return 0;
206}
207arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
new file mode 100644
index 000000000..25cc250f2
--- /dev/null
+++ b/arch/mips/rb532/irq.c
@@ -0,0 +1,234 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2002 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * stevel@mvista.com or source@mvista.com
25 */
26
27#include <linux/bitops.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/kernel_stat.h>
32#include <linux/signal.h>
33#include <linux/sched.h>
34#include <linux/types.h>
35#include <linux/interrupt.h>
36#include <linux/ioport.h>
37#include <linux/timex.h>
38#include <linux/random.h>
39#include <linux/delay.h>
40
41#include <asm/bootinfo.h>
42#include <asm/time.h>
43#include <asm/mipsregs.h>
44
45#include <asm/mach-rc32434/irq.h>
46#include <asm/mach-rc32434/gpio.h>
47
48struct intr_group {
49 u32 mask; /* mask of valid bits in pending/mask registers */
50 volatile u32 *base_addr;
51};
52
53#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
54
55#if (NR_IRQS < RC32434_NR_IRQS)
56#error Too little irqs defined. Did you override <asm/irq.h> ?
57#endif
58
59static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
60 {
61 .mask = 0x0000efff,
62 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
63 {
64 .mask = 0x00001fff,
65 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
66 {
67 .mask = 0x00000007,
68 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
69 {
70 .mask = 0x0003ffff,
71 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
72 {
73 .mask = 0xffffffff,
74 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
75};
76
77#define READ_PEND(base) (*(base))
78#define READ_MASK(base) (*(base + 2))
79#define WRITE_MASK(base, val) (*(base + 2) = (val))
80
81static inline int irq_to_group(unsigned int irq_nr)
82{
83 return (irq_nr - GROUP0_IRQ_BASE) >> 5;
84}
85
86static inline int group_to_ip(unsigned int group)
87{
88 return group + 2;
89}
90
91static inline void enable_local_irq(unsigned int ip)
92{
93 int ipnum = 0x100 << ip;
94
95 set_c0_status(ipnum);
96}
97
98static inline void disable_local_irq(unsigned int ip)
99{
100 int ipnum = 0x100 << ip;
101
102 clear_c0_status(ipnum);
103}
104
105static inline void ack_local_irq(unsigned int ip)
106{
107 int ipnum = 0x100 << ip;
108
109 clear_c0_cause(ipnum);
110}
111
112static void rb532_enable_irq(struct irq_data *d)
113{
114 unsigned int group, intr_bit, irq_nr = d->irq;
115 int ip = irq_nr - GROUP0_IRQ_BASE;
116 volatile unsigned int *addr;
117
118 if (ip < 0)
119 enable_local_irq(irq_nr);
120 else {
121 group = ip >> 5;
122
123 ip &= (1 << 5) - 1;
124 intr_bit = 1 << ip;
125
126 enable_local_irq(group_to_ip(group));
127
128 addr = intr_group[group].base_addr;
129 WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
130 }
131}
132
133static void rb532_disable_irq(struct irq_data *d)
134{
135 unsigned int group, intr_bit, mask, irq_nr = d->irq;
136 int ip = irq_nr - GROUP0_IRQ_BASE;
137 volatile unsigned int *addr;
138
139 if (ip < 0) {
140 disable_local_irq(irq_nr);
141 } else {
142 group = ip >> 5;
143
144 ip &= (1 << 5) - 1;
145 intr_bit = 1 << ip;
146 addr = intr_group[group].base_addr;
147 mask = READ_MASK(addr);
148 mask |= intr_bit;
149 WRITE_MASK(addr, mask);
150
151 /* There is a maximum of 14 GPIO interrupts */
152 if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
153 rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
154
155 /*
156 * if there are no more interrupts enabled in this
157 * group, disable corresponding IP
158 */
159 if (mask == intr_group[group].mask)
160 disable_local_irq(group_to_ip(group));
161 }
162}
163
164static void rb532_mask_and_ack_irq(struct irq_data *d)
165{
166 rb532_disable_irq(d);
167 ack_local_irq(group_to_ip(irq_to_group(d->irq)));
168}
169
170static int rb532_set_type(struct irq_data *d, unsigned type)
171{
172 int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
173 int group = irq_to_group(d->irq);
174
175 if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
176 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
177
178 switch (type) {
179 case IRQ_TYPE_LEVEL_HIGH:
180 rb532_gpio_set_ilevel(1, gpio);
181 break;
182 case IRQ_TYPE_LEVEL_LOW:
183 rb532_gpio_set_ilevel(0, gpio);
184 break;
185 default:
186 return -EINVAL;
187 }
188
189 return 0;
190}
191
192static struct irq_chip rc32434_irq_type = {
193 .name = "RB532",
194 .irq_ack = rb532_disable_irq,
195 .irq_mask = rb532_disable_irq,
196 .irq_mask_ack = rb532_mask_and_ack_irq,
197 .irq_unmask = rb532_enable_irq,
198 .irq_set_type = rb532_set_type,
199};
200
201void __init arch_init_irq(void)
202{
203 int i;
204
205 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
206
207 for (i = 0; i < RC32434_NR_IRQS; i++)
208 irq_set_chip_and_handler(i, &rc32434_irq_type,
209 handle_level_irq);
210}
211
212/* Main Interrupt dispatcher */
213asmlinkage void plat_irq_dispatch(void)
214{
215 unsigned int ip, pend, group;
216 volatile unsigned int *addr;
217 unsigned int cp0_cause = read_c0_cause() & read_c0_status();
218
219 if (cp0_cause & CAUSEF_IP7) {
220 do_IRQ(7);
221 } else {
222 ip = (cp0_cause & 0x7c00);
223 if (ip) {
224 group = 21 + (fls(ip) - 32);
225
226 addr = intr_group[group].base_addr;
227
228 pend = READ_PEND(addr);
229 pend &= ~READ_MASK(addr); /* only unmasked interrupts */
230 pend = 39 + (fls(pend) - 32);
231 do_IRQ((group << 5) + pend);
232 }
233 }
234}
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
new file mode 100644
index 000000000..a9d1f2019
--- /dev/null
+++ b/arch/mips/rb532/prom.c
@@ -0,0 +1,130 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * RouterBoard 500 specific prom routines
4 *
5 * Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
6 * Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
7 * Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
8 * Felix Fietkau <nbd@openwrt.org>
9 * Florian Fainelli <florian@openwrt.org>
10 */
11
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/export.h>
15#include <linux/string.h>
16#include <linux/console.h>
17#include <linux/memblock.h>
18#include <linux/ioport.h>
19#include <linux/blkdev.h>
20
21#include <asm/bootinfo.h>
22#include <asm/mach-rc32434/ddr.h>
23#include <asm/mach-rc32434/prom.h>
24
25unsigned int idt_cpu_freq = 132000000;
26EXPORT_SYMBOL(idt_cpu_freq);
27
28static struct resource ddr_reg[] = {
29 {
30 .name = "ddr-reg",
31 .start = DDR0_PHYS_ADDR,
32 .end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram),
33 .flags = IORESOURCE_MEM,
34 }
35};
36
37void __init prom_free_prom_memory(void)
38{
39 /* No prom memory to free */
40}
41
42static inline int match_tag(char *arg, const char *tag)
43{
44 return strncmp(arg, tag, strlen(tag)) == 0;
45}
46
47static inline unsigned long tag2ul(char *arg, const char *tag)
48{
49 char *num;
50
51 num = arg + strlen(tag);
52 return simple_strtoul(num, 0, 10);
53}
54
55void __init prom_setup_cmdline(void)
56{
57 static char cmd_line[COMMAND_LINE_SIZE] __initdata;
58 char *cp, *board;
59 int prom_argc;
60 char **prom_argv;
61 int i;
62
63 prom_argc = fw_arg0;
64 prom_argv = (char **) fw_arg1;
65
66 cp = cmd_line;
67 /* Note: it is common that parameters start
68 * at argv[1] and not argv[0],
69 * however, our elf loader starts at [0] */
70 for (i = 0; i < prom_argc; i++) {
71 if (match_tag(prom_argv[i], FREQ_TAG)) {
72 idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
73 continue;
74 }
75#ifdef IGNORE_CMDLINE_MEM
76 /* parses out the "mem=xx" arg */
77 if (match_tag(prom_argv[i], MEM_TAG))
78 continue;
79#endif
80 if (i > 0)
81 *(cp++) = ' ';
82 if (match_tag(prom_argv[i], BOARD_TAG)) {
83 board = prom_argv[i] + strlen(BOARD_TAG);
84
85 if (match_tag(board, BOARD_RB532A))
86 mips_machtype = MACH_MIKROTIK_RB532A;
87 else
88 mips_machtype = MACH_MIKROTIK_RB532;
89 }
90
91 strcpy(cp, prom_argv[i]);
92 cp += strlen(prom_argv[i]);
93 }
94 *(cp++) = ' ';
95
96 i = strlen(arcs_cmdline);
97 if (i > 0) {
98 *(cp++) = ' ';
99 strcpy(cp, arcs_cmdline);
100 cp += strlen(arcs_cmdline);
101 }
102 cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
103
104 strcpy(arcs_cmdline, cmd_line);
105}
106
107void __init prom_init(void)
108{
109 struct ddr_ram __iomem *ddr;
110 phys_addr_t memsize;
111 phys_addr_t ddrbase;
112
113 ddr = ioremap(ddr_reg[0].start,
114 ddr_reg[0].end - ddr_reg[0].start);
115
116 if (!ddr) {
117 printk(KERN_ERR "Unable to remap DDR register\n");
118 return;
119 }
120
121 ddrbase = (phys_addr_t)&ddr->ddrbase;
122 memsize = (phys_addr_t)&ddr->ddrmask;
123 memsize = 0 - memsize;
124
125 prom_setup_cmdline();
126
127 /* give all RAM to boot allocator,
128 * except for the first 0x400 and the last 0x200 bytes */
129 memblock_add(ddrbase + 0x400, memsize - 0x600);
130}
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
new file mode 100644
index 000000000..70482540b
--- /dev/null
+++ b/arch/mips/rb532/serial.c
@@ -0,0 +1,54 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Serial port initialisation.
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/tty.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32#include <linux/irq.h>
33
34#include <asm/serial.h>
35#include <asm/mach-rc32434/rb.h>
36
37extern unsigned int idt_cpu_freq;
38
39static struct uart_port rb532_uart = {
40 .flags = UPF_BOOT_AUTOCONF,
41 .line = 0,
42 .irq = UART0_IRQ,
43 .iotype = UPIO_MEM,
44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
45 .regshift = 2
46};
47
48int __init setup_serial_port(void)
49{
50 rb532_uart.uartclk = idt_cpu_freq;
51
52 return early_serial_setup(&rb532_uart);
53}
54arch_initcall(setup_serial_port);
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
new file mode 100644
index 000000000..51af9d374
--- /dev/null
+++ b/arch/mips/rb532/setup.c
@@ -0,0 +1,81 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * setup.c - boot time setup code
4 */
5
6#include <linux/init.h>
7#include <linux/export.h>
8
9#include <asm/bootinfo.h>
10#include <asm/reboot.h>
11#include <asm/time.h>
12#include <linux/ioport.h>
13
14#include <asm/mach-rc32434/rb.h>
15#include <asm/mach-rc32434/pci.h>
16
17struct pci_reg __iomem *pci_reg;
18EXPORT_SYMBOL(pci_reg);
19
20static struct resource pci0_res[] = {
21 {
22 .name = "pci_reg0",
23 .start = PCI0_BASE_ADDR,
24 .end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
25 .flags = IORESOURCE_MEM,
26 }
27};
28
29static void rb_machine_restart(char *command)
30{
31 /* just jump to the reset vector */
32 writel(0x80000001, IDT434_REG_BASE + RST);
33 ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
34}
35
36static void rb_machine_halt(void)
37{
38 for (;;)
39 continue;
40}
41
42void __init plat_mem_setup(void)
43{
44 u32 val;
45
46 _machine_restart = rb_machine_restart;
47 _machine_halt = rb_machine_halt;
48 pm_power_off = rb_machine_halt;
49
50 set_io_port_base(KSEG1);
51
52 pci_reg = ioremap(pci0_res[0].start,
53 pci0_res[0].end - pci0_res[0].start);
54 if (!pci_reg) {
55 printk(KERN_ERR "Could not remap PCI registers\n");
56 return;
57 }
58
59 val = __raw_readl(&pci_reg->pcic);
60 val &= 0xFFFFFF7;
61 __raw_writel(val, (void *)&pci_reg->pcic);
62
63#ifdef CONFIG_PCI
64 /* Enable PCI interrupts in EPLD Mask register */
65 *epld_mask = 0x0;
66 *(epld_mask + 1) = 0x0;
67#endif
68 write_c0_wired(0);
69}
70
71const char *get_system_type(void)
72{
73 switch (mips_machtype) {
74 case MACH_MIKROTIK_RB532A:
75 return "Mikrotik RB532A";
76 break;
77 default:
78 return "Mikrotik RB532";
79 break;
80 }
81}
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
new file mode 100644
index 000000000..68713dd32
--- /dev/null
+++ b/arch/mips/rb532/time.c
@@ -0,0 +1,54 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
5 *
6 * Setting up the clock on the MIPS boards.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel_stat.h>
11#include <linux/ptrace.h>
12#include <linux/sched.h>
13#include <linux/spinlock.h>
14#include <linux/mc146818rtc.h>
15#include <linux/irq.h>
16#include <linux/timex.h>
17
18#include <asm/mipsregs.h>
19#include <asm/time.h>
20#include <asm/mach-rc32434/rc32434.h>
21
22extern unsigned int idt_cpu_freq;
23
24/*
25 * Figure out the r4k offset, the amount to increment the compare
26 * register for each time tick. There is no RTC available.
27 *
28 * The RC32434 counts at half the CPU *core* speed.
29 */
30static unsigned long __init cal_r4koff(void)
31{
32 mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
33
34 return mips_hpt_frequency / HZ;
35}
36
37void __init plat_time_init(void)
38{
39 unsigned int est_freq;
40 unsigned long flags, r4k_offset;
41
42 local_irq_save(flags);
43
44 printk(KERN_INFO "calculating r4koff... ");
45 r4k_offset = cal_r4koff();
46 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
47
48 est_freq = 2 * r4k_offset * HZ;
49 est_freq += 5000; /* round */
50 est_freq -= est_freq % 10000;
51 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
52 (est_freq % 1000000) * 100 / 1000000);
53 local_irq_restore(flags);
54}
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-04-16 14:25:22 +0800