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authorWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
committerWe-unite <3205135446@qq.com>2025-03-08 22:04:20 +0800
commita07bb8fd1299070229f0e8f3dcb57ffd5ef9870a (patch)
tree84f21bd0bf7071bc5fc7dd989e77d7ceb5476682 /arch/mips/sgi-ip32
downloadohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.tar.gz
ohosKernel-a07bb8fd1299070229f0e8f3dcb57ffd5ef9870a.zip
Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release
Diffstat (limited to 'arch/mips/sgi-ip32')
-rw-r--r--arch/mips/sgi-ip32/Makefile8
-rw-r--r--arch/mips/sgi-ip32/Platform10
-rw-r--r--arch/mips/sgi-ip32/crime.c103
-rw-r--r--arch/mips/sgi-ip32/ip32-berr.c38
-rw-r--r--arch/mips/sgi-ip32/ip32-dma.c37
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c499
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c47
-rw-r--r--arch/mips/sgi-ip32/ip32-platform.c138
-rw-r--r--arch/mips/sgi-ip32/ip32-reset.c152
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c100
10 files changed, 1132 insertions, 0 deletions
diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile
new file mode 100644
index 000000000..de0222466
--- /dev/null
+++ b/arch/mips/sgi-ip32/Makefile
@@ -0,0 +1,8 @@
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Makefile for the SGI specific kernel interface routines
4# under Linux.
5#
6
7obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
8 crime.o ip32-memory.o ip32-dma.o
diff --git a/arch/mips/sgi-ip32/Platform b/arch/mips/sgi-ip32/Platform
new file mode 100644
index 000000000..f58a7a02b
--- /dev/null
+++ b/arch/mips/sgi-ip32/Platform
@@ -0,0 +1,10 @@
1#
2# SGI-IP32 (O2)
3#
4# Set the load address to >= 80069000 if you want to leave space for symmon,
5# 0xffffffff80004000 for production kernels. Note that the value must be aligned to
6# a multiple of the kernel stack size or the handling of the current variable
7# will break.
8#
9cflags-$(CONFIG_SGI_IP32) += -I$(srctree)/arch/mips/include/asm/mach-ip32
10load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c
new file mode 100644
index 000000000..a8e0c776c
--- /dev/null
+++ b/arch/mips/sgi-ip32/crime.c
@@ -0,0 +1,103 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2003 Keith M Wesolowski
7 * Copyright (C) 2005 Ilya A. Volynets <ilya@total-knowledge.com>
8 */
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/interrupt.h>
13#include <linux/export.h>
14#include <asm/bootinfo.h>
15#include <asm/io.h>
16#include <asm/mipsregs.h>
17#include <asm/page.h>
18#include <asm/ip32/crime.h>
19#include <asm/ip32/mace.h>
20
21struct sgi_crime __iomem *crime;
22struct sgi_mace __iomem *mace;
23
24EXPORT_SYMBOL_GPL(mace);
25
26void __init crime_init(void)
27{
28 unsigned int id, rev;
29 const int field = 2 * sizeof(unsigned long);
30
31 set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000));
32 crime = ioremap(CRIME_BASE, sizeof(struct sgi_crime));
33 mace = ioremap(MACE_BASE, sizeof(struct sgi_mace));
34
35 id = crime->id;
36 rev = id & CRIME_ID_REV;
37 id = (id & CRIME_ID_IDBITS) >> 4;
38 printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
39 id, rev, field, (unsigned long) CRIME_BASE);
40}
41
42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
43{
44 unsigned long stat, addr;
45 int fatal = 0;
46
47 stat = crime->mem_error_stat & CRIME_MEM_ERROR_STAT_MASK;
48 addr = crime->mem_error_addr & CRIME_MEM_ERROR_ADDR_MASK;
49
50 printk("CRIME memory error at 0x%08lx ST 0x%08lx<", addr, stat);
51
52 if (stat & CRIME_MEM_ERROR_INV)
53 printk("INV,");
54 if (stat & CRIME_MEM_ERROR_ECC) {
55 unsigned long ecc_syn =
56 crime->mem_ecc_syn & CRIME_MEM_ERROR_ECC_SYN_MASK;
57 unsigned long ecc_gen =
58 crime->mem_ecc_chk & CRIME_MEM_ERROR_ECC_CHK_MASK;
59 printk("ECC,SYN=0x%08lx,GEN=0x%08lx,", ecc_syn, ecc_gen);
60 }
61 if (stat & CRIME_MEM_ERROR_MULTIPLE) {
62 fatal = 1;
63 printk("MULTIPLE,");
64 }
65 if (stat & CRIME_MEM_ERROR_HARD_ERR) {
66 fatal = 1;
67 printk("HARD,");
68 }
69 if (stat & CRIME_MEM_ERROR_SOFT_ERR)
70 printk("SOFT,");
71 if (stat & CRIME_MEM_ERROR_CPU_ACCESS)
72 printk("CPU,");
73 if (stat & CRIME_MEM_ERROR_VICE_ACCESS)
74 printk("VICE,");
75 if (stat & CRIME_MEM_ERROR_GBE_ACCESS)
76 printk("GBE,");
77 if (stat & CRIME_MEM_ERROR_RE_ACCESS)
78 printk("RE,REID=0x%02lx,", (stat & CRIME_MEM_ERROR_RE_ID)>>8);
79 if (stat & CRIME_MEM_ERROR_MACE_ACCESS)
80 printk("MACE,MACEID=0x%02lx,", stat & CRIME_MEM_ERROR_MACE_ID);
81
82 crime->mem_error_stat = 0;
83
84 if (fatal) {
85 printk("FATAL>\n");
86 panic("Fatal memory error.");
87 } else
88 printk("NONFATAL>\n");
89
90 return IRQ_HANDLED;
91}
92
93irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
94{
95 unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
97
98 addr <<= 2;
99 printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
100 crime->cpu_error_stat = 0;
101
102 return IRQ_HANDLED;
103}
diff --git a/arch/mips/sgi-ip32/ip32-berr.c b/arch/mips/sgi-ip32/ip32-berr.c
new file mode 100644
index 000000000..c860f95ab
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-berr.c
@@ -0,0 +1,38 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
7 * Copyright (C) 1999, 2000 by Silicon Graphics
8 * Copyright (C) 2002 Maciej W. Rozycki
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/sched.h>
13#include <linux/sched/debug.h>
14#include <linux/sched/signal.h>
15#include <asm/traps.h>
16#include <linux/uaccess.h>
17#include <asm/addrspace.h>
18#include <asm/ptrace.h>
19#include <asm/tlbdebug.h>
20
21static int ip32_be_handler(struct pt_regs *regs, int is_fixup)
22{
23 int data = regs->cp0_cause & 4;
24
25 if (is_fixup)
26 return MIPS_BE_FIXUP;
27
28 printk("Got %cbe at 0x%lx\n", data ? 'd' : 'i', regs->cp0_epc);
29 show_regs(regs);
30 dump_tlb_all();
31 while(1);
32 force_sig(SIGBUS);
33}
34
35void __init ip32_be_init(void)
36{
37 board_be_handler = ip32_be_handler;
38}
diff --git a/arch/mips/sgi-ip32/ip32-dma.c b/arch/mips/sgi-ip32/ip32-dma.c
new file mode 100644
index 000000000..20c6da9d7
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-dma.c
@@ -0,0 +1,37 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
4 */
5#include <linux/dma-direct.h>
6#include <asm/ip32/crime.h>
7
8/*
9 * Few notes.
10 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
11 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
12 * native-endian)
13 * 3. All other devices see memory as one big chunk at 0x40000000
14 * 4. Non-PCI devices will pass NULL as struct device*
15 *
16 * Thus we translate differently, depending on device.
17 */
18
19#define RAM_OFFSET_MASK 0x3fffffffUL
20
21dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
22{
23 dma_addr_t dma_addr = paddr & RAM_OFFSET_MASK;
24
25 if (!dev)
26 dma_addr += CRIME_HI_MEM_BASE;
27 return dma_addr;
28}
29
30phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
31{
32 phys_addr_t paddr = dma_addr & RAM_OFFSET_MASK;
33
34 if (dma_addr >= 256*1024*1024)
35 paddr += CRIME_HI_MEM_BASE;
36 return paddr;
37}
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
new file mode 100644
index 000000000..1bbd5bfb5
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -0,0 +1,499 @@
1/*
2 * Code to handle IP32 IRQs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
10 */
11#include <linux/init.h>
12#include <linux/kernel_stat.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/bitops.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/random.h>
20#include <linux/sched.h>
21#include <linux/sched/debug.h>
22
23#include <asm/irq_cpu.h>
24#include <asm/mipsregs.h>
25#include <asm/signal.h>
26#include <asm/time.h>
27#include <asm/ip32/crime.h>
28#include <asm/ip32/mace.h>
29#include <asm/ip32/ip32_ints.h>
30
31/* issue a PIO read to make sure no PIO writes are pending */
32static inline void flush_crime_bus(void)
33{
34 crime->control;
35}
36
37static inline void flush_mace_bus(void)
38{
39 mace->perif.ctrl.misc;
40}
41
42/*
43 * O2 irq map
44 *
45 * IP0 -> software (ignored)
46 * IP1 -> software (ignored)
47 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
48 * IP3 -> (irq1) X unknown
49 * IP4 -> (irq2) X unknown
50 * IP5 -> (irq3) X unknown
51 * IP6 -> (irq4) X unknown
52 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
53 *
54 * crime: (C)
55 *
56 * CRIME_INT_STAT 31:0:
57 *
58 * 0 -> 8 Video in 1
59 * 1 -> 9 Video in 2
60 * 2 -> 10 Video out
61 * 3 -> 11 Mace ethernet
62 * 4 -> S SuperIO sub-interrupt
63 * 5 -> M Miscellaneous sub-interrupt
64 * 6 -> A Audio sub-interrupt
65 * 7 -> 15 PCI bridge errors
66 * 8 -> 16 PCI SCSI aic7xxx 0
67 * 9 -> 17 PCI SCSI aic7xxx 1
68 * 10 -> 18 PCI slot 0
69 * 11 -> 19 unused (PCI slot 1)
70 * 12 -> 20 unused (PCI slot 2)
71 * 13 -> 21 unused (PCI shared 0)
72 * 14 -> 22 unused (PCI shared 1)
73 * 15 -> 23 unused (PCI shared 2)
74 * 16 -> 24 GBE0 (E)
75 * 17 -> 25 GBE1 (E)
76 * 18 -> 26 GBE2 (E)
77 * 19 -> 27 GBE3 (E)
78 * 20 -> 28 CPU errors
79 * 21 -> 29 Memory errors
80 * 22 -> 30 RE empty edge (E)
81 * 23 -> 31 RE full edge (E)
82 * 24 -> 32 RE idle edge (E)
83 * 25 -> 33 RE empty level
84 * 26 -> 34 RE full level
85 * 27 -> 35 RE idle level
86 * 28 -> 36 unused (software 0) (E)
87 * 29 -> 37 unused (software 1) (E)
88 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
89 * 31 -> 39 VICE
90 *
91 * S, M, A: Use the MACE ISA interrupt register
92 * MACE_ISA_INT_STAT 31:0
93 *
94 * 0-7 -> 40-47 Audio
95 * 8 -> 48 RTC
96 * 9 -> 49 Keyboard
97 * 10 -> X Keyboard polled
98 * 11 -> 51 Mouse
99 * 12 -> X Mouse polled
100 * 13-15 -> 53-55 Count/compare timers
101 * 16-19 -> 56-59 Parallel (16 E)
102 * 20-25 -> 60-62 Serial 1 (22 E)
103 * 26-31 -> 66-71 Serial 2 (28 E)
104 *
105 * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
106 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
107 * is quite different anyway.
108 */
109
110/* Some initial interrupts to set up */
111extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
112extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
113
114/*
115 * This is for pure CRIME interrupts - ie not MACE. The advantage?
116 * We get to split the register in half and do faster lookups.
117 */
118
119static uint64_t crime_mask;
120
121static inline void crime_enable_irq(struct irq_data *d)
122{
123 unsigned int bit = d->irq - CRIME_IRQ_BASE;
124
125 crime_mask |= 1 << bit;
126 crime->imask = crime_mask;
127}
128
129static inline void crime_disable_irq(struct irq_data *d)
130{
131 unsigned int bit = d->irq - CRIME_IRQ_BASE;
132
133 crime_mask &= ~(1 << bit);
134 crime->imask = crime_mask;
135 flush_crime_bus();
136}
137
138static struct irq_chip crime_level_interrupt = {
139 .name = "IP32 CRIME",
140 .irq_mask = crime_disable_irq,
141 .irq_unmask = crime_enable_irq,
142};
143
144static void crime_edge_mask_and_ack_irq(struct irq_data *d)
145{
146 unsigned int bit = d->irq - CRIME_IRQ_BASE;
147 uint64_t crime_int;
148
149 /* Edge triggered interrupts must be cleared. */
150 crime_int = crime->hard_int;
151 crime_int &= ~(1 << bit);
152 crime->hard_int = crime_int;
153
154 crime_disable_irq(d);
155}
156
157static struct irq_chip crime_edge_interrupt = {
158 .name = "IP32 CRIME",
159 .irq_ack = crime_edge_mask_and_ack_irq,
160 .irq_mask = crime_disable_irq,
161 .irq_mask_ack = crime_edge_mask_and_ack_irq,
162 .irq_unmask = crime_enable_irq,
163};
164
165/*
166 * This is for MACE PCI interrupts. We can decrease bus traffic by masking
167 * as close to the source as possible. This also means we can take the
168 * next chunk of the CRIME register in one piece.
169 */
170
171static unsigned long macepci_mask;
172
173static void enable_macepci_irq(struct irq_data *d)
174{
175 macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
176 mace->pci.control = macepci_mask;
177 crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
178 crime->imask = crime_mask;
179}
180
181static void disable_macepci_irq(struct irq_data *d)
182{
183 crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
184 crime->imask = crime_mask;
185 flush_crime_bus();
186 macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
187 mace->pci.control = macepci_mask;
188 flush_mace_bus();
189}
190
191static struct irq_chip ip32_macepci_interrupt = {
192 .name = "IP32 MACE PCI",
193 .irq_mask = disable_macepci_irq,
194 .irq_unmask = enable_macepci_irq,
195};
196
197/* This is used for MACE ISA interrupts. That means bits 4-6 in the
198 * CRIME register.
199 */
200
201#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
202 MACEISA_AUDIO_SC_INT | \
203 MACEISA_AUDIO1_DMAT_INT | \
204 MACEISA_AUDIO1_OF_INT | \
205 MACEISA_AUDIO2_DMAT_INT | \
206 MACEISA_AUDIO2_MERR_INT | \
207 MACEISA_AUDIO3_DMAT_INT | \
208 MACEISA_AUDIO3_MERR_INT)
209#define MACEISA_MISC_INT (MACEISA_RTC_INT | \
210 MACEISA_KEYB_INT | \
211 MACEISA_KEYB_POLL_INT | \
212 MACEISA_MOUSE_INT | \
213 MACEISA_MOUSE_POLL_INT | \
214 MACEISA_TIMER0_INT | \
215 MACEISA_TIMER1_INT | \
216 MACEISA_TIMER2_INT)
217#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
218 MACEISA_PAR_CTXA_INT | \
219 MACEISA_PAR_CTXB_INT | \
220 MACEISA_PAR_MERR_INT | \
221 MACEISA_SERIAL1_INT | \
222 MACEISA_SERIAL1_TDMAT_INT | \
223 MACEISA_SERIAL1_TDMAPR_INT | \
224 MACEISA_SERIAL1_TDMAME_INT | \
225 MACEISA_SERIAL1_RDMAT_INT | \
226 MACEISA_SERIAL1_RDMAOR_INT | \
227 MACEISA_SERIAL2_INT | \
228 MACEISA_SERIAL2_TDMAT_INT | \
229 MACEISA_SERIAL2_TDMAPR_INT | \
230 MACEISA_SERIAL2_TDMAME_INT | \
231 MACEISA_SERIAL2_RDMAT_INT | \
232 MACEISA_SERIAL2_RDMAOR_INT)
233
234static unsigned long maceisa_mask;
235
236static void enable_maceisa_irq(struct irq_data *d)
237{
238 unsigned int crime_int = 0;
239
240 pr_debug("maceisa enable: %u\n", d->irq);
241
242 switch (d->irq) {
243 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
244 crime_int = MACE_AUDIO_INT;
245 break;
246 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
247 crime_int = MACE_MISC_INT;
248 break;
249 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
250 crime_int = MACE_SUPERIO_INT;
251 break;
252 }
253 pr_debug("crime_int %08x enabled\n", crime_int);
254 crime_mask |= crime_int;
255 crime->imask = crime_mask;
256 maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
257 mace->perif.ctrl.imask = maceisa_mask;
258}
259
260static void disable_maceisa_irq(struct irq_data *d)
261{
262 unsigned int crime_int = 0;
263
264 maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
265 if (!(maceisa_mask & MACEISA_AUDIO_INT))
266 crime_int |= MACE_AUDIO_INT;
267 if (!(maceisa_mask & MACEISA_MISC_INT))
268 crime_int |= MACE_MISC_INT;
269 if (!(maceisa_mask & MACEISA_SUPERIO_INT))
270 crime_int |= MACE_SUPERIO_INT;
271 crime_mask &= ~crime_int;
272 crime->imask = crime_mask;
273 flush_crime_bus();
274 mace->perif.ctrl.imask = maceisa_mask;
275 flush_mace_bus();
276}
277
278static void mask_and_ack_maceisa_irq(struct irq_data *d)
279{
280 unsigned long mace_int;
281
282 /* edge triggered */
283 mace_int = mace->perif.ctrl.istat;
284 mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
285 mace->perif.ctrl.istat = mace_int;
286
287 disable_maceisa_irq(d);
288}
289
290static struct irq_chip ip32_maceisa_level_interrupt = {
291 .name = "IP32 MACE ISA",
292 .irq_mask = disable_maceisa_irq,
293 .irq_unmask = enable_maceisa_irq,
294};
295
296static struct irq_chip ip32_maceisa_edge_interrupt = {
297 .name = "IP32 MACE ISA",
298 .irq_ack = mask_and_ack_maceisa_irq,
299 .irq_mask = disable_maceisa_irq,
300 .irq_mask_ack = mask_and_ack_maceisa_irq,
301 .irq_unmask = enable_maceisa_irq,
302};
303
304/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
305 * bits 0-3 and 7 in the CRIME register.
306 */
307
308static void enable_mace_irq(struct irq_data *d)
309{
310 unsigned int bit = d->irq - CRIME_IRQ_BASE;
311
312 crime_mask |= (1 << bit);
313 crime->imask = crime_mask;
314}
315
316static void disable_mace_irq(struct irq_data *d)
317{
318 unsigned int bit = d->irq - CRIME_IRQ_BASE;
319
320 crime_mask &= ~(1 << bit);
321 crime->imask = crime_mask;
322 flush_crime_bus();
323}
324
325static struct irq_chip ip32_mace_interrupt = {
326 .name = "IP32 MACE",
327 .irq_mask = disable_mace_irq,
328 .irq_unmask = enable_mace_irq,
329};
330
331static void ip32_unknown_interrupt(void)
332{
333 printk("Unknown interrupt occurred!\n");
334 printk("cp0_status: %08x\n", read_c0_status());
335 printk("cp0_cause: %08x\n", read_c0_cause());
336 printk("CRIME intr mask: %016lx\n", crime->imask);
337 printk("CRIME intr status: %016lx\n", crime->istat);
338 printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
339 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
340 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
341 printk("MACE PCI control register: %08x\n", mace->pci.control);
342
343 printk("Register dump:\n");
344 show_regs(get_irq_regs());
345
346 printk("Please mail this report to linux-mips@linux-mips.org\n");
347 printk("Spinning...");
348 while(1) ;
349}
350
351/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
352/* change this to loop over all edge-triggered irqs, exception masked out ones */
353static void ip32_irq0(void)
354{
355 uint64_t crime_int;
356 int irq = 0;
357
358 /*
359 * Sanity check interrupt numbering enum.
360 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
361 * chained.
362 */
363 BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
364 BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
365
366 crime_int = crime->istat & crime_mask;
367
368 /* crime sometime delivers spurious interrupts, ignore them */
369 if (unlikely(crime_int == 0))
370 return;
371
372 irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
373
374 if (crime_int & CRIME_MACEISA_INT_MASK) {
375 unsigned long mace_int = mace->perif.ctrl.istat;
376 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
377 }
378
379 pr_debug("*irq %u*\n", irq);
380 do_IRQ(irq);
381}
382
383static void ip32_irq1(void)
384{
385 ip32_unknown_interrupt();
386}
387
388static void ip32_irq2(void)
389{
390 ip32_unknown_interrupt();
391}
392
393static void ip32_irq3(void)
394{
395 ip32_unknown_interrupt();
396}
397
398static void ip32_irq4(void)
399{
400 ip32_unknown_interrupt();
401}
402
403static void ip32_irq5(void)
404{
405 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
406}
407
408asmlinkage void plat_irq_dispatch(void)
409{
410 unsigned int pending = read_c0_status() & read_c0_cause();
411
412 if (likely(pending & IE_IRQ0))
413 ip32_irq0();
414 else if (unlikely(pending & IE_IRQ1))
415 ip32_irq1();
416 else if (unlikely(pending & IE_IRQ2))
417 ip32_irq2();
418 else if (unlikely(pending & IE_IRQ3))
419 ip32_irq3();
420 else if (unlikely(pending & IE_IRQ4))
421 ip32_irq4();
422 else if (likely(pending & IE_IRQ5))
423 ip32_irq5();
424}
425
426void __init arch_init_irq(void)
427{
428 unsigned int irq;
429
430 /* Install our interrupt handler, then clear and disable all
431 * CRIME and MACE interrupts. */
432 crime->imask = 0;
433 crime->hard_int = 0;
434 crime->soft_int = 0;
435 mace->perif.ctrl.istat = 0;
436 mace->perif.ctrl.imask = 0;
437
438 mips_cpu_irq_init();
439 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
440 switch (irq) {
441 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
442 irq_set_chip_and_handler_name(irq,
443 &ip32_mace_interrupt,
444 handle_level_irq,
445 "level");
446 break;
447
448 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
449 irq_set_chip_and_handler_name(irq,
450 &ip32_macepci_interrupt,
451 handle_level_irq,
452 "level");
453 break;
454
455 case CRIME_CPUERR_IRQ:
456 case CRIME_MEMERR_IRQ:
457 irq_set_chip_and_handler_name(irq,
458 &crime_level_interrupt,
459 handle_level_irq,
460 "level");
461 break;
462
463 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
464 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
465 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
466 case CRIME_VICE_IRQ:
467 irq_set_chip_and_handler_name(irq,
468 &crime_edge_interrupt,
469 handle_edge_irq,
470 "edge");
471 break;
472
473 case MACEISA_PARALLEL_IRQ:
474 case MACEISA_SERIAL1_TDMAPR_IRQ:
475 case MACEISA_SERIAL2_TDMAPR_IRQ:
476 irq_set_chip_and_handler_name(irq,
477 &ip32_maceisa_edge_interrupt,
478 handle_edge_irq,
479 "edge");
480 break;
481
482 default:
483 irq_set_chip_and_handler_name(irq,
484 &ip32_maceisa_level_interrupt,
485 handle_level_irq,
486 "level");
487 break;
488 }
489 }
490 if (request_irq(CRIME_MEMERR_IRQ, crime_memerr_intr, 0,
491 "CRIME memory error", NULL))
492 pr_err("Failed to register CRIME memory error interrupt\n");
493 if (request_irq(CRIME_CPUERR_IRQ, crime_cpuerr_intr, 0,
494 "CRIME CPU error", NULL))
495 pr_err("Failed to register CRIME CPU error interrupt\n");
496
497#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
498 change_c0_status(ST0_IM, ALLINTS);
499}
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
new file mode 100644
index 000000000..0f53fed39
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Keith M Wesolowski
7 * Copyright (C) 2005 Ilya A. Volynets (Total Knowledge)
8 */
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/memblock.h>
13#include <linux/mm.h>
14
15#include <asm/ip32/crime.h>
16#include <asm/bootinfo.h>
17#include <asm/page.h>
18
19extern void crime_init(void);
20
21void __init prom_meminit(void)
22{
23 u64 base, size;
24 int bank;
25
26 crime_init();
27
28 for (bank=0; bank < CRIME_MAXBANKS; bank++) {
29 u64 bankctl = crime->bank_ctrl[bank];
30 base = (bankctl & CRIME_MEM_BANK_CONTROL_ADDR) << 25;
31 if (bank != 0 && base == 0)
32 continue;
33 size = (bankctl & CRIME_MEM_BANK_CONTROL_SDRAM_SIZE) ? 128 : 32;
34 size <<= 20;
35 if (base + size > (256 << 20))
36 base += CRIME_HI_MEM_BASE;
37
38 printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n",
39 bank, base, size >> 20);
40 memblock_add(base, size);
41 }
42}
43
44
45void __init prom_free_prom_memory(void)
46{
47}
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
new file mode 100644
index 000000000..c3909bd8d
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -0,0 +1,138 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/serial_8250.h>
11#include <linux/rtc/ds1685.h>
12
13#include <asm/ip32/mace.h>
14#include <asm/ip32/ip32_ints.h>
15
16extern void ip32_prepare_poweroff(void);
17
18#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
19#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
20
21#define MACE_PORT(offset,_irq) \
22{ \
23 .mapbase = MACE_BASE + offset, \
24 .irq = _irq, \
25 .uartclk = 1843200, \
26 .iotype = UPIO_MEM, \
27 .flags = UPF_SKIP_TEST|UPF_IOREMAP, \
28 .regshift = 8, \
29}
30
31static struct plat_serial8250_port uart8250_data[] = {
32 MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
33 MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
34 { },
35};
36
37static struct platform_device uart8250_device = {
38 .name = "serial8250",
39 .id = PLAT8250_DEV_PLATFORM,
40 .dev = {
41 .platform_data = uart8250_data,
42 },
43};
44
45static int __init uart8250_init(void)
46{
47 return platform_device_register(&uart8250_device);
48}
49
50device_initcall(uart8250_init);
51
52static __init int meth_devinit(void)
53{
54 struct platform_device *pd;
55 int ret;
56
57 pd = platform_device_alloc("meth", -1);
58 if (!pd)
59 return -ENOMEM;
60
61 ret = platform_device_add(pd);
62 if (ret)
63 platform_device_put(pd);
64
65 return ret;
66}
67
68device_initcall(meth_devinit);
69
70static __init int sgio2audio_devinit(void)
71{
72 struct platform_device *pd;
73 int ret;
74
75 pd = platform_device_alloc("sgio2audio", -1);
76 if (!pd)
77 return -ENOMEM;
78
79 ret = platform_device_add(pd);
80 if (ret)
81 platform_device_put(pd);
82
83 return ret;
84}
85
86device_initcall(sgio2audio_devinit);
87
88static __init int sgio2btns_devinit(void)
89{
90 return IS_ERR(platform_device_register_simple("sgibtns", -1, NULL, 0));
91}
92
93device_initcall(sgio2btns_devinit);
94
95#define MACE_RTC_RES_START (MACE_BASE + offsetof(struct sgi_mace, isa.rtc))
96#define MACE_RTC_RES_END (MACE_RTC_RES_START + 32767)
97
98static struct resource ip32_rtc_resources[] = {
99 {
100 .start = MACEISA_RTC_IRQ,
101 .end = MACEISA_RTC_IRQ,
102 .flags = IORESOURCE_IRQ
103 }, {
104 .start = MACE_RTC_RES_START,
105 .end = MACE_RTC_RES_END,
106 .flags = IORESOURCE_MEM,
107 }
108};
109
110/* RTC registers on IP32 are each padded by 256 bytes (0x100). */
111static struct ds1685_rtc_platform_data
112ip32_rtc_platform_data[] = {
113 {
114 .regstep = 0x100,
115 .bcd_mode = true,
116 .no_irq = false,
117 .uie_unsupported = false,
118 .access_type = ds1685_reg_direct,
119 .plat_prepare_poweroff = ip32_prepare_poweroff,
120 },
121};
122
123struct platform_device ip32_rtc_device = {
124 .name = "rtc-ds1685",
125 .id = -1,
126 .dev = {
127 .platform_data = ip32_rtc_platform_data,
128 },
129 .num_resources = ARRAY_SIZE(ip32_rtc_resources),
130 .resource = ip32_rtc_resources,
131};
132
133static __init int sgio2_rtc_devinit(void)
134{
135 return platform_device_register(&ip32_rtc_device);
136}
137
138device_initcall(sgio2_rtc_devinit);
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c
new file mode 100644
index 000000000..20d863734
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-reset.c
@@ -0,0 +1,152 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001 Keith M Wesolowski
7 * Copyright (C) 2001 Paul Mundt
8 * Copyright (C) 2003 Guido Guenther <agx@sigxcpu.org>
9 */
10
11#include <linux/compiler.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/sched/signal.h>
17#include <linux/notifier.h>
18#include <linux/delay.h>
19#include <linux/rtc/ds1685.h>
20#include <linux/interrupt.h>
21#include <linux/pm.h>
22
23#include <asm/addrspace.h>
24#include <asm/irq.h>
25#include <asm/reboot.h>
26#include <asm/wbflush.h>
27#include <asm/ip32/mace.h>
28#include <asm/ip32/crime.h>
29#include <asm/ip32/ip32_ints.h>
30
31#define POWERDOWN_TIMEOUT 120
32/*
33 * Blink frequency during reboot grace period and when panicked.
34 */
35#define POWERDOWN_FREQ (HZ / 4)
36#define PANIC_FREQ (HZ / 8)
37
38extern struct platform_device ip32_rtc_device;
39
40static struct timer_list power_timer, blink_timer;
41static unsigned long blink_timer_timeout;
42static int has_panicked, shutting_down;
43
44static __noreturn void ip32_poweroff(void *data)
45{
46 void (*poweroff_func)(struct platform_device *) =
47 symbol_get(ds1685_rtc_poweroff);
48
49#ifdef CONFIG_MODULES
50 /* If the first __symbol_get failed, our module wasn't loaded. */
51 if (!poweroff_func) {
52 request_module("rtc-ds1685");
53 poweroff_func = symbol_get(ds1685_rtc_poweroff);
54 }
55#endif
56
57 if (!poweroff_func)
58 pr_emerg("RTC not available for power-off. Spinning forever ...\n");
59 else {
60 (*poweroff_func)((struct platform_device *)data);
61 symbol_put(ds1685_rtc_poweroff);
62 }
63
64 unreachable();
65}
66
67static void ip32_machine_restart(char *cmd) __noreturn;
68static void ip32_machine_restart(char *cmd)
69{
70 msleep(20);
71 crime->control = CRIME_CONTROL_HARD_RESET;
72 unreachable();
73}
74
75static void blink_timeout(struct timer_list *unused)
76{
77 unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED;
78 mace->perif.ctrl.misc = led;
79 mod_timer(&blink_timer, jiffies + blink_timer_timeout);
80}
81
82static void ip32_machine_halt(void)
83{
84 ip32_poweroff(&ip32_rtc_device);
85}
86
87static void power_timeout(struct timer_list *unused)
88{
89 ip32_poweroff(&ip32_rtc_device);
90}
91
92void ip32_prepare_poweroff(void)
93{
94 if (has_panicked)
95 return;
96
97 if (shutting_down || kill_cad_pid(SIGINT, 1)) {
98 /* No init process or button pressed twice. */
99 ip32_poweroff(&ip32_rtc_device);
100 }
101
102 shutting_down = 1;
103 blink_timer_timeout = POWERDOWN_FREQ;
104 blink_timeout(&blink_timer);
105
106 timer_setup(&power_timer, power_timeout, 0);
107 power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ;
108 add_timer(&power_timer);
109}
110
111static int panic_event(struct notifier_block *this, unsigned long event,
112 void *ptr)
113{
114 unsigned long led;
115
116 if (has_panicked)
117 return NOTIFY_DONE;
118 has_panicked = 1;
119
120 /* turn off the green LED */
121 led = mace->perif.ctrl.misc | MACEISA_LED_GREEN;
122 mace->perif.ctrl.misc = led;
123
124 blink_timer_timeout = PANIC_FREQ;
125 blink_timeout(&blink_timer);
126
127 return NOTIFY_DONE;
128}
129
130static struct notifier_block panic_block = {
131 .notifier_call = panic_event,
132};
133
134static __init int ip32_reboot_setup(void)
135{
136 /* turn on the green led only */
137 unsigned long led = mace->perif.ctrl.misc;
138 led |= MACEISA_LED_RED;
139 led &= ~MACEISA_LED_GREEN;
140 mace->perif.ctrl.misc = led;
141
142 _machine_restart = ip32_machine_restart;
143 _machine_halt = ip32_machine_halt;
144 pm_power_off = ip32_machine_halt;
145
146 timer_setup(&blink_timer, blink_timeout, 0);
147 atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
148
149 return 0;
150}
151
152subsys_initcall(ip32_reboot_setup);
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
new file mode 100644
index 000000000..8019dae17
--- /dev/null
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -0,0 +1,100 @@
1/*
2 * IP32 basic setup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2002, 2003, 2005 Ilya A. Volynets
10 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
11 */
12#include <linux/console.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/param.h>
16#include <linux/sched.h>
17
18#include <asm/bootinfo.h>
19#include <asm/mipsregs.h>
20#include <asm/mmu_context.h>
21#include <asm/sgialib.h>
22#include <asm/time.h>
23#include <asm/traps.h>
24#include <asm/io.h>
25#include <asm/ip32/crime.h>
26#include <asm/ip32/mace.h>
27#include <asm/ip32/ip32_ints.h>
28
29extern void ip32_be_init(void);
30extern void crime_init(void);
31
32#ifdef CONFIG_SGI_O2MACE_ETH
33/*
34 * This is taken care of in here 'cause they say using Arc later on is
35 * problematic
36 */
37extern char o2meth_eaddr[8];
38static inline unsigned char str2hexnum(unsigned char c)
39{
40 if (c >= '0' && c <= '9')
41 return c - '0';
42 if (c >= 'a' && c <= 'f')
43 return c - 'a' + 10;
44 return 0; /* foo */
45}
46
47static inline void str2eaddr(unsigned char *ea, unsigned char *str)
48{
49 int i;
50
51 for (i = 0; i < 6; i++) {
52 unsigned char num;
53
54 if(*str == ':')
55 str++;
56 num = str2hexnum(*str++) << 4;
57 num |= (str2hexnum(*str++));
58 ea[i] = num;
59 }
60}
61#endif
62
63/* An arbitrary time; this can be decreased if reliability looks good */
64#define WAIT_MS 10
65
66void __init plat_time_init(void)
67{
68 printk(KERN_INFO "Calibrating system timer... ");
69 write_c0_count(0);
70 crime->timer = 0;
71 while (crime->timer < CRIME_MASTER_FREQ * WAIT_MS / 1000) ;
72 mips_hpt_frequency = read_c0_count() * 1000 / WAIT_MS;
73 printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000);
74}
75
76void __init plat_mem_setup(void)
77{
78 board_be_init = ip32_be_init;
79
80#ifdef CONFIG_SGI_O2MACE_ETH
81 {
82 char *mac = ArcGetEnvironmentVariable("eaddr");
83 str2eaddr(o2meth_eaddr, mac);
84 }
85#endif
86
87#if defined(CONFIG_SERIAL_CORE_CONSOLE)
88 {
89 char* con = ArcGetEnvironmentVariable("console");
90 if (con && *con == 'd') {
91 static char options[8] __initdata;
92 char *baud = ArcGetEnvironmentVariable("dbaud");
93 if (baud)
94 strcpy(options, baud);
95 add_preferred_console("ttyS", *(con + 1) == '2' ? 1 : 0,
96 baud ? options : NULL);
97 }
98 }
99#endif
100}
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-04-16 09:31:26 +0800