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Diffstat (limited to 'arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts')
-rw-r--r-- | arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts | 406 |
1 files changed, 406 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 000000000..dda0559ce --- /dev/null +++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts | |||
@@ -0,0 +1,406 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. | ||
4 | * | ||
5 | * This device tree is pruned and patched by early boot code before | ||
6 | * use. Because of this, it contains a super-set of the available | ||
7 | * devices and properties. | ||
8 | */ | ||
9 | |||
10 | /include/ "octeon_3xxx.dtsi" | ||
11 | |||
12 | / { | ||
13 | soc@0 { | ||
14 | smi0: mdio@1180000001800 { | ||
15 | phy0: ethernet-phy@0 { | ||
16 | compatible = "marvell,88e1118"; | ||
17 | marvell,reg-init = | ||
18 | /* Fix rx and tx clock transition timing */ | ||
19 | <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ | ||
20 | /* Adjust LED drive. */ | ||
21 | <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ | ||
22 | /* irq, blink-activity, blink-link */ | ||
23 | <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ | ||
24 | reg = <0>; | ||
25 | }; | ||
26 | |||
27 | phy1: ethernet-phy@1 { | ||
28 | compatible = "marvell,88e1118"; | ||
29 | marvell,reg-init = | ||
30 | /* Fix rx and tx clock transition timing */ | ||
31 | <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ | ||
32 | /* Adjust LED drive. */ | ||
33 | <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ | ||
34 | /* irq, blink-activity, blink-link */ | ||
35 | <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ | ||
36 | reg = <1>; | ||
37 | }; | ||
38 | |||
39 | phy2: ethernet-phy@2 { | ||
40 | reg = <2>; | ||
41 | compatible = "marvell,88e1149r"; | ||
42 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
43 | <3 0x11 0 0x00aa>, | ||
44 | <3 0x12 0 0x4105>, | ||
45 | <3 0x13 0 0x0a60>; | ||
46 | }; | ||
47 | phy3: ethernet-phy@3 { | ||
48 | reg = <3>; | ||
49 | compatible = "marvell,88e1149r"; | ||
50 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
51 | <3 0x11 0 0x00aa>, | ||
52 | <3 0x12 0 0x4105>, | ||
53 | <3 0x13 0 0x0a60>; | ||
54 | }; | ||
55 | phy4: ethernet-phy@4 { | ||
56 | reg = <4>; | ||
57 | compatible = "marvell,88e1149r"; | ||
58 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
59 | <3 0x11 0 0x00aa>, | ||
60 | <3 0x12 0 0x4105>, | ||
61 | <3 0x13 0 0x0a60>; | ||
62 | }; | ||
63 | phy5: ethernet-phy@5 { | ||
64 | reg = <5>; | ||
65 | compatible = "marvell,88e1149r"; | ||
66 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
67 | <3 0x11 0 0x00aa>, | ||
68 | <3 0x12 0 0x4105>, | ||
69 | <3 0x13 0 0x0a60>; | ||
70 | }; | ||
71 | |||
72 | phy6: ethernet-phy@6 { | ||
73 | reg = <6>; | ||
74 | compatible = "marvell,88e1149r"; | ||
75 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
76 | <3 0x11 0 0x00aa>, | ||
77 | <3 0x12 0 0x4105>, | ||
78 | <3 0x13 0 0x0a60>; | ||
79 | }; | ||
80 | phy7: ethernet-phy@7 { | ||
81 | reg = <7>; | ||
82 | compatible = "marvell,88e1149r"; | ||
83 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
84 | <3 0x11 0 0x00aa>, | ||
85 | <3 0x12 0 0x4105>, | ||
86 | <3 0x13 0 0x0a60>; | ||
87 | }; | ||
88 | phy8: ethernet-phy@8 { | ||
89 | reg = <8>; | ||
90 | compatible = "marvell,88e1149r"; | ||
91 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
92 | <3 0x11 0 0x00aa>, | ||
93 | <3 0x12 0 0x4105>, | ||
94 | <3 0x13 0 0x0a60>; | ||
95 | }; | ||
96 | phy9: ethernet-phy@9 { | ||
97 | reg = <9>; | ||
98 | compatible = "marvell,88e1149r"; | ||
99 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
100 | <3 0x11 0 0x00aa>, | ||
101 | <3 0x12 0 0x4105>, | ||
102 | <3 0x13 0 0x0a60>; | ||
103 | }; | ||
104 | }; | ||
105 | |||
106 | smi1: mdio@1180000001900 { | ||
107 | compatible = "cavium,octeon-3860-mdio"; | ||
108 | #address-cells = <1>; | ||
109 | #size-cells = <0>; | ||
110 | reg = <0x11800 0x00001900 0x0 0x40>; | ||
111 | |||
112 | phy100: ethernet-phy@1 { | ||
113 | reg = <1>; | ||
114 | compatible = "marvell,88e1149r"; | ||
115 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
116 | <3 0x11 0 0x00aa>, | ||
117 | <3 0x12 0 0x4105>, | ||
118 | <3 0x13 0 0x0a60>; | ||
119 | interrupt-parent = <&gpio>; | ||
120 | interrupts = <12 8>; /* Pin 12, active low */ | ||
121 | }; | ||
122 | phy101: ethernet-phy@2 { | ||
123 | reg = <2>; | ||
124 | compatible = "marvell,88e1149r"; | ||
125 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
126 | <3 0x11 0 0x00aa>, | ||
127 | <3 0x12 0 0x4105>, | ||
128 | <3 0x13 0 0x0a60>; | ||
129 | interrupt-parent = <&gpio>; | ||
130 | interrupts = <12 8>; /* Pin 12, active low */ | ||
131 | }; | ||
132 | phy102: ethernet-phy@3 { | ||
133 | reg = <3>; | ||
134 | compatible = "marvell,88e1149r"; | ||
135 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
136 | <3 0x11 0 0x00aa>, | ||
137 | <3 0x12 0 0x4105>, | ||
138 | <3 0x13 0 0x0a60>; | ||
139 | interrupt-parent = <&gpio>; | ||
140 | interrupts = <12 8>; /* Pin 12, active low */ | ||
141 | }; | ||
142 | phy103: ethernet-phy@4 { | ||
143 | reg = <4>; | ||
144 | compatible = "marvell,88e1149r"; | ||
145 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
146 | <3 0x11 0 0x00aa>, | ||
147 | <3 0x12 0 0x4105>, | ||
148 | <3 0x13 0 0x0a60>; | ||
149 | interrupt-parent = <&gpio>; | ||
150 | interrupts = <12 8>; /* Pin 12, active low */ | ||
151 | }; | ||
152 | }; | ||
153 | |||
154 | mix0: ethernet@1070000100000 { | ||
155 | compatible = "cavium,octeon-5750-mix"; | ||
156 | reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ | ||
157 | <0x11800 0xE0000000 0x0 0x300>, /* AGL */ | ||
158 | <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ | ||
159 | <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ | ||
160 | cell-index = <0>; | ||
161 | interrupts = <0 62>, <1 46>; | ||
162 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
163 | phy-handle = <&phy0>; | ||
164 | }; | ||
165 | |||
166 | mix1: ethernet@1070000100800 { | ||
167 | compatible = "cavium,octeon-5750-mix"; | ||
168 | reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ | ||
169 | <0x11800 0xE0000800 0x0 0x300>, /* AGL */ | ||
170 | <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ | ||
171 | <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ | ||
172 | cell-index = <1>; | ||
173 | interrupts = <1 18>, < 1 46>; | ||
174 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
175 | phy-handle = <&phy1>; | ||
176 | }; | ||
177 | |||
178 | pip: pip@11800a0000000 { | ||
179 | interface@0 { | ||
180 | ethernet@0 { | ||
181 | phy-handle = <&phy2>; | ||
182 | cavium,alt-phy-handle = <&phy100>; | ||
183 | rx-delay = <0>; | ||
184 | tx-delay = <0>; | ||
185 | fixed-link { | ||
186 | speed = <1000>; | ||
187 | full-duplex; | ||
188 | }; | ||
189 | }; | ||
190 | ethernet@1 { | ||
191 | phy-handle = <&phy3>; | ||
192 | cavium,alt-phy-handle = <&phy101>; | ||
193 | rx-delay = <0>; | ||
194 | tx-delay = <0>; | ||
195 | fixed-link { | ||
196 | speed = <1000>; | ||
197 | full-duplex; | ||
198 | }; | ||
199 | }; | ||
200 | ethernet@2 { | ||
201 | phy-handle = <&phy4>; | ||
202 | cavium,alt-phy-handle = <&phy102>; | ||
203 | rx-delay = <0>; | ||
204 | tx-delay = <0>; | ||
205 | }; | ||
206 | ethernet@3 { | ||
207 | compatible = "cavium,octeon-3860-pip-port"; | ||
208 | reg = <0x3>; /* Port */ | ||
209 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
210 | phy-handle = <&phy5>; | ||
211 | cavium,alt-phy-handle = <&phy103>; | ||
212 | }; | ||
213 | ethernet@4 { | ||
214 | compatible = "cavium,octeon-3860-pip-port"; | ||
215 | reg = <0x4>; /* Port */ | ||
216 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
217 | }; | ||
218 | ethernet@5 { | ||
219 | compatible = "cavium,octeon-3860-pip-port"; | ||
220 | reg = <0x5>; /* Port */ | ||
221 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
222 | }; | ||
223 | ethernet@6 { | ||
224 | compatible = "cavium,octeon-3860-pip-port"; | ||
225 | reg = <0x6>; /* Port */ | ||
226 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
227 | }; | ||
228 | ethernet@7 { | ||
229 | compatible = "cavium,octeon-3860-pip-port"; | ||
230 | reg = <0x7>; /* Port */ | ||
231 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
232 | }; | ||
233 | ethernet@8 { | ||
234 | compatible = "cavium,octeon-3860-pip-port"; | ||
235 | reg = <0x8>; /* Port */ | ||
236 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
237 | }; | ||
238 | ethernet@9 { | ||
239 | compatible = "cavium,octeon-3860-pip-port"; | ||
240 | reg = <0x9>; /* Port */ | ||
241 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
242 | }; | ||
243 | ethernet@a { | ||
244 | compatible = "cavium,octeon-3860-pip-port"; | ||
245 | reg = <0xa>; /* Port */ | ||
246 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
247 | }; | ||
248 | ethernet@b { | ||
249 | compatible = "cavium,octeon-3860-pip-port"; | ||
250 | reg = <0xb>; /* Port */ | ||
251 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
252 | }; | ||
253 | ethernet@c { | ||
254 | compatible = "cavium,octeon-3860-pip-port"; | ||
255 | reg = <0xc>; /* Port */ | ||
256 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
257 | }; | ||
258 | ethernet@d { | ||
259 | compatible = "cavium,octeon-3860-pip-port"; | ||
260 | reg = <0xd>; /* Port */ | ||
261 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
262 | }; | ||
263 | ethernet@e { | ||
264 | compatible = "cavium,octeon-3860-pip-port"; | ||
265 | reg = <0xe>; /* Port */ | ||
266 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
267 | }; | ||
268 | ethernet@f { | ||
269 | compatible = "cavium,octeon-3860-pip-port"; | ||
270 | reg = <0xf>; /* Port */ | ||
271 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
272 | }; | ||
273 | }; | ||
274 | |||
275 | interface@1 { | ||
276 | ethernet@0 { | ||
277 | compatible = "cavium,octeon-3860-pip-port"; | ||
278 | reg = <0x0>; /* Port */ | ||
279 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
280 | phy-handle = <&phy6>; | ||
281 | }; | ||
282 | ethernet@1 { | ||
283 | compatible = "cavium,octeon-3860-pip-port"; | ||
284 | reg = <0x1>; /* Port */ | ||
285 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
286 | phy-handle = <&phy7>; | ||
287 | }; | ||
288 | ethernet@2 { | ||
289 | compatible = "cavium,octeon-3860-pip-port"; | ||
290 | reg = <0x2>; /* Port */ | ||
291 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
292 | phy-handle = <&phy8>; | ||
293 | }; | ||
294 | ethernet@3 { | ||
295 | compatible = "cavium,octeon-3860-pip-port"; | ||
296 | reg = <0x3>; /* Port */ | ||
297 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
298 | phy-handle = <&phy9>; | ||
299 | }; | ||
300 | }; | ||
301 | }; | ||
302 | |||
303 | twsi0: i2c@1180000001000 { | ||
304 | rtc@68 { | ||
305 | compatible = "dallas,ds1337"; | ||
306 | reg = <0x68>; | ||
307 | }; | ||
308 | tmp@4c { | ||
309 | compatible = "ti,tmp421"; | ||
310 | reg = <0x4c>; | ||
311 | }; | ||
312 | }; | ||
313 | |||
314 | twsi1: i2c@1180000001200 { | ||
315 | #address-cells = <1>; | ||
316 | #size-cells = <0>; | ||
317 | compatible = "cavium,octeon-3860-twsi"; | ||
318 | reg = <0x11800 0x00001200 0x0 0x200>; | ||
319 | interrupts = <0 59>; | ||
320 | clock-frequency = <100000>; | ||
321 | }; | ||
322 | |||
323 | uart1: serial@1180000000c00 { | ||
324 | compatible = "cavium,octeon-3860-uart","ns16550"; | ||
325 | reg = <0x11800 0x00000c00 0x0 0x400>; | ||
326 | clock-frequency = <0>; | ||
327 | current-speed = <115200>; | ||
328 | reg-shift = <3>; | ||
329 | interrupts = <0 35>; | ||
330 | }; | ||
331 | |||
332 | uart2: serial@1180000000400 { | ||
333 | compatible = "cavium,octeon-3860-uart","ns16550"; | ||
334 | reg = <0x11800 0x00000400 0x0 0x400>; | ||
335 | clock-frequency = <0>; | ||
336 | current-speed = <115200>; | ||
337 | reg-shift = <3>; | ||
338 | interrupts = <1 16>; | ||
339 | }; | ||
340 | |||
341 | bootbus: bootbus@1180000000000 { | ||
342 | led0: led-display@4,0 { | ||
343 | compatible = "avago,hdsp-253x"; | ||
344 | reg = <4 0x20 0x20>, <4 0 0x20>; | ||
345 | }; | ||
346 | |||
347 | cf0: compact-flash@5,0 { | ||
348 | compatible = "cavium,ebt3000-compact-flash"; | ||
349 | reg = <5 0 0x10000>, <6 0 0x10000>; | ||
350 | cavium,bus-width = <16>; | ||
351 | cavium,true-ide; | ||
352 | cavium,dma-engine-handle = <&dma0>; | ||
353 | }; | ||
354 | }; | ||
355 | |||
356 | uctl: uctl@118006f000000 { | ||
357 | compatible = "cavium,octeon-6335-uctl"; | ||
358 | reg = <0x11800 0x6f000000 0x0 0x100>; | ||
359 | ranges; /* Direct mapping */ | ||
360 | #address-cells = <2>; | ||
361 | #size-cells = <2>; | ||
362 | /* 12MHz, 24MHz and 48MHz allowed */ | ||
363 | refclk-frequency = <12000000>; | ||
364 | /* Either "crystal" or "external" */ | ||
365 | refclk-type = "crystal"; | ||
366 | |||
367 | ehci@16f0000000000 { | ||
368 | compatible = "cavium,octeon-6335-ehci","usb-ehci"; | ||
369 | reg = <0x16f00 0x00000000 0x0 0x100>; | ||
370 | interrupts = <0 56>; | ||
371 | big-endian-regs; | ||
372 | }; | ||
373 | ohci@16f0000000400 { | ||
374 | compatible = "cavium,octeon-6335-ohci","usb-ohci"; | ||
375 | reg = <0x16f00 0x00000400 0x0 0x100>; | ||
376 | interrupts = <0 56>; | ||
377 | big-endian-regs; | ||
378 | }; | ||
379 | }; | ||
380 | |||
381 | usbn: usbn@1180068000000 { | ||
382 | /* 12MHz, 24MHz and 48MHz allowed */ | ||
383 | refclk-frequency = <12000000>; | ||
384 | /* Either "crystal" or "external" */ | ||
385 | refclk-type = "crystal"; | ||
386 | }; | ||
387 | }; | ||
388 | |||
389 | aliases { | ||
390 | mix0 = &mix0; | ||
391 | mix1 = &mix1; | ||
392 | pip = &pip; | ||
393 | smi0 = &smi0; | ||
394 | smi1 = &smi1; | ||
395 | twsi0 = &twsi0; | ||
396 | twsi1 = &twsi1; | ||
397 | uart0 = &uart0; | ||
398 | uart1 = &uart1; | ||
399 | uart2 = &uart2; | ||
400 | flash0 = &flash0; | ||
401 | cf0 = &cf0; | ||
402 | uctl = &uctl; | ||
403 | usbn = &usbn; | ||
404 | led0 = &led0; | ||
405 | }; | ||
406 | }; | ||