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-rw-r--r--arch/mips/boot/dts/ingenic/jz4780.dtsi497
1 files changed, 497 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
new file mode 100644
index 000000000..830e5dd35
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -0,0 +1,497 @@
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4#include <dt-bindings/dma/jz4780-dma.h>
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,jz4780";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
19
20 clocks = <&cgu JZ4780_CLK_CPU>;
21 clock-names = "cpu";
22 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
27 reg = <1>;
28
29 clocks = <&cgu JZ4780_CLK_CORE1>;
30 clock-names = "cpu";
31 };
32 };
33
34 cpuintc: interrupt-controller {
35 #address-cells = <0>;
36 #interrupt-cells = <1>;
37 interrupt-controller;
38 compatible = "mti,cpu-interrupt-controller";
39 };
40
41 intc: interrupt-controller@10001000 {
42 compatible = "ingenic,jz4780-intc";
43 reg = <0x10001000 0x50>;
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47
48 interrupt-parent = <&cpuintc>;
49 interrupts = <2>;
50 };
51
52 ext: ext {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 };
56
57 rtc: rtc {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 cgu: jz4780-cgu@10000000 {
64 compatible = "ingenic,jz4780-cgu";
65 reg = <0x10000000 0x100>;
66
67 clocks = <&ext>, <&rtc>;
68 clock-names = "ext", "rtc";
69
70 #clock-cells = <1>;
71 };
72
73 tcu: timer@10002000 {
74 compatible = "ingenic,jz4780-tcu",
75 "ingenic,jz4770-tcu",
76 "simple-mfd";
77 reg = <0x10002000 0x1000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0x0 0x10002000 0x1000>;
81
82 #clock-cells = <1>;
83
84 clocks = <&cgu JZ4780_CLK_RTCLK>,
85 <&cgu JZ4780_CLK_EXCLK>,
86 <&cgu JZ4780_CLK_PCLK>;
87 clock-names = "rtc", "ext", "pclk";
88
89 interrupt-controller;
90 #interrupt-cells = <1>;
91
92 interrupt-parent = <&intc>;
93 interrupts = <27 26 25>;
94
95 watchdog: watchdog@0 {
96 compatible = "ingenic,jz4780-watchdog";
97 reg = <0x0 0xc>;
98
99 clocks = <&tcu TCU_CLK_WDT>;
100 clock-names = "wdt";
101 };
102
103 pwm: pwm@40 {
104 compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
105 reg = <0x40 0x80>;
106
107 #pwm-cells = <3>;
108
109 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
110 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
111 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
112 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
113 clock-names = "timer0", "timer1", "timer2", "timer3",
114 "timer4", "timer5", "timer6", "timer7";
115 };
116
117 ost: timer@e0 {
118 compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
119 reg = <0xe0 0x20>;
120
121 clocks = <&tcu TCU_CLK_OST>;
122 clock-names = "ost";
123
124 interrupts = <15>;
125 };
126 };
127
128 rtc_dev: rtc@10003000 {
129 compatible = "ingenic,jz4780-rtc";
130 reg = <0x10003000 0x4c>;
131
132 interrupt-parent = <&intc>;
133 interrupts = <32>;
134
135 clocks = <&cgu JZ4780_CLK_RTCLK>;
136 clock-names = "rtc";
137 };
138
139 pinctrl: pin-controller@10010000 {
140 compatible = "ingenic,jz4780-pinctrl";
141 reg = <0x10010000 0x600>;
142
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 gpa: gpio@0 {
147 compatible = "ingenic,jz4780-gpio";
148 reg = <0>;
149
150 gpio-controller;
151 gpio-ranges = <&pinctrl 0 0 32>;
152 #gpio-cells = <2>;
153
154 interrupt-controller;
155 #interrupt-cells = <2>;
156
157 interrupt-parent = <&intc>;
158 interrupts = <17>;
159 };
160
161 gpb: gpio@1 {
162 compatible = "ingenic,jz4780-gpio";
163 reg = <1>;
164
165 gpio-controller;
166 gpio-ranges = <&pinctrl 0 32 32>;
167 #gpio-cells = <2>;
168
169 interrupt-controller;
170 #interrupt-cells = <2>;
171
172 interrupt-parent = <&intc>;
173 interrupts = <16>;
174 };
175
176 gpc: gpio@2 {
177 compatible = "ingenic,jz4780-gpio";
178 reg = <2>;
179
180 gpio-controller;
181 gpio-ranges = <&pinctrl 0 64 32>;
182 #gpio-cells = <2>;
183
184 interrupt-controller;
185 #interrupt-cells = <2>;
186
187 interrupt-parent = <&intc>;
188 interrupts = <15>;
189 };
190
191 gpd: gpio@3 {
192 compatible = "ingenic,jz4780-gpio";
193 reg = <3>;
194
195 gpio-controller;
196 gpio-ranges = <&pinctrl 0 96 32>;
197 #gpio-cells = <2>;
198
199 interrupt-controller;
200 #interrupt-cells = <2>;
201
202 interrupt-parent = <&intc>;
203 interrupts = <14>;
204 };
205
206 gpe: gpio@4 {
207 compatible = "ingenic,jz4780-gpio";
208 reg = <4>;
209
210 gpio-controller;
211 gpio-ranges = <&pinctrl 0 128 32>;
212 #gpio-cells = <2>;
213
214 interrupt-controller;
215 #interrupt-cells = <2>;
216
217 interrupt-parent = <&intc>;
218 interrupts = <13>;
219 };
220
221 gpf: gpio@5 {
222 compatible = "ingenic,jz4780-gpio";
223 reg = <5>;
224
225 gpio-controller;
226 gpio-ranges = <&pinctrl 0 160 32>;
227 #gpio-cells = <2>;
228
229 interrupt-controller;
230 #interrupt-cells = <2>;
231
232 interrupt-parent = <&intc>;
233 interrupts = <12>;
234 };
235 };
236
237 spi_gpio {
238 compatible = "spi-gpio";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 num-chipselects = <2>;
242
243 gpio-miso = <&gpe 14 0>;
244 gpio-sck = <&gpe 15 0>;
245 gpio-mosi = <&gpe 17 0>;
246 cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
247
248 spidev@0 {
249 compatible = "spidev";
250 reg = <0>;
251 spi-max-frequency = <1000000>;
252 };
253 };
254
255 uart0: serial@10030000 {
256 compatible = "ingenic,jz4780-uart";
257 reg = <0x10030000 0x100>;
258
259 interrupt-parent = <&intc>;
260 interrupts = <51>;
261
262 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
263 clock-names = "baud", "module";
264
265 status = "disabled";
266 };
267
268 uart1: serial@10031000 {
269 compatible = "ingenic,jz4780-uart";
270 reg = <0x10031000 0x100>;
271
272 interrupt-parent = <&intc>;
273 interrupts = <50>;
274
275 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
276 clock-names = "baud", "module";
277
278 status = "disabled";
279 };
280
281 uart2: serial@10032000 {
282 compatible = "ingenic,jz4780-uart";
283 reg = <0x10032000 0x100>;
284
285 interrupt-parent = <&intc>;
286 interrupts = <49>;
287
288 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
289 clock-names = "baud", "module";
290
291 status = "disabled";
292 };
293
294 uart3: serial@10033000 {
295 compatible = "ingenic,jz4780-uart";
296 reg = <0x10033000 0x100>;
297
298 interrupt-parent = <&intc>;
299 interrupts = <48>;
300
301 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
302 clock-names = "baud", "module";
303
304 status = "disabled";
305 };
306
307 uart4: serial@10034000 {
308 compatible = "ingenic,jz4780-uart";
309 reg = <0x10034000 0x100>;
310
311 interrupt-parent = <&intc>;
312 interrupts = <34>;
313
314 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
315 clock-names = "baud", "module";
316
317 status = "disabled";
318 };
319
320 i2c0: i2c@10050000 {
321 compatible = "ingenic,jz4780-i2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
324
325 reg = <0x10050000 0x1000>;
326
327 interrupt-parent = <&intc>;
328 interrupts = <60>;
329
330 clocks = <&cgu JZ4780_CLK_SMB0>;
331 clock-frequency = <100000>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pins_i2c0_data>;
334
335 status = "disabled";
336 };
337
338 i2c1: i2c@10051000 {
339 compatible = "ingenic,jz4780-i2c";
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0x10051000 0x1000>;
343
344 interrupt-parent = <&intc>;
345 interrupts = <59>;
346
347 clocks = <&cgu JZ4780_CLK_SMB1>;
348 clock-frequency = <100000>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&pins_i2c1_data>;
351
352 status = "disabled";
353 };
354
355 i2c2: i2c@10052000 {
356 compatible = "ingenic,jz4780-i2c";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 reg = <0x10052000 0x1000>;
360
361 interrupt-parent = <&intc>;
362 interrupts = <58>;
363
364 clocks = <&cgu JZ4780_CLK_SMB2>;
365 clock-frequency = <100000>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pins_i2c2_data>;
368
369 status = "disabled";
370 };
371
372 i2c3: i2c@10053000 {
373 compatible = "ingenic,jz4780-i2c";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <0x10053000 0x1000>;
377
378 interrupt-parent = <&intc>;
379 interrupts = <57>;
380
381 clocks = <&cgu JZ4780_CLK_SMB3>;
382 clock-frequency = <100000>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pins_i2c3_data>;
385
386 status = "disabled";
387 };
388
389 i2c4: i2c@10054000 {
390 compatible = "ingenic,jz4780-i2c";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 reg = <0x10054000 0x1000>;
394
395 interrupt-parent = <&intc>;
396 interrupts = <56>;
397
398 clocks = <&cgu JZ4780_CLK_SMB4>;
399 clock-frequency = <100000>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pins_i2c4_data>;
402
403 status = "disabled";
404 };
405
406 nemc: nemc@13410000 {
407 compatible = "ingenic,jz4780-nemc", "simple-mfd";
408 reg = <0x13410000 0x10000>;
409 #address-cells = <2>;
410 #size-cells = <1>;
411 ranges = <0 0 0x13410000 0x10000>,
412 <1 0 0x1b000000 0x1000000>,
413 <2 0 0x1a000000 0x1000000>,
414 <3 0 0x19000000 0x1000000>,
415 <4 0 0x18000000 0x1000000>,
416 <5 0 0x17000000 0x1000000>,
417 <6 0 0x16000000 0x1000000>;
418
419 clocks = <&cgu JZ4780_CLK_NEMC>;
420
421 status = "disabled";
422
423 efuse: efuse@d0 {
424 reg = <0 0xd0 0x30>;
425 compatible = "ingenic,jz4780-efuse";
426
427 clocks = <&cgu JZ4780_CLK_AHB2>;
428
429 #address-cells = <1>;
430 #size-cells = <1>;
431
432 eth0_addr: eth-mac-addr@22 {
433 reg = <0x22 0x6>;
434 };
435 };
436 };
437
438 dma: dma@13420000 {
439 compatible = "ingenic,jz4780-dma";
440 reg = <0x13420000 0x400>, <0x13421000 0x40>;
441 #dma-cells = <2>;
442
443 interrupt-parent = <&intc>;
444 interrupts = <10>;
445
446 clocks = <&cgu JZ4780_CLK_PDMA>;
447 };
448
449 mmc0: mmc@13450000 {
450 compatible = "ingenic,jz4780-mmc";
451 reg = <0x13450000 0x1000>;
452
453 interrupt-parent = <&intc>;
454 interrupts = <37>;
455
456 clocks = <&cgu JZ4780_CLK_MSC0>;
457 clock-names = "mmc";
458
459 cap-sd-highspeed;
460 cap-mmc-highspeed;
461 cap-sdio-irq;
462 dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
463 <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
464 dma-names = "rx", "tx";
465
466 status = "disabled";
467 };
468
469 mmc1: mmc@13460000 {
470 compatible = "ingenic,jz4780-mmc";
471 reg = <0x13460000 0x1000>;
472
473 interrupt-parent = <&intc>;
474 interrupts = <36>;
475
476 clocks = <&cgu JZ4780_CLK_MSC1>;
477 clock-names = "mmc";
478
479 cap-sd-highspeed;
480 cap-mmc-highspeed;
481 cap-sdio-irq;
482 dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
483 <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
484 dma-names = "rx", "tx";
485
486 status = "disabled";
487 };
488
489 bch: bch@134d0000 {
490 compatible = "ingenic,jz4780-bch";
491 reg = <0x134d0000 0x10000>;
492
493 clocks = <&cgu JZ4780_CLK_BCH>;
494
495 status = "disabled";
496 };
497};
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-04-17 23:51:08 +0800