1 files changed, 267 insertions, 0 deletions

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000..535a98284
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "mscc,ocelot";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "mips,mips24KEc";
+                        device_type = "cpu";
+                        clocks = <&cpu_clk>;
+                        reg = <0>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        cpu_clk: cpu-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+        };
+
+        ahb_clk: ahb-clk {
+                compatible = "fixed-factor-clock";
+                #clock-cells = <0>;
+                clocks = <&cpu_clk>;
+                clock-div = <2>;
+                clock-mult = <1>;
+        };
+
+        ahb@70000000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x70000000 0x2000000>;
+
+                interrupt-parent = <&intc>;
+
+                cpu_ctrl: syscon@0 {
+                        compatible = "mscc,ocelot-cpu-syscon", "syscon";
+                        reg = <0x0 0x2c>;
+                };
+
+                intc: interrupt-controller@70 {
+                        compatible = "mscc,ocelot-icpu-intr";
+                        reg = <0x70 0x70>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                uart0: serial@100000 {
+                        pinctrl-0 = <&uart_pins>;
+                        pinctrl-names = "default";
+                        compatible = "ns16550a";
+                        reg = <0x100000 0x20>;
+                        interrupts = <6>;
+                        clocks = <&ahb_clk>;
+                        reg-io-width = <4>;
+                        reg-shift = <2>;
+
+                        status = "disabled";
+                };
+
+                i2c: i2c@100400 {
+                        compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+                        pinctrl-0 = <&i2c_pins>;
+                        pinctrl-names = "default";
+                        reg = <0x100400 0x100>, <0x198 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <8>;
+                        clocks = <&ahb_clk>;
+
+                        status = "disabled";
+                };
+
+                uart2: serial@100800 {
+                        pinctrl-0 = <&uart2_pins>;
+                        pinctrl-names = "default";
+                        compatible = "ns16550a";
+                        reg = <0x100800 0x20>;
+                        interrupts = <7>;
+                        clocks = <&ahb_clk>;
+                        reg-io-width = <4>;
+                        reg-shift = <2>;
+
+                        status = "disabled";
+                };
+
+                spi: spi@101000 {
+                        compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x101000 0x100>, <0x3c 0x18>;
+                        interrupts = <9>;
+                        clocks = <&ahb_clk>;
+
+                        status = "disabled";
+                };
+
+                switch@1010000 {
+                        compatible = "mscc,vsc7514-switch";
+                        reg = <0x1010000 0x10000>,
+                              <0x1030000 0x10000>,
+                              <0x1080000 0x100>,
+                              <0x10e0000 0x10000>,
+                              <0x11e0000 0x100>,
+                              <0x11f0000 0x100>,
+                              <0x1200000 0x100>,
+                              <0x1210000 0x100>,
+                              <0x1220000 0x100>,
+                              <0x1230000 0x100>,
+                              <0x1240000 0x100>,
+                              <0x1250000 0x100>,
+                              <0x1260000 0x100>,
+                              <0x1270000 0x100>,
+                              <0x1280000 0x100>,
+                              <0x1800000 0x80000>,
+                              <0x1880000 0x10000>,
+                              <0x1040000 0x10000>,
+                              <0x1050000 0x10000>,
+                              <0x1060000 0x10000>;
+                        reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
+                                    "port2", "port3", "port4", "port5", "port6",
+                                    "port7", "port8", "port9", "port10", "qsys",
+                                    "ana", "s0", "s1", "s2";
+                        interrupts = <18 21 22>;
+                        interrupt-names = "ptp_rdy", "xtr", "inj";
+
+                        ethernet-ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port0: port@0 {
+                                        reg = <0>;
+                                };
+                                port1: port@1 {
+                                        reg = <1>;
+                                };
+                                port2: port@2 {
+                                        reg = <2>;
+                                };
+                                port3: port@3 {
+                                        reg = <3>;
+                                };
+                                port4: port@4 {
+                                        reg = <4>;
+                                };
+                                port5: port@5 {
+                                        reg = <5>;
+                                };
+                                port6: port@6 {
+                                        reg = <6>;
+                                };
+                                port7: port@7 {
+                                        reg = <7>;
+                                };
+                                port8: port@8 {
+                                        reg = <8>;
+                                };
+                                port9: port@9 {
+                                        reg = <9>;
+                                };
+                                port10: port@10 {
+                                        reg = <10>;
+                                };
+                        };
+                };
+
+                reset@1070008 {
+                        compatible = "mscc,ocelot-chip-reset";
+                        reg = <0x1070008 0x4>;
+                };
+
+                gpio: pinctrl@1070034 {
+                        compatible = "mscc,ocelot-pinctrl";
+                        reg = <0x1070034 0x68>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&gpio 0 0 22>;
+                        interrupt-controller;
+                        interrupts = <13>;
+                        #interrupt-cells = <2>;
+
+                        i2c_pins: i2c-pins {
+                                pins = "GPIO_16", "GPIO_17";
+                                function = "twi";
+                        };
+
+                        uart_pins: uart-pins {
+                                pins = "GPIO_6", "GPIO_7";
+                                function = "uart";
+                        };
+
+                        uart2_pins: uart2-pins {
+                                pins = "GPIO_12", "GPIO_13";
+                                function = "uart2";
+                        };
+
+                        miim1: miim1 {
+                                pins = "GPIO_14", "GPIO_15";
+                                function = "miim";
+                        };
+
+                };
+
+                mdio0: mdio@107009c {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "mscc,ocelot-miim";
+                        reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+                        interrupts = <14>;
+                        status = "disabled";
+
+                        phy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                reg = <2>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                reg = <3>;
+                        };
+                };
+
+                mdio1: mdio@10700c0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "mscc,ocelot-miim";
+                        reg = <0x10700c0 0x24>;
+                        interrupts = <15>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&miim1>;
+                        status = "disabled";
+                };
+
+                hsio: syscon@10d0000 {
+                        compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+                        reg = <0x10d0000 0x10000>;
+
+                        serdes: serdes {
+                                compatible = "mscc,vsc7514-serdes";
+                                #phy-cells = <2>;
+                        };
+                };
+        };
+};