1 files changed, 59 insertions, 0 deletions

diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
new file mode 100644
index 000000000..61132cf15
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,rt3883-soc";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips74Kc";
+                };
+        };
+
+        cpuintc: cpuintc {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc@0 {
+                        compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: intc@200 {
+                        compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                memc@300 {
+                        compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uartlite@c00 {
+                        compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+
+                        reg-shift = <2>;
+                };
+        };
+};