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-rw-r--r--arch/mips/mm/uasm.c643
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400,
28 SIMM9 = 0x800,
29};
30
31#define OP_MASK 0x3f
32#define OP_SH 26
33#define RD_MASK 0x1f
34#define RD_SH 11
35#define RE_MASK 0x1f
36#define RE_SH 6
37#define IMM_MASK 0xffff
38#define IMM_SH 0
39#define JIMM_MASK 0x3ffffff
40#define JIMM_SH 0
41#define FUNC_MASK 0x3f
42#define FUNC_SH 0
43#define SET_MASK 0x7
44#define SET_SH 0
45#define SIMM9_SH 7
46#define SIMM9_MASK 0x1ff
47
48enum opcode {
49 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
50 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
51 insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
52 insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
53 insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
54 insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
55 insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
56 insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
57 insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
58 insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
59 insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
60 insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
61 insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
62 insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
63 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
64 insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
65 insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
66 insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
67 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
68 insn_wsbh, insn_xor, insn_xori, insn_yield,
69 insn_invalid /* insn_invalid must be last */
70};
71
72struct insn {
73 u32 match;
74 enum fields fields;
75};
76
77static inline u32 build_rs(u32 arg)
78{
79 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
80
81 return (arg & RS_MASK) << RS_SH;
82}
83
84static inline u32 build_rt(u32 arg)
85{
86 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
87
88 return (arg & RT_MASK) << RT_SH;
89}
90
91static inline u32 build_rd(u32 arg)
92{
93 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
94
95 return (arg & RD_MASK) << RD_SH;
96}
97
98static inline u32 build_re(u32 arg)
99{
100 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
101
102 return (arg & RE_MASK) << RE_SH;
103}
104
105static inline u32 build_simm(s32 arg)
106{
107 WARN(arg > 0x7fff || arg < -0x8000,
108 KERN_WARNING "Micro-assembler field overflow\n");
109
110 return arg & 0xffff;
111}
112
113static inline u32 build_uimm(u32 arg)
114{
115 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
116
117 return arg & IMM_MASK;
118}
119
120static inline u32 build_scimm(u32 arg)
121{
122 WARN(arg & ~SCIMM_MASK,
123 KERN_WARNING "Micro-assembler field overflow\n");
124
125 return (arg & SCIMM_MASK) << SCIMM_SH;
126}
127
128static inline u32 build_scimm9(s32 arg)
129{
130 WARN((arg > 0xff || arg < -0x100),
131 KERN_WARNING "Micro-assembler field overflow\n");
132
133 return (arg & SIMM9_MASK) << SIMM9_SH;
134}
135
136static inline u32 build_func(u32 arg)
137{
138 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
139
140 return arg & FUNC_MASK;
141}
142
143static inline u32 build_set(u32 arg)
144{
145 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
146
147 return arg & SET_MASK;
148}
149
150static void build_insn(u32 **buf, enum opcode opc, ...);
151
152#define I_u1u2u3(op) \
153Ip_u1u2u3(op) \
154{ \
155 build_insn(buf, insn##op, a, b, c); \
156} \
157UASM_EXPORT_SYMBOL(uasm_i##op);
158
159#define I_s3s1s2(op) \
160Ip_s3s1s2(op) \
161{ \
162 build_insn(buf, insn##op, b, c, a); \
163} \
164UASM_EXPORT_SYMBOL(uasm_i##op);
165
166#define I_u2u1u3(op) \
167Ip_u2u1u3(op) \
168{ \
169 build_insn(buf, insn##op, b, a, c); \
170} \
171UASM_EXPORT_SYMBOL(uasm_i##op);
172
173#define I_u3u2u1(op) \
174Ip_u3u2u1(op) \
175{ \
176 build_insn(buf, insn##op, c, b, a); \
177} \
178UASM_EXPORT_SYMBOL(uasm_i##op);
179
180#define I_u3u1u2(op) \
181Ip_u3u1u2(op) \
182{ \
183 build_insn(buf, insn##op, b, c, a); \
184} \
185UASM_EXPORT_SYMBOL(uasm_i##op);
186
187#define I_u1u2s3(op) \
188Ip_u1u2s3(op) \
189{ \
190 build_insn(buf, insn##op, a, b, c); \
191} \
192UASM_EXPORT_SYMBOL(uasm_i##op);
193
194#define I_u2s3u1(op) \
195Ip_u2s3u1(op) \
196{ \
197 build_insn(buf, insn##op, c, a, b); \
198} \
199UASM_EXPORT_SYMBOL(uasm_i##op);
200
201#define I_u2u1s3(op) \
202Ip_u2u1s3(op) \
203{ \
204 build_insn(buf, insn##op, b, a, c); \
205} \
206UASM_EXPORT_SYMBOL(uasm_i##op);
207
208#define I_u2u1msbu3(op) \
209Ip_u2u1msbu3(op) \
210{ \
211 build_insn(buf, insn##op, b, a, c+d-1, c); \
212} \
213UASM_EXPORT_SYMBOL(uasm_i##op);
214
215#define I_u2u1msb32u3(op) \
216Ip_u2u1msbu3(op) \
217{ \
218 build_insn(buf, insn##op, b, a, c+d-33, c); \
219} \
220UASM_EXPORT_SYMBOL(uasm_i##op);
221
222#define I_u2u1msb32msb3(op) \
223Ip_u2u1msbu3(op) \
224{ \
225 build_insn(buf, insn##op, b, a, c+d-33, c-32); \
226} \
227UASM_EXPORT_SYMBOL(uasm_i##op);
228
229#define I_u2u1msbdu3(op) \
230Ip_u2u1msbu3(op) \
231{ \
232 build_insn(buf, insn##op, b, a, d-1, c); \
233} \
234UASM_EXPORT_SYMBOL(uasm_i##op);
235
236#define I_u1u2(op) \
237Ip_u1u2(op) \
238{ \
239 build_insn(buf, insn##op, a, b); \
240} \
241UASM_EXPORT_SYMBOL(uasm_i##op);
242
243#define I_u2u1(op) \
244Ip_u1u2(op) \
245{ \
246 build_insn(buf, insn##op, b, a); \
247} \
248UASM_EXPORT_SYMBOL(uasm_i##op);
249
250#define I_u1s2(op) \
251Ip_u1s2(op) \
252{ \
253 build_insn(buf, insn##op, a, b); \
254} \
255UASM_EXPORT_SYMBOL(uasm_i##op);
256
257#define I_u1(op) \
258Ip_u1(op) \
259{ \
260 build_insn(buf, insn##op, a); \
261} \
262UASM_EXPORT_SYMBOL(uasm_i##op);
263
264#define I_0(op) \
265Ip_0(op) \
266{ \
267 build_insn(buf, insn##op); \
268} \
269UASM_EXPORT_SYMBOL(uasm_i##op);
270
271I_u2u1s3(_addiu)
272I_u3u1u2(_addu)
273I_u2u1u3(_andi)
274I_u3u1u2(_and)
275I_u1u2s3(_beq)
276I_u1u2s3(_beql)
277I_u1s2(_bgez)
278I_u1s2(_bgezl)
279I_u1s2(_bgtz)
280I_u1s2(_blez)
281I_u1s2(_bltz)
282I_u1s2(_bltzl)
283I_u1u2s3(_bne)
284I_u1(_break)
285I_u2s3u1(_cache)
286I_u1u2(_cfc1)
287I_u2u1(_cfcmsa)
288I_u1u2(_ctc1)
289I_u2u1(_ctcmsa)
290I_u1u2(_ddivu)
291I_u3u1u2(_ddivu_r6)
292I_u1u2u3(_dmfc0)
293I_u3u1u2(_dmodu)
294I_u1u2u3(_dmtc0)
295I_u1u2(_dmultu)
296I_u3u1u2(_dmulu)
297I_u2u1s3(_daddiu)
298I_u3u1u2(_daddu)
299I_u1(_di);
300I_u1u2(_divu)
301I_u3u1u2(_divu_r6)
302I_u2u1(_dsbh);
303I_u2u1(_dshd);
304I_u2u1u3(_dsll)
305I_u2u1u3(_dsll32)
306I_u3u2u1(_dsllv)
307I_u2u1u3(_dsra)
308I_u2u1u3(_dsra32)
309I_u3u2u1(_dsrav)
310I_u2u1u3(_dsrl)
311I_u2u1u3(_dsrl32)
312I_u3u2u1(_dsrlv)
313I_u2u1u3(_drotr)
314I_u2u1u3(_drotr32)
315I_u3u1u2(_dsubu)
316I_0(_eret)
317I_u2u1msbdu3(_ext)
318I_u2u1msbu3(_ins)
319I_u1(_j)
320I_u1(_jal)
321I_u2u1(_jalr)
322I_u1(_jr)
323I_u2s3u1(_lb)
324I_u2s3u1(_lbu)
325I_u2s3u1(_ld)
326I_u2s3u1(_lh)
327I_u2s3u1(_lhu)
328I_u2s3u1(_ll)
329I_u2s3u1(_lld)
330I_u1s2(_lui)
331I_u2s3u1(_lw)
332I_u2s3u1(_lwu)
333I_u1u2u3(_mfc0)
334I_u1u2u3(_mfhc0)
335I_u3u1u2(_modu)
336I_u3u1u2(_movn)
337I_u3u1u2(_movz)
338I_u1(_mfhi)
339I_u1(_mflo)
340I_u1u2u3(_mtc0)
341I_u1u2u3(_mthc0)
342I_u1(_mthi)
343I_u1(_mtlo)
344I_u3u1u2(_mul)
345I_u1u2(_multu)
346I_u3u1u2(_mulu)
347I_u3u1u2(_nor)
348I_u3u1u2(_or)
349I_u2u1u3(_ori)
350I_0(_rfe)
351I_u2s3u1(_sb)
352I_u2s3u1(_sc)
353I_u2s3u1(_scd)
354I_u2s3u1(_sd)
355I_u3u1u2(_seleqz)
356I_u3u1u2(_selnez)
357I_u2s3u1(_sh)
358I_u2u1u3(_sll)
359I_u3u2u1(_sllv)
360I_s3s1s2(_slt)
361I_u2u1s3(_slti)
362I_u2u1s3(_sltiu)
363I_u3u1u2(_sltu)
364I_u2u1u3(_sra)
365I_u3u2u1(_srav)
366I_u2u1u3(_srl)
367I_u3u2u1(_srlv)
368I_u2u1u3(_rotr)
369I_u3u1u2(_subu)
370I_u2s3u1(_sw)
371I_u1(_sync)
372I_0(_tlbp)
373I_0(_tlbr)
374I_0(_tlbwi)
375I_0(_tlbwr)
376I_u1(_wait);
377I_u2u1(_wsbh)
378I_u3u1u2(_xor)
379I_u2u1u3(_xori)
380I_u2u1(_yield)
381I_u2u1msbu3(_dins);
382I_u2u1msb32u3(_dinsm);
383I_u2u1msb32msb3(_dinsu);
384I_u1(_syscall);
385I_u1u2s3(_bbit0);
386I_u1u2s3(_bbit1);
387I_u3u1u2(_lwx)
388I_u3u1u2(_ldx)
389I_u1u2(_ldpte)
390I_u2u1u3(_lddir)
391
392#ifdef CONFIG_CPU_CAVIUM_OCTEON
393#include <asm/octeon/octeon.h>
394void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
395 unsigned int c)
396{
397 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
398 /*
399 * As per erratum Core-14449, replace prefetches 0-4,
400 * 6-24 with 'pref 28'.
401 */
402 build_insn(buf, insn_pref, c, 28, b);
403 else
404 build_insn(buf, insn_pref, c, a, b);
405}
406UASM_EXPORT_SYMBOL(uasm_i_pref);
407#else
408I_u2s3u1(_pref)
409#endif
410
411/* Handle labels. */
412void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
413{
414 (*lab)->addr = addr;
415 (*lab)->lab = lid;
416 (*lab)++;
417}
418UASM_EXPORT_SYMBOL(uasm_build_label);
419
420int uasm_in_compat_space_p(long addr)
421{
422 /* Is this address in 32bit compat space? */
423 return addr == (int)addr;
424}
425UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
426
427static int uasm_rel_highest(long val)
428{
429#ifdef CONFIG_64BIT
430 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
431#else
432 return 0;
433#endif
434}
435
436static int uasm_rel_higher(long val)
437{
438#ifdef CONFIG_64BIT
439 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
440#else
441 return 0;
442#endif
443}
444
445int uasm_rel_hi(long val)
446{
447 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
448}
449UASM_EXPORT_SYMBOL(uasm_rel_hi);
450
451int uasm_rel_lo(long val)
452{
453 return ((val & 0xffff) ^ 0x8000) - 0x8000;
454}
455UASM_EXPORT_SYMBOL(uasm_rel_lo);
456
457void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
458{
459 if (!uasm_in_compat_space_p(addr)) {
460 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
461 if (uasm_rel_higher(addr))
462 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
463 if (uasm_rel_hi(addr)) {
464 uasm_i_dsll(buf, rs, rs, 16);
465 uasm_i_daddiu(buf, rs, rs,
466 uasm_rel_hi(addr));
467 uasm_i_dsll(buf, rs, rs, 16);
468 } else
469 uasm_i_dsll32(buf, rs, rs, 0);
470 } else
471 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
472}
473UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
474
475void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
476{
477 UASM_i_LA_mostly(buf, rs, addr);
478 if (uasm_rel_lo(addr)) {
479 if (!uasm_in_compat_space_p(addr))
480 uasm_i_daddiu(buf, rs, rs,
481 uasm_rel_lo(addr));
482 else
483 uasm_i_addiu(buf, rs, rs,
484 uasm_rel_lo(addr));
485 }
486}
487UASM_EXPORT_SYMBOL(UASM_i_LA);
488
489/* Handle relocations. */
490void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
491{
492 (*rel)->addr = addr;
493 (*rel)->type = R_MIPS_PC16;
494 (*rel)->lab = lid;
495 (*rel)++;
496}
497UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
498
499static inline void __resolve_relocs(struct uasm_reloc *rel,
500 struct uasm_label *lab);
501
502void uasm_resolve_relocs(struct uasm_reloc *rel,
503 struct uasm_label *lab)
504{
505 struct uasm_label *l;
506
507 for (; rel->lab != UASM_LABEL_INVALID; rel++)
508 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
509 if (rel->lab == l->lab)
510 __resolve_relocs(rel, l);
511}
512UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
513
514void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
515 long off)
516{
517 for (; rel->lab != UASM_LABEL_INVALID; rel++)
518 if (rel->addr >= first && rel->addr < end)
519 rel->addr += off;
520}
521UASM_EXPORT_SYMBOL(uasm_move_relocs);
522
523void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
524 long off)
525{
526 for (; lab->lab != UASM_LABEL_INVALID; lab++)
527 if (lab->addr >= first && lab->addr < end)
528 lab->addr += off;
529}
530UASM_EXPORT_SYMBOL(uasm_move_labels);
531
532void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
533 u32 *first, u32 *end, u32 *target)
534{
535 long off = (long)(target - first);
536
537 memcpy(target, first, (end - first) * sizeof(u32));
538
539 uasm_move_relocs(rel, first, end, off);
540 uasm_move_labels(lab, first, end, off);
541}
542UASM_EXPORT_SYMBOL(uasm_copy_handler);
543
544int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
545{
546 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
547 if (rel->addr == addr
548 && (rel->type == R_MIPS_PC16
549 || rel->type == R_MIPS_26))
550 return 1;
551 }
552
553 return 0;
554}
555UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
556
557/* Convenience functions for labeled branches. */
558void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
559 int lid)
560{
561 uasm_r_mips_pc16(r, *p, lid);
562 uasm_i_bltz(p, reg, 0);
563}
564UASM_EXPORT_SYMBOL(uasm_il_bltz);
565
566void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
567{
568 uasm_r_mips_pc16(r, *p, lid);
569 uasm_i_b(p, 0);
570}
571UASM_EXPORT_SYMBOL(uasm_il_b);
572
573void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
574 unsigned int r2, int lid)
575{
576 uasm_r_mips_pc16(r, *p, lid);
577 uasm_i_beq(p, r1, r2, 0);
578}
579UASM_EXPORT_SYMBOL(uasm_il_beq);
580
581void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
582 int lid)
583{
584 uasm_r_mips_pc16(r, *p, lid);
585 uasm_i_beqz(p, reg, 0);
586}
587UASM_EXPORT_SYMBOL(uasm_il_beqz);
588
589void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
590 int lid)
591{
592 uasm_r_mips_pc16(r, *p, lid);
593 uasm_i_beqzl(p, reg, 0);
594}
595UASM_EXPORT_SYMBOL(uasm_il_beqzl);
596
597void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
598 unsigned int reg2, int lid)
599{
600 uasm_r_mips_pc16(r, *p, lid);
601 uasm_i_bne(p, reg1, reg2, 0);
602}
603UASM_EXPORT_SYMBOL(uasm_il_bne);
604
605void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
606 int lid)
607{
608 uasm_r_mips_pc16(r, *p, lid);
609 uasm_i_bnez(p, reg, 0);
610}
611UASM_EXPORT_SYMBOL(uasm_il_bnez);
612
613void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
614 int lid)
615{
616 uasm_r_mips_pc16(r, *p, lid);
617 uasm_i_bgezl(p, reg, 0);
618}
619UASM_EXPORT_SYMBOL(uasm_il_bgezl);
620
621void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
622 int lid)
623{
624 uasm_r_mips_pc16(r, *p, lid);
625 uasm_i_bgez(p, reg, 0);
626}
627UASM_EXPORT_SYMBOL(uasm_il_bgez);
628
629void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
630 unsigned int bit, int lid)
631{
632 uasm_r_mips_pc16(r, *p, lid);
633 uasm_i_bbit0(p, reg, bit, 0);
634}
635UASM_EXPORT_SYMBOL(uasm_il_bbit0);
636
637void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
638 unsigned int bit, int lid)
639{
640 uasm_r_mips_pc16(r, *p, lid);
641 uasm_i_bbit1(p, reg, bit, 0);
642}
643UASM_EXPORT_SYMBOL(uasm_il_bbit1);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-04-17 07:49:59 +0800