Initial commit: OpenHarmony-v4.0-ReleaseOpenHarmony-v4.0-Release

140 files changed, 20661 insertions, 0 deletions

diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
new file mode 100644
index 000000000..2adc8581a
--- /dev/null
+++ b/arch/mips/boot/.gitignore
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+mkboot
+elf2ecoff
+vmlinux.*
+zImage
+zImage.tmp
+calc_vmlinuz_load_addr
+uImage
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
new file mode 100644
index 000000000..a3da2c5d6
--- /dev/null
+++ b/arch/mips/boot/Makefile
@@ -0,0 +1,173 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995, 1998, 2001, 2002 by Ralf Baechle
+# Copyright (C) 2004  Maciej W. Rozycki
+#
+
+#
+# Some DECstations need all possible sections of an ECOFF executable
+#
+ifdef CONFIG_MACH_DECSTATION
+  e2eflag := -a
+endif
+
+#
+# Drop some uninteresting sections in the kernel.
+# This is only relevant for ELF kernels but doesn't hurt a.out
+#
+drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags   := $(addprefix --remove-section=,$(drop-sections))
+
+hostprogs := elf2ecoff
+
+suffix-y                        := bin
+suffix-$(CONFIG_KERNEL_BZIP2)   := bz2
+suffix-$(CONFIG_KERNEL_GZIP)    := gz
+suffix-$(CONFIG_KERNEL_LZMA)    := lzma
+suffix-$(CONFIG_KERNEL_LZO)     := lzo
+
+targets := vmlinux.ecoff
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
+$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
+        $(call if_changed,ecoff)
+
+targets += vmlinux.bin
+quiet_cmd_bin = OBJCOPY $@
+      cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.bin: $(VMLINUX) FORCE
+        $(call if_changed,bin)
+
+targets += vmlinux.srec
+quiet_cmd_srec = OBJCOPY $@
+      cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.srec: $(VMLINUX) FORCE
+        $(call if_changed,srec)
+
+UIMAGE_LOADADDR  = $(VMLINUX_LOAD_ADDRESS)
+UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
+
+#
+# Compressed vmlinux images
+#
+
+extra-y += vmlinux.bin.bz2
+extra-y += vmlinux.bin.gz
+extra-y += vmlinux.bin.lzma
+extra-y += vmlinux.bin.lzo
+
+$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,bzip2)
+
+$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,gzip)
+
+$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,lzma)
+
+$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,lzo)
+
+#
+# Compressed u-boot images
+#
+
+targets += uImage
+targets += uImage.bin
+targets += uImage.bz2
+targets += uImage.gz
+targets += uImage.lzma
+targets += uImage.lzo
+
+$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,uimage,none)
+
+$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 FORCE
+        $(call if_changed,uimage,bzip2)
+
+$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
+        $(call if_changed,uimage,gzip)
+
+$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
+        $(call if_changed,uimage,lzma)
+
+$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
+        $(call if_changed,uimage,lzo)
+
+$(obj)/uImage: $(obj)/uImage.$(suffix-y)
+        @ln -sf $(notdir $<) $@
+        @echo '  Image $@ is ready'
+
+#
+# Flattened Image Tree (.itb) images
+#
+
+ifeq ($(ADDR_BITS),32)
+itb_addr_cells = 1
+endif
+ifeq ($(ADDR_BITS),64)
+itb_addr_cells = 2
+endif
+
+targets += vmlinux.its.S
+
+quiet_cmd_its_cat = CAT     $@
+      cmd_its_cat = cat $(real-prereqs) >$@
+
+$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) FORCE
+        $(call if_changed,its_cat)
+
+targets += vmlinux.its
+targets += vmlinux.gz.its
+targets += vmlinux.bz2.its
+targets += vmlinux.lzma.its
+targets += vmlinux.lzo.its
+
+quiet_cmd_cpp_its_S = ITS     $@
+      cmd_cpp_its_S = $(CPP) -P -C -o $@ $< \
+                        -DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
+                        -DVMLINUX_BINARY="\"$(3)\"" \
+                        -DVMLINUX_COMPRESSION="\"$(2)\"" \
+                        -DVMLINUX_LOAD_ADDRESS=$(VMLINUX_LOAD_ADDRESS) \
+                        -DVMLINUX_ENTRY_ADDRESS=$(VMLINUX_ENTRY_ADDRESS) \
+                        -DADDR_BITS=$(ADDR_BITS) \
+                        -DADDR_CELLS=$(itb_addr_cells)
+
+$(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
+        $(call if_changed,cpp_its_S,none,vmlinux.bin)
+
+$(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
+        $(call if_changed,cpp_its_S,gzip,vmlinux.bin.gz)
+
+$(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX)  FORCE
+        $(call if_changed,cpp_its_S,bzip2,vmlinux.bin.bz2)
+
+$(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
+        $(call if_changed,cpp_its_S,lzma,vmlinux.bin.lzma)
+
+$(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
+        $(call if_changed,cpp_its_S,lzo,vmlinux.bin.lzo)
+
+targets += vmlinux.itb
+targets += vmlinux.gz.itb
+targets += vmlinux.bz2.itb
+targets += vmlinux.lzma.itb
+targets += vmlinux.lzo.itb
+
+quiet_cmd_itb-image = ITB     $@
+      cmd_itb-image = \
+                env PATH="$(objtree)/scripts/dtc:$(PATH)" \
+                $(BASH) $(MKIMAGE) \
+                -D "-I dts -O dtb -p 500 \
+                        --include $(objtree)/arch/mips \
+                        --warning no-unit_address_vs_reg" \
+                -f $(2) $@
+
+$(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE
+        $(call if_changed,itb-image,$<)
+
+$(obj)/vmlinux.%.itb: $(obj)/vmlinux.%.its $(obj)/vmlinux.bin.% FORCE
+        $(call if_changed,itb-image,$<)
diff --git a/arch/mips/boot/compressed/.gitignore b/arch/mips/boot/compressed/.gitignore
new file mode 100644
index 000000000..d35839561
--- /dev/null
+++ b/arch/mips/boot/compressed/.gitignore
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+ashldi3.c
+bswapsi.c
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
new file mode 100644
index 000000000..eae0fad30
--- /dev/null
+++ b/arch/mips/boot/compressed/Makefile
@@ -0,0 +1,155 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.
+#
+# Adapted for MIPS Pete Popov, Dan Malek
+#
+# Copyright (C) 1994 by Linus Torvalds
+# Adapted for PowerPC by Gary Thomas
+# modified by Cort (cort@cs.nmt.edu)
+#
+# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
+# Author: Wu Zhangjin <wuzhangjin@gmail.com>
+#
+
+include $(srctree)/arch/mips/Kbuild.platforms
+
+# set the default size of the mallocing area for decompressing
+BOOT_HEAP_SIZE := 0x400000
+
+# Disable Function Tracer
+KBUILD_CFLAGS := $(filter-out -pg, $(KBUILD_CFLAGS))
+
+KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
+
+# Disable lq/sq in zboot
+ifdef CONFIG_CPU_LOONGSON64
+KBUILD_CFLAGS := $(filter-out -march=loongson3a, $(KBUILD_CFLAGS)) -march=mips64r2
+endif
+
+KBUILD_CFLAGS := $(KBUILD_CFLAGS) -D__KERNEL__ -D__DISABLE_EXPORTS \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
+
+KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
+        -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
+
+# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in.
+KCOV_INSTRUMENT         := n
+UBSAN_SANITIZE := n
+
+# decompressor objects (linked with vmlinuz)
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/bswapsi.o
+
+ifdef CONFIG_DEBUG_ZBOOT
+vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT)                  += $(obj)/dbg.o
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o
+vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY)                 += $(obj)/uart-alchemy.o
+vmlinuzobjs-$(CONFIG_ATH79)                        += $(obj)/uart-ath79.o
+endif
+
+extra-y += uart-ath79.c
+$(obj)/uart-ath79.c: $(srctree)/arch/mips/ath79/early_printk.c
+        $(call cmd,shipped)
+
+vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o
+
+extra-y += ashldi3.c
+$(obj)/ashldi3.c: $(obj)/%.c: $(srctree)/lib/%.c FORCE
+        $(call if_changed,shipped)
+
+extra-y += bswapsi.c
+$(obj)/bswapsi.c: $(obj)/%.c: $(srctree)/arch/mips/lib/%.c FORCE
+        $(call if_changed,shipped)
+
+targets := $(notdir $(vmlinuzobjs-y))
+
+targets += vmlinux.bin
+OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
+        $(call if_changed,objcopy)
+
+tool_$(CONFIG_KERNEL_GZIP)    = gzip
+tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
+tool_$(CONFIG_KERNEL_LZ4)     = lz4
+tool_$(CONFIG_KERNEL_LZMA)    = lzma
+tool_$(CONFIG_KERNEL_LZO)     = lzo
+tool_$(CONFIG_KERNEL_XZ)      = xzkern
+tool_$(CONFIG_KERNEL_ZSTD)    = zstd22
+
+targets += vmlinux.bin.z
+$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,$(tool_y))
+
+targets += piggy.o dummy.o
+OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
+                        --set-section-flags=.image=contents,alloc,load,readonly,data
+$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
+        $(call if_changed,objcopy)
+
+HOSTCFLAGS_calc_vmlinuz_load_addr.o += $(LINUXINCLUDE)
+
+# Calculate the load address of the compressed kernel image
+hostprogs := calc_vmlinuz_load_addr
+
+ifneq ($(zload-y),)
+VMLINUZ_LOAD_ADDRESS := $(zload-y)
+else
+VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
+                $(obj)/vmlinux.bin $(LINKER_LOAD_ADDRESS))
+endif
+UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS)
+
+vmlinuzobjs-y += $(obj)/piggy.o
+
+quiet_cmd_zld = LD      $@
+      cmd_zld = $(LD) $(KBUILD_LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -s $@
+vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
+        $(call cmd,zld)
+        $(call cmd,strip)
+
+#
+# Some DECstations need all possible sections of an ECOFF executable
+#
+ifdef CONFIG_MACH_DECSTATION
+  e2eflag := -a
+endif
+
+# elf2ecoff can only handle 32bit image
+hostprogs += ../elf2ecoff
+
+ifdef CONFIG_32BIT
+        VMLINUZ = vmlinuz
+else
+        VMLINUZ = vmlinuz.32
+endif
+
+quiet_cmd_32 = OBJCOPY $@
+      cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+vmlinuz.32: vmlinuz
+        $(call cmd,32)
+
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
+vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
+        $(call cmd,ecoff)
+
+OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
+vmlinuz.bin: vmlinuz
+        $(call cmd,objcopy)
+
+OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
+vmlinuz.srec: vmlinuz
+        $(call cmd,objcopy)
+
+uzImage.bin: vmlinuz.bin FORCE
+        $(call if_changed,uimage,none)
+
+clean-files += $(objtree)/vmlinuz
+clean-files += $(objtree)/vmlinuz.32
+clean-files += $(objtree)/vmlinuz.ecoff
+clean-files += $(objtree)/vmlinuz.bin
+clean-files += $(objtree)/vmlinuz.srec
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
new file mode 100644
index 000000000..080b926d2
--- /dev/null
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <linux/sizes.h>
+
+int main(int argc, char *argv[])
+{
+        unsigned long long vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
+        struct stat sb;
+
+        if (argc != 3) {
+                fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
+                                argv[0]);
+                return EXIT_FAILURE;
+        }
+
+        if (stat(argv[1], &sb) == -1) {
+                perror("stat");
+                return EXIT_FAILURE;
+        }
+
+        /* Convert hex characters to dec number */
+        errno = 0;
+        if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
+                if (errno != 0)
+                        perror("sscanf");
+                else
+                        fprintf(stderr, "No matching characters\n");
+
+                return EXIT_FAILURE;
+        }
+
+        vmlinux_size = (uint64_t)sb.st_size;
+        vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
+
+        /*
+         * Align with 64KB: KEXEC needs load sections to be aligned to PAGE_SIZE,
+         * which may be as large as 64KB depending on the kernel configuration.
+         */
+
+        vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K);
+
+        printf("0x%llx\n", vmlinuz_load_addr);
+
+        return EXIT_SUCCESS;
+}
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
new file mode 100644
index 000000000..f6728a8fd
--- /dev/null
+++ b/arch/mips/boot/compressed/dbg.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MIPS-specific debug support for pre-boot environment
+ *
+ * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
+ * need to implement your own putc().
+ */
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+void __weak putc(char c)
+{
+}
+
+void puts(const char *s)
+{
+        char c;
+        while ((c = *s++) != '\0') {
+                putc(c);
+                if (c == '\n')
+                        putc('\r');
+        }
+}
+
+void puthex(unsigned long long val)
+{
+
+        unsigned char buf[10];
+        int i;
+        for (i = 7; i >= 0; i--) {
+                buf[i] = "0123456789ABCDEF"[val & 0x0F];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        puts(buf);
+}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
new file mode 100644
index 000000000..1e91155be
--- /dev/null
+++ b/arch/mips/boot/compressed/decompress.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+
+#define DISABLE_BRANCH_PROFILING
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/libfdt.h>
+
+#include <asm/addrspace.h>
+#include <asm/unaligned.h>
+
+/*
+ * These two variables specify the free mem region
+ * that can be used for temporary malloc area
+ */
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+
+/* The linker tells us where the image is. */
+extern unsigned char __image_begin, __image_end;
+
+/* debug interfaces  */
+#ifdef CONFIG_DEBUG_ZBOOT
+extern void puts(const char *s);
+extern void puthex(unsigned long long val);
+#else
+#define puts(s) do {} while (0)
+#define puthex(val) do {} while (0)
+#endif
+
+extern char __appended_dtb[];
+
+void error(char *x)
+{
+        puts("\n\n");
+        puts(x);
+        puts("\n\n -- System halted");
+
+        while (1)
+                ;       /* Halt */
+}
+
+/* activate the code for pre-boot environment */
+#define STATIC static
+
+#ifdef CONFIG_KERNEL_GZIP
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_BZIP2
+#include "../../../../lib/decompress_bunzip2.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZ4
+#include "../../../../lib/decompress_unlz4.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZMA
+#include "../../../../lib/decompress_unlzma.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZO
+#include "../../../../lib/decompress_unlzo.c"
+#endif
+
+#ifdef CONFIG_KERNEL_XZ
+#include "../../../../lib/decompress_unxz.c"
+#endif
+
+#ifdef CONFIG_KERNEL_ZSTD
+#include "../../../../lib/decompress_unzstd.c"
+#endif
+
+const unsigned long __stack_chk_guard = 0x000a0dff;
+
+void __stack_chk_fail(void)
+{
+        error("stack-protector: Kernel stack is corrupted\n");
+}
+
+void decompress_kernel(unsigned long boot_heap_start)
+{
+        unsigned long zimage_start, zimage_size;
+
+        zimage_start = (unsigned long)(&__image_begin);
+        zimage_size = (unsigned long)(&__image_end) -
+            (unsigned long)(&__image_begin);
+
+        puts("zimage at:     ");
+        puthex(zimage_start);
+        puts(" ");
+        puthex(zimage_size + zimage_start);
+        puts("\n");
+
+        /* This area are prepared for mallocing when decompressing */
+        free_mem_ptr = boot_heap_start;
+        free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
+
+        /* Display standard Linux/MIPS boot prompt */
+        puts("Uncompressing Linux at load address ");
+        puthex(VMLINUX_LOAD_ADDRESS_ULL);
+        puts("\n");
+
+        /* Decompress the kernel with according algorithm */
+        __decompress((char *)zimage_start, zimage_size, 0, 0,
+                   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, 0, error);
+
+        if (IS_ENABLED(CONFIG_MIPS_RAW_APPENDED_DTB) &&
+            fdt_magic((void *)&__appended_dtb) == FDT_MAGIC) {
+                unsigned int image_size, dtb_size;
+
+                dtb_size = fdt_totalsize((void *)&__appended_dtb);
+
+                /* last four bytes is always image size in little endian */
+                image_size = get_unaligned_le32((void *)&__image_end - 4);
+
+                /* copy dtb to where the booted kernel will expect it */
+                memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,
+                       __appended_dtb, dtb_size);
+        }
+
+        /* FIXME: should we flush cache here? */
+        puts("Now, booting the kernel...\n");
+}
diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c
new file mode 100644
index 000000000..31dbf45bf
--- /dev/null
+++ b/arch/mips/boot/compressed/dummy.c
@@ -0,0 +1,4 @@
+int main(void)
+{
+        return 0;
+}
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
new file mode 100644
index 000000000..409cb483a
--- /dev/null
+++ b/arch/mips/boot/compressed/head.S
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf Electronics
+ * Written by Ralf Baechle and Andreas Busse
+ * Copyright (C) 1995 - 1999 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Modified for DECStation and hence R3000 support by Paul M. Antoine
+ * Further modifications by David S. Miller and Harald Koerfgen
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+        .set noreorder
+        .cprestore
+        LEAF(start)
+start:
+        /* Save boot rom start args */
+        move    s0, a0
+        move    s1, a1
+        move    s2, a2
+        move    s3, a3
+
+        /* Clear BSS */
+        PTR_LA  a0, _edata
+        PTR_LA  a2, _end
+1:      sw      zero, 0(a0)
+        bne     a2, a0, 1b
+         addiu  a0, a0, 4
+
+        PTR_LA  a0, (.heap)          /* heap address */
+        PTR_LA  sp, (.stack + 8192)  /* stack address */
+
+        PTR_LA  ra, 2f
+        PTR_LA  k0, decompress_kernel
+        jr      k0
+         nop
+2:
+        move    a0, s0
+        move    a1, s1
+        move    a2, s2
+        move    a3, s3
+        PTR_LI  k0, KERNEL_ENTRY
+        jr      k0
+         nop
+3:
+        b       3b
+         nop
+        END(start)
+
+        .comm .heap,BOOT_HEAP_SIZE,4
+        .comm .stack,4096*2,4
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
new file mode 100644
index 000000000..2ed08fbef
--- /dev/null
+++ b/arch/mips/boot/compressed/ld.script
@@ -0,0 +1,57 @@
+/*
+ * ld.script for compressed kernel support of MIPS
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin <wuzhanjing@gmail.com>
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
+ */
+
+OUTPUT_ARCH(mips)
+ENTRY(start)
+PHDRS {
+        text PT_LOAD FLAGS(7); /* RWX */
+}
+SECTIONS
+{
+        /* Text and read-only data */
+        /* . = VMLINUZ_LOAD_ADDRESS; */
+        .text : {
+                *(.text)
+                *(.rodata)
+        }: text
+        /* End of text section */
+
+        /* Writable data */
+        .data : {
+                *(.data)
+                /* Put the compressed image here */
+                __image_begin = .;
+                *(.image)
+                __image_end = .;
+                CONSTRUCTORS
+                . = ALIGN(16);
+        }
+        __appended_dtb = .;
+        /* leave space for appended DTB */
+        . += 0x100000;
+
+        _edata = .;
+        /* End of data section */
+
+        /* BSS */
+        .bss : {
+                *(.bss)
+        }
+        . = ALIGN(16);
+        _end = .;
+
+        /* Sections to be discarded */
+        /DISCARD/ : {
+                *(.MIPS.options)
+                *(.options)
+                *(.pdr)
+                *(.reginfo)
+                *(.comment)
+                *(.note)
+        }
+}
diff --git a/arch/mips/boot/compressed/string.c b/arch/mips/boot/compressed/string.c
new file mode 100644
index 000000000..0b593b709
--- /dev/null
+++ b/arch/mips/boot/compressed/string.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * arch/mips/boot/compressed/string.c
+ *
+ * Very small subset of simple string routines
+ */
+
+#include <linux/compiler_attributes.h>
+#include <linux/types.h>
+
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        int i;
+        const char *s = src;
+        char *d = dest;
+
+        for (i = 0; i < n; i++)
+                d[i] = s[i];
+        return dest;
+}
+
+void *memset(void *s, int c, size_t n)
+{
+        int i;
+        char *ss = s;
+
+        for (i = 0; i < n; i++)
+                ss[i] = c;
+        return s;
+}
+
+void * __weak memmove(void *dest, const void *src, size_t n)
+{
+        unsigned int i;
+        const char *s = src;
+        char *d = dest;
+
+        if ((uintptr_t)dest < (uintptr_t)src) {
+                for (i = 0; i < n; i++)
+                        d[i] = s[i];
+        } else {
+                for (i = n; i > 0; i--)
+                        d[i - 1] = s[i - 1];
+        }
+        return dest;
+}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
new file mode 100644
index 000000000..aee8d7b8f
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * 16550 compatible uart based serial debug support for zboot
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/addrspace.h>
+
+#if defined(CONFIG_MACH_LOONGSON64) || defined(CONFIG_MIPS_MALTA)
+#define UART_BASE 0x1fd003f8
+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
+#endif
+
+#ifdef CONFIG_AR7
+#include <ar7.h>
+#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
+#endif
+
+#ifdef CONFIG_MACH_INGENIC
+#define INGENIC_UART0_BASE_ADDR 0x10030000
+#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset))
+#endif
+
+#ifdef CONFIG_CPU_XLR
+#define UART0_BASE  0x1EF14000
+#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
+#define IOTYPE unsigned int
+#endif
+
+#ifdef CONFIG_CPU_XLP
+#define UART0_BASE  0x18030100
+#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
+#define IOTYPE unsigned int
+#endif
+
+#ifndef IOTYPE
+#define IOTYPE char
+#endif
+
+#ifndef PORT
+#error please define the serial port address for your own machine
+#endif
+
+static inline unsigned int serial_in(int offset)
+{
+        return *((volatile IOTYPE *)PORT(offset)) & 0xFF;
+}
+
+static inline void serial_out(int offset, int value)
+{
+        *((volatile IOTYPE *)PORT(offset)) = value & 0xFF;
+}
+
+void putc(char c)
+{
+        int timeout = 1000000;
+
+        while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
+                ;
+
+        serial_out(UART_TX, c);
+}
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
new file mode 100644
index 000000000..8ec63011e
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <asm/mach-au1x00/au1000.h>
+
+void putc(char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/boot/compressed/uart-prom.c b/arch/mips/boot/compressed/uart-prom.c
new file mode 100644
index 000000000..a8a0a32e0
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-prom.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <asm/setup.h>
+
+void putc(char c)
+{
+        prom_putchar(c);
+}
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
new file mode 100644
index 000000000..19027129a
--- /dev/null
+++ b/arch/mips/boot/dts/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-$(CONFIG_BMIPS_GENERIC)          += brcm
+subdir-$(CONFIG_CAVIUM_OCTEON_SOC)      += cavium-octeon
+subdir-$(CONFIG_MACH_PISTACHIO)         += img
+subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON)   += img
+subdir-$(CONFIG_MACH_INGENIC)           += ingenic
+subdir-$(CONFIG_LANTIQ)                 += lantiq
+subdir-$(CONFIG_MACH_LOONGSON64)        += loongson
+subdir-$(CONFIG_MSCC_OCELOT)            += mscc
+subdir-$(CONFIG_MIPS_MALTA)             += mti
+subdir-$(CONFIG_LEGACY_BOARD_SEAD3)     += mti
+subdir-$(CONFIG_NLM_XLP_BOARD)          += netlogic
+subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
+subdir-$(CONFIG_MACH_PIC32)             += pic32
+subdir-$(CONFIG_ATH79)                  += qca
+subdir-$(CONFIG_RALINK)                 += ralink
+subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)  += xilfpga
+
+obj-$(CONFIG_BUILTIN_DTB)       := $(addsuffix /, $(subdir-y))
diff --git a/arch/mips/boot/dts/brcm/Makefile b/arch/mips/boot/dts/brcm/Makefile
new file mode 100644
index 000000000..d85f446cc
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DT_BCM93384WVG)            += bcm93384wvg.dtb
+dtb-$(CONFIG_DT_BCM93384WVG_VIPER)      += bcm93384wvg_viper.dtb
+dtb-$(CONFIG_DT_BCM96368MVWG)           += bcm96368mvwg.dtb
+dtb-$(CONFIG_DT_BCM9EJTAGPRB)           += bcm9ejtagprb.dtb
+dtb-$(CONFIG_DT_BCM97125CBMB)           += bcm97125cbmb.dtb
+dtb-$(CONFIG_DT_BCM97346DBSMB)          += bcm97346dbsmb.dtb
+dtb-$(CONFIG_DT_BCM97358SVMB)           += bcm97358svmb.dtb
+dtb-$(CONFIG_DT_BCM97360SVMB)           += bcm97360svmb.dtb
+dtb-$(CONFIG_DT_BCM97362SVMB)           += bcm97362svmb.dtb
+dtb-$(CONFIG_DT_BCM97420C)              += bcm97420c.dtb
+dtb-$(CONFIG_DT_BCM97425SVMB)           += bcm97425svmb.dtb
+dtb-$(CONFIG_DT_BCM97435SVMB)           += bcm97435svmb.dtb
+dtb-$(CONFIG_DT_COMTREND_VR3032U)       += bcm63268-comtrend-vr-3032u.dtb
+dtb-$(CONFIG_DT_NETGEAR_CVG834G)        += bcm3368-netgear-cvg834g.dtb
+dtb-$(CONFIG_DT_SFR_NEUFBOX4_SERCOMM)   += bcm6358-neufbox4-sercomm.dtb
+dtb-$(CONFIG_DT_SFR_NEUFBOX6_SERCOMM)   += bcm6362-neufbox6-sercomm.dtb
+
+dtb-$(CONFIG_DT_NONE) += \
+        bcm3368-netgear-cvg834g.dtb \
+        bcm6358-neufbox4-sercomm.dtb \
+        bcm6362-neufbox6-sercomm.dtb \
+        bcm63268-comtrend-vr-3032u.dtb \
+        bcm93384wvg.dtb \
+        bcm93384wvg_viper.dtb \
+        bcm96368mvwg.dtb \
+        bcm9ejtagprb.dtb \
+        bcm97125cbmb.dtb \
+        bcm97346dbsmb.dtb \
+        bcm97358svmb.dtb \
+        bcm97360svmb.dtb \
+        bcm97362svmb.dtb \
+        bcm97420c.dtb \
+        bcm97425svmb.dtb \
+        bcm97435svmb.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts b/arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts
new file mode 100644
index 000000000..ed6023a91
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm3368.dtsi"
+
+/ {
+        compatible = "netgear,cvg834g", "brcm,bcm3368";
+        model = "NETGEAR CVG834G";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x02000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm3368.dtsi b/arch/mips/boot/dts/brcm/bcm3368.dtsi
new file mode 100644
index 000000000..d4b2b430d
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3368.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm3368";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <150000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@fff8c004 {
+                        compatible = "brcm,bcm3368-clocks";
+                        reg = <0xfff8c004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_cntl: syscon@fff8c008 {
+                        compatible = "syscon";
+                        reg = <0xfff8c008 0x4>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@fff8c008 {
+                        compatible = "syscon-reboot";
+                        regmap = <&periph_cntl>;
+                        offset = <0x0>;
+                        mask = <0x1>;
+                };
+
+                periph_intc: interrupt-controller@fff8c00c {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0xfff8c00c 0x8>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>;
+                };
+
+                uart0: serial@fff8c100 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0xfff8c100 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <2>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                uart1: serial@fff8c120 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0xfff8c120 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <3>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi b/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
new file mode 100644
index 000000000..eb2a9c6ed
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
+
+        memory@0 {
+                device_type = "memory";
+
+                /* Typical ranges.  The bootloader should fill these in. */
+                reg = <0x06000000 0x02000000>,
+                      <0x0e000000 0x02000000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* 1/2 of the CPU core clock (standard MIPS behavior) */
+                mips-hpt-frequency = <300000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+        };
+
+        cpu_intc: cpu_intc {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                periph_clk: periph_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <54000000>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "brcm,ubus", "simple-bus";
+                ranges;
+                /* No dma-ranges on Viper. */
+
+                periph_intc: periph_intc@14e00048 {
+                        compatible = "brcm,bcm3380-l2-intc";
+                        reg = <0x14e00048 0x4 0x14e0004c 0x4>,
+                              <0x14e00350 0x4 0x14e00354 0x4>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <4>;
+                };
+
+                cmips_intc: cmips_intc@151f8048 {
+                        compatible = "brcm,bcm3380-l2-intc";
+                        reg = <0x151f8048 0x4 0x151f804c 0x4>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <30>;
+                        brcm,int-map-mask = <0xffffffff>;
+                };
+
+                uart0: serial@14e00520 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x14e00520 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <2>;
+                        clocks = <&periph_clk>;
+                        status = "disabled";
+                };
+
+                ehci0: usb@15400300 {
+                        compatible = "brcm,bcm3384-ehci", "generic-ehci";
+                        reg = <0x15400300 0x100>;
+                        big-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <41>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@15400400 {
+                        compatible = "brcm,bcm3384-ohci", "generic-ohci";
+                        reg = <0x15400400 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <40>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
new file mode 100644
index 000000000..d7ad769a4
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm3384", "brcm,bcm33843";
+
+        memory@0 {
+                device_type = "memory";
+
+                /* Typical range.  The bootloader should fill this in. */
+                reg = <0x0 0x08000000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* On BMIPS5000 this is 1/8th of the CPU core clock */
+                mips-hpt-frequency = <100000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        cpu_intc: cpu_intc {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                periph_clk: periph_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <54000000>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "brcm,ubus", "simple-bus";
+                ranges;
+                dma-ranges = <0x00000000 0x08000000 0x08000000>,
+                             <0x08000000 0x00000000 0x08000000>;
+
+                periph_intc: periph_intc@14e00038 {
+                        compatible = "brcm,bcm3380-l2-intc";
+                        reg = <0x14e00038 0x4 0x14e0003c 0x4>,
+                              <0x14e00340 0x4 0x14e00344 0x4>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <4>;
+                };
+
+                zmips_intc: zmips_intc@104b0060 {
+                        compatible = "brcm,bcm3380-l2-intc";
+                        reg = <0x104b0060 0x4 0x104b0064 0x4>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <29>;
+                        brcm,int-map-mask = <0xffffffff>;
+                };
+
+                iop_intc: iop_intc@14e00058 {
+                        compatible = "brcm,bcm3380-l2-intc";
+                        reg = <0x14e00058 0x4 0x14e0005c 0x4>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <6>;
+                        brcm,int-map-mask = <0xffffffff>;
+                };
+
+                uart0: serial@14e00520 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x14e00520 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <2>;
+                        clocks = <&periph_clk>;
+                        status = "disabled";
+                };
+
+                ehci0: usb@15400300 {
+                        compatible = "brcm,bcm3384-ehci", "generic-ehci";
+                        reg = <0x15400300 0x100>;
+                        big-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <41>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@15400400 {
+                        compatible = "brcm,bcm3384-ohci", "generic-ohci";
+                        reg = <0x15400400 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <40>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts b/arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts
new file mode 100644
index 000000000..8d010b919
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm63268.dtsi"
+
+/ {
+        compatible = "comtrend,vr-3032u", "brcm,bcm63268";
+        model = "Comtrend VR-3032u";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x04000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&leds0 {
+        status = "okay";
+        brcm,serial-leds;
+        brcm,serial-dat-low;
+        brcm,serial-shift-inv;
+
+        led@0 {
+                reg = <0>;
+                brcm,hardware-controlled;
+                brcm,link-signal-sources = <0>;
+                /* GPHY0 Speed 0 */
+        };
+        led@1 {
+                reg = <1>;
+                brcm,hardware-controlled;
+                brcm,link-signal-sources = <1>;
+                /* GPHY0 Speed 1 */
+        };
+        led@2 {
+                reg = <2>;
+                active-low;
+                label = "vr-3032u:red:inet";
+        };
+        led@3 {
+                reg = <3>;
+                active-low;
+                label = "vr-3032u:green:dsl";
+        };
+        led@4 {
+                reg = <4>;
+                active-low;
+                label = "vr-3032u:green:usb";
+        };
+        led@7 {
+                reg = <7>;
+                active-low;
+                label = "vr-3032u:green:wps";
+        };
+        led@8 {
+                reg = <8>;
+                active-low;
+                label = "vr-3032u:green:inet";
+        };
+        led@9 {
+                reg = <9>;
+                brcm,hardware-controlled;
+                /* EPHY0 Activity */
+        };
+        led@10 {
+                reg = <10>;
+                brcm,hardware-controlled;
+                /* EPHY1 Activity */
+        };
+        led@11 {
+                reg = <11>;
+                brcm,hardware-controlled;
+                /* EPHY2 Activity */
+        };
+        led@12 {
+                reg = <12>;
+                brcm,hardware-controlled;
+                /* GPHY0 Activity */
+        };
+        led@13 {
+                reg = <13>;
+                brcm,hardware-controlled;
+                /* EPHY0 Speed */
+        };
+        led@14 {
+                reg = <14>;
+                brcm,hardware-controlled;
+                /* EPHY1 Speed */
+        };
+        led@15 {
+                reg = <15>;
+                brcm,hardware-controlled;
+                /* EPHY2 Speed */
+        };
+        led@20 {
+                reg = <20>;
+                active-low;
+                label = "vr-3032u:green:power";
+                default-state = "on";
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi
new file mode 100644
index 000000000..365fa75cd
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm63268";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <200000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@10000004 {
+                        compatible = "brcm,bcm63268-clocks";
+                        reg = <0x10000004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_cntl: syscon@10000008 {
+                        compatible = "syscon";
+                        reg = <0x10000008 0x4>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@10000008 {
+                        compatible = "syscon-reboot";
+                        regmap = <&periph_cntl>;
+                        offset = <0x0>;
+                        mask = <0x1>;
+                };
+
+                periph_intc: interrupt-controller@10000020 {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0x10000020 0x20>,
+                              <0x10000040 0x20>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                uart0: serial@10000180 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000180 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <5>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                uart1: serial@100001a0 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x100001a0 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <34>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                leds0: led-controller@10001900 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,bcm6328-leds";
+                        reg = <0x10001900 0x24>;
+
+                        status = "disabled";
+                };
+
+                periph_pwr: power-controller@1000184c {
+                        compatible = "brcm,bcm6328-power-controller";
+                        reg = <0x1000184c 0x4>;
+                        #power-domain-cells = <1>;
+                };
+
+                ehci: usb@10002500 {
+                        compatible = "brcm,bcm63268-ehci", "generic-ehci";
+                        reg = <0x10002500 0x100>;
+                        big-endian;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <10>;
+
+                        status = "disabled";
+                };
+
+                ohci: usb@10002600 {
+                        compatible = "brcm,bcm63268-ohci", "generic-ohci";
+                        reg = <0x10002600 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <9>;
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
new file mode 100644
index 000000000..1f9edd710
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm6328";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <160000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@10000004 {
+                        compatible = "brcm,bcm6328-clocks";
+                        reg = <0x10000004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_intc: interrupt-controller@10000020 {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0x10000020 0x10>,
+                              <0x10000030 0x10>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                uart0: serial@10000100 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000100 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <28>;
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+                        status = "disabled";
+                };
+
+                uart1: serial@10000120 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000120 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <39>;
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+                        status = "disabled";
+                };
+
+                timer: syscon@10000040 {
+                        compatible = "syscon";
+                        reg = <0x10000040 0x2c>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@10000068 {
+                        compatible = "syscon-reboot";
+                        regmap = <&timer>;
+                        offset = <0x28>;
+                        mask = <0x1>;
+                };
+
+                leds0: led-controller@10000800 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,bcm6328-leds";
+                        reg = <0x10000800 0x24>;
+                        status = "disabled";
+                };
+
+                periph_pwr: power-controller@10001848 {
+                        compatible = "brcm,bcm6328-power-controller";
+                        reg = <0x10001848 0x4>;
+                        #power-domain-cells = <1>;
+                };
+
+                ehci: usb@10002500 {
+                        compatible = "brcm,bcm6328-ehci", "generic-ehci";
+                        reg = <0x10002500 0x100>;
+                        big-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <42>;
+                        status = "disabled";
+                };
+
+                ohci: usb@10002600 {
+                        compatible = "brcm,bcm6328-ohci", "generic-ohci";
+                        reg = <0x10002600 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <41>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts b/arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts
new file mode 100644
index 000000000..53e57cc29
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm6358.dtsi"
+
+/ {
+        compatible = "sfr,nb4-ser", "brcm,bcm6358";
+        model = "SFR Neufbox 4 (Sercomm)";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x02000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&leds0 {
+        status = "okay";
+
+        led@0 {
+                reg = <0>;
+                active-low;
+                label = "nb4-ser:white:alarm";
+        };
+        led@2 {
+                reg = <2>;
+                active-low;
+                label = "nb4-ser:white:tv";
+        };
+        led@3 {
+                reg = <3>;
+                active-low;
+                label = "nb4-ser:white:tel";
+        };
+        led@4 {
+                reg = <4>;
+                active-low;
+                label = "nb4-ser:white:adsl";
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6358.dtsi b/arch/mips/boot/dts/brcm/bcm6358.dtsi
new file mode 100644
index 000000000..89a3107ca
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm6358";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <150000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@fffe0004 {
+                        compatible = "brcm,bcm6358-clocks";
+                        reg = <0xfffe0004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_cntl: syscon@fffe0008 {
+                        compatible = "syscon";
+                        reg = <0xfffe0008 0x4>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@fffe0008 {
+                        compatible = "syscon-reboot";
+                        regmap = <&periph_cntl>;
+                        offset = <0x0>;
+                        mask = <0x1>;
+                };
+
+                periph_intc: interrupt-controller@fffe000c {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0xfffe000c 0x8>,
+                              <0xfffe0038 0x8>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                leds0: led-controller@fffe00d0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,bcm6358-leds";
+                        reg = <0xfffe00d0 0x8>;
+
+                        status = "disabled";
+                };
+
+                uart0: serial@fffe0100 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0xfffe0100 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <2>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                uart1: serial@fffe0120 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0xfffe0120 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <3>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                ehci: usb@fffe1300 {
+                        compatible = "brcm,bcm6358-ehci", "generic-ehci";
+                        reg = <0xfffe1300 0x100>;
+                        big-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
+
+                ohci: usb@fffe1400 {
+                        compatible = "brcm,bcm6358-ohci", "generic-ohci";
+                        reg = <0xfffe1400 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <5>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts b/arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts
new file mode 100644
index 000000000..3e83bee5b
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm6362.dtsi"
+
+/ {
+        compatible = "sfr,nb6-ser", "brcm,bcm6362";
+        model = "SFR NeufBox 6 (Sercomm)";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6362.dtsi b/arch/mips/boot/dts/brcm/bcm6362.dtsi
new file mode 100644
index 000000000..0b2adefd7
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm6362";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <200000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@10000004 {
+                        compatible = "brcm,bcm6362-clocks";
+                        reg = <0x10000004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_cntl: syscon@10000008 {
+                        compatible = "syscon";
+                        reg = <0x10000008 0x4>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@10000008 {
+                        compatible = "syscon-reboot";
+                        regmap = <&periph_cntl>;
+                        offset = <0x0>;
+                        mask = <0x1>;
+                };
+
+                periph_intc: interrupt-controller@10000020 {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0x10000020 0x10>,
+                              <0x10000030 0x10>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                uart0: serial@10000100 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000100 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <3>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                uart1: serial@10000120 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000120 0x18>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <4>;
+
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+
+                        status = "disabled";
+                };
+
+                periph_pwr: power-controller@10001848 {
+                        compatible = "brcm,bcm6362-power-controller";
+                        reg = <0x10001848 0x4>;
+                        #power-domain-cells = <1>;
+                };
+
+                leds0: led-controller@10001900 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,bcm6328-leds";
+                        reg = <0x10001900 0x24>;
+
+                        status = "disabled";
+                };
+
+                ehci: usb@10002500 {
+                        compatible = "brcm,bcm6362-ehci", "generic-ehci";
+                        reg = <0x10002500 0x100>;
+                        big-endian;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <10>;
+
+                        status = "disabled";
+                };
+
+                ohci: usb@10002600 {
+                        compatible = "brcm,bcm6362-ohci", "generic-ohci";
+                        reg = <0x10002600 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <9>;
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
new file mode 100644
index 000000000..b84a3bfe8
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm6368";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <200000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4350";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                periph_clk: periph-clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ubus {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges;
+
+                clkctl: clock-controller@10000004 {
+                        compatible = "brcm,bcm6368-clocks";
+                        reg = <0x10000004 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                periph_cntl: syscon@100000008 {
+                        compatible = "syscon";
+                        reg = <0x10000008 0x4>;
+                        native-endian;
+                };
+
+                reboot: syscon-reboot@10000008 {
+                        compatible = "syscon-reboot";
+                        regmap = <&periph_cntl>;
+                        offset = <0x0>;
+                        mask = <0x1>;
+                };
+
+                periph_intc: interrupt-controller@10000020 {
+                        compatible = "brcm,bcm6345-l1-intc";
+                        reg = <0x10000020 0x10>,
+                              <0x10000030 0x10>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                leds0: led-controller@100000d0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,bcm6358-leds";
+                        reg = <0x100000d0 0x8>;
+                        status = "disabled";
+                };
+
+                uart0: serial@10000100 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000100 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <2>;
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+                        status = "disabled";
+                };
+
+                uart1: serial@10000120 {
+                        compatible = "brcm,bcm6345-uart";
+                        reg = <0x10000120 0x18>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <3>;
+                        clocks = <&periph_clk>;
+                        clock-names = "refclk";
+                        status = "disabled";
+                };
+
+                ehci: usb@10001500 {
+                        compatible = "brcm,bcm6368-ehci", "generic-ehci";
+                        reg = <0x10001500 0x100>;
+                        big-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <7>;
+                        status = "disabled";
+                };
+
+                ohci: usb@10001600 {
+                        compatible = "brcm,bcm6368-ohci", "generic-ohci";
+                        reg = <0x10001600 0x100>;
+                        big-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <5>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
new file mode 100644
index 000000000..5bf77b6fc
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7125";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <202500000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4380";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4380";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@441400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x441400 0x30>, <0x441600 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@401800 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x401800 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <23>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x2f7>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
+                                                     "bsp_0", "rdc_0", "rptd_0",
+                                                     "avd_0", "jtag_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406780 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <18>, <19>, <20>;
+                        interrupt-names = "upg_main", "upg_bsc", "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x60c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,bcm7038-reboot";
+                        syscon = <&sun_top_ctrl 0x8 0x14>;
+                };
+
+                uart0: serial@406b00 {
+                        compatible = "ns16550a";
+                        reg = <0x406b00 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <21>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406b40 {
+                        compatible = "ns16550a";
+                        reg = <0x406b40 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <64>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406b80 {
+                        compatible = "ns16550a";
+                        reg = <0x406b80 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@406380 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406380 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406580 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406580 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4067e8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4067e8 0x14>;
+                        status = "disabled";
+                };
+
+                upg_gio: gpio@406700 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406700 0x80>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 18>;
+                };
+
+                ehci0: usb@488300 {
+                        compatible = "brcm,bcm7125-ehci", "generic-ehci";
+                        reg = <0x488300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <60>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@488400 {
+                        compatible = "brcm,bcm7125-ohci", "generic-ohci";
+                        reg = <0x488400 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <79>;
+                };
+
+                qspi: spi@443000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@406400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x406400 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
new file mode 100644
index 000000000..2afa0dada
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -0,0 +1,549 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7346";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <163125000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@411400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x411400 0x30>, <0x411600 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <51>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x673>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
+                                                     "rdc_0", "raaga_0",
+                                                     "jtag_0", "svd_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406780 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0xf000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <59>, <57>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x408b80 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <60>, <58>, <62>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406900 {
+                        compatible = "ns16550a";
+                        reg = <0x406900 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <64>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406940 {
+                        compatible = "ns16550a";
+                        reg = <0x406940 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406980 {
+                        compatible = "ns16550a";
+                        reg = <0x406980 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@406380 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406380 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                bsce: i2c@408980 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x408980 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bsce";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406580 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406580 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                pwmb: pwm@406800 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406800 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4067e8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4067e8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408440 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408440 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <53>;
+                        brcm,irq-can-wake;
+                };
+
+                aon_ctrl: syscon@408000 {
+                        compatible = "brcm,brcmstb-aon-ctrl";
+                        reg = <0x408000 0x100>, <0x408200 0x200>;
+                        reg-names = "aon-ctrl", "aon-sram";
+                };
+
+                timers: timer@4067c0 {
+                        compatible = "brcm,brcmstb-timers";
+                        reg = <0x4067c0 0x40>;
+                };
+
+                upg_gio: gpio@406700 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406700 0x60>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 16>;
+                };
+
+                upg_gio_aon: gpio@408c00 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x408c00 0x60>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <27 32 2>;
+                };
+
+                enet0: ethernet@430000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v2";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x430000 0x4c8c>;
+                        interrupts = <24>, <25>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v2";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7346-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <68>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7346-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <70>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@480500 {
+                        compatible = "brcm,bcm7346-ehci", "generic-ehci";
+                        reg = <0x480500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <69>;
+                        status = "disabled";
+                };
+
+                ohci1: usb@480600 {
+                        compatible = "brcm,bcm7346-ohci", "generic-ohci";
+                        reg = <0x480600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <71>;
+                        status = "disabled";
+                };
+
+                ehci2: usb@490300 {
+                        compatible = "brcm,bcm7346-ehci", "generic-ehci";
+                        reg = <0x490300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <73>;
+                        status = "disabled";
+                };
+
+                ohci2: usb@490400 {
+                        compatible = "brcm,bcm7346-ohci", "generic-ohci";
+                        reg = <0x490400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <75>;
+                        status = "disabled";
+                };
+
+                ehci3: usb@490500 {
+                        compatible = "brcm,bcm7346-ehci", "generic-ehci";
+                        reg = <0x490500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <74>;
+                        status = "disabled";
+                };
+
+                ohci3: usb@490600 {
+                        compatible = "brcm,bcm7346-ohci", "generic-ohci";
+                        reg = <0x490600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <76>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@411000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <30>;
+                };
+
+                nand: nand@412800 {
+                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand";
+                        reg = <0x412800 0x400>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>;
+                        status = "disabled";
+                };
+
+                sata: sata@181000 {
+                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+                        reg-names = "ahci", "top-ctrl";
+                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <40>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy0>;
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy1>;
+                        };
+                };
+
+                sata_phy: sata-phy@180100 {
+                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+                        reg = <0x180100 0x0eff>;
+                        reg-names = "phy";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata_phy0: sata-phy@0 {
+                                reg = <0>;
+                                #phy-cells = <0>;
+                        };
+
+                        sata_phy1: sata-phy@1 {
+                                reg = <1>;
+                                #phy-cells = <0>;
+                        };
+                };
+
+                sdhci0: sdhci@413500 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x413500 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <85>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <31>;
+                };
+
+                qspi: spi@413000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@408a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x408a00 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@408e80 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x408e80 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+
+        memory_controllers {
+                compatible = "simple-bus";
+                ranges = <0x0 0x103b0000 0xa000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                memory-controller@0 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x0 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
new file mode 100644
index 000000000..6375fc77f
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7358";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <375000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips3300";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@411400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x411400 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <48>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x2f3>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
+                                                     "rdc_0", "raaga_0",
+                                                     "avd_0", "jtag_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406600 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406600 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <56>, <54>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x408b80 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <57>, <55>, <59>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406800 {
+                        compatible = "ns16550a";
+                        reg = <0x406800 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406840 {
+                        compatible = "ns16550a";
+                        reg = <0x406840 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <62>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406880 {
+                        compatible = "ns16550a";
+                        reg = <0x406880 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <63>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@408980 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x408980 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406400 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406400 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                pwmb: pwm@406700 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406700 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4066a8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4066a8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408240 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408240 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <50>;
+                        brcm,irq-can-wake;
+                };
+
+                upg_gio: gpio@406500 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406500 0xa0>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 29 4>;
+                };
+
+                upg_gio_aon: gpio@408c00 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x408c00 0x60>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <21 32 2>;
+                };
+
+                enet0: ethernet@430000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v2";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x430000 0x4c8c>;
+                        interrupts = <24>, <25>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v2";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7358-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7358-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@411000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <30>;
+                };
+
+                nand: nand@412800 {
+                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand";
+                        reg = <0x412800 0x400>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <31>;
+                };
+
+                qspi: spi@413000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@408a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x408a00 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@408e80 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x408e80 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
new file mode 100644
index 000000000..a57cacea9
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7360";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <375000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips3300";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@411400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x411400 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <48>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x2f3>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
+                                                     "rdc_0", "raaga_0",
+                                                     "avd_0", "jtag_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406600 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406600 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <56>, <54>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x408b80 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <57>, <55>, <59>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406800 {
+                        compatible = "ns16550a";
+                        reg = <0x406800 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406840 {
+                        compatible = "ns16550a";
+                        reg = <0x406840 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <62>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406880 {
+                        compatible = "ns16550a";
+                        reg = <0x406880 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <63>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@408980 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x408980 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406400 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406400 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4066a8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4066a8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408440 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408440 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <50>;
+                        brcm,irq-can-wake;
+                };
+
+                aon_ctrl: syscon@408000 {
+                        compatible = "brcm,brcmstb-aon-ctrl";
+                        reg = <0x408000 0x100>, <0x408200 0x200>;
+                        reg-names = "aon-ctrl", "aon-sram";
+                };
+
+                timers: timer@406680 {
+                        compatible = "brcm,brcmstb-timers";
+                        reg = <0x406680 0x40>;
+                };
+
+                upg_gio: gpio@406500 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406500 0xa0>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 29 4>;
+                };
+
+                upg_gio_aon: gpio@408c00 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x408c00 0x60>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <21 32 2>;
+                };
+
+                enet0: ethernet@430000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v2";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x430000 0x4c8c>;
+                        interrupts = <24>, <25>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v2";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7360-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7360-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@411000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <30>;
+                };
+
+                nand: nand@412800 {
+                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand";
+                        reg = <0x412800 0x400>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>;
+                        status = "disabled";
+                };
+
+                sata: sata@181000 {
+                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+                        reg-names = "ahci", "top-ctrl";
+                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <86>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy0>;
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy1>;
+                        };
+                };
+
+                sata_phy: sata-phy@180100 {
+                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+                        reg = <0x180100 0x0eff>;
+                        reg-names = "phy";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata_phy0: sata-phy@0 {
+                                reg = <0>;
+                                #phy-cells = <0>;
+                        };
+
+                        sata_phy1: sata-phy@1 {
+                                reg = <1>;
+                                #phy-cells = <0>;
+                        };
+                };
+
+                sdhci0: sdhci@410000 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x410000 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <82>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <31>;
+                };
+
+                qspi: spi@413000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@408a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x408a00 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@408e80 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x408e80 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+
+        memory_controllers {
+                compatible = "simple-bus";
+                ranges = <0x0 0x103b0000 0xa000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                memory-controller@0 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x0 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
new file mode 100644
index 000000000..728b9e9f8
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7362";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <375000000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips4380";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips4380";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@411400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x411400 0x30>, <0x411600 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <48>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x2f3>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
+                                                     "rdc_0", "raaga_0",
+                                                     "avd_0", "jtag_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406600 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406600 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <56>, <54>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@408b80 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x408b80 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <57>, <55>, <59>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406800 {
+                        compatible = "ns16550a";
+                        reg = <0x406800 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406840 {
+                        compatible = "ns16550a";
+                        reg = <0x406840 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <62>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406880 {
+                        compatible = "ns16550a";
+                        reg = <0x406880 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <63>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscd: i2c@408980 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x408980 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406400 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406400 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4066a8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4066a8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408440 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408440 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <50>;
+                        brcm,irq-can-wake;
+                };
+
+                aon_ctrl: syscon@408000 {
+                        compatible = "brcm,brcmstb-aon-ctrl";
+                        reg = <0x408000 0x100>, <0x408200 0x200>;
+                        reg-names = "aon-ctrl", "aon-sram";
+                };
+
+                timers: timer@406680 {
+                        compatible = "brcm,brcmstb-timers";
+                        reg = <0x406680 0x40>;
+                };
+
+                upg_gio: gpio@406500 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406500 0xa0>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 29 4>;
+                };
+
+                upg_gio_aon: gpio@408c00 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x408c00 0x60>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <21 32 2>;
+                };
+
+                enet0: ethernet@430000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v2";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x430000 0x4c8c>;
+                        interrupts = <24>, <25>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v2";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7362-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7362-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@411000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <30>;
+                };
+
+                nand: nand@412800 {
+                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand";
+                        reg = <0x412800 0x400>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>;
+                        status = "disabled";
+                };
+
+                sata: sata@181000 {
+                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+                        reg-names = "ahci", "top-ctrl";
+                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <86>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy0>;
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy1>;
+                        };
+                };
+
+                sata_phy: sata-phy@180100 {
+                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+                        reg = <0x180100 0x0eff>;
+                        reg-names = "phy";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata_phy0: sata-phy@0 {
+                                reg = <0>;
+                                #phy-cells = <0>;
+                        };
+
+                        sata_phy1: sata-phy@1 {
+                                reg = <1>;
+                                #phy-cells = <0>;
+                        };
+                };
+
+                sdhci0: sdhci@410000 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x410000 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <82>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <31>;
+                };
+
+                qspi: spi@413000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@408a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x408a00 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@408e80 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x408e80 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+
+        memory_controllers {
+                compatible = "simple-bus";
+                ranges = <0x0 0x103b0000 0xa000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                memory-controller@0 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x0 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
new file mode 100644
index 000000000..9540c27f1
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7420";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <93750000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@441400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x441400 0x30>, <0x441600 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@401800 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x401800 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <23>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x3ff>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
+                                                     "pcie_0", "bsp_0", "rdc_0",
+                                                     "rptd_0", "avd_0", "avd_1",
+                                                     "jtag_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406780 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <18>, <19>, <20>;
+                        interrupt-names = "upg_main", "upg_bsc", "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x60c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,bcm7038-reboot";
+                        syscon = <&sun_top_ctrl 0x8 0x14>;
+                };
+
+                uart0: serial@406b00 {
+                        compatible = "ns16550a";
+                        reg = <0x406b00 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <21>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406b40 {
+                        compatible = "ns16550a";
+                        reg = <0x406b40 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <64>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406b80 {
+                        compatible = "ns16550a";
+                        reg = <0x406b80 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@406380 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406380 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                bsce: i2c@406800 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406800 0x58>;
+                      interrupts = <28>;
+                      interrupt-names = "upg_bsce";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406580 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406580 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                pwmb: pwm@406880 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406880 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4067e8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4067e8 0x14>;
+                        status = "disabled";
+                };
+
+                upg_gio: gpio@406700 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406700 0x80>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 27>;
+                };
+
+                enet0: ethernet@468000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v1";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x468000 0x3c8c>;
+                        interrupts = <69>, <79>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v1";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,65nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@488300 {
+                        compatible = "brcm,bcm7420-ehci", "generic-ehci";
+                        reg = <0x488300 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <60>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@488400 {
+                        compatible = "brcm,bcm7420-ohci", "generic-ohci";
+                        reg = <0x488400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@488500 {
+                        compatible = "brcm,bcm7420-ehci", "generic-ehci";
+                        reg = <0x488500 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <55>;
+                        status = "disabled";
+                };
+
+                ohci1: usb@488600 {
+                        compatible = "brcm,bcm7420-ohci", "generic-ohci";
+                        reg = <0x488600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <62>;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@411d00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x411d00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <78>;
+                };
+
+                qspi: spi@443000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@406400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x406400 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
new file mode 100644
index 000000000..aa0b2d39c
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7425";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <163125000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips5000";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@41a400 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x41a400 0x30>, <0x41a600 0x30>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <47>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7400-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0x177b>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
+                                                     "bsp_0", "rdc_0",
+                                                     "raaga_0", "avd_1",
+                                                     "jtag_0", "svd_0",
+                                                     "vice_0";
+                };
+
+                upg_irq0_intc: interrupt-controller@406780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406780 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <55>, <53>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@409480 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x409480 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <56>, <54>, <59>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406b00 {
+                        compatible = "ns16550a";
+                        reg = <0x406b00 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406b40 {
+                        compatible = "ns16550a";
+                        reg = <0x406b40 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <62>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406b80 {
+                        compatible = "ns16550a";
+                        reg = <0x406b80 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <63>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@409180 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x409180 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@409400 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x409400 0x58>;
+                      interrupts = <28>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                bsce: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bsce";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406580 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406580 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                pwmb: pwm@406800 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406800 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4067e8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4067e8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408440 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408440 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <49>;
+                        brcm,irq-can-wake;
+                };
+
+                aon_ctrl: syscon@408000 {
+                        compatible = "brcm,brcmstb-aon-ctrl";
+                        reg = <0x408000 0x100>, <0x408200 0x200>;
+                        reg-names = "aon-ctrl", "aon-sram";
+                };
+
+                timers: timer@4067c0 {
+                        compatible = "brcm,brcmstb-timers";
+                        reg = <0x4067c0 0x40>;
+                };
+
+                upg_gio: gpio@406700 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406700 0x80>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 21>;
+                };
+
+                upg_gio_aon: gpio@4094c0 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x4094c0 0x40>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <18 4>;
+                };
+
+                enet0: ethernet@b80000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v3";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0xb80000 0x11c88>;
+                        interrupts = <17>, <18>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v3";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7425-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <65>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7425-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <67>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@480500 {
+                        compatible = "brcm,bcm7425-ehci", "generic-ehci";
+                        reg = <0x480500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        status = "disabled";
+                };
+
+                ohci1: usb@480600 {
+                        compatible = "brcm,bcm7425-ohci", "generic-ohci";
+                        reg = <0x480600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <68>;
+                        status = "disabled";
+                };
+
+                ehci2: usb@490300 {
+                        compatible = "brcm,bcm7425-ehci", "generic-ehci";
+                        reg = <0x490300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <70>;
+                        status = "disabled";
+                };
+
+                ohci2: usb@490400 {
+                        compatible = "brcm,bcm7425-ohci", "generic-ohci";
+                        reg = <0x490400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <72>;
+                        status = "disabled";
+                };
+
+                ehci3: usb@490500 {
+                        compatible = "brcm,bcm7425-ehci", "generic-ehci";
+                        reg = <0x490500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <71>;
+                        status = "disabled";
+                };
+
+                ohci3: usb@490600 {
+                        compatible = "brcm,bcm7425-ohci", "generic-ohci";
+                        reg = <0x490600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <73>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@41a000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x41a000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <24>;
+                };
+
+                nand: nand@41b800 {
+                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand", "flash-edu";
+                        reg = <0x41b800 0x400>, <0x41bc00 0x24>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>;
+                        status = "disabled";
+                };
+
+                sata: sata@181000 {
+                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+                        reg-names = "ahci", "top-ctrl";
+                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <41>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy0>;
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy1>;
+                        };
+                };
+
+                sata_phy: sata-phy@180100 {
+                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+                        reg = <0x180100 0x0eff>;
+                        reg-names = "phy";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata_phy0: sata-phy@0 {
+                                reg = <0>;
+                                #phy-cells = <0>;
+                        };
+
+                        sata_phy1: sata-phy@1 {
+                                reg = <1>;
+                                #phy-cells = <0>;
+                        };
+                };
+
+                sdhci0: sdhci@419000 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x419000 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <43>;
+                        sd-uhs-sdr50;
+                        mmc-hs200-1_8v;
+                        status = "disabled";
+                };
+
+                sdhci1: sdhci@419200 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x419200 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <44>;
+                        sd-uhs-sdr50;
+                        mmc-hs200-1_8v;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@41ad00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x41ad00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <25>;
+                };
+
+                qspi: spi@41c000 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@409200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x409200 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@409580 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x409580 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+
+        memory_controllers {
+                compatible = "simple-bus";
+                ranges = <0x0 0x103b0000 0x1a000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                memory-controller@0 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x0 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+
+                memory-controller@1 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x10000 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
new file mode 100644
index 000000000..8398b7f68
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "brcm,bcm7435";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mips-hpt-frequency = <175625000>;
+
+                cpu@0 {
+                        compatible = "brcm,bmips5200";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "brcm,bmips5200";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+
+                cpu@2 {
+                        compatible = "brcm,bmips5200";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+
+                cpu@3 {
+                        compatible = "brcm,bmips5200";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        clocks {
+                uart_clk: uart_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <81000000>;
+                };
+
+                upg_clk: upg_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+
+        rdb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                compatible = "simple-bus";
+                ranges = <0 0x10000000 0x01000000>;
+
+                periph_intc: interrupt-controller@41b500 {
+                        compatible = "brcm,bcm7038-l1-intc";
+                        reg = <0x41b500 0x40>, <0x41b600 0x40>,
+                                <0x41b700 0x40>, <0x41b800 0x40>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <2>, <3>, <2>, <3>;
+                };
+
+                sun_l2_intc: interrupt-controller@403000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x403000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <52>;
+                };
+
+                gisb-arb@400000 {
+                        compatible = "brcm,bcm7435-gisb-arb";
+                        reg = <0x400000 0xdc>;
+                        native-endian;
+                        interrupt-parent = <&sun_l2_intc>;
+                        interrupts = <0>, <2>;
+                        brcm,gisb-arb-master-mask = <0xf77f>;
+                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
+                                                     "pcie_0", "bsp_0",
+                                                     "rdc_0", "raaga_0",
+                                                     "avd_1", "jtag_0",
+                                                     "svd_0", "vice_0",
+                                                     "vice_1", "raaga_1",
+                                                     "scpu";
+                };
+
+                upg_irq0_intc: interrupt-controller@406780 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x406780 0x8>;
+
+                        brcm,int-map-mask = <0x44>, <0x7000000>;
+                        brcm,int-fwd-mask = <0x70000>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <60>, <58>;
+                        interrupt-names = "upg_main", "upg_bsc";
+                };
+
+                upg_aon_irq0_intc: interrupt-controller@409480 {
+                        compatible = "brcm,bcm7120-l2-intc";
+                        reg = <0x409480 0x8>;
+
+                        brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
+                        brcm,int-fwd-mask = <0>;
+                        brcm,irq-can-wake;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <61>, <59>, <64>;
+                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
+                                          "upg_spi";
+                };
+
+                sun_top_ctrl: syscon@404000 {
+                        compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
+                        reg = <0x404000 0x51c>;
+                        native-endian;
+                };
+
+                reboot {
+                        compatible = "brcm,brcmstb-reboot";
+                        syscon = <&sun_top_ctrl 0x304 0x308>;
+                };
+
+                uart0: serial@406b00 {
+                        compatible = "ns16550a";
+                        reg = <0x406b00 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <66>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart1: serial@406b40 {
+                        compatible = "ns16550a";
+                        reg = <0x406b40 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <67>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                uart2: serial@406b80 {
+                        compatible = "ns16550a";
+                        reg = <0x406b80 0x20>;
+                        reg-io-width = <0x4>;
+                        reg-shift = <0x2>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <68>;
+                        clocks = <&uart_clk>;
+                        status = "disabled";
+                };
+
+                bsca: i2c@406300 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406300 0x58>;
+                      interrupts = <26>;
+                      interrupt-names = "upg_bsca";
+                      status = "disabled";
+                };
+
+                bscb: i2c@409400 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x409400 0x58>;
+                      interrupts = <28>;
+                      interrupt-names = "upg_bscb";
+                      status = "disabled";
+                };
+
+                bscc: i2c@406200 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406200 0x58>;
+                      interrupts = <24>;
+                      interrupt-names = "upg_bscc";
+                      status = "disabled";
+                };
+
+                bscd: i2c@406280 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_irq0_intc>;
+                      reg = <0x406280 0x58>;
+                      interrupts = <25>;
+                      interrupt-names = "upg_bscd";
+                      status = "disabled";
+                };
+
+                bsce: i2c@409180 {
+                      clock-frequency = <390000>;
+                      compatible = "brcm,brcmstb-i2c";
+                      interrupt-parent = <&upg_aon_irq0_intc>;
+                      reg = <0x409180 0x58>;
+                      interrupts = <27>;
+                      interrupt-names = "upg_bsce";
+                      status = "disabled";
+                };
+
+                pwma: pwm@406580 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406580 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                pwmb: pwm@406800 {
+                        compatible = "brcm,bcm7038-pwm";
+                        reg = <0x406800 0x28>;
+                        #pwm-cells = <2>;
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+
+                watchdog: watchdog@4067e8 {
+                        clocks = <&upg_clk>;
+                        compatible = "brcm,bcm7038-wdt";
+                        reg = <0x4067e8 0x14>;
+                        status = "disabled";
+                };
+
+                aon_pm_l2_intc: interrupt-controller@408440 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x408440 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <54>;
+                        brcm,irq-can-wake;
+                };
+
+                aon_ctrl: syscon@408000 {
+                        compatible = "brcm,brcmstb-aon-ctrl";
+                        reg = <0x408000 0x100>, <0x408200 0x200>;
+                        reg-names = "aon-ctrl", "aon-sram";
+                };
+
+                timers: timer@4067c0 {
+                        compatible = "brcm,brcmstb-timers";
+                        reg = <0x4067c0 0x40>;
+                };
+
+                upg_gio: gpio@406700 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x406700 0x80>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_irq0_intc>;
+                        interrupts = <6>;
+                        brcm,gpio-bank-widths = <32 32 32 21>;
+                };
+
+                upg_gio_aon: gpio@4094c0 {
+                        compatible = "brcm,brcmstb-gpio";
+                        reg = <0x4094c0 0x40>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupts = <6>;
+                        interrupts-extended = <&upg_aon_irq0_intc 6>,
+                                              <&aon_pm_l2_intc 5>;
+                        wakeup-source;
+                        brcm,gpio-bank-widths = <18 4>;
+                };
+
+                enet0: ethernet@b80000 {
+                        phy-mode = "internal";
+                        phy-handle = <&phy1>;
+                        mac-address = [ 00 10 18 36 23 1a ];
+                        compatible = "brcm,genet-v3";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0xb80000 0x11c88>;
+                        interrupts = <17>, <18>;
+                        interrupt-parent = <&periph_intc>;
+                        status = "disabled";
+
+                        mdio@e14 {
+                                compatible = "brcm,genet-mdio-v3";
+                                #address-cells = <0x1>;
+                                #size-cells = <0x0>;
+                                reg = <0xe14 0x8>;
+
+                                phy1: ethernet-phy@1 {
+                                        max-speed = <100>;
+                                        reg = <0x1>;
+                                        compatible = "brcm,40nm-ephy",
+                                                "ethernet-phy-ieee802.3-c22";
+                                };
+                        };
+                };
+
+                ehci0: usb@480300 {
+                        compatible = "brcm,bcm7435-ehci", "generic-ehci";
+                        reg = <0x480300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <70>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@480400 {
+                        compatible = "brcm,bcm7435-ohci", "generic-ohci";
+                        reg = <0x480400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <72>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@480500 {
+                        compatible = "brcm,bcm7435-ehci", "generic-ehci";
+                        reg = <0x480500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <71>;
+                        status = "disabled";
+                };
+
+                ohci1: usb@480600 {
+                        compatible = "brcm,bcm7435-ohci", "generic-ohci";
+                        reg = <0x480600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <73>;
+                        status = "disabled";
+                };
+
+                ehci2: usb@490300 {
+                        compatible = "brcm,bcm7435-ehci", "generic-ehci";
+                        reg = <0x490300 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <75>;
+                        status = "disabled";
+                };
+
+                ohci2: usb@490400 {
+                        compatible = "brcm,bcm7435-ohci", "generic-ohci";
+                        reg = <0x490400 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <77>;
+                        status = "disabled";
+                };
+
+                ehci3: usb@490500 {
+                        compatible = "brcm,bcm7435-ehci", "generic-ehci";
+                        reg = <0x490500 0x100>;
+                        native-endian;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <76>;
+                        status = "disabled";
+                };
+
+                ohci3: usb@490600 {
+                        compatible = "brcm,bcm7435-ohci", "generic-ohci";
+                        reg = <0x490600 0x100>;
+                        native-endian;
+                        no-big-frame-no;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <78>;
+                        status = "disabled";
+                };
+
+                hif_l2_intc: interrupt-controller@41b000 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x41b000 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <24>;
+                };
+
+                nand: nand@41c800 {
+                        compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg-names = "nand", "flash-dma";
+                        reg = <0x41c800 0x600>, <0x41d000 0x100>;
+                        interrupt-parent = <&hif_l2_intc>;
+                        interrupts = <24>, <4>;
+                        status = "disabled";
+                };
+
+                sata: sata@181000 {
+                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+                        reg-names = "ahci", "top-ctrl";
+                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <45>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy0>;
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy1>;
+                        };
+                };
+
+                sata_phy: sata-phy@180100 {
+                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+                        reg = <0x180100 0x0eff>;
+                        reg-names = "phy";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        sata_phy0: sata-phy@0 {
+                                reg = <0>;
+                                #phy-cells = <0>;
+                        };
+
+                        sata_phy1: sata-phy@1 {
+                                reg = <1>;
+                                #phy-cells = <0>;
+                        };
+                };
+
+                sdhci0: sdhci@41a000 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x41a000 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <47>;
+                        sd-uhs-sdr50;
+                        mmc-hs200-1_8v;
+                        status = "disabled";
+                };
+
+                sdhci1: sdhci@41a200 {
+                        compatible = "brcm,bcm7425-sdhci";
+                        reg = <0x41a200 0x100>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <48>;
+                        sd-uhs-sdr50;
+                        mmc-hs200-1_8v;
+                        status = "disabled";
+                };
+
+                spi_l2_intc: interrupt-controller@41bd00 {
+                        compatible = "brcm,l2-intc";
+                        reg = <0x41bd00 0x30>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&periph_intc>;
+                        interrupts = <25>;
+                };
+
+                qspi: spi@41d200 {
+                        #address-cells = <0x1>;
+                        #size-cells = <0x0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-qspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
+                        reg-names = "cs_reg", "hif_mspi", "bspi";
+                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
+                        interrupt-parent = <&spi_l2_intc>;
+                        interrupt-names = "spi_lr_fullness_reached",
+                                          "spi_lr_session_aborted",
+                                          "spi_lr_impatient",
+                                          "spi_lr_session_done",
+                                          "spi_lr_overread",
+                                          "mspi_done",
+                                          "mspi_halted";
+                        status = "disabled";
+                };
+
+                mspi: spi@409200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "brcm,spi-bcm-qspi",
+                                     "brcm,spi-brcmstb-mspi";
+                        clocks = <&upg_clk>;
+                        reg = <0x409200 0x180>;
+                        reg-names = "mspi";
+                        interrupts = <0x14>;
+                        interrupt-parent = <&upg_aon_irq0_intc>;
+                        interrupt-names = "mspi_done";
+                        status = "disabled";
+                };
+
+                waketimer: waketimer@409580 {
+                        compatible = "brcm,brcmstb-waketimer";
+                        reg = <0x409580 0x14>;
+                        interrupts = <0x3>;
+                        interrupt-parent = <&aon_pm_l2_intc>;
+                        interrupt-names = "timer";
+                        clocks = <&upg_clk>;
+                        status = "disabled";
+                };
+        };
+
+        memory_controllers {
+                compatible = "simple-bus";
+                ranges = <0x0 0x103b0000 0x1a000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                memory-controller@0 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x0 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+
+                memory-controller@1 {
+                        compatible = "brcm,brcmstb-memc", "simple-bus";
+                        ranges = <0x0 0x10000 0xa000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        memc-arb@1000 {
+                                compatible = "brcm,brcmstb-memc-arb";
+                                reg = <0x1000 0x248>;
+                        };
+
+                        memc-ddr@2000 {
+                                compatible = "brcm,brcmstb-memc-ddr";
+                                reg = <0x2000 0x300>;
+                        };
+
+                        ddr-phy@6000 {
+                                compatible = "brcm,brcmstb-ddr-phy";
+                                reg = <0x6000 0xc8>;
+                        };
+
+                        shimphy@8000 {
+                                compatible = "brcm,brcmstb-ddr-shimphy";
+                                reg = <0x8000 0x13c>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm93384wvg.dts b/arch/mips/boot/dts/brcm/bcm93384wvg.dts
new file mode 100644
index 000000000..601e4d929
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm93384wvg.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm3384_zephyr.dtsi"
+
+/ {
+        compatible = "brcm,bcm93384wvg", "brcm,bcm3384";
+        model = "Broadcom BCM93384WVG";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts b/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
new file mode 100644
index 000000000..938a8e661
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm3384_viper.dtsi"
+
+/ {
+        compatible = "brcm,bcm93384wvg-viper", "brcm,bcm3384-viper";
+        model = "Broadcom BCM93384WVG-viper";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm96368mvwg.dts b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts
new file mode 100644
index 000000000..6d772c394
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm6368.dtsi"
+
+/ {
+        compatible = "brcm,bcm96368mvwg", "brcm,bcm6368";
+        model = "Broadcom BCM96368MVWG";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x04000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+/* FIXME: need to set up USB_CTRL registers first */
+&ehci {
+        status = "disabled";
+};
+
+&ohci {
+        status = "disabled";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
new file mode 100644
index 000000000..79e9769f7
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7125.dtsi"
+
+/ {
+        compatible = "brcm,bcm97125cbmb", "brcm,bcm7125";
+        model = "Broadcom BCM97125CBMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+/* FIXME: USB is wonky; disable it for now */
+&ehci0 {
+        status = "disabled";
+};
+
+&ohci0 {
+        status = "disabled";
+};
+
+&mspi {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
new file mode 100644
index 000000000..28370ff77
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7346.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
+
+/ {
+        compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
+        model = "Broadcom BCM97346DBSMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&bsce {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&pwmb {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&ehci2 {
+        status = "okay";
+};
+
+&ohci2 {
+        status = "okay";
+};
+
+&ehci3 {
+        status = "okay";
+};
+
+&ohci3 {
+        status = "okay";
+};
+
+&nand {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
new file mode 100644
index 000000000..41c1b510c
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7358.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
+
+/ {
+        compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
+        model = "Broadcom BCM97358SVMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&pwmb {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&nand {
+        status = "okay";
+};
+
+&qspi {
+        status = "okay";
+
+        m25p80@0 {
+                compatible = "m25p80";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+                spi-cpol;
+                spi-cpha;
+                use-bspi;
+                m25p,fast-read;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        flash0.cfe@0 {
+                                reg = <0x0 0x200000>;
+                        };
+
+                        flash0.mac@200000 {
+                                reg = <0x200000 0x40000>;
+                        };
+
+                        flash0.nvram@240000 {
+                                reg = <0x240000 0x10000>;
+                        };
+                };
+        };
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
new file mode 100644
index 000000000..9f6c6c9b7
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7360.dtsi"
+
+/ {
+        compatible = "brcm,bcm97360svmb", "brcm,bcm7360";
+        model = "Broadcom BCM97360SVMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&qspi {
+        status = "okay";
+
+        m25p80@0 {
+                compatible = "m25p80";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+                spi-cpol;
+                spi-cpha;
+                use-bspi;
+                m25p,fast-read;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        flash0.cfe@0 {
+                                reg = <0x0 0x200000>;
+                        };
+
+                        flash0.mac@200000 {
+                                reg = <0x200000 0x40000>;
+                        };
+
+                        flash0.nvram@240000 {
+                                reg = <0x240000 0x10000>;
+                        };
+                };
+        };
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
new file mode 100644
index 000000000..df8b755c3
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7362.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
+
+/ {
+        compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
+        model = "Broadcom BCM97362SVMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&nand {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts
new file mode 100644
index 000000000..086faeaa3
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97420c.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7420.dtsi"
+
+/ {
+        compatible = "brcm,bcm97420c", "brcm,bcm7420";
+        model = "Broadcom BCM97420C";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>,
+                      <0x20000000 0x30000000>,
+                      <0x60000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&bsce {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&pwmb {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+/* FIXME: MAC driver comes up but cannot attach to PHY */
+&enet0 {
+        status = "disabled";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&mspi {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
new file mode 100644
index 000000000..0ed22217b
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7425.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
+
+/ {
+        compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
+        model = "Broadcom BCM97425SVMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>,
+                      <0x20000000 0x30000000>,
+                      <0x90000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&bsce {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&pwmb {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&ehci2 {
+        status = "okay";
+};
+
+&ohci2 {
+        status = "okay";
+};
+
+&ehci3 {
+        status = "okay";
+};
+
+&ohci3 {
+        status = "okay";
+};
+
+&nand {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&sdhci1 {
+        status = "okay";
+};
+
+&qspi {
+        status = "okay";
+
+        m25p80@0 {
+                compatible = "m25p80";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+                spi-cpol;
+                spi-cpha;
+                use-bspi;
+                m25p,fast-read;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        flash0.cfe@0 {
+                                reg = <0x0 0x200000>;
+                        };
+
+                        flash0.mac@200000 {
+                                reg = <0x200000 0x40000>;
+                        };
+
+                        flash0.nvram@240000 {
+                                reg = <0x240000 0x10000>;
+                        };
+                };
+        };
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
new file mode 100644
index 000000000..2c145a883
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm7435.dtsi"
+/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
+
+/ {
+        compatible = "brcm,bcm97435svmb", "brcm,bcm7435";
+        model = "Broadcom BCM97435SVMB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>,
+                      <0x20000000 0x30000000>,
+                      <0x90000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&bsca {
+        status = "okay";
+};
+
+&bscb {
+        status = "okay";
+};
+
+&bscc {
+        status = "okay";
+};
+
+&bscd {
+        status = "okay";
+};
+
+&bsce {
+        status = "okay";
+};
+
+&pwma {
+        status = "okay";
+};
+
+&pwmb {
+        status = "okay";
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&enet0 {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&ehci2 {
+        status = "okay";
+};
+
+&ohci2 {
+        status = "okay";
+};
+
+&ehci3 {
+        status = "okay";
+};
+
+&ohci3 {
+        status = "okay";
+};
+
+&nand {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&sdhci1 {
+        status = "okay";
+};
+
+&mspi {
+        status = "okay";
+};
+
+&waketimer {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
new file mode 100644
index 000000000..96c30d857
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+&nand {
+        nandcs@1 {
+                compatible = "brcm,nandcs";
+                reg = <1>;
+                nand-on-flash-bbt;
+
+                nand-ecc-strength = <24>;
+                nand-ecc-step-size = <1024>;
+                brcm,nand-oob-sector-size = <27>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        flash1.rootfs@0 {
+                                reg = <0x0 0x10000000>;
+                        };
+
+                        flash1.kernel@10000000 {
+                                reg = <0x10000000 0x400000>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
new file mode 100644
index 000000000..7b5afefbb
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+&nand {
+        nandcs@1 {
+                compatible = "brcm,nandcs";
+                reg = <1>;
+                nand-on-flash-bbt;
+
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+                brcm,nand-oob-sector-size = <16>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        flash1.rootfs@0 {
+                                reg = <0x0 0x10000000>;
+                        };
+
+                        flash1.kernel@10000000 {
+                                reg = <0x10000000 0x400000>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts b/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
new file mode 100644
index 000000000..8d58c1971
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "bcm6328.dtsi"
+
+/ {
+        compatible = "brcm,bcm9ejtagprb", "brcm,bcm6328";
+        model = "Broadcom BCM9EJTAGPRB";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/cavium-octeon/Makefile b/arch/mips/boot/dts/cavium-octeon/Makefile
new file mode 100644
index 000000000..17aef35f3
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
new file mode 100644
index 000000000..2fdb4baad
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device tree source for D-Link DSR-1000N.
+ *
+ * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
+ */
+
+/include/ "dlink_dsr-500n-1000n.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "dlink,dsr-1000n";
+
+        soc@0 {
+                uart0: serial@1180000000800 {
+                        clock-frequency = <500000000>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                usb1 {
+                        label = "usb1";
+                        gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+                };
+
+                usb2 {
+                        label = "usb2";
+                        gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+                };
+
+                wps {
+                        label = "wps";
+                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+                };
+
+                wireless1 {
+                        label = "5g";
+                        gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+                };
+
+                wireless2 {
+                        label = "2.4g";
+                        gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi
new file mode 100644
index 000000000..b4acdb26a
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device tree source for D-Link DSR-500N/1000N (common parts).
+ *
+ * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
+ */
+
+/include/ "octeon_3xxx.dtsi"
+
+/ {
+        soc@0 {
+                smi0: mdio@1180000001800 {
+                        phy8: ethernet-phy@8 {
+                                reg = <8>;
+                                compatible = "ethernet-phy-ieee802.3-c22";
+                        };
+                };
+
+                pip: pip@11800a0000000 {
+                        interface@0 {
+                                ethernet@0 {
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+                                ethernet@1 {
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+                                ethernet@2 {
+                                        phy-handle = <&phy8>;
+                                };
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        rtc@68 {
+                                compatible = "dallas,ds1337";
+                                reg = <0x68>;
+                        };
+                };
+
+                usbn: usbn@1180068000000 {
+                        refclk-frequency = <12000000>;
+                        refclk-type = "crystal";
+                };
+        };
+
+        aliases {
+                pip = &pip;
+        };
+};
diff --git a/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
new file mode 100644
index 000000000..e04237281
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device tree source for D-Link DSR-500N.
+ *
+ * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
+ */
+
+/include/ "dlink_dsr-500n-1000n.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "dlink,dsr-500n";
+        compatible = "dlink,dsr-500n", "cavium,octeon-3860";
+
+        soc@0 {
+                uart0: serial@1180000000800 {
+                        clock-frequency = <300000000>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                usb {
+                        gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+                };
+
+                wps {
+                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+                };
+
+                wireless {
+                        label = "2.4g";
+                        gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
new file mode 100644
index 000000000..dda0559ce
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
+ *
+ * This device tree is pruned and patched by early boot code before
+ * use.  Because of this, it contains a super-set of the available
+ * devices and properties.
+ */
+
+/include/ "octeon_3xxx.dtsi"
+
+/ {
+        soc@0 {
+                smi0: mdio@1180000001800 {
+                        phy0: ethernet-phy@0 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <0>;
+                        };
+
+                        phy1: ethernet-phy@1 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <1>;
+                        };
+
+                        phy2: ethernet-phy@2 {
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy4: ethernet-phy@4 {
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy5: ethernet-phy@5 {
+                                reg = <5>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+
+                        phy6: ethernet-phy@6 {
+                                reg = <6>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy7: ethernet-phy@7 {
+                                reg = <7>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy8: ethernet-phy@8 {
+                                reg = <8>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy9: ethernet-phy@9 {
+                                reg = <9>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi1: mdio@1180000001900 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00001900 0x0 0x40>;
+
+                        phy100: ethernet-phy@1 {
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy101: ethernet-phy@2 {
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy102: ethernet-phy@3 {
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy103: ethernet-phy@4 {
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                };
+
+                mix0: ethernet@1070000100000 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000000 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <0>;
+                        interrupts = <0 62>, <1 46>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy0>;
+                };
+
+                mix1: ethernet@1070000100800 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000800 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <1>;
+                        interrupts = <1 18>, < 1 46>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy1>;
+                };
+
+                pip: pip@11800a0000000 {
+                        interface@0 {
+                                ethernet@0 {
+                                        phy-handle = <&phy2>;
+                                        cavium,alt-phy-handle = <&phy100>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0>;
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+                                ethernet@1 {
+                                        phy-handle = <&phy3>;
+                                        cavium,alt-phy-handle = <&phy101>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0>;
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+                                ethernet@2 {
+                                        phy-handle = <&phy4>;
+                                        cavium,alt-phy-handle = <&phy102>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy5>;
+                                        cavium,alt-phy-handle = <&phy103>;
+                                };
+                                ethernet@4 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x4>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@5 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x5>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@6 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x6>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@7 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x7>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@8 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x8>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@9 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x9>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@a {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xa>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@b {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xb>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@c {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xc>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@d {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xd>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@e {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xe>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@f {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xf>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                        };
+
+                        interface@1 {
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy6>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy7>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy8>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy9>;
+                                };
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        rtc@68 {
+                                compatible = "dallas,ds1337";
+                                reg = <0x68>;
+                        };
+                        tmp@4c {
+                                compatible = "ti,tmp421";
+                                reg = <0x4c>;
+                        };
+                };
+
+                twsi1: i2c@1180000001200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001200 0x0 0x200>;
+                        interrupts = <0 59>;
+                        clock-frequency = <100000>;
+                };
+
+                uart1: serial@1180000000c00 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000c00 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <0 35>;
+                };
+
+                uart2: serial@1180000000400 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000400 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <1 16>;
+                };
+
+                bootbus: bootbus@1180000000000 {
+                        led0: led-display@4,0 {
+                                compatible = "avago,hdsp-253x";
+                                reg = <4 0x20 0x20>, <4 0 0x20>;
+                        };
+
+                        cf0: compact-flash@5,0 {
+                                compatible = "cavium,ebt3000-compact-flash";
+                                reg = <5 0 0x10000>, <6 0 0x10000>;
+                                cavium,bus-width = <16>;
+                                cavium,true-ide;
+                                cavium,dma-engine-handle = <&dma0>;
+                        };
+                };
+
+                uctl: uctl@118006f000000 {
+                        compatible = "cavium,octeon-6335-uctl";
+                        reg = <0x11800 0x6f000000 0x0 0x100>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+
+                        ehci@16f0000000000 {
+                                compatible = "cavium,octeon-6335-ehci","usb-ehci";
+                                reg = <0x16f00 0x00000000 0x0 0x100>;
+                                interrupts = <0 56>;
+                                big-endian-regs;
+                        };
+                        ohci@16f0000000400 {
+                                compatible = "cavium,octeon-6335-ohci","usb-ohci";
+                                reg = <0x16f00 0x00000400 0x0 0x100>;
+                                interrupts = <0 56>;
+                                big-endian-regs;
+                        };
+                };
+
+                usbn: usbn@1180068000000 {
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+                };
+        };
+
+        aliases {
+                mix0 = &mix0;
+                mix1 = &mix1;
+                pip = &pip;
+                smi0 = &smi0;
+                smi1 = &smi1;
+                twsi0 = &twsi0;
+                twsi1 = &twsi1;
+                uart0 = &uart0;
+                uart1 = &uart1;
+                uart2 = &uart2;
+                flash0 = &flash0;
+                cf0 = &cf0;
+                uctl = &uctl;
+                usbn = &usbn;
+                led0 = &led0;
+        };
+ };
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi
new file mode 100644
index 000000000..3c296623d
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/* OCTEON 3XXX DTS common parts. */
+
+/dts-v1/;
+
+/ {
+        compatible = "cavium,octeon-3860";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&ciu>;
+
+        soc@0 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges; /* Direct mapping */
+
+                ciu: interrupt-controller@1070000000000 {
+                        compatible = "cavium,octeon-3860-ciu";
+                        interrupt-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) Controller register (0 or 1)
+                         * 2) Bit within the register (0..63)
+                         */
+                        #interrupt-cells = <2>;
+                        reg = <0x10700 0x00000000 0x0 0x7000>;
+                };
+
+                gpio: gpio-controller@1070000000800 {
+                        #gpio-cells = <2>;
+                        compatible = "cavium,octeon-3860-gpio";
+                        reg = <0x10700 0x00000800 0x0 0x100>;
+                        gpio-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) GPIO pin number (0..15)
+                         * 2) Triggering (1 - edge rising
+                         *                2 - edge falling
+                         *                4 - level active high
+                         *                8 - level active low)
+                         */
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        /* The GPIO pin connect to 16 consecutive CUI bits */
+                        interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
+                                     <0 20>, <0 21>, <0 22>, <0 23>,
+                                     <0 24>, <0 25>, <0 26>, <0 27>,
+                                     <0 28>, <0 29>, <0 30>, <0 31>;
+                };
+
+                smi0: mdio@1180000001800 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00001800 0x0 0x40>;
+                };
+
+                pip: pip@11800a0000000 {
+                        compatible = "cavium,octeon-3860-pip";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+                        interface@0 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                        };
+
+                        interface@1 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <1>; /* interface */
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001000 0x0 0x200>;
+                        interrupts = <0 45>;
+                        clock-frequency = <100000>;
+                };
+
+                uart0: serial@1180000000800 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000800 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <0 34>;
+                };
+
+                bootbus: bootbus@1180000000000 {
+                        compatible = "cavium,octeon-3860-bootbus";
+                        reg = <0x11800 0x00000000 0x0 0x200>;
+                        /* The chip select number and offset */
+                        #address-cells = <2>;
+                        /* The size of the chip select region */
+                        #size-cells = <1>;
+                        ranges = <0 0  0x0 0x1f400000  0xc00000>,
+                                 <1 0  0x10000 0x30000000  0>,
+                                 <2 0  0x10000 0x40000000  0>,
+                                 <3 0  0x10000 0x50000000  0>,
+                                 <4 0  0x0 0x1d020000  0x10000>,
+                                 <5 0  0x0 0x1d040000  0x10000>,
+                                 <6 0  0x0 0x1d050000  0x10000>,
+                                 <7 0  0x10000 0x90000000  0>;
+
+                        cavium,cs-config@0 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <0>;
+                                cavium,t-adr  = <20>;
+                                cavium,t-ce   = <60>;
+                                cavium,t-oe   = <60>;
+                                cavium,t-we   = <45>;
+                                cavium,t-rd-hld = <35>;
+                                cavium,t-wr-hld = <45>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <0>;
+                                cavium,t-page   = <35>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@4 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <4>;
+                                cavium,t-adr  = <320>;
+                                cavium,t-ce   = <320>;
+                                cavium,t-oe   = <320>;
+                                cavium,t-we   = <320>;
+                                cavium,t-rd-hld = <320>;
+                                cavium,t-wr-hld = <320>;
+                                cavium,t-pause  = <320>;
+                                cavium,t-wait   = <320>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@5 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <5>;
+                                cavium,t-adr  = <5>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <30>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <30>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <16>;
+                        };
+                        cavium,cs-config@6 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <6>;
+                                cavium,t-adr  = <5>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <270>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <70>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <0>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,wait-mode;
+                                cavium,bus-width = <16>;
+                        };
+
+                        flash0: nor@0,0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                        };
+                };
+
+                dma0: dma-engine@1180000000100 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000100 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+
+                dma1: dma-engine@1180000000108 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000108 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+
+                usbn: usbn@1180068000000 {
+                        compatible = "cavium,octeon-5750-usbn";
+                        reg = <0x11800 0x68000000 0x0 0x1000>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+
+                        usbc@16f0010000000 {
+                                compatible = "cavium,octeon-5750-usbc";
+                                reg = <0x16f00 0x10000000 0x0 0x80000>;
+                                interrupts = <0 56>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts
new file mode 100644
index 000000000..3d0acbb2e
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts
@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+/*
+ * OCTEON 68XX device tree skeleton.
+ *
+ * This device tree is pruned and patched by early boot code before
+ * use.  Because of this, it contains a super-set of the available
+ * devices and properties.
+ */
+/ {
+        compatible = "cavium,octeon-6880";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&ciu2>;
+
+        soc@0 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges; /* Direct mapping */
+
+                ciu2: interrupt-controller@1070100000000 {
+                        compatible = "cavium,octeon-6880-ciu2";
+                        interrupt-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) Controller register (0 or 7)
+                         * 2) Bit within the register (0..63)
+                         */
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x10701 0x00000000 0x0 0x4000000>;
+                };
+
+                gpio: gpio-controller@1070000000800 {
+                        #gpio-cells = <2>;
+                        compatible = "cavium,octeon-3860-gpio";
+                        reg = <0x10700 0x00000800 0x0 0x100>;
+                        gpio-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) GPIO pin number (0..15)
+                         * 2) Triggering (1 - edge rising
+                         *                2 - edge falling
+                         *                4 - level active high
+                         *                8 - level active low)
+                         */
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        /* The GPIO pins connect to 16 consecutive CUI bits */
+                        interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
+                                     <7 4>,  <7 5>,  <7 6>,  <7 7>,
+                                     <7 8>,  <7 9>,  <7 10>, <7 11>,
+                                     <7 12>, <7 13>, <7 14>, <7 15>;
+                };
+
+                smi0: mdio@1180000003800 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003800 0x0 0x40>;
+
+                        phy0: ethernet-phy@6 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <6>;
+                        };
+
+                        phy1: ethernet-phy@1 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy4: ethernet-phy@4 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi1: mdio@1180000003880 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003880 0x0 0x40>;
+
+                        phy41: ethernet-phy@1 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy42: ethernet-phy@2 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy43: ethernet-phy@3 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy44: ethernet-phy@4 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi2: mdio@1180000003900 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003900 0x0 0x40>;
+
+                        phy21: ethernet-phy@1 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy22: ethernet-phy@2 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy23: ethernet-phy@3 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy24: ethernet-phy@4 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi3: mdio@1180000003980 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003980 0x0 0x40>;
+
+                        phy11: ethernet-phy@1 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy12: ethernet-phy@2 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy13: ethernet-phy@3 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy14: ethernet-phy@4 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                mix0: ethernet@1070000100000 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000000 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <0>;
+                        interrupts = <6 40>, <6 32>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy0>;
+                };
+
+                pip: pip@11800a0000000 {
+                        compatible = "cavium,octeon-3860-pip";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+                        interface@4 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x4>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy1>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy2>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy3>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy4>;
+                                };
+                        };
+
+                        interface@3 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x3>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy11>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy12>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy13>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy14>;
+                                };
+                        };
+
+                        interface@2 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x2>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy21>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy22>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy23>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy24>;
+                                };
+                        };
+
+                        interface@1 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x1>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                        };
+
+                        interface@0 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x0>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy41>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy42>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy43>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy44>;
+                                };
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001000 0x0 0x200>;
+                        interrupts = <3 32>;
+                        clock-frequency = <100000>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1337";
+                                reg = <0x68>;
+                        };
+                        tmp@4c {
+                                compatible = "ti,tmp421";
+                                reg = <0x4c>;
+                        };
+                };
+
+                twsi1: i2c@1180000001200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001200 0x0 0x200>;
+                        interrupts = <3 33>;
+                        clock-frequency = <100000>;
+                };
+
+                uart0: serial@1180000000800 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000800 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <3 36>;
+                };
+
+                uart1: serial@1180000000c00 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000c00 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <3 37>;
+                };
+
+                bootbus: bootbus@1180000000000 {
+                        compatible = "cavium,octeon-3860-bootbus";
+                        reg = <0x11800 0x00000000 0x0 0x200>;
+                        /* The chip select number and offset */
+                        #address-cells = <2>;
+                        /* The size of the chip select region */
+                        #size-cells = <1>;
+                        ranges = <0 0  0       0x1f400000  0xc00000>,
+                                 <1 0  0x10000 0x30000000  0>,
+                                 <2 0  0x10000 0x40000000  0>,
+                                 <3 0  0x10000 0x50000000  0>,
+                                 <4 0  0       0x1d020000  0x10000>,
+                                 <5 0  0       0x1d040000  0x10000>,
+                                 <6 0  0       0x1d050000  0x10000>,
+                                 <7 0  0x10000 0x90000000  0>;
+
+                        cavium,cs-config@0 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <0>;
+                                cavium,t-adr  = <10>;
+                                cavium,t-ce   = <50>;
+                                cavium,t-oe   = <50>;
+                                cavium,t-we   = <35>;
+                                cavium,t-rd-hld = <25>;
+                                cavium,t-wr-hld = <35>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <300>;
+                                cavium,t-page   = <25>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@4 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <4>;
+                                cavium,t-adr  = <320>;
+                                cavium,t-ce   = <320>;
+                                cavium,t-oe   = <320>;
+                                cavium,t-we   = <320>;
+                                cavium,t-rd-hld = <320>;
+                                cavium,t-wr-hld = <320>;
+                                cavium,t-pause  = <320>;
+                                cavium,t-wait   = <320>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@5 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <5>;
+                                cavium,t-adr  = <0>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <300>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <300>;
+                                cavium,t-page   = <310>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <16>;
+                        };
+                        cavium,cs-config@6 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <6>;
+                                cavium,t-adr  = <0>;
+                                cavium,t-ce   = <30>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <30>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <30>;
+                                cavium,t-page   = <310>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,wait-mode;
+                                cavium,bus-width = <16>;
+                        };
+
+                        flash0: nor@0,0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "bootloader";
+                                        reg = <0 0x200000>;
+                                        read-only;
+                                };
+                                partition@200000 {
+                                        label = "kernel";
+                                        reg = <0x200000 0x200000>;
+                                };
+                                partition@400000 {
+                                        label = "cramfs";
+                                        reg = <0x400000 0x3fe000>;
+                                };
+                                partition@7fe000 {
+                                        label = "environment";
+                                        reg = <0x7fe000 0x2000>;
+                                        read-only;
+                                };
+                        };
+
+                        led0: led-display@4,0 {
+                                compatible = "avago,hdsp-253x";
+                                reg = <4 0x20 0x20>, <4 0 0x20>;
+                        };
+
+                        compact-flash@5,0 {
+                                compatible = "cavium,ebt3000-compact-flash";
+                                reg = <5 0 0x10000>, <6 0 0x10000>;
+                                cavium,bus-width = <16>;
+                                cavium,true-ide;
+                                cavium,dma-engine-handle = <&dma0>;
+                        };
+                };
+
+                dma0: dma-engine@1180000000100 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000100 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+                dma1: dma-engine@1180000000108 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000108 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+
+                uctl: uctl@118006f000000 {
+                        compatible = "cavium,octeon-6335-uctl";
+                        reg = <0x11800 0x6f000000 0x0 0x100>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+
+                        ehci@16f0000000000 {
+                                compatible = "cavium,octeon-6335-ehci","usb-ehci";
+                                reg = <0x16f00 0x00000000 0x0 0x100>;
+                                interrupts = <3 44>;
+                                big-endian-regs;
+                        };
+                        ohci@16f0000000400 {
+                                compatible = "cavium,octeon-6335-ohci","usb-ohci";
+                                reg = <0x16f00 0x00000400 0x0 0x100>;
+                                interrupts = <3 44>;
+                                big-endian-regs;
+                        };
+                };
+        };
+
+        aliases {
+                mix0 = &mix0;
+                pip = &pip;
+                smi0 = &smi0;
+                smi1 = &smi1;
+                smi2 = &smi2;
+                smi3 = &smi3;
+                twsi0 = &twsi0;
+                twsi1 = &twsi1;
+                uart0 = &uart0;
+                uart1 = &uart1;
+                uctl = &uctl;
+                led0 = &led0;
+                flash0 = &flash0;
+        };
+ };
diff --git a/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts
new file mode 100644
index 000000000..cb219b730
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device tree source for EdgeRouter Lite.
+ *
+ * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
+ */
+
+/include/ "octeon_3xxx.dtsi"
+
+/ {
+        model = "ubnt,e100";
+
+        soc@0 {
+                smi0: mdio@1180000001800 {
+                        phy5: ethernet-phy@5 {
+                                reg = <5>;
+                                compatible = "ethernet-phy-ieee802.3-c22";
+                        };
+                        phy6: ethernet-phy@6 {
+                                reg = <6>;
+                                compatible = "ethernet-phy-ieee802.3-c22";
+                        };
+                        phy7: ethernet-phy@7 {
+                                reg = <7>;
+                                compatible = "ethernet-phy-ieee802.3-c22";
+                        };
+                };
+
+                pip: pip@11800a0000000 {
+                        interface@0 {
+                                ethernet@0 {
+                                        phy-handle = <&phy7>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0x10>;
+                                };
+                                ethernet@1 {
+                                        phy-handle = <&phy6>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0x10>;
+                                };
+                                ethernet@2 {
+                                        phy-handle = <&phy5>;
+                                        rx-delay = <0>;
+                                        tx-delay = <0x10>;
+                                };
+                        };
+                };
+
+                uart0: serial@1180000000800 {
+                        clock-frequency = <500000000>;
+                };
+
+                usbn: usbn@1180068000000 {
+                        refclk-frequency = <12000000>;
+                        refclk-type = "crystal";
+                };
+        };
+
+        aliases {
+                pip = &pip;
+        };
+};
diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile
new file mode 100644
index 000000000..441a3c16e
--- /dev/null
+++ b/arch/mips/boot/dts/img/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON)      += boston.dtb
+
+dtb-$(CONFIG_MACH_PISTACHIO)    += pistachio_marduk.dtb
+obj-$(CONFIG_MACH_PISTACHIO)    += pistachio_marduk.dtb.o
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
new file mode 100644
index 000000000..84328afa3
--- /dev/null
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/clock/boston-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "img,boston";
+
+        chosen {
+                stdout-path = "uart0:115200";
+        };
+
+        aliases {
+                uart0 = &uart0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "img,mips";
+                        reg = <0>;
+                        clocks = <&clk_boston BOSTON_CLK_CPU>;
+                };
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        pci0: pci@10000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x10000000 0x2000000>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+
+                ranges = <0x02000000 0 0x40000000
+                          0x40000000 0 0x40000000>;
+
+                bus-range = <0x00 0xff>;
+
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci0_intc 1>,
+                                <0 0 0 2 &pci0_intc 2>,
+                                <0 0 0 3 &pci0_intc 3>,
+                                <0 0 0 4 &pci0_intc 4>;
+
+                pci0_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+        };
+
+        pci1: pci@12000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x12000000 0x2000000>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+
+                ranges = <0x02000000 0 0x20000000
+                          0x20000000 0 0x20000000>;
+
+                bus-range = <0x00 0xff>;
+
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci1_intc 1>,
+                                <0 0 0 2 &pci1_intc 2>,
+                                <0 0 0 3 &pci1_intc 3>,
+                                <0 0 0 4 &pci1_intc 4>;
+
+                pci1_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+        };
+
+        pci2: pci@14000000 {
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                device_type = "pci";
+                reg = <0x14000000 0x2000000>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+
+                ranges = <0x02000000 0 0x16000000
+                          0x16000000 0 0x100000>;
+
+                bus-range = <0x00 0xff>;
+
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pci2_intc 1>,
+                                <0 0 0 2 &pci2_intc 2>,
+                                <0 0 0 3 &pci2_intc 3>,
+                                <0 0 0 4 &pci2_intc 4>;
+
+                pci2_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+
+                pci2_root@0,0,0 {
+                        compatible = "pci10ee,7021";
+                        reg = <0x00000000 0 0 0 0>;
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+
+                        eg20t_bridge@1,0,0 {
+                                compatible = "pci8086,8800";
+                                reg = <0x00010000 0 0 0 0>;
+
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+
+                                eg20t_phub@2,0,0 {
+                                        compatible = "pci8086,8801";
+                                        reg = <0x00020000 0 0 0 0>;
+                                        intel,eg20t-prefetch = <0>;
+                                };
+
+                                eg20t_mac@2,0,1 {
+                                        compatible = "pci8086,8802";
+                                        reg = <0x00020100 0 0 0 0>;
+                                        phy-reset-gpios = <&eg20t_gpio 6
+                                                           GPIO_ACTIVE_LOW>;
+                                };
+
+                                eg20t_gpio: eg20t_gpio@2,0,2 {
+                                        compatible = "pci8086,8803";
+                                        reg = <0x00020200 0 0 0 0>;
+
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
+                                eg20t_i2c@2,12,2 {
+                                        compatible = "pci8086,8817";
+                                        reg = <0x00026200 0 0 0 0>;
+
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        rtc@68 {
+                                                compatible = "st,m41t81s";
+                                                reg = <0x68>;
+                                        };
+                                };
+                        };
+                };
+        };
+
+        gic: interrupt-controller@16120000 {
+                compatible = "mti,gic";
+                reg = <0x16120000 0x20000>;
+
+                interrupt-controller;
+                #interrupt-cells = <3>;
+
+                timer {
+                        compatible = "mti,gic-timer";
+                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+                        clocks = <&clk_boston BOSTON_CLK_CPU>;
+                };
+        };
+
+        cdmm@16140000 {
+                compatible = "mti,mips-cdmm";
+                reg = <0x16140000 0x8000>;
+        };
+
+        cpc@16200000 {
+                compatible = "mti,mips-cpc";
+                reg = <0x16200000 0x8000>;
+        };
+
+        plat_regs: system-controller@17ffd000 {
+                compatible = "img,boston-platform-regs", "syscon";
+                reg = <0x17ffd000 0x1000>;
+
+                clk_boston: clock {
+                        compatible = "img,boston-clock";
+                        #clock-cells = <1>;
+                };
+        };
+
+        reboot: syscon-reboot {
+                compatible = "syscon-reboot";
+                regmap = <&plat_regs>;
+                offset = <0x10>;
+                mask = <0x10>;
+        };
+
+        uart0: uart@17ffe000 {
+                compatible = "ns16550a";
+                reg = <0x17ffe000 0x1000>;
+                reg-shift = <2>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+                clocks = <&clk_boston BOSTON_CLK_SYS>;
+        };
+
+        lcd: lcd@17fff000 {
+                compatible = "img,boston-lcd";
+                reg = <0x17fff000 0x8>;
+        };
+};
diff --git a/arch/mips/boot/dts/img/pistachio.dtsi b/arch/mips/boot/dts/img/pistachio.dtsi
new file mode 100644
index 000000000..dc3b7909d
--- /dev/null
+++ b/arch/mips/boot/dts/img/pistachio.dtsi
@@ -0,0 +1,920 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
+ * Copyright (C) 2015 Google, Inc.
+ */
+
+#include <dt-bindings/clock/pistachio-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/reset/pistachio-resets.h>
+
+/ {
+        compatible = "img,pistachio";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mti,interaptiv";
+                        reg = <0>;
+                        clocks = <&clk_core CLK_MIPS_PLL>;
+                        clock-names = "cpu";
+                        clock-latency = <1000>;
+                        operating-points = <
+                                /* kHz    uV(dummy) */
+                                546000 1150000
+                                520000 1100000
+                                494000 1000000
+                                468000 950000
+                                442000 900000
+                                416000 800000
+                        >;
+                };
+        };
+
+        i2c0: i2c@18100000 {
+                compatible = "img,scb-i2c";
+                reg = <0x18100000 0x200>;
+                interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_I2C0>,
+                         <&cr_periph SYS_CLK_I2C0>;
+                clock-names = "scb", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_I2C0_DIV>;
+                assigned-clock-rates = <100000000>, <33333334>;
+                status = "disabled";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_pins>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2c1: i2c@18100200 {
+                compatible = "img,scb-i2c";
+                reg = <0x18100200 0x200>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_I2C1>,
+                         <&cr_periph SYS_CLK_I2C1>;
+                clock-names = "scb", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_I2C1_DIV>;
+                assigned-clock-rates = <100000000>, <33333334>;
+                status = "disabled";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_pins>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2c2: i2c@18100400 {
+                compatible = "img,scb-i2c";
+                reg = <0x18100400 0x200>;
+                interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_I2C2>,
+                         <&cr_periph SYS_CLK_I2C2>;
+                clock-names = "scb", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_I2C2_DIV>;
+                assigned-clock-rates = <100000000>, <33333334>;
+                status = "disabled";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_pins>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2c3: i2c@18100600 {
+                compatible = "img,scb-i2c";
+                reg = <0x18100600 0x200>;
+                interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_I2C3>,
+                         <&cr_periph SYS_CLK_I2C3>;
+                clock-names = "scb", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_I2C3_DIV>;
+                assigned-clock-rates = <100000000>, <33333334>;
+                status = "disabled";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c3_pins>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        i2s_in: i2s-in@18100800 {
+                compatible = "img,i2s-in";
+                reg = <0x18100800 0x200>;
+                interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 30 0xffffffff 0>;
+                dma-names = "rx";
+                clocks = <&cr_periph SYS_CLK_I2S_IN>;
+                clock-names = "sys";
+                img,i2s-channels = <6>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s_in_pins>;
+                status = "disabled";
+
+                #sound-dai-cells = <0>;
+        };
+
+        i2s_out: i2s-out@18100a00 {
+                compatible = "img,i2s-out";
+                reg = <0x18100a00 0x200>;
+                interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 23 0xffffffff 0>;
+                dma-names = "tx";
+                clocks = <&cr_periph SYS_CLK_I2S_OUT>,
+                         <&clk_core CLK_I2S>;
+                clock-names = "sys", "ref";
+                assigned-clocks = <&clk_core CLK_I2S_DIV>;
+                assigned-clock-rates = <12288000>;
+                img,i2s-channels = <6>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s_out_pins>;
+                status = "disabled";
+                resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
+                reset-names = "rst";
+                #sound-dai-cells = <0>;
+        };
+
+        parallel_out: parallel-audio-out@18100c00 {
+                compatible = "img,parallel-out";
+                reg = <0x18100c00 0x100>;
+                interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 16 0xffffffff 0>;
+                dma-names = "tx";
+                clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
+                         <&clk_core CLK_AUDIO_DAC>;
+                clock-names = "sys", "ref";
+                assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
+                assigned-clock-rates = <12288000>;
+                status = "disabled";
+                resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
+                reset-names = "rst";
+                #sound-dai-cells = <0>;
+        };
+
+        spdif_out: spdif-out@18100d00 {
+                compatible = "img,spdif-out";
+                reg = <0x18100d00 0x100>;
+                interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 14 0xffffffff 0>;
+                dma-names = "tx";
+                clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
+                         <&clk_core CLK_SPDIF>;
+                clock-names = "sys", "ref";
+                assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
+                assigned-clock-rates = <12288000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spdif_out_pin>;
+                status = "disabled";
+                resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
+                reset-names = "rst";
+                #sound-dai-cells = <0>;
+        };
+
+        spdif_in: spdif-in@18100e00 {
+                compatible = "img,spdif-in";
+                reg = <0x18100e00 0x100>;
+                interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 15 0xffffffff 0>;
+                dma-names = "rx";
+                clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
+                clock-names = "sys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spdif_in_pin>;
+                status = "disabled";
+
+                #sound-dai-cells = <0>;
+        };
+
+        internal_dac: internal-dac {
+                compatible = "img,pistachio-internal-dac";
+                img,cr-top = <&cr_top>;
+                img,voltage-select = <1>;
+
+                #sound-dai-cells = <0>;
+        };
+
+        spfi0: spi@18100f00 {
+                compatible = "img,spfi";
+                reg = <0x18100f00 0x100>;
+                interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
+                clock-names = "sys", "spfi";
+                dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
+                dma-names = "rx", "tx";
+                spfi-max-frequency = <50000000>;
+                status = "disabled";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spfi1: spi@18101000 {
+                compatible = "img,spfi";
+                reg = <0x18101000 0x100>;
+                interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
+                clock-names = "sys", "spfi";
+                dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
+                dma-names = "rx", "tx";
+                img,supports-quad-mode;
+                spfi-max-frequency = <50000000>;
+                status = "disabled";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        pwm: pwm@18101300 {
+                compatible = "img,pistachio-pwm";
+                reg = <0x18101300 0x100>;
+                clocks = <&clk_periph PERIPH_CLK_PWM>,
+                         <&cr_periph SYS_CLK_PWM>;
+                clock-names = "pwm", "sys";
+                img,cr-periph = <&cr_periph>;
+                #pwm-cells = <2>;
+                status = "disabled";
+        };
+
+        uart0: uart@18101400 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18101400 0x100>;
+                interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
+                clock-names = "baudclk", "apb_pclk";
+                assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
+                                  <&clk_core CLK_UART0_DIV>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
+                pinctrl-names = "default";
+                status = "disabled";
+        };
+
+        uart1: uart@18101500 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18101500 0x100>;
+                interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
+                clock-names = "baudclk", "apb_pclk";
+                assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
+                                  <&clk_core CLK_UART1_DIV>;
+                assigned-clock-rates = <114278400>, <1843200>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-0 = <&uart1_pins>;
+                pinctrl-names = "default";
+                status = "disabled";
+        };
+
+        adc: adc@18101600 {
+                compatible = "cosmic,10001-adc";
+                reg = <0x18101600 0x24>;
+                adc-reserved-channels = <0x30>;
+                clocks = <&clk_core CLK_AUX_ADC>;
+                clock-names = "adc";
+                assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
+                                  <&clk_core CLK_AUX_ADC_DIV>;
+                assigned-clock-rates = <100000000>, <1000000>;
+                status = "disabled";
+
+                #io-channel-cells = <1>;
+        };
+
+        pinctrl: pinctrl@18101c00 {
+                compatible = "img,pistachio-system-pinctrl";
+                reg = <0x18101c00 0x400>;
+
+                gpio0: gpio0 {
+                        interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 0 16>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio1: gpio1 {
+                        interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 16 16>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio2: gpio2 {
+                        interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 32 16>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio3: gpio3 {
+                        interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 48 16>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio4: gpio4 {
+                        interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 64 16>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio5: gpio5 {
+                        interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 80 10>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                i2c0_pins: i2c0-pins {
+                        pin_i2c0: i2c0 {
+                                pins = "mfio28", "mfio29";
+                                function = "i2c0";
+                                drive-strength = <4>;
+                        };
+                };
+
+                i2c1_pins: i2c1-pins {
+                        pin_i2c1: i2c1 {
+                                pins = "mfio30", "mfio31";
+                                function = "i2c1";
+                                drive-strength = <4>;
+                        };
+                };
+
+                i2c2_pins: i2c2-pins {
+                        pin_i2c2: i2c2 {
+                                pins = "mfio32", "mfio33";
+                                function = "i2c2";
+                                drive-strength = <4>;
+                        };
+                };
+
+                i2c3_pins: i2c3-pins {
+                        pin_i2c3: i2c3 {
+                                pins = "mfio34", "mfio35";
+                                function = "i2c3";
+                                drive-strength = <4>;
+                        };
+                };
+
+                spim0_pins: spim0-pins {
+                        pin_spim0: spim0 {
+                                pins = "mfio9", "mfio10";
+                                function = "spim0";
+                                drive-strength = <4>;
+                        };
+                        spim0_clk: spim0-clk {
+                                pins = "mfio8";
+                                function = "spim0";
+                                drive-strength = <4>;
+                        };
+                };
+
+                spim0_cs0_alt_pin: spim0-cs0-alt-pin {
+                        spim0-cs0 {
+                                pins = "mfio2";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs1_pin: spim0-cs1-pin {
+                        spim0-cs1 {
+                                pins = "mfio1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs2_pin: spim0-cs2-pin {
+                        spim0-cs2 {
+                                pins = "mfio55";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs2_alt_pin: spim0-cs2-alt-pin {
+                        spim0-cs2 {
+                                pins = "mfio28";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs3_pin: spim0-cs3-pin {
+                        spim0-cs3 {
+                                pins = "mfio56";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs3_alt_pin: spim0-cs3-alt-pin {
+                        spim0-cs3 {
+                                pins = "mfio29";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs4_pin: spim0-cs4-pin {
+                        spim0-cs4 {
+                                pins = "mfio57";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim0_cs4_alt_pin: spim0-cs4-alt-pin {
+                        spim0-cs4 {
+                                pins = "mfio30";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_pins: spim1-pins {
+                        spim1 {
+                                pins = "mfio3", "mfio4", "mfio5";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_quad_pins: spim1-quad-pins {
+                        spim1-quad {
+                                pins = "mfio6", "mfio7";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs0_pin: spim1-cs0-pins {
+                        spim1-cs0 {
+                                pins = "mfio0";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs1_pin: spim1-cs1-pin {
+                        spim1-cs1 {
+                                pins = "mfio1";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs1_alt_pin: spim1-cs1-alt-pin {
+                        spim1-cs1 {
+                                pins = "mfio58";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs2_pin: spim1-cs2-pin {
+                        spim1-cs2 {
+                                pins = "mfio2";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
+                        spim1-cs2 {
+                                pins = "mfio31";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
+                        spim1-cs2 {
+                                pins = "mfio55";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs3_pin: spim1-cs3-pin {
+                        spim1-cs3 {
+                                pins = "mfio56";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                spim1_cs4_pin: spim1-cs4-pin {
+                        spim1-cs4 {
+                                pins = "mfio57";
+                                function = "spim1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                uart0_pins: uart0-pins {
+                        uart0 {
+                                pins = "mfio55", "mfio56";
+                                function = "uart0";
+                                drive-strength = <2>;
+                        };
+                };
+
+                uart0_rts_cts_pins: uart0-rts-cts-pins {
+                        uart0-rts-cts {
+                                pins = "mfio57", "mfio58";
+                                function = "uart0";
+                                drive-strength = <2>;
+                        };
+                };
+
+                uart1_pins: uart1-pins {
+                        uart1 {
+                                pins = "mfio59", "mfio60";
+                                function = "uart1";
+                                drive-strength = <2>;
+                        };
+                };
+
+                uart1_rts_cts_pins: uart1-rts-cts-pins {
+                        uart1-rts-cts {
+                                  pins = "mfio1", "mfio2";
+                                  function = "uart1";
+                                  drive-strength = <2>;
+                        };
+                };
+
+                enet_pins: enet-pins {
+                        pin_enet: enet {
+                                pins = "mfio63", "mfio64", "mfio65", "mfio66",
+                                       "mfio67", "mfio68", "mfio69", "mfio70";
+                                function = "eth";
+                                slew-rate = <1>;
+                                drive-strength = <4>;
+                        };
+                        pin_enet_phy_clk: enet-phy-clk {
+                                pins = "mfio71";
+                                function = "eth";
+                                slew-rate = <1>;
+                                drive-strength = <8>;
+                        };
+                };
+
+                sdhost_pins: sdhost-pins {
+                        pin_sdhost_clk: sdhost-clk {
+                                pins = "mfio15";
+                                function = "sdhost";
+                                slew-rate = <1>;
+                                drive-strength = <4>;
+                        };
+                        pin_sdhost_cmd: sdhost-cmd {
+                                pins = "mfio16";
+                                function = "sdhost";
+                                slew-rate = <1>;
+                                drive-strength = <4>;
+                        };
+                        pin_sdhost_data: sdhost-data {
+                                pins = "mfio17", "mfio18", "mfio19", "mfio20",
+                                       "mfio21", "mfio22", "mfio23", "mfio24";
+                                function = "sdhost";
+                                slew-rate = <1>;
+                                drive-strength = <4>;
+                        };
+                        pin_sdhost_power_select: sdhost-power-select {
+                                pins = "mfio25";
+                                function = "sdhost";
+                                slew-rate = <1>;
+                                drive-strength = <2>;
+                        };
+                        pin_sdhost_card_detect: sdhost-card-detect {
+                                pins = "mfio26";
+                                function = "sdhost";
+                                drive-strength = <2>;
+                        };
+                        pin_sdhost_write_protect: sdhost-write-protect {
+                                pins = "mfio27";
+                                function = "sdhost";
+                                drive-strength = <2>;
+                        };
+                };
+
+                ir_pin: ir-pin {
+                        ir-data {
+                                pins = "mfio72";
+                                function = "ir";
+                                drive-strength = <2>;
+                        };
+                };
+
+                pwmpdm0_pin: pwmpdm0-pin {
+                        pwmpdm0 {
+                                pins = "mfio73";
+                                function = "pwmpdm";
+                                drive-strength = <2>;
+                        };
+                };
+
+                pwmpdm1_pin: pwmpdm1-pin {
+                        pwmpdm1 {
+                                pins = "mfio74";
+                                function = "pwmpdm";
+                                drive-strength = <2>;
+                        };
+                };
+
+                pwmpdm2_pin: pwmpdm2-pin {
+                        pwmpdm2 {
+                                pins = "mfio75";
+                                function = "pwmpdm";
+                                drive-strength = <2>;
+                        };
+                };
+
+                pwmpdm3_pin: pwmpdm3-pin {
+                        pwmpdm3 {
+                                pins = "mfio76";
+                                function = "pwmpdm";
+                                drive-strength = <2>;
+                        };
+                };
+
+                dac_clk_pin: dac-clk-pin {
+                        pin_dac_clk: dac-clk {
+                                pins = "mfio45";
+                                function = "i2s_dac_clk";
+                                drive-strength = <4>;
+                        };
+                };
+
+                i2s_mclk_pin: i2s-mclk-pin {
+                        pin_i2s_mclk: i2s-mclk {
+                                pins = "mfio36";
+                                function = "i2s_out";
+                                drive-strength = <4>;
+                        };
+                };
+
+                spdif_out_pin: spdif-out-pin {
+                        spdif-out {
+                                pins = "mfio61";
+                                function = "spdif_out";
+                                slew-rate = <1>;
+                                drive-strength = <2>;
+                        };
+                };
+
+                spdif_in_pin: spdif-in-pin {
+                        spdif-in {
+                                pins = "mfio62";
+                                function = "spdif_in";
+                                drive-strength = <2>;
+                        };
+                };
+
+                i2s_out_pins: i2s-out-pins {
+                        pins_i2s_out_clk: i2s-out-clk {
+                                pins = "mfio37", "mfio38";
+                                function = "i2s_out";
+                                drive-strength = <4>;
+                        };
+                        pins_i2s_out: i2s-out {
+                                pins = "mfio39", "mfio40",
+                                       "mfio41", "mfio42",
+                                       "mfio43", "mfio44";
+                                function = "i2s_out";
+                                drive-strength = <2>;
+                        };
+                };
+
+                i2s_in_pins: i2s-in-pins {
+                        i2s-in {
+                                pins = "mfio47", "mfio48", "mfio49",
+                                       "mfio50", "mfio51", "mfio52",
+                                       "mfio53", "mfio54";
+                                function = "i2s_in";
+                                drive-strength = <2>;
+                        };
+                };
+        };
+
+        timer: timer@18102000 {
+                compatible = "img,pistachio-gptimer";
+                reg = <0x18102000 0x100>;
+                interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
+                         <&cr_periph SYS_CLK_TIMER>;
+                clock-names = "fast", "sys";
+                img,cr-periph = <&cr_periph>;
+        };
+
+        wdt: watchdog@18102100 {
+                compatible = "img,pdc-wdt";
+                reg = <0x18102100 0x100>;
+                interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
+                clock-names = "wdt", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_WD_DIV>;
+                assigned-clock-rates = <4000000>, <32768>;
+        };
+
+        ir: ir@18102200 {
+                compatible = "img,ir-rev1";
+                reg = <0x18102200 0x100>;
+                interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
+                clock-names = "core", "sys";
+                assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
+                                  <&clk_periph PERIPH_CLK_IR_DIV>;
+                assigned-clock-rates = <4000000>, <32768>;
+                pinctrl-0 = <&ir_pin>;
+                pinctrl-names = "default";
+                status = "disabled";
+        };
+
+        usb: usb@18120000 {
+                compatible = "snps,dwc2";
+                reg = <0x18120000 0x1c000>;
+                interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
+                phys = <&usb_phy>;
+                phy-names = "usb2-phy";
+                g-tx-fifo-size = <256 256 256 256>;
+                status = "disabled";
+        };
+
+        enet: ethernet@18140000 {
+                compatible = "snps,dwmac";
+                reg = <0x18140000 0x2000>;
+                interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "macirq";
+                clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
+                clock-names = "stmmaceth", "pclk";
+                assigned-clocks = <&clk_core CLK_ENET_MUX>,
+                                  <&clk_core CLK_ENET_DIV>;
+                assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
+                assigned-clock-rates = <0>, <50000000>;
+                pinctrl-0 = <&enet_pins>;
+                pinctrl-names = "default";
+                phy-mode = "rmii";
+                status = "disabled";
+        };
+
+        sdhost: mmc@18142000 {
+                compatible = "img,pistachio-dw-mshc";
+                reg = <0x18142000 0x400>;
+                interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
+                clock-names = "ciu", "biu";
+                pinctrl-0 = <&sdhost_pins>;
+                pinctrl-names = "default";
+                fifo-depth = <0x20>;
+                clock-frequency = <50000000>;
+                bus-width = <8>;
+                cap-mmc-highspeed;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sram: sram@1b000000 {
+                compatible = "mmio-sram";
+                reg = <0x1b000000 0x10000>;
+        };
+
+        mdc: dma-controller@18143000 {
+                compatible = "img,pistachio-mdc-dma";
+                reg = <0x18143000 0x1000>;
+                interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cr_periph SYS_CLK_MDC>;
+                clock-names = "sys";
+
+                img,max-burst-multiplier = <16>;
+                img,cr-periph = <&cr_periph>;
+
+                #dma-cells = <3>;
+        };
+
+        clk_core: clk@18144000 {
+                compatible = "img,pistachio-clk", "syscon";
+                clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
+                         <&cr_top EXT_CLK_ENET_IN>;
+                clock-names = "xtal", "audio_refclk_ext_gate",
+                              "ext_enet_in_gate";
+                reg = <0x18144000 0x800>;
+                #clock-cells = <1>;
+        };
+
+        clk_periph: clk@18144800 {
+                compatible = "img,pistachio-clk-periph";
+                reg = <0x18144800 0x1000>;
+                clocks = <&clk_core CLK_PERIPH_SYS>;
+                clock-names = "periph_sys_core";
+                #clock-cells = <1>;
+        };
+
+        cr_periph: clk@18148000 {
+                compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
+                reg = <0x18148000 0x1000>;
+                clocks = <&clk_periph PERIPH_CLK_SYS>;
+                clock-names = "sys";
+                #clock-cells = <1>;
+
+                pistachio_reset: reset-controller {
+                        compatible = "img,pistachio-reset";
+                        #reset-cells = <1>;
+                };
+        };
+
+        cr_top: clk@18149000 {
+                compatible = "img,pistachio-cr-top", "syscon";
+                reg = <0x18149000 0x200>;
+                #clock-cells = <1>;
+        };
+
+        hash: hash@18149600 {
+                compatible = "img,hash-accelerator";
+                reg = <0x18149600 0x100>, <0x18101100 0x4>;
+                interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
+                dmas = <&mdc 8 0xffffffff 0>;
+                dma-names = "tx";
+                clocks = <&cr_periph SYS_CLK_HASH>,
+                         <&clk_periph PERIPH_CLK_ROM>;
+                clock-names = "sys", "hash";
+        };
+
+        gic: interrupt-controller@1bdc0000 {
+                compatible = "mti,gic";
+                reg = <0x1bdc0000 0x20000>;
+
+                interrupt-controller;
+                #interrupt-cells = <3>;
+
+                timer {
+                        compatible = "mti,gic-timer";
+                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+                        clocks = <&clk_core CLK_MIPS>;
+                };
+        };
+
+        usb_phy: usb-phy {
+                compatible = "img,pistachio-usb-phy";
+                clocks = <&clk_core CLK_USB_PHY>;
+                clock-names = "usb_phy";
+                assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
+                assigned-clock-rates = <50000000>;
+                img,refclk = <0x2>;
+                img,cr-top = <&cr_top>;
+                #phy-cells = <0>;
+        };
+
+        xtal: xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <52000000>;
+                clock-output-names = "xtal";
+        };
+};
diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts
new file mode 100644
index 000000000..bf69da96d
--- /dev/null
+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
+ *
+ * IMG Marduk board is also known as Creator Ci40.
+ */
+
+/dts-v1/;
+
+#include "pistachio.dtsi"
+
+/ {
+        model = "IMG Marduk (Creator Ci40)";
+        compatible = "img,pistachio-marduk", "img,pistachio";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                ethernet0 = &enet;
+                spi0 = &spfi0;
+                spi1 = &spfi1;
+        };
+
+        chosen {
+                bootargs = "root=/dev/sda1 rootwait ro lpj=723968";
+                stdout-path = "serial1:115200";
+        };
+
+        memory {
+                device_type = "memory";
+                reg =  <0x00000000 0x10000000>;
+        };
+
+        reg_1v8: fixed-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "aux_adc_vref";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-boot-on;
+        };
+
+        internal_dac_supply: internal-dac-supply {
+                compatible = "regulator-fixed";
+                regulator-name = "internal_dac_supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        leds {
+                compatible = "pwm-leds";
+                heartbeat {
+                        label = "marduk:red:heartbeat";
+                        pwms = <&pwm 3 300000>;
+                        max-brightness = <255>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        keys {
+                compatible = "gpio-keys";
+                button@1 {
+                        label = "Button 1";
+                        linux,code = <0x101>; /* BTN_1 */
+                        gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+                };
+                button@2 {
+                        label = "Button 2";
+                        linux,code = <0x102>; /* BTN_2 */
+                        gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&internal_dac {
+        VDD-supply = <&internal_dac_supply>;
+};
+
+&spfi1 {
+        status = "okay";
+
+        pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
+                    <&spim1_cs1_pin>;
+        pinctrl-names = "default";
+        cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
+
+        flash@0 {
+                compatible = "spansion,s25fl016k", "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <50000000>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+        assigned-clock-rates = <114278400>, <1843200>;
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb {
+        status = "okay";
+};
+
+&enet {
+        status = "okay";
+};
+
+&pin_enet {
+        drive-strength = <2>;
+};
+
+&pin_enet_phy_clk {
+        drive-strength = <2>;
+};
+
+&sdhost {
+        status = "okay";
+        bus-width = <4>;
+        disable-wp;
+};
+
+&pin_sdhost_cmd {
+        drive-strength = <2>;
+};
+
+&pin_sdhost_data {
+        drive-strength = <2>;
+};
+
+&pwm {
+        status = "okay";
+
+        pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
+                    <&pwmpdm3_pin>;
+        pinctrl-names = "default";
+};
+
+&adc {
+        status = "okay";
+        vref-supply = <&reg_1v8>;
+        adc-reserved-channels = <0x10>;
+};
+
+&i2c2 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tpm@20 {
+                compatible = "infineon,slb9645tt";
+                reg = <0x20>;
+        };
+
+};
+
+&i2c3 {
+        status = "okay";
+        clock-frequency = <400000>;
+};
diff --git a/arch/mips/boot/dts/ingenic/Makefile b/arch/mips/boot/dts/ingenic/Makefile
new file mode 100644
index 000000000..54aa0c4e6
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_JZ4740_QI_LB60)    += qi_lb60.dtb
+dtb-$(CONFIG_JZ4740_RS90)       += rs90.dtb
+dtb-$(CONFIG_JZ4770_GCW0)       += gcw0.dtb
+dtb-$(CONFIG_JZ4780_CI20)       += ci20.dtb
+dtb-$(CONFIG_X1000_CU1000_NEO)  += cu1000-neo.dtb
+dtb-$(CONFIG_X1830_CU1830_NEO)  += cu1830-neo.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
new file mode 100644
index 000000000..75f5bfbf2
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4780.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/regulator/active-semi,8865-regulator.h>
+
+/ {
+        compatible = "img,ci20", "ingenic,jz4780";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial3 = &uart3;
+                serial4 = &uart4;
+        };
+
+        chosen {
+                stdout-path = &uart4;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x10000000
+                       0x30000000 0x30000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                sw1 {
+                        label = "ci20:sw1";
+                        linux,code = <KEY_F13>;
+                        gpios = <&gpd 17 GPIO_ACTIVE_HIGH>;
+                        wakeup-source;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led0 {
+                        label = "ci20:red:led0";
+                        gpios = <&gpc 3 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "none";
+                };
+
+                led1 {
+                        label = "ci20:red:led1";
+                        gpios = <&gpc 2 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "nand-disk";
+                };
+
+                led2 {
+                        label = "ci20:red:led2";
+                        gpios = <&gpc 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu1";
+                };
+
+                led3 {
+                        label = "ci20:red:led3";
+                        gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu0";
+                };
+        };
+
+        eth0_power: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "eth0_power";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
+                enable-active-high;
+        };
+
+        ir: ir {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
+        };
+
+        wlan0_power: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "wlan0_power";
+                gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
+                enable-active-high;
+        };
+};
+
+&ext {
+        clock-frequency = <48000000>;
+};
+
+&mmc0 {
+        status = "okay";
+
+        bus-width = <4>;
+        max-frequency = <50000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc0>;
+
+        cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
+};
+
+&mmc1 {
+        status = "okay";
+
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        non-removable;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc1>;
+
+        brcmf: wifi@1 {
+/*              reg = <4>;*/
+                compatible = "brcm,bcm4330-fmac";
+                vcc-supply = <&wlan0_power>;
+                device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
+                shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart0>;
+};
+
+&uart1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart1>;
+};
+
+&uart2 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart2>;
+        uart-has-rtscts;
+
+        bluetooth {
+                compatible = "brcm,bcm4330-bt";
+                reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
+                vcc-supply = <&wlan0_power>;
+                device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
+                host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
+                shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&uart3 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart3>;
+};
+
+&uart4 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart4>;
+};
+
+&i2c0 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c0>;
+
+        clock-frequency = <400000>;
+
+        act8600: act8600@5a {
+                compatible = "active-semi,act8600";
+                reg = <0x5a>;
+                status = "okay";
+
+                regulators {
+                        vddcore: SUDCDC1 {
+                                regulator-name = "DCDC_REG1";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
+                        vddmem: SUDCDC2 {
+                                regulator-name = "DCDC_REG2";
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+                        vcc_33: SUDCDC3 {
+                                regulator-name = "DCDC_REG3";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vcc_50: SUDCDC4 {
+                                regulator-name = "SUDCDC_REG4";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                regulator-always-on;
+                        };
+                        vcc_25: LDO_REG5 {
+                                regulator-name = "LDO_REG5";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+                        wifi_io: LDO_REG6 {
+                                regulator-name = "LDO_REG6";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+                        vcc_28: LDO_REG7 {
+                                regulator-name = "LDO_REG7";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+                        vcc_15: LDO_REG8 {
+                                regulator-name = "LDO_REG8";
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+                        vrtc_18: LDO_REG9 {
+                                regulator-name = "LDO_REG9";
+                                /* Despite the datasheet stating 3.3V
+                                 * for REG9 and the driver expecting that,
+                                 * REG9 outputs 1.8V.
+                                 * Likely the CI20 uses a proprietary
+                                 * factory programmed chip variant.
+                                 * Since this is a simple on/off LDO the
+                                 * exact values do not matter.
+                                 */
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vcc_11: LDO_REG10 {
+                                regulator-name = "LDO_REG10";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&i2c1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c1>;
+
+};
+
+&i2c2 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c2>;
+
+};
+
+&i2c3 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c3>;
+
+};
+
+&i2c4 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c4>;
+
+        clock-frequency = <400000>;
+
+                rtc@51 {
+                        compatible = "nxp,pcf8563";
+                        reg = <0x51>;
+
+                        interrupt-parent = <&gpf>;
+                        interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+                };
+};
+
+&nemc {
+        status = "okay";
+
+        nandc: nand-controller@1 {
+                compatible = "ingenic,jz4780-nand";
+                reg = <1 0 0x1000000>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ingenic,bch-controller = <&bch>;
+
+                ingenic,nemc-tAS = <10>;
+                ingenic,nemc-tAH = <5>;
+                ingenic,nemc-tBP = <10>;
+                ingenic,nemc-tAW = <15>;
+                ingenic,nemc-tSTRV = <100>;
+
+                /*
+                 * Only CLE/ALE are needed for the devices that are connected, rather
+                 * than the full address line set.
+                 */
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_nemc>;
+
+                nand@1 {
+                        reg = <1>;
+
+                        nand-ecc-step-size = <1024>;
+                        nand-ecc-strength = <24>;
+                        nand-ecc-mode = "hw";
+                        nand-on-flash-bbt;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pins_nemc_cs1>;
+
+                        partitions {
+                                compatible = "fixed-partitions";
+                                #address-cells = <2>;
+                                #size-cells = <2>;
+
+                                partition@0 {
+                                        label = "u-boot-spl";
+                                        reg = <0x0 0x0 0x0 0x800000>;
+                                };
+
+                                partition@800000 {
+                                        label = "u-boot";
+                                        reg = <0x0 0x800000 0x0 0x200000>;
+                                };
+
+                                partition@a00000 {
+                                        label = "u-boot-env";
+                                        reg = <0x0 0xa00000 0x0 0x200000>;
+                                };
+
+                                partition@c00000 {
+                                        label = "boot";
+                                        reg = <0x0 0xc00000 0x0 0x4000000>;
+                                };
+
+                                partition@4c00000 {
+                                        label = "system";
+                                        reg = <0x0 0x4c00000 0x1 0xfb400000>;
+                                };
+                        };
+                };
+        };
+
+        dm9000@6 {
+                compatible = "davicom,dm9000";
+                davicom,no-eeprom;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_nemc_cs6>;
+
+                reg = <6 0 1   /* addr */
+                       6 2 1>; /* data */
+
+                ingenic,nemc-tAS = <15>;
+                ingenic,nemc-tAH = <10>;
+                ingenic,nemc-tBP = <20>;
+                ingenic,nemc-tAW = <50>;
+                ingenic,nemc-tSTRV = <100>;
+
+                reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+                vcc-supply = <&eth0_power>;
+
+                interrupt-parent = <&gpe>;
+                interrupts = <19 4>;
+
+                nvmem-cells = <&eth0_addr>;
+                nvmem-cell-names = "mac-address";
+        };
+};
+
+&bch {
+        status = "okay";
+};
+
+&pinctrl {
+        pins_uart0: uart0 {
+                function = "uart0";
+                groups = "uart0-data";
+                bias-disable;
+        };
+
+        pins_uart1: uart1 {
+                function = "uart1";
+                groups = "uart1-data";
+                bias-disable;
+        };
+
+        pins_uart2: uart2 {
+                function = "uart2";
+                groups = "uart2-data", "uart2-hwflow";
+                bias-disable;
+        };
+
+        pins_uart3: uart3 {
+                function = "uart3";
+                groups = "uart3-data", "uart3-hwflow";
+                bias-disable;
+        };
+
+        pins_uart4: uart4 {
+                function = "uart4";
+                groups = "uart4-data";
+                bias-disable;
+        };
+
+        pins_i2c0: i2c0 {
+                function = "i2c0";
+                groups = "i2c0-data";
+                bias-disable;
+        };
+
+        pins_i2c1: i2c1 {
+                function = "i2c1";
+                groups = "i2c1-data";
+                bias-disable;
+        };
+
+        pins_i2c2: i2c2 {
+                function = "i2c2";
+                groups = "i2c2-data";
+                bias-disable;
+        };
+
+        pins_i2c3: i2c3 {
+                function = "i2c3";
+                groups = "i2c3-data";
+                bias-disable;
+        };
+
+        pins_i2c4: i2c4 {
+                function = "i2c4";
+                groups = "i2c4-data-e";
+                bias-disable;
+        };
+
+        pins_nemc: nemc {
+                function = "nemc";
+                groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
+                bias-disable;
+        };
+
+        pins_nemc_cs1: nemc-cs1 {
+                function = "nemc-cs1";
+                groups = "nemc-cs1";
+                bias-disable;
+        };
+
+        pins_nemc_cs6: nemc-cs6 {
+                function = "nemc-cs6";
+                groups = "nemc-cs6";
+                bias-disable;
+        };
+
+        pins_mmc0: mmc0 {
+                function = "mmc0";
+                groups = "mmc0-1bit-e", "mmc0-4bit-e";
+                bias-disable;
+        };
+
+        pins_mmc1: mmc1 {
+                function = "mmc1";
+                groups = "mmc1-1bit-d", "mmc1-4bit-d";
+                bias-disable;
+        };
+};
+
+&tcu {
+        /* 3 MHz for the system timer and clocksource */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+        assigned-clock-rates = <3000000>, <3000000>;
+};
diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
new file mode 100644
index 000000000..22a1066d6
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "x1000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        compatible = "yna,cu1000-neo", "ingenic,x1000e";
+        model = "YSH & ATIL General Board CU1000-Neo";
+
+        aliases {
+                serial2 = &uart2;
+        };
+
+        chosen {
+                stdout-path = "serial2:115200n8";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x04000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led-0 {
+                        gpios = <&gpb 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        wlan_pwrseq: msc1-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+
+                reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
+                post-power-on-delay-ms = <200>;
+        };
+};
+
+&exclk {
+        clock-frequency = <24000000>;
+};
+
+&tcu {
+        /* 1500 kHz for the system timer and clocksource */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+        assigned-clock-rates = <1500000>, <1500000>;
+
+        /* Use channel #0 for the system timer channel #2 for the clocksource */
+        ingenic,pwm-channels-mask = <0xfa>;
+};
+
+&uart2 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart2>;
+};
+
+&i2c0 {
+        status = "okay";
+
+        clock-frequency = <400000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c0>;
+
+        ads7830: adc@48 {
+                compatible = "ti,ads7830";
+                reg = <0x48>;
+        };
+};
+
+&msc0 {
+        status = "okay";
+
+        bus-width = <8>;
+        max-frequency = <50000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_msc0>;
+
+        non-removable;
+};
+
+&msc1 {
+        status = "okay";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        bus-width = <4>;
+        max-frequency = <50000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_msc1>;
+
+        non-removable;
+
+        mmc-pwrseq = <&wlan_pwrseq>;
+
+        ap6212a: wifi@1 {
+                compatible = "brcm,bcm4329-fmac";
+                reg = <1>;
+
+                interrupt-parent = <&gpc>;
+                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+                interrupt-names = "host-wake";
+
+                brcm,drive-strength = <10>;
+        };
+};
+
+&mac {
+        status = "okay";
+
+        phy-mode = "rmii";
+        phy-handle = <&lan8720a>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mac>;
+
+        snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 30000>;
+};
+
+&mdio {
+        status = "okay";
+
+        lan8720a: ethernet-phy@0 {
+                compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+};
+
+&pinctrl {
+        pins_uart2: uart2 {
+                function = "uart2";
+                groups = "uart2-data-d";
+                bias-pull-up;
+        };
+
+        pins_i2c0: i2c0 {
+                function = "i2c0";
+                groups = "i2c0-data";
+                bias-pull-up;
+        };
+
+        pins_msc0: msc0 {
+                function = "mmc0";
+                groups = "mmc0-1bit", "mmc0-4bit", "mmc0-8bit";
+                bias-disable;
+        };
+
+        pins_msc1: msc1 {
+                function = "mmc1";
+                groups = "mmc1-1bit", "mmc1-4bit";
+                bias-disable;
+        };
+
+        pins_mac: mac {
+                function = "mac";
+                groups = "mac";
+                bias-disable;
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
new file mode 100644
index 000000000..640f96c00
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "x1830.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        compatible = "yna,cu1830-neo", "ingenic,x1830";
+        model = "YSH & ATIL General Board CU1830-Neo";
+
+        aliases {
+                serial1 = &uart1;
+        };
+
+        chosen {
+                stdout-path = "serial1:115200n8";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x08000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led-0 {
+                        gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        wlan_pwrseq: msc1-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+
+                reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
+                post-power-on-delay-ms = <200>;
+        };
+};
+
+&exclk {
+        clock-frequency = <24000000>;
+};
+
+&tcu {
+        /* 1500 kHz for the system timer and clocksource */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+        assigned-clock-rates = <1500000>, <1500000>;
+
+        /* Use channel #0 for the system timer channel #2 for the clocksource */
+        ingenic,pwm-channels-mask = <0xfa>;
+};
+
+&uart1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart1>;
+};
+
+&i2c0 {
+        status = "okay";
+
+        clock-frequency = <400000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_i2c0>;
+
+        ads7830: adc@48 {
+                compatible = "ti,ads7830";
+                reg = <0x48>;
+        };
+};
+
+&msc0 {
+        status = "okay";
+
+        bus-width = <4>;
+        max-frequency = <50000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_msc0>;
+
+        non-removable;
+};
+
+&msc1 {
+        status = "okay";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        bus-width = <4>;
+        max-frequency = <50000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_msc1>;
+
+        non-removable;
+
+        mmc-pwrseq = <&wlan_pwrseq>;
+
+        ap6212a: wifi@1 {
+                compatible = "brcm,bcm4329-fmac";
+                reg = <1>;
+
+                interrupt-parent = <&gpc>;
+                interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+                interrupt-names = "host-wake";
+
+                brcm,drive-strength = <10>;
+        };
+};
+
+&mac {
+        status = "okay";
+
+        phy-mode = "rmii";
+        phy-handle = <&ip101gr>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mac>;
+
+        snps,reset-gpio = <&gpb 28 GPIO_ACTIVE_LOW>; /* PB28 */
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 30000>;
+};
+
+&mdio {
+        status = "okay";
+
+        ip101gr: ethernet-phy@0 {
+                compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+};
+
+&pinctrl {
+        pins_uart1: uart1 {
+                function = "uart1";
+                groups = "uart1-data";
+                bias-pull-up;
+        };
+
+        pins_i2c0: i2c0 {
+                function = "i2c0";
+                groups = "i2c0-data";
+                bias-pull-up;
+        };
+
+        pins_msc0: msc0 {
+                function = "mmc0";
+                groups = "mmc0-1bit", "mmc0-4bit";
+                bias-disable;
+        };
+
+        pins_msc1: msc1 {
+                function = "mmc1";
+                groups = "mmc1-1bit", "mmc1-4bit";
+                bias-disable;
+        };
+
+        pins_mac: mac {
+                function = "mac";
+                groups = "mac";
+                bias-disable;
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
new file mode 100644
index 000000000..bc72304a2
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4770.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/adc/ingenic,adc.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        compatible = "gcw,zero", "ingenic,jz4770";
+        model = "GCW Zero";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+
+        memory: memory {
+                device_type = "memory";
+                reg = <0x0 0x10000000>,
+                      <0x30000000 0x10000000>;
+        };
+
+        chosen {
+                stdout-path = "serial2:57600n8";
+        };
+
+        vcc: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc";
+
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        mmc1_power: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc1_vcc";
+                gpio = <&gpe 9 0>;
+
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc>;
+        };
+
+        headphones_amp: analog-amplifier@0 {
+                compatible = "simple-audio-amplifier";
+                enable-gpios = <&gpf 3 GPIO_ACTIVE_LOW>;
+                enable-delay-ms = <50>;
+
+                VCC-supply = <&ldo5>;
+                sound-name-prefix = "Headphones Amp";
+        };
+
+        speaker_amp: analog-amplifier@1 {
+                compatible = "simple-audio-amplifier";
+                enable-gpios = <&gpf 20 GPIO_ACTIVE_HIGH>;
+
+                VCC-supply = <&ldo5>;
+                sound-name-prefix = "Speaker Amp";
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,name = "gcw0-audio";
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,widgets =
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphones",
+                        "Line", "FM Radio",
+                        "Microphone", "Built-in Mic";
+                simple-audio-card,routing =
+                        "Headphones Amp INL", "LHPOUT",
+                        "Headphones Amp INR", "RHPOUT",
+                        "Headphones", "Headphones Amp OUTL",
+                        "Headphones", "Headphones Amp OUTR",
+                        "Speaker Amp INL", "LOUT",
+                        "Speaker Amp INR", "ROUT",
+                        "Speaker", "Speaker Amp OUTL",
+                        "Speaker", "Speaker Amp OUTR",
+                        "LLINEIN", "FM Radio",
+                        "RLINEIN", "FM Radio",
+                        "Built-in Mic", "MICBIAS",
+                        "MIC1P", "Built-in Mic",
+                        "MIC1N", "Built-in Mic";
+                simple-audio-card,pin-switches = "Speaker", "Headphones";
+
+                simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>;
+                simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>;
+
+                simple-audio-card,bitclock-master = <&dai_codec>;
+                simple-audio-card,frame-master = <&dai_codec>;
+
+                dai_cpu: simple-audio-card,cpu {
+                        sound-dai = <&aic>;
+                };
+
+                dai_codec: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                };
+        };
+
+        rumble {
+                compatible = "pwm-vibrator";
+                pwms = <&pwm 4 2000000 0>;
+                pwm-names = "enable";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_pwm4>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 1 40000 0>;
+                power-supply = <&vcc>;
+
+                brightness-levels = <0 16 32 48 64 80 96 112 128
+                                     144 160 176 192 208 224 240 255>;
+                default-brightness-level = <12>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_pwm1>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                autorepeat;
+
+                button@0 {
+                        label = "D-pad up";
+                        linux,code = <KEY_UP>;
+                        linux,can-disable;
+                        gpios = <&gpe 21 GPIO_ACTIVE_LOW>;
+                };
+
+                button@1 {
+                        label = "D-pad down";
+                        linux,code = <KEY_DOWN>;
+                        linux,can-disable;
+                        gpios = <&gpe 25 GPIO_ACTIVE_LOW>;
+                };
+
+                button@2 {
+                        label = "D-pad left";
+                        linux,code = <KEY_LEFT>;
+                        linux,can-disable;
+                        gpios = <&gpe 23 GPIO_ACTIVE_LOW>;
+                };
+
+                button@3 {
+                        label = "D-pad right";
+                        linux,code = <KEY_RIGHT>;
+                        linux,can-disable;
+                        gpios = <&gpe 24 GPIO_ACTIVE_LOW>;
+                };
+
+                button@4 {
+                        label = "Button A";
+                        linux,code = <KEY_LEFTCTRL>;
+                        linux,can-disable;
+                        gpios = <&gpe 29 GPIO_ACTIVE_LOW>;
+                };
+
+                button@5 {
+                        label = "Button B";
+                        linux,code = <KEY_LEFTALT>;
+                        linux,can-disable;
+                        gpios = <&gpe 20 GPIO_ACTIVE_LOW>;
+                };
+
+                button@6 {
+                        label = "Button Y";
+                        linux,code = <KEY_SPACE>;
+                        linux,can-disable;
+                        gpios = <&gpe 27 GPIO_ACTIVE_LOW>;
+                };
+
+                button@7 {
+                        label = "Button X";
+                        linux,code = <KEY_LEFTSHIFT>;
+                        linux,can-disable;
+                        gpios = <&gpe 28 GPIO_ACTIVE_LOW>;
+                };
+
+                button@8 {
+                        label = "Left shoulder button";
+                        linux,code = <KEY_TAB>;
+                        linux,can-disable;
+                        gpios = <&gpb 20 GPIO_ACTIVE_LOW>;
+                };
+
+                button@9 {
+                        label = "Right shoulder button";
+                        linux,code = <KEY_BACKSPACE>;
+                        linux,can-disable;
+                        gpios = <&gpe 26 GPIO_ACTIVE_LOW>;
+                };
+
+                button@10 {
+                        label = "Start button";
+                        linux,code = <KEY_ENTER>;
+                        linux,can-disable;
+                        gpios = <&gpb 21 GPIO_ACTIVE_LOW>;
+                };
+
+                button@11 {
+                        label = "Select button";
+                        linux,code = <KEY_ESC>;
+                        linux,can-disable;
+                        /*
+                         * This is the only button that is active high,
+                         * since it doubles as BOOT_SEL1.
+                         */
+                        gpios = <&gpd 18 GPIO_ACTIVE_HIGH>;
+                };
+
+                button@12 {
+                        label = "Power slider";
+                        linux,code = <KEY_POWER>;
+                        linux,can-disable;
+                        gpios = <&gpa 30 GPIO_ACTIVE_LOW>;
+                        wakeup-source;
+                };
+
+                button@13 {
+                        label = "Power hold";
+                        linux,code = <KEY_PAUSE>;
+                        linux,can-disable;
+                        gpios = <&gpf 11 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        i2c3: i2c-controller@3 {
+                compatible = "i2c-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sda-gpios = <&gpd 5 GPIO_ACTIVE_HIGH>;
+                scl-gpios = <&gpd 4 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>; /* 250 kHz */
+
+                act8600: pmic@5a {
+                        compatible = "active-semi,act8600";
+                        reg = <0x5a>;
+
+                        regulators {
+                                /* USB OTG */
+                                otg_vbus: SUDCDC_REG4 {
+                                        /*
+                                         * 5.3V instead of 5.0V to compensate
+                                         * for the voltage drop of a diode
+                                         * between the regulator and the
+                                         * connector.
+                                         */
+                                        regulator-min-microvolt = <5300000>;
+                                        regulator-max-microvolt = <5300000>;
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /*
+                                 * When this is off, there is no sound, but also
+                                 * no USB networking.
+                                 */
+                                ldo5: LDO5 {
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /* LCD panel and FM radio */
+                                ldo6: LDO6 {
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /* ??? */
+                                LDO7 {
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        /*regulator-always-on;*/
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /*
+                                 * The colors on the LCD are wrong when this is
+                                 * off. Which is strange, since the LCD panel
+                                 * data sheet only mentions a 3.3V input.
+                                 */
+                                LDO8 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /* RTC fixed 3.3V */
+                                LDO_REG9 {
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        inl-supply = <&vcc>;
+                                };
+
+                                /* Unused fixed 1.2V */
+                                LDO_REG10 {
+                                        inl-supply = <&vcc>;
+                                };
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led {
+                        gpios = <&gpb 30 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                };
+        };
+
+        spi {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sck-gpios = <&gpe 15 GPIO_ACTIVE_HIGH>;
+                mosi-gpios = <&gpe 17 GPIO_ACTIVE_HIGH>;
+                cs-gpios = <&gpe 16 GPIO_ACTIVE_HIGH>;
+                num-chipselects = <1>;
+
+                nt39016@0 {
+                        compatible = "kingdisplay,kd035g6-54nt";
+                        reg = <0>;
+
+                        spi-max-frequency = <3125000>;
+                        spi-3wire;
+                        spi-cs-high;
+
+                        reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
+
+                        backlight = <&backlight>;
+                        power-supply = <&ldo6>;
+
+                        port {
+                                panel_input: endpoint {
+                                        remote-endpoint = <&panel_output>;
+                                };
+                        };
+                };
+        };
+
+        connector {
+                compatible = "gpio-usb-b-connector", "usb-b-connector";
+                label = "mini-USB";
+                type = "mini";
+
+                /*
+                 * USB OTG is not yet working reliably, the ID detection
+                 * mechanism tends to fry easily for unknown reasons.
+                 * Until this is fixed, disable OTG by not providing the
+                 * ID GPIO to the driver.
+                 */
+                //id-gpios = <&gpf 18 GPIO_ACTIVE_LOW>;
+
+                vbus-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
+                vbus-supply = <&otg_vbus>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_otg>;
+
+                port {
+                        usb_ep: endpoint {
+                                remote-endpoint = <&usb_otg_ep>;
+                        };
+                };
+        };
+};
+
+&ext {
+        clock-frequency = <12000000>;
+};
+
+&pinctrl {
+        pins_lcd: lcd {
+                function = "lcd";
+                groups = "lcd-24bit";
+        };
+
+        pins_uart2: uart2 {
+                function = "uart2";
+                groups = "uart2-data";
+        };
+
+        pins_mmc0: mmc0 {
+                function = "mmc0";
+                groups = "mmc0-1bit-a", "mmc0-4bit-a";
+        };
+
+        pins_mmc1: mmc1 {
+                function = "mmc1";
+                groups = "mmc1-1bit-d", "mmc1-4bit-d";
+        };
+
+        pins_otg: otg {
+                otg-vbus-pin {
+                        function = "otg";
+                        groups = "otg-vbus";
+                };
+
+                vbus-pin {
+                        pins = "PB5";
+                        bias-disable;
+                };
+        };
+
+        pins_pwm1: pwm1 {
+                function = "pwm1";
+                groups = "pwm1";
+        };
+
+        pins_pwm4: pwm4 {
+                function = "pwm4";
+                groups = "pwm4";
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart2>;
+
+        status = "okay";
+};
+
+&cgu {
+        /*
+         * Put high-speed peripherals under PLL1, such that we can change the
+         * PLL0 frequency on demand without having to suspend peripherals.
+         * We use a rate of 432 MHz, which is the least common multiple of
+         * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
+         * Put the GPU under PLL0 since we want a higher frequency.
+         * Use the 32 kHz oscillator as the parent of the RTC for a higher
+         * precision.
+         */
+        assigned-clocks =
+                <&cgu JZ4770_CLK_PLL1>,
+                <&cgu JZ4770_CLK_GPU>,
+                <&cgu JZ4770_CLK_RTC>,
+                <&cgu JZ4770_CLK_UHC>,
+                <&cgu JZ4770_CLK_LPCLK_MUX>,
+                <&cgu JZ4770_CLK_MMC0_MUX>,
+                <&cgu JZ4770_CLK_MMC1_MUX>;
+        assigned-clock-parents =
+                <0>,
+                <&cgu JZ4770_CLK_PLL0>,
+                <&cgu JZ4770_CLK_OSC32K>,
+                <&cgu JZ4770_CLK_PLL1>,
+                <&cgu JZ4770_CLK_PLL1>,
+                <&cgu JZ4770_CLK_PLL1>,
+                <&cgu JZ4770_CLK_PLL1>;
+        assigned-clock-rates =
+                <432000000>,
+                <600000000>;
+};
+
+&uhc {
+        /* The WiFi module is connected to the UHC. */
+        status = "okay";
+};
+
+&tcu {
+        /*
+         * 750 kHz for the system timer and clocksource, 12 MHz for the OST,
+         * and use RTC as the parent for the watchdog clock
+         */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>,
+                          <&tcu TCU_CLK_OST>, <&tcu TCU_CLK_WDT>;
+        assigned-clock-parents = <0>, <0>, <0>, <&cgu JZ4770_CLK_RTC>;
+        assigned-clock-rates = <750000>, <750000>, <12000000>;
+
+        /* PWM1 is in use, so use channel #2 for the clocksource */
+        ingenic,pwm-channels-mask = <0xfa>;
+};
+
+&usb_otg {
+        port {
+                usb_otg_ep: endpoint {
+                        remote-endpoint = <&usb_ep>;
+                };
+        };
+};
+
+&otg_phy {
+        vcc-supply = <&ldo5>;
+};
+
+&rtc {
+        clocks = <&cgu JZ4770_CLK_RTC>;
+        clock-names = "rtc";
+
+        system-power-controller;
+};
+
+&mmc0 {
+        status = "okay";
+
+        bus-width = <4>;
+        max-frequency = <48000000>;
+        vmmc-supply = <&vcc>;
+        non-removable;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc0>;
+};
+
+&mmc1 {
+        status = "okay";
+
+        bus-width = <4>;
+        max-frequency = <48000000>;
+        cd-gpios = <&gpb 2 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&mmc1_power>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc1>;
+};
+
+&lcd {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_lcd>;
+
+        port {
+                panel_output: endpoint {
+                        remote-endpoint = <&panel_input>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/gcw0_proto.dts b/arch/mips/boot/dts/ingenic/gcw0_proto.dts
new file mode 100644
index 000000000..02df22f8a
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/gcw0_proto.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "gcw0.dts"
+
+/ {
+        model = "GCW Zero Prototype";
+};
+
+&memory {
+        /* Prototype has only 256 MiB of RAM */
+        reg = <0x0 0x10000000>;
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4725b.dtsi b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
new file mode 100644
index 000000000..a1f0b71c9
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4725b.dtsi
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/jz4725b-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,jz4725b";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-mxu1.0";
+                        reg = <0>;
+
+                        clocks = <&cgu JZ4725B_CLK_CCLK>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
+                reg = <0x10001000 0x14>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        ext: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        osc32k: osc32k {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: clock-controller@10000000 {
+                compatible = "ingenic,jz4725b-cgu";
+                reg = <0x10000000 0x100>;
+
+                clocks = <&ext>, <&osc32k>;
+                clock-names = "ext", "osc32k";
+
+                #clock-cells = <1>;
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,jz4725b-tcu", "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu JZ4725B_CLK_RTC>,
+                         <&cgu JZ4725B_CLK_EXT>,
+                         <&cgu JZ4725B_CLK_PCLK>,
+                         <&cgu JZ4725B_CLK_TCU>;
+                clock-names = "rtc", "ext", "pclk", "tcu";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <23>, <22>, <21>;
+
+                watchdog: watchdog@0 {
+                        compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
+                        reg = <0x0 0xc>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+
+                pwm: pwm@60 {
+                        compatible = "ingenic,jz4725b-pwm";
+                        reg = <0x60 0x40>;
+
+                        #pwm-cells = <3>;
+
+                        clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+                                 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+                                 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
+                        clock-names = "timer0", "timer1", "timer2",
+                                      "timer3", "timer4", "timer5";
+                };
+
+                ost: timer@e0 {
+                        compatible = "ingenic,jz4725b-ost";
+                        reg = <0xe0 0x20>;
+
+                        clocks = <&tcu TCU_CLK_OST>;
+                        clock-names = "ost";
+
+                        interrupts = <15>;
+                };
+        };
+
+        rtc_dev: rtc@10003000 {
+                compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
+                reg = <0x10003000 0x40>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <6>;
+
+                clocks = <&cgu JZ4725B_CLK_RTC>;
+                clock-names = "rtc";
+        };
+
+        pinctrl: pinctrl@10010000 {
+                compatible = "ingenic,jz4725b-pinctrl";
+                reg = <0x10010000 0x400>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,jz4725b-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,jz4725b-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <15>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,jz4725b-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <14>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,jz4725b-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <13>;
+                };
+        };
+
+        aic: audio-controller@10020000 {
+                compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
+                reg = <0x10020000 0x38>;
+
+                #sound-dai-cells = <0>;
+
+                clocks = <&cgu JZ4725B_CLK_AIC>,
+                         <&cgu JZ4725B_CLK_I2S>,
+                         <&cgu JZ4725B_CLK_EXT>,
+                         <&cgu JZ4725B_CLK_PLL_HALF>;
+                clock-names = "aic", "i2s", "ext", "pll half";
+
+                interrupt-parent = <&intc>;
+                interrupts = <10>;
+
+                dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
+                dma-names = "rx", "tx";
+        };
+
+        codec: audio-codec@100200a4 {
+                compatible = "ingenic,jz4725b-codec";
+                reg = <0x100200a4 0x8>;
+
+                #sound-dai-cells = <0>;
+
+                clocks = <&cgu JZ4725B_CLK_AIC>;
+                clock-names = "aic";
+        };
+
+        mmc0: mmc@10021000 {
+                compatible = "ingenic,jz4725b-mmc";
+                reg = <0x10021000 0x1000>;
+
+                clocks = <&cgu JZ4725B_CLK_MMC0>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <25>;
+
+                dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+        };
+
+        mmc1: mmc@10022000 {
+                compatible = "ingenic,jz4725b-mmc";
+                reg = <0x10022000 0x1000>;
+
+                clocks = <&cgu JZ4725B_CLK_MMC1>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <24>;
+
+                dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+        };
+
+        uart: serial@10030000 {
+                compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
+                reg = <0x10030000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <9>;
+
+                clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
+                clock-names = "baud", "module";
+        };
+
+        adc: adc@10070000 {
+                compatible = "ingenic,jz4725b-adc";
+                #io-channel-cells = <1>;
+
+                reg = <0x10070000 0x30>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10070000 0x30>;
+
+                clocks = <&cgu JZ4725B_CLK_ADC>;
+                clock-names = "adc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+        };
+
+        nemc: memory-controller@13010000 {
+                compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
+                reg = <0x13010000 0x10000>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
+                         <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
+
+                clocks = <&cgu JZ4725B_CLK_MCLK>;
+        };
+
+        dmac: dma-controller@13020000 {
+                compatible = "ingenic,jz4725b-dma";
+                reg = <0x13020000 0xd8>, <0x13020300 0x14>;
+
+                #dma-cells = <2>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <29>;
+
+                clocks = <&cgu JZ4725B_CLK_DMA>;
+        };
+
+        udc: usb@13040000 {
+                compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
+                reg = <0x13040000 0x10000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <27>;
+                interrupt-names = "mc";
+
+                clocks = <&cgu JZ4725B_CLK_UDC>;
+                clock-names = "udc";
+        };
+
+        lcd: lcd-controller@13050000 {
+                compatible = "ingenic,jz4725b-lcd";
+                reg = <0x13050000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <31>;
+
+                clocks = <&cgu JZ4725B_CLK_LCD>;
+                clock-names = "lcd_pclk";
+
+                lcd_ports: ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@8 {
+                                reg = <8>;
+
+                                ipu_output: endpoint {
+                                        remote-endpoint = <&ipu_input>;
+                                };
+                        };
+                };
+        };
+
+        ipu: ipu@13080000 {
+                compatible = "ingenic,jz4725b-ipu";
+                reg = <0x13080000 0x64>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <30>;
+
+                clocks = <&cgu JZ4725B_CLK_IPU>;
+                clock-names = "ipu";
+
+                port {
+                        ipu_input: endpoint {
+                                remote-endpoint = <&ipu_output>;
+                        };
+                };
+        };
+
+        bch: ecc-controller@130d0000 {
+                compatible = "ingenic,jz4725b-bch";
+                reg = <0x130d0000 0x44>;
+
+                clocks = <&cgu JZ4725B_CLK_BCH>;
+        };
+
+        rom: memory@1fc00000 {
+                compatible = "mtd-rom";
+                probe-type = "map_rom";
+                reg = <0x1fc00000 0x2000>;
+
+                bank-width = <4>;
+                device-width = <1>;
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
new file mode 100644
index 000000000..eee523678
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/jz4740-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,jz4740";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-mxu1.0";
+                        reg = <0>;
+
+                        clocks = <&cgu JZ4740_CLK_CCLK>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,jz4740-intc";
+                reg = <0x10001000 0x14>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        ext: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        rtc: rtc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: jz4740-cgu@10000000 {
+                compatible = "ingenic,jz4740-cgu";
+                reg = <0x10000000 0x100>;
+
+                clocks = <&ext>, <&rtc>;
+                clock-names = "ext", "rtc";
+
+                #clock-cells = <1>;
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,jz4740-tcu", "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu JZ4740_CLK_RTC>,
+                         <&cgu JZ4740_CLK_EXT>,
+                         <&cgu JZ4740_CLK_PCLK>,
+                         <&cgu JZ4740_CLK_TCU>;
+                clock-names = "rtc", "ext", "pclk", "tcu";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <23 22 21>;
+
+                watchdog: watchdog@0 {
+                        compatible = "ingenic,jz4740-watchdog";
+                        reg = <0x0 0xc>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+
+                pwm: pwm@40 {
+                        compatible = "ingenic,jz4740-pwm";
+                        reg = <0x40 0x80>;
+
+                        #pwm-cells = <3>;
+
+                        clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+                                 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+                                 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
+                                 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
+                        clock-names = "timer0", "timer1", "timer2", "timer3",
+                                      "timer4", "timer5", "timer6", "timer7";
+                };
+        };
+
+        rtc_dev: rtc@10003000 {
+                compatible = "ingenic,jz4740-rtc";
+                reg = <0x10003000 0x40>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <15>;
+
+                clocks = <&cgu JZ4740_CLK_RTC>;
+                clock-names = "rtc";
+        };
+
+        pinctrl: pin-controller@10010000 {
+                compatible = "ingenic,jz4740-pinctrl";
+                reg = <0x10010000 0x400>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,jz4740-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <28>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,jz4740-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <27>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,jz4740-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <26>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,jz4740-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <25>;
+                };
+        };
+
+        aic: audio-controller@10020000 {
+                compatible = "ingenic,jz4740-i2s";
+                reg = <0x10020000 0x38>;
+
+                #sound-dai-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+
+                clocks = <&cgu JZ4740_CLK_AIC>,
+                         <&cgu JZ4740_CLK_I2S>,
+                         <&cgu JZ4740_CLK_EXT>,
+                         <&cgu JZ4740_CLK_PLL_HALF>;
+                clock-names = "aic", "i2s", "ext", "pll half";
+
+                dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
+                dma-names = "rx", "tx";
+        };
+
+        codec: audio-codec@100200a4 {
+                compatible = "ingenic,jz4740-codec";
+                reg = <0x10020080 0x8>;
+
+                #sound-dai-cells = <0>;
+
+                clocks = <&cgu JZ4740_CLK_AIC>;
+                clock-names = "aic";
+        };
+
+        mmc: mmc@10021000 {
+                compatible = "ingenic,jz4740-mmc";
+                reg = <0x10021000 0x1000>;
+
+                clocks = <&cgu JZ4740_CLK_MMC>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <14>;
+
+                dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+        };
+
+        uart0: serial@10030000 {
+                compatible = "ingenic,jz4740-uart";
+                reg = <0x10030000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <9>;
+
+                clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
+                clock-names = "baud", "module";
+        };
+
+        uart1: serial@10031000 {
+                compatible = "ingenic,jz4740-uart";
+                reg = <0x10031000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <8>;
+
+                clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
+                clock-names = "baud", "module";
+        };
+
+        adc: adc@10070000 {
+                compatible = "ingenic,jz4740-adc";
+                reg = <0x10070000 0x30>;
+                #io-channel-cells = <1>;
+
+                clocks = <&cgu JZ4740_CLK_ADC>;
+                clock-names = "adc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <12>;
+        };
+
+        nemc: memory-controller@13010000 {
+                compatible = "ingenic,jz4740-nemc";
+                reg = <0x13010000 0x54>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <1 0 0x18000000 0x4000000>,
+                         <2 0 0x14000000 0x4000000>,
+                         <3 0 0x0c000000 0x4000000>,
+                         <4 0 0x08000000 0x4000000>;
+
+                clocks = <&cgu JZ4740_CLK_MCLK>;
+        };
+
+        ecc: ecc-controller@13010100 {
+                compatible = "ingenic,jz4740-ecc";
+                reg = <0x13010100 0x2C>;
+
+                clocks = <&cgu JZ4740_CLK_MCLK>;
+        };
+
+        dmac: dma-controller@13020000 {
+                compatible = "ingenic,jz4740-dma";
+                reg = <0x13020000 0xbc>, <0x13020300 0x14>;
+                #dma-cells = <2>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <20>;
+
+                clocks = <&cgu JZ4740_CLK_DMA>;
+        };
+
+        uhc: uhc@13030000 {
+                compatible = "ingenic,jz4740-ohci", "generic-ohci";
+                reg = <0x13030000 0x1000>;
+
+                clocks = <&cgu JZ4740_CLK_UHC>;
+                assigned-clocks = <&cgu JZ4740_CLK_UHC>;
+                assigned-clock-rates = <48000000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <3>;
+
+                status = "disabled";
+        };
+
+        udc: usb@13040000 {
+                compatible = "ingenic,jz4740-musb";
+                reg = <0x13040000 0x10000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <24>;
+                interrupt-names = "mc";
+
+                clocks = <&cgu JZ4740_CLK_UDC>;
+                clock-names = "udc";
+        };
+
+        lcd: lcd-controller@13050000 {
+                compatible = "ingenic,jz4740-lcd";
+                reg = <0x13050000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <30>;
+
+                clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
+                clock-names = "lcd_pclk", "lcd";
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
new file mode 100644
index 000000000..018721a9e
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/jz4770-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,jz4770";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+                        reg = <0>;
+
+                        clocks = <&cgu JZ4770_CLK_CCLK>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,jz4770-intc";
+                reg = <0x10001000 0x40>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        ext: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        osc32k: osc32k {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: jz4770-cgu@10000000 {
+                compatible = "ingenic,jz4770-cgu", "simple-mfd";
+                reg = <0x10000000 0x100>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10000000 0x100>;
+
+                clocks = <&ext>, <&osc32k>;
+                clock-names = "ext", "osc32k";
+
+                #clock-cells = <1>;
+
+                otg_phy: usb-phy@3c {
+                        compatible = "ingenic,jz4770-phy";
+                        reg = <0x3c 0x10>;
+
+                        clocks = <&cgu JZ4770_CLK_OTG_PHY>;
+
+                        #phy-cells = <0>;
+                };
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,jz4770-tcu", "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu JZ4770_CLK_RTC>,
+                         <&cgu JZ4770_CLK_EXT>,
+                         <&cgu JZ4770_CLK_PCLK>;
+                clock-names = "rtc", "ext", "pclk";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <27 26 25>;
+
+                watchdog: watchdog@0 {
+                        compatible = "ingenic,jz4770-watchdog",
+                                     "ingenic,jz4740-watchdog";
+                        reg = <0x0 0xc>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+
+                pwm: pwm@40 {
+                        compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
+                        reg = <0x40 0x80>;
+
+                        #pwm-cells = <3>;
+
+                        clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+                                 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+                                 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
+                                 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
+                        clock-names = "timer0", "timer1", "timer2", "timer3",
+                                      "timer4", "timer5", "timer6", "timer7";
+                };
+
+                ost: timer@e0 {
+                        compatible = "ingenic,jz4770-ost";
+                        reg = <0xe0 0x20>;
+
+                        clocks = <&tcu TCU_CLK_OST>;
+                        clock-names = "ost";
+
+                        interrupts = <15>;
+                };
+        };
+
+        rtc: rtc@10003000 {
+                compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc";
+                reg = <0x10003000 0x40>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <32>;
+        };
+
+        pinctrl: pin-controller@10010000 {
+                compatible = "ingenic,jz4770-pinctrl";
+                reg = <0x10010000 0x600>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <17>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <15>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <14>;
+                };
+
+                gpe: gpio@4 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <4>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 128 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <13>;
+                };
+
+                gpf: gpio@5 {
+                        compatible = "ingenic,jz4770-gpio";
+                        reg = <5>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 160 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+                };
+        };
+
+        aic: audio-controller@10020000 {
+                compatible = "ingenic,jz4770-i2s";
+                reg = <0x10020000 0x94>;
+
+                #sound-dai-cells = <0>;
+
+                clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
+                         <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
+                clock-names = "aic", "i2s", "ext", "pll half";
+
+                interrupt-parent = <&intc>;
+                interrupts = <34>;
+
+                dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>;
+                dma-names = "rx", "tx";
+        };
+
+        codec: audio-codec@100200a0 {
+                compatible = "ingenic,jz4770-codec";
+                reg = <0x100200a4 0x8>;
+
+                #sound-dai-cells = <0>;
+
+                clocks = <&cgu JZ4770_CLK_AIC>;
+                clock-names = "aic";
+        };
+
+        mmc0: mmc@10021000 {
+                compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
+                reg = <0x10021000 0x1000>;
+
+                clocks = <&cgu JZ4770_CLK_MMC0>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <37>;
+
+                dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                status = "disabled";
+        };
+
+        mmc1: mmc@10022000 {
+                compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
+                reg = <0x10022000 0x1000>;
+
+                clocks = <&cgu JZ4770_CLK_MMC1>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <36>;
+
+                dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                status = "disabled";
+        };
+
+        mmc2: mmc@10023000 {
+                compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc";
+                reg = <0x10023000 0x1000>;
+
+                clocks = <&cgu JZ4770_CLK_MMC2>;
+                clock-names = "mmc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <35>;
+
+                dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                status = "disabled";
+        };
+
+        uart0: serial@10030000 {
+                compatible = "ingenic,jz4770-uart";
+                reg = <0x10030000 0x100>;
+
+                clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
+                clock-names = "baud", "module";
+
+                interrupt-parent = <&intc>;
+                interrupts = <5>;
+
+                status = "disabled";
+        };
+
+        uart1: serial@10031000 {
+                compatible = "ingenic,jz4770-uart";
+                reg = <0x10031000 0x100>;
+
+                clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
+                clock-names = "baud", "module";
+
+                interrupt-parent = <&intc>;
+                interrupts = <4>;
+
+                status = "disabled";
+        };
+
+        uart2: serial@10032000 {
+                compatible = "ingenic,jz4770-uart";
+                reg = <0x10032000 0x100>;
+
+                clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
+                clock-names = "baud", "module";
+
+                interrupt-parent = <&intc>;
+                interrupts = <3>;
+
+                status = "disabled";
+        };
+
+        uart3: serial@10033000 {
+                compatible = "ingenic,jz4770-uart";
+                reg = <0x10033000 0x100>;
+
+                clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
+                clock-names = "baud", "module";
+
+                interrupt-parent = <&intc>;
+                interrupts = <2>;
+
+                status = "disabled";
+        };
+
+        adc: adc@10070000 {
+                compatible = "ingenic,jz4770-adc";
+                reg = <0x10070000 0x30>;
+
+                #io-channel-cells = <1>;
+
+                clocks = <&cgu JZ4770_CLK_ADC>;
+                clock-names = "adc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+        };
+
+        gpu: gpu@13040000 {
+                compatible = "vivante,gc";
+                reg = <0x13040000 0x10000>;
+
+                clocks = <&cgu JZ4770_CLK_GPU>,
+                         <&cgu JZ4770_CLK_GPU>,
+                         <&cgu JZ4770_CLK_GPU>;
+                clock-names = "bus", "core", "shader";
+
+                interrupt-parent = <&intc>;
+                interrupts = <6>;
+        };
+
+        lcd: lcd-controller@13050000 {
+                compatible = "ingenic,jz4770-lcd";
+                reg = <0x13050000 0x300>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <31>;
+
+                clocks = <&cgu JZ4770_CLK_LPCLK_MUX>;
+                clock-names = "lcd_pclk";
+        };
+
+        dmac0: dma-controller@13420000 {
+                compatible = "ingenic,jz4770-dma";
+                reg = <0x13420000 0xC0>, <0x13420300 0x20>;
+
+                #dma-cells = <2>;
+
+                clocks = <&cgu JZ4770_CLK_DMA>;
+                interrupt-parent = <&intc>;
+                interrupts = <24>;
+        };
+
+        dmac1: dma-controller@13420100 {
+                compatible = "ingenic,jz4770-dma";
+                reg = <0x13420100 0xC0>, <0x13420400 0x20>;
+
+                #dma-cells = <2>;
+
+                clocks = <&cgu JZ4770_CLK_DMA>;
+                interrupt-parent = <&intc>;
+                interrupts = <23>;
+        };
+
+        uhc: uhc@13430000 {
+                compatible = "generic-ohci";
+                reg = <0x13430000 0x1000>;
+
+                clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
+                assigned-clocks = <&cgu JZ4770_CLK_UHC>;
+                assigned-clock-rates = <48000000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <20>;
+
+                status = "disabled";
+        };
+
+        usb_otg: usb@13440000 {
+                compatible = "ingenic,jz4770-musb";
+                reg = <0x13440000 0x10000>;
+
+                clocks = <&cgu JZ4770_CLK_OTG>;
+                clock-names = "udc";
+
+                interrupt-parent = <&intc>;
+                interrupts = <21>;
+                interrupt-names = "mc";
+
+                phys = <&otg_phy>;
+
+                usb-role-switch;
+        };
+
+        rom: memory@1fc00000 {
+                compatible = "mtd-rom";
+                probe-type = "map_rom";
+                reg = <0x1fc00000 0x2000>;
+
+                bank-width = <4>;
+                device-width = <1>;
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
new file mode 100644
index 000000000..830e5dd35
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/jz4780-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/dma/jz4780-dma.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,jz4780";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+                        reg = <0>;
+
+                        clocks = <&cgu JZ4780_CLK_CPU>;
+                        clock-names = "cpu";
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+                        reg = <1>;
+
+                        clocks = <&cgu JZ4780_CLK_CORE1>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,jz4780-intc";
+                reg = <0x10001000 0x50>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        ext: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        rtc: rtc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: jz4780-cgu@10000000 {
+                compatible = "ingenic,jz4780-cgu";
+                reg = <0x10000000 0x100>;
+
+                clocks = <&ext>, <&rtc>;
+                clock-names = "ext", "rtc";
+
+                #clock-cells = <1>;
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,jz4780-tcu",
+                             "ingenic,jz4770-tcu",
+                             "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu JZ4780_CLK_RTCLK>,
+                         <&cgu JZ4780_CLK_EXCLK>,
+                         <&cgu JZ4780_CLK_PCLK>;
+                clock-names = "rtc", "ext", "pclk";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <27 26 25>;
+
+                watchdog: watchdog@0 {
+                        compatible = "ingenic,jz4780-watchdog";
+                        reg = <0x0 0xc>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+
+                pwm: pwm@40 {
+                        compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
+                        reg = <0x40 0x80>;
+
+                        #pwm-cells = <3>;
+
+                        clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+                                 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+                                 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
+                                 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
+                        clock-names = "timer0", "timer1", "timer2", "timer3",
+                                      "timer4", "timer5", "timer6", "timer7";
+                };
+
+                ost: timer@e0 {
+                        compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
+                        reg = <0xe0 0x20>;
+
+                        clocks = <&tcu TCU_CLK_OST>;
+                        clock-names = "ost";
+
+                        interrupts = <15>;
+                };
+        };
+
+        rtc_dev: rtc@10003000 {
+                compatible = "ingenic,jz4780-rtc";
+                reg = <0x10003000 0x4c>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <32>;
+
+                clocks = <&cgu JZ4780_CLK_RTCLK>;
+                clock-names = "rtc";
+        };
+
+        pinctrl: pin-controller@10010000 {
+                compatible = "ingenic,jz4780-pinctrl";
+                reg = <0x10010000 0x600>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <17>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <15>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <14>;
+                };
+
+                gpe: gpio@4 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <4>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 128 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <13>;
+                };
+
+                gpf: gpio@5 {
+                        compatible = "ingenic,jz4780-gpio";
+                        reg = <5>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 160 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+                };
+        };
+
+        spi_gpio {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                num-chipselects = <2>;
+
+                gpio-miso = <&gpe 14 0>;
+                gpio-sck = <&gpe 15 0>;
+                gpio-mosi = <&gpe 17 0>;
+                cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
+
+                spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <1000000>;
+                };
+        };
+
+        uart0: serial@10030000 {
+                compatible = "ingenic,jz4780-uart";
+                reg = <0x10030000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <51>;
+
+                clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart1: serial@10031000 {
+                compatible = "ingenic,jz4780-uart";
+                reg = <0x10031000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <50>;
+
+                clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart2: serial@10032000 {
+                compatible = "ingenic,jz4780-uart";
+                reg = <0x10032000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <49>;
+
+                clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart3: serial@10033000 {
+                compatible = "ingenic,jz4780-uart";
+                reg = <0x10033000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <48>;
+
+                clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart4: serial@10034000 {
+                compatible = "ingenic,jz4780-uart";
+                reg = <0x10034000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <34>;
+
+                clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        i2c0: i2c@10050000 {
+                compatible = "ingenic,jz4780-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reg = <0x10050000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <60>;
+
+                clocks = <&cgu JZ4780_CLK_SMB0>;
+                clock-frequency = <100000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_i2c0_data>;
+
+                status = "disabled";
+        };
+
+        i2c1: i2c@10051000 {
+                compatible = "ingenic,jz4780-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x10051000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <59>;
+
+                clocks = <&cgu JZ4780_CLK_SMB1>;
+                clock-frequency = <100000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_i2c1_data>;
+
+                status = "disabled";
+        };
+
+        i2c2: i2c@10052000 {
+                compatible = "ingenic,jz4780-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x10052000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <58>;
+
+                clocks = <&cgu JZ4780_CLK_SMB2>;
+                clock-frequency = <100000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_i2c2_data>;
+
+                status = "disabled";
+        };
+
+        i2c3: i2c@10053000 {
+                compatible = "ingenic,jz4780-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x10053000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <57>;
+
+                clocks = <&cgu JZ4780_CLK_SMB3>;
+                clock-frequency = <100000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_i2c3_data>;
+
+                status = "disabled";
+        };
+
+        i2c4: i2c@10054000 {
+                compatible = "ingenic,jz4780-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x10054000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <56>;
+
+                clocks = <&cgu JZ4780_CLK_SMB4>;
+                clock-frequency = <100000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_i2c4_data>;
+
+                status = "disabled";
+        };
+
+        nemc: nemc@13410000 {
+                compatible = "ingenic,jz4780-nemc", "simple-mfd";
+                reg = <0x13410000 0x10000>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x13410000 0x10000>,
+                         <1 0 0x1b000000 0x1000000>,
+                         <2 0 0x1a000000 0x1000000>,
+                         <3 0 0x19000000 0x1000000>,
+                         <4 0 0x18000000 0x1000000>,
+                         <5 0 0x17000000 0x1000000>,
+                         <6 0 0x16000000 0x1000000>;
+
+                clocks = <&cgu JZ4780_CLK_NEMC>;
+
+                status = "disabled";
+
+                efuse: efuse@d0 {
+                        reg = <0 0xd0 0x30>;
+                        compatible = "ingenic,jz4780-efuse";
+
+                        clocks = <&cgu JZ4780_CLK_AHB2>;
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        eth0_addr: eth-mac-addr@22 {
+                                reg = <0x22 0x6>;
+                        };
+                };
+        };
+
+        dma: dma@13420000 {
+                compatible = "ingenic,jz4780-dma";
+                reg = <0x13420000 0x400>, <0x13421000 0x40>;
+                #dma-cells = <2>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <10>;
+
+                clocks = <&cgu JZ4780_CLK_PDMA>;
+        };
+
+        mmc0: mmc@13450000 {
+                compatible = "ingenic,jz4780-mmc";
+                reg = <0x13450000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <37>;
+
+                clocks = <&cgu JZ4780_CLK_MSC0>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+                dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
+                       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        mmc1: mmc@13460000 {
+                compatible = "ingenic,jz4780-mmc";
+                reg = <0x13460000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <36>;
+
+                clocks = <&cgu JZ4780_CLK_MSC1>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+                dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
+                       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        bch: bch@134d0000 {
+                compatible = "ingenic,jz4780-bch";
+                reg = <0x134d0000 0x10000>;
+
+                clocks = <&cgu JZ4780_CLK_BCH>;
+
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts
new file mode 100644
index 000000000..ba0218971
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4740.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/adc/ingenic,adc.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/input/input.h>
+
+#define KEY_QI_QI       KEY_F13
+#define KEY_QI_UPRED    KEY_RIGHTALT
+#define KEY_QI_VOLUP    KEY_VOLUMEUP
+#define KEY_QI_VOLDOWN  KEY_VOLUMEDOWN
+#define KEY_QI_FN       KEY_LEFTCTRL
+
+/ {
+        compatible = "qi,lb60", "ingenic,jz4740";
+        model = "Ben Nanonote";
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        chosen {
+                stdout-path = &uart0;
+        };
+
+        vcc: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc";
+
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        mmc_power: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcc";
+                gpio = <&gpd 2 0>;
+
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        amp_supply: regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "amp_supply";
+                gpio = <&gpd 4 0>;
+                enable-active-high;
+
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        amp: analog-amplifier {
+                compatible = "simple-audio-amplifier";
+                enable-gpios = <&gpb 29 GPIO_ACTIVE_HIGH>;
+                VCC-supply = <&amp_supply>;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,name = "QI LB60";
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,widgets =
+                        "Speaker", "Speaker",
+                        "Microphone", "Mic";
+                simple-audio-card,routing =
+                        "MIC", "Mic",
+                        "Speaker", "OUTL",
+                        "Speaker", "OUTR",
+                        "INL", "LOUT",
+                        "INR", "ROUT";
+
+                simple-audio-card,aux-devs = <&amp>;
+
+                simple-audio-card,bitclock-master = <&dai_codec>;
+                simple-audio-card,frame-master = <&dai_codec>;
+
+                dai_cpu: simple-audio-card,cpu {
+                        sound-dai = <&aic>;
+                };
+
+                dai_codec: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                };
+        };
+
+        keys {
+                compatible = "gpio-keys";
+
+                key {
+                        label = "Power";
+                        wakeup-source;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpd 29 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        keyboard {
+                compatible = "gpio-matrix-keypad";
+
+                col-scan-delay-us = <10>;
+                debounce-delay-ms = <10>;
+                wakeup-source;
+
+                row-gpios = <&gpd 18 0>, <&gpd 19 0>, <&gpd 20 0>, <&gpd 21 0>,
+                            <&gpd 22 0>, <&gpd 23 0>, <&gpd 24 0>, <&gpd 26 0>;
+                col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
+                            <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
+                gpio-activelow;
+
+                linux,keymap =
+                        <MATRIX_KEY(0, 0, KEY_F1)>,     /* S2 */
+                        <MATRIX_KEY(0, 1, KEY_F2)>,     /* S3 */
+                        <MATRIX_KEY(0, 2, KEY_F3)>,     /* S4 */
+                        <MATRIX_KEY(0, 3, KEY_F4)>,     /* S5 */
+                        <MATRIX_KEY(0, 4, KEY_F5)>,     /* S6 */
+                        <MATRIX_KEY(0, 5, KEY_F6)>,     /* S7 */
+                        <MATRIX_KEY(0, 6, KEY_F7)>,     /* S8 */
+
+                        <MATRIX_KEY(1, 0, KEY_Q)>,      /* S10 */
+                        <MATRIX_KEY(1, 1, KEY_W)>,      /* S11 */
+                        <MATRIX_KEY(1, 2, KEY_E)>,      /* S12 */
+                        <MATRIX_KEY(1, 3, KEY_R)>,      /* S13 */
+                        <MATRIX_KEY(1, 4, KEY_T)>,      /* S14 */
+                        <MATRIX_KEY(1, 5, KEY_Y)>,      /* S15 */
+                        <MATRIX_KEY(1, 6, KEY_U)>,      /* S16 */
+                        <MATRIX_KEY(1, 7, KEY_I)>,      /* S17 */
+                        <MATRIX_KEY(2, 0, KEY_A)>,      /* S18 */
+                        <MATRIX_KEY(2, 1, KEY_S)>,      /* S19 */
+                        <MATRIX_KEY(2, 2, KEY_D)>,      /* S20 */
+                        <MATRIX_KEY(2, 3, KEY_F)>,      /* S21 */
+                        <MATRIX_KEY(2, 4, KEY_G)>,      /* S22 */
+                        <MATRIX_KEY(2, 5, KEY_H)>,      /* S23 */
+                        <MATRIX_KEY(2, 6, KEY_J)>,      /* S24 */
+                        <MATRIX_KEY(2, 7, KEY_K)>,      /* S25 */
+                        <MATRIX_KEY(3, 0, KEY_ESC)>,    /* S26 */
+                        <MATRIX_KEY(3, 1, KEY_Z)>,      /* S27 */
+                        <MATRIX_KEY(3, 2, KEY_X)>,      /* S28 */
+                        <MATRIX_KEY(3, 3, KEY_C)>,      /* S29 */
+                        <MATRIX_KEY(3, 4, KEY_V)>,      /* S30 */
+                        <MATRIX_KEY(3, 5, KEY_B)>,      /* S31 */
+                        <MATRIX_KEY(3, 6, KEY_N)>,      /* S32 */
+                        <MATRIX_KEY(3, 7, KEY_M)>,      /* S33 */
+                        <MATRIX_KEY(4, 0, KEY_TAB)>,    /* S34 */
+                        <MATRIX_KEY(4, 1, KEY_CAPSLOCK)>,       /* S35 */
+                        <MATRIX_KEY(4, 2, KEY_BACKSLASH)>,      /* S36 */
+                        <MATRIX_KEY(4, 3, KEY_APOSTROPHE)>,     /* S37 */
+                        <MATRIX_KEY(4, 4, KEY_COMMA)>,  /* S38 */
+                        <MATRIX_KEY(4, 5, KEY_DOT)>,    /* S39 */
+                        <MATRIX_KEY(4, 6, KEY_SLASH)>,  /* S40 */
+                        <MATRIX_KEY(4, 7, KEY_UP)>,     /* S41 */
+                        <MATRIX_KEY(5, 0, KEY_O)>,      /* S42 */
+                        <MATRIX_KEY(5, 1, KEY_L)>,      /* S43 */
+                        <MATRIX_KEY(5, 2, KEY_EQUAL)>,  /* S44 */
+                        <MATRIX_KEY(5, 3, KEY_QI_UPRED)>,       /* S45 */
+                        <MATRIX_KEY(5, 4, KEY_SPACE)>,  /* S46 */
+                        <MATRIX_KEY(5, 5, KEY_QI_QI)>,  /* S47 */
+                        <MATRIX_KEY(5, 6, KEY_RIGHTCTRL)>,      /* S48 */
+                        <MATRIX_KEY(5, 7, KEY_LEFT)>,   /* S49 */
+                        <MATRIX_KEY(6, 0, KEY_F8)>,     /* S50 */
+                        <MATRIX_KEY(6, 1, KEY_P)>,      /* S51 */
+                        <MATRIX_KEY(6, 2, KEY_BACKSPACE)>,/* S52 */
+                        <MATRIX_KEY(6, 3, KEY_ENTER)>,  /* S53 */
+                        <MATRIX_KEY(6, 4, KEY_QI_VOLUP)>,       /* S54 */
+                        <MATRIX_KEY(6, 5, KEY_QI_VOLDOWN)>,     /* S55 */
+                        <MATRIX_KEY(6, 6, KEY_DOWN)>,   /* S56 */
+                        <MATRIX_KEY(6, 7, KEY_RIGHT)>,  /* S57 */
+
+                        <MATRIX_KEY(7, 0, KEY_LEFTSHIFT)>,      /* S58 */
+                        <MATRIX_KEY(7, 1, KEY_LEFTALT)>, /* S59 */
+                        <MATRIX_KEY(7, 2, KEY_QI_FN)>;  /* S60 */
+        };
+
+        spi {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
+                mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>;
+                cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>;
+                num-chipselects = <1>;
+        };
+
+        usb_charger: charger {
+                compatible = "gpio-charger";
+                charger-type = "usb-sdp";
+                gpios = <&gpd 28 GPIO_ACTIVE_LOW>;
+                status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>;
+        };
+
+        simple_battery: battery {
+                compatible = "simple-battery";
+                voltage-min-design-microvolt = <3600000>;
+                voltage-max-design-microvolt = <4200000>;
+        };
+
+        pmu {
+                compatible = "ingenic,jz4740-battery";
+                io-channels = <&adc INGENIC_ADC_BATTERY>;
+                io-channel-names = "battery";
+                power-supplies = <&usb_charger>;
+                monitored-battery = <&simple_battery>;
+        };
+
+        hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&adc INGENIC_ADC_AUX>;
+        };
+
+        panel: panel {
+                compatible = "giantplus,gpm940b0";
+
+                power-supply = <&vcc>;
+
+                port {
+                        panel_input: endpoint {
+                                remote-endpoint = <&panel_output>;
+                        };
+                };
+        };
+
+        usb_phy: usb-phy {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+
+                vcc-supply = <&vcc>;
+        };
+};
+
+&ext {
+        clock-frequency = <12000000>;
+};
+
+&rtc_dev {
+        system-power-controller;
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_uart0>;
+};
+
+&uart1 {
+        status = "disabled";
+};
+
+&nemc {
+        nandc: nand-controller@1 {
+                compatible = "ingenic,jz4740-nand";
+                reg = <1 0 0x4000000>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ecc-engine = <&ecc>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_nemc>;
+
+                rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
+
+                nand@1 {
+                        reg = <1>;
+
+                        nand-ecc-step-size = <512>;
+                        nand-ecc-strength = <4>;
+                        nand-ecc-mode = "hw";
+                        nand-is-boot-medium;
+                        nand-on-flash-bbt;
+
+                        partitions {
+                                compatible = "fixed-partitions";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "boot";
+                                        reg = <0x0 0x400000>;
+                                };
+
+                                partition@400000 {
+                                        label = "kernel";
+                                        reg = <0x400000 0x400000>;
+                                };
+
+                                partition@800000 {
+                                        label = "rootfs";
+                                        reg = <0x800000 0x0>;
+                                };
+                        };
+                };
+        };
+};
+
+&lcd {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_lcd>;
+
+        port {
+                panel_output: endpoint {
+                        remote-endpoint = <&panel_input>;
+                };
+        };
+};
+
+&udc {
+        phys = <&usb_phy>;
+};
+
+&pinctrl {
+        pins_lcd: lcd {
+                function = "lcd";
+                groups = "lcd-8bit";
+        };
+
+        pins_nemc: nemc {
+                function = "nand";
+                groups = "nand-fre-fwe", "nand-cs1";
+        };
+
+        pins_uart0: uart0 {
+                function = "uart0";
+                groups = "uart0-data";
+                bias-disable;
+        };
+
+        pins_mmc: mmc {
+                mmc {
+                        function = "mmc";
+                        groups = "mmc-1bit", "mmc-4bit";
+                        bias-disable;
+                };
+
+                mmc-gpios {
+                        pins = "PD0", "PD2";
+                        bias-disable;
+                };
+        };
+};
+
+&mmc {
+        bus-width = <4>;
+        max-frequency = <24000000>;
+        cd-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&mmc_power>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc>;
+};
+
+&tcu {
+        /* 750 kHz for the system timer and clocksource */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+        assigned-clock-rates = <750000>, <750000>;
+};
diff --git a/arch/mips/boot/dts/ingenic/rs90.dts b/arch/mips/boot/dts/ingenic/rs90.dts
new file mode 100644
index 000000000..4eb1edbfc
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/rs90.dts
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4725b.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/adc/ingenic,adc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+        compatible = "ylm,rs90", "ingenic,jz4725b";
+        model = "RS-90";
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        vcc: regulator {
+                compatible = "regulator-fixed";
+
+                regulator-name = "vcc";
+                regulaor-min-microvolt = <3300000>;
+                regulaor-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 40000 0>;
+
+                brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
+                default-brightness-level = <8>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_pwm3>;
+
+                power-supply = <&vcc>;
+        };
+
+        keys@0 {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                key@0 {
+                        label = "D-pad up";
+                        linux,code = <KEY_UP>;
+                        gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
+                };
+
+                key@1 {
+                        label = "D-pad down";
+                        linux,code = <KEY_DOWN>;
+                        gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
+                };
+
+                key@2 {
+                        label = "D-pad left";
+                        linux,code = <KEY_LEFT>;
+                        gpios = <&gpb 31 GPIO_ACTIVE_LOW>;
+                };
+
+                key@3 {
+                        label = "D-pad right";
+                        linux,code = <KEY_RIGHT>;
+                        gpios = <&gpd 21 GPIO_ACTIVE_LOW>;
+                };
+
+                key@4 {
+                        label = "Button A";
+                        linux,code = <KEY_LEFTCTRL>;
+                        gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
+                };
+
+                key@5 {
+                        label = "Button B";
+                        linux,code = <KEY_LEFTALT>;
+                        gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
+                };
+
+                key@6 {
+                        label = "Right shoulder button";
+                        linux,code = <KEY_BACKSPACE>;
+                        gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
+                        debounce-interval = <10>;
+                };
+
+                key@7 {
+                        label = "Start button";
+                        linux,code = <KEY_ENTER>;
+                        gpios = <&gpd 17 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        keys@1 {
+                compatible = "adc-keys";
+                io-channels = <&adc INGENIC_ADC_AUX>;
+                io-channel-names = "buttons";
+                keyup-threshold-microvolt = <1400000>;
+                poll-interval = <30>;
+
+                key@0 {
+                        label = "Left shoulder button";
+                        linux,code = <KEY_TAB>;
+                        press-threshold-microvolt = <800000>;
+                };
+
+                key@1 {
+                        label = "Select button";
+                        linux,code = <KEY_ESC>;
+                        press-threshold-microvolt = <1100000>;
+                };
+        };
+
+        amp: analog-amplifier {
+                compatible = "simple-audio-amplifier";
+                enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
+
+                VCC-supply = <&vcc>;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,name = "rs90-audio";
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,widgets =
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphones";
+                simple-audio-card,routing =
+                        "INL", "LHPOUT",
+                        "INR", "RHPOUT",
+                        "Headphones", "LHPOUT",
+                        "Headphones", "RHPOUT",
+                        "Speaker", "OUTL",
+                        "Speaker", "OUTR";
+                simple-audio-card,pin-switches = "Speaker";
+
+                simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>;
+                simple-audio-card,aux-devs = <&amp>;
+
+                simple-audio-card,bitclock-master = <&dai_codec>;
+                simple-audio-card,frame-master = <&dai_codec>;
+
+                dai_cpu: simple-audio-card,cpu {
+                        sound-dai = <&aic>;
+                };
+
+                dai_codec: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                };
+
+        };
+
+        usb_phy: usb-phy {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+
+                clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
+                clock-names = "main_clk";
+                vcc-supply = <&vcc>;
+        };
+
+        panel {
+                compatible = "sharp,ls020b1dd01d";
+
+                backlight = <&backlight>;
+                power-supply = <&vcc>;
+
+                port {
+                        panel_input: endpoint {
+                                remote-endpoint = <&panel_output>;
+                        };
+                };
+        };
+};
+
+&ext {
+        clock-frequency = <12000000>;
+};
+
+&rtc_dev {
+        system-power-controller;
+};
+
+&udc {
+        phys = <&usb_phy>;
+};
+
+&pinctrl {
+        pins_mmc1: mmc1 {
+                function = "mmc1";
+                groups = "mmc1-1bit";
+        };
+
+        pins_nemc: nemc {
+                function = "nand";
+                groups = "nand-cs1", "nand-cle-ale", "nand-fre-fwe";
+        };
+
+        pins_pwm3: pwm3 {
+                function = "pwm3";
+                groups = "pwm3";
+                bias-disable;
+        };
+
+        pins_lcd: lcd {
+                function = "lcd";
+                groups = "lcd-8bit", "lcd-16bit", "lcd-special";
+        };
+};
+
+&mmc0 {
+        status = "disabled";
+};
+
+&mmc1 {
+        bus-width = <1>;
+        max-frequency = <48000000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_mmc1>;
+
+        cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
+};
+
+&uart {
+        /*
+         * The pins for RX/TX are used for the right shoulder button and
+         * backlight PWM.
+         */
+        status = "disabled";
+};
+
+&nemc {
+        nandc: nand-controller@1 {
+                compatible = "ingenic,jz4725b-nand";
+                reg = <1 0 0x4000000>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ecc-engine = <&bch>;
+
+                ingenic,nemc-tAS = <10>;
+                ingenic,nemc-tAH = <5>;
+                ingenic,nemc-tBP = <10>;
+                ingenic,nemc-tAW = <15>;
+                ingenic,nemc-tSTRV = <100>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_nemc>;
+
+                rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
+
+                nand@1 {
+                        reg = <1>;
+
+                        nand-ecc-step-size = <512>;
+                        nand-ecc-strength = <8>;
+                        nand-ecc-mode = "hw";
+                        nand-is-boot-medium;
+                        nand-on-flash-bbt;
+
+                        partitions {
+                                compatible = "fixed-partitions";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "bootloader";
+                                        reg = <0x0 0x20000>;
+                                };
+
+                                partition@20000 {
+                                        label = "system";
+                                        reg = <0x20000 0x0>;
+                                };
+                        };
+                };
+        };
+};
+
+&cgu {
+        /* Use 32kHz oscillator as the parent of the RTC clock */
+        assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
+        assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
+};
+
+&tcu {
+        /*
+         * 750 kHz for the system timer and clocksource, and use RTC as the
+         * parent for the watchdog clock.
+         */
+        assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_WDT>;
+        assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
+        assigned-clock-rates = <750000>, <750000>;
+};
+
+&lcd {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pins_lcd>;
+};
+
+&lcd_ports {
+        port@0 {
+                reg = <0>;
+
+                panel_output: endpoint {
+                        remote-endpoint = <&panel_input>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
new file mode 100644
index 000000000..1f1f896dd
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include <dt-bindings/dma/x1000-dma.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,x1000", "ingenic,x1000e";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+                        reg = <0>;
+
+                        clocks = <&cgu X1000_CLK_CPU>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
+                reg = <0x10001000 0x50>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        exclk: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        rtclk: rtc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: x1000-cgu@10000000 {
+                compatible = "ingenic,x1000-cgu";
+                reg = <0x10000000 0x100>;
+
+                #clock-cells = <1>;
+
+                clocks = <&exclk>, <&rtclk>;
+                clock-names = "ext", "rtc";
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,x1000-tcu", "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu X1000_CLK_RTCLK>,
+                         <&cgu X1000_CLK_EXCLK>,
+                         <&cgu X1000_CLK_PCLK>;
+                clock-names = "rtc", "ext", "pclk";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <27 26 25>;
+
+                wdt: watchdog@0 {
+                        compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog";
+                        reg = <0x0 0x10>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+        };
+
+        rtc: rtc@10003000 {
+                compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc";
+                reg = <0x10003000 0x4c>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <32>;
+
+                clocks = <&cgu X1000_CLK_RTCLK>;
+                clock-names = "rtc";
+        };
+
+        pinctrl: pin-controller@10010000 {
+                compatible = "ingenic,x1000-pinctrl";
+                reg = <0x10010000 0x800>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,x1000-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <17>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,x1000-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,x1000-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <15>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,x1000-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <14>;
+                };
+        };
+
+        uart0: serial@10030000 {
+                compatible = "ingenic,x1000-uart";
+                reg = <0x10030000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <51>;
+
+                clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart1: serial@10031000 {
+                compatible = "ingenic,x1000-uart";
+                reg = <0x10031000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <50>;
+
+                clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart2: serial@10032000 {
+                compatible = "ingenic,x1000-uart";
+                reg = <0x10032000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <49>;
+
+                clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        i2c0: i2c-controller@10050000 {
+                compatible = "ingenic,x1000-i2c";
+                reg = <0x10050000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <60>;
+
+                clocks = <&cgu X1000_CLK_I2C0>;
+
+                status = "disabled";
+        };
+
+        i2c1: i2c-controller@10051000 {
+                compatible = "ingenic,x1000-i2c";
+                reg = <0x10051000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <59>;
+
+                clocks = <&cgu X1000_CLK_I2C1>;
+
+                status = "disabled";
+        };
+
+        i2c2: i2c-controller@10052000 {
+                compatible = "ingenic,x1000-i2c";
+                reg = <0x10052000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <58>;
+
+                clocks = <&cgu X1000_CLK_I2C2>;
+
+                status = "disabled";
+        };
+
+        pdma: dma-controller@13420000 {
+                compatible = "ingenic,x1000-dma";
+                reg = <0x13420000 0x400>, <0x13421000 0x40>;
+                #dma-cells = <2>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <10>;
+
+                clocks = <&cgu X1000_CLK_PDMA>;
+        };
+
+        msc0: mmc@13450000 {
+                compatible = "ingenic,x1000-mmc";
+                reg = <0x13450000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <37>;
+
+                clocks = <&cgu X1000_CLK_MSC0>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>,
+                           <&pdma X1000_DMA_MSC0_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        msc1: mmc@13460000 {
+                compatible = "ingenic,x1000-mmc";
+                reg = <0x13460000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <36>;
+
+                clocks = <&cgu X1000_CLK_MSC1>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>,
+                           <&pdma X1000_DMA_MSC1_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        mac: ethernet@134b0000 {
+                compatible = "ingenic,x1000-mac", "snps,dwmac";
+                reg = <0x134b0000 0x2000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <55>;
+                interrupt-names = "macirq";
+
+                clocks = <&cgu X1000_CLK_MAC>;
+                clock-names = "stmmaceth";
+
+                status = "disabled";
+
+                mdio: mdio {
+                        compatible = "snps,dwmac-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
new file mode 100644
index 000000000..b05dac3ae
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/clock/x1830-cgu.h>
+#include <dt-bindings/dma/x1830-dma.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ingenic,x1830";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "ingenic,xburst-fpu2.0-mxu2.0";
+                        reg = <0>;
+
+                        clocks = <&cgu X1830_CLK_CPU>;
+                        clock-names = "cpu";
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        intc: interrupt-controller@10001000 {
+                compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
+                reg = <0x10001000 0x50>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <2>;
+        };
+
+        exclk: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        rtclk: rtc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        cgu: x1830-cgu@10000000 {
+                compatible = "ingenic,x1830-cgu";
+                reg = <0x10000000 0x100>;
+
+                #clock-cells = <1>;
+
+                clocks = <&exclk>, <&rtclk>;
+                clock-names = "ext", "rtc";
+        };
+
+        tcu: timer@10002000 {
+                compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
+                reg = <0x10002000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x10002000 0x1000>;
+
+                #clock-cells = <1>;
+
+                clocks = <&cgu X1830_CLK_RTCLK
+                          &cgu X1830_CLK_EXCLK
+                          &cgu X1830_CLK_PCLK>;
+                clock-names = "rtc", "ext", "pclk";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <27 26 25>;
+
+                wdt: watchdog@0 {
+                        compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
+                        reg = <0x0 0x10>;
+
+                        clocks = <&tcu TCU_CLK_WDT>;
+                        clock-names = "wdt";
+                };
+        };
+
+        rtc: rtc@10003000 {
+                compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
+                reg = <0x10003000 0x4c>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <32>;
+
+                clocks = <&cgu X1830_CLK_RTCLK>;
+                clock-names = "rtc";
+        };
+
+        pinctrl: pin-controller@10010000 {
+                compatible = "ingenic,x1830-pinctrl";
+                reg = <0x10010000 0x800>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                gpa: gpio@0 {
+                        compatible = "ingenic,x1830-gpio";
+                        reg = <0>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <17>;
+                };
+
+                gpb: gpio@1 {
+                        compatible = "ingenic,x1830-gpio";
+                        reg = <1>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 32 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                };
+
+                gpc: gpio@2 {
+                        compatible = "ingenic,x1830-gpio";
+                        reg = <2>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 64 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <15>;
+                };
+
+                gpd: gpio@3 {
+                        compatible = "ingenic,x1830-gpio";
+                        reg = <3>;
+
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 96 32>;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <14>;
+                };
+        };
+
+        uart0: serial@10030000 {
+                compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
+                reg = <0x10030000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <51>;
+
+                clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        uart1: serial@10031000 {
+                compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
+                reg = <0x10031000 0x100>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <50>;
+
+                clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
+                clock-names = "baud", "module";
+
+                status = "disabled";
+        };
+
+        i2c0: i2c-controller@10050000 {
+                compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
+                reg = <0x10050000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <60>;
+
+                clocks = <&cgu X1830_CLK_SMB0>;
+
+                status = "disabled";
+        };
+
+        i2c1: i2c-controller@10051000 {
+                compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
+                reg = <0x10051000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <59>;
+
+                clocks = <&cgu X1830_CLK_SMB1>;
+
+                status = "disabled";
+        };
+
+        i2c2: i2c-controller@10052000 {
+                compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
+                reg = <0x10052000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <58>;
+
+                clocks = <&cgu X1830_CLK_SMB2>;
+
+                status = "disabled";
+        };
+
+        pdma: dma-controller@13420000 {
+                compatible = "ingenic,x1830-dma";
+                reg = <0x13420000 0x400
+                           0x13421000 0x40>;
+                #dma-cells = <2>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <10>;
+
+                clocks = <&cgu X1830_CLK_PDMA>;
+        };
+
+        msc0: mmc@13450000 {
+                compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
+                reg = <0x13450000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <37>;
+
+                clocks = <&cgu X1830_CLK_MSC0>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
+                           <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        msc1: mmc@13460000 {
+                compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
+                reg = <0x13460000 0x1000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <36>;
+
+                clocks = <&cgu X1830_CLK_MSC1>;
+                clock-names = "mmc";
+
+                cap-sd-highspeed;
+                cap-mmc-highspeed;
+                cap-sdio-irq;
+
+                dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
+                           <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
+                dma-names = "rx", "tx";
+
+                status = "disabled";
+        };
+
+        mac: ethernet@134b0000 {
+                compatible = "ingenic,x1830-mac", "snps,dwmac";
+                reg = <0x134b0000 0x2000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <55>;
+                interrupt-names = "macirq";
+
+                clocks = <&cgu X1830_CLK_MAC>;
+                clock-names = "stmmaceth";
+
+                status = "disabled";
+
+                mdio: mdio {
+                        compatible = "snps,dwmac-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/lantiq/Makefile b/arch/mips/boot/dts/lantiq/Makefile
new file mode 100644
index 000000000..f5dfc0624
--- /dev/null
+++ b/arch/mips/boot/dts/lantiq/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DT_EASY50712)      += easy50712.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi
new file mode 100644
index 000000000..510be63c8
--- /dev/null
+++ b/arch/mips/boot/dts/lantiq/danube.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "lantiq,xway", "lantiq,danube";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips24Kc";
+                };
+        };
+
+        biu@1f800000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "lantiq,biu", "simple-bus";
+                reg = <0x1f800000 0x800000>;
+                ranges = <0x0 0x1f800000 0x7fffff>;
+
+                icu0: icu@80200 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "lantiq,icu";
+                        reg = <0x80200 0x120>;
+                };
+
+                watchdog@803f0 {
+                        compatible = "lantiq,wdt";
+                        reg = <0x803f0 0x10>;
+                };
+        };
+
+        sram@1f000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "lantiq,sram";
+                reg = <0x1f000000 0x800000>;
+                ranges = <0x0 0x1f000000 0x7fffff>;
+
+                eiu0: eiu@101000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        interrupt-parent;
+                        compatible = "lantiq,eiu-xway";
+                        reg = <0x101000 0x1000>;
+                };
+
+                pmu0: pmu@102000 {
+                        compatible = "lantiq,pmu-xway";
+                        reg = <0x102000 0x1000>;
+                };
+
+                cgu0: cgu@103000 {
+                        compatible = "lantiq,cgu-xway";
+                        reg = <0x103000 0x1000>;
+                        #clock-cells = <1>;
+                };
+
+                rcu0: rcu@203000 {
+                        compatible = "lantiq,rcu-xway";
+                        reg = <0x203000 0x1000>;
+                };
+        };
+
+        fpi@10000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "lantiq,fpi", "simple-bus";
+                ranges = <0x0 0x10000000 0xeefffff>;
+                reg = <0x10000000 0xef00000>;
+
+                gptu@e100a00 {
+                        compatible = "lantiq,gptu-xway";
+                        reg = <0xe100a00 0x100>;
+                };
+
+                serial@e100c00 {
+                        compatible = "lantiq,asc";
+                        reg = <0xe100c00 0x400>;
+                        interrupt-parent = <&icu0>;
+                        interrupts = <112 113 114>;
+                };
+
+                dma0: dma@e104100 {
+                        compatible = "lantiq,dma-xway";
+                        reg = <0xe104100 0x800>;
+                };
+
+                ebu0: ebu@e105300 {
+                        compatible = "lantiq,ebu-xway";
+                        reg = <0xe105300 0x100>;
+                };
+
+                pci0: pci@e105400 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        compatible = "lantiq,pci-xway";
+                        bus-range = <0x0 0x0>;
+                        ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
+                                  0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
+                        reg = <0x7000000 0x8000         /* config space */
+                                0xe105400 0x400>;       /* pci bridge */
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/lantiq/easy50712.dts b/arch/mips/boot/dts/lantiq/easy50712.dts
new file mode 100644
index 000000000..1ce20b7d0
--- /dev/null
+++ b/arch/mips/boot/dts/lantiq/easy50712.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "danube.dtsi"
+
+/ {
+        chosen {
+                bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        fpi@10000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                localbus@0 {
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
+                                1 0 0x4000000 0x4000010>; /* addsel1 */
+                        compatible = "lantiq,localbus", "simple-bus";
+
+                        nor-boot@0 {
+                                compatible = "lantiq,nor";
+                                bank-width = <2>;
+                                reg = <0 0x0 0x2000000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "uboot";
+                                        reg = <0x00000 0x10000>; /* 64 KB */
+                                };
+
+                                partition@10000 {
+                                        label = "uboot_env";
+                                        reg = <0x10000 0x10000>; /* 64 KB */
+                                };
+
+                                partition@20000 {
+                                        label = "linux";
+                                        reg = <0x20000 0x3d0000>;
+                                };
+
+                                partition@400000 {
+                                        label = "rootfs";
+                                        reg = <0x400000 0x400000>;
+                                };
+                        };
+                };
+
+                gpio: pinmux@e100b10 {
+                        compatible = "lantiq,danube-pinctrl";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xe100b10 0xa0>;
+
+                        state_default: pinmux {
+                                stp {
+                                        lantiq,groups = "stp";
+                                        lantiq,function = "stp";
+                                };
+                                exin {
+                                        lantiq,groups = "exin1";
+                                        lantiq,function = "exin";
+                                };
+                                pci {
+                                        lantiq,groups = "gnt1";
+                                        lantiq,function = "pci";
+                                };
+                                conf_out {
+                                        lantiq,pins = "io4", "io5", "io6"; /* stp */
+                                        lantiq,open-drain;
+                                        lantiq,pull = <0>;
+                                };
+                        };
+                };
+
+                etop@e180000 {
+                        compatible = "lantiq,etop-xway";
+                        reg = <0xe180000 0x40000>;
+                        interrupt-parent = <&icu0>;
+                        interrupts = <73 78>;
+                        phy-mode = "rmii";
+                        mac-address = [ 00 11 22 33 44 55 ];
+                };
+
+                stp0: stp@e100bb0 {
+                        #gpio-cells = <2>;
+                        compatible = "lantiq,gpio-stp-xway";
+                        gpio-controller;
+                        reg = <0xe100bb0 0x40>;
+
+                        lantiq,shadow = <0xfff>;
+                        lantiq,groups = <0x3>;
+                };
+
+                pci@e105400 {
+                        lantiq,bus-clock = <33333333>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
+                        >;
+                        gpios-reset = <&gpio 21 0>;
+                        req-mask = <0x1>;               /* GNT1 */
+                };
+
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000..8fd0efb37
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,8 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64)   += loongson64c_4core_ls7a.dtb
+dtb-$(CONFIG_MACH_LOONGSON64)   += loongson64c_4core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64)   += loongson64c_8core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64)   += loongson64g_4core_ls7a.dtb
+dtb-$(CONFIG_MACH_LOONGSON64)   += loongson64v_4core_virtio.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson64c-package.dtsi b/arch/mips/boot/dts/loongson/loongson64c-package.dtsi
new file mode 100644
index 000000000..5bb876a4d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64c-package.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        package0: bus@1fe00000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+                        0 0x3ff00000 0 0x3ff00000 0x100000
+                        /* 3A HT Config Space */
+                        0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
+                        /* 3B HT Config Space */
+                        0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
+
+                liointc: interrupt-controller@3ff01400 {
+                        compatible = "loongson,liointc-1.0";
+                        reg = <0 0x3ff01400 0x64>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>, <3>;
+                        interrupt-names = "int0", "int1";
+
+                        loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+                                                <0x0f000000>, /* int1 */
+                                                <0x00000000>, /* int2 */
+                                                <0x00000000>; /* int3 */
+
+                };
+
+                cpu_uart0: serial@1fe001e0 {
+                        compatible = "ns16550a";
+                        reg = <0 0x1fe001e0 0x8>;
+                        clock-frequency = <33000000>;
+                        interrupt-parent = <&liointc>;
+                        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                cpu_uart1: serial@1fe001e8 {
+                        status = "disabled";
+                        compatible = "ns16550a";
+                        reg = <0 0x1fe001e8 0x8>;
+                        clock-frequency = <33000000>;
+                        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-parent = <&liointc>;
+                        no-loopback-test;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
new file mode 100644
index 000000000..c7ea4f1c0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64c-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+        compatible = "loongson,loongson64c-4core-ls7a";
+};
+
+&package0 {
+        htvec: interrupt-controller@efdfb000080 {
+                compatible = "loongson,htvec-1.0";
+                reg = <0xefd 0xfb000080 0x40>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&liointc>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+                             <25 IRQ_TYPE_LEVEL_HIGH>,
+                             <26 IRQ_TYPE_LEVEL_HIGH>,
+                             <27 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
+
+&pch {
+        msi: msi-controller@2ff00000 {
+                compatible = "loongson,pch-msi-1.0";
+                reg = <0 0x2ff00000 0 0x8>;
+                interrupt-controller;
+                msi-controller;
+                loongson,msi-base-vec = <64>;
+                loongson,msi-num-vecs = <64>;
+                interrupt-parent = <&htvec>;
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
new file mode 100644
index 000000000..d681a295d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64c-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+        compatible = "loongson,loongson64c-4core-rs780e";
+};
+
+&package0 {
+        htpic: interrupt-controller@efdfb000080 {
+                compatible = "loongson,htpic-1.0";
+                reg = <0xefd 0xfb000080 0x40>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&liointc>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+                                <25 IRQ_TYPE_LEVEL_HIGH>,
+                                <26 IRQ_TYPE_LEVEL_HIGH>,
+                                <27 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
new file mode 100644
index 000000000..3c2044142
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64c-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+        compatible = "loongson,loongson64c-8core-rs780e";
+};
+
+&package0 {
+        htpic: interrupt-controller@1efdfb000080 {
+                compatible = "loongson,htpic-1.0";
+                reg = <0x1efd 0xfb000080 0x40>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&liointc>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+                                <25 IRQ_TYPE_LEVEL_HIGH>,
+                                <26 IRQ_TYPE_LEVEL_HIGH>,
+                                <27 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64g-package.dtsi b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
new file mode 100644
index 000000000..38abc570c
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        package0: bus@1fe00000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+                        0 0x3ff00000 0 0x3ff00000 0x100000
+                        0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
+
+                liointc: interrupt-controller@3ff01400 {
+                        compatible = "loongson,liointc-1.0";
+                        reg = <0 0x3ff01400 0x64>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>, <3>;
+                        interrupt-names = "int0", "int1";
+
+                        loongson,parent_int_map = <0x00ffffff>, /* int0 */
+                                                <0xff000000>, /* int1 */
+                                                <0x00000000>, /* int2 */
+                                                <0x00000000>; /* int3 */
+
+                };
+
+                cpu_uart0: serial@1fe001e0 {
+                        compatible = "ns16550a";
+                        reg = <0 0x1fe00100 0x10>;
+                        clock-frequency = <100000000>;
+                        interrupt-parent = <&liointc>;
+                        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                cpu_uart1: serial@1fe001e8 {
+                        status = "disabled";
+                        compatible = "ns16550a";
+                        reg = <0 0x1fe00110 0x10>;
+                        clock-frequency = <100000000>;
+                        interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-parent = <&liointc>;
+                        no-loopback-test;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
new file mode 100644
index 000000000..c945f8565
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64g-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+        compatible = "loongson,loongson64g-4core-ls7a";
+};
+
+&package0 {
+        htvec: interrupt-controller@efdfb000080 {
+                compatible = "loongson,htvec-1.0";
+                reg = <0xefd 0xfb000080 0x40>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&liointc>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+                             <25 IRQ_TYPE_LEVEL_HIGH>,
+                             <26 IRQ_TYPE_LEVEL_HIGH>,
+                             <27 IRQ_TYPE_LEVEL_HIGH>,
+                             <28 IRQ_TYPE_LEVEL_HIGH>,
+                             <29 IRQ_TYPE_LEVEL_HIGH>,
+                             <30 IRQ_TYPE_LEVEL_HIGH>,
+                             <31 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
+
+&pch {
+        msi: msi-controller@2ff00000 {
+                compatible = "loongson,pch-msi-1.0";
+                reg = <0 0x2ff00000 0 0x8>;
+                interrupt-controller;
+                msi-controller;
+                loongson,msi-base-vec = <64>;
+                loongson,msi-num-vecs = <192>;
+                interrupt-parent = <&htvec>;
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts b/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts
new file mode 100644
index 000000000..41f0b110d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/ {
+        compatible = "loongson,loongson64v-4core-virtio";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        package0: bus@1fe00000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+                        0 0x3ff00000 0 0x3ff00000 0x100000
+                        0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
+
+                liointc: interrupt-controller@3ff01400 {
+                        compatible = "loongson,liointc-1.0";
+                        reg = <0 0x3ff01400 0x64>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>, <3>;
+                        interrupt-names = "int0", "int1";
+
+                        loongson,parent_int_map = <0x00000001>, /* int0 */
+                                                <0xfffffffe>, /* int1 */
+                                                <0x00000000>, /* int2 */
+                                                <0x00000000>; /* int3 */
+
+                };
+
+                cpu_uart0: serial@1fe001e0 {
+                        compatible = "ns16550a";
+                        reg = <0 0x1fe001e0 0x8>;
+                        clock-frequency = <33000000>;
+                        interrupt-parent = <&liointc>;
+                        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+        };
+
+        bus@10000000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
+                                0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */
+
+                rtc0: rtc@10081000 {
+                        compatible = "google,goldfish-rtc";
+                        reg = <0 0x10081000 0 0x1000>;
+                        interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-parent = <&liointc>;
+                };
+
+                pci@1a000000 {
+                        compatible = "pci-host-ecam-generic";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+
+                        bus-range = <0x0 0x1f>;
+                        reg = <0 0x1a000000 0 0x02000000>;
+
+                        ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>,
+                                 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+                        interrupt-map = <
+                                0x0000 0x0 0x0  0x1  &liointc  0x2 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0x0 0x0  0x1  &liointc  0x3 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0x0 0x0  0x1  &liointc  0x4 IRQ_TYPE_LEVEL_HIGH
+                                0x1800 0x0 0x0  0x1  &liointc  0x5 IRQ_TYPE_LEVEL_HIGH
+                                >;
+
+                        interrupt-map-mask = <0x1800 0x0 0x0  0x7>;
+                };
+
+                isa {
+                        compatible = "isa";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <1 0 0 0x18000000 0x4000>;
+                };
+        };
+
+        hypervisor {
+                compatible = "linux,kvm";
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
new file mode 100644
index 000000000..f99a7a11f
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+        pch: bus@10000000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
+                                0 0x20000000 0 0x20000000 0 0x10000000
+                                0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
+                                0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
+
+                pic: interrupt-controller@10000000 {
+                        compatible = "loongson,pch-pic-1.0";
+                        reg = <0 0x10000000 0 0x400>;
+                        interrupt-controller;
+                        interrupt-parent = <&htvec>;
+                        loongson,pic-base-vec = <0>;
+                        #interrupt-cells = <2>;
+                };
+
+                ls7a_uart0: serial@10080000 {
+                        compatible = "ns16550a";
+                        reg = <0 0x10080000 0 0x100>;
+                        clock-frequency = <50000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                ls7a_uart1: serial@10080100 {
+                        status = "disabled";
+                        compatible = "ns16550a";
+                        reg = <0 0x10080100 0 0x100>;
+                        clock-frequency = <50000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                ls7a_uart2: serial@10080200 {
+                        status = "disabled";
+                        compatible = "ns16550a";
+                        reg = <0 0x10080200 0 0x100>;
+                        clock-frequency = <50000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                ls7a_uart3: serial@10080300 {
+                        status = "disabled";
+                        compatible = "ns16550a";
+                        reg = <0 0x10080300 0 0x100>;
+                        clock-frequency = <50000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                        no-loopback-test;
+                };
+
+                pci@1a000000 {
+                        compatible = "loongson,ls7a-pci";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <2>;
+                        msi-parent = <&msi>;
+
+                        reg = <0 0x1a000000 0 0x02000000>,
+                                <0xefe 0x00000000 0 0x20000000>;
+
+                        ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
+                                 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+                        ohci@4,0 {
+                                compatible = "pci0014,7a24.0",
+                                                   "pci0014,7a24",
+                                                   "pciclass0c0310",
+                                                   "pciclass0c03";
+
+                                reg = <0x2000 0x0 0x0 0x0 0x0>;
+                                interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        ehci@4,1 {
+                                compatible = "pci0014,7a14.0",
+                                                   "pci0014,7a14",
+                                                   "pciclass0c0320",
+                                                   "pciclass0c03";
+
+                                reg = <0x2100 0x0 0x0 0x0 0x0>;
+                                interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        ohci@5,0 {
+                                compatible = "pci0014,7a24.0",
+                                                   "pci0014,7a24",
+                                                   "pciclass0c0310",
+                                                   "pciclass0c03";
+
+                                reg = <0x2800 0x0 0x0 0x0 0x0>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        ehci@5,1 {
+                                compatible = "pci0014,7a14.0",
+                                                   "pci0014,7a14",
+                                                   "pciclass0c0320",
+                                                   "pciclass0c03";
+
+                                reg = <0x2900 0x0 0x0 0x0 0x0>;
+                                interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        sata@8,0 {
+                                compatible = "pci0014,7a08.0",
+                                                   "pci0014,7a08",
+                                                   "pciclass010601",
+                                                   "pciclass0106";
+
+                                reg = <0x4000 0x0 0x0 0x0 0x0>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        sata@8,1 {
+                                compatible = "pci0014,7a08.0",
+                                                   "pci0014,7a08",
+                                                   "pciclass010601",
+                                                   "pciclass0106";
+
+                                reg = <0x4100 0x0 0x0 0x0 0x0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        sata@8,2 {
+                                compatible = "pci0014,7a08.0",
+                                                   "pci0014,7a08",
+                                                   "pciclass010601",
+                                                   "pciclass0106";
+
+                                reg = <0x4200 0x0 0x0 0x0 0x0>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        gpu@6,0 {
+                                compatible = "pci0014,7a15.0",
+                                                   "pci0014,7a15",
+                                                   "pciclass030200",
+                                                   "pciclass0302";
+
+                                reg = <0x3000 0x0 0x0 0x0 0x0>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        dc@6,1 {
+                                compatible = "pci0014,7a06.0",
+                                                   "pci0014,7a06",
+                                                   "pciclass030000",
+                                                   "pciclass0300";
+
+                                reg = <0x3100 0x0 0x0 0x0 0x0>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        hda@7,0 {
+                                compatible = "pci0014,7a07.0",
+                                                   "pci0014,7a07",
+                                                   "pciclass040300",
+                                                   "pciclass0403";
+
+                                reg = <0x3800 0x0 0x0 0x0 0x0>;
+                                interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+                        };
+
+                        gmac@3,0 {
+                                compatible = "pci0014,7a03.0",
+                                                   "pci0014,7a03",
+                                                   "pciclass020000",
+                                                   "pciclass0200";
+
+                                reg = <0x1800 0x0 0x0 0x0 0x0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+                                             <13 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "macirq", "eth_lpi";
+                                interrupt-parent = <&pic>;
+                                phy-mode = "rgmii";
+                                mdio {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "snps,dwmac-mdio";
+                                        phy0: ethernet-phy@0 {
+                                                reg = <0>;
+                                        };
+                                };
+                        };
+
+                        gmac@3,1 {
+                                compatible = "pci0014,7a03.0",
+                                                   "pci0014,7a03",
+                                                   "pciclass020000",
+                                                   "pciclass0200";
+
+                                reg = <0x1900 0x0 0x0 0x0 0x0>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+                                             <15 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "macirq", "eth_lpi";
+                                interrupt-parent = <&pic>;
+                                phy-mode = "rgmii";
+                                mdio {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "snps,dwmac-mdio";
+                                        phy1: ethernet-phy@1 {
+                                                reg = <0>;
+                                        };
+                                };
+                        };
+
+                        pci_bridge@9,0 {
+                                compatible = "pci0014,7a19.1",
+                                                   "pci0014,7a19",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x4800 0x0 0x0 0x0 0x0>;
+                                interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@a,0 {
+                                compatible = "pci0014,7a09.1",
+                                                   "pci0014,7a09",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x5000 0x0 0x0 0x0 0x0>;
+                                interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@b,0 {
+                                compatible = "pci0014,7a09.1",
+                                                   "pci0014,7a09",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x5800 0x0 0x0 0x0 0x0>;
+                                interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@c,0 {
+                                compatible = "pci0014,7a09.1",
+                                                   "pci0014,7a09",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x6000 0x0 0x0 0x0 0x0>;
+                                interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@d,0 {
+                                compatible = "pci0014,7a19.1",
+                                                   "pci0014,7a19",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x6800 0x0 0x0 0x0 0x0>;
+                                interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@e,0 {
+                                compatible = "pci0014,7a09.1",
+                                                   "pci0014,7a09",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x7000 0x0 0x0 0x0 0x0>;
+                                interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@f,0 {
+                                compatible = "pci0014,7a29.1",
+                                                   "pci0014,7a29",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x7800 0x0 0x0 0x0 0x0>;
+                                interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@10,0 {
+                                compatible = "pci0014,7a19.1",
+                                                   "pci0014,7a19",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x8000 0x0 0x0 0x0 0x0>;
+                                interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@11,0 {
+                                compatible = "pci0014,7a29.1",
+                                                   "pci0014,7a29",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x8800 0x0 0x0 0x0 0x0>;
+                                interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@12,0 {
+                                compatible = "pci0014,7a19.1",
+                                                   "pci0014,7a19",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x9000 0x0 0x0 0x0 0x0>;
+                                interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@13,0 {
+                                compatible = "pci0014,7a29.1",
+                                                   "pci0014,7a29",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0x9800 0x0 0x0 0x0 0x0>;
+                                interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        pci_bridge@14,0 {
+                                compatible = "pci0014,7a19.1",
+                                                   "pci0014,7a19",
+                                                   "pciclass060400",
+                                                   "pciclass0604";
+
+                                reg = <0xa000 0x0 0x0 0x0 0x0>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&pic>;
+
+                                #interrupt-cells = <1>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                isa {
+                        compatible = "isa";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <1 0 0 0x18000000 0x20000>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000..871c866e0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+        bus@10000000 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+                                0 0x40000000 0 0x40000000 0 0x40000000
+                                0xfd 0xfe000000 0xfd 0xfe000000  0 0x2000000 /* PCI Config Space */>;
+
+                pci@1a000000 {
+                        compatible = "loongson,rs780e-pci";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        reg = <0 0x1a000000 0 0x02000000>;
+
+                        ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
+                                 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+                };
+
+                isa {
+                        compatible = "isa";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <1 0 0 0x18000000 0x4000>;
+
+                        rtc0: rtc@70 {
+                                compatible = "motorola,mc146818";
+                                reg = <1 0x70 0x8>;
+                                interrupts = <8>;
+                                interrupt-parent = <&htpic>;
+                        };
+
+                        acpi@800 {
+                                compatible = "loongson,rs780e-acpi";
+                                reg = <1 0x800 0x100>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
new file mode 100644
index 000000000..eb7151587
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_MSCC_OCELOT)       += ocelot_pcb123.dtb ocelot_pcb120.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000..535a98284
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "mscc,ocelot";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "mips,mips24KEc";
+                        device_type = "cpu";
+                        clocks = <&cpu_clk>;
+                        reg = <0>;
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        cpu_clk: cpu-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+        };
+
+        ahb_clk: ahb-clk {
+                compatible = "fixed-factor-clock";
+                #clock-cells = <0>;
+                clocks = <&cpu_clk>;
+                clock-div = <2>;
+                clock-mult = <1>;
+        };
+
+        ahb@70000000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x70000000 0x2000000>;
+
+                interrupt-parent = <&intc>;
+
+                cpu_ctrl: syscon@0 {
+                        compatible = "mscc,ocelot-cpu-syscon", "syscon";
+                        reg = <0x0 0x2c>;
+                };
+
+                intc: interrupt-controller@70 {
+                        compatible = "mscc,ocelot-icpu-intr";
+                        reg = <0x70 0x70>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                uart0: serial@100000 {
+                        pinctrl-0 = <&uart_pins>;
+                        pinctrl-names = "default";
+                        compatible = "ns16550a";
+                        reg = <0x100000 0x20>;
+                        interrupts = <6>;
+                        clocks = <&ahb_clk>;
+                        reg-io-width = <4>;
+                        reg-shift = <2>;
+
+                        status = "disabled";
+                };
+
+                i2c: i2c@100400 {
+                        compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+                        pinctrl-0 = <&i2c_pins>;
+                        pinctrl-names = "default";
+                        reg = <0x100400 0x100>, <0x198 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <8>;
+                        clocks = <&ahb_clk>;
+
+                        status = "disabled";
+                };
+
+                uart2: serial@100800 {
+                        pinctrl-0 = <&uart2_pins>;
+                        pinctrl-names = "default";
+                        compatible = "ns16550a";
+                        reg = <0x100800 0x20>;
+                        interrupts = <7>;
+                        clocks = <&ahb_clk>;
+                        reg-io-width = <4>;
+                        reg-shift = <2>;
+
+                        status = "disabled";
+                };
+
+                spi: spi@101000 {
+                        compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x101000 0x100>, <0x3c 0x18>;
+                        interrupts = <9>;
+                        clocks = <&ahb_clk>;
+
+                        status = "disabled";
+                };
+
+                switch@1010000 {
+                        compatible = "mscc,vsc7514-switch";
+                        reg = <0x1010000 0x10000>,
+                              <0x1030000 0x10000>,
+                              <0x1080000 0x100>,
+                              <0x10e0000 0x10000>,
+                              <0x11e0000 0x100>,
+                              <0x11f0000 0x100>,
+                              <0x1200000 0x100>,
+                              <0x1210000 0x100>,
+                              <0x1220000 0x100>,
+                              <0x1230000 0x100>,
+                              <0x1240000 0x100>,
+                              <0x1250000 0x100>,
+                              <0x1260000 0x100>,
+                              <0x1270000 0x100>,
+                              <0x1280000 0x100>,
+                              <0x1800000 0x80000>,
+                              <0x1880000 0x10000>,
+                              <0x1040000 0x10000>,
+                              <0x1050000 0x10000>,
+                              <0x1060000 0x10000>;
+                        reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
+                                    "port2", "port3", "port4", "port5", "port6",
+                                    "port7", "port8", "port9", "port10", "qsys",
+                                    "ana", "s0", "s1", "s2";
+                        interrupts = <18 21 22>;
+                        interrupt-names = "ptp_rdy", "xtr", "inj";
+
+                        ethernet-ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port0: port@0 {
+                                        reg = <0>;
+                                };
+                                port1: port@1 {
+                                        reg = <1>;
+                                };
+                                port2: port@2 {
+                                        reg = <2>;
+                                };
+                                port3: port@3 {
+                                        reg = <3>;
+                                };
+                                port4: port@4 {
+                                        reg = <4>;
+                                };
+                                port5: port@5 {
+                                        reg = <5>;
+                                };
+                                port6: port@6 {
+                                        reg = <6>;
+                                };
+                                port7: port@7 {
+                                        reg = <7>;
+                                };
+                                port8: port@8 {
+                                        reg = <8>;
+                                };
+                                port9: port@9 {
+                                        reg = <9>;
+                                };
+                                port10: port@10 {
+                                        reg = <10>;
+                                };
+                        };
+                };
+
+                reset@1070008 {
+                        compatible = "mscc,ocelot-chip-reset";
+                        reg = <0x1070008 0x4>;
+                };
+
+                gpio: pinctrl@1070034 {
+                        compatible = "mscc,ocelot-pinctrl";
+                        reg = <0x1070034 0x68>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&gpio 0 0 22>;
+                        interrupt-controller;
+                        interrupts = <13>;
+                        #interrupt-cells = <2>;
+
+                        i2c_pins: i2c-pins {
+                                pins = "GPIO_16", "GPIO_17";
+                                function = "twi";
+                        };
+
+                        uart_pins: uart-pins {
+                                pins = "GPIO_6", "GPIO_7";
+                                function = "uart";
+                        };
+
+                        uart2_pins: uart2-pins {
+                                pins = "GPIO_12", "GPIO_13";
+                                function = "uart2";
+                        };
+
+                        miim1: miim1 {
+                                pins = "GPIO_14", "GPIO_15";
+                                function = "miim";
+                        };
+
+                };
+
+                mdio0: mdio@107009c {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "mscc,ocelot-miim";
+                        reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+                        interrupts = <14>;
+                        status = "disabled";
+
+                        phy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                reg = <2>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                reg = <3>;
+                        };
+                };
+
+                mdio1: mdio@10700c0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "mscc,ocelot-miim";
+                        reg = <0x10700c0 0x24>;
+                        interrupts = <15>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&miim1>;
+                        status = "disabled";
+                };
+
+                hsio: syscon@10d0000 {
+                        compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+                        reg = <0x10d0000 0x10000>;
+
+                        serdes: serdes {
+                                compatible = "mscc,vsc7514-serdes";
+                                #phy-cells = <2>;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
new file mode 100644
index 000000000..897de5025
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy-ocelot-serdes.h>
+#include "ocelot.dtsi"
+
+/ {
+        compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0e000000>;
+        };
+};
+
+&gpio {
+        phy_int_pins: phy_int_pins {
+                pins = "GPIO_4";
+                function = "gpio";
+        };
+
+        phy_load_save_pins: phy_load_save_pins {
+                pins = "GPIO_10";
+                function = "ptp2";
+        };
+};
+
+&mdio0 {
+        status = "okay";
+};
+
+&mdio1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+
+        phy7: ethernet-phy@0 {
+                reg = <0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&gpio>;
+                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+        };
+        phy6: ethernet-phy@1 {
+                reg = <1>;
+                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&gpio>;
+                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+        };
+        phy5: ethernet-phy@2 {
+                reg = <2>;
+                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&gpio>;
+                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+        };
+        phy4: ethernet-phy@3 {
+                reg = <3>;
+                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&gpio>;
+                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&port0 {
+        phy-handle = <&phy0>;
+};
+
+&port1 {
+        phy-handle = <&phy1>;
+};
+
+&port2 {
+        phy-handle = <&phy2>;
+};
+
+&port3 {
+        phy-handle = <&phy3>;
+};
+
+&port4 {
+        phy-handle = <&phy7>;
+        phy-mode = "sgmii";
+        phys = <&serdes 4 SERDES1G(2)>;
+};
+
+&port5 {
+        phy-handle = <&phy4>;
+        phy-mode = "sgmii";
+        phys = <&serdes 5 SERDES1G(5)>;
+};
+
+&port6 {
+        phy-handle = <&phy6>;
+        phy-mode = "sgmii";
+        phys = <&serdes 6 SERDES1G(3)>;
+};
+
+&port9 {
+        phy-handle = <&phy5>;
+        phy-mode = "sgmii";
+        phys = <&serdes 9 SERDES1G(4)>;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
new file mode 100644
index 000000000..ef852f382
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include "ocelot.dtsi"
+
+/ {
+        compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0e000000>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&spi {
+        status = "okay";
+
+        flash@0 {
+                compatible = "macronix,mx25l25635f", "jedec,spi-nor";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c {
+        clock-frequency = <100000>;
+        i2c-sda-hold-time-ns = <300>;
+        status = "okay";
+};
+
+&mdio0 {
+        status = "okay";
+};
+
+&port0 {
+        phy-handle = <&phy0>;
+};
+
+&port1 {
+        phy-handle = <&phy1>;
+};
+
+&port2 {
+        phy-handle = <&phy2>;
+};
+
+&port3 {
+        phy-handle = <&phy3>;
+};
diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
new file mode 100644
index 000000000..b5f742699
--- /dev/null
+++ b/arch/mips/boot/dts/mti/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_MIPS_MALTA)        += malta.dtb
+dtb-$(CONFIG_LEGACY_BOARD_SEAD3)        += sead3.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
new file mode 100644
index 000000000..f03279b1c
--- /dev/null
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/memreserve/ 0x00000000 0x00001000;     /* YAMON exception vectors */
+/memreserve/ 0x00001000 0x000ef000;     /* YAMON */
+/memreserve/ 0x000f0000 0x00010000;     /* PIIX4 ISA memory */
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "mti,malta";
+
+        cpu_intc: interrupt-controller {
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        gic: interrupt-controller@1bdc0000 {
+                compatible = "mti,gic";
+                reg = <0x1bdc0000 0x20000>;
+
+                interrupt-controller;
+                #interrupt-cells = <3>;
+
+                /*
+                 * Declare the interrupt-parent even though the mti,gic
+                 * binding doesn't require it, such that the kernel can
+                 * figure out that cpu_intc is the root interrupt
+                 * controller & should be probed first.
+                 */
+                interrupt-parent = <&cpu_intc>;
+
+                timer {
+                        compatible = "mti,gic-timer";
+                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+                };
+        };
+
+        i8259: interrupt-controller@20 {
+                compatible = "intel,i8259";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        flash@1e000000 {
+                compatible = "intel,dt28f160", "cfi-flash";
+                reg = <0x1e000000 0x400000>;
+                bank-width = <4>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        yamon@0 {
+                                label = "YAMON";
+                                reg = <0x0 0x100000>;
+                                read-only;
+                        };
+
+                        user-fs@100000 {
+                                label = "User FS";
+                                reg = <0x100000 0x2e0000>;
+                        };
+
+                        board-config@3e0000 {
+                                label = "Board Config";
+                                reg = <0x3e0000 0x20000>;
+                                read-only;
+                        };
+                };
+        };
+
+        fpga_regs: system-controller@1f000000 {
+                compatible = "mti,malta-fpga", "syscon", "simple-mfd";
+                reg = <0x1f000000 0x1000>;
+                native-endian;
+
+                lcd@410 {
+                        compatible = "mti,malta-lcd";
+                        offset = <0x410>;
+                };
+
+                reboot {
+                        compatible = "syscon-reboot";
+                        regmap = <&fpga_regs>;
+                        offset = <0x500>;
+                        mask = <0x42>;
+                };
+        };
+
+        isa {
+                compatible = "isa";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <1 0 0 0x1000>;
+
+                rtc@70 {
+                        compatible = "motorola,mc146818";
+                        reg = <1 0x70 0x8>;
+
+                        interrupt-parent = <&i8259>;
+                        interrupts = <8>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts
new file mode 100644
index 000000000..192c26ff1
--- /dev/null
+++ b/arch/mips/boot/dts/mti/sead3.dts
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000;     // reserved
+/memreserve/ 0x00001000 0x000ef000;     // ROM data
+/memreserve/ 0x000f0000 0x004cc000;     // reserved
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "mti,sead-3";
+        model = "MIPS SEAD-3";
+
+        chosen {
+                stdout-path = "serial1:115200";
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "mti,mips14KEc", "mti,mips14Kc";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x08000000>;
+        };
+
+        cpu_intc: interrupt-controller {
+                compatible = "mti,cpu-interrupt-controller";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        gic: interrupt-controller@1b1c0000 {
+                compatible = "mti,gic";
+                reg = <0x1b1c0000 0x20000>;
+
+                interrupt-controller;
+                #interrupt-cells = <3>;
+
+                /*
+                 * Declare the interrupt-parent even though the mti,gic
+                 * binding doesn't require it, such that the kernel can
+                 * figure out that cpu_intc is the root interrupt
+                 * controller & should be probed first.
+                 */
+                interrupt-parent = <&cpu_intc>;
+        };
+
+        ehci@1b200000 {
+                compatible = "generic-ehci";
+                reg = <0x1b200000 0x1000>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
+
+                has-transaction-translator;
+        };
+
+        flash@1c000000 {
+                compatible = "intel,28f128j3", "cfi-flash";
+                reg = <0x1c000000 0x2000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                bank-width = <4>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        user-fs@0 {
+                                label = "User FS";
+                                reg = <0x0 0x1fc0000>;
+                        };
+
+                        board-config@3e0000 {
+                                label = "Board Config";
+                                reg = <0x1fc0000 0x40000>;
+                        };
+                };
+        };
+
+        fpga_regs: system-controller@1f000000 {
+                compatible = "mti,sead3-fpga", "syscon", "simple-mfd";
+                reg = <0x1f000000 0x200>;
+
+                reboot {
+                        compatible = "syscon-reboot";
+                        regmap = <&fpga_regs>;
+                        offset = <0x50>;
+                        mask = <0x4d>;
+                };
+
+                poweroff {
+                        compatible = "restart-poweroff";
+                };
+        };
+
+        system-controller@1f000200 {
+                compatible = "mti,sead3-cpld", "syscon", "simple-mfd";
+                reg = <0x1f000200 0x300>;
+
+                led@10.0 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x1>;
+                        label = "pled0";
+                };
+                led@10.1 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x2>;
+                        label = "pled1";
+                };
+                led@10.2 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x4>;
+                        label = "pled2";
+                };
+                led@10.3 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x8>;
+                        label = "pled3";
+                };
+                led@10.4 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x10>;
+                        label = "pled4";
+                };
+                led@10.5 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x20>;
+                        label = "pled5";
+                };
+                led@10.6 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x40>;
+                        label = "pled6";
+                };
+                led@10.7 {
+                        compatible = "register-bit-led";
+                        offset = <0x10>;
+                        mask = <0x80>;
+                        label = "pled7";
+                };
+
+                led@18.0 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x1>;
+                        label = "fled0";
+                };
+                led@18.1 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x2>;
+                        label = "fled1";
+                };
+                led@18.2 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x4>;
+                        label = "fled2";
+                };
+                led@18.3 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x8>;
+                        label = "fled3";
+                };
+                led@18.4 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x10>;
+                        label = "fled4";
+                };
+                led@18.5 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x20>;
+                        label = "fled5";
+                };
+                led@18.6 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x40>;
+                        label = "fled6";
+                };
+                led@18.7 {
+                        compatible = "register-bit-led";
+                        offset = <0x18>;
+                        mask = <0x80>;
+                        label = "fled7";
+                };
+
+                lcd@200 {
+                        compatible = "mti,sead3-lcd";
+                        offset = <0x200>;
+                };
+        };
+
+        /* UART connected to FTDI & miniUSB socket */
+        uart0: uart@1f000900 {
+                compatible = "ns16550a";
+                reg = <0x1f000900 0x20>;
+                reg-io-width = <4>;
+                reg-shift = <2>;
+
+                clock-frequency = <14745600>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
+
+                no-loopback-test;
+        };
+
+        /* UART connected to RS232 socket */
+        uart1: uart@1f000800 {
+                compatible = "ns16550a";
+                reg = <0x1f000800 0x20>;
+                reg-io-width = <4>;
+                reg-shift = <2>;
+
+                clock-frequency = <14745600>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
+
+                no-loopback-test;
+        };
+
+        eth@1f010000 {
+                compatible = "smsc,lan9115";
+                reg = <0x1f010000 0x10000>;
+                reg-io-width = <4>;
+
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
+
+                phy-mode = "mii";
+                smsc,irq-push-pull;
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/mips/boot/dts/netlogic/Makefile b/arch/mips/boot/dts/netlogic/Makefile
new file mode 100644
index 000000000..45af42244
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DT_XLP_EVP)        += xlp_evp.dtb
+dtb-$(CONFIG_DT_XLP_SVP)        += xlp_svp.dtb
+dtb-$(CONFIG_DT_XLP_FVP)        += xlp_fvp.dtb
+dtb-$(CONFIG_DT_XLP_GVP)        += xlp_gvp.dtb
+dtb-$(CONFIG_DT_XLP_RVP)        += xlp_rvp.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/netlogic/xlp_evp.dts b/arch/mips/boot/dts/netlogic/xlp_evp.dts
new file mode 100644
index 000000000..e63e55926
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_evp.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XLP8XX Device Tree Source for EVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-EVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x30100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                serial1: serial@31000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x31100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <18>;
+                };
+                i2c0: ocores@32000 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x32100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <30>;
+                };
+                i2c1: ocores@33000 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x33100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <31>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1374";
+                                reg = <0x68>;
+                        };
+
+                        dtt@4c {
+                                compatible = "national,lm90";
+                                reg = <0x4c>;
+                        };
+                };
+                pic: pic@4000 {
+                        compatible = "netlogic,xlp-pic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x4000 0x200>;
+                        interrupt-controller;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+                gpio: xlp_gpio@34100 {
+                        compatible = "netlogic,xlp832-gpio";
+                        reg = <0 0x34100 0x1000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <39>;
+                        interrupt-controller;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/boot/dts/netlogic/xlp_fvp.dts b/arch/mips/boot/dts/netlogic/xlp_fvp.dts
new file mode 100644
index 000000000..d05abf13f
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_fvp.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XLP2XX Device Tree Source for FVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-FVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x30100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                serial1: serial@31000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x31100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <18>;
+                };
+                i2c0: ocores@37100 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x37100 0x20>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <30>;
+                };
+                i2c1: ocores@37120 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x37120 0x20>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <31>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1374";
+                                reg = <0x68>;
+                        };
+
+                        dtt@4c {
+                                compatible = "national,lm90";
+                                reg = <0x4c>;
+                        };
+                };
+                pic: pic@4000 {
+                        compatible = "netlogic,xlp-pic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x4000 0x200>;
+                        interrupt-controller;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+                gpio: xlp_gpio@34100 {
+                        compatible = "netlogic,xlp208-gpio";
+                        reg = <0 0x34100 0x1000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <39>;
+                        interrupt-controller;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/boot/dts/netlogic/xlp_gvp.dts b/arch/mips/boot/dts/netlogic/xlp_gvp.dts
new file mode 100644
index 000000000..d47de4851
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_gvp.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XLP9XX Device Tree Source for GVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-GVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x112100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <125000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                pic: pic@110000 {
+                        compatible = "netlogic,xlp-pic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x110000 0x200>;
+                        interrupt-controller;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+                gpio: xlp_gpio@114100 {
+                        compatible = "netlogic,xlp980-gpio";
+                        reg = <0 0x114100 0x1000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <39>;
+                        interrupt-controller;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/boot/dts/netlogic/xlp_rvp.dts b/arch/mips/boot/dts/netlogic/xlp_rvp.dts
new file mode 100644
index 000000000..aa0faee19
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_rvp.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XLP5XX Device Tree Source for RVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-RVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x112100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <125000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                pic: pic@110000 {
+                        compatible = "netlogic,xlp-pic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x110000 0x200>;
+                        interrupt-controller;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+                gpio: xlp_gpio@114100 {
+                        compatible = "netlogic,xlp532-gpio";
+                        reg = <0 0x114100 0x1000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <39>;
+                        interrupt-controller;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/boot/dts/netlogic/xlp_svp.dts b/arch/mips/boot/dts/netlogic/xlp_svp.dts
new file mode 100644
index 000000000..3bb0b2e08
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_svp.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * XLP3XX Device Tree Source for SVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-SVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x30100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                serial1: serial@31000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x31100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <133333333>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <18>;
+                };
+                i2c0: ocores@32000 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x32100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <30>;
+                };
+                i2c1: ocores@33000 {
+                        compatible = "opencores,i2c-ocores";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0x33100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <32000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <31>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1374";
+                                reg = <0x68>;
+                        };
+
+                        dtt@4c {
+                                compatible = "national,lm90";
+                                reg = <0x4c>;
+                        };
+                };
+                pic: pic@4000 {
+                        compatible = "netlogic,xlp-pic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x4000 0x200>;
+                        interrupt-controller;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+                gpio: xlp_gpio@34100 {
+                        compatible = "netlogic,xlp316-gpio";
+                        reg = <0 0x34100 0x1000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <39>;
+                        interrupt-controller;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
new file mode 100644
index 000000000..5389ef46c
--- /dev/null
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -0,0 +1,100 @@
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ni,169445";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mti,mips14KEc";
+                        clocks = <&baseclk>;
+                        reg = <0>;
+                };
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x10000000>;
+        };
+
+        baseclk: baseclock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ahb@1f300000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x1f300000 0x80FFF>;
+
+                gpio1: gpio@10 {
+                        compatible = "ni,169445-nand-gpio";
+                        reg = <0x10 0x4>;
+                        reg-names = "dat";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpio2: gpio@14 {
+                        compatible = "ni,169445-nand-gpio";
+                        reg = <0x14 0x4>;
+                        reg-names = "dat";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        no-output;
+                };
+
+                nand@0 {
+                        compatible = "gpio-control-nand";
+                        nand-on-flash-bbt;
+                        nand-ecc-mode = "soft_bch";
+                        nand-ecc-step-size = <512>;
+                        nand-ecc-strength = <4>;
+                        reg = <0x0 4>;
+                        gpios = <&gpio2 0 0>, /* rdy */
+                                <&gpio1 1 0>, /* nce */
+                                <&gpio1 2 0>, /* ale */
+                                <&gpio1 3 0>, /* cle */
+                                <&gpio1 4 0>; /* nwp */
+                };
+
+                serial@80000 {
+                        compatible = "ns16550a";
+                        reg = <0x80000 0x1000>;
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <6>;
+                        clocks = <&baseclk>;
+                        reg-shift = <0>;
+                };
+
+                ethernet@40000 {
+                        compatible = "snps,dwmac-4.10a";
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <5>;
+                        interrupt-names = "macirq";
+                        reg = <0x40000 0x2000>;
+                        clock-names = "stmmaceth", "pclk";
+                        clocks = <&baseclk>, <&baseclk>;
+
+                        phy-mode = "rgmii";
+
+                        fixed-link {
+                                speed = <1000>;
+                                full-duplex;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
new file mode 100644
index 000000000..93867e1a5
--- /dev/null
+++ b/arch/mips/boot/dts/ni/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445)    += 169445.dtb
diff --git a/arch/mips/boot/dts/pic32/Makefile b/arch/mips/boot/dts/pic32/Makefile
new file mode 100644
index 000000000..fb57f3632
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_PIC32_MZDA_SK)         += pic32mzda_sk.dtb
+
+dtb-$(CONFIG_DTB_PIC32_NONE)            += \
+                                        pic32mzda_sk.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/pic32/pic32mzda.dtsi b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
new file mode 100644
index 000000000..f1e3dad6b
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ */
+#include <dt-bindings/clock/microchip,pic32-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&evic>;
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+                gpio3 = &gpio3;
+                gpio4 = &gpio4;
+                gpio5 = &gpio5;
+                gpio6 = &gpio6;
+                gpio7 = &gpio7;
+                gpio8 = &gpio8;
+                gpio9 = &gpio9;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "mti,mips14KEc";
+                        device_type = "cpu";
+                };
+        };
+
+        soc {
+                compatible = "microchip,pic32mzda-infra";
+                interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+        };
+
+        /* external clock input on TxCLKI pin */
+        txcki: txcki_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <4000000>;
+                status = "disabled";
+        };
+
+        /* external input on REFCLKIx pin */
+        refix: refix_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                status = "disabled";
+        };
+
+        rootclk: clock-controller@1f801200 {
+                compatible = "microchip,pic32mzda-clk";
+                reg = <0x1f801200 0x200>;
+                #clock-cells = <1>;
+                microchip,pic32mzda-sosc;
+        };
+
+        evic: interrupt-controller@1f810000 {
+                compatible = "microchip,pic32mzda-evic";
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0x1f810000 0x1000>;
+                microchip,external-irqs = <3 8 13 18 23>;
+        };
+
+        pic32_pinctrl: pinctrl@1f801400{
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "microchip,pic32mzda-pinctrl";
+                reg = <0x1f801400 0x400>;
+                clocks = <&rootclk PB1CLK>;
+        };
+
+        /* PORTA */
+        gpio0: gpio0@1f860000 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860000 0x100>;
+                interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <0>;
+                gpio-ranges = <&pic32_pinctrl 0 0 16>;
+        };
+
+        /* PORTB */
+        gpio1: gpio1@1f860100 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860100 0x100>;
+                interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <1>;
+                gpio-ranges = <&pic32_pinctrl 0 16 16>;
+        };
+
+        /* PORTC */
+        gpio2: gpio2@1f860200 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860200 0x100>;
+                interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <2>;
+                gpio-ranges = <&pic32_pinctrl 0 32 16>;
+        };
+
+        /* PORTD */
+        gpio3: gpio3@1f860300 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860300 0x100>;
+                interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <3>;
+                gpio-ranges = <&pic32_pinctrl 0 48 16>;
+        };
+
+        /* PORTE */
+        gpio4: gpio4@1f860400 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860400 0x100>;
+                interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <4>;
+                gpio-ranges = <&pic32_pinctrl 0 64 16>;
+        };
+
+        /* PORTF */
+        gpio5: gpio5@1f860500 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860500 0x100>;
+                interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <5>;
+                gpio-ranges = <&pic32_pinctrl 0 80 16>;
+        };
+
+        /* PORTG */
+        gpio6: gpio6@1f860600 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860600 0x100>;
+                interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <6>;
+                gpio-ranges = <&pic32_pinctrl 0 96 16>;
+        };
+
+        /* PORTH */
+        gpio7: gpio7@1f860700 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860700 0x100>;
+                interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <7>;
+                gpio-ranges = <&pic32_pinctrl 0 112 16>;
+        };
+
+        /* PORTI does not exist */
+
+        /* PORTJ */
+        gpio8: gpio8@1f860800 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860800 0x100>;
+                interrupts = <126 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <8>;
+                gpio-ranges = <&pic32_pinctrl 0 128 16>;
+        };
+
+        /* PORTK */
+        gpio9: gpio9@1f860900 {
+                compatible = "microchip,pic32mzda-gpio";
+                reg = <0x1f860900 0x100>;
+                interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                clocks = <&rootclk PB4CLK>;
+                microchip,gpio-bank = <9>;
+                gpio-ranges = <&pic32_pinctrl 0 144 16>;
+        };
+
+        sdhci: sdhci@1f8ec000 {
+                compatible = "microchip,pic32mzda-sdhci";
+                reg = <0x1f8ec000 0x100>;
+                interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
+                clock-names = "base_clk", "sys_clk";
+                bus-width = <4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        uart1: serial@1f822000 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822000 0x50>;
+                interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
+                        <113 IRQ_TYPE_LEVEL_HIGH>,
+                        <114 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+
+        uart2: serial@1f822200 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822200 0x50>;
+                interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
+                        <146 IRQ_TYPE_LEVEL_HIGH>,
+                        <147 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+
+        uart3: serial@1f822400 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822400 0x50>;
+                interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
+                        <158 IRQ_TYPE_LEVEL_HIGH>,
+                        <159 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+
+        uart4: serial@1f822600 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822600 0x50>;
+                interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
+                        <171 IRQ_TYPE_LEVEL_HIGH>,
+                        <172 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+
+        uart5: serial@1f822800 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822800 0x50>;
+                interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
+                        <180 IRQ_TYPE_LEVEL_HIGH>,
+                        <181 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+
+        uart6: serial@1f822A00 {
+                compatible = "microchip,pic32mzda-uart";
+                reg = <0x1f822A00 0x50>;
+                interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
+                        <189 IRQ_TYPE_LEVEL_HIGH>,
+                        <190 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&rootclk PB2CLK>;
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
new file mode 100644
index 000000000..d7fa5d55d
--- /dev/null
+++ b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "pic32mzda.dtsi"
+
+/ {
+        compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda";
+        model = "Microchip PIC32MZDA Starter Kit";
+
+        memory {
+                device_type = "memory";
+                reg = <0x08000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "earlyprintk=ttyPIC1,115200n8r console=ttyPIC1,115200n8";
+        };
+
+        leds0 {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+
+                led@1 {
+                        label = "pic32mzda_sk:red:led1";
+                        gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led@2 {
+                        label = "pic32mzda_sk:yellow:led2";
+                        gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                };
+
+                led@3 {
+                        label = "pic32mzda_sk:green:led3";
+                        gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        keys0 {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&user_buttons_s0>;
+                pinctrl-names = "default";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@sw1 {
+                        label = "ESC";
+                        linux,code = <1>;
+                        gpios = <&gpio1 12 0>;
+                };
+
+                button@sw2 {
+                        label = "Home";
+                        linux,code = <102>;
+                        gpios = <&gpio1 13 0>;
+                };
+
+                button@sw3 {
+                        label = "Menu";
+                        linux,code = <139>;
+                        gpios = <&gpio1 14 0>;
+                };
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
+
+&sdhci {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sdhc1>;
+        status = "okay";
+        assigned-clocks = <&rootclk REF2CLK>, <&rootclk REF4CLK>,
+                <&rootclk REF5CLK>;
+        assigned-clock-rates = <50000000>, <25000000>, <40000000>;
+};
+
+&pic32_pinctrl {
+
+        pinctrl_sdhc1: sdhc1_pins0 {
+                pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0";
+                microchip,digital;
+        };
+
+        user_leds_s0: user_leds_s0 {
+                pins = "H0", "H1", "H2";
+                output-low;
+                microchip,digital;
+        };
+
+        user_buttons_s0: user_buttons_s0 {
+                pins = "B12", "B13", "B14";
+                microchip,digital;
+                input-enable;
+                bias-pull-up;
+        };
+
+        pinctrl_uart2: pinctrl_uart2 {
+                uart2-tx {
+                        pins = "G9";
+                        function = "U2TX";
+                        microchip,digital;
+                        output-high;
+                };
+                uart2-rx {
+                        pins = "B0";
+                        function = "U2RX";
+                        microchip,digital;
+                        input-enable;
+                };
+        };
+
+        pinctrl_uart4: uart4-0 {
+                uart4-tx {
+                        pins = "C3";
+                        function = "U4TX";
+                        microchip,digital;
+                        output-high;
+                };
+                uart4-rx {
+                        pins = "E8";
+                        function = "U4RX";
+                        microchip,digital;
+                        input-enable;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
new file mode 100644
index 000000000..4451cf45b
--- /dev/null
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+# All DTBs
+dtb-$(CONFIG_ATH79)                     += ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)                     += ar9331_dpt_module.dtb
+dtb-$(CONFIG_ATH79)                     += ar9331_dragino_ms14.dtb
+dtb-$(CONFIG_ATH79)                     += ar9331_omega.dtb
+dtb-$(CONFIG_ATH79)                     += ar9331_tl_mr3020.dtb
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
new file mode 100644
index 000000000..61dcfa5b6
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+        compatible = "qca,ar9132";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mips,mips24Kc";
+                        clocks = <&pll ATH79_CLK_CPU>;
+                        reg = <0>;
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
+                qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
+                                        <&ddr_ctrl 0>, <&ddr_ctrl 1>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                ranges;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+
+                apb {
+                        compatible = "simple-bus";
+                        ranges;
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        interrupt-parent = <&miscintc>;
+
+                        ddr_ctrl: memory-controller@18000000 {
+                                compatible = "qca,ar9132-ddr-controller",
+                                                "qca,ar7240-ddr-controller";
+                                reg = <0x18000000 0x100>;
+
+                                #qca,ddr-wb-channel-cells = <1>;
+                        };
+
+                        uart: uart@18020000 {
+                                compatible = "ns8250";
+                                reg = <0x18020000 0x20>;
+                                interrupts = <3>;
+
+                                clocks = <&pll ATH79_CLK_AHB>;
+                                clock-names = "uart";
+
+                                reg-io-width = <4>;
+                                reg-shift = <2>;
+                                no-loopback-test;
+
+                                status = "disabled";
+                        };
+
+                        gpio: gpio@18040000 {
+                                compatible = "qca,ar9132-gpio",
+                                                "qca,ar7100-gpio";
+                                reg = <0x18040000 0x30>;
+                                interrupts = <2>;
+
+                                ngpios = <22>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        pll: pll-controller@18050000 {
+                                compatible = "qca,ar9132-pll",
+                                                "qca,ar9130-pll";
+                                reg = <0x18050000 0x20>;
+
+                                clock-names = "ref";
+                                /* The board must provides the ref clock */
+
+                                #clock-cells = <1>;
+                                clock-output-names = "cpu", "ddr", "ahb";
+                        };
+
+                        wdt: wdt@18060008 {
+                                compatible = "qca,ar7130-wdt";
+                                reg = <0x18060008 0x8>;
+
+                                interrupts = <4>;
+
+                                clocks = <&pll ATH79_CLK_AHB>;
+                                clock-names = "wdt";
+                        };
+
+                        miscintc: interrupt-controller@18060010 {
+                                compatible = "qca,ar9132-misc-intc",
+                                           "qca,ar7100-misc-intc";
+                                reg = <0x18060010 0x8>;
+
+                                interrupt-parent = <&cpuintc>;
+                                interrupts = <6>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        rst: reset-controller@1806001c {
+                                compatible = "qca,ar9132-reset",
+                                                "qca,ar7100-reset";
+                                reg = <0x1806001c 0x4>;
+
+                                #reset-cells = <1>;
+                        };
+                };
+
+                usb: usb@1b000100 {
+                        compatible = "qca,ar7100-ehci", "generic-ehci";
+                        reg = <0x1b000100 0x100>;
+
+                        interrupts = <3>;
+                        resets = <&rst 5>;
+
+                        has-transaction-translator;
+
+                        phy-names = "usb";
+                        phys = <&usb_phy>;
+
+                        status = "disabled";
+                };
+
+                spi: spi@1f000000 {
+                        compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+                        reg = <0x1f000000 0x10>;
+
+                        clocks = <&pll ATH79_CLK_AHB>;
+                        clock-names = "ahb";
+
+                        status = "disabled";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        usb_phy: usb-phy {
+                compatible = "qca,ar7100-usb-phy";
+
+                reset-names = "phy", "suspend-override";
+                resets = <&rst 4>, <&rst 3>;
+
+                #phy-cells = <0>;
+
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
new file mode 100644
index 000000000..7fccf6357
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9132.dtsi"
+
+/ {
+        compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
+        model = "TP-Link TL-WR1043ND Version 1";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        extosc: ref {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <40000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@0 {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+                        debounce-interval = <60>;
+                };
+
+                button@1 {
+                        label = "qss";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+                        debounce-interval = <60>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@0 {
+                        label = "tp-link:green:usb";
+                        gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+                };
+
+                led@1 {
+                        label = "tp-link:green:system";
+                        gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led@2 {
+                        label = "tp-link:green:qss";
+                        gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+                };
+
+                led@3 {
+                        label = "tp-link:green:wlan";
+                        gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&uart {
+        status = "okay";
+};
+
+&pll {
+        clocks = <&extosc>;
+};
+
+&usb {
+        status = "okay";
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&spi {
+        status = "okay";
+        num-cs = <1>;
+
+        flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "s25sl064a";
+                reg = <0>;
+                spi-max-frequency = <25000000>;
+
+                partition@0 {
+                        label = "u-boot";
+                        reg = <0x000000 0x020000>;
+                };
+
+                partition@1 {
+                        label = "firmware";
+                        reg = <0x020000 0x7D0000>;
+                };
+
+                partition@2 {
+                        label = "art";
+                        reg = <0x7F0000 0x010000>;
+                        read-only;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 000000000..83b3c0ce1
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+        compatible = "qca,ar9331";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mips,mips24Kc";
+                        clocks = <&pll ATH79_CLK_CPU>;
+                        reg = <0>;
+                };
+        };
+
+        cpuintc: interrupt-controller {
+                compatible = "qca,ar7100-cpu-intc";
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+
+                qca,ddr-wb-channel-interrupts = <2>, <3>;
+                qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+        };
+
+        ref: ref {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                ranges;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                interrupt-parent = <&cpuintc>;
+
+                apb {
+                        compatible = "simple-bus";
+                        ranges;
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        interrupt-parent = <&miscintc>;
+
+                        ddr_ctrl: memory-controller@18000000 {
+                                compatible = "qca,ar7240-ddr-controller";
+                                reg = <0x18000000 0x100>;
+
+                                #qca,ddr-wb-channel-cells = <1>;
+                        };
+
+                        uart: serial@18020000 {
+                                compatible = "qca,ar9330-uart";
+                                reg = <0x18020000 0x14>;
+
+                                interrupts = <3>;
+
+                                clocks = <&ref>;
+                                clock-names = "uart";
+
+                                status = "disabled";
+                        };
+
+                        gpio: gpio@18040000 {
+                                compatible = "qca,ar7100-gpio";
+                                reg = <0x18040000 0x34>;
+                                interrupts = <2>;
+
+                                ngpios = <30>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+
+                                status = "disabled";
+                        };
+
+                        pll: pll-controller@18050000 {
+                                compatible = "qca,ar9330-pll";
+                                reg = <0x18050000 0x100>;
+
+                                clocks = <&ref>;
+                                clock-names = "ref";
+
+                                #clock-cells = <1>;
+                        };
+
+                        miscintc: interrupt-controller@18060010 {
+                                compatible = "qca,ar7240-misc-intc";
+                                reg = <0x18060010 0x8>;
+
+                                interrupt-parent = <&cpuintc>;
+                                interrupts = <6>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        rst: reset-controller@1806001c {
+                                compatible = "qca,ar7100-reset";
+                                reg = <0x1806001c 0x4>;
+
+                                #reset-cells = <1>;
+                        };
+                };
+
+                eth0: ethernet@19000000 {
+                        compatible = "qca,ar9330-eth";
+                        reg = <0x19000000 0x200>;
+                        interrupts = <4>;
+
+                        resets = <&rst 9>, <&rst 22>;
+                        reset-names = "mac", "mdio";
+                        clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
+                        clock-names = "eth", "mdio";
+
+                        phy-mode = "mii";
+                        phy-handle = <&phy_port4>;
+
+                        status = "disabled";
+                };
+
+                eth1: ethernet@1a000000 {
+                        compatible = "qca,ar9330-eth";
+                        reg = <0x1a000000 0x200>;
+                        interrupts = <5>;
+                        resets = <&rst 13>, <&rst 23>;
+                        reset-names = "mac", "mdio";
+                        clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
+                        clock-names = "eth", "mdio";
+
+                        phy-mode = "gmii";
+
+                        status = "disabled";
+
+                        fixed-link {
+                                speed = <1000>;
+                                full-duplex;
+                        };
+
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                switch10: switch@10 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        compatible = "qca,ar9331-switch";
+                                        reg = <0x10>;
+                                        resets = <&rst 8>;
+                                        reset-names = "switch";
+
+                                        interrupt-parent = <&miscintc>;
+                                        interrupts = <12>;
+
+                                        interrupt-controller;
+                                        #interrupt-cells = <1>;
+
+                                        ports {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+
+                                                switch_port0: port@0 {
+                                                        reg = <0x0>;
+                                                        label = "cpu";
+                                                        ethernet = <&eth1>;
+
+                                                        phy-mode = "gmii";
+
+                                                        fixed-link {
+                                                                speed = <1000>;
+                                                                full-duplex;
+                                                        };
+                                                };
+
+                                                switch_port1: port@1 {
+                                                        reg = <0x1>;
+                                                        phy-handle = <&phy_port0>;
+                                                        phy-mode = "internal";
+
+                                                        status = "disabled";
+                                                };
+
+                                                switch_port2: port@2 {
+                                                        reg = <0x2>;
+                                                        phy-handle = <&phy_port1>;
+                                                        phy-mode = "internal";
+
+                                                        status = "disabled";
+                                                };
+
+                                                switch_port3: port@3 {
+                                                        reg = <0x3>;
+                                                        phy-handle = <&phy_port2>;
+                                                        phy-mode = "internal";
+
+                                                        status = "disabled";
+                                                };
+
+                                                switch_port4: port@4 {
+                                                        reg = <0x4>;
+                                                        phy-handle = <&phy_port3>;
+                                                        phy-mode = "internal";
+
+                                                        status = "disabled";
+                                                };
+                                        };
+
+                                        mdio {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+
+                                                interrupt-parent = <&switch10>;
+
+                                                phy_port0: phy@0 {
+                                                        reg = <0x0>;
+                                                        interrupts = <0>;
+                                                        status = "disabled";
+                                                };
+
+                                                phy_port1: phy@1 {
+                                                        reg = <0x1>;
+                                                        interrupts = <0>;
+                                                        status = "disabled";
+                                                };
+
+                                                phy_port2: phy@2 {
+                                                        reg = <0x2>;
+                                                        interrupts = <0>;
+                                                        status = "disabled";
+                                                };
+
+                                                phy_port3: phy@3 {
+                                                        reg = <0x3>;
+                                                        interrupts = <0>;
+                                                        status = "disabled";
+                                                };
+
+                                                phy_port4: phy@4 {
+                                                        reg = <0x4>;
+                                                        interrupts = <0>;
+                                                        status = "disabled";
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                usb: usb@1b000100 {
+                        compatible = "chipidea,usb2";
+                        reg = <0x1b000000 0x200>;
+
+                        interrupts = <3>;
+                        resets = <&rst 5>;
+
+                        phy-names = "usb-phy";
+                        phys = <&usb_phy>;
+
+                        status = "disabled";
+                };
+
+                spi: spi@1f000000 {
+                        compatible = "qca,ar7100-spi";
+                        reg = <0x1f000000 0x10>;
+
+                        clocks = <&pll ATH79_CLK_AHB>;
+                        clock-names = "ahb";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        status = "disabled";
+                };
+        };
+
+        usb_phy: usb-phy {
+                compatible = "qca,ar7100-usb-phy";
+
+                reset-names = "phy", "suspend-override";
+                resets = <&rst 4>, <&rst 3>;
+
+                #phy-cells = <0>;
+
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/qca/ar9331_dpt_module.dts b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts
new file mode 100644
index 000000000..7695d326d
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "ar9331.dtsi"
+
+/ {
+        model = "DPTechnics DPT-Module";
+        compatible = "dptechnics,dpt-module";
+
+        aliases {
+                serial0 = &uart;
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x4000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led-0 {
+                        function = LED_FUNCTION_STATUS;
+                        color = <LED_COLOR_ID_GREEN>;
+                        gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@0 {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&ref {
+        clock-frequency = <25000000>;
+};
+
+&uart {
+        status = "okay";
+};
+
+&gpio {
+        status = "okay";
+};
+
+&usb {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&spi {
+        num-chipselects = <1>;
+        status = "okay";
+
+        /* Winbond 25Q128FVSG SPI flash */
+        spiflash: w25q128@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "winbond,w25q128", "jedec,spi-nor";
+                spi-max-frequency = <104000000>;
+                reg = <0>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+};
+
+&eth1 {
+        status = "okay";
+};
+
+&switch_port1 {
+        label = "lan0";
+        status = "okay";
+};
+
+&phy_port0 {
+        status = "okay";
+};
+
+&phy_port4 {
+        status = "okay";
+};
diff --git a/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
new file mode 100644
index 000000000..d38aa73f1
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+        model = "Dragino MS14 (Dragino 2)";
+        compatible = "dragino,ms14";
+
+        aliases {
+                serial0 = &uart;
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x4000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                wlan {
+                        label = "dragino2:red:wlan";
+                        gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                lan {
+                        label = "dragino2:red:lan";
+                        gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                wan {
+                        label = "dragino2:red:wan";
+                        gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                system {
+                        label = "dragino2:red:system";
+                        gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@0 {
+                        label = "jumpstart";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+                };
+
+                button@1 {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&ref {
+        clock-frequency = <25000000>;
+};
+
+&uart {
+        status = "okay";
+};
+
+&gpio {
+        status = "okay";
+};
+
+&usb {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&spi {
+        num-chipselects = <1>;
+        status = "okay";
+
+        /* Winbond 25Q128BVFG SPI flash */
+        spiflash: w25q128@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "winbond,w25q128", "jedec,spi-nor";
+                spi-max-frequency = <104000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/mips/boot/dts/qca/ar9331_omega.dts b/arch/mips/boot/dts/qca/ar9331_omega.dts
new file mode 100644
index 000000000..11778abac
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331_omega.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+        model = "Onion Omega";
+        compatible = "onion,omega";
+
+        aliases {
+                serial0 = &uart;
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x4000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                system {
+                        label = "onion:amber:system";
+                        gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@0 {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&ref {
+        clock-frequency = <25000000>;
+};
+
+&uart {
+        status = "okay";
+};
+
+&gpio {
+        status = "okay";
+};
+
+&usb {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&spi {
+        num-chipselects = <1>;
+        status = "okay";
+
+        /* Winbond 25Q128FVSG SPI flash */
+        spiflash: w25q128@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "winbond,w25q128", "jedec,spi-nor";
+                spi-max-frequency = <104000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
new file mode 100644
index 000000000..c8290d36c
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+        model = "TP-Link TL-MR3020";
+        compatible = "tplink,tl-mr3020";
+
+        aliases {
+                serial0 = &uart;
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                wlan {
+                        label = "tp-link:green:wlan";
+                        gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                lan {
+                        label = "tp-link:green:lan";
+                        gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                wps {
+                        label = "tp-link:green:wps";
+                        gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led3g {
+                        label = "tp-link:green:3g";
+                        gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@0 {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+                };
+
+                button@1 {
+                        label = "sw1";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+                };
+
+                button@2 {
+                        label = "sw2";
+                        linux,code = <BTN_1>;
+                        gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        reg_usb_vbus: reg_usb_vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+};
+
+&ref {
+        clock-frequency = <25000000>;
+};
+
+&uart {
+        status = "okay";
+};
+
+&gpio {
+        status = "okay";
+};
+
+&usb {
+        dr_mode = "host";
+        vbus-supply = <&reg_usb_vbus>;
+        status = "okay";
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&spi {
+        num-chipselects = <1>;
+        status = "okay";
+
+        /* Spansion S25FL032PIF SPI flash */
+        spiflash: s25sl032p@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25sl032p", "jedec,spi-nor";
+                spi-max-frequency = <104000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
new file mode 100644
index 000000000..6c26dfa0a
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_RT2880_EVAL)   += rt2880_eval.dtb
+dtb-$(CONFIG_DTB_RT305X_EVAL)   += rt3052_eval.dtb
+dtb-$(CONFIG_DTB_RT3883_EVAL)   += rt3883_eval.dtb
+dtb-$(CONFIG_DTB_MT7620A_EVAL)  += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_OMEGA2P)       += omega2p.dtb
+dtb-$(CONFIG_DTB_VOCORE2)       += vocore2.dtb
+
+obj-$(CONFIG_BUILTIN_DTB)       += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
new file mode 100644
index 000000000..6069b33cf
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Stefan Roese <sr@denx.de>
+ */
+
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        compatible = "gardena,smart-gateway-mt7688", "ralink,mt7688a-soc",
+                     "ralink,mt7628a-soc";
+        model = "GARDENA smart Gateway (MT7688)";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x8000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_gpio_gpio>;        /* GPIO11 */
+
+                user_btn1 {
+                        label = "USER_BTN1";
+                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+                        linux,code =<KEY_PROG1> ;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_pwm0_gpio>,        /* GPIO18 */
+                            <&pinmux_pwm1_gpio>,        /* GPIO19 */
+                            <&pinmux_sdmode_gpio>,      /* GPIO22..29 */
+                            <&pinmux_p0led_an_gpio>;    /* GPIO43 */
+                /*
+                 * <&pinmux_i2s_gpio> (covers GPIO0..3) is needed here as
+                 * well for GPIO3. But this is already claimed for uart1
+                 * (see below). So we can't include it in this LED node.
+                 */
+
+                power_blue {
+                        label = "smartgw:power:blue";
+                        gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                power_green {
+                        label = "smartgw:power:green";
+                        gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                power_red {
+                        label = "smartgw:power:red";
+                        gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                radio_blue {
+                        label = "smartgw:radio:blue";
+                        gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                radio_green {
+                        label = "smartgw:radio:green";
+                        gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                radio_red {
+                        label = "smartgw:radio:red";
+                        gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                internet_blue {
+                        label = "smartgw:internet:blue";
+                        gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                internet_green {
+                        label = "smartgw:internet:green";
+                        gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                internet_red {
+                        label = "smartgw:internet:red";
+                        gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                ethernet_link {
+                        label = "smartgw:eth:link";
+                        gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "netdev";
+                };
+
+                ethernet_activity {
+                        label = "smartgw:eth:act";
+                        gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "netdev";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+};
+
+&i2c {
+        status = "okay";
+};
+
+&spi {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinmux_spi_spi>, <&pinmux_spi_cs1_cs>;
+
+        m25p80@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0 0xa0000>;
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                label = "uboot_env0";
+                                reg = <0xa0000 0x10000>;
+                        };
+
+                        partition@b0000 {
+                                label = "uboot_env1";
+                                reg = <0xb0000 0x10000>;
+                        };
+
+                        factory: partition@c0000 {
+                                label = "factory";
+                                reg = <0xc0000 0x10000>;
+                                read-only;
+                        };
+                };
+        };
+
+        nand_flash@1 {
+                compatible = "spi-nand";
+                linux,mtd-name = "gd5f";
+                reg = <1>;
+                spi-max-frequency = <40000000>;
+        };
+};
+
+&uart1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinmux_i2s_gpio>;         /* GPIO0..3 */
+
+        fifo-size = <8>;
+        tx-threshold = <8>;
+
+        rts-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+        cts-gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+};
+
+&uart2 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinmux_p2led_an_gpio>,    /* GPIO41 */
+                    <&pinmux_p3led_an_gpio>;    /* GPIO40 */
+
+        rts-gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
+        cts-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+};
+
+&watchdog {
+        status = "okay";
+};
+
+&wmac {
+        status = "okay";
+        mediatek,mtd-eeprom = <&factory 0x0000>;
+};
diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
new file mode 100644
index 000000000..1f6e5320f
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,mtk7620a-soc";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips24KEc";
+                };
+        };
+
+        cpuintc: cpuintc {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc@0 {
+                        compatible = "ralink,mt7620a-sysc";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: intc@200 {
+                        compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                memc@300 {
+                        compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uartlite@c00 {
+                        compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+
+                        reg-shift = <2>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/mt7620a_eval.dts b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
new file mode 100644
index 000000000..8de8f89f3
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+        compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+        model = "Ralink MT7620A evaluation board";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000000000..892e8ab86
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,mt7628a-soc";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "mti,mips24KEc";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+        };
+
+        resetc: reset-controller {
+                compatible = "ralink,rt2880-reset";
+                #reset-cells = <1>;
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc: system-controller@0 {
+                        compatible = "ralink,mt7620a-sysc", "syscon";
+                        reg = <0x0 0x60>;
+                };
+
+                pinmux: pinmux@60 {
+                        compatible = "pinctrl-single";
+                        reg = <0x60 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #pinctrl-cells = <2>;
+                        pinctrl-single,bit-per-mux;
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <0x1>;
+
+                        pinmux_gpio_gpio: pinmux_gpio_gpio {
+                                pinctrl-single,bits = <0x0 0x0 0x3>;
+                        };
+
+                        pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
+                                pinctrl-single,bits = <0x0 0x0 0x30>;
+                        };
+
+                        pinmux_i2s_gpio: pinmux_i2s_gpio {
+                                pinctrl-single,bits = <0x0 0x40 0xc0>;
+                        };
+
+                        pinmux_uart0_uart: pinmux_uart0_uart0 {
+                                pinctrl-single,bits = <0x0 0x0 0x300>;
+                        };
+
+                        pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
+                                pinctrl-single,bits = <0x0 0x0 0xc00>;
+                        };
+
+                        pinmux_sdmode_gpio: pinmux_sdmode_gpio {
+                                pinctrl-single,bits = <0x0 0x400 0xc00>;
+                        };
+
+                        pinmux_spi_spi: pinmux_spi_spi {
+                                pinctrl-single,bits = <0x0 0x0 0x1000>;
+                        };
+
+                        pinmux_refclk_gpio: pinmux_refclk_gpio {
+                                pinctrl-single,bits = <0x0 0x40000 0x40000>;
+                        };
+
+                        pinmux_i2c_i2c: pinmux_i2c_i2c {
+                                pinctrl-single,bits = <0x0 0x0 0x300000>;
+                        };
+
+                        pinmux_uart1_uart: pinmux_uart1_uart1 {
+                                pinctrl-single,bits = <0x0 0x0 0x3000000>;
+                        };
+
+                        pinmux_uart2_uart: pinmux_uart2_uart {
+                                pinctrl-single,bits = <0x0 0x0 0xc000000>;
+                        };
+
+                        pinmux_pwm0_pwm: pinmux_pwm0_pwm {
+                                pinctrl-single,bits = <0x0 0x0 0x30000000>;
+                        };
+
+                        pinmux_pwm0_gpio: pinmux_pwm0_gpio {
+                                pinctrl-single,bits = <0x0 0x10000000
+                                                       0x30000000>;
+                        };
+
+                        pinmux_pwm1_pwm: pinmux_pwm1_pwm {
+                                pinctrl-single,bits = <0x0 0x0 0xc0000000>;
+                        };
+
+                        pinmux_pwm1_gpio: pinmux_pwm1_gpio {
+                                pinctrl-single,bits = <0x0 0x40000000
+                                                       0xc0000000>;
+                        };
+
+                        pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
+                                pinctrl-single,bits = <0x4 0x4 0xc>;
+                        };
+
+                        pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
+                                pinctrl-single,bits = <0x4 0x10 0x30>;
+                        };
+
+                        pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
+                                pinctrl-single,bits = <0x4 0x40 0xc0>;
+                        };
+
+                        pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
+                                pinctrl-single,bits = <0x4 0x100 0x300>;
+                        };
+
+                        pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
+                                pinctrl-single,bits = <0x4 0x400 0xc00>;
+                        };
+                };
+
+                watchdog: watchdog@100 {
+                        compatible = "mediatek,mt7621-wdt";
+                        reg = <0x100 0x30>;
+
+                        resets = <&resetc 8>;
+                        reset-names = "wdt";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <24>;
+
+                        status = "disabled";
+                };
+
+                intc: interrupt-controller@200 {
+                        compatible = "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        resets = <&resetc 9>;
+                        reset-names = "intc";
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+
+                        ralink,intc-registers = <0x9c 0xa0
+                                                 0x6c 0xa4
+                                                 0x80 0x78>;
+                };
+
+                memory-controller@300 {
+                        compatible = "ralink,mt7620a-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                gpio: gpio@600 {
+                        compatible = "mediatek,mt7621-gpio";
+                        reg = <0x600 0x100>;
+
+                        gpio-controller;
+                        interrupt-controller;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <6>;
+                };
+
+                spi: spi@b00 {
+                        compatible = "ralink,mt7621-spi";
+                        reg = <0xb00 0x100>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinmux_spi_spi>;
+
+                        resets = <&resetc 18>;
+                        reset-names = "spi";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        status = "disabled";
+                };
+
+                i2c: i2c@900 {
+                        compatible = "mediatek,mt7621-i2c";
+                        reg = <0x900 0x100>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinmux_i2c_i2c>;
+
+                        resets = <&resetc 16>;
+                        reset-names = "i2c";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        status = "disabled";
+                };
+
+                uart0: uartlite@c00 {
+                        compatible = "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinmux_uart0_uart>;
+
+                        resets = <&resetc 12>;
+                        reset-names = "uart0";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <20>;
+
+                        reg-shift = <2>;
+                };
+
+                uart1: uart1@d00 {
+                        compatible = "ns16550a";
+                        reg = <0xd00 0x100>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinmux_uart1_uart>;
+
+                        resets = <&resetc 19>;
+                        reset-names = "uart1";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <21>;
+
+                        reg-shift = <2>;
+                };
+
+                uart2: uart2@e00 {
+                        compatible = "ns16550a";
+                        reg = <0xe00 0x100>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinmux_uart2_uart>;
+
+                        resets = <&resetc 20>;
+                        reset-names = "uart2";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <22>;
+
+                        reg-shift = <2>;
+                };
+        };
+
+        usb_phy: usb-phy@10120000 {
+                compatible = "mediatek,mt7628-usbphy";
+                reg = <0x10120000 0x1000>;
+
+                #phy-cells = <0>;
+
+                ralink,sysctl = <&sysc>;
+                resets = <&resetc 22 &resetc 25>;
+                reset-names = "host", "device";
+        };
+
+        ehci@101c0000 {
+                compatible = "generic-ehci";
+                reg = <0x101c0000 0x1000>;
+
+                phys = <&usb_phy>;
+                phy-names = "usb";
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+        };
+
+        wmac: wmac@10300000 {
+                compatible = "mediatek,mt7628-wmac";
+                reg = <0x10300000 0x100000>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <6>;
+
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/omega2p.dts b/arch/mips/boot/dts/ralink/omega2p.dts
new file mode 100644
index 000000000..5884fd48f
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/omega2p.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+/ {
+        compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";
+        model = "Onion Omega2+";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
new file mode 100644
index 000000000..8fc1987d9
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,rt2880-soc";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips4KEc";
+                };
+        };
+
+        cpuintc: cpuintc {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@300000 {
+                compatible = "palmbus";
+                reg = <0x300000 0x200000>;
+                ranges = <0x0 0x300000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc@0 {
+                        compatible = "ralink,rt2880-sysc";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: intc@200 {
+                        compatible = "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                memc@300 {
+                        compatible = "ralink,rt2880-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uartlite@c00 {
+                        compatible = "ralink,rt2880-uart", "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <8>;
+
+                        reg-shift = <2>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt2880_eval.dts b/arch/mips/boot/dts/ralink/rt2880_eval.dts
new file mode 100644
index 000000000..759bc1dd5
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt2880_eval.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "rt2880.dtsi"
+
+/ {
+        compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
+        model = "Ralink RT2880 evaluation board";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x8000000 0x2000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+
+        cfi@1f000000 {
+                compatible = "cfi-flash";
+                reg = <0x1f000000 0x400000>;
+
+                bank-width = <2>;
+                device-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "uboot";
+                        reg = <0x0 0x30000>;
+                        read-only;
+                };
+                partition@30000 {
+                        label = "uboot-env";
+                        reg = <0x30000 0x10000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "calibration";
+                        reg = <0x40000 0x10000>;
+                        read-only;
+                };
+                partition@50000 {
+                        label = "linux";
+                        reg = <0x50000 0x3b0000>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
new file mode 100644
index 000000000..23062333a
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips24KEc";
+                };
+        };
+
+        cpuintc: cpuintc {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc@0 {
+                        compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: intc@200 {
+                        compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                memc@300 {
+                        compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uartlite@c00 {
+                        compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+
+                        reg-shift = <2>;
+                };
+        };
+
+        usb@101c0000 {
+                compatible = "ralink,rt3050-usb", "snps,dwc2";
+                reg = <0x101c0000 40000>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+
+                status = "disabled";
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt3052_eval.dts b/arch/mips/boot/dts/ralink/rt3052_eval.dts
new file mode 100644
index 000000000..6408ff629
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt3052_eval.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "rt3050.dtsi"
+
+/ {
+        compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
+        model = "Ralink RT3052 evaluation board";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+
+        cfi@1f000000 {
+                compatible = "cfi-flash";
+                reg = <0x1f000000 0x800000>;
+
+                bank-width = <2>;
+                device-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "uboot";
+                        reg = <0x0 0x30000>;
+                        read-only;
+                };
+                partition@30000 {
+                        label = "uboot-env";
+                        reg = <0x30000 0x10000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "calibration";
+                        reg = <0x40000 0x10000>;
+                        read-only;
+                };
+                partition@50000 {
+                        label = "linux";
+                        reg = <0x50000 0x7b0000>;
+                };
+        };
+
+        usb@101c0000 {
+                status = "okay";
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
new file mode 100644
index 000000000..61132cf15
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,rt3883-soc";
+
+        cpus {
+                cpu@0 {
+                        compatible = "mips,mips74Kc";
+                };
+        };
+
+        cpuintc: cpuintc {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc@0 {
+                        compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: intc@200 {
+                        compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+                };
+
+                memc@300 {
+                        compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uartlite@c00 {
+                        compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <12>;
+
+                        reg-shift = <2>;
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/rt3883_eval.dts b/arch/mips/boot/dts/ralink/rt3883_eval.dts
new file mode 100644
index 000000000..c22bc84df
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/rt3883_eval.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "rt3883.dtsi"
+
+/ {
+        compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
+        model = "Ralink RT3883 evaluation board";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/vocore2.dts b/arch/mips/boot/dts/ralink/vocore2.dts
new file mode 100644
index 000000000..fa8a5f8f2
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+        compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+        model = "VoCore2";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS2,115200";
+                stdout-path = &uart2;
+        };
+};
diff --git a/arch/mips/boot/dts/xilfpga/Makefile b/arch/mips/boot/dts/xilfpga/Makefile
new file mode 100644
index 000000000..69ca00590
--- /dev/null
+++ b/arch/mips/boot/dts/xilfpga/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)     += nexys4ddr.dtb
diff --git a/arch/mips/boot/dts/xilfpga/microAptiv.dtsi b/arch/mips/boot/dts/xilfpga/microAptiv.dtsi
new file mode 100644
index 000000000..87b2b1f9a
--- /dev/null
+++ b/arch/mips/boot/dts/xilfpga/microAptiv.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "img,xilfpga";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mips,m14Kc";
+                        clocks  = <&ext>;
+                        reg = <0>;
+                };
+        };
+
+        ext: ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+};
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
new file mode 100644
index 000000000..cc8dbea09
--- /dev/null
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "microAptiv.dtsi"
+
+/ {
+        compatible = "digilent,nexys4ddr";
+
+        aliases {
+                serial0 = &axi_uart16550;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x08000000>;
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        axi_intc: interrupt-controller@10200000 {
+                #interrupt-cells = <1>;
+                compatible = "xlnx,xps-intc-1.00.a";
+                interrupt-controller;
+                reg = <0x10200000 0x10000>;
+                xlnx,kind-of-intr = <0x0>;
+                xlnx,num-intr-inputs = <0x6>;
+
+                interrupt-parent = <&cpuintc>;
+                interrupts = <6>;
+        };
+
+        axi_gpio: gpio@10600000 {
+                #gpio-cells = <1>;
+                compatible = "xlnx,xps-gpio-1.00.a";
+                gpio-controller;
+                reg = <0x10600000 0x10000>;
+                xlnx,all-inputs = <0x0>;
+                xlnx,dout-default = <0x0>;
+                xlnx,gpio-width = <0x16>;
+                xlnx,interrupt-present = <0x0>;
+                xlnx,is-dual = <0x0>;
+                xlnx,tri-default = <0xffffffff>;
+        } ;
+
+        axi_ethernetlite: ethernet@10e00000 {
+                compatible = "xlnx,xps-ethernetlite-3.00.a";
+                device_type = "network";
+                interrupt-parent = <&axi_intc>;
+                interrupts = <1>;
+                phy-handle = <&phy0>;
+                reg = <0x10e00000 0x10000>;
+                xlnx,duplex = <0x1>;
+                xlnx,include-global-buffers = <0x1>;
+                xlnx,include-internal-loopback = <0x0>;
+                xlnx,include-mdio = <0x1>;
+                xlnx,instance = "axi_ethernetlite_inst";
+                xlnx,rx-ping-pong = <0x1>;
+                xlnx,s-axi-id-width = <0x1>;
+                xlnx,tx-ping-pong = <0x1>;
+                xlnx,use-internal = <0x0>;
+                mdio {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy0: phy@1 {
+                                device_type = "ethernet-phy";
+                                reg = <1>;
+                        };
+                };
+        };
+
+        axi_uart16550: serial@10400000 {
+                compatible = "ns16550a";
+                reg = <0x10400000 0x10000>;
+
+                reg-shift = <2>;
+                reg-offset = <0x1000>;
+
+                clocks  = <&ext>;
+
+                interrupt-parent = <&axi_intc>;
+                interrupts = <0>;
+        };
+
+        axi_i2c: i2c@10a00000 {
+            compatible = "xlnx,xps-iic-2.00.a";
+            interrupt-parent = <&axi_intc>;
+            interrupts = <4>;
+            reg = < 0x10a00000 0x10000 >;
+            clocks = <&ext>;
+            xlnx,clk-freq = <0x5f5e100>;
+            xlnx,family = "Artix7";
+            xlnx,gpo-width = <0x1>;
+            xlnx,iic-freq = <0x186a0>;
+            xlnx,scl-inertial-delay = <0x0>;
+            xlnx,sda-inertial-delay = <0x0>;
+            xlnx,ten-bit-adr = <0x0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ad7420@4b {
+                compatible = "adi,adt7420";
+                reg = <0x4b>;
+            };
+        } ;
+};
+
+&ext {
+        clock-frequency = <50000000>;
+};
diff --git a/arch/mips/boot/ecoff.h b/arch/mips/boot/ecoff.h
new file mode 100644
index 000000000..5be79ebfc
--- /dev/null
+++ b/arch/mips/boot/ecoff.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Some ECOFF definitions.
+ */
+
+#include <stdint.h>
+
+typedef struct filehdr {
+        uint16_t        f_magic;        /* magic number */
+        uint16_t        f_nscns;        /* number of sections */
+        int32_t         f_timdat;       /* time & date stamp */
+        int32_t         f_symptr;       /* file pointer to symbolic header */
+        int32_t         f_nsyms;        /* sizeof(symbolic hdr) */
+        uint16_t        f_opthdr;       /* sizeof(optional hdr) */
+        uint16_t        f_flags;        /* flags */
+} FILHDR;
+#define FILHSZ  sizeof(FILHDR)
+
+#define MIPSEBMAGIC     0x160
+#define MIPSELMAGIC     0x162
+
+typedef struct scnhdr {
+        char            s_name[8];      /* section name */
+        int32_t         s_paddr;        /* physical address, aliased s_nlib */
+        int32_t         s_vaddr;        /* virtual address */
+        int32_t         s_size;         /* section size */
+        int32_t         s_scnptr;       /* file ptr to raw data for section */
+        int32_t         s_relptr;       /* file ptr to relocation */
+        int32_t         s_lnnoptr;      /* file ptr to gp histogram */
+        uint16_t        s_nreloc;       /* number of relocation entries */
+        uint16_t        s_nlnno;        /* number of gp histogram entries */
+        int32_t         s_flags;        /* flags */
+} SCNHDR;
+#define SCNHSZ          sizeof(SCNHDR)
+#define SCNROUND        ((int32_t)16)
+
+typedef struct aouthdr {
+        int16_t magic;          /* see above                            */
+        int16_t vstamp;         /* version stamp                        */
+        int32_t tsize;          /* text size in bytes, padded to DW bdry*/
+        int32_t dsize;          /* initialized data "  "                */
+        int32_t bsize;          /* uninitialized data "   "             */
+        int32_t entry;          /* entry pt.                            */
+        int32_t text_start;     /* base of text used for this file      */
+        int32_t data_start;     /* base of data used for this file      */
+        int32_t bss_start;      /* base of bss used for this file       */
+        int32_t gprmask;        /* general purpose register mask        */
+        int32_t cprmask[4];     /* co-processor register masks          */
+        int32_t gp_value;       /* the gp value used for this object    */
+} AOUTHDR;
+#define AOUTHSZ sizeof(AOUTHDR)
+
+#define OMAGIC          0407
+#define NMAGIC          0410
+#define ZMAGIC          0413
+#define SMAGIC          0411
+#define LIBMAGIC        0443
+
+#define N_TXTOFF(f, a) \
+ ((a).magic == ZMAGIC || (a).magic == LIBMAGIC ? 0 : \
+  ((a).vstamp < 23 ? \
+   ((FILHSZ + AOUTHSZ + (f).f_nscns * SCNHSZ + 7) & 0xfffffff8) : \
+   ((FILHSZ + AOUTHSZ + (f).f_nscns * SCNHSZ + SCNROUND-1) & ~(SCNROUND-1)) ) )
+#define N_DATOFF(f, a) \
+  N_TXTOFF(f, a) + (a).tsize;
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
new file mode 100644
index 000000000..6972b9723
--- /dev/null
+++ b/arch/mips/boot/elf2ecoff.c
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 1995
+ *      Ted Lemon (hereinafter referred to as the author)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* elf2ecoff.c
+
+   This program converts an elf executable to an ECOFF executable.
+   No symbol table is retained.   This is useful primarily in building
+   net-bootable kernels for machines (e.g., DECstation and Alpha) which
+   only support the ECOFF object file format. */
+
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <elf.h>
+#include <limits.h>
+#include <netinet/in.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+
+#include "ecoff.h"
+
+/*
+ * Some extra ELF definitions
+ */
+#define PT_MIPS_REGINFO         0x70000000      /* Register usage information */
+#define PT_MIPS_ABIFLAGS        0x70000003      /* Records ABI related flags  */
+
+/* -------------------------------------------------------------------- */
+
+struct sect {
+        uint32_t vaddr;
+        uint32_t len;
+};
+
+int *symTypeTable;
+int must_convert_endian;
+int format_bigendian;
+
+static void copy(int out, int in, off_t offset, off_t size)
+{
+        char ibuf[4096];
+        int remaining, cur, count;
+
+        /* Go to the start of the ELF symbol table... */
+        if (lseek(in, offset, SEEK_SET) < 0) {
+                perror("copy: lseek");
+                exit(1);
+        }
+
+        remaining = size;
+        while (remaining) {
+                cur = remaining;
+                if (cur > sizeof ibuf)
+                        cur = sizeof ibuf;
+                remaining -= cur;
+                if ((count = read(in, ibuf, cur)) != cur) {
+                        fprintf(stderr, "copy: read: %s\n",
+                                count ? strerror(errno) :
+                                "premature end of file");
+                        exit(1);
+                }
+                if ((count = write(out, ibuf, cur)) != cur) {
+                        perror("copy: write");
+                        exit(1);
+                }
+        }
+}
+
+/*
+ * Combine two segments, which must be contiguous.   If pad is true, it's
+ * okay for there to be padding between.
+ */
+static void combine(struct sect *base, struct sect *new, int pad)
+{
+        if (!base->len)
+                *base = *new;
+        else if (new->len) {
+                if (base->vaddr + base->len != new->vaddr) {
+                        if (pad)
+                                base->len = new->vaddr - base->vaddr;
+                        else {
+                                fprintf(stderr,
+                                        "Non-contiguous data can't be converted.\n");
+                                exit(1);
+                        }
+                }
+                base->len += new->len;
+        }
+}
+
+static int phcmp(const void *v1, const void *v2)
+{
+        const Elf32_Phdr *h1 = v1;
+        const Elf32_Phdr *h2 = v2;
+
+        if (h1->p_vaddr > h2->p_vaddr)
+                return 1;
+        else if (h1->p_vaddr < h2->p_vaddr)
+                return -1;
+        else
+                return 0;
+}
+
+static char *saveRead(int file, off_t offset, off_t len, char *name)
+{
+        char *tmp;
+        int count;
+        off_t off;
+        if ((off = lseek(file, offset, SEEK_SET)) < 0) {
+                fprintf(stderr, "%s: fseek: %s\n", name, strerror(errno));
+                exit(1);
+        }
+        if (!(tmp = (char *) malloc(len))) {
+                fprintf(stderr, "%s: Can't allocate %ld bytes.\n", name,
+                        len);
+                exit(1);
+        }
+        count = read(file, tmp, len);
+        if (count != len) {
+                fprintf(stderr, "%s: read: %s.\n",
+                        name,
+                        count ? strerror(errno) : "End of file reached");
+                exit(1);
+        }
+        return tmp;
+}
+
+#define swab16(x) \
+        ((uint16_t)( \
+                (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
+                (((uint16_t)(x) & (uint16_t)0xff00U) >> 8) ))
+
+#define swab32(x) \
+        ((unsigned int)( \
+                (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
+                (((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) | \
+                (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) | \
+                (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) ))
+
+static void convert_elf_hdr(Elf32_Ehdr * e)
+{
+        e->e_type = swab16(e->e_type);
+        e->e_machine = swab16(e->e_machine);
+        e->e_version = swab32(e->e_version);
+        e->e_entry = swab32(e->e_entry);
+        e->e_phoff = swab32(e->e_phoff);
+        e->e_shoff = swab32(e->e_shoff);
+        e->e_flags = swab32(e->e_flags);
+        e->e_ehsize = swab16(e->e_ehsize);
+        e->e_phentsize = swab16(e->e_phentsize);
+        e->e_phnum = swab16(e->e_phnum);
+        e->e_shentsize = swab16(e->e_shentsize);
+        e->e_shnum = swab16(e->e_shnum);
+        e->e_shstrndx = swab16(e->e_shstrndx);
+}
+
+static void convert_elf_phdrs(Elf32_Phdr * p, int num)
+{
+        int i;
+
+        for (i = 0; i < num; i++, p++) {
+                p->p_type = swab32(p->p_type);
+                p->p_offset = swab32(p->p_offset);
+                p->p_vaddr = swab32(p->p_vaddr);
+                p->p_paddr = swab32(p->p_paddr);
+                p->p_filesz = swab32(p->p_filesz);
+                p->p_memsz = swab32(p->p_memsz);
+                p->p_flags = swab32(p->p_flags);
+                p->p_align = swab32(p->p_align);
+        }
+
+}
+
+static void convert_elf_shdrs(Elf32_Shdr * s, int num)
+{
+        int i;
+
+        for (i = 0; i < num; i++, s++) {
+                s->sh_name = swab32(s->sh_name);
+                s->sh_type = swab32(s->sh_type);
+                s->sh_flags = swab32(s->sh_flags);
+                s->sh_addr = swab32(s->sh_addr);
+                s->sh_offset = swab32(s->sh_offset);
+                s->sh_size = swab32(s->sh_size);
+                s->sh_link = swab32(s->sh_link);
+                s->sh_info = swab32(s->sh_info);
+                s->sh_addralign = swab32(s->sh_addralign);
+                s->sh_entsize = swab32(s->sh_entsize);
+        }
+}
+
+static void convert_ecoff_filehdr(struct filehdr *f)
+{
+        f->f_magic = swab16(f->f_magic);
+        f->f_nscns = swab16(f->f_nscns);
+        f->f_timdat = swab32(f->f_timdat);
+        f->f_symptr = swab32(f->f_symptr);
+        f->f_nsyms = swab32(f->f_nsyms);
+        f->f_opthdr = swab16(f->f_opthdr);
+        f->f_flags = swab16(f->f_flags);
+}
+
+static void convert_ecoff_aouthdr(struct aouthdr *a)
+{
+        a->magic = swab16(a->magic);
+        a->vstamp = swab16(a->vstamp);
+        a->tsize = swab32(a->tsize);
+        a->dsize = swab32(a->dsize);
+        a->bsize = swab32(a->bsize);
+        a->entry = swab32(a->entry);
+        a->text_start = swab32(a->text_start);
+        a->data_start = swab32(a->data_start);
+        a->bss_start = swab32(a->bss_start);
+        a->gprmask = swab32(a->gprmask);
+        a->cprmask[0] = swab32(a->cprmask[0]);
+        a->cprmask[1] = swab32(a->cprmask[1]);
+        a->cprmask[2] = swab32(a->cprmask[2]);
+        a->cprmask[3] = swab32(a->cprmask[3]);
+        a->gp_value = swab32(a->gp_value);
+}
+
+static void convert_ecoff_esecs(struct scnhdr *s, int num)
+{
+        int i;
+
+        for (i = 0; i < num; i++, s++) {
+                s->s_paddr = swab32(s->s_paddr);
+                s->s_vaddr = swab32(s->s_vaddr);
+                s->s_size = swab32(s->s_size);
+                s->s_scnptr = swab32(s->s_scnptr);
+                s->s_relptr = swab32(s->s_relptr);
+                s->s_lnnoptr = swab32(s->s_lnnoptr);
+                s->s_nreloc = swab16(s->s_nreloc);
+                s->s_nlnno = swab16(s->s_nlnno);
+                s->s_flags = swab32(s->s_flags);
+        }
+}
+
+int main(int argc, char *argv[])
+{
+        Elf32_Ehdr ex;
+        Elf32_Phdr *ph;
+        Elf32_Shdr *sh;
+        int i, pad;
+        struct sect text, data, bss;
+        struct filehdr efh;
+        struct aouthdr eah;
+        struct scnhdr esecs[6];
+        int infile, outfile;
+        uint32_t cur_vma = UINT32_MAX;
+        int addflag = 0;
+        int nosecs;
+
+        text.len = data.len = bss.len = 0;
+        text.vaddr = data.vaddr = bss.vaddr = 0;
+
+        /* Check args... */
+        if (argc < 3 || argc > 4) {
+              usage:
+                fprintf(stderr,
+                        "usage: elf2ecoff <elf executable> <ecoff executable> [-a]\n");
+                exit(1);
+        }
+        if (argc == 4) {
+                if (strcmp(argv[3], "-a"))
+                        goto usage;
+                addflag = 1;
+        }
+
+        /* Try the input file... */
+        if ((infile = open(argv[1], O_RDONLY)) < 0) {
+                fprintf(stderr, "Can't open %s for read: %s\n",
+                        argv[1], strerror(errno));
+                exit(1);
+        }
+
+        /* Read the header, which is at the beginning of the file... */
+        i = read(infile, &ex, sizeof ex);
+        if (i != sizeof ex) {
+                fprintf(stderr, "ex: %s: %s.\n",
+                        argv[1],
+                        i ? strerror(errno) : "End of file reached");
+                exit(1);
+        }
+
+        if (ex.e_ident[EI_DATA] == ELFDATA2MSB)
+                format_bigendian = 1;
+
+        if (ntohs(0xaa55) == 0xaa55) {
+                if (!format_bigendian)
+                        must_convert_endian = 1;
+        } else {
+                if (format_bigendian)
+                        must_convert_endian = 1;
+        }
+        if (must_convert_endian)
+                convert_elf_hdr(&ex);
+
+        /* Read the program headers... */
+        ph = (Elf32_Phdr *) saveRead(infile, ex.e_phoff,
+                                     ex.e_phnum * sizeof(Elf32_Phdr),
+                                     "ph");
+        if (must_convert_endian)
+                convert_elf_phdrs(ph, ex.e_phnum);
+        /* Read the section headers... */
+        sh = (Elf32_Shdr *) saveRead(infile, ex.e_shoff,
+                                     ex.e_shnum * sizeof(Elf32_Shdr),
+                                     "sh");
+        if (must_convert_endian)
+                convert_elf_shdrs(sh, ex.e_shnum);
+
+        /* Figure out if we can cram the program header into an ECOFF
+           header...  Basically, we can't handle anything but loadable
+           segments, but we can ignore some kinds of segments.  We can't
+           handle holes in the address space.  Segments may be out of order,
+           so we sort them first. */
+
+        qsort(ph, ex.e_phnum, sizeof(Elf32_Phdr), phcmp);
+
+        for (i = 0; i < ex.e_phnum; i++) {
+                /* Section types we can ignore... */
+                switch (ph[i].p_type) {
+                case PT_NULL:
+                case PT_NOTE:
+                case PT_PHDR:
+                case PT_MIPS_REGINFO:
+                case PT_MIPS_ABIFLAGS:
+                        continue;
+
+                case PT_LOAD:
+                        /* Writable (data) segment? */
+                        if (ph[i].p_flags & PF_W) {
+                                struct sect ndata, nbss;
+
+                                ndata.vaddr = ph[i].p_vaddr;
+                                ndata.len = ph[i].p_filesz;
+                                nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
+                                nbss.len = ph[i].p_memsz - ph[i].p_filesz;
+
+                                combine(&data, &ndata, 0);
+                                combine(&bss, &nbss, 1);
+                        } else {
+                                struct sect ntxt;
+
+                                ntxt.vaddr = ph[i].p_vaddr;
+                                ntxt.len = ph[i].p_filesz;
+
+                                combine(&text, &ntxt, 0);
+                        }
+                        /* Remember the lowest segment start address. */
+                        if (ph[i].p_vaddr < cur_vma)
+                                cur_vma = ph[i].p_vaddr;
+                        break;
+
+                default:
+                        /* Section types we can't handle... */
+                        fprintf(stderr,
+                                "Program header %d type %d can't be converted.\n",
+                                ex.e_phnum, ph[i].p_type);
+                        exit(1);
+                }
+        }
+
+        /* Sections must be in order to be converted... */
+        if (text.vaddr > data.vaddr || data.vaddr > bss.vaddr ||
+            text.vaddr + text.len > data.vaddr
+            || data.vaddr + data.len > bss.vaddr) {
+                fprintf(stderr,
+                        "Sections ordering prevents a.out conversion.\n");
+                exit(1);
+        }
+
+        /* If there's a data section but no text section, then the loader
+           combined everything into one section.   That needs to be the
+           text section, so just make the data section zero length following
+           text. */
+        if (data.len && !text.len) {
+                text = data;
+                data.vaddr = text.vaddr + text.len;
+                data.len = 0;
+        }
+
+        /* If there is a gap between text and data, we'll fill it when we copy
+           the data, so update the length of the text segment as represented in
+           a.out to reflect that, since a.out doesn't allow gaps in the program
+           address space. */
+        if (text.vaddr + text.len < data.vaddr)
+                text.len = data.vaddr - text.vaddr;
+
+        /* We now have enough information to cons up an a.out header... */
+        eah.magic = OMAGIC;
+        eah.vstamp = 200;
+        eah.tsize = text.len;
+        eah.dsize = data.len;
+        eah.bsize = bss.len;
+        eah.entry = ex.e_entry;
+        eah.text_start = text.vaddr;
+        eah.data_start = data.vaddr;
+        eah.bss_start = bss.vaddr;
+        eah.gprmask = 0xf3fffffe;
+        memset(&eah.cprmask, '\0', sizeof eah.cprmask);
+        eah.gp_value = 0;       /* unused. */
+
+        if (format_bigendian)
+                efh.f_magic = MIPSEBMAGIC;
+        else
+                efh.f_magic = MIPSELMAGIC;
+        if (addflag)
+                nosecs = 6;
+        else
+                nosecs = 3;
+        efh.f_nscns = nosecs;
+        efh.f_timdat = 0;       /* bogus */
+        efh.f_symptr = 0;
+        efh.f_nsyms = 0;
+        efh.f_opthdr = sizeof eah;
+        efh.f_flags = 0x100f;   /* Stripped, not sharable. */
+
+        memset(esecs, 0, sizeof esecs);
+        strcpy(esecs[0].s_name, ".text");
+        strcpy(esecs[1].s_name, ".data");
+        strcpy(esecs[2].s_name, ".bss");
+        if (addflag) {
+                strcpy(esecs[3].s_name, ".rdata");
+                strcpy(esecs[4].s_name, ".sdata");
+                strcpy(esecs[5].s_name, ".sbss");
+        }
+        esecs[0].s_paddr = esecs[0].s_vaddr = eah.text_start;
+        esecs[1].s_paddr = esecs[1].s_vaddr = eah.data_start;
+        esecs[2].s_paddr = esecs[2].s_vaddr = eah.bss_start;
+        if (addflag) {
+                esecs[3].s_paddr = esecs[3].s_vaddr = 0;
+                esecs[4].s_paddr = esecs[4].s_vaddr = 0;
+                esecs[5].s_paddr = esecs[5].s_vaddr = 0;
+        }
+        esecs[0].s_size = eah.tsize;
+        esecs[1].s_size = eah.dsize;
+        esecs[2].s_size = eah.bsize;
+        if (addflag) {
+                esecs[3].s_size = 0;
+                esecs[4].s_size = 0;
+                esecs[5].s_size = 0;
+        }
+        esecs[0].s_scnptr = N_TXTOFF(efh, eah);
+        esecs[1].s_scnptr = N_DATOFF(efh, eah);
+#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10
+#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1))
+        esecs[2].s_scnptr = esecs[1].s_scnptr +
+            ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah));
+        if (addflag) {
+                esecs[3].s_scnptr = 0;
+                esecs[4].s_scnptr = 0;
+                esecs[5].s_scnptr = 0;
+        }
+        esecs[0].s_relptr = esecs[1].s_relptr = esecs[2].s_relptr = 0;
+        esecs[0].s_lnnoptr = esecs[1].s_lnnoptr = esecs[2].s_lnnoptr = 0;
+        esecs[0].s_nreloc = esecs[1].s_nreloc = esecs[2].s_nreloc = 0;
+        esecs[0].s_nlnno = esecs[1].s_nlnno = esecs[2].s_nlnno = 0;
+        if (addflag) {
+                esecs[3].s_relptr = esecs[4].s_relptr
+                    = esecs[5].s_relptr = 0;
+                esecs[3].s_lnnoptr = esecs[4].s_lnnoptr
+                    = esecs[5].s_lnnoptr = 0;
+                esecs[3].s_nreloc = esecs[4].s_nreloc = esecs[5].s_nreloc =
+                    0;
+                esecs[3].s_nlnno = esecs[4].s_nlnno = esecs[5].s_nlnno = 0;
+        }
+        esecs[0].s_flags = 0x20;
+        esecs[1].s_flags = 0x40;
+        esecs[2].s_flags = 0x82;
+        if (addflag) {
+                esecs[3].s_flags = 0x100;
+                esecs[4].s_flags = 0x200;
+                esecs[5].s_flags = 0x400;
+        }
+
+        /* Make the output file... */
+        if ((outfile = open(argv[2], O_WRONLY | O_CREAT, 0777)) < 0) {
+                fprintf(stderr, "Unable to create %s: %s\n", argv[2],
+                        strerror(errno));
+                exit(1);
+        }
+
+        if (must_convert_endian)
+                convert_ecoff_filehdr(&efh);
+        /* Write the headers... */
+        i = write(outfile, &efh, sizeof efh);
+        if (i != sizeof efh) {
+                perror("efh: write");
+                exit(1);
+
+                for (i = 0; i < nosecs; i++) {
+                        printf
+                            ("Section %d: %s phys %"PRIx32"  size %"PRIx32"\t file offset %"PRIx32"\n",
+                             i, esecs[i].s_name, esecs[i].s_paddr,
+                             esecs[i].s_size, esecs[i].s_scnptr);
+                }
+        }
+        fprintf(stderr, "wrote %d byte file header.\n", i);
+
+        if (must_convert_endian)
+                convert_ecoff_aouthdr(&eah);
+        i = write(outfile, &eah, sizeof eah);
+        if (i != sizeof eah) {
+                perror("eah: write");
+                exit(1);
+        }
+        fprintf(stderr, "wrote %d byte a.out header.\n", i);
+
+        if (must_convert_endian)
+                convert_ecoff_esecs(&esecs[0], nosecs);
+        i = write(outfile, &esecs, nosecs * sizeof(struct scnhdr));
+        if (i != nosecs * sizeof(struct scnhdr)) {
+                perror("esecs: write");
+                exit(1);
+        }
+        fprintf(stderr, "wrote %d bytes of section headers.\n", i);
+
+        pad = (sizeof(efh) + sizeof(eah) + nosecs * sizeof(struct scnhdr)) & 15;
+        if (pad) {
+                pad = 16 - pad;
+                i = write(outfile, "\0\0\0\0\0\0\0\0\0\0\0\0\0\0", pad);
+                if (i < 0) {
+                        perror("ipad: write");
+                        exit(1);
+                }
+                fprintf(stderr, "wrote %d byte pad.\n", i);
+        }
+
+        /*
+         * Copy the loadable sections.   Zero-fill any gaps less than 64k;
+         * complain about any zero-filling, and die if we're asked to zero-fill
+         * more than 64k.
+         */
+        for (i = 0; i < ex.e_phnum; i++) {
+                /* Unprocessable sections were handled above, so just verify that
+                   the section can be loaded before copying. */
+                if (ph[i].p_type == PT_LOAD && ph[i].p_filesz) {
+                        if (cur_vma != ph[i].p_vaddr) {
+                                uint32_t gap = ph[i].p_vaddr - cur_vma;
+                                char obuf[1024];
+                                if (gap > 65536) {
+                                        fprintf(stderr,
+                                                "Intersegment gap (%"PRId32" bytes) too large.\n",
+                                                gap);
+                                        exit(1);
+                                }
+                                fprintf(stderr,
+                                        "Warning: %d byte intersegment gap.\n",
+                                        gap);
+                                memset(obuf, 0, sizeof obuf);
+                                while (gap) {
+                                        int count =
+                                            write(outfile, obuf,
+                                                  (gap >
+                                                   sizeof obuf ? sizeof
+                                                   obuf : gap));
+                                        if (count < 0) {
+                                                fprintf(stderr,
+                                                        "Error writing gap: %s\n",
+                                                        strerror(errno));
+                                                exit(1);
+                                        }
+                                        gap -= count;
+                                }
+                        }
+                        fprintf(stderr, "writing %d bytes...\n",
+                                ph[i].p_filesz);
+                        copy(outfile, infile, ph[i].p_offset,
+                             ph[i].p_filesz);
+                        cur_vma = ph[i].p_vaddr + ph[i].p_filesz;
+                }
+        }
+
+        /*
+         * Write a page of padding for boot PROMS that read entire pages.
+         * Without this, they may attempt to read past the end of the
+         * data section, incur an error, and refuse to boot.
+         */
+        {
+                char obuf[4096];
+                memset(obuf, 0, sizeof obuf);
+                if (write(outfile, obuf, sizeof(obuf)) != sizeof(obuf)) {
+                        fprintf(stderr, "Error writing PROM padding: %s\n",
+                                strerror(errno));
+                        exit(1);
+                }
+        }
+
+        /* Looks like we won... */
+        exit(0);
+}
diff --git a/arch/mips/boot/tools/.gitignore b/arch/mips/boot/tools/.gitignore
new file mode 100644
index 000000000..d36dc7cf9
--- /dev/null
+++ b/arch/mips/boot/tools/.gitignore
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+relocs
diff --git a/arch/mips/boot/tools/Makefile b/arch/mips/boot/tools/Makefile
new file mode 100644
index 000000000..592e05a51
--- /dev/null
+++ b/arch/mips/boot/tools/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+
+hostprogs       += relocs
+relocs-objs     += relocs_32.o
+relocs-objs     += relocs_64.o
+relocs-objs     += relocs_main.o
+PHONY += relocs
+relocs: $(obj)/relocs
+        @:
diff --git a/arch/mips/boot/tools/relocs.c b/arch/mips/boot/tools/relocs.c
new file mode 100644
index 000000000..1bf53f352
--- /dev/null
+++ b/arch/mips/boot/tools/relocs.c
@@ -0,0 +1,681 @@
+// SPDX-License-Identifier: GPL-2.0
+/* This is included from relocs_32/64.c */
+
+#define ElfW(type)              _ElfW(ELF_BITS, type)
+#define _ElfW(bits, type)       __ElfW(bits, type)
+#define __ElfW(bits, type)      Elf##bits##_##type
+
+#define Elf_Addr                ElfW(Addr)
+#define Elf_Ehdr                ElfW(Ehdr)
+#define Elf_Phdr                ElfW(Phdr)
+#define Elf_Shdr                ElfW(Shdr)
+#define Elf_Sym                 ElfW(Sym)
+
+static Elf_Ehdr ehdr;
+
+struct relocs {
+        uint32_t        *offset;
+        unsigned long   count;
+        unsigned long   size;
+};
+
+static struct relocs relocs;
+
+struct section {
+        Elf_Shdr       shdr;
+        struct section *link;
+        Elf_Sym        *symtab;
+        Elf_Rel        *reltab;
+        char           *strtab;
+        long           shdr_offset;
+};
+static struct section *secs;
+
+static const char * const regex_sym_kernel = {
+/* Symbols matching these regex's should never be relocated */
+        "^(__crc_)",
+};
+
+static regex_t sym_regex_c;
+
+static int regex_skip_reloc(const char *sym_name)
+{
+        return !regexec(&sym_regex_c, sym_name, 0, NULL, 0);
+}
+
+static void regex_init(void)
+{
+        char errbuf[128];
+        int err;
+
+        err = regcomp(&sym_regex_c, regex_sym_kernel,
+                        REG_EXTENDED|REG_NOSUB);
+
+        if (err) {
+                regerror(err, &sym_regex_c, errbuf, sizeof(errbuf));
+                die("%s", errbuf);
+        }
+}
+
+static const char *rel_type(unsigned type)
+{
+        static const char * const type_name[] = {
+#define REL_TYPE(X)[X] = #X
+                REL_TYPE(R_MIPS_NONE),
+                REL_TYPE(R_MIPS_16),
+                REL_TYPE(R_MIPS_32),
+                REL_TYPE(R_MIPS_REL32),
+                REL_TYPE(R_MIPS_26),
+                REL_TYPE(R_MIPS_HI16),
+                REL_TYPE(R_MIPS_LO16),
+                REL_TYPE(R_MIPS_GPREL16),
+                REL_TYPE(R_MIPS_LITERAL),
+                REL_TYPE(R_MIPS_GOT16),
+                REL_TYPE(R_MIPS_PC16),
+                REL_TYPE(R_MIPS_CALL16),
+                REL_TYPE(R_MIPS_GPREL32),
+                REL_TYPE(R_MIPS_64),
+                REL_TYPE(R_MIPS_HIGHER),
+                REL_TYPE(R_MIPS_HIGHEST),
+                REL_TYPE(R_MIPS_PC21_S2),
+                REL_TYPE(R_MIPS_PC26_S2),
+#undef REL_TYPE
+        };
+        const char *name = "unknown type rel type name";
+
+        if (type < ARRAY_SIZE(type_name) && type_name[type])
+                name = type_name[type];
+        return name;
+}
+
+static const char *sec_name(unsigned shndx)
+{
+        const char *sec_strtab;
+        const char *name;
+
+        sec_strtab = secs[ehdr.e_shstrndx].strtab;
+        if (shndx < ehdr.e_shnum)
+                name = sec_strtab + secs[shndx].shdr.sh_name;
+        else if (shndx == SHN_ABS)
+                name = "ABSOLUTE";
+        else if (shndx == SHN_COMMON)
+                name = "COMMON";
+        else
+                name = "<noname>";
+        return name;
+}
+
+static struct section *sec_lookup(const char *secname)
+{
+        int i;
+
+        for (i = 0; i < ehdr.e_shnum; i++)
+                if (strcmp(secname, sec_name(i)) == 0)
+                        return &secs[i];
+
+        return NULL;
+}
+
+static const char *sym_name(const char *sym_strtab, Elf_Sym *sym)
+{
+        const char *name;
+
+        if (sym->st_name)
+                name = sym_strtab + sym->st_name;
+        else
+                name = sec_name(sym->st_shndx);
+        return name;
+}
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define le16_to_cpu(val) (val)
+#define le32_to_cpu(val) (val)
+#define le64_to_cpu(val) (val)
+#define be16_to_cpu(val) bswap_16(val)
+#define be32_to_cpu(val) bswap_32(val)
+#define be64_to_cpu(val) bswap_64(val)
+
+#define cpu_to_le16(val) (val)
+#define cpu_to_le32(val) (val)
+#define cpu_to_le64(val) (val)
+#define cpu_to_be16(val) bswap_16(val)
+#define cpu_to_be32(val) bswap_32(val)
+#define cpu_to_be64(val) bswap_64(val)
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+#define le16_to_cpu(val) bswap_16(val)
+#define le32_to_cpu(val) bswap_32(val)
+#define le64_to_cpu(val) bswap_64(val)
+#define be16_to_cpu(val) (val)
+#define be32_to_cpu(val) (val)
+#define be64_to_cpu(val) (val)
+
+#define cpu_to_le16(val) bswap_16(val)
+#define cpu_to_le32(val) bswap_32(val)
+#define cpu_to_le64(val) bswap_64(val)
+#define cpu_to_be16(val) (val)
+#define cpu_to_be32(val) (val)
+#define cpu_to_be64(val) (val)
+#endif
+
+static uint16_t elf16_to_cpu(uint16_t val)
+{
+        if (ehdr.e_ident[EI_DATA] == ELFDATA2LSB)
+                return le16_to_cpu(val);
+        else
+                return be16_to_cpu(val);
+}
+
+static uint32_t elf32_to_cpu(uint32_t val)
+{
+        if (ehdr.e_ident[EI_DATA] == ELFDATA2LSB)
+                return le32_to_cpu(val);
+        else
+                return be32_to_cpu(val);
+}
+
+static uint32_t cpu_to_elf32(uint32_t val)
+{
+        if (ehdr.e_ident[EI_DATA] == ELFDATA2LSB)
+                return cpu_to_le32(val);
+        else
+                return cpu_to_be32(val);
+}
+
+#define elf_half_to_cpu(x)      elf16_to_cpu(x)
+#define elf_word_to_cpu(x)      elf32_to_cpu(x)
+
+#if ELF_BITS == 64
+static uint64_t elf64_to_cpu(uint64_t val)
+{
+        if (ehdr.e_ident[EI_DATA] == ELFDATA2LSB)
+                return le64_to_cpu(val);
+        else
+                return be64_to_cpu(val);
+}
+#define elf_addr_to_cpu(x)      elf64_to_cpu(x)
+#define elf_off_to_cpu(x)       elf64_to_cpu(x)
+#define elf_xword_to_cpu(x)     elf64_to_cpu(x)
+#else
+#define elf_addr_to_cpu(x)      elf32_to_cpu(x)
+#define elf_off_to_cpu(x)       elf32_to_cpu(x)
+#define elf_xword_to_cpu(x)     elf32_to_cpu(x)
+#endif
+
+static void read_ehdr(FILE *fp)
+{
+        if (fread(&ehdr, sizeof(ehdr), 1, fp) != 1)
+                die("Cannot read ELF header: %s\n", strerror(errno));
+
+        if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG) != 0)
+                die("No ELF magic\n");
+
+        if (ehdr.e_ident[EI_CLASS] != ELF_CLASS)
+                die("Not a %d bit executable\n", ELF_BITS);
+
+        if ((ehdr.e_ident[EI_DATA] != ELFDATA2LSB) &&
+            (ehdr.e_ident[EI_DATA] != ELFDATA2MSB))
+                die("Unknown ELF Endianness\n");
+
+        if (ehdr.e_ident[EI_VERSION] != EV_CURRENT)
+                die("Unknown ELF version\n");
+
+        /* Convert the fields to native endian */
+        ehdr.e_type      = elf_half_to_cpu(ehdr.e_type);
+        ehdr.e_machine   = elf_half_to_cpu(ehdr.e_machine);
+        ehdr.e_version   = elf_word_to_cpu(ehdr.e_version);
+        ehdr.e_entry     = elf_addr_to_cpu(ehdr.e_entry);
+        ehdr.e_phoff     = elf_off_to_cpu(ehdr.e_phoff);
+        ehdr.e_shoff     = elf_off_to_cpu(ehdr.e_shoff);
+        ehdr.e_flags     = elf_word_to_cpu(ehdr.e_flags);
+        ehdr.e_ehsize    = elf_half_to_cpu(ehdr.e_ehsize);
+        ehdr.e_phentsize = elf_half_to_cpu(ehdr.e_phentsize);
+        ehdr.e_phnum     = elf_half_to_cpu(ehdr.e_phnum);
+        ehdr.e_shentsize = elf_half_to_cpu(ehdr.e_shentsize);
+        ehdr.e_shnum     = elf_half_to_cpu(ehdr.e_shnum);
+        ehdr.e_shstrndx  = elf_half_to_cpu(ehdr.e_shstrndx);
+
+        if ((ehdr.e_type != ET_EXEC) && (ehdr.e_type != ET_DYN))
+                die("Unsupported ELF header type\n");
+
+        if (ehdr.e_machine != ELF_MACHINE)
+                die("Not for %s\n", ELF_MACHINE_NAME);
+
+        if (ehdr.e_version != EV_CURRENT)
+                die("Unknown ELF version\n");
+
+        if (ehdr.e_ehsize != sizeof(Elf_Ehdr))
+                die("Bad Elf header size\n");
+
+        if (ehdr.e_phentsize != sizeof(Elf_Phdr))
+                die("Bad program header entry\n");
+
+        if (ehdr.e_shentsize != sizeof(Elf_Shdr))
+                die("Bad section header entry\n");
+
+        if (ehdr.e_shstrndx >= ehdr.e_shnum)
+                die("String table index out of bounds\n");
+}
+
+static void read_shdrs(FILE *fp)
+{
+        int i;
+        Elf_Shdr shdr;
+
+        secs = calloc(ehdr.e_shnum, sizeof(struct section));
+        if (!secs)
+                die("Unable to allocate %d section headers\n", ehdr.e_shnum);
+
+        if (fseek(fp, ehdr.e_shoff, SEEK_SET) < 0)
+                die("Seek to %d failed: %s\n", ehdr.e_shoff, strerror(errno));
+
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+
+                sec->shdr_offset = ftell(fp);
+                if (fread(&shdr, sizeof(shdr), 1, fp) != 1)
+                        die("Cannot read ELF section headers %d/%d: %s\n",
+                            i, ehdr.e_shnum, strerror(errno));
+                sec->shdr.sh_name      = elf_word_to_cpu(shdr.sh_name);
+                sec->shdr.sh_type      = elf_word_to_cpu(shdr.sh_type);
+                sec->shdr.sh_flags     = elf_xword_to_cpu(shdr.sh_flags);
+                sec->shdr.sh_addr      = elf_addr_to_cpu(shdr.sh_addr);
+                sec->shdr.sh_offset    = elf_off_to_cpu(shdr.sh_offset);
+                sec->shdr.sh_size      = elf_xword_to_cpu(shdr.sh_size);
+                sec->shdr.sh_link      = elf_word_to_cpu(shdr.sh_link);
+                sec->shdr.sh_info      = elf_word_to_cpu(shdr.sh_info);
+                sec->shdr.sh_addralign = elf_xword_to_cpu(shdr.sh_addralign);
+                sec->shdr.sh_entsize   = elf_xword_to_cpu(shdr.sh_entsize);
+                if (sec->shdr.sh_link < ehdr.e_shnum)
+                        sec->link = &secs[sec->shdr.sh_link];
+        }
+}
+
+static void read_strtabs(FILE *fp)
+{
+        int i;
+
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+
+                if (sec->shdr.sh_type != SHT_STRTAB)
+                        continue;
+
+                sec->strtab = malloc(sec->shdr.sh_size);
+                if (!sec->strtab)
+                        die("malloc of %d bytes for strtab failed\n",
+                            sec->shdr.sh_size);
+
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0)
+                        die("Seek to %d failed: %s\n",
+                            sec->shdr.sh_offset, strerror(errno));
+
+                if (fread(sec->strtab, 1, sec->shdr.sh_size, fp) !=
+                    sec->shdr.sh_size)
+                        die("Cannot read symbol table: %s\n", strerror(errno));
+        }
+}
+
+static void read_symtabs(FILE *fp)
+{
+        int i, j;
+
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                if (sec->shdr.sh_type != SHT_SYMTAB)
+                        continue;
+
+                sec->symtab = malloc(sec->shdr.sh_size);
+                if (!sec->symtab)
+                        die("malloc of %d bytes for symtab failed\n",
+                            sec->shdr.sh_size);
+
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0)
+                        die("Seek to %d failed: %s\n",
+                            sec->shdr.sh_offset, strerror(errno));
+
+                if (fread(sec->symtab, 1, sec->shdr.sh_size, fp) !=
+                    sec->shdr.sh_size)
+                        die("Cannot read symbol table: %s\n", strerror(errno));
+
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Sym); j++) {
+                        Elf_Sym *sym = &sec->symtab[j];
+
+                        sym->st_name  = elf_word_to_cpu(sym->st_name);
+                        sym->st_value = elf_addr_to_cpu(sym->st_value);
+                        sym->st_size  = elf_xword_to_cpu(sym->st_size);
+                        sym->st_shndx = elf_half_to_cpu(sym->st_shndx);
+                }
+        }
+}
+
+static void read_relocs(FILE *fp)
+{
+        static unsigned long base = 0;
+        int i, j;
+
+        if (!base) {
+                struct section *sec = sec_lookup(".text");
+
+                if (!sec)
+                        die("Could not find .text section\n");
+
+                base = sec->shdr.sh_addr;
+        }
+
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+
+                if (sec->shdr.sh_type != SHT_REL_TYPE)
+                        continue;
+
+                sec->reltab = malloc(sec->shdr.sh_size);
+                if (!sec->reltab)
+                        die("malloc of %d bytes for relocs failed\n",
+                            sec->shdr.sh_size);
+
+                if (fseek(fp, sec->shdr.sh_offset, SEEK_SET) < 0)
+                        die("Seek to %d failed: %s\n",
+                            sec->shdr.sh_offset, strerror(errno));
+
+                if (fread(sec->reltab, 1, sec->shdr.sh_size, fp) !=
+                    sec->shdr.sh_size)
+                        die("Cannot read symbol table: %s\n", strerror(errno));
+
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {
+                        Elf_Rel *rel = &sec->reltab[j];
+
+                        rel->r_offset = elf_addr_to_cpu(rel->r_offset);
+                        /* Set offset into kernel image */
+                        rel->r_offset -= base;
+#if (ELF_BITS == 32)
+                        rel->r_info   = elf_xword_to_cpu(rel->r_info);
+#else
+                        /* Convert MIPS64 RELA format - only the symbol
+                         * index needs converting to native endianness
+                         */
+                        rel->r_info   = rel->r_info;
+                        ELF_R_SYM(rel->r_info) = elf32_to_cpu(ELF_R_SYM(rel->r_info));
+#endif
+#if (SHT_REL_TYPE == SHT_RELA)
+                        rel->r_addend = elf_xword_to_cpu(rel->r_addend);
+#endif
+                }
+        }
+}
+
+static void remove_relocs(FILE *fp)
+{
+        int i;
+        Elf_Shdr shdr;
+
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+
+                if (sec->shdr.sh_type != SHT_REL_TYPE)
+                        continue;
+
+                if (fseek(fp, sec->shdr_offset, SEEK_SET) < 0)
+                        die("Seek to %d failed: %s\n",
+                            sec->shdr_offset, strerror(errno));
+
+                if (fread(&shdr, sizeof(shdr), 1, fp) != 1)
+                        die("Cannot read ELF section headers %d/%d: %s\n",
+                            i, ehdr.e_shnum, strerror(errno));
+
+                /* Set relocation section size to 0, effectively removing it.
+                 * This is necessary due to lack of support for relocations
+                 * in objcopy when creating 32bit elf from 64bit elf.
+                 */
+                shdr.sh_size = 0;
+
+                if (fseek(fp, sec->shdr_offset, SEEK_SET) < 0)
+                        die("Seek to %d failed: %s\n",
+                            sec->shdr_offset, strerror(errno));
+
+                if (fwrite(&shdr, sizeof(shdr), 1, fp) != 1)
+                        die("Cannot write ELF section headers %d/%d: %s\n",
+                            i, ehdr.e_shnum, strerror(errno));
+        }
+}
+
+static void add_reloc(struct relocs *r, uint32_t offset, unsigned type)
+{
+        /* Relocation representation in binary table:
+         * |76543210|76543210|76543210|76543210|
+         * |  Type  |  offset from _text >> 2  |
+         */
+        offset >>= 2;
+        if (offset > 0x00FFFFFF)
+                die("Kernel image exceeds maximum size for relocation!\n");
+
+        offset = (offset & 0x00FFFFFF) | ((type & 0xFF) << 24);
+
+        if (r->count == r->size) {
+                unsigned long newsize = r->size + 50000;
+                void *mem = realloc(r->offset, newsize * sizeof(r->offset[0]));
+
+                if (!mem)
+                        die("realloc failed\n");
+
+                r->offset = mem;
+                r->size = newsize;
+        }
+        r->offset[r->count++] = offset;
+}
+
+static void walk_relocs(int (*process)(struct section *sec, Elf_Rel *rel,
+                        Elf_Sym *sym, const char *symname))
+{
+        int i;
+
+        /* Walk through the relocations */
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                char *sym_strtab;
+                Elf_Sym *sh_symtab;
+                struct section *sec_applies, *sec_symtab;
+                int j;
+                struct section *sec = &secs[i];
+
+                if (sec->shdr.sh_type != SHT_REL_TYPE)
+                        continue;
+
+                sec_symtab  = sec->link;
+                sec_applies = &secs[sec->shdr.sh_info];
+                if (!(sec_applies->shdr.sh_flags & SHF_ALLOC))
+                        continue;
+
+                sh_symtab = sec_symtab->symtab;
+                sym_strtab = sec_symtab->link->strtab;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {
+                        Elf_Rel *rel = &sec->reltab[j];
+                        Elf_Sym *sym = &sh_symtab[ELF_R_SYM(rel->r_info)];
+                        const char *symname = sym_name(sym_strtab, sym);
+
+                        process(sec, rel, sym, symname);
+                }
+        }
+}
+
+static int do_reloc(struct section *sec, Elf_Rel *rel, Elf_Sym *sym,
+                      const char *symname)
+{
+        unsigned r_type = ELF_R_TYPE(rel->r_info);
+        unsigned bind = ELF_ST_BIND(sym->st_info);
+
+        if ((bind == STB_WEAK) && (sym->st_value == 0)) {
+                /* Don't relocate weak symbols without a target */
+                return 0;
+        }
+
+        if (regex_skip_reloc(symname))
+                return 0;
+
+        switch (r_type) {
+        case R_MIPS_NONE:
+        case R_MIPS_REL32:
+        case R_MIPS_PC16:
+        case R_MIPS_PC21_S2:
+        case R_MIPS_PC26_S2:
+                /*
+                 * NONE can be ignored and PC relative relocations don't
+                 * need to be adjusted.
+                 */
+        case R_MIPS_HIGHEST:
+        case R_MIPS_HIGHER:
+                /* We support relocating within the same 4Gb segment only,
+                 * thus leaving the top 32bits unchanged
+                 */
+        case R_MIPS_LO16:
+                /* We support relocating by 64k jumps only
+                 * thus leaving the bottom 16bits unchanged
+                 */
+                break;
+
+        case R_MIPS_64:
+        case R_MIPS_32:
+        case R_MIPS_26:
+        case R_MIPS_HI16:
+                add_reloc(&relocs, rel->r_offset, r_type);
+                break;
+
+        default:
+                die("Unsupported relocation type: %s (%d)\n",
+                    rel_type(r_type), r_type);
+                break;
+        }
+
+        return 0;
+}
+
+static int write_reloc_as_bin(uint32_t v, FILE *f)
+{
+        unsigned char buf[4];
+
+        v = cpu_to_elf32(v);
+
+        memcpy(buf, &v, sizeof(uint32_t));
+        return fwrite(buf, 1, 4, f);
+}
+
+static int write_reloc_as_text(uint32_t v, FILE *f)
+{
+        int res;
+
+        res = fprintf(f, "\t.long 0x%08"PRIx32"\n", v);
+        if (res < 0)
+                return res;
+        else
+                return sizeof(uint32_t);
+}
+
+static void emit_relocs(int as_text, int as_bin, FILE *outf)
+{
+        int i;
+        int (*write_reloc)(uint32_t, FILE *) = write_reloc_as_bin;
+        int size = 0;
+        int size_reserved;
+        struct section *sec_reloc;
+
+        sec_reloc = sec_lookup(".data.reloc");
+        if (!sec_reloc)
+                die("Could not find relocation section\n");
+
+        size_reserved = sec_reloc->shdr.sh_size;
+
+        /* Collect up the relocations */
+        walk_relocs(do_reloc);
+
+        /* Print the relocations */
+        if (as_text) {
+                /* Print the relocations in a form suitable that
+                 * gas will like.
+                 */
+                printf(".section \".data.reloc\",\"a\"\n");
+                printf(".balign 4\n");
+                /* Output text to stdout */
+                write_reloc = write_reloc_as_text;
+                outf = stdout;
+        } else if (as_bin) {
+                /* Output raw binary to stdout */
+                outf = stdout;
+        } else {
+                /* Seek to offset of the relocation section.
+                * Each relocation is then written into the
+                * vmlinux kernel image.
+                */
+                if (fseek(outf, sec_reloc->shdr.sh_offset, SEEK_SET) < 0) {
+                        die("Seek to %d failed: %s\n",
+                                sec_reloc->shdr.sh_offset, strerror(errno));
+                }
+        }
+
+        for (i = 0; i < relocs.count; i++)
+                size += write_reloc(relocs.offset[i], outf);
+
+        /* Print a stop, but only if we've actually written some relocs */
+        if (size)
+                size += write_reloc(0, outf);
+
+        if (size > size_reserved)
+                /* Die, but suggest a value for CONFIG_RELOCATION_TABLE_SIZE
+                 * which will fix this problem and allow a bit of headroom
+                 * if more kernel features are enabled
+                 */
+                die("Relocations overflow available space!\n" \
+                    "Please adjust CONFIG_RELOCATION_TABLE_SIZE " \
+                    "to at least 0x%08x\n", (size + 0x1000) & ~0xFFF);
+}
+
+/*
+ * As an aid to debugging problems with different linkers
+ * print summary information about the relocs.
+ * Since different linkers tend to emit the sections in
+ * different orders we use the section names in the output.
+ */
+static int do_reloc_info(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
+                                const char *symname)
+{
+        printf("%16s  0x%08x  %16s  %40s  %16s\n",
+                sec_name(sec->shdr.sh_info),
+                (unsigned int)rel->r_offset,
+                rel_type(ELF_R_TYPE(rel->r_info)),
+                symname,
+                sec_name(sym->st_shndx));
+        return 0;
+}
+
+static void print_reloc_info(void)
+{
+        printf("%16s  %10s  %16s  %40s  %16s\n",
+                "reloc section",
+                "offset",
+                "reloc type",
+                "symbol",
+                "symbol section");
+        walk_relocs(do_reloc_info);
+}
+
+#if ELF_BITS == 64
+# define process process_64
+#else
+# define process process_32
+#endif
+
+void process(FILE *fp, int as_text, int as_bin,
+             int show_reloc_info, int keep_relocs)
+{
+        regex_init();
+        read_ehdr(fp);
+        read_shdrs(fp);
+        read_strtabs(fp);
+        read_symtabs(fp);
+        read_relocs(fp);
+        if (show_reloc_info) {
+                print_reloc_info();
+                return;
+        }
+        emit_relocs(as_text, as_bin, fp);
+        if (!keep_relocs)
+                remove_relocs(fp);
+}
diff --git a/arch/mips/boot/tools/relocs.h b/arch/mips/boot/tools/relocs.h
new file mode 100644
index 000000000..607ff0103
--- /dev/null
+++ b/arch/mips/boot/tools/relocs.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef RELOCS_H
+#define RELOCS_H
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+#include <elf.h>
+#include <byteswap.h>
+#define USE_BSD
+#include <endian.h>
+#include <regex.h>
+
+void die(char *fmt, ...);
+
+/*
+ * Introduced for MIPSr6
+ */
+#ifndef R_MIPS_PC21_S2
+#define R_MIPS_PC21_S2          60
+#endif
+
+#ifndef R_MIPS_PC26_S2
+#define R_MIPS_PC26_S2          61
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+enum symtype {
+        S_ABS,
+        S_REL,
+        S_SEG,
+        S_LIN,
+        S_NSYMTYPES
+};
+
+void process_32(FILE *fp, int as_text, int as_bin,
+                int show_reloc_info, int keep_relocs);
+void process_64(FILE *fp, int as_text, int as_bin,
+                int show_reloc_info, int keep_relocs);
+#endif /* RELOCS_H */
diff --git a/arch/mips/boot/tools/relocs_32.c b/arch/mips/boot/tools/relocs_32.c
new file mode 100644
index 000000000..428bea489
--- /dev/null
+++ b/arch/mips/boot/tools/relocs_32.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "relocs.h"
+
+#define ELF_BITS 32
+
+#define ELF_MACHINE             EM_MIPS
+#define ELF_MACHINE_NAME        "MIPS"
+#define SHT_REL_TYPE            SHT_REL
+#define Elf_Rel                 ElfW(Rel)
+
+#define ELF_CLASS               ELFCLASS32
+#define ELF_R_SYM(val)          ELF32_R_SYM(val)
+#define ELF_R_TYPE(val)         ELF32_R_TYPE(val)
+#define ELF_ST_TYPE(o)          ELF32_ST_TYPE(o)
+#define ELF_ST_BIND(o)          ELF32_ST_BIND(o)
+#define ELF_ST_VISIBILITY(o)    ELF32_ST_VISIBILITY(o)
+
+#include "relocs.c"
diff --git a/arch/mips/boot/tools/relocs_64.c b/arch/mips/boot/tools/relocs_64.c
new file mode 100644
index 000000000..154015d74
--- /dev/null
+++ b/arch/mips/boot/tools/relocs_64.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "relocs.h"
+
+#define ELF_BITS 64
+
+#define ELF_MACHINE             EM_MIPS
+#define ELF_MACHINE_NAME        "MIPS64"
+#define SHT_REL_TYPE            SHT_RELA
+#define Elf_Rel                 Elf64_Rela
+
+typedef uint8_t Elf64_Byte;
+
+typedef union {
+        struct {
+                Elf64_Word r_sym;       /* Symbol index.  */
+                Elf64_Byte r_ssym;      /* Special symbol.  */
+                Elf64_Byte r_type3;     /* Third relocation.  */
+                Elf64_Byte r_type2;     /* Second relocation.  */
+                Elf64_Byte r_type;      /* First relocation.  */
+        } fields;
+        Elf64_Xword unused;
+} Elf64_Mips_Rela;
+
+#define ELF_CLASS               ELFCLASS64
+#define ELF_R_SYM(val)          (((Elf64_Mips_Rela *)(&val))->fields.r_sym)
+#define ELF_R_TYPE(val)         (((Elf64_Mips_Rela *)(&val))->fields.r_type)
+#define ELF_ST_TYPE(o)          ELF64_ST_TYPE(o)
+#define ELF_ST_BIND(o)          ELF64_ST_BIND(o)
+#define ELF_ST_VISIBILITY(o)    ELF64_ST_VISIBILITY(o)
+
+#include "relocs.c"
diff --git a/arch/mips/boot/tools/relocs_main.c b/arch/mips/boot/tools/relocs_main.c
new file mode 100644
index 000000000..e2453a564
--- /dev/null
+++ b/arch/mips/boot/tools/relocs_main.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <endian.h>
+#include <elf.h>
+
+#include "relocs.h"
+
+void die(char *fmt, ...)
+{
+        va_list ap;
+
+        va_start(ap, fmt);
+        vfprintf(stderr, fmt, ap);
+        va_end(ap);
+        exit(1);
+}
+
+static void usage(void)
+{
+        die("relocs [--reloc-info|--text|--bin|--keep] vmlinux\n");
+}
+
+int main(int argc, char **argv)
+{
+        int show_reloc_info, as_text, as_bin, keep_relocs;
+        const char *fname;
+        FILE *fp;
+        int i;
+        unsigned char e_ident[EI_NIDENT];
+
+        show_reloc_info = 0;
+        as_text = 0;
+        as_bin = 0;
+        keep_relocs = 0;
+        fname = NULL;
+        for (i = 1; i < argc; i++) {
+                char *arg = argv[i];
+
+                if (*arg == '-') {
+                        if (strcmp(arg, "--reloc-info") == 0) {
+                                show_reloc_info = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--text") == 0) {
+                                as_text = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--bin") == 0) {
+                                as_bin = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--keep") == 0) {
+                                keep_relocs = 1;
+                                continue;
+                        }
+                } else if (!fname) {
+                        fname = arg;
+                        continue;
+                }
+                usage();
+        }
+        if (!fname)
+                usage();
+
+        fp = fopen(fname, "r+");
+        if (!fp)
+                die("Cannot open %s: %s\n", fname, strerror(errno));
+
+        if (fread(&e_ident, 1, EI_NIDENT, fp) != EI_NIDENT)
+                die("Cannot read %s: %s", fname, strerror(errno));
+
+        rewind(fp);
+        if (e_ident[EI_CLASS] == ELFCLASS64)
+                process_64(fp, as_text,  as_bin, show_reloc_info, keep_relocs);
+        else
+                process_32(fp, as_text, as_bin, show_reloc_info, keep_relocs);
+        fclose(fp);
+        return 0;
+}